DS90LV804 [TI]
4 通道 800Mbps LVDS 缓冲器/中继器;
| 型号： | DS90LV804 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 4 通道 800Mbps LVDS 缓冲器/中继器 中继器 |
| 文件： | 总17页 (文件大小：444K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS90LV804
www.ti.com
SNLS195L –SEPTEMBER 2005–REVISED APRIL 2013
DS90LV804 4-Channel 800 Mbps LVDS Buffer/Repeater
Check for Samples: DS90LV804
In order to maximize signal integrity, the DS90LV804
1
FEATURES
features both an internal input and output (source)
termination to eliminate these extra components from
the board, and to also place the terminations as close
as possible to receiver inputs and driver output. This
is especially significant when driving longer cables.
23
•
800 Mbps Data Rate per Channel
Low Output Skew and Jitter
•
•
LVDS/CML/LVPECL Compatible Input, LVDS
Output
The DS90LV804, available in the WQFN (Leadless
Leadframe Package) package, minimizes the
footprint, and improves system performance.
•
•
•
•
•
•
On-Chip 100Ω Input and Output Termination
12 kV ESD Protection on LVDS Outputs
Single 3.3V Supply
An output enable pin is provided, which allows the
user to place the LVDS outputs and internal biasing
generators in a TRI-STATE®, low power mode.
Very Low Power Consumption
Industrial -40 to +85°C Temperature Range
Small WQFN Package Footprint
The differential inputs interface to LVDS, and Bus
LVDS signals such as those on TI's 10-, 16-, and 18-
bit Bus LVDS SerDes, as well as CML and LVPECL.
The differential inputs are internally terminated with a
100Ω resistor to improve performance and minimize
board space. This function is especially useful for
boosting signals over lossy cables or point-to-point
backplane configurations.
DESCRIPTION
The DS90LV804 is a four channel 800 Mbps LVDS
buffer/repeater. In many large systems, signals are
distributed across cables and signal integrity is highly
dependent on the data rate, cable type, length, and
the termination scheme.
Block and Connection Diagrams
EN
OUT0+
OUT0-
IN0+
IN0-
OUT1+
OUT1-
IN1+
IN1-
OUT2+
OUT2-
IN2+
IN2-
OUT3+
OUT3-
IN3+
IN3-
Figure 1. DS90LV804 Block Diagram
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TRI-STATE is a registered trademark of National Semiconductor Corporation.
2
3
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2013, Texas Instruments Incorporated
DS90LV804
SNLS195L –SEPTEMBER 2005–REVISED APRIL 2013
www.ti.com
8
7
6
5
4
3
2
1
OUT0+
OUT0-
OUT1+
OUT1-
OUT2+
OUT2-
OUT3+
OUT3-
IN0+
IN0-
IN1+
IN1-
IN2+
IN2-
IN3+
IN3-
32
31
30
29
28
27
26
25
9
10
11
12
13
14
15
16
DAP
(GND)
17 18 19 20 21 22 23 24
DS90LV804 WQFN Pinout
(Top View)
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)
Supply Voltage (VDD
)
−0.3V to +4.0V
−0.3V to (VDD+0.3V)
−0.3V to (VDD+0.3V)
−0.3V to (VDD+0.3V)
+90 mA
CMOS Input Voltage (EN)
LVDS Input Voltage(2)
LVDS Output Voltage
LVDS Output Short Circuit Current
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
260°C
Lead Temperature (Solder, 4sec)
Max Pkg Power Capacity @ 25°C
4.16W
θJA
θJC
29.5°C/W
Thermal Resistance
3.5°C/W
Package Derating above +25°C
33.3mW/°C
12 kV
HBM, 1.5kΩ, 100pF
EIAJ, 0Ω, 200pF
ESD Last Passing Voltage (LVDS output pins)
ESD Last Passing Voltage (All other pins)
250V
Charged Device Model
HBM, 1.5kΩ, 100pF
EIAJ, 0Ω, 200pF
1000V
8 kV
250V
Charged Device Model
1000V
(1) Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met,
without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. TI
does not recommend operation of products outside of recommended operation conditions.
(2) VID max < 2.4V
2
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SNLS195L –SEPTEMBER 2005–REVISED APRIL 2013
Recommended Operating Conditions
Supply Voltage (VCC
Input Voltage (VI)(1)
Output Voltage (VO)
)
3.15V to 3.45V
0V to VDD
0V to VDD
Operating Temperature (TA)
(1) VID max < 2.4V
Industrial
−40°C to +85°C
Electrical Characteristics
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
Typ(1)
Max
Units
LVTTL DC SPECIFICATIONS (EN)
VIH
VIL
IIH
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
2.0
GND
−10
−10
VDD
0.8
V
V
VIN = VDD = VDDMAX
+10
+10
µA
µA
pF
V
IIL
VIN = VSS, VDD = VDDMAX
Any Digital Input Pin to VSS
ICL = −18 mA
CIN1
VCL
3.5
Input Clamp Voltage
−1.5
−0.8
LVDS INPUT DC SPECIFICATIONS (INn±)
VTH
VCM = 0.8V to 3.4V,
VDD = 3.45V
Differential Input High Threshold(2)
0
0
100
mV
mV
VTL
VCM = 0.8V to 3.4V,
VDD = 3.45V
Differential Input Low Threshold(2)
−100
VID
Differential Input Voltage
Common Mode Voltage Range
Input Capacitance
VCM = 0.8V to 3.4V, VDD = 3.45V
VID = 150 mV, VDD = 3.45V
IN+ or IN− to VSS
100
2400
3.40
mV
V
VCMR
CIN2
IIN
0.05
3.5
pF
µA
µA
VIN = 3.45V, VDD = VDDMAX
VIN = 0V, VDD = VDDMAX
−10
−10
+10
+10
Input Current
LVDS OUTPUT DC SPECIFICATIONS (OUTn±)
VOD
Differential Output Voltage(2)
250
−35
1.05
−35
500
600
35
mV
mV
V
ΔVOD
Change in VOD between
Complementary States
Offset Voltage(3)
RL = 100Ω external resistor between OUT+ and
OUT−
VOS
1.18
1.475
35
ΔVOS
Change in VOS between
Complementary States
mV
IOS
Output Short Circuit Current
Output Capacitance
OUT+ or OUT− Short to GND
−60
−90
mA
pF
COUT2
OUT+ or OUT− to GND when TRI-STATE
5.5
SUPPLY CURRENT (Static)
ICC
All inputs and outputs enabled and active,
terminated with external differential load of 100Ω
between OUT+ and OUT-.
Total Supply Current
117
2.7
140
6
mA
mA
ICCZ
TRI-STATE Supply Current
EN = 0V
(1) Typical parameters are measured at VDD = 3.3V, TA = 25°C. They are for reference purposes, and are not production-tested.
(2) Differential output voltage VOD is defined as ABS(OUT+–OUT−). Differential input voltage VID is defined as ABS(IN+–IN−).
(3) Output offset voltage VOS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states.
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SNLS195L –SEPTEMBER 2005–REVISED APRIL 2013
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Units
Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
Typ(1)
Max
SWITCHING CHARACTERISTICS—LVDS OUTPUTS
tLHT
Differential Low to High Transition
Time
210
210
2.0
300
300
3.2
ps
ps
ns
Use an alternating 1 and 0 pattern at 200 Mbps,
measure between 20% and 80% of VOD
(4)
tHLT
Differential High to Low Transition
Time
tPLHD
tPHLD
Differential Low to High
Propagation Delay
Use an alternating 1 and 0 pattern at 200 Mbps,
measure at 50% VOD between input to output.
Differential High to Low
Propagation Delay
2.0
25
50
3.2
80
ns
ps
ps
(4)
tSKD1
tSKCC
Pulse Skew
|tPLHD–tPHLD|
Difference in propagation delay (tPLHD or tPHLD
)
Output Channel to Channel Skew
Part to Part Skew
125
among all output channels(4)
(4)
tSKP
tJIT
Common edge, parts at same temp and VCC
RJ - Alternating 1 and 0 at 400 MHz(6)
DJ - K28.5 Pattern, 800 Mbps(7)
1.1
1.5
35
ns
1.1
15
30
psrms
psp-p
psp-p
Jitter(5)
TJ - PRBS 223-1 Pattern, 800 Mbps(8)
55
tON
Time from EN to OUT± change from TRI-STATE to
active.
LVDS Output Enable Time
LVDS Output Disable Time
300
12
ns
ns
tOFF
Time from EN to OUT± change from active to TRI-
STATE.
(4) Not production tested. Ensured by statistical analysis on a sample basis at the time of characterization.
(5) Jitter is not production tested, but ensured through characterization on a sample basis.
(6) Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. The input voltage = VID = 500mV, 50%
duty cycle at 400 MHz, tr = tf = 50ps (20% to 80%).
(7) Deterministic Jitter, or DJ, is measured to a histogram mean with a sample size of 350 hits. The input voltage = VID = 500mV, K28.5
pattern at 800 Mbps, tr = tf = 50ps (20% to 80%). The K28.5 pattern is repeating bit streams of (0011111010 1100000101).
(8) Total Jitter, or TJ, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture Jitter has been
subtracted. The input voltage = VID = 500mV, 223-1 PRBS pattern at 800 Mbps, tr = tf = 50ps (20% to 80%).
Typical Application
DS90LV804
Cable or Backplane
4
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SNLS195L –SEPTEMBER 2005–REVISED APRIL 2013
APPLICATION INFORMATION
INTERNAL TERMINATIONS
The DS90LV804 has integrated termination resistors on both the input and outputs. The inputs have a 100Ω
resistor across the differential pair, placing the receiver termination as close as possible to the input stage of the
device. The LVDS outputs also contain an integrated 100Ω ohm termination resistor, this resistor is used to
reduce the effects of Near End Crosstalk (NEXT) and does not take the place of the 100 ohm termination at the
inputs to the receiving device. The integrated terminations improve signal integrity and decrease the external
component count resulting in space savings.
OUTPUT CHARACTERISTICS
The output characteristics of the DS90LV804 have been optimized for point-to-point backplane and cable
applications, and are not intended for multipoint or multidrop signaling.
TRI-STATE MODE
The EN input activates a hardware TRI-STATE mode. When the TRI-STATE mode is active (EN=L), all input and
output buffers and internal bias circuitry are powered off and disabled. Outputs are tri-stated in TRI-STATE
mode. When exiting TRI-STATE mode, there is a delay associated with turning on bandgap references and
input/output buffer circuits as indicated in the LVDS Output Switching Characteristics
INPUT FAILSAFE BIASING
External pull up and pull down resistors may be used to provide enough of an offset to enable an input failsafe
under open-circuit conditions. This configuration ties the positive LVDS input pin to VDD thru a pull up resistor and
the negative LVDS input pin is tied to GND by a pull down resistor. The pull up and pull down resistors should be
in the 5kΩ to 15kΩ range to minimize loading and waveform distortion to the driver. The common-mode bias
point ideally should be set to approximately 1.2V (less than 1.75V) to be compatible with the internal circuitry.
Please refer to application note AN-1194 “Failsafe Biasing of LVDS Interfaces” for more information.
INPUT INTERFACING
The DS90LV804 accepts differential signals and allow simple AC or DC coupling. With a wide common mode
range, the DS90LV804 can be DC-coupled with all common differential drivers (that is, LVPECL, LVDS, CML).
Figure 2, Figure 3, and Figure 4 illustrate typical DC-coupled interface to common differential drivers. Note that
the DS90LV804 inputs are internally terminated with a 100Ω resistor.
LVDS
Driver
DS90LV804
Receiver
100W Differential T-Line
OUT+
IN+
100W
IN-
OUT-
Figure 2. Typical LVDS Driver DC-Coupled Interface to DS90LV804 Input
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DS90LV804
SNLS195L –SEPTEMBER 2005–REVISED APRIL 2013
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CML3.3V or CML2.5V
Driver
V
CC
DS90LV804
Receiver
50W
50W
100W Differential T-Line
OUT+
OUT-
IN+
IN-
100W
Figure 3. Typical CML Driver DC-Coupled Interface to DS90LV804 Input
LVPECL
Driver
LVDS
Receiver
100W Differential T-Line
IN+
IN-
OUT+
100W
OUT-
150-250W
150-250W
Figure 4. Typical LVPECL Driver DC-Coupled Interface to DS90LV804 Input
OUTPUT INTERFACING
The DS90LV804 outputs signals that are compliant to the LVDS standard. Their outputs can be DC-coupled to
most common differential receivers. Figure 5 illustrates typical DC-coupled interface to common differential
receivers and assumes that the receivers have high impedance inputs. While most differential receivers have a
common mode input range that can accommodate LVDS compliant signals, it is recommended to check
respective receiver's data sheet prior to implementing the suggested interface implementation.
DS90LV804
Driver
Differential
Receiver
100W Differential T-Line
OUT+
IN+
CML or
LVPECL or
LVDS
100W
100W
IN-
OUT-
Figure 5. Typical DS90LV804 Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver
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SNLS195L –SEPTEMBER 2005–REVISED APRIL 2013
PIN DESCRIPTIONS
Pin
Name
WQFN Pin
Number
I/O, Type
Description
DIFFERENTIAL INPUTS
IN0+
IN0−
9
10
I, LVDS Channel 0 inverting and non-inverting differential inputs.
I, LVDS Channel 1 inverting and non-inverting differential inputs.
I, LVDS Channel 2 inverting and non-inverting differential inputs.
I, LVDS Channel 3 inverting and non-inverting differential inputs.
IN1+
IN1−
11
12
IN2+
IN2−
13
14
IN3+
IN3−
15
16
DIFFERENTIAL OUTPUTS
OUT0+
OUT0−
32
31
O, LVDS Channel 0 inverting and non-inverting differential outputs(1)
O, LVDS Channel 1 inverting and non-inverting differential outputs(1)
O, LVDS Channel 2 inverting and non-inverting differential outputs(1)
O, LVDS Channel 3 inverting and non-inverting differential outputs(1)
OUT1+
OUT1−
30
29
OUT2+
OUT2−
28
27
OUT3+
OUT3-
26
25
DIGITAL CONTROL INTERFACE
EN
8
I, LVTTL Enable pin. When EN is LOW, the driver is disabled and the LVDS outputs are in TRI-
STATE. When EN is HIGH, the driver is enabled. LVCMOS/LVTTL level input.
POWER
VDD
3, 4, 6, 7, 19, 20, 21, 22
1, 2, 5, 17, 18(2)
I, Power VDD = 3.3V, ±5%
GND
I, Power Ground reference for LVDS and CMOS circuitry. For the WQFN package, the DAP is
used as the primary GND connection to the device. The DAP is the exposed metal
contact at the bottom of the WQFN-32 package. It should be connected to the ground
plane with at least 4 vias for optimal AC and thermal performance. The pin numbers
listed should also be tied to ground for proper biasing.
N/C
23, 24
No Connect
(1) The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the DS90LV804 device have
been optimized for point-to-point backplane and cable applications.
(2) Note that for the WQFN package the GND is connected thru the DAP on the back side of the WQFN package in addition to grounding
actual pins on the package as listed.
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Typical Performance Characteristics
350
300
250
200
150
100
50
Clock
PRBS-23
0
0
0.25
0.5
0.75
1.0
BIT DATA RATE (Gbps)
A. Dynamic power supply current was measured while running a clock or PRBS 223-1 pattern with all 4 channels active. VCC = 3.3V, TA
=
+25°C, VID = 0.5V, VCM = 1.2V
Figure 6. Power Supply Current vs Bit Data Rate
PACKAGING INFORMATION
The Leadless Leadframe Package (WQFN) is a leadframe based chip scale package (CSP) that may enhance
chip speed, reduce thermal impedance, and reduce the printed circuit board area required for mounting. The
small size and very low profile make this package ideal for high density PCBs used in small-scale electronic
applications such as cellular phones, pagers, and handheld PDAs. The WQFN package is offered in the no
Pullback configuration. In the no Pullback configuration the standard solder pads extend and terminate at the
edge of the package. This feature offers a visible solder fillet after board mounting.
The WQFN has the following advantages:
•
•
•
•
•
Low thermal resistance
Reduced electrical parasitics
Improved board space efficiency
Reduced package height
Reduced package mass
For more details about WQFN packaging technology, refer to applications note AN-1187, "Leadless Leadframe
Package".
8
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SNLS195L –SEPTEMBER 2005–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision K (April 2013) to Revision L
Page
•
Changed layout of National Data Sheet to TI format ............................................................................................................ 8
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PACKAGE OPTION ADDENDUM
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30-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS90LV804TSQ
NRND
WQFN
RTV
32
1000
Non-RoHS
& Green
Call TI
Level-3-260C-168 HR
-40 to 85
804TSQ
DS90LV804TSQ/NOPB
DS90LV804TSQX/NOPB
ACTIVE
ACTIVE
WQFN
WQFN
RTV
RTV
32
32
1000 RoHS & Green
SN
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
804TSQ
804TSQ
4500 RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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30-Sep-2021
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
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9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS90LV804TSQ
WQFN
WQFN
RTV
RTV
RTV
32
32
32
1000
1000
4500
178.0
178.0
330.0
12.4
12.4
12.4
5.3
5.3
5.3
5.3
5.3
5.3
1.3
1.3
1.3
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
DS90LV804TSQ/NOPB
DS90LV804TSQX/NOPB WQFN
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS90LV804TSQ
WQFN
WQFN
WQFN
RTV
RTV
RTV
32
32
32
1000
1000
4500
208.0
208.0
356.0
191.0
191.0
356.0
35.0
35.0
35.0
DS90LV804TSQ/NOPB
DS90LV804TSQX/NOPB
Pack Materials-Page 2
PACKAGE OUTLINE
RTV0032A
WQFN - 0.8 mm max height
S
C
A
L
E
2
.
5
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.15
4.85
A
B
PIN 1 INDEX AREA
5.15
4.85
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
2X 3.5
SYMM
EXPOSED
THERMAL PAD
(0.1) TYP
9
16
8
17
SYMM
33
2X 3.5
3.1 0.1
28X 0.5
1
24
0.30
32X
0.18
32
25
PIN 1 ID
0.1
C A B
0.5
0.3
32X
0.05
4224386/B 04/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RTV0032A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(3.1)
SYMM
SEE SOLDER MASK
DETAIL
32
25
32X (0.6)
1
24
32X (0.24)
28X (0.5)
(3.1)
33
SYMM
(4.8)
(1.3)
8
17
(R0.05) TYP
(
0.2) TYP
VIA
9
16
(1.3)
(4.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224386/B 04/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RTV0032A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.775) TYP
25
32
32X (0.6)
1
32X (0.24)
28X (0.5)
24
(0.775) TYP
(4.8)
33
SYMM
(R0.05) TYP
4X (1.35)
17
8
9
16
4X (1.35)
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
EXPOSED PAD 33
76% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4224386/B 04/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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