DS90UB903Q-Q1_技术文档

DS90UB903Q, DS90UB904Q

www.ti.com

SNLS332E –JUNE 2010–REVISED APRIL 2013

DS90UB903Q/DS90UB904Q 10 - 43MHz 18 Bit Color FPD-Link III Serializer and

Deserializer with Bidirectional Control Channel

Check for Samples: DS90UB903Q, DS90UB904Q

1

FEATURES

DESCRIPTION

The DS90UB903Q/DS90UB904Q chipset offers a

FPD-Link III interface with a high-speed forward

channel and a bidirectional control channel for data

transmission over a single differential pair. The

2

•

10 MHz to 43 MHz Input PCLK Support

210 Mbps to 903 Mbps Data Throughput

Single Differential Pair Interconnect

•

DS90UB903Q/904Q

incorporates

differential

Bidirectional Control Interface Channel with

I²C Support

signaling on both the high-speed forward channel and

bidirectional control channel data paths. The

Serializer/ Deserializer pair is targeted for direct

connections between graphics host controller and

displays modules. This chipset is ideally suited for

driving video data to displays requiring 18-bit color

depth (RGB666 + HS, VS, and DE) along with

bidirectional control channel bus. The primary

transport converts 21 bit data over a single high-

speed serial stream, along with a separate low

latency bidirectional control channel transport that

accepts control information from an I²C port. Using

TI’s embedded clock technology allows transparent

full-duplex communication over a single differential

pair, carrying asymmetrical bidirectional control

channel information in both directions. This single

serial stream simplifies transferring a wide data bus

over PCB traces and cable by eliminating the skew

problems between parallel data and clock paths. This

significantly saves system cost by narrowing data

paths that in turn reduce PCB layers, cable width,

and connector size and pins.

•

Embedded Clock with DC Balanced Coding to

Support AC-Coupled Interconnects

Capable to Drive up to 10 Meters Shielded

Twisted-Pair

I²C Compatible Serial Interface

•

Single Hardware Device Addressing Pin

Up to 4 General Purpose Input (GPI)/ Output

(GPO)

•

LOCK Output Reporting Pin and AT-SPEED

BIST Diagnosis Feature to Validate Link

Integrity

•

Integrated Termination Resistors

1.8V- or 3.3V-Compatible Parallel Bus Interface

Single Power Supply at 1.8V

ISO 10605 ESD and IEC 61000-4-2 ESD

Compliant

•

Automotive Grade Product: AEC-Q100 Grade 2

Qualified

In addition, the Deserializer inputs provide

equalization control to compensate for loss from the

media over longer distances. Internal DC balanced

encoding/decoding is used to support AC-Coupled

interconnects.

•

Temperature Range −40°C to +105°C

No Reference Clock Required on Deserializer

Programmable Receive Equalization

EMI/EMC Mitigation

The Serializer is offered in a 40-pin lead in WQFN

and Deserializer is offered in a 48-pin WQFN

packages.

–

DES Programmable Spread Spectrum

(SSCG) Outputs

–

DES Receiver Staggered Outputs

APPLICATIONS

•

Automotive Display Systems

–

Central Information Displays

Navigation Displays

Rear Seat Entertainment

Touch Screen Displays

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

DS90UB903Q, DS90UB904Q

SNLS332E –JUNE 2010–REVISED APRIL 2013

www.ti.com

Typical Application Diagram

Parallel

Data Out

18+3

Parallel

Data In

18+3

FPD-Link III

Graphics

Controller

--

Video

Display

Module,

Touch Panel

4

DS90UB903Q

DS90UB904Q

GPO

GPI

2

Bidirectional

Control Channel

2

Processor

Bidirectional

Control Bus

Bidirectional

Control Bus

Serializer

Deserializer

Figure 1. Typical Application Circuit

Block Diagrams

R

T

R

T

R

T

DOUT+

DOUT-

21

T

RIN+

RIN-

R/G/B[5:0],

HS,VS,DE

21

R/G/B[5:0],

HS,VS,DE

4

GPI[3:0]

GPO[3:0]

PCLK

LOCK

PASS

Clock

Gen

PCLK

PLL

Clock

Gen

CDR

Timing

and

Control

PDB

Timing

and

Control

MODE

BISTEN

MODE

SDA

SCL

SDA

SCL

ID[x]

DS90UB903Q - SERIALIZER

DS90UB904Q - DESERIALIZER

Figure 2. Block Diagram

DS90UB903Q

Serializer

DS90UB904Q

Deserializer

FPD-Link III

R[5:0]

G[5:0]

B[5:0]

VS

HS

DE

R[5:0]

G[5:0]

B[5:0]

VS

HS

DE

Timing

Controller

PCLK

Graphics

Controller

---

Video

Processor

LCD

Display

---

PLL

PCLK

PDB

MODE

BISTEN

GPI[3:0]

PDB

MODE

Config.

Touch Panel

Config.

GPO[3:0]

mC

2

SDA

SCL

SDA

SCL

2

I C

mC

I C

Figure 3. Application Block Diagram

2

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SNLS332E –JUNE 2010–REVISED APRIL 2013

DS90UB903Q Pin Diagram

31

32

33

34

35

36

37

38

39

40

20 GPO[1]

19 GPO[0]

V

DDIO

DIN[8]

DIN[9]

DAP = GND

18

V

DDCML

17 DOUT+

16 DOUT-

V

DDD

DS9UB903Q

Serializer

40-Pin WQFN

(Top View)

DIN[10]

DIN[11]

15

14

V

DDT

DIN[12]

DIN[13]

DIN[14]

DIN[15]

DDPLL

13 PDB

12 MODE

11 RES

Serializer - DS90UB903Q

40 Pin WQFN (Top View)

See Package Number RTA0040A

DS90UB903Q SERIALIZER PIN DESCRIPTIONS

Pin Name

Pin No.

I/O, Type

Description

LVCMOS PARALLEL INTERFACE

DIN[20:0]

PCLK

5, 4, 3, 2, 1,

40, 39, 38, 37,

36, 35, 33, 32,

30, 29, 28, 27,

26, 25, 24, 23

Inputs,

LVCMOS

w/ pull down

Parallel data inputs.

6

Input, LVCMOS Pixel Clock Input Pin. Strobe edge set by TRFB control register.

w/ pull down

GENERAL PURPOSE OUTPUT (GPO)

GPO[3:0] 22, 21, 20, 19

Output,

General-purpose output pins can be used to control and respond to various

commands.

LVCMOS

BIDIRECTIONAL CONTROL BUS - I²C COMPATIBLE

Input/Output,

Open Drain

Clock line for the bidirectional control bus communication

SCL

SDA

7

8

SCL requires an external pull-up resistor to V_DDIO

.

Input/Output,

Open Drain

Data line for the bidirectional control bus communication

SDA requires an external pull-up resistor to V_DDIO

I²C Mode select

.

MODE = L, Master mode (default); Device generates and drives the SCL clock line.

Device is connected to slave peripheral on the bus. (Serializer initially starts up in

Standby mode and is enabled through remote wakeup by Deserializer)

MODE = H, Slave mode; Device accepts SCL clock input and attached to an I²C

controller master on the bus. Slave mode does not generate the SCL clock, but uses

the clock generated by the Master for the data transfers.

Input, LVCMOS

w/ pull down

MODE

ID[x]

12

9

Device ID Address Select

Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 3

Input, analog

CONTROL AND CONFIGURATION

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SNLS332E –JUNE 2010–REVISED APRIL 2013

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DS90UB903Q SERIALIZER PIN DESCRIPTIONS (continued)

Pin Name

Pin No.

I/O, Type

Description

Power down Mode Input Pin.

PDB = H, Serializer is enabled and is ON.

PDB = L, Serailizer is in Power Down mode. When the Serializer is in Power Down,

the PLL is shutdown, and IDD is minimized. Programmed control register data are

NOT retained and reset to default values

Input, LVCMOS

w/ pull down

PDB

13

Input, LVCMOS Reserved.

RES

10, 11

w/ pull down

This pin MUST be tied LOW.

FPD-LINK III INTERFACE

Input/Output,

CML

Non-inverting differential output, bidirectional control channel input. The interconnect

must be AC Coupled with a 100 nF capacitor.

DOUT+

DOUT-

17

16

Input/Output,

CML

Inverting differential output, bidirectional control channel input. The interconnect must

be AC Coupled with a 100 nF capacitor.

POWER AND GROUND

VDDPLL

14

15

18

34

Power, Analog PLL Power, 1.8V ±5%

VDDT

Power, Analog Tx Analog Power, 1.8V ±5%

Power, Analog CML & Bidirectional Channel Driver Power, 1.8V ±5%

Power, Digital Digital Power, 1.8V ±5%

VDDCML

VDDD

Power, Digital Power for I/O stage. The single-ended inputs and SDA, SCL are powered from V_DDIO

V_DDIOcan be connected to a 1.8V ±5% or 3.3V ±10%

.

VDDIO

31

Ground, DAP DAP must be grounded. DAP is the large metal contact at the bottom side, located at

the center of the WQFN package. Connected to the ground plane (GND) with at least

16 vias.

VSS

DAP

4

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SNLS332E –JUNE 2010–REVISED APRIL 2013

DS90UB904Q Pin Diagram

PASS

ROUT[4]

ROUT[5]

ROUT[6]

ROUT[7]

37

38

39

40

41

42

43

44

45

46

47

48

24

23

22

21

20

19

18

17

16

15

14

13

RES/CMLOUTP

RES/CMLOUTN

DAP = GND

V

DDCML

RIN+

V

DDIO2

DS90UB904Q

RIN-

RES

ROUT[8]

ROUT[9]

Deserializer

48-Pin WQFN

(Top View)

BISTEN

V

DDD

ROUT[10]

ROUT[11]

ROUT[12]

ROUT[13]

V

DDPLL

RES

MODE

ID[x]

Deserializer - DS90UB904Q

48 Pin WQFN (Top View)

See Package Number RHS0048A

DS90UB904Q DESERIALIZER PIN DESCRIPTIONS

Pin Name

Pin No.

I/O, Type

Description

LVCMOS PARALLEL INTERFACE

ROUT[20:0]

PCLK

5, 6, 8, 9, 10,

11, 12, 13, 14,

15, 16, 18, 19,

21, 22, 23, 24,

25, 26, 27, 28

Outputs,

LVCMOS

Parallel data outputs.

Output,

LVCMOS

Pixel Clock Output Pin.

Strobe edge set by RRFB control register.

4

GENERAL PURPOSE INPUT (GPI)

General-purpose input pins can be used to control and respond to various

commands.

GPI[3:0] 30, 31, 32, 33 Input, LVCMOS

BIDIRECTIONAL CONTROL BUS - I²C COMPATIBLE

Input/Output,

Open Drain

Clock line for the bidirectional control bus communication

SCL

SDA

2

1

SCL requires an external pull-up resistor to V_DDIO

.

Input/Output,

Open Drain

Data line for bidirectional control bus communication

SDA requires an external pull-up resistor to V_DDIO

I²C Mode select

.

MODE = L, Master mode; Device generates and drives the SCL clock line, where

Input, LVCMOS required such as Read. Device is connected to slave peripheral on the bus.

MODE

ID[x]

47

48

w/ pull up

MODE = H, Slave mode (default); Device accepts SCL clock input and attached to an

I²C controller master on the bus. Slave mode does not generate the SCL clock, but

uses the clock generated by the Master for the data transfers.

Device ID Address Select

Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 4.

Input, analog

CONTROL AND CONFIGURATION

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SNLS332E –JUNE 2010–REVISED APRIL 2013

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DS90UB904Q DESERIALIZER PIN DESCRIPTIONS (continued)

Pin Name

Pin No.

I/O, Type

Description

Power down Mode Input Pin.

PDB = H, Deserializer is enabled and is ON.

PDB = L, Deserializer is in Power Down mode. When the Deserializer is in Power

Down. Programmed control register data are NOT retained and reset to default

values.

Input, LVCMOS

w/ pull down

PDB

35

LOCK Status Output Pin.

Output,

LVCMOS

LOCK = H, PLL is Locked, outputs are active

LOCK = L, PLL is unlocked, ROUT and PCLK output states are controlled by

OSS_SEL control register. May be used as Link Status.

LOCK

RES

34

Reserved.

Pins 38, 39: Route to test point or leave open if unused. See also FPD-LINK III

INTERFACE pin description section.

Pin 46: This pin MUST be tied LOW.

Pin 43: Leave pin open.

38, 39, 43, 46

-

BIST MODE

BIST Enable Pin.

BISTEN = H, BIST Mode is enabled.

BISTEN = L, BIST Mode is disabled.

Input, LVCMOS

w/ pull down

BISTEN

44

37

PASS Output Pin for BIST mode.

Output,

PASS = H, ERROR FREE Transmission

PASS

LVCOMS

PASS = L, one or more errors were detected in the received payload.

Leave Open if unused. Route to test point (pad) recommended.

FPD-LINK III INTERFACE

Input/Output,

CML

Non-inverting differential input, bidirectional control channel output. The interconnect

must be AC Coupled with a 100 nF capacitor.

RIN+

RIN-

41

Input/Output,

CML

Inverting differential input, bidirectional control channel output. The interconnect must

be AC Coupled with a 100 nF capacitor.

42

38

Non-inverting CML Output

Monitor point for equalized differential signal. Test port is enabled via control

registers.

CMLOUTP

CMLOUTN

Output, CML

Inverting CML Output

Monitor point for equalized differential signal. Test port is enabled via control

registers.

39

3

POWER AND GROUND

SSCG Power, 1.8V ±5%

Power supply must be connected regardless if SSCG function is in operation.

VDDSSCG

Power, Digital

LVCMOS I/O Buffer Power, The single-ended outputs and control input are powered

from V_DDIO. V_DDIOcan be connected to a 1.8V ±5% or 3.3V ±10%

VDDIO1/2/3

29, 20, 7

VDDD

17

36

40

45

Power, Digital Digital Core Power, 1.8V ±5%

Power, Analog Rx Analog Power, 1.8V ±5%

Power, Analog Bidirectional Channel Driver Power, 1.8V ±5%

Power, Analog PLL Power, 1.8V ±5%

VDDR

VDDCML

VDDPLL

DAP must be grounded. DAP is the large metal contact at the bottom side, located at

VSS

DAP

Ground, DAP the center of the WQFN package. Connected to the ground plane (GND) with at least

16 vias.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

6

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SNLS332E –JUNE 2010–REVISED APRIL 2013

Absolute Maximum Ratings^(1)(2)(3)

Supply Voltage – V_DDn(1.8V)

−0.3V to +2.5V

−0.3V to +4.0V

Supply Voltage – V_DDIO

LVCMOS Input Voltage I/O Voltage

−0.3V to + (VDDIO + 0.3V)

−0.3V to +(V_DD+ 0.3V)

−0.3V to (V_DD+ 0.3V)

+150°C

CML Driver I/O Voltage (V_DD

)

CML Receiver I/O Voltage (V_DD

)

Junction Temperature

Storage Temperature

−65°C to +150°C

Maximum Package Power Dissipation Capacity

Package Derating

1/θ_JA°C/W above +25°

θ_JA(based on 16 thermal vias)

θ_JC(based on 16 thermal vias)

θ_JA(based on 16 thermal vias)

θ_JC(based on 16 thermal vias)

30.7 °C/W

6.8 °C/W

40 Lead WQFN

48 Lead WQFN

26.9 °C/W

4.4 °C/W

ESD Rating (IEC 61000-4-2)

R_D= 330Ω, C_S= 150pF

≥±25 kV

Air Discharge (DOUT+, DOUT-, RIN+, RIN-)

Contact Discharge (DOUT+, DOUT-, RIN+, RIN-)

ESD Rating (ISO10605)

≥±10 kV

R_D= 330Ω, C_S= 150/330pF

R_D= 2KΩ, C_S= 150/330pF

≥±15 kV

ESD Rating (ISO10605)

Air Discharge (DOUT+, DOUT-, RIN+, RIN-)

Contact Discharge (DOUT+, DOUT-, RIN+, RIN-)

ESD Rating (HBM)

≥±10 kV

≥±8 kV

ESD Rating (CDM)

≥±1 kV

ESD Rating (MM)

≥±250 V

(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of

device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or

other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating

Conditions indicate conditions at which the device is functional; the device should not be operated beyond such conditions.

(2) For soldering specifications: see product folder at www.ti.com

(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and

specifications.

Recommended Operating Conditions⁽¹⁾

Min

1.71

Nom

1.8

Max

1.89

Units

Supply Voltage (V_DDn

)

V

LVCMOS Supply Voltage (V_DDIO

OR

)

1.8

LVCMOS Supply Voltage (V_DDIO

3.0

3.3

3.6

25

V

V_DDn(1.8V)

V_DDIO(1.8V)

V_DDIO(3.3V)

mVp-p

°C

Supply Noise

25

50

Operating Free Air Temperature (T_A)

PCLK Clock Frequency

-40

10

+25

+105

43

MHz

(1) Supply noise testing was done with minimum capacitors (as shown on Figure 37 and Figure 38) on the PCB. A sinusoidal signal is AC

coupled to the VDDn (1.8V) supply with amplitude = 25 mVp-p measured at the device VDDn pins. Bit error rate testing of input to the

Ser and output of the Des with 10 meter cable shows no error when the noise frequency on the Ser is less than 1 MHz. The Des on the

other hand shows no error when the noise frequency is less than 750 kHz.

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Electrical Characteristics^(1)(2)(3)

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

LVCMOS DC SPECIFICATIONS 3.3V I/O (SER INPUTS, DES OUTPUTS, GPI, GPO, CONTROL INPUTS AND OUTPUTS)

V_IH

V_IL

High Level Input

Voltage

V_IN= 3.0V to 3.6V

2.0

V_IN

V

Low Level Input

Voltage

V_IN= 3.0V to 3.6V

GND

-20

0.8

+20

V

µA

V

I_IN

Input Current

V_IN= 0V or 3.6V, V_IN= 3.0V to 3.6V

V_DDIO= 3.0V to 3.6V, I_OH= −4 mA

±1

V_OH

High Level Output

Voltage

2.4

V_DDIO

V_OL

I_OS

Low Level Output

Voltage

V_DDIO= 3.0V to 3.6V, I_OL= +4 mA

GND

0.4

V

Serializer GPO

-24

-39

±1

Outputs

Output Short Circuit

Current

V_OUT= 0V

mA

µA

Deserializer LVCMOS

Outputs

TRI-STATE Output

Current

PDB = 0V,

V_OUT= 0V or V_DD

I_OZ

LVCMOS Outputs

-20

+20

LVCMOS DC SPECIFICATIONS 1.8V I/O (SER INPUTS, DES OUTPUTS, GPI, GPO, CONTROL INPUTS AND OUTPUTS)

V_IH

High Level Input

Voltage

V_IN= 1.71V to 1.89V

0.65 V_IN

V_IN+0.3

V

V_IL

Low Level Input

Voltage

V_IN= 1.71V to 1.89V

GND

-20

0.35 V_IN

+20

I_IN

Input Current

V_IN= 0V or 1.89V, V_IN= 1.71V to 1.89V

V_DDIO= 1.71V to 1.89V, I_OH= −4 mA

±1

µA

V

V_OH

High Level Output

Voltage

V_DDIO

0.45

-

V_DDIO

V_OL

I_OS

Low Level Output

Voltage

V_DDIO= 1.71V to 1.89V

I_OL= +4 mA

Deserializer LVCMOS

Outputs

GND

0.45

V

Serializer GPO

Outputs

-11

-20

±1

Output Short Circuit

Current

V_OUT= 0V

mA

µA

Deserializer LVCMOS

Outputs

I_OZ

TRI-STATE Output

Current

PDB = 0V,

V_OUT= 0V or V_DD

LVCMOS Outputs

-20

+20

CML DRIVER DC SPECIFICATIONS (DOUT+, DOUT-)

Output Differential

Voltage

|V_OD

|

R_T= 100Ω (Figure 8)

R_L= 100Ω

268

340

412

50

mV

V

Output Differential

Voltage Unbalance

ΔV_OD

1

V_DD- V_OD

1

V_OS

Output Differential

Offset Voltage

V_{DD (MIN)}

V_{OD (MAX)}

-

V_{DD (MAX)}

V_{OD (MIN)}

-

R_L= 100Ω (Figure 8)

R_L= 100Ω

ΔV_OS

I_OS

Offset Voltage

Unbalance

50

mV

mA

Output Short Circuit

Current

DOUT+/- = 0V

-27

R_T

Differential Internal

Termination

Differential across DOUT+ and DOUT-

80

100

120

Ω

Resistance

CML RECEIVER DC SPECIFICATIONS (RIN+, RIN-)

(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as

otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and

are not ensured.

(2) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground

except VOD, ΔVOD, VTH and VTL which are differential voltages.

(3) Typical values represent most likely parametric norms at 1.8V or 3.3V, T_A= +25°C, and at the Recommended Operation Conditions at

the time of product characterization and are not ensured.

8

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SNLS332E –JUNE 2010–REVISED APRIL 2013

Electrical Characteristics^(1)(2)(3)

(continued)

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Differential Threshold

High Voltage

V_TH

+90

(Figure 10)

RIN+ - RIN-

mV

V_TL

V_IN

Differential Threshold

Low Voltage

-90

Differential Input

Voltage Range

180

-20

mV

µA

I_IN

Input Current

V_IN= V_DDor 0V, V_DD= 1.89V

±1

+20

120

R_T

Differential Internal

Termination

Differential across RIN+ and RIN-

80

100

Ω

Resistance

SER/DES SUPPLY CURRENT *DIGITAL, PLL, AND ANALOG VDD

I_DDT

R_T= 100Ω

WORST CASE pattern

(Figure 5)

Serializer (Tx)

VDDn Supply Current

(includes load

current)

62

55

2

90

VDDn = 1.89V

PCLK = 43 MHz

Default Registers

mA

R_T= 100Ω

RANDOM PRBS-7 pattern

I_DDIOT

VDDIO = 1.89V

PCLK = 43 MHz

Default Registers

5

Serializer (Tx)

VDDIO Supply

Current (includes load

current)

R_T= 100Ω

WORST CASE pattern

(Figure 5)

mA

µA

VDDIO = 3.6V

PCLK = 43 MHz

Default Registers

7

15

I_DDTZ

V_DDn= 1.89V

V_DDIO= 1.89V

V_DDIO= 3.6V

370

55

775

125

135

Serializer (Tx) Supply PDB = 0V; All other

Current Power-down LVCMOS Inputs = 0V

I_DDIOTZ

65

I_DDR

V_DDn= 1.89V, C_L= 8 pF

PCLK = 43 MHz

SSCG[3:0] = ON

Default Registers

Deserializer (Rx)

WORST CASE Pattern

60

53

21

49

96

VDDn Supply Current

(Figure 5)

(includes load

V_DDn= 1.89V, C_L= 8 pF

current)

PCLK = 43 MHz

Default Registers

RANDOM PRBS-7 Pattern

mA

I_DDIOR

V_DDIO= 1.89V, C_L= 8 pF

PCLK = 43 MHz

Default Registers

Deserializer (Rx)

WORST CASE Pattern

32

83

VDDIO Supply

(Figure 5)

Current (includes load

V_DDIO= 3.6V, C_L= 8 pF

current)

PCLK = 43 MHz

Default Registers

WORST CASE Pattern

I_DDRZ

V_DDn= 1.89V

V_DDIO= 1.89V

V_DDIO= 3.6V

42

8

400

40

Deserializer (Rx)

PDB = 0V; All other

Supply Current

I_DDIORZ

µA

LVCMOS Inputs = 0V

Power-down

350

800

Recommended Serializer Timing for PCLK⁽¹⁾

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

t_TCP

Transmit Clock Period

23.3

T

100

ns

t_TCIH

t_TCIL

t_CLKT

f_OSC

Transmit Clock Input High

Time

0.4T

0.5

0.5T

0.6T

3

ns

10 MHz – 43 MHz

Transmit Clock Input Low

Time

PCLK Input Transition Time

(Figure 11)

ns

Internal oscillator clock

source

25

MHz

(1) Recommended Input Timing Requirements are input specifications and not tested in production.

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Serializer Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol

t_LHT

Parameter

Conditions

Min

Typ

Max

Units

CML Low-to-High Transition

Time

R_L= 100Ω (Figure 6)

150

330

ps

t_HLT

CML High-to-Low Transition

Time

R_L= 100Ω (Figure 6)

150

330

ps

t_DIS

t_DIH

t_PLD

t_SD

Data Input Setup to PCLK

Data Input Hold from PCLK

Serializer PLL Lock Time

2.0

ns

Serializer Data Inputs (Figure 12)

R_L= 100Ω⁽¹⁾⁽²⁾

1

2

ms

R_T= 100Ω, PCLK = 10–43 MHz

Register 0x03h b[0] (TRFB = 1)

(Figure 14)

6.386T

+ 5

6.386T

+ 12

6.386T

+ 19.7

Serializer Delay

ns

UI

t_JIND

Serializer output intrinsic deterministic

jitter . Measured (cycle-cycle) with

PRBS-7 test pattern

Serializer Output

Deterministic Jitter

0.13

0.04

PCLK = 43 MHz⁽³⁾⁽⁴⁾

t_JINR

Serializer output intrinsic random jitter

(cycle-cycle). Alternating-1,0 pattern.

PCLK = 43 MHz⁽³⁾⁽⁴⁾

Serializer Output Random

Jitter

t_JINT

Serializer output peak-to-peak jitter

includes deterministic jitter, random

jitter, and jitter transfer from serializer

input. Measured (cycle-cycle) with

PRBS-7 test pattern.

Peak-to-peak Serializer

Output Jitter

0.396

UI

PCLK = 43 MHz⁽³⁾⁽⁴⁾

λ_STXBW

δ_STX

Serializer Jitter Transfer

Function -3 dB Bandwidth

PCLK = 43 MHz, Default Registers

(Figure 20)⁽³⁾

1.90

MHz

dB

Serializer Jitter Transfer

Function (Peaking)

PCLK = 43 MHz, Default Registers

(Figure 20)⁽³⁾

0.944

δ_STXf

Serializer Jitter Transfer

Function (Peaking

Frequency)

PCLK = 43 MHz, Default Registers

(Figure 20)⁽³⁾

500

kHz

(1) t_PLDand t_DDLTis the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK

(2) Specification is ensured by design.

(3) Typical values represent most likely parametric norms at 1.8V or 3.3V, T_A= +25°C, and at the Recommended Operation Conditions at

the time of product characterization and are not ensured.

(4) UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.

Deserializer Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol

t_RCP

Parameter

Conditions

t_RCP= t_TCP

Pin/Freq.

Min

Typ

Max

Units

Receiver Output Clock Period

PCLK

23.3

T

100

ns

t_PDC

Default Registers

SSCG[3:0] = OFF

PCLK Duty Cycle

PCLK

45

50

55

%

LVCMOS Low-to-High Transition

Time

V_DDIO: 1.71V to 1.89V or

3.0 to 3.6V,

t_CLH

t_CHL

1.3

2.0

2.8

C_L= 8 pF (lumped load) PCLK

Default Registers

ns

LVCMOS High-to-Low Transition

Time

1.3

1.6

2.0

2.4

2.8

3.3

(Figure 16)⁽¹⁾

LVCMOS Low-to-High Transition

Time

V_DDIO: 1.71V to 1.89V or

3.0 to 3.6V,

C_L= 8 pF (lumped load)

Default Registers

(Figure 16)⁽¹⁾

t_CLH

t_CHL

Deserializer ROUTn

Data Outputs

ns

LVCMOS High-to-Low Transition

Time

1.6

2.4

t_ROS

t_ROH

ROUT Setup Data to PCLK

ROUT Hold Data to PCLK

V_DDIO: 1.71V to 1.89V or

3.0V to 3.6V,

C_L= 8 pF (lumped load) Data Outputs

Default Registers

0.38T

0.5T

Deserializer ROUTn

(1) Specification is ensured by characterization and is not tested in production.

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Deserializer Switching Characteristics (continued)

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol

Parameter

Deserializer Delay

Conditions

Pin/Freq.

Min

Typ

Max

Units

Default Registers

Register 0x03h b[0]

(RRFB = 1) (Figure 17)

4.571T

+ 8

4.571T

+ 12

4.571T

+ 16

t_DD

10 MHz–43 MHz

ns

t_DDLT

t_RJIT

Deserializer Data Lock Time

Receiver Input Jitter Tolerance

(Figure 15)⁽²⁾

10 MHz–43 MHz

43 MHz

10

ms

UI

(Figure 19,

0.53

Figure 21)⁽³⁾⁽⁴⁾

t_RCJ

10 MHz

43 MHz

10 MHz

43 MHz

10 MHz

43 MHz

300

120

425

320

300

550

250

600

480

500

PCLK

Receiver Clock Jitter

ps

SSCG[3:0] = OFF⁽¹⁾⁽⁵⁾

t_DPJ

PCLK

Deserializer Period Jitter

SSCG[3:0] = OFF⁽¹⁾⁽⁶⁾

t_DCCJ

Deserializer Cycle-to-Cycle Clock PCLK

Jitter

SSCG[3:0] = OFF⁽¹⁾⁽⁷⁾

fdev

Spread Spectrum Clocking

Deviation Frequency

±0.5% to

±2.0%

20 MHz–43 MHz

%

LVCMOS Output Bus

SSC[3:0] = ON

(Figure 22)

fmod

Spread Spectrum Clocking

Modulation Frequency

9 kHz to

66 kHz

kHz

(2) t_PLDand t_DDLTis the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK

(3) UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.

(4) t_RJITmax (0.61UI) is limited by instrumentation and actual t_RJITof in-band jitter at low frequency (<2 MHz) is greater 1 UI.

(5) t_DCJis the maximum amount of jitter measured over 30,000 samples based on Time Interval Error (TIE).

(6) t_DPJis the maximum amount the period is allowed to deviate measured over 30,000 samples.

(7) t_DCCJis the maximum amount of jitter between adjacent clock cycles measured over 30,000 samples.

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Units

Bidirectional Control Bus AC Timing Specifications (SCL, SDA) - I²C Compliant

Over recommended supply and temperature ranges unless otherwise specified. See Figure 4.

Symbol

Parameter

Conditions

Min

Typ

Max

RECOMMENDED INPUT TIMING REQUIREMENTS⁽¹⁾

f_SCL

SCL Clock Frequency

SCL Low Period

>0

4.7

4.0

100

kHz

µs

t_LOW

t_HIGH

SCL High Period

µs

Hold time for a start or a repeated start

condition

t_HD:STA

t_SU:STA

4.0

4.7

µs

Set Up time for a start or a repeated

start condition

f_SCL= 100 kHz

t_HD:DAT

t_SU:DAT

t_SU:STO

t_r

Data Hold Time

0

3.45

µs

ns

µs

ns

pF

Data Set Up Time

250

4.0

Set Up Time for STOP Condition

SCL & SDA Rise Time

SCL & SDA Fall Time

Capacitive load for bus

1000

300

t_f

C_b

400

SWITCHING CHARACTERISTICS⁽²⁾

Serializer MODE = 0 – R/W

Register 0x05 = 0x40'h

100

f_SCL

SCL Clock Frequency

SCL Low Period

kHz

µs

Deserializer MODE = 0 – READ

Register 0x06 b[6:4] = 0x00'h

Serializer MODE = 0 – R/W

Register 0x05 = 0x40'h

t_LOW

4.7

4.0

Deserializer MODE = 0 – READ

Register 0x06 b[6:4] = 0x00'h

Serializer MODE = 0 – R/W

Register 0x05 = 0x40'h

t_HIGH

SCL High Period

µs

Deserializer MODE = 0 – READ

Register 0x06 b[6:4] = 0x00'h

Hold time for a start or a repeated start

condition

Serializer MODE = 0

Register 0x05 = 0x40'h

t_HD:STA

t_SU:STA

4.0

4.7

µs

Set Up time for a start or a repeated

start condition

Serializer MODE = 0

Register 0x05 = 0x40'h

t_HD:DAT

t_SU:DAT

t_SU:STO

t_f

Data Hold Time

0

3.45

300

µs

ns

µs

ns

Data Set Up Time

250

4.0

Set Up Time for STOP Condition

SCL & SDA Fall Time

Serializer MODE = 0

Bus free time between a stop and start

condition

t_BUF

Serializer MODE = 0

Serializer MODE = 1

4.7

µs

1

t_TIMEOUTNACK Time out

ms

Deserializer MODE = 1

Register 0x06 b[2:0]=111'b

25

(1) Recommended Input Timing Requirements are input specifications and not tested in production.

(2) Specification is ensured by design.

12

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SDA

SCL

t

BUF

t

f

t

HD;STA

t

r

LOW

t

f

r

t

HD;STA

SU;STA

t

SU;STO

t

HIGH

t

SU;DAT

HD;DAT

STOP START

START

REPEATED

START

Figure 4. Bidirectional Control Bus Timing

Bidirectional Control Bus DC Characteristics (SCL, SDA) - I²C Compliant

Over recommended supply and temperature ranges unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

V_IH

V_IL

0.7 x

V_DDIO

Input High Level

SDA and SCL

V_DDIO

V

0.3 x

V_DDIO

Input Low Level Voltage

SDA and SCL

GND

V

V_HY

I_OZ

I_IN

Input Hysteresis

>50

±1

mV

µA

pF

TRI-STATE Output Current

Input Current

PDB = 0V, V_OUT= 0V or V_DD

-20

+20

SDA or SCL, Vin = V_DDIOor GND

±1

C_IN

V_OL

Input Pin Capacitance

<5

SCL and SDA, V_DDIO= 3.0V

I_OL= 1.5 mA

0.36

V

Low Level Output Voltage

SCL and SDA, V_DDIO= 1.71V

I_OL= 1 mA

AC Timing Diagrams and Test Circuits

Device Pin Name

Signal Pattern

T

PCLK

(RFB = H)

D

/R

IN OUT

Figure 5. “Worst Case” Test Pattern

80%

20%

80%

Vdiff

Vdiff = 0V

20%

t

LHT

HLT

Vdiff = (D

+) - (D

-)

OUT

Figure 6. Serializer CML Output Load and Transition Times

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100 nF

D

+

OUT

50W

SCOPE

BW 8 4.0 GHz

Z

Diff

= 100W

100W

D

-

OUT

Figure 7. Serializer CML Output Load and Transition Times

D

+

OUT

21

R

D

IN

L

-

OUT

PCLK

Figure 8. Serializer VOD DC Diagram

D

OUT

-

Single Ended

V

OD-

OD

OD+

V

D

OUT

+

OS

ö

0V

Differential

V

OD+

0V

(D +)-(D )

OUT OUT-

V

OD-

Figure 9. Serializer VOD DC Diagram

RIN+

RIN-

V

TH

V

CM

V

TL

V

IN

V

ID

V

IN

ID

RIN-

GND

Figure 10. Differential VTH/VTL Definition Diagram

V

DD

80%

PCLK

20%

0V

t

CLKT

Figure 11. Serializer Input Clock Transition Times

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t

TCP

PCLK

DINn

V

DDIO

/2

V

/2

V

/2

DDIO

t

DIH

DIS

DDIO

Setup

Hold

V

/2

V

/2

DDIO

0V

Figure 12. Serializer Setup/Hold Times

VDDIO/2

PDB

PCLK

t

PLD

TRI-STATE

Output Active

D

±

OUT

Figure 13. Serializer Data Lock Time

SYMBOL N

VDDIO/2

SYMBOL N+1

SYMBOL N+2

SYMBOL N+3

D

IN

t

SD

PCLK

SYMBOL N-4

SYMBOL N-3

SYMBOL N-2

SYMBOL N-1

SYMBOL N

0V

DOUT+-

Figure 14. Serializer Delay

VDDIO/2

PDB

t

DDLT

R

IN±

LOCK

TRI-STATE

VDDIO/2

Figure 15. Deserializer Data Lock Time

80%

20%

80%

20%

Deserializer

8 pF

lumped

t

CHL

CLH

Figure 16. Deserializer LVCMOS Output Load and Transition Times

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SYMBOL N

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SYMBOL N + 1

SYMBOL N + 2

SYMBOL N + 3

RIN±

0V

t

DD

PCLK

VDDIO/2

SYMBOL N - 3

SYMBOL N - 2

SYMBOL N - 1

SYMBOL N

SYMBOL N+1

ROUTn

Figure 17. Deserializer Delay

t

RCP

V

DDIO

PCLK

1/2 V

DDIO

0V

V

DDIO

ROUT[n],

VS, HS

1/2 V

DDIO

1/2 V

DDIO

0V

t

ROH

ROS

Figure 18. Deserializer Output Setup/Hold Times

Ideal Data

Bit End

Sampling

Window

Ideal Data Bit

Beginning

V

TH

0V

RxIN_TOL

Left

RxIN_TOL

Right

V

TL

Ideal Center Position (t /2)

BIT

t

(1 UI)

BIT

t

= RxIN_TOL (Left + Right)

RJIT

Sampling Window = 1 UI - t

RJIT

Figure 19. Receiver Input Jitter Tolerance

2

0

-2

-4

-6

-8

-10

-12

-14

-16

-18

1.0E+04

1.0E+05

1.0E+06

1.0E+07

MODULATION FREQUENCY (Hz)

Figure 20. Typical Serializer Jitter Transfer Function Curve at 43 MHz

16

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0.62

0.61

0.60

0.59

0.58

0.57

0.56

0.55

0.54

0.53

0.52

1.0E+06

JITTER FREQUENCY (Hz)

1.0E+04

1.0E+05

1.0E+07

Figure 21. Typical Deserializer Input Jitter Tolerance Curve at 43 MHz

Frequency

F_PCLK+

F_PCLK

F_PCLK-

fdev (max)

fdev

fdev (min)

Time

1 / fmod

Figure 22. Spread Spectrum Clock Output Profile

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Table 1. DS90UB903Q Control Registers

Addr

(Hex)

Name

Bits Field

R/W

Default

Description

7-bit address of Serializer; 0x58'h

(1011_000X'b) default

7:1

DEVICE ID

0

I²C Device ID

RW

0xB0'h

0x00'h

0: Device ID is from ID[x]

0

SER ID SEL

RESERVED

1: Register I²C Device ID overrides ID[x]

7:3

Reserved

Standby mode control. Retains control register data.

Supported only when MODE = 0

2

STANDBY

RW

0

0: Enabled. Low-current Standby mode with wake-up

capability. Suspends all clocks and functions.

1: Disabled. Standby and wake-up disabled

1

2

Reset

DIGITAL

RESET0

1: Resets the device to default register values. Does not

1

0

RW

self clear affect device I²C Bus or Device ID

0

1: Digital Reset, retains all register values

DIGITAL RESET1

self clear

Reserved

7:0

7:6

RESERVED

0x20'h

11'b

Reserved

Auto V_DDIOdetect

Allows manual setting of VDDIO by register.

0: Disable

1: Enable (auto detect mode)

VDDIO Control

VDDIO Mode

5

4

VDDIO CONTOL

VDDIO MODE

RW

1

VDDIO voltage set

Only used when VDDIOCONTROL = 0

0: 1.8V

1: 3.3V

I²C Pass-Through

0: Disabled

RW

I²C PASS-

THROUGH

I²C Pass-Through

RESERVED

3

2

1

0

3

1: Enabled

RESERVED

Reserved

Switch over to internal 25 MHz Oscillator clock in the

absence of PCLK

0: Disable

1: Enable

PCLK_AUTO

1

PCLK_AUTO

RW

1

Pixel Clock Edge Select:

0: Parallel Interface Data is strobed on the Falling Clock

Edge.

TRFB

0

TRFB

1

1: Parallel Interface Data is strobed on the Rising Clock

Edge.

4

5

RESERVED

I²C Bus Rate

7:0

RESERVED

0x80'h

0x40'h

0xC0'h

Reserved

I²C SCL frequency is determined by the following:

f_SCL= 6.25 MHz / Register value (in decimal)

0x40'h = ~100 kHz SCL (default)

I²C BUS RATE

RW

Note: Register values <0x32'h are NOT supported.

Deserializer Device ID = 0x60'h

(1100_000X'b) default

7:1

DES DEV ID

6

7

DES ID

0

RESERVED

SLAVE DEV ID

RESERVED

Reserved

7:1

0

RW

0x00'h

Slave Device ID. Sets remote slave I²C address.

Slave ID

Reserved

8

9

Reserved

7:0

0x00'h

0x01'h

0x00'h

A

B

18

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Table 1. DS90UB903Q Control Registers (continued)

Addr

(Hex)

Name

Reserved

PCLK Detect

Reserved

Bits Field

R/W

Default

Description

7:3

2

RESERVED

0x00'h

Reserved

1: Valid PCLK detected

0: Valid PCLK not detected

PCLK DETECT

RESERVED

R

0

C

3

Reserved

Cable Link Detect

Status

0: Cable link not detected

1: Cable link detected

0

LINK DETECT

R

D

E

Reserved

7:0

RESERVED

GPCR[7]

0x11'h

0x01'h

0x03'h

Reserved

0: LOW

F

10

11

12

GPCR[6]

1: HIGH

GPCR[5]

GPCR[4]

General Purpose

Control Reg

13

7:0

RW

0x00'h

GPCR[3]

GPCR[2]

GPCR[1]

GPCR[0]

Table 2. DS90UB904Q Control Registers

Addr

(Hex)

Name

Bits

Field

R/W

Default

Description

RW

0xC0'h

7-bit address of Deserializer; 0x60h

(1100_000X) default

7:1

DEVICE ID

0

I²C Device ID

0: Device ID is from ID[x]

0

DES ID SEL

RESERVED

1: Register I²C Device ID overrides ID[x]

7:3

0x00'h

Reserved

Remote Wake-up Select

1: Enable

Generate remote wakeup signal automatically wake-up

the Serializer in Standby mode

0: Disable

2

REM_WAKEUP

RW

0

1

Reset

Puts the Serializer in Standby mode

1: Resets the device to default register values. Does not

1

0

DIGITALRESET0

DIGITALRESET1

RW

self clear affect device I²C Bus or Device ID

0

1: Digital Reset, retains all register values

self clear

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Table 2. DS90UB904Q Control Registers (continued)

Addr

(Hex)

Name

Bits

7:6

5

Field

RESERVED

AUTO_CLOCK

R/W

Default

00'b

0

Description

RESERVED

Auto Clock

Reserved

1: Output PCLK or Internal 25 MHz Oscillator clock

0: Only PCLK when valid PCLK present

RW

Output Sleep State Select

0: Outputs = TRI-STATE, when LOCK = L

1: Outputs = LOW , when LOCK = L

OSS Select

4

OSS_SEL

0

SSCG Select

0000: Normal Operation, SSCG OFF (default)

0001: fmod (kHz) PCLK/2168, fdev ±0.50%

0010: fmod (kHz) PCLK/2168, fdev ±1.00%

0011: fmod (kHz) PCLK/2168, fdev ±1.50%

0100: fmod (kHz) PCLK/2168, fdev ±2.00%

0101: fmod (kHz) PCLK/1300, fdev ±0.50%

0110: fmod (kHz) PCLK/1300, fdev ±1.00%

0111: fmod (kHz) PCLK/1300, fdev ±1.50%

1000: fmod (kHz) PCLK/1300, fdev ±2.00%

1001: fmod (kHz) PCLK/868, fdev ±0.50%

1010: fmod (kHz) PCLK/868, fdev ±1.00%

1011: fmod (kHz) PCLK/868, fdev ±1.50%

1100: fmod (kHz) PCLK/868, fdev ±2.00%

1101: fmod (kHz) PCLK/650, fdev ±0.50%

1110: fmod (kHz) PCLK/650, fdev ±1.00%

1111: fmod (kHz) PCLK/650, fdev ±1.50%

2

SSCG

3:0

SSCG

0000'b

RESERVED

7:6

5

RESERVED

11'b

1

Reserved

Auto voltage control

0: Disable

1: Enable (auto detect mode)

VDDIO Control

VDDIO CONTROL

RW

VDDIO voltage set

Only used when VDDIOCONTROL = 0

0: 1.8V

1: 3.3V

I²C Pass-Through Mode

0: Disabled

VDDIO Mode

4

3

VDDIO MODE

0

1

I²C PASS-

THROUGH

3

I²C Pass-Through

RW

1: Enabled

0: Disable

1: Enable

Auto ACK

2

1

AUTO ACK

RESERVED

0

RESERVED

Reserved

Pixel Clock Edge Select

0: Parallel Interface Data is strobed on the Falling Clock

RRFB

0

RRFB

RW

1

Edge

1: Parallel Interface Data is strobed on the Rising Clock

Edge.

EQ Gain

00'h = ~0.0 dB

01'h = ~4.5 dB

03'h = ~6.5 dB

07'h = ~7.5 dB

0F'h = ~8.0 dB

1F'h = ~11.0 dB

3F'h = ~12.5 dB

FF'h = ~14.0 dB

4

5

EQ Control

7:0

EQ

0x00'h

RESERVED

Reserved

20

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Table 2. DS90UB904Q Control Registers (continued)

Addr

(Hex)

Name

Bits

Field

R/W

Default

Description

RESERVED

7

RESERVED

0

Reserved

Prescales the SCL clock line when reading data byte

from a slave device (MODE = 0)

000 : ~100 kHz SCL (default)

001 : ~125 kHz SCL

101 : ~11 kHz SCL

110 : ~33 kHz SCL

SCL Prescale

Remote NACK

6:4

SCL_PRESCALE

RW

000'b

111 : ~50 kHz SCL

Other values are NOT supported.

Remote NACK Timer Enable

In slave mode (MODE = 1) if bit is set the I²C core will

REM_NACK_TIME

R

automatically timeout when no acknowledge condition

was detected.

1: Enable

6

3

RW

1

0: Disable

Remote NACK Timeout.

000: 2.0 ms

001: 5.2 ms

010: 8.6 ms

Remote NACK

2:0

7:1

NACK_TIMEOUT

SER DEV ID

111'b

011: 11.8 ms

100: 14.4 ms

101: 18.4 ms

110: 21.6 ms

111: 25.0 ms

RW

0xB0'h

0x00'h

Serializer Device ID = 0x58'h

(1011_000X'b) default

7

SER ID

0

7:1

0

RESERVED

ID[0] INDEX

RESERVED

ID[1] INDEX

RESERVED

ID[2] INDEX

RESERVED

ID[3] INDEX

RESERVED

ID[4] INDEX

RESERVED

ID[5] INDEX

RESERVED

ID[6] INDEX

RESERVED

ID[7] INDEX

RESERVED

ID[0] MATCH

RESERVED

ID[1] MATCH

RESERVED

ID[2] MATCH

RESERVED

ID[3] MATCH

RESERVED

ID[4] MATCH

RESERVED

Reserved

Target slave Device ID slv_id0 [7:1]

Reserved

8

9

ID[0] Index

ID[1] Index

ID[2] Index

ID[3] Index

ID[4] Index

ID[5] Index

ID[6] Index

ID[7] Index

ID[0] Match

ID[1] Match

ID[2] Match

ID[3] Match

ID[4] Match

7:1

0

Target slave Device ID slv_id1 [7:1]

Reserved

RW

0x00'h

7:1

0

Target slave Device ID slv_id2 [7:1]

Reserved

A

7:1

0

Target slave Device ID slv_id3 [7:1]

Reserved

B

7:1

0

Target slave Device ID slv_id4 [7:1]

Reserved

C

7:1

0

Target slave Device ID slv_id5 [7:1]

Reserved

D

7:1

0

Target slave Device ID slv_id6 [7:1]

Reserved

E

7:1

0

Target slave Device ID slv_id7 [7:1]

Reserved

F

7:1

0

Alias to match Device ID slv_id0 [7:1]

Reserved

10

11

12

13

14

7:1

0

Alias to match Device ID slv_id1 [7:1]

Reserved

7:1

0

Alias to match Device ID slv_id2 [7:1]

Reserved

7:1

0

Alias to match Device ID slv_id3 [7:1]

Reserved

7:1

0

Alias to match Device ID slv_id4 [7:1]

Reserved

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Table 2. DS90UB904Q Control Registers (continued)

Addr

(Hex)

Name

Bits

Field

R/W

Default

Description

7:1

0

ID[5] MATCH

RESERVED

ID[6] MATCH

RESERVED

ID[7] MATCH

RESERVED

Alias to match Device ID slv_id5 [7:1]

15

16

17

ID[5] Match

RW

0x00'h

Reserved

7:1

0

Alias to match Device ID slv_id6 [7:1]

ID[6] Match

ID[7] Match

RW

0x00'h

Reserved

7:1

0

Alias to match Device ID slv_id [7:1]

Reserved

18

19

1A

1B

RESERVED

7:0

7:3

2

0x00'h

0x01'h

0x00'h

0

Signal Detect

Status

0: Active signal not detected

1: Active signal detected

1C

1

0

R

0

0: CDR/PLL Unlocked

1: CDR/PLL Locked

LOCK Pin Status

1D

1E

1F

20

21

22

Reserved

7:0

RESERVED

0x17'h

0x07'h

0x01'h

Reserved

GPCR[7]

GPCR[6]

GPCR[5]

GPCR[4]

GPCR[3]

GPCR[2]

GPCR[1]

GPCR[0]

0: LOW

1: HIGH

General Purpose

Control Reg

23

7:0

RW

0x00'h

BIST Enable

24

25

BIST

0

BIST_EN

RW

R

0

0: Normal operation

1: Bist Enable

BIST_ERR

7:0

7:6

BIST_ERR

0x00'h

00'b

Bist Error Counter

11: Enable remote wake up mode

00: Normal operation mode

Other values are NOT supported

REM_WAKEUP_

EN

RW

Remote Wake

Enable

26

27

5:0

7:6

5:0

7:5

RESERVED

BCC

RW

0

00'b

0

Reserved

11: Normal operation mode

Reserved

BCC

RESERVED

0

Reserved

CMLOUT P/N

Enable

1: Disabled (Default)

0: Enabled

3F

CMLOUT Config

4

RW

1

0

3:0

RESERVED

Reserved

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FUNCTIONAL DESCRIPTION

The DS90UB903Q/904Q FPD-Link III chipset is intended for video display applications. The Serializer/

Deserializer chipset operates from a 10 MHz to 43 MHz pixel clock frequency. The DS90UB903Q transforms a

21-bit wide parallel LVCMOS data bus along with a bidirectional control bus into a single high-speed differential

pair. The high-speed serial bit stream contains an embedded clock and DC-balance information which enhances

signal quality to support AC coupling. The DS90UB904Q receives the single serial data stream and converts it

back into a 21-bit wide parallel data bus together with the bidirectional control channel data bus.

The control channel function of the DS90UB903Q/904Q provides bidirectional communication between the host

processor and display. The integrated control channel transfers data simultaneously over the same differential

pair used for video data interface. This interface offers advantages over other chipsets by eliminating the need

for additional wires for programming and control. The control supports I²C port. The bidirectional control channel

offers asymmetrical communication and is not dependent on video blanking intervals.

DISPLAY APPLICATION

The DS90UB903Q/904Q chipset is intended for interface between a host (graphics processor) and a Display. It

supports a 21 bit parallel video bus for 18-bit color depth (RGB666) display format. In a RGB666 configuration,

18 color bits (R[5:0], G[5:0], B[5:0]), Pixel Clock (PCLK) and three control bits (VS, HS and DE) are supported

across the serial link.

The DS90UB903Q Serializer accepts a 21-bit parallel data bus along with a bidirectional control bus. The parallel

data and bidirectional control channel information is converted into a single differential link. The integrated

bidirectional control channel bus supports I2C compatible operation for controlling auxiliary data transport to and

from host processor and display module. The DS90UB904Q Deserializer extracts the clock/control information

from the incoming data stream and reconstructs the 21-bit data with control channel data.

DS90UB903Q

Serializer

DS90UB904Q

Deserializer

FPD-Link III

R[5:0]

G[5:0]

B[5:0]

VS

R[5:0]

G[5:0]

B[5:0]

VS

Graphics

Controller

---

Timing

Controller

LCD Display

--

Touch Panel

HS

DE

PCLK

HS

DE

PCLK

Video

Processor

SDA

SCL

2

SDA

SCL

2

mC

I C

Figure 23. Typical Display System Diagram

SERIAL FRAME FORMAT

The DS90UB903Q/904Q chipset will transmit and receive a pixel of data in the following format:

I2C

Bit 0 to Bit 20

Figure 24. Serial Bitstream for 28-bit Symbol

The High Speed Forward Channel is a 28-bit symbol composed of 21 bits of data containing video data & control

information transmitted from Serializer to Deserializer. CLK1 and CLK0 represent the embedded clock in the

serial stream. CLK1 is always HIGH and CLK0 is always LOW. This data payload is optimized for signal

transmission over an AC coupled link. Data is randomized, balanced and scrambled.

The bidirectional control channel data is transferred along with the high-speed forward data over the same serial

link. This architecture provides a full duplex low speed forward channel across the serial link together with a high

speed forward channel without the dependence of the video blanking phase.

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DESCRIPTION OF BIDIRECTIONAL CONTROL BUS AND I2C MODES

The I²C compatible interface allows programming of the DS90UB903Q, DS90UB904Q, or an external remote

device (such as a display) through the bidirectional control channel. Register programming transactions to/from

the DS90UB903Q/904Q chipset are employed through the clock (SCL) and data (SDA) lines. These two signals

have open-drain I/Os and both lines must be pulled-up to VDDIO by external resistor. Figure 4 shows the timing

relationships of the clock (SCL) and data (SDA) signals. Pull-up resistors or current sources are required on the

SCL and SDA busses to pull them high when they are not being driven low. A logic zero is transmitted by driving

the output low. A logic high is transmitted by releasing the output and allowing it to be pulled-up externally. The

appropriate pull-up resistor values will depend upon the total bus capacitance and operating speed. The

DS90UB903Q/904Q I²C bus data rate supports up to 100 kbps according to I²C specification.

To start any data transfer, the DS90UB903Q/904Q must be configured in the proper I²C mode. Each device can

function as an I²C slave proxy or master proxy depending on the mode determined by MODE pin. The Ser/Des

interface acts as a virtual bridge between Master Controller Unit (MCU) and the remote device. When the MODE

pin is set to High, the device is treated as a slave proxy; acts as a slave on behalf of the remote slave. When

addressing a remote peripheral or Serializer/Deserializer (not wired directly to the MCU), the slave proxy will

forward any byte transactions sent by the Master controller to the target device. When MODE pin is set to Low,

the device will function as a master proxy device; acts as a master on behalf of the I²C master controller. Note

that the devices must have complementary settings for the MODE configuration. For example, if the Serializer

MODE pin is set to High then the Deserializer MODE pin must be set to Low and vice-versa.

Bus Activity:

Master

Register

Address

Slave

Address

Data

SDA Line

7-bit Address

P

S

0

A

C

K

A

C

K

A

C

K

Bus Activity:

Slave

Figure 25. Write Byte

N

A

C

K

Bus Activity:

Master

Register

Address

Slave

Address

Slave

Address

S

P

SDA Line

S

7-bit Address

0

1

A

C

K

A

C

K

A

C

K

Data

Bus Activity:

Slave

Figure 26. Read Byte

ACK

LSB

MSB

N/ACK

SDA

SCL

MSB

LSB

R/W

Direction

7-bit Slave Address

Data Byte

Bit

Acknowledge

*Acknowledge

or Not-ACK

from the Device

8

9

8

9

1

2

6

7

1

2

Repeated for the Lower Data Byte

and Additional Data Transfers

START

STOP

Figure 27. Basic Operation

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SDA

SCL

S

P

STOP condition

START condition, or

START repeat condition

Figure 28. START and STOP Conditions

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SLAVE CLOCK STRETCHING

In order to communicate and synchronize with remote devices on the I²C bus through the bidirectional control

channel, slave clock stretching must be supported by the I²C master controller/MCU. The chipset utilizes bus

clock stretching (holding the SCL line low) during data transmission; where the I²C slave pulls the SCL line low

prior to the 9th clock of every I²C data transfer (before the ACK signal). The slave device will not control the

clock and only stretches it until the remote peripheral has responded.

Any remote access involves the clock stretching period following the transmitted byte, prior to completion of the

acknowledge bit. Since each byte transferred to the I²C slave must be acknowledged separately, the clock

stretching will be done for each byte sent by the host controller. For remote accesses, the “Response Delay”

shown is on the order of 12 µs (typical). See Application Note AN-2173 (SNLA131) for more details.

ID[X] ADDRESS DECODER

The ID[x] pin is used to decode and set the physical slave address of the Serializer/Deserializer (I²C only) to

allow up to six devices on the bus using only a single pin. The pin sets one of six possible addresses for each

Serializer/Deserializer device. The pin must be pulled to VDD (1.8V, NOT VDDIO)) with a 10 kΩ resistor and a

pull down resistor (RID) of the recommended value to set the physical device address. The recommended

maximum resistor tolerance is 0.1% worst case (0.2% total tolerance).

1.8V

10k

V

DDIO

ID[x]

RPU

SER

or

R

ID

HOST

SCL

SDA

SCL

SDA

DES

To other

Devices

Figure 29. Bidirectional Control Bus Connection

Table 3. ID[x] Resistor Value – DS90UB903Q

ID[x] Resistor Value - DS90UB903Q Ser

Resistor RID Ω (±0.1%)

Address 7'b⁽¹⁾

Address 8'b 0 appended (WRITE)

0, GND

2.0k

7b' 101 1000 (h'58)

7b' 101 1001 (h'59)

7b' 101 1010 (h'5A)

7b' 101 1011 (h'5B)

7b' 101 1100 (h'5C)

7b' 101 1110 (h'5E)

8b' 1011 0000 (h'B0)

8b' 1011 0010 (h'B2)

8b' 1011 0100 (h'B4)

8b' 1011 0110 (h'B6)

8b' 1011 1000 (h'B8)

8b' 1011 1100 (h'BC)

4.7k

8.2k

12.1k

39.0k

(1) Specification is ensured by design.

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Table 4. ID[x] Resistor Value – DS90UB904Q

ID[x] Resistor Value - DS90UB904Q Des

Address 7'b⁽¹⁾

Resistor RID Ω (±0.1%)

Address 8'b 0 appended (WRITE)

8b' 1100 0000 (h'C0)

0, GND

2.0k

7b' 110 0000 (h'60)

7b' 110 0001 (h'61)

8b' 1100 0010 (h'C2)

4.7k

7b' 110 0010 (h'62)

8b' 1100 0100 (h'C4)

8.2k

7b' 110 0011 (h'63)

8b' 1101 0110 (h'C6)

12.1k

39.0k

7b' 110 0100 (h'64)

8b' 1101 1000 (h'C8)

7b' 110 0110 (h'66)

8b' 1100 1100 (h'CC)

(1) Specification is ensured by design.

CAMERA MODE OPERATION

In Camera mode, I²C transactions originate from the Deserializer from the Master controller (Figure 30). The I²C

slave core in the Deserializer will detect if a transaction is intended for the Serializer or a slave at the Serializer.

Commands are sent over the bidirectional control channel to initiate the transactions. The Serializer will receive

the command and generate an I²C transaction on its local I²C bus. At the same time, the Serializer will capture

the response on the I²C bus and return the response as a command on the forward channel link. The

Deserializer parses the response and passes the appropriate response to the Deserializer I²C bus.

To configure the devices for camera mode operation, set the Serializer MODE pin to Low and the Deserializer

MODE pin to High. Before initiating any I²C commands, the Deserializer needs to be programmed with the target

slave device addresses and Serializer device address. SER_DEV_ID Register 0x07h sets the Serializer device

address and SLAVE_x_MATCH/SLAVE_x_INDEX registers 0x08h~0x17h set the remote target slave addresses.

The slave address match registers must also be set. In slave mode the address register is compared with the

address byte sent by the I²C master. If the addresses are equal to any of registers values, the I²C slave will

acknowledge the transaction to the I²C master allowing reads or writes to target device.

DS90UB904Q

DS90UB903Q

Deserializer

Host

--

Serializer

FPGA

--

Video

Processor

CMOS

Image

Sensor

DIN[20:0]

PCLK

ROUT[20:0]

PCLK

µC

I²C

SDA

SCL

SDA

SCL

Figure 30. Typical Camera System Diagram

DISPLAY MODE OPERATION

In Display mode, I²C transactions originate from the controller attached to the Serializer. The I²C slave core in

the Serializer will detect if a transaction targets (local) registers within the Serialier or the (remote) registers within

the Deserializer or a remote slave connected to the I²C master interface of the Deserializer. Commands are sent

over the forward channel link to initiate the transactions. The Deserializer will receive the command and generate

an I²C transaction on its local I²C bus. At the same time, the Deserializer will capture the response on the I²C

bus and return the response as a command on the bidirectional control channel. The Serializer parses the

response and passes the appropriate response to the Serializer I²C bus.

The physical device ID of the I²C slave in the Serializer is determined by the analog voltage on the ID[x] input. It

can be reprogrammed by using the SER_DEV_ID register and setting the bit . The device ID of the logical I²C

slave in the Deserializer is determined by programming the DES ID in the Serializer. The state of the ID[x] input

on the Deserializer is used to set the device ID. The I²C transactions between Ser/Des will be bridged between

the host to the remote slave.

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To configure the devices for display mode operation, set the Serializer MODE pin to High and the Deserializer

MODE pin to Low. Before initiating any I²C commands, the Serializer needs to be programmed with the target

slave device address and Serializer device address. DES_DEV_ID Register 0x06h sets the Deserializer device

address and SLAVE_DEV_ID register 0x7h sets the remote target slave address. If the I²C slave address

matches any of registers values, the I²C slave will acknowledge the transaction allowing read or write to target

device. Note: In Display mode operation, registers 0x08h~0x17h on Deserializer must be reset to 0x00.

PROGRAMMABLE CONTROLLER

An integrated I²C slave controller is embedded in each of the DS90UB903Q Serializer and DS90UB904Q

Deserializer. It must be used to access and program the extra features embedded within the configuration

registers. Refer to Table 1 and Table 2 for details of control registers.

I²C PASS THROUGH

I²C pass-through provides an alternative means to independently address slave devices. The mode enables or

disables I²C bidirectional control channel communication to the remote I²C bus. This option is used to determine

whether or not an I²C instruction is to be transferred over to the remote I²C device. When enabled, the I²C bus

traffic will continue to pass through and will be received by I²C devices downstream. If disabled, I²C commands

will be excluded to the remote I²C device. The pass through function also provides access and communication to

only specific devices on the remote bus. The feature is effective for both Camera mode and Display mode.

SYNCHRONIZING MULTIPLE LINKS

For applications requiring synchronization across multiple links, it is recommended to utilize the General Purpose

Input/Output (GPI/GPO) pins to transmit control signals to synchronize slave peripherals together. To

synchronize the peripherals properly, the system controller needs to provide a sync signal output. Note this form

of synchronization timing relationship has a non-deterministic latency. After the control data is reconstructed from

the birectional control channel, there will be a time variation of the GPI/GPO signals arriving at the different target

devices (between the parallel links). The maximum latency delta (t1) of the GPI/GPO data transmitted across

multiple links is 25 us.

Note: The user must verify that the timing variations between the different links are within their system and timing

specifications.

The maximum time (t1) between the rising edge of GPI/GPO (i.e. sync signal) arriving at SER A and SER B is 25

us.

DES A

GPI[n] Input

DES B

GPI[n] Input

SER A

GPO[n] Output

SER B

GPO[n] Output

t1

Figure 31. GPI/GPO Delta Latency

GENERAL PURPOSE I/O (GPI/GPO)

The DS90UB903Q/904Q has up to 4 GPO and 4 GPI on the Serializer and Deserializer respectively. The

GPI/GPO maximum switching rate is up to 66 kHz for communication between Deserializer GPI to Serializer

GPO.

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AT-SPEED BIST (BISTEN, PASS)

An optional AT SPEED Built in Self Test (BIST) feature supports at speed testing of the high-speed serial and

the bidirectional control channel link. Control pins at the Deserializer are used to enable the BIST test mode and

allow the system to initiate the test and set the duration. A HIGH on PASS pin indicates that all payloads

received during the test were error free during the BIST duration test. A LOW on this pin at the conclusion of the

test indicates that one or more payloads were detected with errors.

The BIST duration is defined by the width of BISTEN. BIST starts when Deserializer LOCK goes HIGH and

BISTEN is set HIGH. BIST ends when BISTEN goes LOW. Any errors detected after the BIST Duration are not

included in PASS logic.

Note: AT-SPEED BIST is only available in the Camera mode and not the Display mode

The following diagram shows how to perform system AT SPEED BIST:

Serializer MODE = 0 and Deserializer MODE = 1

Apply power for Serializer and Deserializer

Normal

Step 1: Enable AT SPEED BIST by placing the

Deserializer in BIST by mode setting BISTEN = H

BIST Wait

Step 4: Place System in

Normal Operating Mode

BISTEN = L

Step 2: Deserializer will setup Serializer and enable BIST

mode through Bidirectional control channel

communication and then reacquire forward channel clock

BIST Start

Step 3: Stop AT SPEED BIST by turning off BIST

mode with BISTEN = L at the Deserializer.

BIST Stop

Figure 32. AT-SPEED BIST System Flow Diagram

Step 1: Place the Deserializer in BIST Mode.

Serializer and Deserializer power supply must be supplied. Enable the AT SPEED BIST mode on the

Deserializer by setting the BISTEN pin High. The 904 GPI[1:0] pins are used to select the PCLK frequency of the

on-chip oscillator for the BIST test on high speed data path.

Table 5. BIST Oscillator Frequency Select

Des GPI[1:0]

Oscillator Source

External PCLK

min (MHz)

typ (MHz)

max (MHz)

00

01

10

11

10

43

Internal

50

25

12.5

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The Deserializer GPI[1:0] set to 00 will bypass the on-chip oscillator and an external oscillator to Serializer PCLK

input is required. This allows the user to operate BIST under different frequencies other than the predefined

ranges.

Step 2: Enable AT SPEED BIST by placing the Serializer into BIST mode.

Deserializer will communicate through the bidirectional control channel to configure Serializer into BIST mode.

Once the BIST mode is set, the Serializer will initiate BIST transmission to the Deserializer.

Wait 10 ms for Deserializer to acquire lock and then monitor the LOCK pin transition from LOW to HIGH. At this

point, AT SPEED BIST is operational and the BIST process has begun. The Serializer will start transfer of an

internally generated PRBS data pattern through the high speed serial link. This pattern traverses across the

interconnecting link to the Deserializer. Check the status of the PASS pin; a HIGH indicates a pass, a LOW

indicates a fail. A fail will stay LOW for ½ a clock cycle. If two or more bits in the serial frame fail, the PASS pin

will toggle ½ clock cycle HIGH and ½ clock cycle low. The user can use the PASS pin to count the number of

fails on the high speed link. In addition, there is a defined SER and DES register that will keep track of the

accumulated error count. The Serializer 903 GPO[0] pin will be assigned as a PASS flag error indicator for the

bidirectional control channel link.

Recovered

Pixel Clock

BISTEN

Case 1: No bit errors

Recovered

Pixel Data

PASS

—BIST“ State

Case 2: Bit error(s)

Recovered

Pixel Data

B

PASS

E

Case 3: Bit error(s) AFTER BIST

Duration

Recovered

Pixel Data

B

—BIST“ State

B = Bad Pixel

PE = Payload Error

BIST Duration

(when BISTEN=H)

BIST Status

(when BISTEN=L)

Figure 33. BIST Timing Diagram

Step 3: Stop at SPEED BIST by turning off BIST mode in the Deserializer to determine Pass/Fail.

To end BIST, the system must pull BISTEN pin of the Deserializer LOW. The BIST duration is fully defined by

the BISTEN width and Deserializer LOCK is HIGH; thus the Bit Error Rate is determined by how long the system

holds BISTEN HIGH.

30

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BIST Duration (s)

f_pixel(MHz)

Pixel

x Total Pixels Transmitted = Total Bits Transmitted

BIST Duration (s) x

=

1 Pixel period (ns) x Total Bits

Bit (Pixel) Error Rate

(for passing BIST)

[Total Bits Transmitted] ^-1

=

[Total Bits Transmitted x Bits/Pixel] ^-1

Figure 34. BIST BER Calculation

Step 4: Place system in Normal Operating Mode by disabling BIST at the Serializer.

Once Step 3 is complete, AT SPEED BIST is over and the Deserializer is out of BIST mode. To fully return to

Normal mode, apply Normal input data into the Serializer.

Any PASS result will remain unless it is changed by a new BIST session or cleared by asserting and releasing

PDB. The default state of PASS after a PDB toggle is HIGH.

It is important to note that AT SPEED BIST will only determine if there is an issue on the link that is not related to

the clock and data recovery of the link (whose status is flagged with LOCK pin).

LVCMOS VDDIO OPTION

1.8V or 3.3V SER Inputs and DES Outputs are user seletable to provide compatibility with 1.8V and 3.3V system

interfaces.

REMOTE WAKE UP (Camera Mode)

After initial power up, the Serializer is in a low-power Standby mode. The Deserializer (controlled by ECU/MCU)

'Remote Wake-up' register allows the Deserializer side to generate a signal across the link to remotely wake-up

the Serializer. Once the Serializer detects the wake-up signal Serializer switches from Standby mode to active

mode. In active mode, the Serializer locks onto PCLK input (if present), otherwise the on-chip oscillator is used

as the input clock source. Note the MCU controller should monitor the Deserializer LOCK pin and confirm LOCK

= H before performing any I²C communication across the link.

For Remote Wake-up to function properly:

•

The chipset needs to be configured in Camera mode: Serializer MODE = 0 and Deserializer MODE = 1

Serializer expects remote wake-up by default at power on.

Configure the control channel driver of the Deserializer to be in remote wake-up mode by setting Deserializer

Register 0x26h = 0xC0h

•

Perform remote wake-up on Serializer by setting Deserializer Register 0x01 b[2] = 1

Return the control channel driver of the Deserializer to the normal operation mode by setting Deserializer

Register 0x26h = 0x00h

•

Configure the control channel driver of the Deserializer to be in normal operation mode by setting Deserializer

Register 0x27h = 0xC0h.

Serializer can also be put into standby mode by programming the Deserializer remote wake-up control register

0x01 b[2] REM_WAKEUP to 0.

POWERDOWN

The SER has a PDB input pin to ENABLE or Powerdown the device. The modes can be controlled by the host

and is used to disable the Link to save power when the remote device is not operational. An auto mode is also

available. In this mode, the PDB pin is tied High and the SER switches over to an internal oscillator when the

PCLK stops or not present. When a PCLK starts again, the SER will then lock to the valid input PCLK and

transmits the data to the DES. In powerdown mode, the high-speed driver outputs are static (High).

The DES has a PDB input pin to ENABLE or Powerdown the device. This pin can be controlled by the system

and is used to disable the DES to save power. An auto mode is also available. In this mode, the PDB pin is tied

High and the DES will enter powerdown when the serial stream stops. When the serial stream starts up again,

the DES will lock to the input stream and assert the LOCK pin and output valid data. In powerdown mode, the

Data and PCLK outputs are set by the OSS_SEL control register.

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POWER UP REQUIREMENTS AND PDB PIN

It is required to delay and release the PDB input signal after VDD (VDDn and VDDIO) power supplies have

settled to the recommended operating voltages. A external RC network can be connected to the PDB pin to

ensure PDB arrives after all the VDD have stabilized.

SIGNAL QUALITY ENHANCERS

Des - Receiver Input Equalization (EQ)

The receiver inputs provided input equalization filter in order to compensate for loss from the media. The level of

equalization is controlled via register setting. Note this function can be observed at the CMLOUTP/N test port

enabled via the control registers.

EMI REDUCTION

Des - Receiver Staggered Output

The Receiver staggered outputs allows for outputs to switch in a random distribution of transitions within a

defined window. Outputs transitions are distributed randomly. This minimizes the number of outputs switching

simultaneously and helps to reduce supply noise. In addition it spreads the noise spectrum out reducing overall

EMI.

Des Spread Spectrum Clocking

The DS90UB904Q parallel data and clock outputs have programmable SSCG ranges from 9 kHz–66 kHz and

±0.5%–±2% from 20 MHz to 43 MHz. The modulation rate and modulation frequency variation of output spread is

controlled through the SSC control registers.

PIXEL CLOCK EDGE SELECT (TRFB/RRFB)

The TRFB/RRFB selects which edge of the Pixel Clock is used. For the SER, this register determines the edge

that the data is latched on. If TRFB register is 1, data is latched on the Rising edge of the PCLK. If TRFB register

is 0, data is latched on the Falling edge of the PCLK. For the DES, this register determines the edge that the

data is strobed on. If RRFB register is 1, data is strobed on the Rising edge of the PCLK. If RRFB register is 0,

data is strobed on the Falling edge of the PCLK.

PCLK

DIN/

ROUT

TRFB/RRFB: 0

TRFB/RRFB: 1

Figure 35. Programmable PCLK Strobe Select

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APPLICATIONS INFORMATION

AC COUPLING

The SER/DES supports only AC-coupled interconnects through an integrated DC balanced decoding scheme.

External AC coupling capacitors must be placed in series in the FPD-Link III signal path as illustrated in

Figure 36.

D

+

OUT

R

+

IN

D

R

D

-

R

IN

-

OUT

Figure 36. AC-Coupled Connection

For high-speed FPD-Link III transmissions, the smallest available package should be used for the AC coupling

capacitor. This will help minimize degradation of signal quality due to package parasitics. The I/O’s require a 100

nF AC coupling capacitors to the line.

TYPICAL APPLICATION CONNECTION

Figure 37 shows a typical connection of the DS90UB903Q Serializer.

DS90UB903Q (SER)

1.8V

VDDIO

VDDT

VDDIO

C4

C3

FB2

FB3

FB1

C12

C8

C13

C9

DIN0

DIN1

DIN2

DIN3

DIN4

DIN5

DIN6

VDDPLL

VDDCML

VDDD

C10

C11

C5

C6

C7

FB4

FB5

DIN7

DIN8

DIN9

DIN10

DIN11

DIN12

DIN13

LVCMOS

Parallel

Bus

C1

C2

Serial

DOUT+

DOUT-

DIN14

DIN15

DIN16

DIN17

DIN18

FPD-Link III

Interface

1.8V

DIN19

DIN20

PCLK

10 kW

LVCMOS

Control

Interface

ID[X]

MODE

PDB

RID

GPO[0]

GPO[1]

GPO[2]

GPO[3]

GPO

Control

Interface

NOTE:

C1 - C2 = 0.1 mF (50 WV)

C3 - C9 = 0.1 mF

C10 - C13 = 4.7 mF

C14 - C15 = >100 pF

RPU = 1 kW to 4.7 kW

RID (see ID[x] Resistor Value Table)

FB1 - FB7: Impedance = 1 kW (@ 100 MHz)

low DC resistance (<1W)

VDDIO

RPU

C15

I2C

Bus

Interface

SCL

SDA

FB6

RES

DAP (GND)

The "Optional" components shown are

provisions to provide higher system noise

immunity and will therefore result in higher

performance.

FB7

C14

Optional

Figure 37. DS90UB903Q Typical Connection Diagram — Pin Control

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Figure 38 shows a typical connection of the DS90UB904Q Deserializer.

DS90UB904Q (DES)

1.8V

VDDIO

VDDD

VDDIO1

VDDIO2

VDDIO3

FB1

C13

C11

C8

C12 C14

FB6

C3

C4

C5

VDDR

C9

FB2

FB3

FB4

VDDSSCG

VDDPLL

VDDCML

C10

ROUT0

ROUT1

ROUT2

ROUT3

ROUT4

ROUT5

ROUT6

C15

C6

C7

FB5

C16

C1

ROUT7

ROUT8

ROUT9

ROUT10

ROUT11

ROUT12

ROUT13

Serial

RIN+

RIN-

LVCMOS

Parallel

Bus

FPD-Link III

Interface

C2

ROUT14

ROUT15

ROUT16

ROUT17

ROUT18

ROUT19

ROUT20

TP_A

TP_B

RES_PIN38

RES_PIN39

LVCMOS

Control

Interface

MODE

PDB

PCLK

GPI[0]

GPI[1]

GPI[2]

GPI[3]

VDDIO

RPU

GPI

Control

Interface

RPU

C18

I2C

Bus

SCL

SDA

FB7

LOCK

PASS

Interface

1.8V

FB8

C17

Optional

NOTE:

C1 - C2 = 0.1 mF (50 WV)

C3 - C12 = 0.1 mF

C13 - C16 = 4.7 mF

C17 - C18 = >100 pF

RPU = 1 kW to 4.7 kW

10 kW

ID[X]

RES_PIN46

DAP (GND)

RID

RID (see ID[x] Resistor Value Table)

FB1 - FB8: Impedance = 1 kW (@ 100 MHz)

low DC resistance (<1W)

The "Optional" components shown are

provisions to provide higher system noise

immunity and will therefore result in higher

performance.

Figure 38. DS90UB904Q Typical Connection Diagram — Pin Control

TRANSMISSION MEDIA

The Ser/Des chipset is intended to be used over a wide variety of balanced cables depending on distance and

signal quality requirements. The Ser/Des employ internal termination providing a clean signaling environment.

The interconnect for FPD-Link III interface should present a differential impedance of 100 Ohms. Use of cables

and connectors that have matched differential impedance will minimize impedance discontinuities. Shielded or

un-shielded cables may be used depending upon the noise environment and application requirements. The

chipset's optimum cable drive performance is achieved at 43 MHz at 10 meters length. The maximum signaling

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rate increases as the cable length decreases. Therefore, the chipset supports 50 MHz at shorter distances. Other

cable parameters that may limit the cable's performance boundaries are: cable attenuation, near-end crosstalk

and pair-to-pair skew. The maximum length of cable that can be used is dependant on the quality of the cable

(gauge, impedance), connector, board (discontinuities, power plane), the electrical environment (e.g. power

stability, ground noise, input clock jitter, PCLK frequency, etc.) and the application environment.

The resulting signal quality at the receiving end of the transmission media may be assessed by monitoring the

differential eye opening of the CMLOUT P/N output. A differential probe should be used to measure across the

termination resistor at the CMLOUT P/N pins.

For obtaining optimal performance, we recommend:

•

Use Shielded Twisted Pair (STP) cable

100Ω differential impedance and 24 AWG (or lower AWG) cable

Low skew, impedance matched

Ground and/or terminate unused conductors

Figure 39 shows the Typical Performance Characteristics demonstrating various lengths and data rates using

Rosenberger HSD and Leoni DACAR 538 Cable.

70

60

50

40

30

20

10

0

1960

1680

1400

1120

840

DS90UB903Q/904Q

560

280

0

5

15

CABLE LENGTH (m)

20

25

10

*Note: Equalization is enabled for cable lengths greater than 7 meters

Figure 39. Rosenberger HSD & Leoni DACAR 538 Cable Performance

PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS

Circuit board layout and stack-up for the Ser/Des devices should be designed to provide low-noise power feed to

the device. Good layout practice will also separate high frequency or high-level inputs and outputs to minimize

unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by

using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane capacitance

for the PCB power system with low-inductance parasitics, which has proven especially effective at high

frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass

capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the

range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the

tantalum capacitors should be at least 5X the power supply voltage being used.

Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per

supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power

entry. This is typically in the 50uF to 100uF range and will smooth low frequency switching noise. It is

recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors

connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external

bypass capacitor will increase the inductance of the path.

A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size

reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of

these external bypass capacitors, usually in the range of 20-30 MHz. To provide effective bypassing, multiple

capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At

high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing

the impedance at high frequency.

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Some devices provide separate power for different portions of the circuit. This is done to isolate switching noise

effects between different sections of the circuit. Separate planes on the PCB are typically not required. Pin

Description tables typically provide guidance on which circuit blocks are connected to which power pin pairs. In

some cases, an external filter many be used to provide clean power to sensitive circuits such as PLLs.

Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the

differential lines to prevent coupling from the LVCMOS lines to the differential lines. Closely-coupled differential

lines of 100 Ohms are typically recommended for differential interconnect. The closely coupled lines help to

ensure that coupled noise will appear as common-mode and thus is rejected by the receivers. The tightly coupled

lines will also radiate less.

Information on the WQFN style package is provided in Application Note: AN-1187 “Leadless Leadframe Package

(LLP) Application Report” (literature number SNOA401).

INTERCONNECT GUIDELINES

See AN-1108 (SNLA008) and AN-905 (SNLA035) for full details.

•

Use 100Ω coupled differential pairs

Use the S/2S/3S rule in spacings

–

S = space between the pair

2S = space between pairs

3S = space to LVCMOS signal

•

Minimize the number of Vias

Use differential connectors when operating above 500Mbps line speed

Maintain balance of the traces

Minimize skew within the pair

Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the Texas

Instruments web site at: www.ti.com/lvds

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Revision History

04/16/2012

•

Added CMLOUT P/N in DS90UB904Q Deserializer Pin Descriptions

Added ESD CDM and ESD MM values

Added 3.3V I/O VOH conditions: IOH = -4 mA

Corrected 3.3V I/O VOL conditions: IOL = +4 mA

Changed NSID DS90UB903/904QSQX to qty 2500

Added “Only used when VDDIOCONTROL = 0” note for UB904 Register 0x03 bit[4] description

Added Register 0x27 BCC in UB904 Register table

Added Register 0x3F CML Output in UB904 Register table

Updated SLAVE CLOCK STRETCHING in Functional Description section

Updated REMOTE WAKE UP (Camera Mode) procedure in Functional Description section

Updated Des - Receiver Input Equalization (EQ) in Functional Description section

Updated TRANSMISSION MEDIA in Applications Information section

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REVISION HISTORY

Changes from Revision D (April 2013) to Revision E

Page

•

Changed layout of National Data Sheet to TI format .......................................................................................................... 37

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PACKAGE MATERIALS INFORMATION

www.ti.com

24-Apr-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

DS90UB903QSQ/NOPB WQFN

DS90UB903QSQE/NOPB WQFN

DS90UB903QSQX/NOPB WQFN

DS90UB904QSQ/NOPB WQFN

DS90UB904QSQE/NOPB WQFN

DS90UB904QSQX/NOPB WQFN

RTA

RHS

40

48

1000

250

330.0

178.0

330.0

178.0

330.0

16.4

6.3

7.3

6.3

7.3

1.5

1.3

12.0

16.0

Q1

2500

1000

250

2500

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

24-Apr-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

DS90UB903QSQ/NOPB

DS90UB903QSQE/NOPB

DS90UB903QSQX/NOPB

DS90UB904QSQ/NOPB

DS90UB904QSQE/NOPB

DS90UB904QSQX/NOPB

WQFN

RTA

RHS

40

48

1000

250

367.0

213.0

367.0

213.0

367.0

191.0

367.0

191.0

367.0

38.0

55.0

38.0

55.0

38.0

2500

1000

250

2500

Pack Materials-Page 2

MECHANICAL DATA

RTA0040A

SQA40A (Rev B)

www.ti.com

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型号：	DS90UB903Q-Q1
厂家：	TEXAS INSTRUMENTS
描述：	具有双向控制通道的 10 - 43MHz 18 位色彩 FPD-Link III 串行器驱动光电二极管线路驱动器或接收器驱动程序和接口
文件：	总45页 (文件大小：1099K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DS90UB903Q-Q1 [TI]

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