DS90UB921-Q1 [TI]

5MHz-96MHz 24 位彩色 FPD-Link III 串行器;


型号：	DS90UB921-Q1
厂家：	TEXAS INSTRUMENTS
描述：	5MHz-96MHz 24 位彩色 FPD-Link III 串行器光电二极管
文件：	总55页 (文件大小：1844K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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DS90UB921-Q1

ZHCSEV0 –MARCH 2016

DS90UB921-Q1 具有双向控制通道的 5MHz 到 96MHz 24 位彩色 FPD-

Link III 串行器

1 特性

3 说明

•

适用于汽车电子应用

DS90UB921-Q1 串行器与 DS90UB922-Q1、

DS90UB926Q-Q1、DS90UB928Q-Q1、DS90UB948-

Q1 或 DS90UB940-Q1 解串器配套使用，可提供完整

的数字接口以实现汽车显示屏和图像传感应用中视频、

音频和控制数据的高速并行传输。

•

具有符合 AEC-Q100 标准的下列结果：

–

器件温度等级 2：-40℃ 至 +105℃ 的环境运行

温度范围

器件人体放电模型 (HBM) 静电放电 (ESD) 分类

等级 ±8kV

该芯片组非常适合 WVGA 和 HD 格式的车载视频显示

系统。DS90UB921-Q1 整合了嵌入式双向控制通道和

低延迟 GPIO 控制。该芯片组将并行接口转换为单对

高速串行化接口。FPD-Link III 串行总线方案支持通过

单个链路实现高速视频数据传输和双向控制通信的全双

工控制。通过单个差分对（或单线）整合视频数据和控

制可减少互连线尺寸和重量，同时还消除了偏差问题并

简化了系统设计。

器件组件充电模式 (CDM) ESD 分类等级 C6

•

支持扩展高清 (1920x720p/60Hz) 数字视频格式

支持 5MHz–96MHz 像素时钟 (PCLK)（STP 模

式）

•

支持 15MHz–96MHz PCLK（同轴模式）

RGB888 + VS、HS 和 DE

并行 LVCMOS 视频输入

允许存在幅值偏差的扩频输入

4 条可选的双向 GPIO 通道

双向控制接口通道接口，可连接到 I²C 兼容串行控

制总线

可选的 I²S 支持

DS90UB921-Q1 串行器内嵌时钟，可通过直流扰频 &

均衡数据有效载荷，并将信号电平转换为高速低压差分

（或单端）信令。最多有 24 个数据位可随视频控制信

号一同串行化。

•

长达 10 米的交流耦合同轴或屏蔽双绞线 (STP) 互

连

低压摆幅信令的使用、数据换序和随机生成以及扩频定

时兼容性最大限度地减少了电磁干扰 (EMI)。

•

通过 1.8V 或 3.3V 兼容 LVCMOS I/O 接口实现

3.3V 单电源运行

来自下行解串器的远程中断被映射至一个本地输出引

脚。

•

具有嵌入式时钟的直流均衡和扰频数据

内部模式生成

器件信息 ⁽¹⁾

低功率模式最大限度地减少了功率耗散

>8kV ISO 10605 静电放电 (ESD) 额定值

部件号

封装

WQFN (48)

封装尺寸（标称值）

DS90UB921-Q1

7.00mm x 7.00mm

2 应用

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

•

汽车用触摸显示屏

汽车导航显示屏

汽车仪表板

VDDIO

(3.3V) (1.8Vor3.3V)

VDD33

VDDIO

(1.8Vor3.3V) (3.3V)

VDD33

R[7:0]

G[7:0]

R[7:0]

G[7:0]

FPD-Link III

1 Coax / AC Coupled

B[7:0]

PCLK

HOST

Graphics

Processor

RGB Display

720p

24-bit color depth

DOUT+

RIN+

RIN-

PCLK

DOUT-

DS90UB921-Q1

Serializer

DS90UB922-Q1

Deserializer

LOCK

PASS

PDB

OSS_SEL

OEN

PDB

I2S AUDIO

(STEREO)

I2S AUDIO

(STEREO)

MODE_SEL

INTB

INTB_IN

MCLK

SCL

SDA

IDx

SCL

SDA

IDx

DAP

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SNLS488

DS90UB921-Q1

ZHCSEV0 –MARCH 2016

www.ti.com.cn

7.4 Device Functional Modes........................................ 24

7.5 Programming .......................................................... 27

7.6 Register Maps ........................................................ 28

Application and Implementation ........................ 40

8.1 Application Information............................................ 40

8.2 AVMUTE Operation ................................................ 40

8.3 Typical Application .................................................. 41

Power Supply Recommendations...................... 45

9.1 Power Up Requirements and PDB Pin................... 45

9.2 CML Interconnect Guidelines.................................. 46

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 6

6.1 Absolute Maximum Ratings ..................................... 6

6.2 ESD Ratings - JEDEC ............................................. 6

6.3 ESD Ratings—IEC and ISO...................................... 6

6.4 Recommended Operating Conditions....................... 6

6.5 Thermal Information.................................................. 7

6.6 DC Electrical Characteristics .................................... 7

6.7 AC Electrical Characteristics..................................... 9

6.8 PCLK Timing Requirements ..................................... 9

6.9 Recommended Timing for the Serial Control Bus .. 10

6.10 Switching Characteristics...................................... 13

6.11 Typical Charateristics ........................................... 14

Detailed Description ............................................ 15

7.1 Overview ................................................................. 15

7.2 Functional Block Diagram ....................................... 15

7.3 Feature Description................................................. 15

10 Layout................................................................... 47

10.1 Layout Guidelines ................................................. 47

10.2 Layout Example .................................................... 48

11 器件和文档支持 ..................................................... 51

11.1 文档支持................................................................ 51

11.2 社区资源................................................................ 51

11.3 商标....................................................................... 51

11.4 静电放电警告......................................................... 51

11.5 Glossary................................................................ 51

12 机械、封装和可订购信息....................................... 51

4 修订历史记录

日期

修订版本

注释

2016 年 3 月

最初发布版本。

DS90UB921-Q1

www.ti.com.cn

ZHCSEV0 –MARCH 2016

5 Pin Configuration and Functions

DS90UB921-Q1

48 Pin WQFN (RHS)

Top View

G2 / DIN10

MODE_SEL

CMF

G3 / DIN11

G4 / DIN12

VDD33

PDB

G5 / DIN13

G6 / DIN14

DOUT+

DOUT-

G7 / DIN15

DS90UB921-Q1

TOP VIEW

RES1

GPO_REG4 / B0 / DIN16

CAPHS12

REM_INTB

FSEL

GPO_REG5 / B1 / DIN17 44

B2 / DIN18

DAP = GND

B3 / DIN19

B4 / DIN20

CAPP12

I2S_CLK

B5 / DIN21

Pin Functions

I/O, TYPE

NUMBER

DESCRIPTION

NAME

LVCMOS PARALLEL INTERFACE - Layout note: for unused LVCMOS input pins, tie to an external pulldown

DIN[23:18],

DIN[15:10],

DIN[7:2] /

R[7:2],

27, 28, 29, 32, 33,

34, 37, 38, 39, 40,

41, 42, 45, 46, 47,

48, 1, 2

I, LVCMOS, Parallel Interface Data Input Pins

G[7:2],

B[7:2]

DIN[1:0],

DIN[9:8],

DIN[17:16] /

R[1:0],

25, 26, 35, 36, 43,

Multi-function Parallel Interface Data Input Pins

I/O, LVCMOS,

DIN0 / R0 can optionally be used as GPIO0 and DIN1 / R1 can optionally be used as

GPIO1

DIN8 / G0 can optionally be used as GPIO2 and DIN9 /G1 can optionally be used as

GPIO3

G[1:0],

B[1:0]

DIN16 / B0 can optionally be used as GPO_REG4 and DIN17 / B1 can optionally be

used as GPO_REG5

DS90UB921-Q1

ZHCSEV0 –MARCH 2016

www.ti.com.cn

Pin Functions (continued)

I/O, TYPE

DESCRIPTION

NAME

NUMBER

I, LVCMOS, Horizontal Sync Input Pin

Video control signal pulse width must be 3 PCLKs or longer to be transmitted when

the Control Signal Filter is enabled. There is no restriction on the minimum transition

pulse when the Control Signal Filter is disabled. The signal is limited to 2 transitions

per 130 PCLKs.

See Video Control Signal Filter.

I, LVCMOS, Vertical Sync Input Pin

PD Video control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse

width is 130 PCLKs.

See Video Control Signal Filter.

I, LVCMOS, Data Enable Input Pin

PD Video control signal pulse width must be 3 PCLKs or longer to be transmitted when

the Control Signal Filter is enabled. There is no restriction on the minimum transition

pulse when the Control Signal Filter is disabled. The signal is limited to 2 transitions

per 130 PCLKs.

See Video Control Signal Filter.

PCLK

I, LVCMOS, Pixel Clock Input Pin. Strobe edge set by TRFB configuration register. See 表 7

PD 0x03[0].

I2S_CLK,

I2S_WC,

I2S_DA

13, 12, 11

Multi-function Digital Audio Interface Data Input Pins

I, LVCMOS,

Leave open if unused

I2S_CLK can optionally be used as GPO_REG8, I2S_WC can optionally be used as

GPO_REG7, and I2S_DA can optionally be used as GPO_REG6.

OPTIONAL PARALLEL INTERFACE - Layout note: for unused interface pins, tie to an external pulldown

GPIO[3:0]

36, 35, 26, 25

Multi-function General Purpose IOs. Available only in 18-bit color mode, and set by MODE_SEL pin

I/O, LVCMOS,

or configuration register. See 表 7 0x0D - 0x0F.

Leave open if unused.

Shared with DIN9, DIN8, DIN1 and DIN0

GPO_REG[

7:4]

12, 11, 44, 43

Multi-function General Purpose Outputs and set by configuration register. See 表 7 0x0F - 0x11.

O, LVCMOS,

Share with I2S_WC, I2S_DA, or DIN17, DIN16.

CONTROL

PDB

I, LVCMOS, Power-down Mode Input Pin

PDB = H, device is enabled (normal operation)

Refer to Power Up Requirements and PDB Pin section.

PDB = L, device is powered down.

When the device is in the powered down state, the Driver Outputs are both HIGH, the

PLL is shutdown, and IDD is minimized. Control Registers are RESET.

MODE_SEL

FSEL

Device Configuration Select. See 表 5.

I, LVCMOS, Frequency Mode Select. Enables Intermediate Frequency mode for coaxial operation.

See Frequency Mode Optimizations.

I²C

IDx

I²C Serial Control Bus Device ID Address Select

External pull-up to VDD33 is required under all conditions, DO NOT FLOAT.

Connect to external pull-up and pull-down resistor to create a voltage divider. See 表

SCL

SDA

I/O, Open

Drain

I²C Clock Input / Output Interface

Must have an external pull-up to VDD33, DO NOT FLOAT.

Recommended pull-up: 4.7kΩ.

I²C Data Input / Output Interface

Must have an external pull-up to VDD33, DO NOT FLOAT.

Recommended pull-up: 4.7kΩ.

I/O, Open

Drain

DS90UB921-Q1

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ZHCSEV0 –MARCH 2016

Pin Functions (continued)

I/O, TYPE

DESCRIPTION

NAME

NUMBER

STATUS - Layout note: for unused interface pins, leave as No Connect

INTB

O, Open Drain Interrupt

INTB = H, normal

INTB = L, Interrupt request

Typically connected with 4.7kΩ to VDDIO.

REM_INTB

O, LVCMOS, Interrupt. Mirrors status of INTB_IN from the remote deserializer. Note: REM_INTB

will be driven LOW until lock is achieved with the downstream deserializer.

REM_INTB = H, normal

REM_INTB = L, interrupt request

FPD-LINK III SERIAL INTERFACE

DOUT+

DOUT-

CMF

O, LVDS

CAP

True Output

The output must be AC-coupled per the typical connection diagram.

Inverting Output

The output must be AC-coupled per the typical connection diagram.

Common Mode Filter.

Typically connected with 0.1µF to GND

(1)

POWER AND GROUND

VDD33

VDDIO

Power

Power to on-chip regulator 3.0 V - 3.6 V. Typically connected with 4.7 uF to GND

LVCMOS I/O Power 1.71 V - 1.89 V OR 3.0 V - 3.6 V. Typically connected with 4.7

uF to GND

GND

DAP

Ground

DAP is the large metal contact at the bottom side, located at the center of the WQFN

package. Connect to the ground plane (GND) with at least 9 vias.

REGULATOR CAPACITOR

CAPHS12,

CAPP12

17, 14

CAP

Decoupling capacitor connection for on-chip regulator. Typically connected with 4.7uF

to GND at each CAP pin.

CAPL12

Decoupling capacitor connection for on-chip regulator. Typically connected with two

4.7uF to GND at this CAP pin.

OTHERS

RES1

GND

Reserved. Tie to Ground.

(1) The VDD (VDD33 and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise.

The definitions below define the functionality of the I/O cells for each pin. I/O TYPE:

•

CAP = Capacitor connection

LVCMOS = LVCMOS pin; Referenced to VDDIO IO supply

I = Input

O = Output

I/O = Input/Output

S = Strap pin. All strap pins have weak internal pull-ups or pull-downs. If the default strap value is needed to

be changed then an external resistor should be used.

•

PD, PU = Weak Internal Pull-Down/Pull-Up

Multi-function pin

DS90UB921-Q1

ZHCSEV0 –MARCH 2016

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

MIN

–0.3

MAX

UNIT

Supply voltage – VDD33

Supply voltage – VDDIO

LVCMOS I/O voltage

VDDIO + 0.3

2.75

Serializer output voltage - DOUT±

Junction temperature

150

°C

Storage temperature, T_stg

–65

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

6.2 ESD Ratings - JEDEC

VALUE

±8000

±1500

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

Charged-device model (CDM), per AEC Q100-011

V_(ESD)

Electrostatic discharge

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 ESD Ratings—IEC and ISO

VALUE

UNIT

IEC, powered-up only contact discharge

(DOUT+, DOUT-)

±8000

±18000

±8000

R_D= 330 Ω, C_S= 150 pF

Electrostatic discharge R_D= 330 Ω, C_S= 150 and 330 pF

R_D= 2 kΩ, C_S= 150 and 330 pF

IEC, powered-up only air-gap discharge

(DOUT+, DOUT-)

ISO10605 contact discharge (DOUT+,

DOUT-)

V_(ESD)

ISO10605 air-gap discharge (DOUT+,

DOUT-)

±18000

±8000

ISO10605 contact discharge (DOUT+,

DOUT-)

ISO10605 air-gap discharge (DOUT+,

DOUT-)

±18000

6.4 Recommended Operating Conditions

MIN

NOM

3.3

1.8

MAX

3.6

1.89

105

UNIT

Supply voltage (VDD33)

LVCMOS supply voltage (VDDIO)

1.71

−40

Operating free-air temperature (T_A)

°C

PCLK frequency, Coax operation, high frequency mode⁽¹⁾

PCLK frequency, Coax operation, intermediate frequency mode⁽¹⁾

PCLK frequency, Coax operation, low frequency mode⁽¹⁾

PCLK frequency, STP operation, high frequency mode⁽¹⁾

PCLK frequency, STP operation, low frequency mode⁽¹⁾

Supply noise -- (DC-50MHz)

MHz

mV_P-P

100

(1) For configuration of cable type and frequency mode, refer to Frequency Mode Optimizations.

DS90UB921-Q1

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ZHCSEV0 –MARCH 2016

6.5 Thermal Information

DS90UB921-Q1

THERMAL METRIC⁽¹⁾

RHS (WQFN)

UNIT

48 PINS

R_θJA

Junction-to-ambient thermal resistance

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

11.7

5.0

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.1

ψ_JB

6.0

R_θJC(bot)

1.7

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.6 DC Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)^(1)(2)(3)

PARAMETER

TEST CONDITIONS

PIN/FREQ.

MIN

TYP

MAX

UNIT

LVCMOS I/O DC SPECIFICATIONS

V_IH

V_IL

High-level input voltage VDDIO = 3 V to 3.6 V

Low-level input voltage VDDIO = 3 V to 3.6 V

VDDIO

0.8

GND

PDB

V_IN= 0 V or

V_IN= VDDIO (3 V to 3.6 V)

I_IN

Input current

–10

±1

VDDIO

0.8

µA

VDDIO = 3 V to 3.6 V

V_IH

High-level input voltage

0.65 ×

VDDIO

VDDIO = 1.71 V to 1.89 V

VDDIO = 3 V to 3.6 V

DIN[23:0], HS,

VS, DE, PCLK,

I2S_CLK,

GND

V_IL

Low-level input voltage

Input current

0.35 ×

VDDIO

VDDIO = 1.71 V to 1.89 V

GND

I2S_WC,

I2S_DA

VDDIO = 3 V to

–10

2.4

±1

µA

3.6 V

V_IN= 0 V or

V_IN= VDDIO

I_IN

VDDIO = 1.71 V

to 1.89 V

VDDIO = 3 V to

3.6 V

VDDIO

0.4

High-level output

voltage

V_OH

I_OH= –4 mA

VDDIO = 1.71 V

to 1.89 V

VDDIO –

0.45

VDDIO = 3 V to

3.6 V

GND

Low-level output

voltage

GPIO[3:0],

GPO_REG[7:4],

REM_INTB

V_OL

I_OH= 4 mA

V_OUT= 0 V

VDDIO = 1.71 V

to 1.89 V

0.35

Output short-circuit

current

I_OS

–50

V_OUT= 0 V or

V_OUT= VDDIO

PDB = L

TRI-STATE output

current

I_OZ

–10

µA

(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as

otherwise modified or specified by the Electrical Characteristics conditions and/or Notes. Typical specifications are estimations only and

are not ensured.

(2) Typical values represent most likely parametric norms at nominal conditions at the time of product characterization and are not ensured.

(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground

except V_ODand ΔV_OD, which are differential voltages.

DS90UB921-Q1

ZHCSEV0 –MARCH 2016

www.ti.com.cn

DC Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)^(1)(2)(3)

PARAMETER

TEST CONDITIONS

PIN/FREQ.

MIN

TYP

MAX

UNIT

FPD-LINK III CML DRIVER DC SPECIFICATIONS

Differential output

V_OD

voltage (DOUT+) –

(DOUT–)

R_L= 100 Ω, see 图 1

700

350

800

1000

mVp-p

Single-ended output

voltage (DOUT+ or

DOUT-)

R_L= 50 Ω

See 图 2

V_OUT

ΔV_OD

V_OS

400

500

Output voltage

unbalance

2.5 –

0.5 ×

V_OD

R_L= 100 Ω

See 图 1

Offset voltage —

single-ended

DOUT±

Offset voltage

unbalanced single-

ended

ΔV_OS

–38

Output short-circuit

current

I_OS

DOUT± = 0 V, PDB = L or H

Internal termination

resistor — single-

ended

R_T

SERIAL CONTROL BUS

0.7 ×

VDD33

V_IH

V_IL

Input high level, I2C

VDD33

Input low-level voltage,

I2C

0.3 ×

VDD33

V_HY

V_OL

Input hysteresis, I2C

> 50

< 5

SDA, SCL

Output Low Level, I2C I_OL= +1.25mA

0.36

V_IN= 0V or

Input Current, I2C

I_IN

–10

µA

V_IN= VDD33

C_IN

Input capacitance, I2C

SUPPLY CURRENT

I_DD1

VDD33 = 3.6V

VDDIO = 3.6V

VDDIO = 1.89V

VDD33 = 3.6V

VDDIO = 3.6V

VDDIO = 1.89V

VDD33 = 3.6V

VDDIO = 3.6V

VDDIO = 1.89V

VDD33 = 3.6V

VDDIO = 3.6V

VDDIO = 1.89V

148

180

μA

Supply Current

(includes load current)

R_L= 100Ω, f = 96MHz

Checker Board Pattern,

See 图 3

I_DDIO1

I_DDS1

I_DDIOS1

I_DDS2

I_DDIOS2

I_DDS3

μA

1.2

Supply Current Remote

Auto Power Down

Mode

0x01[7] = 1, deserializer is powered

down

200

μA

Supply Current Power

Down

PDB = L, All LVCMOS inputs are not

connected (NC) or tied to GND

200

μA

Supply Current Sleep

State

0x01[7] = 1, PCLK is removed.

I_DDIOS3

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ZHCSEV0 –MARCH 2016

6.7 AC Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)^(1)(2)(3)

PARAMETER

GPIO BIT RATE

TEST CONDITIONS

PIN/FREQUENCY

MIN

TYP

MAX

UNIT

Forward channel bit

rate

ƒ = 5 – 96 MHz

GPIO[3:0]

B_RF

See⁽⁴⁾

0.25 × ƒ

Mbps

kbps

STP cable - HFMODE

STP cable - LFMODE

Coax cable - HFMODE,

IFMODE, or LFMODE

B_RB

Back channel bit rate

GPIO[3:0]

kbps

(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as

otherwise modified or specified by the Electrical Characteristics conditions and/or Notes. Typical specifications are estimations only and

are not ensured.

(2) Typical values represent most likely parametric norms at nominal conditions at the time of product characterization and are not ensured.

(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground

except V_ODand ΔV_OD, which are differential voltages.

(4) Specification is ensured by design and is not tested in production.

6.8 PCLK Timing Requirements

over operating free-air temperature range (unless otherwise noted)^(1)(2)(3)

MIN

NOM

MAX

UNIT

PCLK period with STP cable, see⁽⁴⁾

ƒ = 5 to 96 MHz

PCLK period with Coax cable, see⁽⁴⁾

ƒ = 15 to 96 MHz

10.41

200

t_TCP

10.41

66.7

t_CIH

t_CIL

PCLK input high time; pin/frequency: PCLK

PCLK input low time; pin/frequency: PCLK

PCLK input transition time⁽⁴⁾, see 图 4; ƒ = 5 MHz

PCLK input transition time⁽⁴⁾, see 图 4; ƒ = 96 MHz

0.4*T

0.5*T

0.6*T

t_CLKT

0.5

PCLK input jitter, bit error rate ≤ 10^–10

ƒ / 40 < jitter freq < ƒ / 20

0.35

ƒ = 5 to 78 MHz

(4)(5)

Paired with DS90UB926Q-Q1

PCLK input jitter, bit error rate ≤ 10^–10

ƒ / 40 < jitter freq < ƒ / 20

t_IJIT

f = 5 - 85MHz

(4)(5)

Paired with DS90UB928Q-Q1

PCLK input jitter, bit error rate ≤ 10^–10

ƒ / 40 < jitter freq < ƒ / 20

f = 25 - 96MHz

(4)(5)

Paired with DS90UB940-Q1, or DS90UB948-Q1

(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as

otherwise modified or specified by the Electrical Characteristics conditions and/or Notes. Typical specifications are estimations only and

are not ensured.

(2) Typical values represent most likely parametric norms at nominal conditions at the time of product characterization and are not ensured.

(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground

except V_ODand ΔV_OD, which are differential voltages.

(4) Specification is ensured by characterization and is not tested in production.

(5) UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1 / 35 × PCLK). The UI scales with PCLK frequency.

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6.9 Recommended Timing for the Serial Control Bus

Over 3.3-V supply and temperature ranges unless otherwise specified.

MIN

TYP

MAX

100

UNIT

kHz

µs

Standard mode

ƒ_SCL

t_LOW

t_HIGH

SCL clock frequency

SCL low period

Fast mode

400

Standard mode

Fast mode

4.7

1.3

µs

Standard mode

Fast mode

µs

SCL high period

0.6

µs

Hold time for a start or a

repeated start condition,

see 图 10

Standard mode

µs

t_HD;STA

Fast mode

0.6

4.7

0.6

µs

Set-up time for a start or a Standard mode

repeated start condition,

t_SU:STA

Fast mode

see 图 10

Standard mode

Data hold time, see 图 10

Fast mode

0.615

0.56

3.45

0.9

µs

t_HD;DAT

Standard mode

Fast mode

250

100

Data set-up time, see 图

t_SU;DAT

0.56

Set-up time for STOP

condition,

See 图 10

Standard mode

t_SU;STO

Fast mode

0.6

4.7

µs

Bus free time

between STOP and

START,

Standard mode

t_BUF

Fast mode

1.3

µs

See图 10

Standard mode

Fast mode

430

200

1000

300

SCL and SDA rise time,

See 图 10

t_r

Standard mode

Fast mode

SCL and SDA fall time,

See 图 10

t_f

t_sp

Input filter

DOUT+

0.1 mF

Differential probe

Input Impedance û 100

DIN[23:0],

HS,VS,DE,

I2S

SCOPE

BW û 4 GHz

100W

ú 0.5 pF

DOUT-

BW û 3.5 GHz

PCLK

+) - (D

OUT

图 1. Serializer Differential V_ODDC Output

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DOUT+

DOUT-

0.33 mF

0.15 mF

SCOPE

BW û 4 GHz

Input Impedance = 50W

DIN[23:0],

HS,VS,DE,

I2S

50O

PCLK

OUT

ö ^V

图 2. Serializer Single-ended V_OUTDC Output

DDIO

PCLK

GND

DDIO

DIN[n] (odd),

VS, HS

GND

DDIO

DIN[n] (even),

GND

图 3. Checker Board Data Pattern

VDDIO

80%

PCLK

20%

CLKT

图 4. Serializer Input Clock Transition Time

80%

Differential

Signal

diff

= 0V

20%

HLT

LHT

图 5. Serializer CML Output Load and Transition Time

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TCP

DDIO

PCLK

DDIO

DIH

DIS

DDIO

DIN[23:0],

HS,VS,DE

DDIO

Setup

Hold

图 6. Serializer Setup and Hold Times

PDB

1/2 V

DDIO

PCLK

"X"

active

PLD

DOUT

(Diff.)

Driver On

Driver OFF, V

= 0V

图 7. Serializer Lock Time

RGB[7:0],

SYMBOL N

SYMBOL N+1

HS, VS, DE

PCLK

START

BIT

STOP

BIT

START

BIT

STOP

BIT

DOUT±

SYMBOL N

SYMBOL N-1

图 8. Serializer Delay Time

VOD (+)

DOUT

(Diff.)

EYE OPENING

VOD (-)

(1 UI)

BIT

图 9. Serializer CML Output Jitter

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SDA

SCL

BUF

HD;STA

LOW

HD;STA

SU;STA

SU;STO

HIGH

SU;DAT

HD;DAT

STOP START

START

REPEATED

START

图 10. Serial Control Bus Timing Diagram

6.10 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

PIN/FREQ.

MIN

TYP

MAX UNIT

t_LHT

t_HLT

t_DIS

CML Output Low-to-High

Transition Time

DOUT+,

DOUT-

See 图 5

CML Output High-to-Low

Transition Time

Data Input Setup to PCLK

R[7:0],

G[7:0],

B[7:0], HS,

VS, DE,

PCLK

2.0

See 图 6

t_DIH

Data Input Hold from PCLK

(1)

t_PLD

t_SD

See 图 7

See 图 8

f = 5 -

96MHz

Serializer PLL Lock Time

Delay — Latency

131*T

145*T

f = 5 -

96MHz

R_L= 100Ω

f = 96MHz

See 图 9

Output Total Intrinsic Jitter, Jitter

frequency > f/10

DOUT+,

DOUT-

t_TJIT

0.25

0.30

Bit Error Rate ≥10^{-10 (2) (3)}

(1) tPLD is the time required by the device to obtain lock when exiting power-down state with an active PCLK

(2) Specification is ensured by characterization and is not tested in production.

(3) UI – Unit Interval is equivalent to one serialized data bit width 1UI = 1 / (35*PCLK). The UI scales with PCLK frequency.

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6.11 Typical Charateristics

Time (1.0 ns/DIV)

Time (2.0 ns/DIV)

Note: On the rising edge of each clock period, the CML driver outputs

a low Stop bit, high Start bit, and 33 DC-scrambled data bits.

图 11. Serializer CML Driver Output with 96 MHz TX Pixel

Clock

图 12. Serializer CMLOUT Driver Output and 96 MHz

LVCMOS PCLK Input

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7 Detailed Description

7.1 Overview

The DS90UB921-Q1 serializer transmits a 35-bit symbol over a single serial FPD-Link III channel operating up to

3.36 Gbps line rate. The serial stream contains an embedded clock, video control signals and DC-balanced video

data and audio data which enhance signal quality to support AC coupling. The serializer is intended for use with

the DS90UB926Q-Q1, DS90UB928Q-Q1, DS90UB948-Q1, or DS90UB940-Q1 deserializers.

The DS90UB921-Q1 serializer and compatible deserializer incorporate an I²C compatible interface. The I²C

compatible interface allows programming of serializer or deserializer devices from a local host controller. In

addition, the devices incorporate a bidirectional control channel (BCC) that allows communication between

serializer/deserializer as well as remote I²C slave devices.

The bidirectional control channel is implemented via embedded signaling in the high-speed forward channel

(serializer to deserializer) as well as lower speed signaling in the reverse channel (deserializer to serializer).

Through this interface, the BCC provides a mechanism to bridge I²C transactions across the serial link from one

I²C bus to another. The implementation allows for arbitration with other I²C compatible masters at either side of

the serial link.

There are two operating modes available on DS90UB921-Q1, display mode and camera mode. In display mode,

I²C transactions originate from the host controller attached to the serializer and target either the deserializer or an

I²C slave attached to the deserializer. Transactions are detected by the I²C slave in the serializer and forwarded

to the I²C master in the deserializer. Similarly, in camera mode, I²C transactions originate from a controller

attached to the deserializer and target either the serializer or an I²C slave attached to the serializer. Transactions

are detected by the I²C slave in the deserializer and forwarded to the I²C master in the serializer.

7.2 Functional Block Diagram

w9DÜ[!Çhw

CMF

DIN [23:0]

OUT

PCLK

OUT

I2S_CLK

I2S_WC

I2S_DA

PDB

MODE_SEL

INTB

PLL

REM_INTB

SDA

Timing

and

Control

SCL

IDx

DS90UB921-Q1

Serializer

7.3 Feature Description

7.3.1 High Speed Forward Channel Data Transfer

The High Speed Forward Channel (HS_FC) is composed of 35 bits of data containing DIN[23:0] or RGB[7:0] or

YUV data, sync signals, I²C, and I2S audio transmitted from Serializer to Deserializer. 图 13 illustrates the serial

stream per PCLK cycle. This data payload is optimized for signal transmission over an AC coupled link. Data is

randomized, balanced and scrambled.

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Feature Description (接下页)

图 13. FPD-Link III Serial Stream

The device supports clocks in the range of 5 MHz to 96 MHz. The actual line rate is 3.36 Gbps maximum and

525 Mbps Minimum.

7.3.2 Low Speed Back Channel Data Transfer

The Low-Speed Backward Channel (LS_BC) of the DS90UB921-Q1 provides bidirectional communication

between the display and host processor. The information is carried back from the Deserializer to the Serializer

per serial symbol. The back channel control data is transferred over the single serial link along with the high-

speed forward data, DC balance coding and embedded clock information. This architecture provides a backward

path across the serial link together with a high speed forward channel. The back channel contains the I²C, CRC

and 4 bits of standard GPIO information with 3.1 Mbps line rate in Coax mode and low frequency STP mode,

and 4.4Mbps line rate in high frequency STP mode. The back channel data rate is configured automatically when

STP or Coax is selected (see Frequency Mode Optimizations).

7.3.3 Common Mode Filter Pin (CMF)

The serializer provides access to the center tap of the internal termination. A capacitor must be placed on this pin

for additional common-mode filtering of the differential pair. This can be useful in high noise environments for

additional noise rejection capability. A 0.1 μF capacitor must be connected to this pin to Ground.

7.3.4 Video Control Signal Filter

When operating the devices in Normal Mode, the Video Control Signals (DE, HS, VS) have the following

restrictions:

•

Normal Mode with Control Signal Filter Enabled: DE and HS — Only 2 transitions per 130 clock cycles are

transmitted, the transition pulse must be 3 PCLK or longer.

Normal Mode with Control Signal Filter Disabled: DE and HS — Only 2 transitions per 130 clock cycles are

transmitted, no restriction on minimum transition pulse.

VS — Only 1 transition per 130 clock cycles are transmitted, minimum pulse width is 130 clock cycles.

Video Control Signals are defined as low frequency signals with limited transitions. Glitches of a control signal

can cause a visual display error. This feature allows for the chipset to validate and filter out any high frequency

noise on the control signals. See 图 14.

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Feature Description (接下页)

PCLK

HS/VS/DE

Latency

PCLK

OUT

Pulses 1 or 2

PCLKs wide

HS/VS/DE

OUT

Filetered OUT

图 14. Video Control Signal Filter Waveform

7.3.5 EMI Reduction Features

7.3.5.1 Input SSC Tolerance (SSCT)

The DS90UB921-Q1 serializer is capable of tracking a triangular input spread spectrum clocking (SSC) profile up

to ±2.5% amplitude deviations (center spread), up to 35 kHz modulation at 5–96 MHz, from a host source.

7.3.6 LVCMOS VDDIO Option

1.8 V or 3.3 V Inputs and Outputs are powered from a separate VDDIO supply to offer compatibility with external

system interface signals.

注

When configuring the VDDIO power supplies, all the single-ended data and control input

pins for device need to scale together with the same operating VDDIO levels.

7.3.7 Power Down (PDB)

The Serializer has a PDB input pin to ENABLE or POWER DOWN the device. This pin can be controlled by the

host or through the VDDIO, where VDDIO = 3.0V to 3.6V or VDD33. To save power disable the link when the

display is not needed (PDB = LOW). When the pin is driven by the host, make sure to release it after VDD33 and

VDDIO have reached final levels; no external components are required. In the case of driven by the VDDIO =

3.0V to 3.6V or VDD33 directly, a 10 kohm resistor to the VDDIO = 3.0V to 3.6V or VDD33 , and a >10uF

capacitor to the ground are required (See 图 26).

7.3.8 Remote Auto Power-Down Mode

The DS90UB921-Q1 serializer features a Remote Auto Power Down mode. This feature is enabled and disabled

through the register bit 0x01[7] (表 7). When the back channel is not detected, either due to an idle or powered-

down deserializer, the serializer enters remote auto power down mode. Power dissipation of the serializer is

significantly reduced in this mode. The serializer automatically attempts to resume normal operation upon

detection of an active back channel from the deserializer. To complete the wake-up process and reactivate

forward channel operation, the remote power-down feature must be disabled by either a local I²C host, or by an

auto-ACK I²C transaction from a remote I²C host located at the deserializer. The Remote Auto Power Down

Sleep/Wake cycle is shown below in 图 15:

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Feature Description (接下页)

Enable

Set reg_0x01[7]=1

Back Channel IDLE

Remote Auto Power

Down Enabled

Forward-channel

OFF

Normal Operation

Sleep

Disable

Back Channel ACTIVE

Set reg_0x01[7]=0

图 15. Remote Auto Power Down Sleep/Wake Cycle

To resume normal operation, the Remote Auto Power Down feature must be disabled in the device control

remote I²C controller located at the deserializer, perform the following procedure to complete the wake-up

process:

1. Power up remote deserializer (back channel must be active)

2. Enable I²C PASS-THROUGH ALL by setting deserializer register reg_0x05[7]=1

3. Enable I²C AUTO ACK by setting deserializer register reg_0x03[2]=1

4. Disable Remote Auto Power Down by setting serializer register reg_0x01[7]=0

5. Disable I²C AUTO ACK by setting deserializer register reg_0x03[2]=0

6. Disable I²C PASS-THROUGH ALL by setting deserializer register reg_0x05[7]=0

7.3.9 Input PCLK Loss Detect

The serializer can be programmed to enter a low power SLEEP state when the input clock (PCLK) is lost. This is

done via register 0x03[1] (see 表 7). A clock loss condition is detected when PCLK drops below approximately

1MHz. When a PCLK is detected again, the serializer will then lock to the incoming PCLK. Note – when PCLK is

lost, the Serial Control Bus Registers values are still RETAINED.

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Feature Description (接下页)

7.3.10 Serial Link Fault Detect

The serial link fault detection is able to detect any of following seven (7) conditions:

1. cable open

2. “+” to “-“ short

3. “+” short to GND

4. “-“ short to GND

5. “+” short to battery

6. “-“ short to battery

7. Cable is linked correctly

If any one of the fault conditions (first 6 conditions above) occurs, The Link Detect Status is 0 (cable is not

detected) on bit 0 of address 0x0C 表 7.

7.3.11 Pixel Clock Edge Select (TRFB)

The TRFB control register bit selects which edge of the Pixel Clock is used. For the serializer, this pin determines

the edge that the data is latched on. If TRFB is HIGH (‘1’), data is latched on the Rising edge of the PCLK. If

TRFB is LOW (‘0’), data is latched on the Falling edge of the PCLK.

7.3.12 Frequency Mode Optimizations

HFMODE, LFMODE, and IFMODE are set through a combination of the FSEL pin and MODE_SEL pin, with

Frequency Mode (LFMODE), Intermediate Frequency mode (IFMODE), or High Frequency mode (HFMODE).

See 表 1 for details on how each mode is enabled.

表 1. HFMODE / LFMODE / IFMODE Configuration Table

FSEL (pin 15, or

ALTERNATE

MODE

PCLK RANGE for COAX

PCLK RANGE for STP

FREQUENCY (set by

MODE_SEL pin, or

HFMODE

IFMODE

LFMODE

N/A

15 - 96 MHz

N/A

48 - 96 MHz

24 - 48 MHz

15 - 24 MHz

N/A

5 - 15 MHz

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7.3.13 Interrupt Pins – Funtional Description and Usage (INTB, REM_INTB)

The REM_INTB pin mirrors the status of INTB_IN from the remote deserializer. Any change in INTB_IN status of

the remote device will be reflected at the REM_INTB output of the serializer. REM_INTB will remain LOW until

lock is achieved with the downstream deserializer. Alternately, the INTB pin can be set to trigger on remote

interrupts by following the steps below.

1. On DS90UB921-Q1, read register 0xC7.

2. On DS90UB921-Q1, set register 0xC6[5] = 1 and 0xC6[0] = 1

3. Deserializer INTB_IN is set LOW by some downstream device.

4. DS90UB921-Q1 serializer pulls INTB (pin 31) LOW. The signal is active low, so a LOW indicates an interrupt

condition.

5. External controller detects INTB = LOW; to determine interrupt source, read ISR register 0xC7.

6. A read to ISR will clear the interrupt at the DS90UB921-Q1, releasing INTB.

7. The external controller typically must then access the remote device to determine downstream interrupt

source and clear the interrupt driving INTB_IN. This would be when the downstream device releases the

INTB_IN on the deserializer. The system is now ready to return to step (1) at next falling edge of INTB_IN.

If using the REM_INTB pin instead of INTB for remote interrupts, the IS_RX_INT bit (0xC6[5]) of the serializer's

ICR register must be set low (default) masking remote interrupts to the INTB pin.

7.3.14 Internal Pattern Generation

The DS90UB921-Q1 serializer supports the internal pattern generation feature. It allows basic testing and

debugging of an integrated panel through the FPD-Link III output stream. The test patterns are simple and

repetitive and allow for a quick visual verification of panel operation. As long as the device is not in power down

mode, the test pattern will be displayed even if no parallel input is applied. If no PCLK is received, the test

pattern can be configured to use a programmed oscillator frequency. For detailed information, refer to Application

Note AN-2198 (SNLA132).

7.3.15 GPIO[3:0] and GPO_REG[7:4]

In 18-bit RGB operation mode, the optional R[1:0] and G[1:0] of the DS90UB921-Q1 can be used as the general

purpose IOs GPIO[3:0] in either forward channel (Inputs) or back channel (Outputs) applications.

7.3.15.1 GPIO[3:0] Enable Sequence

See 表 2 for the GPIO enable sequencing.

Step 1: Enable the 18-bit mode either through the configuration register bit 表 7 on DS90UB921-Q1 only. The

deserializer is automatically configured as in the 18-bit mode.

Step 2: To enable GPIO3 forward channel, write 0x03 to address 0x0F on DS90UB921-Q1, then write 0x05 to

address 0x1F on the deserializer.

表 2. GPIO Enable Sequencing Table

DESCRIPTION

DEVICE

FORWARD CHANNEL

0x12 = 0x04

BACK CHANNEL

0x12 = 0x04

Enable 18-bit

mode

DS90UB921-Q1

DS90UB926Q-Q1

DS90UB921-Q1

DS90UB926Q-Q1

DS90UB921-Q1

DS90UB926Q-Q1

DS90UB921-Q1

DS90UB926Q-Q1

DS90UB921-Q1

DS90UB926Q-Q1

Auto Load from DS90UB921-Q1

0x0F = 0x03

Auto Load from DS90UB921-Q1

0x0F = 0x05

GPIO3

GPIO2

GPIO1

GPIO0

0x1F = 0x05

0x1F = 0x03

0x0E = 0x30

0x0E = 0x50

0x1E = 0x50

0x1E = 0x30

0x0E = 0x03

0x0E = 0x05

0x1E = 0x05

0x1E = 0x03

0x0D = 0x93

0x0D = 0x95

0x1D = 0x95

0x1D = 0x93

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Note: GPO_REG4 of the DS90UB921-Q1 can be used as a forward channel GPIO, outputting on GPIO0 of

DS90UB928Q-Q1. This is configured as follows:

•

Set DS90UB921-Q1 in 18-bit mode by register 0x12[2] = 1.

Set DS90UB928Q-Q1 register 0x1D[0] = 1 and 0x1D[2] = 1; this enables GPIO0 of DS90UB928Q-Q1 as an

output.

•

Set DS90UB921-Q1 register 0x0F[4] = 1 and 0x0F[5] = 1; this enables GPO_REG4 of DS90UB921-Q1 as an

input.

Similarly GPO_REG5 of DS90UB921-Q1 can output to GPIO1 of DS90UB928Q-Q1:

•

Set DS90UB921-Q1 in 18-bit mode by register 0x12[2] = 1.

Set DS90UB928Q-Q1 register 0x1E[0] = 1 and 0x1E[2] = 1; this enables GPIO1 of DS90UB928Q-Q1 as an

output.

•

Set DS90UB921-Q1 register 0x10[0] = 1 and 0x10[1] = 1; this enables GPO_REG5 DS90UB921-Q1 as an

input.

7.3.15.2 GPO_REG[7:4] Enable Sequence

GPO_REG[7:4] are the outputs only pins. They must be programmed through the local register bits. See 表 3 for

the GPO_REG enable sequencing.

Step 1: Enable the 18-bit mode either through the configuration register bit 表 7 on DS90UB921-Q1 only. The

deserializer is automatically configured as in the 18-bit mode.

Step 2: To enable GPO_REG7 outputs an “1”, write 0x09 to address 0x11 on DS90UB921-Q1.

表 3. GPO_REG Enable Sequencing Table

DESCRIPTION

Enable 18-bit mode

GPO_REG7

DEVICE

LOCAL ACCESS

0x12 = 0x04

0x11 = 0x09

0x11 = 0x01

0x10 = 0x90

0x10 = 0x10

0x10 = 0x09

0x10 = 0x01

0x0F = 0x90

0x0F = 0x10

LOCAL OUTPUT

DS90UB921-Q1

“1”

“0”

“1”

“0”

“1”

“0”

“1”

“0”

GPO_REG6

GPO_REG5

GPO_REG4

DS90UB921-Q1

7.3.16 I2S Transmitting

In normal 24-bit RGB operation mode, the DS90UB921-Q1 supports 3 bits of I2S. They are I2S_CLK, I2S_WC

and I2S_DA. The optionally packetized audio information can be transmitted during the video blanking (data

island transport) or during active video (forward channel frame transport). Note: The bit rates of any I2S bits must

maintain one fourth of the PCLK rate. 表 4 covers the range of I2S sample rates.

表 4. Audio Interface Frequencies

SAMPLE RATE (kHz)

I2S DATA WORD SIZE (BITS)

I2S CLK (MHz)

1.024

44.1

1.411

1.536

3.072

192

6.144

1.536

44.1

2.117

2.304

4.608

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表 4. Audio Interface Frequencies (接下页)

SAMPLE RATE (kHz)

I2S DATA WORD SIZE (BITS)

I2S CLK (MHz)

9.216

192

2.048

44.1

2.822

3.072

6.144

192

12.288

7.3.17 Built In Self Test (BIST)

An optional At-Speed Built In Self Test (BIST) feature supports the testing of the high speed serial link and the

low- speed back channel. This is useful in the prototype stage, equipment production, in-system test and also for

system diagnostics.

7.3.17.1 BIST Configuration and Status

The BIST mode is enabled at the deseralizer by the Pin select (BISTEN and BISTC) or configuration register (表

7) through the deserializer. When LFMODE = 0, the pin based configuration defaults to external PCLK or 33

MHz internal Oscillator clock (OSC) frequency. In the absence of PCLK, the user can select the desired OSC

frequency (default 33 MHz or 25MHz) through the register bit. When LFMODE = 1, the pin based configuration

defaults to external PCLK or 12.5MHz MHz internal Oscillator clock (OSC) frequency.

When BISTEN of the deserializer is high, the BIST mode enable information is sent to the serializer through the

Back Channel. The serializer outputs a test pattern and drives the link at speed. The deserializer detects the test

pattern and monitors it for errors. The PASS output pin toggles to flag any payloads that are received with 1 to

35 bit errors.

The BIST status is monitored real time on PASS pin. The result of the test is held on the PASS output until reset

(new BIST test or Power Down). A high on PASS indicates NO ERRORS were detected. A Low on PASS

indicates one or more errors were detected. The duration of the test is controlled by the pulse width applied to

the deserializer BISTEN pin. This BIST feature also contains a Link Error Count and a Lock Status. If the

connection of the serial link is broken, then the link error count is shown in the register. When the PLL of the

deserializer is locked or unlocked, the lock status can be read in the register. See 表 7.

7.3.17.1.1 Sample BIST Sequence

See 图 16 for the BIST mode flow diagram.

Step 1: BIST Mode is enabled via the BISTEN pin of the deserializer. The desired clock source is selected

through BISTC pin.

Step 2: The DS90UB921-Q1 serializer is woken up through the back channel if it is not already on. The all zero

pattern on the data pins is sent through the FPD-Link III to the deserializer. Once the serializer and the

deserializer are in BIST mode and the deserializer acquires Lock, the PASS pin of the deserializer goes high and

BIST starts checking the data stream. If an error in the payload (1 to 35) is detected, the PASS pin will switch low

for one half of the clock period. During the BIST test, the PASS output can be monitored and counted to

determine the payload error rate.

Step 3: To Stop the BIST mode, the deserializer BISTEN pin is set Low. The deserializer stops checking the

data. The final test result is held on the PASS pin. If the test ran error free, the PASS output will be High. If there

was one or more errors detected, the PASS output will be Low. The PASS output state is held until a new BIST

is run, the device is RESET, or Powered Down. The BIST duration is user controlled by the duration of the

BISTEN signal.

Step 4: The Link returns to normal operation after the deserializer BISTEN pin is low. 图 17 shows the waveform

diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple errors. In

most cases it is difficult to generate errors due to the robustness of the link (differential data transmission etc.),

thus they may be introduced by greatly extending the cable length, faulting the interconnect, reducing signal

condition enhancements (Rx Equalization).

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Normal

Step 1: DES in BIST

BIST

Wait

Step 2: Wait, SER in BIST

BIST

start

Step 3: DES in Normal Mode -

check PASS

BIST

stop

Step 4: DES/SER in Normal

图 16. Bist Mode Flow Diagram

7.3.17.2 Forward Channel And Back Channel Error Checking

While in BIST mode, the serializer stops sampling RGB input pins and switches over to an internal all-zero

pattern. The internal all-zeroes pattern goes through scrambler, dc-balancing etc. and goes over the serial link to

the deserializer. The deserializer on locking to the serial stream compares the recovered serial stream with all-

zeroes and records any errors in status registers and dynamically indicates the status on PASS pin. The

deserializer then outputs a simultaneous switching output (SSO) pattern on the RGB output pins.

The back-channel data is checked for CRC errors once the serializer locks onto back-channel serial stream as

indicated by link detect status (register bit 0x0C[0]). The CRC errors are recorded in an 8-bit register. The

functional mode CRC register starts recording the CRC errors. The BIST mode CRC error register is active in

BIST mode only and keeps the record of last BIST run until cleared or enters BIST mode again.

BISTEN

(DES)

PCLK

(RFB = L)

ROUT[23:0]

HS, VS, DE

DATA

(internal)

PASS

Prior Result

PASS

FAIL

X = bit error(s)

DATA

(internal)

PASS

BIST

Result

Held

Normal

SSO

Normal

BIST Test

BIST Duration

图 17. Bist Waveforms

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7.4 Device Functional Modes

7.4.1 Configuration Select (MODE_SEL)

Configuration of the device may be done via the MODE_SEL input pin, or via the configuration register bit. A pull-

up resistor and a pull-down resistor of suggested values may be used to set the voltage ratio of the MODE_SEL

input (V_R4) and VDD33 to select one of the other 7 possible selected modes. The voltage range in between the

Minimum and Maximum V_R4must be adhered even when taking resistor tolerances into account. The 1%

suggested resistors meet this for all cases, but others that also meet the desired voltage range are also

acceptable. See 图 18 and 表 5.

DD33

MODE_SEL

SER

图 18. MODE_SEL Connection Diagram

表 5. Configuration Select (MODE_SEL)

MINIMUM

V_R4(V)⁽¹⁾

MAXIMUM

V_R4(V)⁽¹⁾

SUGGESTED

RESISTOR R3

kΩ (1% tol)

SUGGESTED

RESISTOR R4

kΩ (1% tol)

ALTERNATE

FREQUENCY

REPEATER

18–BIT MODE

0.000

0.530

0.725

0.930

1.165

1.480

1.750

0.150

0.596

0.800

1.012

1.284

1.599

1.905

Open

90.9

93.1

71.5

68.1

82.5

73.2

40.2 or Any

18.7

28.0

30.1

40.2

71.5

90.9

Alternate Frequency:

See Frequency Mode Optimizations

Repeater:

L = Repeater OFF (Default)

H = Repeater ON

18-bit Mode:

L = Normal 24-bit RGB Mode (Default)

H = 18-bit RGB Mode. Note: use of GPIO(s) on unused inputs must be enabled by register.

7.4.2 Repeater Application

The DS90UB921-Q1 and DS90UB926Q-Q1 can be configured to extend data transmission over multiple links to

multiple display devices. Setting the devices into repeater mode provides a mechanism for transmitting to all

receivers in the system.

7.4.2.1 Repeater Configuration

In the repeater application, in this document, the DS90UB921-Q1 is referred to as the Transmitter or transmit

port (TX), and the DS90UB926Q-Q1 is referred to as the Receiver (RX). 图 19 shows the maximum configuration

supported for Repeater implementations using the DS90UB921-Q1 (TX) and DS90UB926Q-Q1 (RX). Two levels

of Repeaters are supported with a maximum of three Transmitters per Receiver.

(1) Voltage indicated assumes nominal VDD33.

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Device Functional Modes (接下页)

1:3 Repeater

Display

Source

Display

1:3 Repeater

Display

1:3 Repeater

Display

图 19. Maximum Repeater Application

In a repeater application, the I2C interface at each TX and RX may be configured to transparently pass I2C

communications upstream or downstream to any I2C device within the system. This includes a mechanism for

assigning alternate IDs (Slave Aliases) to downstream devices in the case of duplicate addresses.

At each repeater node, the parallel LVCMOS interface fans out to up to three serializer devices, providing parallel

RGB video data, HS/VS/DE control signals and, optionally, packetized audio data (transported during video

blanking intervals). Alternatively, the I2S audio interface may be used to transport digital audio data between

receiver and transmitters in place of packetized audio. All audio and video data is transmitted at the output of the

Receiver and is received by the Transmitter.

图 20 provides more detailed block diagram of a 1:2 repeater configuration.

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Device Functional Modes (接下页)

DS90UB921-Q1

Transmitter

downstream

Receiver

I2C

Slave

I2C

Master

Repeater

upstream

Transmitter

Parallel

LVCMOS

DS90UB921-Q1

Transmitter

DS90UB926-Q1

Receiver

I2S Audio

downstream

Receiver

I2C

Slave

Repeater

FPD-Link III interfaces

图 20. 1:2 Repeater Configuration

7.4.2.2 Repeater Connections

The Repeater requires the following connections between the Receiver and each Transmitter 图 21.

1. Video Data – Connect PCLK, RGB and control signals (DE, VS, HS).

2. I2C – Connect SCL and SDA signals. Both signals should be pulled up to VDD33 with 4.7 kΩ resistors.

3. Audio – Connect I2S_CLK, I2S_WC, and I2S_DA signals.

4. IDx pin – Each Transmitter and Receiver must have an unique I2C address.

5. MODE_SEL pin – All Transmitter and Receiver must be set into the Repeater Mode.

6. Interrupt pin – Connect DS90UB926Q-Q1 INTB_IN pin to DS90UB921-Q1 INTB pin. The signal must be

pulled up to VDDIO.

5{90Ü.926-v1

5{90Ü.921-v1

RGB[7:0) / ROUT[23:0]

DIN[23:0] / RGB[7:0]

I2S_CLK

I2S_WC

I2S_DA

I2S_CLK

I2S_WC

I2S_DA

VDD33

hptionꢁl

VDDIO

ah59_{9[

hptionꢁl

INTB_IN

INTB

VDD33

L5ꢀx]

SDA

SCL

图 21. Repeater Connection Diagram

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7.5 Programming

The DS90UB921-Q1 is configured by the use of a serial control bus that is I2C protocol compatible. Multiple

serializer devices may share the serial control bus since 9 device addresses are supported. Device address is

set via R₁and R₂values on IDx pin. See 图 22.

The serial control bus consists of two signals and a configuration pin. The SCL is a Serial Bus Clock Input /

Output. The SDA is the Serial Bus Data Input / Output signal. Both SCL and SDA signals require an external

pull-up resistor to VDD33. For most applications a 4.7 k pull-up resistor to VDD33 may be used. The resistor

value may be adjusted for capacitive loading and data rate requirements. The signals are either pulled High, or

driven Low.

V_DD33

R₁

V_DD33

VR2

IDx

4.7k

R₂

HOST

DS90UB921-Q1

Slave

SCL

SDA

SCL

SDA

To other

Devices

图 22. Serial Control Bus Connection

The configuration pin is the IDx pin. This pin sets one of 8 possible device addresses. A pull-up resistor and a

pull-down resistor of suggested values may be used to set the voltage ratio of the IDx input (V_R2) and VDD33 to

select one of the other 8 possible addresses. The voltage range in between the Minimum and Maximum V_R2

must be adhered even when taking resistor tolerances into account. The 1% suggested resistors meet this for all

cases, but others that also meet the desired voltage range are also acceptable. See 表 6.

表 6. Serial Control Bus Addresses for IDx

Maximum Voltage

Minimum Voltage

V_R2(V)⁽¹⁾

Suggested Resistor Suggested Resistor

Address 8'b

Appended

V_R2

Address 7'b

R1 kΩ (1% tol)

R2 kΩ (1% tol)

(V)⁽¹⁾

0.000

0.535

0.723

0.947

1.203

1.493

1.789

2.469

0.150

0.578

0.775

0.995

1.258

1.565

1.855

2.515

Open

86.6

90.9

71.5

84.5

54.9

78.7

30.9

40.2 or Any

17.4

0x0C

0x0E

0x10

0x12

0x14

0x16

0x18

0x1A

0x18

0x1C

0x20

0x24

0x28

0x2C

0x30

0x34

26.7

30.1

49.9

47.5

97.6

95.3

(1) Voltage indicated assumes nominal VDD33.

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The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when

SCL transitions Low while SDA is High. A STOP occurs when SDA transition High while SCL is also HIGH. See

图 23.

SDA

SCL

START condition, or

STOP condition

START repeat condition

图 23. Start and Stop Conditions

To communicate with a remote device, the host controller (master) sends the slave address and listens for a

response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is

addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't

match a device's slave address, it Not-acknowledges (NACKs) the master by letting SDA be pulled High. ACKs

also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after

every data byte is successfully received. When the master is reading data, the master ACKs after every data

byte is received to let the slave know it wants to receive another data byte. When the master wants to stop

reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus

begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop

condition. A READ is shown in 图 24 and a WRITE is shown in 图 25.

If the Serial Bus is not required, the three pins may be left open (NC).

Slave Address

Data

图 24. Serial Control Bus — Read

Slave Address

Data

图 25. Serial Control Bus — Write

7.6 Register Maps

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表 7. Serial Control Bus Registers

ADD

(dec)

ADD

(hex)

DEFAULT

FUNCTION

(hex)

BIT(S)

TYPE

DESCRIPTION

0x00

I2C Device ID

7:1

Device ID

ID Setting

7–bit address of Serializer

I2C ID Setting

1: Register I2C Device ID (Overrides IDx pin)

0: Device ID is from IDx pin

0x01

Reset

0x00

Soft Sleep

1: Enable power down when no Bidirectional Control Channel Link detected.

0: Do not power down when no Bidirectional Control Channel Link detected.

6:2

Reserved

Digital RESET1 Reset the entire digital block including registers

This bit is self-clearing.

1: Reset

0: Normal operation

Digital RESET0 Reset the entire digital block except registers

This bit is self-clearing

1: Reset

0: Normal operation

0x03

Configuration [0]

0xD2

Back channel

CRC Checker

Enable

Back Channel Check Enable

1: Enable

0: Disable

Reserved

I2C Remote

Write Auto

Acknowledge

Automatically Acknowledge I2C Remote Write When enabled, I2C writes to

the Deserializer (or any remote I2C Slave, if I2C PASS ALL is enabled) are

immediately acknowledged without waiting for the Deserializer to

acknowledge the write. This allows higher throughput on the I2C bus

1: Enable

0: Disable

Filter Enable

HS, VS, DE two clock filter When enabled, pulses less than two full PCLK

cycles on the DE, HS, and VS inputs will be rejected

1: Filtering enable

0: Filtering disable

I2C Pass-

through

I2C Pass-Through Mode

1: Pass-Through Enabled

0: Pass-Through Disabled

Reserved

PCLK Auto

TRFB

Switch over to internal OSC in the absence of PCLK

1: Enable auto-switch

0: Disable auto-switch

Pixel Clock Edge Select

1: Parallel Interface Data is strobed on the Rising Clock Edge.

0: Parallel Interface Data is strobed on the Falling Clock Edge.

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表 7. Serial Control Bus Registers (接下页)

ADD

(dec)

ADD

(hex)

DEFAULT

(hex)

BIT(S)

TYPE

FUNCTION

DESCRIPTION

0x04

Configuration [1]

0x80

Failsafe State

Input Failsafe State

1: Failsafe to Low

0: Failsafe to High

Reserved

CRC Error Reset Clear back channel CRC Error Counters

This bit is NOT self-clearing

1: Clear Counters

0: Normal Operation

RGB

1: Gate RGB data with DE

DE Gate

0: Pass RGB data independent of DE (default)

This bit is recommended to be set to 1 to avoid unintentionally entering

AVMUTE mode. See AVMUTE Operation.

3:2

Reserved

ALTERNATE

FREQUENCY

select by pin or

Frequency range is set by MODE_SEL pin or register, in conjunction with

FSEL pin or register 0x35[7:6]. See Frequency Mode Optimizations.

1: Frequency range is set by register. Use register bit reg_0x04[0] to set

Alternate Frequency.

0: Frequency range is set by MODE_SEL pin.

ALTERNATE

FREQUENCY

Override Value

Frequency range select, in conjunction with FSEL pin or register 0x35[7:6].

See Frequency Mode Optimizations.

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表 7. Serial Control Bus Registers (接下页)

ADD

(dec)

ADD

(hex)

DEFAULT

(hex)

BIT(S)

TYPE

FUNCTION

DESCRIPTION

0x05

I2C Control

7:5

4:3

0x00

Reserved

SDA Output

Delay

SDA output delay

Configures output delay on the SDA output. Setting this value will increase

output delay in units of 40ns.

Nominal output delay values for SCL to SDA are

00: 240ns

01: 280ns

10: 320ns

11: 360ns

Local Write

Disable

Disable remote writes to local registers

Setting the bit to a 1 prevents remote writes to local device registers from

across the control channel. It prevents writes to the Serializer registers from

an I2C master attached to the Deserializer.

Setting this bit does not affect remote access to I2C slaves at the Serializer

I2C Bus Timer

Speedup

Speed up I2C bus watchdog timer

1: Watchdog timer expires after ~50 ms.

0: Watchdog Timer expires after ~1 s

I2C Bus timer

Disable

Disable I2C bus watchdog timer

When the I2C watchdog timer may be used to detect when the I2C bus is

free or hung up following an invalid termination of a transaction.

If SDA is high and no signalling occurs for ~1 s, the I2C bus assumes to be

free. If SDA is low and no signaling occurs, the device attempts to clear the

bus by driving 9 clocks on SCL

0x06

DES ID

7:1

0x00

DES Device ID

7-bit Deserializer Device ID

Configures the I2C Slave ID of the remote Deserializer. A value of 0 in this

field disables I2C access to the remote Deserializer. This field is

automatically configured by the Bidirectional Control Channel once RX Lock

has been detected. Software may overwrite this value, but should also

assert the FREEZE DEVICE ID bit to prevent overwriting by the

Bidirectional Control Channel.

Device ID

Frozen

Freeze Deserializer Device ID

Prevents autoloading of the Deserializer Device ID by the Bidirectional

Control Channel. The ID will be frozen at the value written.

0x07

Slave ID

7:1

0x00

Slave Device ID 7-bit Remote Slave Device ID

Configures the physical I2C address of the remote I2C Slave device

attached to the remote Deserializer. If an I2C transaction is addressed to

the Slave Device Alias ID, the transaction will be remapped to this address

before passing the transaction across the Bidirectional Control Channel to

the Deserializer

Reserved

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表 7. Serial Control Bus Registers (接下页)

ADD

(dec)

ADD

(hex)

DEFAULT

(hex)

BIT(S)

TYPE

FUNCTION

DESCRIPTION

0x08

Slave Alias

7:1

0x00

Slave Device

Alias ID

7-bit Remote Slave Device Alias ID

Assigns an Alias ID to an I2C Slave device attached to the remote

Deserializer. The transaction will be remapped to the address specified in

the Slave ID register. A value of 0 in this field disables access to the remote

I2C Slave.

Reserved

0x0A

0x0B

0x0C

CRC Errors

7:0

7:4

0x00

CRC Error LSB

Number of back channel CRC errors – 8 least significant bits

CRC Error MSB Number of back channel CRC errors – 8 most significant bits

General Status

Reserved

BIST CRC Error Back channel CRC error during BIST communication with Deserializer.

The bit is cleared upon loss of link, restart of BIST, or assertion of CRC

ERROR RESET in register 0x04.

PCLK Detect

PCLK Status

1: Valid PCLK detected

0: Valid PCLK not detected

DES Error

Back channel CRC error during communication with Deserializer.

The bit is cleared upon loss of link or assertion of CRC ERROR RESET in

LINK Detect

RESERVED

LINK Status

1: Cable link detected

0: Cable link not detected (Fault Condition)

0x0D

GPIO0 Configuration

7:4

0x00

Reserved

GPIO0 Output

Value

Local GPIO output value

This value is output on the GPIO pin when the GPIO function is enabled,

the local GPIO direction is Output, and remote GPIO control is disabled.

GPIO0 Remote

Enable

Remote GPIO control

1: Enable GPIO control from remote Deserializer. The GPIO pin will be an

output, and the value is received from the remote Deserializer.

0: Disable GPIO control from remote Deserializer.

GPIO0 Direction Local GPIO Direction

1: Input

0: Output

GPIO0 Enable

GPIO function enable

1: Enable GPIO operation

0: Enable normal operation

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表 7. Serial Control Bus Registers (接下页)

ADD

(dec)

ADD

(hex)

DEFAULT

(hex)

BIT(S)

TYPE

FUNCTION

DESCRIPTION

0x0E

GPIO2 and GPIO1

Configurations

0x00

GPIO2 Output

Value

Local GPIO output value

This value is output on the GPIO pin when the GPIO function is enabled,

the local GPIO direction is Output, and remote GPIO control is disabled.

GPIO2 Remote

Enable

Remote GPIO control

1: Enable GPIO control from remote Deserializer. The GPIO pin will be an

output, and the value is received from the remote Deserializer.

0: Disable GPIO control from remote Deserializer.

GPIO2 Direction Local GPIO Direction

1: Input

0: Output

GPIO2 Enable

GPIO function enable

1: Enable GPIO operation

0: Enable normal operation

GPIO1 Output

Value

Local GPIO output value

This value is output on the GPIO pin when the GPIO function is enabled,

the local GPIO direction is Output, and remote GPIO control is disabled.

GPIO1 Remote

Enable

Remote GPIO control

1: Enable GPIO control from remote Deserializer. The GPIO pin will be an

output, and the value is received from the remote Deserializer.

0: Disable GPIO control from remote Deserializer.

GPIO1 Direction Local GPIO Direction

1: Input

0: Output

GPIO1 Enable

GPIO function enable

1: Enable GPIO operation

0: Enable normal operation

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表 7. Serial Control Bus Registers (接下页)

ADD

(dec)

ADD

(hex)

DEFAULT

(hex)

BIT(S)

TYPE

FUNCTION

DESCRIPTION

0x0F

GPO_REG4 and

GPIO3 Configurations

0x00

GPO_REG4

Output Value

Local GPO_REG4 output value

This value is output on the GPO pin when the GPO function is enabled.

(The local GPO direction is Output, and remote GPO control is disabled)

6:5

Reserved

GPO_REG4

Enable

GPO_REG4 function enable

1: Enable GPO operation

0: Enable normal operation

GPIO3 Output

Value

Local GPIO output value

This value is output on the GPIO pin when the GPIO function is enabled,

the local GPIO direction is Output, and remote GPIO control is disabled.

GPIO3 Remote

Enable

Remote GPIO control

1: Enable GPIO control from remote Deserializer. The GPIO pin will be an

output, and the value is received from the remote Deserializer.

0: Disable GPIO control from remote Deserializer.

GPIO3 Direction Local GPIO Direction

1: Input

0: Output

GPIO3 Enable

GPIO function enable

1: Enable GPIO operation

0: Enable normal operation

0x10

GPO_REG6 and

GPO_REG5

Configurations

0x00

GPO_REG6

Output Value

Local GPO_REG6 output value

This value is output on the GPO pin when the GPO function is enabled.

(The local GPO direction is Output, and remote GPO control is disabled)

6:5

Reserved

GPO_REG6

Enable

GPO_REG6 function enable

1: Enable GPO operation

0: Enable normal operation

GPO_REG5

Output Value

Local GPO_REG5 output value

This value is output on the GPO pin when the GPO function is enabled, the

local GPO direction is Output, and remote GPO control is disabled.

2:1

Reserved

GPO_REG5

Enable

GPO_REG5 function enable

1: Enable GPO operation

0: Enable normal operation

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ZHCSEV0 –MARCH 2016

表 7. Serial Control Bus Registers (接下页)

ADD

(dec)

ADD

(hex)

DEFAULT

(hex)

BIT(S)

TYPE

FUNCTION

DESCRIPTION

0x11

GPO_REG7

Configurations

7:4

0x00

Reserved

Local GPO_REG7 output value

This value is output on the GPO pin when the GPO function is enabled, the

local GPO direction is Output, and remote GPO control is disabled.

GPO_REG7

Output Value

2:1

Reserved

GPO_REG7

Enable

GPO_REG7 function enable

1: Enable GPO operation

0: Enable normal operation

0x12

Data Path Control

7:6

0x00

Reserved

DE Polarity

The bit indicates the polarity of the DE (Data Enable) signal.

1: DE is inverted (active low, idle high)

0: DE is positive (active high, idle low)

I2S Repeater

Regen

I2S Repeater Regeneration

1: Repeater regenerate I2S from I2S pins

0: Repeater pass through I2S from video pins

Reserved

18-bit Video

Select

18–bit video select

1: Select 18-bit video mode

Note: use of GPIO(s) on unused inputs must be enabled by register.

0: Select 24-bit video mode

I2S Transport

Select

I2S Transport Mode Slect

1: Enable I2S Data Forward Channel Frame Transport

0: Enable I2S Data Island Transport

7:5

Reserved

0x13

Mode Status

0x10

MODE_SEL

Alternate

MODE_SEL Status

1: MODE_SEL decode circuit is completed

0: MODE_SEL decode circuit is not completed

Alternate Frequency Mode Status

Frequency Mode Indicates either Low Frequency mode or Intermediate Frequency mode,

depending on FSEL status. See Frequency Mode Optimizations.

Repeater Mode

Repeater Mode Status

1: Repeater mode ON

0: Repeater Mode OFF

Reserved

18-Bit Mode

18-bit Mode Strap Status. The initial strap value can be overridden by

1: 18-bit RGB mode

0: 24-bit RGB mode

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表 7. Serial Control Bus Registers (接下页)

ADD

(dec)

ADD

(hex)

DEFAULT

(hex)

BIT(S)

TYPE

FUNCTION

DESCRIPTION

0x14

Oscillator Clock

Source and BIST

Status

7:3

2:1

0x00

Reserved

OSC Clock

Source

OSC Clock Source

(When LFMODE = 1, Oscillator = 12.5MHz ONLY)

00: External Pixel Clock

01: 33 MHz Oscillator

10: Reserved

11: 25 MHz Oscillator

BIST Enable

Status

BIST status

1: Enabled

0: Disabled

0x16

0x17

BCC Watchdog

Control

7:1

0xFE

Timer Value

The watchdog timer allows termination of a control channel transaction if it

fails to complete within a programmed amount of time.

This field sets the Bidirectional Control Channel Watchdog Timeout value in

units of 2 ms.

This field should not be set to 0

Timer Control

I2C Pass All

Disable Bidirectional Control Channel Watchdog Timer

1: Disables BCC Watchdog Timer operation

0: Enables BCC Watchdog Timer operation

I2C Control

0x5E

I2C Control

1: Enable Forward Control Channel pass-through of all I2C accesses to I2C

Slave IDs that do not match the Serializer I2C Slave ID.

0: Enable Forward Control Channel pass-through only of I2C accesses to

I2C Slave IDs matching either the remote Deserializer Slave ID or the

remote Slave ID.

Reserved

5:4

SDA Hold Time

Internal SDA Hold Time

Configures the amount of internal hold time provided for the SDA input

relative to the SCL input. Units are 40 ns

3:0

7:0

I2C Filter Depth Configures the maximum width of glitch pulses on the SCL and SDA inputs

that will be rejected. Units are 5 ns

0x18

SCL High Time

0xA1

SCL HIGH Time I2C Master SCL High Time

This field configures the high pulse width of the SCL output when the

Serializer is the Master on the local I2C bus. Units are 40 ns for the nominal

oscillator clock frequency. The default value is set to provide a minimum

5us SCL high time with the internal oscillator clock running at 32.5MHz

rather than the nominal 25MHz.

DS90UB921-Q1

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ZHCSEV0 –MARCH 2016

表 7. Serial Control Bus Registers (接下页)

ADD

(dec)

ADD

(hex)

DEFAULT

(hex)

BIT(S)

TYPE

FUNCTION

DESCRIPTION

0x19

SCL Low Time

7:0

0xA5

SCL LOW Time I2C SCL Low Time

This field configures the low pulse width of the SCL output when the

Serializer is the Master on the local I2C bus. This value is also used as the

SDA setup time by the I2C Slave for providing data prior to releasing SCL

during accesses over the Bidirectional Control Channel. Units are 40 ns for

the nominal oscillator clock frequency. The default value is set to provide a

minimum 5us SCL low time with the internal oscillator clock running at

32.5MHz rather than the nominal 25MHz.

0x1B

0x35

BIST BC Error

FSEL Override

7:0

0x00

BIST Back

Channel CRC

Error Counter

BIST Mode Back Channel CRC Error Counter

This error counter is active only in the BIST mode. It clears itself at the start

of the BIST run.

FSEL Register

Override Control

FSEL Override. FSEL value is set by pin or through register.

0: FSEL set by pin 15 at power-up

1: FSEL is set by register 0x35[6]

FSEL Override

Value

This value will be used for FSEL when FSEL Register Override is set

(0x35[7]). See Frequency Mode Optimizations.

5:0

7:4

RESERVED

Pattern

Reserved.

100

0x64

Pattern Generator

Control

0x10

Fixed Pattern Select

Generator Select This field selects the pattern to output when in Fixed Pattern Mode. Scaled

patterns are evenly distributed across the horizontal or vertical active

regions. This field is ignored when Auto-Scrolling Mode is enabled. The

following table shows the color selections in non-inverted followed by

inverted color mode

0000: Reserved

0001: White/Black

0010: Black/White

0011: Red/Cyan

0100: Green/Magenta

0101: Blue/Yellow

0110: Horizontally Scaled Black to White/White to Black

0111: Horizontally Scaled Black to Red/Cyan to White

1000: Horizontally Scaled Black to Green/Magenta to White

1001: Horizontally Scaled Black to Blue/Yellow to White

1010: Vertically Scaled Black to White/White to Black

1011: Vertically Scaled Black to Red/Cyan to White

1100: Vertically Scaled Black to Green/Magenta to White

1101: Vertically Scaled Black to Blue/Yellow to White

1110: Custom color (or its inversion) configured in PGRS, PGGS, PGBS

registers

1111: Reserved

3:1

Reserved

Pattern

Generator

Enable

Pattern Generator Enable

1: Enable Pattern Generator

0: Disable Pattern Generator

DS90UB921-Q1

ZHCSEV0 –MARCH 2016

www.ti.com.cn

表 7. Serial Control Bus Registers (接下页)

ADD

(dec)

ADD

(hex)

DEFAULT

(hex)

BIT(S)

TYPE

FUNCTION

DESCRIPTION

101

0x65

Pattern Generator

Configuration

7:5

0x00

Reserved

Pattern

18-bit Mode Select

Generator 18

Bits

1: Enable 18-bit color pattern generation. Scaled patterns will have 64 levels

of brightness and the R, G, and B outputs use the six most significant color

bits.

0: Enable 24-bit pattern generation. Scaled patterns use 256 levels of

brightness.

Pattern

Generator

External Clock

Select External Clock Source

1: Selects the external pixel clock when using internal timing.

0: Selects the internal divided clock when using internal timing

This bit has no effect in external timing mode (PATGEN_TSEL = 0).

Pattern

Timing Select Control

Generator

Timing Select

1: The Pattern Generator creates its own video timing as configured in the

Pattern Generator Total Frame Size, Active Frame Size. Horizontal Sync

Width, Vertical Sync Width, Horizontal Back Porch, Vertical Back Porch, and

Sync Configuration registers.

0: the Pattern Generator uses external video timing from the pixel clock,

Data Enable, Horizontal Sync, and Vertical Sync signals.

Pattern

Enable Inverted Color Patterns

Generator Color 1: Invert the color output.

Invert

0: Do not invert the color output.

Pattern

Auto-Scroll Enable:

Generator Auto- 1: The Pattern Generator will automatically move to the next enabled

Scroll Enable

pattern after the number of frames specified in the Pattern Generator Frame

Time (PGFT) register.

0: The Pattern Generator retains the current pattern.

102

103

198

0x66

0x67

0xC6

Pattern Generator

Indirect Address

7:0

0x00

Indirect Address This 8-bit field sets the indirect address for accesses to indirectly-mapped

registers. It should be written prior to reading or writing the Pattern

Generator Indirect Data register.

See AN-2198 (SNLA132).

Pattern Generator

Indirect Data

When writing to indirect registers, this register contains the data to be

written. When reading from indirect registers, this register contains the read

back value.

See AN-2198 (SNLA132)

ICR

7:6

Reserved

IS_RX_INT

INT Enable

Interrupt on Receiver interrupt

Enables interrupt on indication from the Receiver. Allows propagation of

interrupts from downstream devices

4:1

Reserved

Global Interrupt Enable

Enables interrupt on the interrupt signal to the controller.

DS90UB921-Q1

www.ti.com.cn

ZHCSEV0 –MARCH 2016

表 7. Serial Control Bus Registers (接下页)

ADD

(dec)

ADD

(hex)

DEFAULT

(hex)

ISR

BIT(S)

TYPE

FUNCTION

DESCRIPTION

199

0xC7

7:6

Reserved

IS RX INT

Interrupt on Receiver interrupt

Receiver has indicated an interrupt request from down-stream device

4:1

Reserved

INT

Global Interrupt

Set if any enabled interrupt is indicated

DS90UB921-Q1

ZHCSEV0 –MARCH 2016

www.ti.com.cn

8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The DS90UB921-Q1, in conjunction with the DS90UB948-Q1, is intended for interface between a host (graphics

processor) and a Display. It supports a 24-bit color depth (RGB888) and extended high definition (1920x720p)

digital video format. It can receive a three 8-bit RGB stream with a pixel rate up to 96 MHz together with three

control bits (VS, HS and DE) and three I2S-bus audio stream with an audio sampling rate up to 192 kHz.

8.2 AVMUTE Operation

When using DS90UB921-Q1, it is possible to send video data during the blanking period (DE = L). If a specific

pattern is sent during the blanking period, the paired Deserializer will enter AVMUTE mode. The pattern that the

Deserializer is looking for is 24'h666666. If the last pixel of the frame is 24'h666666, and the video transmission

extends into the DE = L, period, then AVMUTE mode will be enabled.

Setting 0x04[1] = "1" on the DS90UB921-Q1 will prevent video from being sent during the blanking interval. This

will ensure AVMUTE mode is not entered during normal operation.

DS90UB921-Q1

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ZHCSEV0 –MARCH 2016

8.3 Typical Application

DS90UB921-Q1

3.3V/1.8V

3.3V

VDDIO

VDD33

CAPP12

CAPL12

FB1

FB2

DIN0

DIN1

DIN2

DIN3

DIN4

DIN5

DIN6

DIN7

CAPHS12

DIN8

DIN9

DIN10

DIN11

DIN12

DIN13

DIN14

DIN15

Serial

FPD-Link III

Interface

DOUT+

DOUT-

CMF

LVCMOS

Parallel

Video

Interface

DIN16

DIN17

DIN18

DIN19

DIN20

DIN21

DIN22

DIN23

VDD33

MODE_SEL

PCLK

VDDIO VDD33*

VDD33

NOTE:

LVCMOS

Control

Interface

FB1-FB2: Impedance = 1 kW @ 100 MHz,

Low DC resistance (<1W)

C1-C3 = 0.1 mF (50 WV; C1, C2: 0402; C3: 0603)

C4-C9 = 4.7 mF

INTB

PDB

ID[X]

SCL

SDA

C10

REM_INTB

C10 =>10 mF

I2S_CLK

I2S_WC

I2S_DA

and R (see IDx Resistor Values Table)

and R (see MODE_SEL Resistor Values Table)

RES1

DAP (GND)

FSEL

= 10 kW

= 4.7 kW

* or VDDIO = 3.3V+0.3V

图 26. Typical STP Connection Diagram

DS90UB921-Q1

ZHCSEV0 –MARCH 2016

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Typical Application (接下页)

DS90UB921-Q1

3.3V/1.8V

3.3V

VDDIO

VDD33

CAPP12

CAPL12

FB1

FB2

DIN0

DIN1

DIN2

DIN3

DIN4

DIN5

DIN6

DIN7

CAPHS12

DIN8

DIN9

DIN10

DIN11

DIN12

DIN13

DIN14

DIN15

Serial

FPD-Link III

Interface

DOUT+

DOUT-

CMF

LVCMOS

Parallel

Video

R₇

Interface

DIN16

DIN17

DIN18

DIN19

DIN20

DIN21

DIN22

DIN23

VDD33

MODE_SEL

PCLK

VDDIO VDD33*

NOTE:

VDD33

FB1-FB2: Impedance = 1 kW @ 100 MHz,

Low DC resistance (<1W)

C1 = 330nF (50 WV; C1, C2: 0402; C3: 0603)

C2 = 150nF

C3 = 0.1 mF

C4-C9 = 4.7 mF

LVCMOS

Control

Interface

INTB

PDB

ID[X]

SCL

SDA

C10

REM_INTB

C10 =>10 mF

C11-C12 = 0.1 mF

I2S_CLK

I2S_WC

I2S_DA

and R (see IDx Resistor Values Table)

and R (see MODE_SEL Resistor Values Table)

RES1

DAP (GND)

FSEL

= 10 kW

= 4.7 kW

= 50 W

* or VDDIO = 3.3V+0.3V

图 27. Typical Coax Connection Diagram

DS90UB921-Q1

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ZHCSEV0 –MARCH 2016

Typical Application (接下页)

DDIO

DD33

DDIO

DD33

(3.3V) (1.8Vor3.3V)

(1.8Vor3.3V) (3.3V)

R[7:0]

G[7:0]

R[7:0]

G[7:0]

FPD-Link III

1 Pair / AC Coupled

B[7:0]

PCLK

B[7:0]

HOST

Graphics

Processor

RGB Display

720p

24-bit color depth

DOUT+

RIN+

RIN-

PCLK

DOUT-

DS90UB921-Q1

Serializer

DS90UB926Q-Q1

Deserializer

LOCK

PASS

PDB

OSS_SEL

OEN

PDB

I2S AUDIO

(STEREO)

I2S AUDIO

(STEREO)

MODE_SEL

INTB

INTB_IN

MCLK

SCL

SDA

IDx

SCL

SDA

IDx

DAP

图 28. Typical STP System Diagram

DDIO

(1.8Vor3.3V) (3.3V)

DD33

DDIO

DD33

(3.3V)

DD12

(1.2V)

(1.8Vor3.3V)

FPD-Link

(Open LDI)

R[7:0]

G[7:0]

B[7:0]

PCLK

FPD-Link III

1 Pair / AC Coupled

CLK1+/-

D0+/-

HOST

Graphics

Processor

DOUT+

RIN0+

RIN0-

D1+/-

D2+/-

D3+/-

DOUT-

LVDS

Display

720p60

or Graphic

Processor

DS90UB921-Q1

Serializer

PDB

DS90UB948-Q1

Deserializer

CLK2+/-

D4+/-

I2S AUDIO

(STEREO)

PDB

INTB_IN

MODE_SEL

INTB

MODE_SEL[1:0]

D5+/-

SCL

SDA

IDx

SCL

SDA

IDx

D6+/-

D7+/-

DAP

图 29. Typical Coax Applications Diagram

8.3.1 Design Requirements

For the typical design application, use the following as input parameters.

表 8. Design Parameters

DESIGN PARAMETER

VDDIO

EXAMPLE VALUE

1.8 V or 3.3 V

3.3 V

VDD33

100 nF on DOUT+ and 100nF on DOUT- for STP

330nF on DOUT+ and 150nF on DOUT- for Coax

AC Coupling Capacitor for DOUT±

PCLK Frequency

74.25 MHz

DS90UB921-Q1

ZHCSEV0 –MARCH 2016

www.ti.com.cn

8.3.2 Detailed Design Procedure

图 26 shows a typical application of the DS90UB921-Q1 serializer for an 96 MHz 24-bit Color Display

Application. The CML outputs must have an external 0.1 μF AC coupling capacitor on the high speed serial lines

for STP applications and 0.33 μF / 0.15 μF AC coupling capacitors for coax applications. The same AC coupling

capacitor values should be used on the paired deserializer board. The serializer has an internal termination.

Bypass capacitors are placed near the power supply pins. At a minimum, six (6) 4.7μF capacitors and two (2)

additional 1μF capacitors should be used for local device bypassing. Ferrite beads are placed on the two (2)

VDDs (VDD33 and VDDIO) for effective noise suppression. The interface to the graphics source is with 3.3V

LVCMOS levels, thus the VDDIO pin is connected to the 3.3 V rail.

8.3.3 Application Curves

Time (200 ps/DIV)

Time (2.0 ns/DIV)

图 30. Serializer Eye Diagram with 74.25 MHz TX Pixel

图 31. Serializer CML Output with 74.25 MHz TX Pixel

Clock

DS90UB921-Q1

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ZHCSEV0 –MARCH 2016

9 Power Supply Recommendations

9.1 Power Up Requirements and PDB Pin

When VDDIO and VDD33 are powered separately, the VDDIO supply (1.8V or 3.3V) should ramp 100us before

the other supply, VDD33. If VDDIO is tied with VDD33, both supplies may ramp at the same time. The VDDs

(VDD33 and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If the PDB pin is not

controlled by a microcontroller, a large capacitor on the pin is needed to ensure PDB arrives after all the VDDs

have settled to the recommended operating voltage. When PDB pin is pulled to VDDIO = 3.0V to 3.6V or

VDD33, it is recommended to use a 10 kΩ pull-up and a >10 uF cap to GND to delay the PDB input signal.

A minimum low pulse of 2ms is required when toggling the PDB pin to perform a hard reset.

All inputs must not be driven until VDD33 and VDDIO has reached its steady state value.

t₀

VDDIO

GND

t₃

VDD33

GND

t₁

VDD33

V_{PDB_HIGH}

PDB^(*)

V_{PDB_LOW}

t₄

GND

^(*)It is recommended to assert PDB (active High) with a microcontroller rather than an RC filter

network to help ensure proper sequencing of PDB pin after settling of power supplies.

图 32. Timing Diagram of DS90UB921-Q1

表 9. Power-Up Sequencing Constraints

Symbol

VDDIO

VDD33

Description

Test Conditions

Min

3.0

Typ

Max

3.6

Units

VDDIO voltage range

VDD33 voltage range

1.71

3.0

1.89

3.6

PDB LOW threshold

Note: V_PDBshould not exceed

limit for respective I/O voltage

before 90% voltage of VDD12

V_{PDB_LOW}

VDDIO = 3.3V ± 10%

0.8

V_{PDB_HIGH}

t₀

PDB HIGH threshold

2.0

These time constants are specified for

rise time of power supply voltage ramp

(10% - 90%)

VDDIO rise time

0.05

<1.5

These time constants are specified for

rise time of power supply voltage ramp

(10% - 90%)

t₃

VDD33 rise time

<1.5

DS90UB921-Q1

ZHCSEV0 –MARCH 2016

www.ti.com.cn

Power Up Requirements and PDB Pin (接下页)

表 9. Power-Up Sequencing Constraints (接下页)

Symbol

Description

Test Conditions

Min

Typ

Max

Units

V_ILof rising edge (VDDIO) to V_ILof rising

edge (VDD33)

t₁

VDD33 delay time

The power supplies may be ramped

simultaneously. If sequenced, VDDIO

should be first..

The part is powered up after the startup

time has elapsed from the moment PDB

goes HIGH. Local I2C is available to

read/write 921 registers after this time.

t₄

Startup time

This device is designed to operate from an input core voltage supply of 3.3V. Some devices provide separate

power and ground terminals for different portions of the circuit. This is done to isolate switching noise effects

between different sections of the circuit. Separate planes on the PCB are typically not required. Terminal

description tables typically provide guidance on which circuit blocks are connected to which power terminal pairs.

In some cases, an external filter may be used to provide clean power to sensitive circuits such as PLLs.

9.2 CML Interconnect Guidelines

See AN-1108 (SNLA008) and AN-905 (SNLA035) for full details.

•

Use 100Ω coupled differential pairs

Use the S/2S/3S rule in spacings

–

– S = space between the pair

– 2S = space between pairs

– 3S = space to LVCMOS signal

•

Minimize the number of Vias

Use differential connectors when operating above 500 Mbps line speed

Maintain balance of the traces

Minimize skew within the pair

Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the Texas

Instruments web site at: www.ti.com/lvds.

DS90UB921-Q1

www.ti.com.cn

ZHCSEV0 –MARCH 2016

10 Layout

10.1 Layout Guidelines

Circuit board layout and stack-up for the FPD-Link III devices should be designed to provide low-noise power

feed to the device. Good layout practice will also separate high frequency or high-level inputs and outputs to

minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly

improved by using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane

capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at

high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass

capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the

range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the

tantalum capacitors should be at least 5X the power supply voltage being used.

Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per

supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power

entry. This is typically in the 50uF to 100uF range and will smooth low frequency switching noise. It is

recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors

connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external

bypass capacitor will increase the inductance of the path.

A small body size X7R chip capacitor, such as 0603 or 0402, is recommended for external bypass. Its small body

size reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of

these external bypass capacitors, usually in the range of 20-30 MHz. To provide effective bypassing, multiple

capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At

high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing

the impedance at high frequency.

Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate

switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not

required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power

pin pairs. In some cases, an external filter may be used to provide clean power to sensitive circuits such as

PLLs.

Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the CML

lines to prevent coupling from the LVCMOS lines to the CML lines. Closely-coupled differential lines of 100 Ohms

are typically recommended for CML interconnect. The closely coupled lines help to ensure that coupled noise will

appear as common-mode and thus is rejected by the receivers. The tightly coupled lines will also radiate less.

Information on the WQFN style package is provided in TI Application Note: AN-1187 (SNOA401).

DS90UB921-Q1

ZHCSEV0 –MARCH 2016

www.ti.com.cn

10.2 Layout Example

Stencil parameters such as aperture area ratio and the fabrication process have a significant impact on paste

deposition. Inspection of the stencil prior to placement of the WQFN package is highly recommended to improve

board assembly yields. If the via and aperture openings are not carefully monitored, the solder may flow

unevenly through the DAP. Stencil parameters for aperture opening and via locations are shown below:

图 33. No Pullback WQFN, Single Row Reference Diagram

表 10. No Pullback WQFN Stencil Aperture Summary

DEVICE

COUN

MKT Dwg PCB I/O

PCB

PCB DAP

SIZE (mm)

STENCIL I/O

APERTURE

(mm)

STENCIL

DAP

Aperture

(mm)

NUMBER of

DAP

APERTURE

OPENINGS

GAP BETWEEN

DAP APERTURE

(Dim A mm)

Pad Size PITCH

(mm)

DS90UB921-

0.25 x

0.6

SQA48A

0.5

5.1 x 5.1

0.25 x 0.7

1.1 x 1.1

0.2

图 34. 48-Pin WQFN Stencil Example of Via and Opening Placement

DS90UB921-Q1

www.ti.com.cn

ZHCSEV0 –MARCH 2016

图 35 and 图 36 PCB layout examples are derived from the layout design of the DS90UB921-Q1EVM Evaluation

Board. The graphic and layout description are used to determine proper routing when designing the Serializer

board. 图 35 shows the high speed FPD-Link III traces routed differentially to the connector. The traces are

buried in an internal layer with a GND layer and power layer on each adjacent layer. Burying the traces helps

reduce emissions, and it is important not to route other high speed signals near these critical signal traces. 100Ω

differential characteristic impedance and 50Ω single-ended characteristic impedance traces are maintained as

much as possible for both STP and coax applications. For layout of a coax board, 100Ω coupled traces should

be used with the DOUT- termination near to the connector.

Buried signal traces

图 35. DS90UB921-Q1 Serializer Example Layout, Inner Layer

图 36 shows the high speed FPD-Link III traces close to the DOUT± pins. In this case, the AC coupling

capacitors are on the opposide side of the board, so there is an additional via that would not be needed if the

components were all on the same side. This via, the AC coupling capacitors, the common-mode choke, and the

second via (going to the buried traces to the connector) are all place closely together so that the impedance

discontinuity appears as tightly grouped as possible.

DS90UB921-Q1

ZHCSEV0 –MARCH 2016

www.ti.com.cn

Tightly

grouped

discontinuities

图 36. DS90UB921-Q1 Serializer Example Layout, Bottom Layer

DS90UB921-Q1

www.ti.com.cn

ZHCSEV0 –MARCH 2016

11 器件和文档支持

11.1 文档支持

11.1.1 相关文档ꢀ

•

《AN-2198 探究内部测试模式生成》，SNLA132

《AN-1108 通道链路 PCB 和互连设计指南》，SNLA008

《SCAN18245T 具有三态输出的同向收发器》，SNLA035

TI 接口网站 www.ti.com.cn/lvds

《AN-1187 无引线框架封装 (LLP)》，SNOA401

《半导体和 IC 封装热指标》，SPRA953

11.2 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.3 商标

E2E is a trademark of Texas Instruments.

11.4 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

11.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对

本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

DS90UB921TRHSRQ1

DS90UB921TRHSTQ1

ACTIVE

WQFN

RHS

1000 RoHS & Green

250 RoHS & Green

Level-3-260C-168 HR

-40 to 105

UB921Q

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

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(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

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DS90UB921-Q1 [TI]

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