DS90UB924TRHSTQ1_技术文档

Sample &

Buy

Support &

Community

Reference

Design

Product

Folder

Tools &

Software

Technical

Documents

DS90UB924-Q1

ZHCSEY4 –APRIL 2016

DS90UB924-Q1 具有双向控制通道的 5MHz 至 96MHz 24 位彩色 FPD-

Link III 转 OpenLDI 解串器

1 特性

2 应用范围

1

•

适用于汽车电子应用 AEC-Q100

•

汽车用触摸显示屏

汽车导航显示屏

汽车仪表板

–

器件温度 2 级：-40℃ 至 +105℃ 的环境运行温

度范围

器件人体放电模型 (HBM) 静电放电 (ESD) 分类

等级 ±8kV

3 说明

带电器件模型 (CDM) ESD 分类等级 C6

DS90UB924-Q1 解串器与 DS90UB921-Q1、

•

支持 5MHz 至 96MHz 像素时钟

双向控制通道接口，可连接兼容 I²C 的串行控制总

线

DS90UB925Q-Q1、DS90UB927Q-Q1、DS90UB929-

Q1、DS90UB949-Q1 或 DS90UB947-Q1 串行器配套

使用，可针对汽车信息娱乐系统内的数字视频和音频的

分配提供一套解决方案。该器件可将嵌入时钟的高速串

行化接口（通过单信号对 (FPD-Link III) 传输）转换为

四个 LVDS 数据/控制流、一个 LVDS 时钟对

•

低电磁干扰 (EMI) OpenLDI 视频输出

支持高清 (720p) 数字视频

支持 RGB888 + VS，HS，DE 和 I2S 音频

多达 4 个适用于环绕立体声应用的 I2S 数字音频

输出

(OpenLDI) 以及 I2S 音频数据。FPD-Link III 串行总线

方案支持通过单条差分链路实现高速正向通道数据传输

和低速反向通道通信的全双工控制。通过单个差分对整

合音频、视频和和控制数据可减小互连线尺寸和重量，

同时还消除了偏差问题并简化了系统设计。

•

4 条具有 2 个专用引脚的双向通用输入输出 (GPIO)

通道

通过兼容 1.8V 或 3.3V 的低电压互补金属氧化物半

导体 (LVCMOS) I/O 接口实现 3.3V 单电源供电运

行

通过对串行输入数据流使用自适应输入均衡功能，可对

传输介质损耗和确定性抖动进行补偿。通过使用低压差

分信令可最大限度减少电磁干扰 (EMI)。

•

具有嵌入式时钟的直流均衡和扰频数据

自适应电缆均衡

内部模式生成

器件信息 ⁽¹⁾

向后兼容模式

部件号

封装

WQFN (48)

封装尺寸（标称值）

DS90UB924-Q1

7.00mm x 7.00mm

(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。

FPD-Link

(Open LDI)

V_DD33

V_DDIO

V

DDIO

(1.8Vor3.3V) (3.3V)

DD33

(3.3V) (1.8V or 3.3V)

R[7:0]

G[7:0]

B[7:0]

HS

VS

DE

PCLK

TxOUT3+/-

TxOUT2+/-

FPD-Link III

1 Pair/AC Coupled

HOST

Graphics

Processor

LVDS Display

720p or

Graphic

DOUT+

RIN+

RIN-

TxOUT1+/-

TxOUT0+/-

DOUT-

Proccesor

100Q STP Cable

TxCLKOUT+/-

INTB_IN

DS90UB921-Q1

Serializer

PDB

DS90UB924-Q1

Deserializer

3

OEN

LOCK

PASS

I2S

MCLK

SCL

SDA

IDx

I2S AUDIO

(STEREO)

OSS_SEL

PDB

MAPSEL

LFMODE

BISTEN

6

MODE_SEL

INTB

SCL

SDA

IDx

DAP

MODE_SEL

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SNLS512

DS90UB924-Q1

ZHCSEY4 –APRIL 2016

www.ti.com.cn

7.4 Device Functional Modes........................................ 27

7.5 Programming........................................................... 33

7.6 Register Maps......................................................... 35

Application and Implementation ........................ 50

8.1 Application Information............................................ 50

8.2 Typical Application .................................................. 50

Power Supply Recommendations...................... 53

9.1 Power Up Requirements and PDB Pin................... 53

9.2 Analog Power Signal Routing ................................. 55

1

2

3

4

5

6

特性.......................................................................... 1

应用范围................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 6

6.1 Absolute Maximum Ratings ..................................... 6

6.2 ESD Ratings.............................................................. 6

6.3 Recommended Operating Conditions....................... 6

6.4 Thermal Information.................................................. 7

6.5 DC Electrical Characteristics .................................... 7

6.6 AC Electrical Characteristics..................................... 9

6.7 DC and AC Serial Control Bus Characteristics....... 10

6.8 Timing Requirements for the Serial Control Bus .... 10

6.9 Timing Requirements.............................................. 11

6.10 Typical Characteristics.......................................... 15

Detailed Description ............................................ 16

7.1 Overview ................................................................. 16

7.2 Functional Block Diagram ....................................... 16

7.3 Feature Description................................................. 17

8

9

10 Layout................................................................... 55

10.1 Layout Guidelines ................................................. 55

10.2 Layout Example .................................................... 57

11 器件和文档支持 ..................................................... 58

11.1 文档支持................................................................ 58

11.2 社区资源................................................................ 58

11.3 商标....................................................................... 58

11.4 静电放电警告......................................................... 58

11.5 Glossary................................................................ 58

12 机械、封装和可订购信息....................................... 58

7

4 修订历史记录

日期

修订版本

注释

2016 年 4 月

*

首次发布。

2

DS90UB924-Q1

www.ti.com.cn

ZHCSEY4 –APRIL 2016

5 Pin Configuration and Functions

RHS Package

48-Pin WQFN

Top View

I2S_DC/GPIO2

VDD33_A

RES1

37

38

39

24

23

22

21

20

19

18

17

16

15

TxOUT0-

TxOUT0+

TxOUT1-

TxOUT1+

TxOUT2-

TxOUT2+

RIN+ 40

RIN- 41

CMF 42

DS90UB924-Q1

TOP VIEW

43

44

45

46

47

48

BISTC/INTB_IN

CMLOUTP

TxCLKOUT-

TxCLKOUT+

TxOUT3-

DAP = GND

CMLOUTN

CAPR12

TxOUT3+

CAPP12

14 GPIO0/SWC

MODE_SEL

GPIO1/SDOUT

13

Pin Functions

I/O, TYPE

DESCRIPTION

NAME

NO.

FPD-LINK (OpenLDI) OUTPUT INTERFACE

TxCLKOUT-

TxCLKOUT+

TxOUT[3:0]-

TxOUT[3:0]+

18

17

O, LVDS

Inverting LVDS Clock Output

The pair requires external 100-Ω differential termination for standard LVDS levels

True LVDS Clock Output

The pair requires external 100-Ω differential termination for standard LVDS levels

16, 20, 22,

24

Inverting LVDS Data Outputs

Each pair requires external 100-Ω differential termination for standard LVDS levels

15, 19, 21,

23

True LVDS Data Outputs

Each pair requires external 100-Ω differential termination for standard LVDS levels

LVCMOS INTERFACE

GPIO[1:0]

13, 14

I/O, LVCMOS General Purpose IO

with pulldown Shared with SDOUT, SWC

GPIO[3:2]

36, 37

I/O, LVCMOS General Purpose I/O

with pulldown Shared with I2S_DD, I2S_DC

3

DS90UB924-Q1

ZHCSEY4 –APRIL 2016

www.ti.com.cn

Pin Functions (continued)

I/O, TYPE

DESCRIPTION

NAME

NO.

GPIO_REG[8

:5]

8, 10, 7, 3

I/O, LVCMOS General Purpose I/O, register access only

with pulldown Shared with I2S_CLK, I2S_WC, I2S_DA, I2S_DB

I2S_DA

I2S_DB

I2S_DC

I2S_DD

7

3

37

36

O, LVCMOS Digital Audio Interface I2S Data Outputs

Shared with GPIO_REG6, GPIO_REG5, GPIO2, GPIO3

INTB_IN

43

I, LVCMOS Interrupt Input

with pulldown Shared with BISTC

MCLK

I2S_WC

I2S_CLK

11

10

8

O, LVCMOS Digital Audio Interface I2S Master Clock, Word Clock and I2S Bit Clock Outputs

I2S_WC and I2S_CLK are shared with GPIO_REG7 and GPIO_REG8

SDOUT

SWC

13

14

O, LVCMOS Auxiliary Digital Audio Interface I2S Data Output and Word Clock

with pulldown Shared with GPIO1 and GPIO0

CONTROL AND CONFIGURATION

BISTC

43

I, LVCMOS BIST Clock Select

with pulldown Shared with INTB_IN

Requires a 10-KΩ pullup if set HIGH

BISTEN

IDx

9

I, LVCMOS BIST Enable

with pulldown Requires a 10-KΩ pullup if set HIGH

12

I, Analog

I2C Address Select

External pullup to VDD33 is required under all conditions. DO NOT FLOAT.

Connect to external pullup to VDD33 and pulldown to GND to create a voltage divider.

See Table 7

LFMODE

MAPSEL

32

26

48

I, LVCMOS Low Frequency Mode Select

with pulldown LFMODE = 0, 15-MHz ≤ TxCLKOUT ≤ 96-MHz (Default)

LFMODE = 1, 5-MHz ≤ TxCLKOUT < 15-MHz

Requires a 10-KΩ pullup if set HIGH

I, LVCMOS FPD-Link (OpenLDI) Output Map Select

with pulldown MAPSEL = 0, LSBs on TxOUT3± (Default)

MAPSEL = 1, MSBs on TxOUT3±

Requires a 10-KΩ pullup if set HIGH

MODE_SEL

I, Analog

Device Configuration Select

Configures Backwards Compatibility (BKWD), Repeater (REPEAT), I2S 4 channel (I2S_B),

and Long Cable (LCBL) modes

Connect to external pullup to VDD33 and pulldown to GND resistors to create a voltage

divider. DO NOT FLOAT

See Table 6

OEN

30

35

1

I, LVCMOS Output Enable

with pulldown Requires a 10-KΩ pullup if set HIGH

See Table 5

OSS_SEL

PDB

I, LVCMOS Output Sleep State Select

with pulldown Requires a 10 KΩ pullup if set HIGH

See Table 5

I, LVCMOS Power-down Mode Input Pin

Must be driven or pulled up to VDD33. Refer to Power Up Requirements and PDB PinPower

Up Requirements and PDB Pin in Application and Implementation.

PDB = H, device is enabled (normal operation)

PDB = L, device is powered down

When the device is in the powered down state, the LVDS and LVCMOS outputs are tri-state,

the PLL is shutdown, and I_DDis minimized. Control Registers are RESET.

SCL

SDA

5

4

I/O, Open

Drain

I²C Clock Input/Output Interface

Must have an external pullup to V_DD33. DO NOT FLOAT

Recommended pullup: 4.7 KΩ

I/O, Open

Drain

I2C Data Input/Output Interface

Must have an external pullup to VDD33. DO NOT FLOAT

Recommended pullup: 4.7 kΩ

4

DS90UB924-Q1

www.ti.com.cn

ZHCSEY4 –APRIL 2016

Pin Functions (continued)

I/O, TYPE

DESCRIPTION

NAME

STATUS

LOCK

NO.

27

O, LVCMOS LOCK Status Output

0: PLL is unlocked, I2S, GPIO, TxOUT[3:0]±, and TxCLKOUT± are idle with output states

controlled by OEN and OSS_SEL. May be used to indicate Link Status or Display Enable.

1: PLL is locked, outputs are active with output states controlled by OEN and OSS_SEL

Route to test point or pad (recommended). Float if unused.

PASS

28

O, LVCMOS PASS Status Output

0: One or more errors were detected in the received BIST payload (BIST Mode)

1: Error-free transmission (BIST Mode)

Route to test point or pad (Recommended). Float if unused.

FPD-LINK III SERIAL INTERFACE

CMF

42

45

44

41

40

Analog

O, LVDS

I/O, LVDS

Common Mode Filter

Requires a 0.1-µF capacitor to GND

CMLOUTN

CMLOUTP

RIN-

Inverting Loop-through Driver Output

Monitor point for equalized forward channel differential signal

True Loop-through Driver Output

Monitor point for equalized forward channel differential signal

FPD-Link III Inverting Input

The output must be AC-coupled with a 0.1-µF capacitor

RIN+

FPD-Link III True Input

The output must be AC-coupled with a 0.1-µF capacitor

(1)

POWER AND GROUND

GND

DAP

Ground

Power

Large metal contact at the bottom center of the device package

Connect to the ground plane (GND) with at least 9 vias

VDD33_A

VDD33_B

38

31

3.3-V power to on-chip regulator

Each pin requires a 4.7-µF capacitor to GND

VDDIO

6

1.8-V / 3.3-V LVCMOS I/O Power

Requires a 4.7-µF capacitor to GND

REGULATOR CAPACITOR

CAPI2S

2

CAP

Decoupling capacitor connection for on-chip regulator

Each requires a 4.7-µF decoupling capacitor to GND

CAPLV25

CAPLV12

CAPR12

CAPP12

25

29

46

47

CAPL12

33

CAP

GND

Decoupling capacitor connection for on-chip regulator

Requires two 4.7-µF decoupling capacitors to GND

OTHER

RES[1:0]

39, 34

Reserved

Connect to GND

(1) The V_DD(V_DD33and V_DDIO) supply ramp must be faster than 1.5 ms with a monotonic rise.

5

DS90UB924-Q1

ZHCSEY4 –APRIL 2016

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless othewise noted)⁽¹⁾

(2)

MIN

−0.3

MAX

UNIT

V

(3)

Supply voltage – V_DD33

4

(3)

Supply voltage – V_DDIO

V

LVCMOS I/O voltage

(V_DDIO

0.3)

+

−0.3

V

Deserializer input voltage

Junction temperature

2.75

150

V

°C

Storage temperature, T_stg

−65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) For soldering specifications, see product folder at www.ti.com and Absolute Maximum Ratings for Soldering SNOA549.

(3) The DS90UB924-Q1 V_DD33and V_DDIOvoltages require a specific ramp rate during power up. The power supply ramp time must be less

than 1.5 ms with a monotonic rise.

6.2 ESD Ratings

VALUE

±8000

±1250

±250

UNIT

V

(1)

Human body model (HBM), per AEC Q100-002, all pins

Charged device model (CDM), per AEC Q100-011, all pins

Machine model (MM)

V

Air Discharge (Pins 40, 41, 44, and 45)

±15000

±8000

±15000

±8000

±15000

V

(IEC, powered-up only)

R_D= 330 Ω, C_S= 150 pF

Electrostatic

discharge

Contact Discharge (Pins 40, 41, 44, and 45)

Air Discharge (Pins 40, 41, 44, and 45)

Contact Discharge (Pins 40, 41, 44, and 45)

Air Discharge (Pins 40, 41, 44, and 45)

V

V_(ESD)

V

(ISO10605)

R_D= 330 Ω, C_S= 150 pF

V

(ISO10605)

V

R_D= 2 kΩ, C_S= 150 pF or

330 pF

Contact Discharge (Pins 40, 41, 44, and 45)

V

±8000

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

MIN NOM

MAX UNIT

(1)

Supply Voltage (V_DD33

)

3

3.3

1.8

3.6

V

(1) (2)

LVCMOS Supply Voltage (V_DDIO

)

Connect V_DDIOto 3.3 V and use 3.3-V IOs

Connect V_DDIOto 1.8 V and use 1.8-V IOs

1.71

1.89

Operating Free Air

Temperature (T_A)

−40

25

105

°C

PCLK Frequency (out of TxCLKOUT±)

5

96 MHz

(3)

Supply Noise

100 mV_P-P

(1) The DS90UB924-Q1 V_DD33and V_DDIOvoltages require a specific ramp rate during power up. The power supply ramp time must be less

than 1.5 ms with a monotonic rise.

(2) V_DDIOmust not exceed V_DD33by more than 300 mV (V_DDIO< V_DD33+ 0.3 V).

(3) Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC-coupled to the V_DD33and V_DDIOsupplies

with amplitude >100 mVp-p measured at the device VDD33 and VDDIO pins. Bit error rate testing of input to the Ser and output of the

Des shows no error when the noise frequency on the Ser is less than 50 MHz. The Des on the other hand shows no error when the

noise frequency is less than 50 MHz.

6

DS90UB924-Q1

www.ti.com.cn

ZHCSEY4 –APRIL 2016

6.4 Thermal Information

DS90UB924-Q1

(1)

THERMAL METRIC

RHS (WQFN)

UNIT

48 PINS

26.4

4.4

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

Junction-to-top characterization parameter

°C/W

R_θJC(top)

R_θJB

4.3

ψ_JT

0.1

ψ_JB

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

4.3

R_θJC(bot)

0.8

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.5 DC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

(1) (2) (3)

PARAMETER

3.3 V LVCMOS I/O

TEST CONDITIONS

PIN/FREQ.

MIN

TYP

MAX UNIT

V_IH

V_IL

High Level Input Voltage

Low Level Input Voltage

GPIO[3:0],

REG_GPIO[8:

5], LFMODE,

MAPSEL,

BISTEN,

2

V_DDIO

0.8

V

V_DDIO= 3.0 V to 3.6 V

GND

BISTC,

INTB_IN,

OEN,

I_IN

Input Current

V_IN= 0 V or V_IN= 3.0 V to 3.6 V

-10

±1

10

μA

OSS_SEL

V_IH

V_IL

High Level Input Voltage

Low Level Input Voltage

2

V_DDIO

0.7

V

GND

⁽⁴⁾PDB

V_IN= 0 V or V_IN= 3.0 V to 3.6 V

I_IN

Input Current

-10

±1

10

μA

(4)

V_OH

V_OL

I_OS

HIGH Level Output Voltage

LOW Level Output Voltage

Output Short Circuit Current

I_OH= -4 mA

I_OL= 4 mA

GPIO[3:0],

REG_GPIO[8:

5], MCLK,

2.4

0

V_DDIO

0.4

V

(5)

V_OUT= 0 V

-55

mA

I2S_WC,

I2S_CLK,

I2S_D[A:D],

LOCK, PASS

I_OZ

Tri-state Output Current

V_OUT= 0 V or V_DDIO, PDB = L

-20

20

μA

(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as

otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and

are not ensured.

(2) Typical values represent most likely parametric norms at V_DD33= 3.3 V, V_DDIO= 1.8 V or 3.3 V, T_A= 25°C, and at the Recommended

Operating Conditions at the time of product characterization and are not ensured.

(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground

except V_ODand ΔV_OD, which are differential voltages.

(4) PDB is specified to 3.3 V LVCMOS only and must be driven or pulled up to V_DD33or to V_DDIO≥ 3 V.

(5) I_OSis not specified for an indefinite period of time. Do not hold in short circuit for more than 500 ms or part damage may result.

7

DS90UB924-Q1

ZHCSEY4 –APRIL 2016

www.ti.com.cn

MAX UNIT

DC Electrical Characteristics (continued)

(1) (2) (3)

Over recommended operating supply and temperature ranges unless otherwise specified.

PARAMETER

1.8 V LVCMOS I/O

TEST CONDITIONS

PIN/FREQ.

MIN

TYP

GPIO[3:0],

REG_GPIO[8:

5], LFMODE,

MAPSEL,

BISTEN,

0.65 *

V_DDIO

V_IH

V_IL

High Level Input Voltage

Low Level Input Voltage

V_DDIO

V

V_DDIO= 1.71 V to 1.89 V

0.35 *

V_DDIO

0

BISTC,

INTB_IN,

OEN,

V_IN= 0 V or V_IN= 1.71 V to

1.89 V

I_IN

Input Current

-10

10

μA

OSS_SEL

GPIO[3:0],

REG_GPIO[8:

5], MCLK,

I2S_WC,

I2S_CLK,

V_DDIO-

0.45

V_OH

HIGH Level Output Voltage

I_OH= -4 mA

I_OL= +4 mA

V_DDIO

0.45

V

V_OL

I_OS

LOW Level Output Voltage

Output Short Circuit Current

0

V

(5)

V_OUT= 0 V

-35

mA

I2S_D[A:D],

LOCK, PASS

I_OZ

TRI-STATE® Output Current

V_OUT= 0 V or V_DDIO, PDB = L,

-20

20

μA

FPD-LINK (OpenLDI) LVDS OUTPUT

Register 0x4B[1:0] = b'00

R_L= 100 Ω

140

220

200

300

400

600

300

380

mV

Output Voltage Swing (single-

ended)

V_OD

Register 0x4B[1:0] = b'01

R_L= 100 Ω

Register 0x4B[1:0] = b'00

R_L= 100 Ω

V_ODp-p

Differential Output Voltage

Register 0x4B[1:0] = b'01

R_L= 100 Ω

TxCLK±,

TxOUT[3:0]±

ΔV_OD

V_OS

Output Voltage Unbalance

Common Mode Voltage

Offset Voltage Unbalance

Output Short Circuit Current

1

1.2

1

50

1.5

50

mV

V

R_L= 100 Ω

1

-500

-50

ΔV_OS

I_OS

mV

mA

V_OUT= GND

-5

OEN = GND, V_OUT= V_DDIOor

GND, 0.8 V ≤ V_IN≤ 1.6 V

I_OZ

Output TRI-STATE® Current

500

μA

FPD-LINK III RECEIVER

V_TH

V_TL

V_ID

Input Threshold High

50

mV

V

Input Threshold Low

V_CM= 2.1 V (Internal V_BIAS)

Input Differential Threshold

Common-mode Voltage

100

RIN±

V_CM

2.1

Internal Termination Resistance

(Differential)

R_T

80

100

120

Ω

SUPPLY CURRENT

I_DD33

V_DD33= 3.6 V

V_DDIO= 3.6 V

V_DDIO= 1.89 V

V_DD33= 3.6 V

V_DDIO= 3.6 V

V_DDIO= 1.89 V

200

30

3

260

250

8

mA

μA

mA

μA

Supply Current

R_L= 100 Ω,

PCLK = 96 MHz

I_DDIO

I_DDZ

PDB = 0 V, All other LVCMOS

inputs = 0 V

Supply Current — Power Down

100

50

500

250

I_DDIOZ

8

DS90UB924-Q1

www.ti.com.cn

ZHCSEY4 –APRIL 2016

6.6 AC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

(1) (2) (3)

PARAMETER

TEST CONDITIONS

PIN/FREQ.

MIN

TYP

MAX UNIT

GPIO

GPIO[3:0],

PCLK =

5MHz to

96MHz

GPIO Pulse Width, Forward

Channel

(4)

t_GPIO,FC

See

2/PCLK

s

(4)

t_GPIO,BC

RESET

t_LRST

GPIO Pulse Width, Back Channel See

GPIO[3:0]

20

2

µs

ms

PDB Reset Low Pulse

See

PDB

LOOP-THROUGH MONITOR OUTPUT

E_W

Differential Output Eye Opening

Width⁽⁴⁾

R_L= 100 Ω, Jitter freq > f/40

CMLOUTP,

CMLOUTN

0.4

UI

E_H

Differential Output Eye Height

300

mV

FPD-LINK (OpenLDI) LVDS OUTPUT

t_TLHT

t_THLT

t_DCCJ

t_TTPn

Low -to-High Transition Time

High-to-Low Transition Time

Cycle-to-Cycle Output Jitter

Transmitter Pulse Position

R_L= 100 Ω

TxCLK±,

TxOUT[3:0]±

0.25

0.5

65

ns

ps

UI

5 MHz ≤ PCLK ≤ 96 MHz

TxCLK±

40

5 MHz ≤ PCLK ≤ 96 MHz

n=[6:0] for bits [6:0]

See Figure 13

TxOUT[3:0]±

0.5 + n

Δt_TTP

Offset Transmitter Pulse Position

(bit 6 - bit 0)

PCLK = 96 MHz

0.1

UI

t_DD

Delay Latency

147*T

900

6

T

t_TPDD

t_TXZR

Power Down Delay Active to OFF

Enable Delay OFF to Active

µs

ns

FPD-LINK III INPUT

t_DDLTLock Time

LVCMOS OUTPUTS

(4)

5 MHz ≤ PCLK ≤ 96 MHz

RIN±, LOCK

LOCK, PASS

6

40

ms

t_CLH

Low-to-High Transition Time

High-to-Low Transition Time

C_L= 8 pF

3

2

7

5

ns

t_CHL

BIST MODE

t_PASS

BIST PASS Valid Time

PASS

MCLK

800

2

ns

I2S TRANSMITTER

t_J

Clock Output Jitter

ns

T_I2S

I2S Clock Period

PCLK=5 MHz to 96 MHz

I2S_CLK,

PCLK =

5MHz to

96MHz

4/PCLK

or

1/12.288

MHz

(4) (5)

Figure 10,

(5)

T_{HC_I2S}

T_{LC_I2S}

t_{SR_I2S}

I2S Clock High Time Figure 10,

I2S Clock Low Time Figure 10,

I2S Set-up Time Figure 10,

I2S_CLK

0.35

0.2

T_I2S

I2S_WC

I2S_D[A:D]

t_{HR_I2S}

I2S Hold Time Figure 10

I2S_WC

0.2

T_I2S

I2S_D[A:D]

(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as

otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and

are not ensured.

(2) Typical values represent most likely parametric norms at V_DD33= 3.3 V, V_DDIO= 1.8 V or 3.3 V, T_A= 25°C, and at the Recommended

Operating Conditions at the time of product characterization and are not ensured.

(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground

except V_ODand ΔV_OD, which are differential voltages.

(4) Specification is ensured by design and is not tested in production.

(5) I2S specifications for t_LCand t_HCpulses must each be greater than 2 PCLK period to ensure sampling and supersedes the 0.35*T_{I2S_CLK}

requirement. t_LCand t_HCmust be longer than the greater of either 0.35*T_{I2S_CLK}or 2*PCLK.

9

DS90UB924-Q1

ZHCSEY4 –APRIL 2016

www.ti.com.cn

MAX UNIT

6.7 DC and AC Serial Control Bus Characteristics

Over 3.3-V supply and temperature ranges unless otherwise specified.

(1) (2) (3)

PARAMETER

TEST CONDITIONS

MIN

TYP

V_IH

V_IL

0.7*

V_DDIO

Input High Level

SDA and SCL

V_DD33

V

0.3*

V_DD33

Input Low Level Voltage

Input Hysteresis

GND

V_HY

V_OL

I_in

50

mV

V

SDA or SCL, I_OL= 1.25 mA

0

0.36

10

SDA or SCL, V_IN= V_DDIOor GND

-10

µA

ns

pF

t_SP

C_in

Input Filter

50

5

Input Capacitance

SDA or SCL

(1) The Electrical Characteristics tables list specifications under the listed Recommended Operating Conditions except as otherwise

modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and are not

ensured.

(2) Typical values represent most likely parametric norms at V_DD33= 3.3 V, V_DDIO= 1.8 V or 3.3 V, T_A= 25°C, and at the Recommended

Operating Conditions at the time of product characterization and are not ensured.

(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground

except V_ODand ΔV_OD, which are differential voltages.

6.8 Timing Requirements for the Serial Control Bus

Over 3.3-V supply and temperature ranges unless otherwise specified.

(1) (2)

MIN

0

TYP

MAX UNIT

Standard Mode

Fast Mode

100 kHz

f_SCL

SCL Clock Frequency

0

400 kHz

Standard Mode

Fast Mode

4.7

1.3

4.0

0.6

4.0

0.6

4.7

0.6

0

µs

t_LOW

t_HIGH

t_HD;STA

t_SU:STA

t_HD;DAT

t_SU;DAT

t_SU;STO

t_BUF

SCL Low Period

Standard Mode

Fast Mode

SCL High Period

Standard Mode

Fast Mode

(3)

Hold time for a start or a repeated start condition

Standard Mode

Fast Mode

(3)

Set Up time for a start or a repeated start condition

Standard Mode

Fast Mode

3.45

0.9

µs

ns

µs

ns

(3)

Data Hold Time

0

Standard Mode

Fast Mode

250

100

4

(3)

Data Set Up Time

Standard Mode

Fast Mode

(3)

Set Up Time for STOP Condition

0.6

4.7

1.3

Bus Free Time

Between STOP and START

Standard Mode

Fast Mode

(3)

Standard Mode

Fast Mode

1000

300

(3)

t_r

SCL & SDA Rise Time,

Standard Mode

Fast mode

(3)

t_f

SCL & SDA Fall Time,

(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as

otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and

are not ensured.

(2) Typical values represent most likely parametric norms at V_DD33= 3.3 V, V_DDIO= 1.8 V or 3.3 V, T_A= +25°C, and at the Recommended

Operating Conditions at the time of product characterization and are not ensured.

(3) Specification is ensured by design and is not tested in production.

10

DS90UB924-Q1

www.ti.com.cn

ZHCSEY4 –APRIL 2016

6.9 Timing Requirements

MIN

NOM

430

20

MAX

UNIT

ns

t_R

SDA RiseTime – READ

SDA Fall Time – READ

Set Up Time – READ

Hold Up Time – READ

SDA, RPU = 10 kΩ, Cb ≤ 400 pF, Figure 9

t_F

ns

t_SU;DAT

t_HD;DAT

Figure 9

560

615

ns

+V_OD

TxCLKOUT

TxOUT3

-V_OD

+V_OD

-V_OD

+V_OD

-V_OD

+V_OD

-V_OD

TxOUT2

TxOUT1

TxOUT0

+V_OD

-V_OD

Cycle N

Cycle N+1

Figure 1. Checkerboard Data Pattern

EW

VOD (+)

RIN

(Diff.)

EH

0V

EH

VOD (-)

t

(1 UI)

BIT

Figure 2. CML Output Driver

V

DDIO

80%

20%

GND

t

CHL

CLH

Figure 3. LVCMOS Transition Times

START

STOP

BIT

START

BIT

STOP

BIT

START

BIT

STOP

BIT

START STOP

BIT BIT

SYMBOLN+3

BIT

SYMBOLN

SYMBOLN+1

SYMBOLN+2

RIN

DCA, DCB

t

DD

TxCLKOUT

TxOUT[3:0]

SYMBOL N-3

SYMBOL N-2

SYMBOL N-1

SYMBOL N

Figure 4. Latency Delay

11

DS90UB924-Q1

ZHCSEY4 –APRIL 2016

www.ti.com.cn

PDB

RIN

VILmax

X

t

TPDD

LOCK

PASS

Z

TxCLKOUT

TxOUT[3:0]

Z

Figure 5. FPD-Link (OpenLDI) and LVCMOS Power Down Delay

PDB

LOCK

t

TXZR

OEN

VIHmin

Z

TxCLKOUT

TxOUT[3:0]

Figure 6. FPD-Link (OpenLDI) Outputs Enable Delay

PDB

VIH(min)

RIN±

t_DDLT

LOCK

VOH(min)

TRI-STATE

Figure 7. CML PLL Lock Time

RIN+

RIN-

V_TL

V_CM

V_TH

GND

Figure 8. FPD-Link III Receiver DC V_TH/V_TLDefinition

12

DS90UB924-Q1

www.ti.com.cn

ZHCSEY4 –APRIL 2016

V

DDIO

I2S_CLK,

MCLK

1/2 V

DDIO

GND

V

DDIO

GPIO,

I2S_WC,

I2S_D[D:A]

V

OHmin

V

OLmax

GND

t

ROH

ROS

Figure 9. Output Data Valid (Setup and Hold) Times

t_I2S

t_{LC_I2S}

t_{HC_I2S}

V_IH

V_IL

I2S_CLK

t_{SR_I2S}

t_{HR_I2S}

V_IH

V_IL

I2S_WC

I2S_D[A,B,C,D]

Figure 10. Output State (Setup and Hold) Times

+VOD

0V

-VOD

80%

20%

TxOUT[3:0]

TxCLKOUT

(Differential)

t

HLT

LHT

Figure 11. Input Transition Times

TxOUT[3:0]+

TxCLKOUT+

V_OD-

V_OD+

TxOUT[3:0]-

TxCLKOUT-

V_OS

GND

(TxOUT[3:0]+) -

(TxOUT[3:0]-) or

(TxCLKOUT+) -

(TxCLKOUT-)

V_OD+

0V

V_ODp-p

V_OD-

Figure 12. FPD-Link (OpenLDI) Single-Ended and Differential Waveforms

13

DS90UB924-Q1

ZHCSEY4 –APRIL 2016

www.ti.com.cn

T

TxCLKOUT±

TxOUT[3:0]±

bit 1 bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

t

TTP1

TTP2

TTP3

TTP4

TTP5

TTP6

TTP7

0.5UI

1.5UI

2.5UI

2∆t

TTP

3.5UI

4.5UI

5.5UI

6.5UI

Figure 13. FPD-Link (OpenLDI) Transmitter Pulse Positions

Ideal Data

Bit End

Sampling

Window

Ideal Data Bit

Beginning

V

TH

0V

RxIN_TOL

Left

RxIN_TOL

Right

V

TL

Ideal Center Position (t /2)

BIT

t

(1 UI)

BIT

t

_IJIT= RxIN_TOL (Left + Right)

Sampling Window = 1 UI - t

IJIT

Figure 14. Receiver Input Jitter Tolerance

BISTEN

1/2 V

DDIO

t

PASS

1/2 V

PASS

(w/errors)

DDIO

Result Held

Prior BIST Result

Current BIST Test - Toggle on Error

Figure 15. BIST PASS Waveform

SDA

t

BUF

t

f

t

HD;STA

t

r

LOW

t

f

r

SCL

t

HD;STA

SU;STA

t

SU;STO

t

HIGH

t

SU;DAT

HD;DAT

STOP START

START

REPEATED

START

Figure 16. Serial Control Bus Timing Diagram

14

DS90UB924-Q1

www.ti.com.cn

ZHCSEY4 –APRIL 2016

6.10 Typical Characteristics

Time (4 ns/DIV)

Time (1.0 ns/DIV)

Figure 18. 96 MHz Clock at Serializer and Deserializer

Figure 17. Serializer Output Stream with 96 MHz Input Clock

15

DS90UB924-Q1

ZHCSEY4 –APRIL 2016

www.ti.com.cn

7 Detailed Description

7.1 Overview

The DS90UB924-Q1 receives a 35-bit symbol over a single serial FPD-Link III pair operating at up to 3.36 Gbps

line rate and converts this stream into an FPD-Link (OpenLDI) Interface (4 LVDS data channels + 1 LVDS

Clock). The FPD-Link III serial stream contains an embedded clock, video control signals, and the DC-balanced

video data and audio data which enhance signal quality to support AC coupling.

The DS90UB924-Q1 deserializer attains lock to a data stream without the use of a separate reference clock

source, which greatly simplifies system complexity and overall cost. The deserializer also synchronizes to the

serializer regardless of the data pattern, delivering true automatic plug and lock performance. It can lock to the

incoming serial stream without the need of special training patterns or sync characters. The deserializer recovers

the clock and data by extracting the embedded clock information, validating then deserializing the incoming data

stream.

The DS90UB924-Q1 deserializer incorporates an I²C-compatible interface. The I²C-compatible interface allows

programming of serializer or deserializer devices from

a

local host controller. In addition, the

serializer/deserializer devices incorporate a bidirectional control channel (BCC) that allows communication

between serializer/deserializer as well as remote I2C slave devices.

The bidirectional control channel (BCC) is implemented via embedded signaling in the high-speed forward

channel (serializer to deserializer) combined with lower speed signaling in the reverse channel (deserializer to

serializer). Through this interface, the BCC provides a mechanism to bridge I²C transactions across the serial link

from one I²C bus to another. The implementation allows for arbitration with other I²C compatible masters at either

side of the serial link.

The DS90UB924-Q1 deserializer is intended for use with DS90UB921-Q1, DS90UB925Q-Q1, or DS90UB927Q-

Q1 serializers, but is also backward compatible with DS90UR905Q and DS90UR907Q FPD-Link III serializers.

7.2 Functional Block Diagram

OEN

REGULATOR

OSS_SEL

CMF

TxOUT3±

TxOUT2±

RIN+

TxOUT1±

RIN-

TxOUT0±

TxCLKOUT±

8

I2S / GPIO

Error

Detector

BISTEN

BISTC

PASS

LFMODE

MAPSEL

Clock and

Data

Recovery

PDB

SCL

SCA

LOCK

Timing and

Control

IDx

MODE_SEL

16

DS90UB924-Q1

www.ti.com.cn

ZHCSEY4 –APRIL 2016

7.3 Feature Description

7.3.1 High-Speed Forward Channel Data Transfer

The high-speed Forward Channel is composed of a 35-bit frame containing video data, sync signals, I²C, and I2S

audio transmitted from serializer to deserializer. Figure 19 shows the serial stream PCLK cycle. This data

payload is optimized for signal transmission over an AC-coupled link. Data is randomized, DC-balanced and

scrambled.

C0

C1

Figure 19. FPD-Link III Serial Stream

The device supports pixel clock ranges of 5 MHz to 15 MHz (LFMODE=1) and 15 MHz to 96 MHz (LFMODE=0).

This corresponds to an application payload rate range of 155 Mbps to 2.976 Gbps, with an actual line rate range

of 525 Mbps to 3.36 Gbps.

7.3.2 Low-Speed Back Channel Data Transfer

The low-speed back channel of the DS90UB924-Q1 provides bidirectional communication between the display

and host processor. The back channel control data is transferred over the single serial link along with the high-

speed forward data, DC balance coding, and embedded clock information. Together, the forward channel and

back channel form the bidirectional control channel (BCC). This architecture provides a backward path across

the serial link together with a high speed forward channel. The back channel contains the I²C, CRC and 4 bits of

standard GPIO information with 10 Mbps line rate.

7.3.3 Backward Compatible Mode

The DS90UB924-Q1 is also backward compatible to the DS90UR905Q and DS90UR907Q for PCLK frequencies

ranging from 15 MHz to 65 MHz. The deserializer receives 28 bits of data over a single serial FPD-Link III pair

operating at a payload rate of 120 Mbps to 1.8 Gbps, corresponding to a line rate of 140 Mbps to 2.1 Gbps. The

backward compatibility configuration can be selected through the MODE_SEL pin or programmed through the

device control registers (Table 8). The bidirectional control channel, bidirectional GPIOs, I2S, and interrupt

(INTB) are not active in this mode. However, local I²C access to the serializer is still available.

7.3.4 Input Equalization

An FPD-Link III input adaptive equalizer provides compensation for transmission medium losses and reduces

medium-induced deterministic jitter.

The adaptive equalizer may be set to a Long Cable Mode (LCBL), using the MODE_SEL pin (Table 6). This

mode is typically used with longer cables where it may be desirable to start adaptive equalization from a higher

default gain. In this mode, the device attempts to lock from a minimum floor AEQ value, defined by a value

stored in the control registers (Table 8).

7.3.5 Common Mode Filter Pin (CMF)

The deserializer provides access to the center tap of the internal CML termination. A 0.1 μF capacitor must be

connected from this pin to GND for additional common-mode filtering of the differential pair (Figure 37). This

increases noise rejection capability in high-noise environments.

7.3.6 Power Down (PDB)

The deserializer has a PDB input pin to enable or power down the device. This pin may be controlled by an

external device, or through V_DDIO, where V_DDIO= 3 V to 3.6 V or V_DD33. To save power, disable the link when the

display is not needed (PDB = LOW). Ensure that this pin is not driven HIGH before V_DD33and V_DDIOhave

reached final levels. When PDB is driven low, ensure that the pin is driven to 0 V for at least 1.5 ms before

releasing or driving high (See Recommended Operating Conditions ). If the PDB is pulled up to V_DDIO= 3.0 V to

3.6 V or V_DD33directly, a 10 kΩ pullup resistor and a >10 µF capacitor to ground are required (See Figure 37).

Toggling PDB low POWER DOWN the device and RESET all control registers to default. During this time, PDB

must be held low for a minimum of 2 ms (see AC Electrical Characteristics).

17

DS90UB924-Q1

ZHCSEY4 –APRIL 2016

www.ti.com.cn

Feature Description (continued)

7.3.7 Video Control Signals

The video control signal bits embedded in the high-speed FPD-Link (OpenLDI) LVDS are subject to certain

limitations relative to the video pixel clock period (PCLK). By default, the device applies a minimum pulse width

filter on these signals to help eliminate spurious transitions.

Normal Mode Control Signals (VS, HS, DE) have the following restrictions:

•

Horizontal Sync (HS): The video control signal pulse width must be 3 PCLKs or longer when the Control

Signal Filter (register bit 0x03[4]) is enabled (default). Disabling the Control Signal Filter removes this

restriction (minimum is 1 PCLK). See Table 8. HS can have at most two transitions per 130 PCLKs.

•

Vertical Sync (VS): The video control signal pulse is limited to 1 transition per 130 PCLKs. Thus, the minimum

pulse width is 130 PCLKs.

Data Enable Input (DE): The video control signal pulse width must be 3 PCLKs or longer when the Control

Signal Filter (register bit 0x03[4]) is enabled (default). Disabling the Control Signal Filter removes this

restriction (minimum is 1 PCLK). See Table 8. DE can have at most two transitions per 130 PCLKs.

7.3.8 EMI Reduction Features

7.3.8.1 LVCMOS VDDIO Option

The 1.8 V/3.3 V LVCMOS inputs and outputs are powered from a separate VDDIO supply pin to offer

compatibility with external system interface signals. Note: When configuring the V_DDIOpower supplies, all the

single-ended control input pins (except PDB) for device need to scale together with the same operating V_DDIO

levels. If V_DDIOis selected to operate in the 3.0 V to 3.6 V range, V_DDIOmust be operated within 300 mV of V_DD33

(See Recommended Operating Conditions).

7.3.9 Built In Self Test (BIST)

An optional At-speed Built-In Self Test (BIST) feature supports testing of the high-speed serial link and the low-

speed back channel without external data connections. This is useful in the prototype stage, equipment

production, in-system test, and system diagnostics.

7.3.9.1 BIST Configuration and Status

The BIST mode is enabled at the deserializer by pin (BISTEN) or BIST configuration register. The test may

select either an external PCLK or the 33 MHz internal oscillator clock (OSC) frequency. In the absence of PCLK,

the user can select the internal OSC frequency at the deserializer through the BISTC pin or BIST configuration

register.

When BIST is activated at the deserializer, a BIST enable signal is sent to the serializer through the back

channel. The serializer outputs a test pattern and drives the link at speed. The deserializer detects the test

pattern and monitors it for errors. The deserializer PASS output pin toggles to flag each frame received

containing one or more errors. The serializer also tracks errors indicated by the CRC fields in each back channel

frame.

The BIST status can be monitored real time on the deserializer PASS pin, with each detected error resulting in a

half pixel clock period toggled LOW. After BIST is deactivated, the result of the last test is held on the PASS

output until reset (new BIST test or Power Down). A high on PASS indicates NO ERRORS were detected. A Low

on PASS indicates one or more errors were detected. The duration of the test is controlled by the pulse width

applied to the deserializer BISTEN pin. LOCK status is valid throughout the entire duration of BIST.

See Figure 20 for the BIST mode flow diagram.

18

DS90UB924-Q1

www.ti.com.cn

ZHCSEY4 –APRIL 2016

Feature Description (continued)

7.3.9.1.1 Sample BIST Sequence

1. BIST Mode is enabled via the BISTEN pin of Deserializer. The desired clock source is selected through the

deserializer BISTC pin.

2. The serializer is awakened through the back channel if it is not already on. An all zeros pattern is balanced,

scrambled, randomized, and sent through the FPD-Link III interface to the deserializer. Once the serializer

and the deserializer are in BIST mode and the deserializer acquires LOCK, the PASS pin of the deserializer

goes high, and BIST starts checking the data stream. If an error in the payload (1 to 35) is detected, the

PASS pin switches low for one half of the clock period. During the BIST test, the PASS output can be

monitored and counted to determine the payload error rate.

3. To stop BIST mode, set the BISTEN pin LOW. The deserializer stops checking the data, and the final test

result is held on the PASS pin. If the test ran error free, the PASS output remains HIGH. If there one or more

errors were detected, the PASS output outputs constant LOW. The PASS output state is held until a new

BIST is run, the device is RESET, or the device is powered down. BIST duration is user-controlled and may

be of any length.

The link returns to normal operation after the deserializer BISTEN pin is low. Figure 21 shows the waveform

diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple errors. In

most cases it is difficult to generate errors due to the robustness of the link (differential data transmission, and so

forth.), thus they may be introduced by greatly extending the cable length, faulting the interconnect medium, or

reducing signal condition enhancements (Rx equalization).

Normal

Step 1: DES in BIST

BIST

Wait

Step 2: Wait, SER in BIST

BIST

start

Step 3: DES in Normal

Mode - check PASS

BIST

stop

Step 4: DES/SER in Normal

Figure 20. BIST Mode Flow Diagram

7.3.9.2 Forward Channel and Back Channel Error Checking

The deserializer, on locking to the serial stream, compares the recovered serial stream with all zeroes and

records any errors in status registers. Errors are also dynamically reported on the PASS pin of the deserializer.

Forward channel errors may also be read from register 0x25 ( Table 8).

The back-channel data is checked for CRC errors once the serializer locks onto the back-channel serial stream,

as indicated by link detect status (register bit 0x1C[0] - Table 8). CRC errors are recorded in an 8-bit register in

the deserializer. The register is cleared when the serializer enters the BIST mode. As soon as the serializer

enters BIST mode, the functional mode CRC register starts recording any back channel CRC errors. The BIST

mode CRC error register is active in BIST mode only and keeps the record of the last BIST run until cleared or

the serializer enters BIST mode again.

19

DS90UB924-Q1

ZHCSEY4 –APRIL 2016

www.ti.com.cn

Feature Description (continued)

BISTEN

(DES)

TxCLKOUT

TxOUT[3:0]

7 bits/frame

DATA

(internal)

PASS

Prior Result

PASS

FAIL

X = bit error(s)

DATA

(internal)

X

PASS

BIST

Result

Held

Normal

SSO

Normal

BIST Test

BIST Duration

Figure 21. BIST Waveforms

7.3.10 Internal Pattern Generation

The DS90UB924-Q1 deserializer features an internal pattern generator. It allows basic testing and debugging of

an integrated panel. The test patterns are simple and repetitive and allow for a quick visual verification of panel

operation. As long as the device is not in power down mode, the test pattern is displayed even if no input is

applied. If no clock is received, the test pattern can be configured to use a programmed oscillator frequency. For

detailed information, refer to TI Application Note: (AN-2198).

7.3.10.1 Pattern Options

The DS90UB924-Q1 deserializer pattern generator is capable of generating 17 default patterns for use in basic

testing and debugging of panels. Each pattern can be inverted using register bits (see Table 8). The 17 default

patterns are listed as follows:

1. White/Black (default/inverted)

2. Black/White

3. Red/Cyan

4. Green/Magenta

5. Blue/Yellow

6. Horizontally Scaled Black to White/White to Black

7. Horizontally Scaled Black to Red/Cyan to White

8. Horizontally Scaled Black to Green/Magenta to White

9. Horizontally Scaled Black to Blue/Yellow to White

10. Vertically Scaled Black to White/White to Black

11. Vertically Scaled Black to Red/Cyan to White

12. Vertically Scaled Black to Green/Magenta to White

13. Vertically Scaled Black to Blue/Yellow to White

14. Custom Color / Inverted configured in PGRS

15. Black-White/White-Black Checkerboard (or custom checkerboard color, configured in PGCTL)

16. YCBR/RBCY VCOM pattern, orientation is configurable from PGCTL

17. Color Bars (White, Yellow, Cyan, Green, Magenta, Red, Blue, Black) – Note: not included in the auto-

scrolling feature

20

DS90UB924-Q1

www.ti.com.cn

ZHCSEY4 –APRIL 2016

Feature Description (continued)

7.3.10.2 Color Modes

By default, the Pattern Generator operates in 24-bit color mode, where all bits of the red, green, and blue outputs

are enabled. 18-bit color mode can be activated from the configuration registers (Table 8). In 18-bit mode, the 6

most significant bits (bits 7-2) of the Red, Green, and Blue outputs are enabled; the 2 least significant bits are 0.

7.3.10.3 Video Timing Modes

The Pattern Generator has two video timing modes – external and internal. In external timing mode, the Pattern

Generator detects the video frame timing present on the DE and VS inputs. If Vertical Sync signaling is not

present on VS, the Pattern Generator determines Vertical Blank by detecting when the number of inactive pixel

clocks (DE = 0) exceeds twice the detected active line length. In internal timing mode, the Pattern Generator

uses custom video timing as configured in the control registers. The internal timing generation may also be

driven by an external clock. By default, external timing mode is enabled. Internal timing or Internal timing with

External Clock are enabled by the control registers (Table 8). If internal clock generation is used, register 0x39

bit 1 must be set.

7.3.10.4 External Timing

In external timing mode, the pattern generator passes the incoming DE, HS, and VS signals unmodified to the

video control outputs after a two-pixel clock delay. It extracts the active frame dimensions from the incoming

signals in order to properly scale the brightness patterns. If the incoming video stream does not use the VS

signal, the Pattern Generator determines the Vertical Blank time by detecting a long period of pixel clocks without

DE asserted.

7.3.10.5 Pattern Inversion

The Pattern Generator also incorporates a global inversion control, located in the PGCFG register, which causes

the output pattern to be bitwise-inverted. For example, the full-screen Red pattern becomes full-screen cyan, and

the Vertically Scaled Black to Green pattern becomes Vertically Scaled White to Magenta.

7.3.10.6 Auto Scrolling

The Pattern Generator supports an Auto-Scrolling mode, in which the output pattern cycles through a list of

enabled pattern types. A sequence of up to 16 patterns may be defined in the registers. The patterns may

appear in any order in the sequence and may also appear more than once.

7.3.10.7 Additional Features

Additional pattern generator features can be accessed through the Pattern Generator Indirect Register Map. It

consists of the Pattern Generator Indirect Address (PGIA — Table 8) and the Pattern Generator Indirect Data

(PGID — Table 8).

7.3.11 Serial Link Fault Detect

The DS90UB924-Q1 can detect fault conditions in the FPD-Link III interconnect. If a fault condition occurs, the

Link Detect Status is 0 (cable is not detected) on bit 0 of address 0x1C (Table 8). The device detects any of the

following conditions:

1. Cable open

2. RIN+ to - short

3. RIN+ to GND short

4. RIN- to GND short

5. RIN+ to battery short

6. RIN- to battery short

7. Cable is linked incorrectly (RIN+/RIN- connections reversed)

21

DS90UB924-Q1

ZHCSEY4 –APRIL 2016

www.ti.com.cn

Feature Description (continued)

NOTE

The device detects any of the above conditions, but does not report specifically which one

has occurred.

7.3.12 Oscillator Output

The deserializer provides an optional TxCLKOUT± output when the input clock (serial stream) has been lost.

This is based on an internal oscillator and may be controlled from register 0x02, bit 5 (OSC Clock Output Enable)

Table 8.

7.3.13 Interrupt Pin (INTB / INTB_IN)

1. Read HDCP_ISR Register 0xC7. (Table 8)

2. On the serializer, set register (ICR) 0xC6[5] = 1 and 0xC6[0] = 1 to configure the interrupt.

3. On the serializer, read from ISR register 0xC7 to arm the interrupt for the first time.

4. When INTB_IN is set LOW, the INTB pin on the serializer also pulls low, indicating an interrupt condition.

5. The external controller detects INTB = LOW and reads the ISR register to determine the interrupt source.

Reading this register also clears and resets the interrupt.

The INTB_IN signal is sampled and required approximately 8.6 μs of the minimum setup and hold time.

8.6 μs = 30 bit per back channel frame / (5 Mbps rate × ±30% Variation) = 30 / (5E6 × 0.7)

Note that -30% is the worst case.

7.3.14 General-Purpose I/O

7.3.14.1 GPIO[3:0]

In normal operation, GPIO[3:0] may be used as general purpose IOs in either forward channel (outputs) or back

channel (inputs) mode. GPIO modes may be configured from the registers (Table 8). GPIO[1:0] are dedicated

pins and GPIO[3:2] are shared with I2S_DC and I2S_DD respectively. Note: if the DS90UB924-Q1 is paired with

a DS90UB921-Q1 or DS90UB925Q-Q1 serializer, the devices must be configured into 18-bit mode to allow

usage of GPIO pins on the serializer. To enable 18-bit mode, set serializer register 0x12[2] = 1. 18-bit mode is

auto-loaded into the deserializer from the serializer. See Table 1 for GPIO enable and configuration.

Table 1. DS90UB921-Q1/DS90UB925Q-Q1 GPIO Enable and Configuration

DESCRIPTION

DEVICE

FORWARD CHANNEL

BACK CHANNEL

GPIO3

DS90UB921-Q1/

DS90UB925Q-Q1

0x0F = 0x03

0x0F = 0x05

DS90UB924-Q1

0x1F = 0x05

0x0E = 0x30

0x1F = 0x03

0x0E = 0x50

GPIO2

DS90UB921-Q1/

DS90UB925Q-Q1

DS90UB924-Q1

0x1E = 0x50

N/A

0x1E = 0x30

0x0E = 0x05

GPIO1/GPIO1

(SER/DES)

DS90UB921-Q1/

DS90UB925Q-Q1

DS90UB924-Q1

N/A

0x1E = 0x03

N/A

GPO_REG5/GPIO1

(SER/DES)

DS90UB921-Q1/

DS90UB925Q-Q1

0x10 = 0x03

DS90UB924-Q1

0x1E = 0x05

N/A

GPIO0/GPIO0

(SER/DES)

DS90UB921-Q1/

DS90UB925Q-Q1

0x0D = 0x05

DS90UB924-Q1

N/A

0x1D = 0x03

N/A

GPO_REG4/GPIO0

(SER/DES)

DS90UB921-Q1/

DS90UB925Q-Q1

0x0F = 0x30

DS90UB924-Q1

0x1D = 0x05

N/A

22

DS90UB924-Q1

www.ti.com.cn

ZHCSEY4 –APRIL 2016

Table 2. DS90UB927Q-Q1 GPIO Enable and Configuration

DESCRIPTION

DEVICE

FORWARD CHANNEL

0x0F = 0x03

BACK CHANNEL

GPIO3

GPIO2

GPIO1

GPIO0

DS90UB927Q-Q1

DS90UB924-Q1

DS90UB927Q-Q1

DS90UB924-Q1

DS90UB927Q-Q1

DS90UB924-Q1

DS90UB927Q-Q1

DS90UB924-Q1

0x0F = 0x05

0x1F = 0x03

0x0E = 0x50

0x1E = 0x30

0x0E = 0x05

0x1E = 0x03

0x0D = 0x05

0x1D = 0x03

0x1F = 0x05

0x0E = 0x30

0x1E = 0x50

0x0E = 0x03

0x1E = 0x05

0x0D = 0x03

0x1D = 0x05

Note: GPO_REG4 of the DS90UB921-Q1 or DS90UB925-Q1 can be used as a forward channel GPIO,

outputting on GPIO0 of DS90UB924-Q1. This can be set as follows:

•

Set DS90UB921-Q1 or DS90UB925-Q1 in 18-bit mode by mode pin = 1 or by register 0x12[2] = 1.

Set DS90UB924-Q1 register 0x1D[0] = 1 and 0x1D[2] = 1; this will enable GPIO0 of DS90UB924-Q1 as

output.

•

Set DS90UB921-Q1 or DS90UB925-Q1 register 0x0F[4] = 1 and 0x0F[5] = 1; this will enable GPO_REG4 of

DS90UB921-Q1 or DS90UB925-Q1 as input.

Similarly GPO_REG5 of DS90UB921-Q1 or DS90UB925-Q1 can output to GPIO1 of DS90UB924-Q1:

•

Set DS90UB921-Q1 or DS90UB925-Q1 in 18-bit mode by mode pin = 1 or by register 0x12[2] = 1.

Set DS90UB924-Q1 register 0x1E[0] = 1 and 0x1E[2] = 1; this will enable GPIO1 of DS90UB924-Q1 as

output.

•

Set DS90UB921-Q1 or DS90UB925-Q1 register 0x10[0] = 1 and 0x10[1] = 1; this will enable GPO_REG5

DS90UB921-Q1 or DS90UB925-Q1 as input.

The input value present on GPIO[3:0] may also be read from register or configured to local output mode

(Table 8).

7.3.14.2 GPIO[8:5]

GPIO_REG[8:5] are register-only GPIOs and may be programmed as outputs or read as inputs through local

register bits only. Where applicable, these bits are shared with I2S pins and override I2S input if enabled into

GPIO_REG mode. See Table 3 for GPIO enable and configuration.

Note: Local GPIO value may be configured and read either through local register access, or remote register

access through the Low-Speed Bidirectional Control Channel. Configuration and state of these pins are not

transported from serializer to deserializer as is the case for GPIO[3:0].

Table 3. GPIO_REG and GPIO Local Enable and Configuration

DESCRIPTION

REGISTER CONFIGURATION

0x21 = 0x01

FUNCTION

Output, L

GPIO_REG8

0x21 = 0x09

Output, H

0x21 = 0x03

Input, Read: 0x6F[0]

Output, L

GPIO_REG7

GPIO_REG6

GPIO_REG5

0x21 = 0x01

0x21 = 0x09

Output, H

0x21 = 0x03

Input, Read: 0x6E[7]

Output, L

0x20 = 0x01

0x20 = 0x09

Output, H

0x20 = 0x03

Input, Read: 0x6E[6]

Output, L

0x20 = 0x01

0x20 = 0x09

Output, H

0x20 = 0x03

Input, Read: 0x6E[5]

23

DS90UB924-Q1

ZHCSEY4 –APRIL 2016

www.ti.com.cn

Table 3. GPIO_REG and GPIO Local Enable and Configuration (continued)

DESCRIPTION

REGISTER CONFIGURATION

0x1F = 0x01

FUNCTION

Output, L

GPIO3

0x1F = 0x09

Output, H

0x1F = 0x03

Input, Read: 0x6E[3]

Output, L

GPIO2

GPIO1

GPIO0

0x1E = 0x01

0x1E = 0x09

Output, H

0x1E = 0x03

Input, Read: 0x6E[2]

Output, L

0x1E = 0x01

0x1E = 0x09

Output, H

0x1E = 0x03

Input, Read: 0x6E[1]

Output, L

0x1D = 0x01

0x1D = 0x09

Output, H

0x1D = 0x03

Input, Read: 0x6E[0]

7.3.15 I2S Audio Interface

The DS90UB924-Q1 deserializer features six I2S output pins that, when paired with a DS90UB927Q-Q1

serializer, supports surround-sound audio applications. The bit clock (I2S_CLK) supports frequencies between 1

MHz and the smaller of < PCLK/4 or < 13 MHz. Four I2S data outputs carry two channels of I2S-formatted digital

audio each, with each channel delineated by the word select (I2C_WC) input. The I2S audio interface is not

available in Backwards Compatibility Mode (BKWD = 1).

Deserializer

System Clock

MCLK

Bit Clock

I2S_CLK

I2S Receiver

4

Word Select

Data

I2S_WC

I2S_Dx

Figure 22. I2S Connection Diagram

I2S_WC

I2S_CLK

MSB

LSB

MSB

LSB

I2S_Dx

Figure 23. I2S Frame Timing Diagram

When paired with a DS90UB921-Q1 or DS90UB925Q-Q1, the DS90UB924-Q1 I2S interface supports a single

I2S data output through I2S_DA (24-bit video mode), or two I2S data outputs through I2S_DA and I2S_DB (18-

bit video mode).

7.3.15.1 I2S Transport Modes

By default, packetized audio is received during video blanking periods in dedicated data island transport frames.

The transport mode is set in the serializer and auto-loaded into the deserializer by default. The audio

configuration may be disabled from control registers if Forward Channel Frame Transport of I2S data is desired.

In frame transport, only I2S_DA is received to the DS90UB924-Q1 deserializer. Surround Sound Mode, which

transmits all four I2S data inputs (I2S_D[D:A]), may only be operated in Data Island Transport mode. This mode

is only available when connected to a DS90UB927Q-Q1 serializer. If connected to a DS90UB921-Q1 or

DS90UB925Q-Q1 serializer, only I2S_DA and I2S_DB may be received.

24

DS90UB924-Q1

www.ti.com.cn

ZHCSEY4 –APRIL 2016

7.3.15.2 I2S Repeater

I2S audio may be fanned-out and propagated in the repeater application. By default, data is propagated via data

island transport on the FPD-Link (OpenLDI) interface during the video blanking periods. If frame transport is

desired, connect the I2S pins from the deserializer to all serializers. Activating surround sound at the top-level

serializer automatically configures downstream serializers and deserializers for surround-sound transport utilizing

Data Island Transport. If 4-channel operation utilizing I2S_DA and I2S_DB only is desired, this mode must be

explicitly set in each serializer and deserializer control register throughout the repeater tree (Table 8).

A DS90UB924-Q1 deserializer configured in repeater mode may also regenerate I2S audio from its I2S input

pins in lieu of Data Island frames. See Figure 31 and the I2C control registers (Table 8) for additional details.

7.3.15.3 I2S Jitter Cleaning

The DS90UB924-Q1 features a standalone PLL to clean the I2S data jitter, supporting high-end car audio

systems. If I2S_CLK frequency is less than 1 MHz, this feature must be disabled through register 0x2B[7]. See

Table 8.

7.3.15.4 MCLK

The deserializer has an I2S Master Clock Output (MCLK). It supports ×1, ×2, or ×4 of I2S CLK Frequency. When

the I2S PLL is disabled, the MCLK output is off. Table 4 covers the range of I2S sample rates and MCLK

frequencies. By default, all the MCLK output frequencies are ×2 of the I2S CLK frequencies. The MCLK

frequencies can also be enabled through the register bits 0x3A[6:4] (I2S DIVSEL), shown in Table 8. To select

desired MCLK frequency, write 0x3A[7], then write to bit [6:4] accordingly.

Table 4. Audio Interface Frequencies

SAMPLE RATE

I2S DATA WORD SIZE (BITS) I2S_CLK (MHz)

MCLK OUTPUT (MHz)

REGISTER 0x3A[6:4]'b

(kHz)

I2S_CLK x1

I2S_CLK x2

I2S_CLK x4

I2S_CLK x1

I2S_CLK x2

I2S_CLK x4

I2S_CLK x1

I2S_CLK x2

I2S_CLK x4

I2S_CLK x1

I2S_CLK x2

I2S_CLK x4

I2S_CLK x1

I2S_CLK x2

I2S_CLK x4

000

001

010

000

001

010

000

001

010

001

010

011

010

011

100

32

1.024

44.1

48

1.4112

16

1.536

3.072

6.144

96

192

25

DS90UB924-Q1

ZHCSEY4 –APRIL 2016

www.ti.com.cn

Table 4. Audio Interface Frequencies (continued)

SAMPLE RATE

(kHz)

I2S DATA WORD SIZE (BITS) I2S_CLK (MHz)

MCLK OUTPUT (MHz)

REGISTER 0x3A[6:4]'b

I2S_CLK x1

I2S_CLK x2

I2S_CLK x4

I2S_CLK x1

I2S_CLK x2

I2S_CLK x4

I2S_CLK x1

I2S_CLK x2

I2S_CLK x4

I2S_CLK x1

I2S_CLK x2

I2S_CLK x4

I2S_CLK x1

I2S_CLK x2

I2S_CLK x4

I2S_CLK x1

I2S_CLK x2

I2S_CLK x4

I2S_CLK x1

I2S_CLK x2

I2S_CLK x4

I2S_CLK x1

I2S_CLK x2

I2S_CLK x4

I2S_CLK x1

I2S_CLK x2

I2S_CLK x4

I2S_CLK x1

I2S_CLK x2

I2S_CLK x4

000

001

010

001

010

011

001

010

011

010

011

100

011

100

101

001

010

011

001

010

011

001

010

011

010

011

100

011

100

110

32

44.1

48

1.536

2.117

2.304

4.608

9.216

2.048

2.8224

3.072

6.144

12.288

24

96

192

32

44.1

48

32

96

192

7.3.16 AV Mute Prevention

The DS90UB924-Q1 may inadvertently enter the AV MUTE state if the serializer sends video data during

blanking period (DE = L) with a specific data pattern (24’h666666). Once the device enters the AV MUTE

state, the device mutes both audio and video outputs resulting in a black display screen. Setting the gate DE

Register 0x04[4] on the serializer will prevent video signals from being sent during the blanking interval. This

will ensure AV MUTE mode is not entered during normal operation

If unexpected AV MUTE state is seen, it is recommended to verify checking the data path control setting of

the paired Serializer. This setting is not accessible from DS90UB924-Q1.

7.3.17 OEN Toggling Limitation

OEN must be enabled LVDS outputs after PDB turns to high state and the internal circuit is stabled. Since OEN

function is asynchronous signal to internal digital blocks, repeatedly OEN toggling may result in horizontal pixel

shift at the LVDS output. To avoid this, recommend to reset by programming Register 0x01[0] for digital blocks

after OEN turns to ON state.

26

DS90UB924-Q1

www.ti.com.cn

ZHCSEY4 –APRIL 2016

7.4 Device Functional Modes

7.4.1 Clock and Output Status

When PDB is driven HIGH, the CDR PLL begins locking to the serial input, and LOCK is TRI-STATE or LOW

(depending on the value of the OEN setting). After the deserializer completes its lock sequence to the input serial

data, the LOCK output is driven HIGH, indicating valid data and clock recovered from the serial input is available

on the LVCMOS and LVDS outputs. The state of the outputs is based on the OEN and OSS_SEL setting

(Table 5) or register bit (Table 8).

Table 5. Output State Table

INPUTS

OEN

OUTPUTS

SERIAL

INPUT

TxCLKOUT/Tx

OUT[3:0]

PDB

OSS_SEL

LOCK

PASS

DATA/GPIO/I2S

X

L

H

X

L

X

L

Z

L

Z

L

Z

L

Z

L or H

H

L/OSC (Register

EN)

Static

H

L

Static

Active

H

L

Previous Status

L

H

Valid

7.4.2 FPD-Link (OpenLDI) Input Frame and Color Bit Mapping Select

The DS90UB924-Q1 can be configured to output 24-bit color (RGB888) or 18-bit color (RGB666) with 2 different

mapping schemes, shown in Figure 24, or MSBs on TxOUT[3], shown in Figure 25. Each frame corresponds to a

single pixel clock (PCLK) cycle. The LVDS clock output from TxCLKOUT± follows a 4:3 duty cycle scheme, with

each 28-bit pixel frame starting with two LVDS bit clock periods high, three low, and ending with two high. The

mapping scheme is controlled by MAPSEL pin or by Register (Table 8).

TxCLKOUT

Previous cycle

Current cycle

B[1]

(bit 26)

B[0]

(bit 25)

G[1]

(bit 24)

G[0]

(bit 23)

R[1]

(bit 22)

R[0]

(bit 21)

TxOUT3

TxOUT2

DE

(bit 20)

VS

(bit 19)

HS

(bit 18)

B[7]

(bit 17)

B[6]

(bit 16)

B[5]

(bit 15)

B[4]

(bit 14)

B[3]

(bit 13)

B[2]

(bit 12)

G[7]

(bit 11)

G[6]

(bit 10)

G[5]

(bit 9)

G[4]

(bit 8)

G[3]

(bit 7)

TxOUT1

TxOUT0

G[2]

(bit 6)

R[7]

(bit 5)

R[6]

(bit 4)

R[5]

(bit 3)

R[4]

(bit 2)

R[3]

(bit 1)

R[2]

(bit 0)

Figure 24. 24-bit Color FPD-Link (OpenLDI) Mapping: LSBs on TxOUT3 (MAPSEL=L)

27

DS90UB924-Q1

ZHCSEY4 –APRIL 2016

www.ti.com.cn

TxCLKOUT

Previous cycle

Current cycle

B[7]

(bit 26)

B[6]

(bit 25)

G[7]

(bit 24)

G[6]

(bit 23)

R[7]

(bit 22)

R[6]

(bit 21)

TxOUT3

TxOUT2

DE

(bit 20)

VS

(bit 19)

HS

(bit 18)

B[5]

(bit 17)

B[4]

(bit 16)

B[3]

(bit 15)

B[2]

(bit 14)

B[1]

(bit 13)

B[0]

(bit 12)

G[5]

(bit 11)

G[4]

(bit 10)

G[3]

(bit 9)

G[2]

(bit 8)

G[1]

(bit 7)

TxOUT1

TxOUT0

G[0]

(bit 6)

R[5]

(bit 5)

R[4]

(bit 4)

R[3]

(bit 3)

R[2]

(bit 2)

R[1]

(bit 1)

R[0]

(bit 0)

Figure 25. 24-bit Color FPD-Link (OpenLDI) Mapping: MSBs on TxOUT3 (MAPSEL=H)

TxCLKOUT

Previous cycle

Current cycle

TxOUT3

TxOUT2

DE

(bit 20)

VS

(bit 19)

HS

(bit 18)

B[5]

(bit 17)

B[4]

(bit 16)

B[3]

(bit 15)

B[2]

(bit 14)

B[1]

(bit 13)

B[0]

(bit 12)

G[5]

(bit 11)

G[4]

(bit 10)

G[3]

(bit 9)

G[2]

(bit 8)

G[1]

(bit 7)

TxOUT1

TxOUT0

G[0]

(bit 6)

R[5]

(bit 5)

R[4]

(bit 4)

R[3]

(bit 3)

R[2]

(bit 2)

R[1]

(bit 1)

R[0]

(bit 0)

Figure 26. 18-bit Color FPD-Link (OpenLDI) Mapping (MAPSEL = L)

TxCLKOUT

Previous cycle

Current cycle

B[5]

(bit 26)

B[4]

(bit 25)

G[5]

(bit 24)

G[4]

(bit 23)

R[5]

(bit 22)

R[4]

(bit 21)

TxOUT3

TxOUT2

DE

(bit 20)

VS

(bit 19)

HS

(bit 18)

B[3]

(bit 17)

B[2]

(bit 16)

B[1]

(bit 15)

B[0]

(bit 14)

G[3]

(bit 11)

G[2]

(bit 10)

G[1]

(bit 9)

G[0]

(bit 8)

TxOUT1

TxOUT0

R[3]

(bit 5)

R[2]

(bit 4)

R[1]

(bit 3)

R[0]

(bit 2)

Figure 27. 18-bit Color FPD-Link (OpenLDI) Mapping (MAPSEL = H)

28

DS90UB924-Q1

www.ti.com.cn

ZHCSEY4 –APRIL 2016

7.4.3 Low Frequency Optimization (LFMODE)

The LFMODE is set via register (Table 8) or by the LFMODE Pin. This mode optimizes device operation for

lower input data clock ranges supported by the serializer. If LFMODE is Low (LFMODE=0, default), the

TxCLKOUT± PCLK frequency is between 15 MHz and 96 MHz. If LFMODE is High (LFMODE=1), the

TxCLKOUT± frequency is between 5 MHz and <15 MHz. Note: when the device LFMODE is changed, a PDB

reset is required. When LFMODE is high (LFMODE=1), the line rate relative to the input data rate is multiplied by

four. Thus, for the operating range of 5 MHz to <15 MHz, the line rate is 700 Mbps to <2.1 Gbps with an effective

data payload of 175 Mbps to 525 Mbps. Note: for Backwards Compatibility Mode (BKWD=1), the line rate relative

to the input data rate remains the same.

7.4.4 Mode Select (MODE_SEL)

Device configuration may be done via the MODE_SEL pin or via register (Table 7). A pullup resistor and a

pulldown resistor of suggested values may be used to set the voltage ratio of the MODE_SEL input (VR4) and

V_DD33to select one of the 9 possible selected modes. See Figure 28 and Table 6.

V

DD33

R

3

V_R4

MODE_SEL

Deserializer

R

4

Figure 28. MODE_SEL Connection Diagram

Table 6. Configuration Select (MODE_SEL)

Suggested

Resistor R₃

(kΩ, 1% tol)

Suggested

Resistor R₄

(kΩ, 1% tol)

Ideal Ratio

Ideal

V_R4(V)

NO.

REPEAT

BKWD

I2S_B

LCBL

(V_R4/V_DD33

)

1

2

3

4

5

6

7

8

9

0

OPEN

294

255

267

255

226

205

162

124

40.2

49.9

76.8

102

130

165

191

210

L

H

L

0.120

0.164

0.223

0.286

0.365

0.446

0.541

0.629

0.397

0.540

0.737

0.943

1.205

1.472

1.786

2.075

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

7.4.5 Repeater Configuration

The supported Repeater application provides a mechanism to extend transmission over multiple links to multiple

display devices.

For the repeater application, this document refers to the DS90UB927Q-Q1 as the Transmitter (TX), and refers to

the DS90UB924-Q1 as the Receiver (RX). Figure 29 shows the maximum configuration supported for Repeater

implementations. Two levels of Repeaters are supported with a maximum of three Transmitters per Receiver.

29

DS90UB924-Q1

ZHCSEY4 –APRIL 2016

www.ti.com.cn

1:3 Repeater

Display

RX

TX

RX

TX

Source

TX

RX

TX

Display

RX

1:3 Repeater

Display

RX

TX

RX

Display

RX

1:3 Repeater

Display

RX

TX

RX

Display

RX

Figure 29. Maximum Repeater Application

In a repeater application, the I²C interface at each TX and RX is configured to transparently pass I²C

communications upstream or downstream to any I²C device within the system. This includes a mechanism for

assigning alternate IDs (Slave Aliases) to downstream devices in the case of duplicate addresses.

Repeater Node

Transmitter

Downstream

Receiver

or

Repeater

I2C

Slave

I2C

Master

Upstream

Transmitter

FPD-Link

(LVDS)

Transmitter

Receiver

I2S Audio

Downstream

Receiver

or

I2C

Slave

Repeater

FPD-Link III interfaces

Figure 30. 1:2 Repeater Configuration

30

DS90UB924-Q1

www.ti.com.cn

ZHCSEY4 –APRIL 2016

7.4.5.1 Repeater Connections

The Repeater requires the following connections between the Receiver and each Transmitter (Figure 31).

1. Video Data – Connect all FPD-Link (OpenLDI) data and clock pairs

2. I²C – Connect SCL and SDA signals. Both signals must be pulled up to V_DD33or V_DDIO= 3.0 V to 3.6 V with

4.7-kΩ resistors.

3. Audio (optional) – Connect I2S_CLK, I2S_WC, and I2S_Dx signals.

4. IDx pin – Each Transmitter and Receiver must have an unique I²C address.

5. REPEAT & MODE_SEL pins — All Transmitters and Receivers must be set into Repeater Mode.

6. Interrupt pin – Connect DS90UB924-Q1 INTB_IN pin to the serializer INTB pin. The signal must be pulled up

to V_DDIOwith a 10-kΩ resistor.

Deserializer

Serializer

RxIN0+

RxIN0-

TxOUT0+

TxOUT0-

RxIN1+

RxIN1-

TxOUT1+

TxOUT1-

RxIN2+

RxIN2-

TxOUT2+

TxOUT2-

RxIN3+

RxIN3-

TxOUT3+

TxOUT3-

RxCLKIN+

RxCLKIN-

TxCLKOUT+

TxCLKOUT-

VDD33

MODE_SEL

REPEAT

I2S_CLK

I2S_WC

I2S_Dx

I2S_CLK

I2S_WC

I2S_Dx

Optional

VDDIO

VDD33

IDx

INTB

INTB_IN

VDD33

SDA

SCL

SDA

SCL

Figure 31. Repeater Connection Diagram

7.4.5.1.1 Repeater Fan-Out Electrical Requirements

Repeater applications requiring fan-out from one DS90UB924-Q1 deserializer to up to three DS90UB927Q-Q1

serializers requires special considerations for routing and termination of the FPD-Link (OpenLDI) differential

traces. Figure 32 Details the requirements that must be met for each signal pair:

31

DS90UB924-Q1

ZHCSEY4 –APRIL 2016

www.ti.com.cn

L3

< 60 mm

TX

(UB927)

RX

(UB924)

TX

(UB927)

R1=100

ꢀ

R2=100 ꢀ

L1

<

75 mm

L2 < 60 mm

TX

(UB927)

L3

< 60 mm

Copyright

©

2016, Texas Instruments Incorporated

Figure 32. FPD-Link (OpenLDI) Fan-Out Electrical Requirements

32

DS90UB924-Q1

www.ti.com.cn

ZHCSEY4 –APRIL 2016

7.5 Programming

The DS90UB924-Q1 may also be configured by the use of an I²C compatible serial control bus. Multiple devices

may share the serial control bus (up to 10 device addresses supported). The device address is set via a resistor

divider (R1 and R2 — see Figure 33) connected to the IDx pin.

V_DD33

R₁

R₂

VR2

IDx

4.7kQ

HOST

DES

SCL

SDA

SCL

SDA

To other

Devices

Figure 33. Serial Control Bus Connection

The serial control bus consists of two signals and an address configuration pin. SCL is a Serial Bus Clock

Input/Output. SDA is the Serial Bus Data Input/Output signal. Both SCL and SDA signals require an external

pullup resistor to V_DD33or V_DDIO= 3.0 V to 3.6 V. For most applications, a 4.7-kΩ pullup resistor to V_DD33is

recommended. The signals are either pulled HIGH, or driven LOW.

The IDx pin configures the control interface to one of 10 possible device addresses. A pullup resistor and a

pulldown resistor is used to set the appropriate voltage ratio between the IDx input pin (V_R2) and V_DD33, each

ratio corresponding to a specific device address. See Table 8.

Table 7. Serial Control Bus Addresses for IDx

SUGGESTED

RESISTOR R1 kΩ

(1% tol)

SUGGESTED

RESISTOR R2 kΩ

(1% tol)

IDEAL RATIO

V_R2/ V_DD33

IDEAL V_R2

(V)

NO.

ADDRESS 7'b

ADDRESS 8'b

1

2

0

OPEN

226

215

200

187

174

154

150

137

90.9

40.2 or >10

97.6

113

0x2C

0x33

0x34

0x35

0x36

0x37

0x38

0x39

0x3A

0x3B

0x58

0x66

0x68

0x6A

0x6C

0x6E

0x70

0x72

0x74

0x76

0.995

1.137

1.282

1.413

1.570

1.707

1.848

1.997

2.535

0.302

0.345

0.388

0.428

0.476

0.517

0.560

0.605

0.768

3

4

127

5

140

6

158

7

165

8

191

9

210

10

301

33

DS90UB924-Q1

ZHCSEY4 –APRIL 2016

www.ti.com.cn

The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when

SCL transitions Low while SDA is High. A STOP occurs when SDA transitions High while SCL is also HIGH. See

Figure 34.

SDA

SCL

S

P

START condition, or

STOP condition

START repeat condition

Figure 34. START and STOP Conditions

To communicate with a remote device, the host controller (master) sends the slave address and listens for a

response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is

addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus LOW. If the address doesn't

match the slave address of device, it Not-acknowledges (NACKs) the master by letting SDA be pulled HIGH.

ACKs also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs

after every data byte is successfully received. When the master is reading data, the master ACKs after every

data byte is received to let the slave know it wants to receive another data byte. When the master wants to stop

reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus

begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop

condition. A READ is shown in Figure 35 and a WRITE is shown in Figure 36.

Register Address

Slave Address

Data

a

c

k

a

c

k

a

c

k

a

c

k

A

2

A

1

A

0

A

2

A

1

A

0

S

1

P

Figure 35. Serial Control Bus — READ

Register Address

Slave Address

Data

a

c

k

a

c

k

a

c

k

A

2

A

1

A

0

S

P

Figure 36. Serial Control Bus — WRITE

To support I²C transactions over the BCC. the I²C Master located at the DS90UB924-Q1 deserializer must

support I²C clock stretching. For more information on I²C interface requirements and throughput considerations,

refer to AN-2173 I2C Communication Over FPD-Link III with Bidirectional Control Channel SNLA131.

34

DS90UB924-Q1

www.ti.com.cn

ZHCSEY4 –APRIL 2016

7.6 Register Maps

(1) (2)

Table 8. Serial Control Bus Registers

ADD

(dec)

ADD

(hex)

Register

Type

Default

(hex)

Register Name

Bit

Function

Description

0

0x00 I2C Device ID

7:1

RW

IDx

Device ID

7–bit address of Deserializer

Note: Read-only unless bit 0 is set

0

RW

ID Setting

I2C ID Setting

0: Device ID is from IDx pin

1: Register I2C Device ID overrides IDx pin

1

0x01 Reset

7:3

2

0x04

Reserved

RW

BC Enable Back Channel Enable

0: Disable

1: Enable

1

0

7

Digital

RESET1

Reset the entire digital block including registers

This bit is self-clearing.

0: Normal operation (default)

1: Reset

RW

Digital

RESET0

Reset the entire digital block except registers

This bit is self-clearing

0: Normal operation (default)

1: Reset

2

0x02 General

Configuration 0

0x00

OEN

LVCMOS Output Enable. Self-clearing on loss of

LOCK

0: Disable, Tristate Outputs (default)

1: Enable

6

5

RW

OEN/OSS_ Output Enable and Output Sleep State Select override

SEL

Override

0: Disable over-write (default)

1: Enable over-write

Auto Clock OSC Clock Output. Enable On loss of lock, OSC

Enable

clock is output onto TxCLK±

0: Disable (default)

1: Enable

4

RW

OSS_SEL

Output Sleep State Select. Enable Select to control

output state during lock low period

0: Disable, Tri-State Outputs (default)

1: Enable

3

2

1

0

RW

BKWD

Override

Backwards Compatibility Mode Override

0: Use MODE_SEL pin (default)

1: Use register bit to set BKWD mode

BKWD

Mode

Backwards Compatibility Mode Select

0: Backwards Compatibility Mode disabled (default)

1: Backwards Compatibility Mode enabled

LFMODE

Override

Low Frequency Mode Override

0: Use LFMODE pin (default)

1: User register bit to set LFMODE

LFMODE

Low Frequency Mode

0: 15MHz ≤ PCLK ≤ 96MHz (default)

1: 5MHz ≤ PCLK < 15MHz

(1) Addresses not listed are reserved.

(2) Do not alter Reserved fields from their default values.

35

DS90UB924-Q1

ZHCSEY4 –APRIL 2016

www.ti.com.cn

Register Maps (continued)

(1) (2)

Table 8. Serial Control Bus Registers

(continued)

ADD

(dec)

ADD

(hex)

Register

Type

Default

(hex)

Register Name

Bit

Function

Description

3

0x03 General

Configuration 1

7

6

0xF0

Reserved

RW

Back

channel

CRC

Back Channel CRC Generator Enable

0: Disable

1: Enable (default)

Generator

Enable

5

4

RW

Failsafe

Outputs Failsafe Mode. Determines the pull direction

for undriven LVCMOS inputs

0: Pullup

1: Pulldown (default)

Filter

Enable

HS, VS, DE two clock filter. When enabled, pulses

less than two full PCLK cycles on the DE, HS, and VS

inputs will be rejected

0: Filtering disable

1: Filtering enable (default)

3

RW

I2C Pass-

Through

I2C Pass-Through Mode

Read/Write transactions matching any entry in the

DeviceAlias registers will be passed through to the

remote serializer I2C interface.

0: Pass-Through Disabled (default)

1: Pass-Through Enabled

2

1

RW

Auto ACK

Automatically Acknowledge I2C transactions

independent of the forward channel Lock state.

0: Disable (default)

1: Enable

DE Gate

RGB

Gate RGB data with DE signal. RGB data is not gated

with DE by default. However, to enable packetized

audio in DS90UB924-Q1, this bit must be set.

0: Pass RGB data independent of DE in Backward

Compatibility mode or interfacing to DS90UB925 or

DS90UB927

1: Gate RGB data with DE in Backward Compatibility

mode or interfacing to DS90UB925 or DS90UB927

0

Reserved

4

0x04 BCC Watchdog

Control

7:1

RW

0xFE

BCC

Watchdog

Timer

BCC Watchdog Timer The watchdog timer allows

termination of a control channel transaction if it fails to

complete within a programmed amount of time. This

field sets the Bidirectional Control Channel Watchdog

Timeout value in units of 2 milliseconds. This field

must not be set to 0.

0

RW

BCC

Watchdog

Disable

Disable Bidirectional Control Channel Watchdog

Timer

0: Enable (default)

1: Disable

5

0x05 I2C Control 1

7

0x1E

I2C Pass-

All

I2C Pass-Through All Transactions. Pass all local I2C

transactions to the remote serializer.

0: Disable (default)

1: Enable

6:4

3:0

I2C SDA

Hold

Internal I2C SDA Hold Time

This field configures the amount of internal hold time

is provided for the SDA input relative to the SCL input.

Units are 50ns.

I2C Filter

Depth

I2C Glitch Filter Depth

This field configures the maximum width of glitch

pulses on the SCL and SDA inputs that will be

rejected. Units are 5 nanoseconds.

36

DS90UB924-Q1

www.ti.com.cn

ZHCSEY4 –APRIL 2016

Register Maps (continued)

(1) (2)

Table 8. Serial Control Bus Registers

(continued)

ADD

(dec)

ADD

(hex)

Register

Type

Default

(hex)

Register Name

Bit

Function

Description

6

0x06 I2C Control 2

7

RW

0x00

Forward

Channel

Sequence

Error

Control Channel Sequence Error Detected

Indicates a sequence error has been detected in

forward control channel. It this bit is set, an error may

have occurred in the control channel operation.

6

RW

Clear

Sequence

Error

Clears the Sequence Error Detect bit This bit is not

self-clearing.

5

Reserved

4:3

RW

SDA Output SDA Output Delay

Delay This field configures output delay on the SDA output.

Setting this value will increase output delay in units of

50ns. Nominal output delay values for SCL to SDA

are:

00: 250ns (default)

01: 300ns

10: 350ns

11: 400ns

2

RW

Local Write Disable Remote Writes to Local Registers through

Disable

Serializer (Does not affect remote access to I2C

slaves)

0: Remote write to local device registers (default)

1: Stop remote write to local device registers

1

0

RW

I2C Bus

Timer

Speedup

Speed up I2C Bus Watchdog Timer

0: Timer expires after approximately 1s (default)

1: Timer expires after approximately 50µs

I2C Bus

Timer

Disable

Disable I2C Bus Watchdog Timer.

When the I2C Watchdog Timer may be used to detect

when the I2C bus is free or hung up following an

invalid termination of a transaction. If SDA is high and

no signaling occurs for approximately 1 second, the

I2C bus is assumed to be free. If SDA is low and no

signaling occurs, the device will attempt to clear the

bus by driving 9 clocks on SCL

7

8

0x07 Remote ID

7:1

0

R

0x00

Remote ID Remote Serializer ID

RW if bit 0 is set

RW

Freeze

Freeze Serializer Device ID

Device ID

0: Auto-load Serializer Device ID (default)

1: Prevent auto-loading of Serializer Device ID from

the remote device. The ID will be frozen at the value

written.

0x08 Slave ID[0]

7:1

RW

Slave

7-bit Remote Slave Device ID 0

Device ID0 Configures the physical I2C address of the remote

I2C Slave device attached to the remote Serializer. If

an I2C transaction is addressed to the Slave Alias

ID[0], the transaction will be re-mapped to this

address before passing the transaction across the

Bidirectional Control Channel to the Serializer.

0

Reserved

9

0x09 Slave ID[1]

7:1

0x00

Slave

7-bit Remote Slave Device ID1

Device ID1 Configures the physical I2C address of the remote

I2C Slave device attached to the remote Serializer. If

an I2C transaction is addressed to the Slave Alias

ID[1], the transaction will be re-mapped to this

address before passing the transaction across the

Bidirectional Control Channel to the Serializer.

0

Reserved

37

DS90UB924-Q1

ZHCSEY4 –APRIL 2016

www.ti.com.cn

Register Maps (continued)

(1) (2)

Table 8. Serial Control Bus Registers

(continued)

ADD

(dec)

ADD

(hex)

Register

Type

Default

(hex)

Register Name

Bit

Function

Description

10

11

12

13

14

15

16

0x0A Slave ID[2]

0x0B Slave ID[3]

0x0C Slave ID[4]

0x0D Slave ID[5]

0x0E Slave ID[6]

0x0F Slave ID[7]

0x10 Slave Alias[0]

7:1

RW

0x00

Slave

7-bit Remote Slave Device ID2

Device ID2 Configures the physical I2C address of the remote

I2C Slave device attached to the remote Serializer. If

an I2C transaction is addressed to the Slave Alias

ID[2], the transaction will be re-mapped to this

address before passing the transaction across the

Bidirectional Control Channel to the Serializer.

0

Reserved

7:1

Slave

7-bit Remote Slave Device ID3

Device ID3 Configures the physical I2C address of the remote

I2C Slave device attached to the remote Serializer. If

an I2C transaction is addressed to the Slave Alias

ID[3], the transaction will be re-mapped to this

address before passing the transaction across the

Bidirectional Control Channel to the Serializer.

0

Reserved

7:1

Slave

7-bit Remote Slave Device ID4

Device ID4 Configures the physical I2C address of the remote

I2C Slave device attached to the remote Serializer. If

an I2C transaction is addressed to the Slave Alias

ID[4], the transaction will be re-mapped to this

address before passing the transaction across the

Bidirectional Control Channel to the Serializer.

0

Reserved

7:1

Slave

7-bit Remote Slave Device ID5

Device ID5 Configures the physical I2C address of the remote

I2C Slave device attached to the remote Serializer. If

an I2C transaction is addressed to the Slave Alias

ID[5], the transaction will be re-mapped to this

address before passing the transaction across the

Bidirectional Control Channel to the Serializer.

0

Reserved

7:1

Slave

7-bit Remote Slave Device ID6

Device ID6 Configures the physical I2C address of the remote

I2C Slave device attached to the remote Serializer. If

an I2C transaction is addressed to the Slave Alias

ID[6], the transaction will be re-mapped to this

address before passing the transaction across the

Bidirectional Control Channel to the Serializer.

0

Reserved

7:1

Slave

7-bit Remote Slave Device ID 7

Device ID7 Configures the physical I2C address of the remote

I2C Slave device attached to the remote Serializer. If

an I2C transaction is addressed to the Slave Alias

ID[7], the transaction will be re-mapped to this

address before passing the transaction across the

Bidirectional Control Channel to the Serializer.

0

Reserved

7:1

Slave

7-bit Remote Slave Alias 0

Device

Alias 0

Configures the physical I2C address of the remote

I2C Slave device attached to the remote Serializer. If

an I2C transaction is addressed to the Slave Alias

ID[0], the transaction will be re-mapped to the ID

address before passing the transaction across the

Bidirectional Control Channel to the Serializer.

0

Reserved

38

DS90UB924-Q1

www.ti.com.cn

ZHCSEY4 –APRIL 2016

Register Maps (continued)

(1) (2)

Table 8. Serial Control Bus Registers

(continued)

ADD

(dec)

ADD

(hex)

Register

Type

Default

(hex)

Register Name

Bit

Function

Description

17

18

19

20

21

22

23

0x11 Slave Alias[1]

0x12 Slave Alias[2]

0x13 Slave Alias[3]

0x14 Slave Alias[4]

0x15 Slave Alias[5]

0x16 Slave Alias[6]

0x17 Slave Alias[7]

7:1

RW

0x00

Slave

Device

Alias 1

7-bit Remote Slave Alias 1

Configures the physical I2C address of the remote

I2C Slave device attached to the remote Serializer. If

an I2C transaction is addressed to the Slave Alias

ID[1], the transaction will be re-mapped to the ID

address before passing the transaction across the

Bidirectional Control Channel to the Serializer.

0

Reserved

7:1

Slave

Device

Alias 2

7-bit Remote Slave Alias 2

Configures the physical I2C address of the remote

I2C Slave device attached to the remote Serializer. If

an I2C transaction is addressed to the Slave Alias

ID[2], the transaction will be re-mapped to the ID

address before passing the transaction across the

Bidirectional Control Channel to the Serializer.

0

Reserved

7:1

Slave

Device

Alias 3

7-bit Remote Slave Alias 3

Configures the physical I2C address of the remote

I2C Slave device attached to the remote Serializer. If

an I2C transaction is addressed to the Slave Alias

ID[3], the transaction will be re-mapped to the ID

address before passing the transaction across the

Bidirectional Control Channel to the Serializer.

0

Reserved

7:1

Slave

Device

Alias 4

7-bit Remote Slave Alias 4

Configures the physical I2C address of the remote

I2C Slave device attached to the remote Serializer. If

an I2C transaction is addressed to the Slave Alias

ID[4], the transaction will be re-mapped to the ID

address before passing the transaction across the

Bidirectional Control Channel to the Serializer.

0

Reserved

7:1

Slave

Device

Alias 5

7-bit Remote Slave Alias 5

Configures the physical I2C address of the remote

I2C Slave device attached to the remote Serializer. If

an I2C transaction is addressed to the Slave Alias

ID[5], the transaction will be re-mapped to the ID

address before passing the transaction across the

Bidirectional Control Channel to the Serializer.

0

Reserved

7:1

Slave

Device

Alias 6

7-bit Remote Slave Alias 6

Configures the physical I2C address of the remote

I2C Slave device attached to the remote Serializer. If

an I2C transaction is addressed to the Slave Alias

ID[6], the transaction will be re-mapped to the ID

address before passing the transaction across the

Bidirectional Control Channel to the Serializer.

0

Reserved

7:1

Slave

7-bit Remote Slave Alias 7

Device

Alias 7

Configures the physical I2C address of the remote

I2C Slave device attached to the remote Serializer. If

an I2C transaction is addressed to the Slave Alias

ID[7], the transaction will be re-mapped to the ID

address before passing the transaction across the

Bidirectional Control Channel to the Serializer.

0

Reserved

39

DS90UB924-Q1

ZHCSEY4 –APRIL 2016

www.ti.com.cn

Register Maps (continued)

(1) (2)

Table 8. Serial Control Bus Registers

(continued)

ADD

(dec)

ADD

(hex)

Register

Type

Default

(hex)

Register Name

Bit

Function

Description

24

25

27

0x18 Mailbox[0]

7:0

RW

0x00

0x01

0x00

Mailbox

Register 0

Mailbox Register 0

This register may be used to temporarily store

temporary data, such as status or multi-master

arbitration

0x19 Mailbox[1]

7:0

Mailbox

Register 1

Mailbox Register 1

This register may be used to temporarily store

temporary data, such as status or multi-master

arbitration

0x1B Frequency

Counter

Frequency

Count

Frequency Counter control

A write to this register will enable a frequency counter

to count the number of pixel clock during a specified

time interval. The time interval is equal to the value

written multiplied by the oscillator clock period

(nominally 50ns). A read of the register returns the

number of pixel clock edges seen during the enabled

interval. The frequency counter will saturate at 0xff if it

reaches the maximum value. The frequency counter

will provide a rough estimate of the pixel clock period.

If the pixel clock frequency is known, the frequency

counter may be used to determine the actual oscillator

clock frequency.

28

0x1C General Status

7:4

3

0x00

Reserved

R

I2S Locked I2S Lock Status

0: I2S PLL controller not locked (default)

1: I2S PLL controller locked to input I2S clock

2

CRC Error

CRC Error Detected

0: No CRC errors detected

1: CRC errors detected

1

0

Reserved

R

LOCK

Deserializer CDR and PLL Locked to recovered clock

frequency

0: Deserializer not Locked (default)

1: Deserializer Locked to recovered clock

29

0x1D GPIO0

Configuration

7:4

3

R

0x20

Revision ID Device Revision ID:

0010: Production Device

RW

GPIO0

Output

Value

Local GPIO Output Value This value is output on the

GPIO pin when the GPIO function is enabled, the

local GPIO direction is Output, and remote GPIO

control is disabled.

0: Output LOW (default)

1: Output HIGH

2

RW

GPIO0

Remote

Enable

Remote GPIO Control

0: Disable GPIO control from remote device (default)

1: Enable GPIO control from remote device. The

GPIO pin will be an output, and the value is received

from the remote device.

1

0

RW

GPIO0

Direction

Local GPIO Direction

0: Output (default)

1: Input

GPIO0

Enable

GPIO Function Enable

0: Enable normal operation (default)

1: Enable GPIO operation

40

DS90UB924-Q1

www.ti.com.cn

ZHCSEY4 –APRIL 2016

Register Maps (continued)

(1) (2)

Table 8. Serial Control Bus Registers

(continued)

ADD

(dec)

ADD

(hex)

Register

Type

Default

(hex)

Register Name

Bit

Function

Description

30

0x1E GPIO1 and

GPIO2

7

RW

0x00

GPIO2

Output

Value

Local GPIO Output Value This value is output on the

GPIO pin when the GPIO function is enabled, the

local GPIO direction is Output, and remote GPIO

control is disabled.

Configuration

0: Output LOW (default)

1: Output HIGH

6

RW

GPIO2

Remote

Enable

Remote GPIO Control

0: Disable GPIO control from remote device (default)

1: Enable GPIO control from remote device. The

GPIO pin will be an output, and the value is received

from the remote device.

5

4

3

RW

GPIO2

Direction

Local GPIO Direction

0: Output (default)

1: Input

GPIO2

Enable

GPIO Function Enable

0: Enable normal operation (default)

1: Enable GPIO operation

GPIO1

Output

Value

Local GPIO Output Value This value is output on the

GPIO pin when the GPIO function is enabled, the

local GPIO direction is Output, and remote GPIO

control is disabled.

0: Output LOW (default)

1: Output HIGH

2

RW

GPIO1

Remote

Enable

Remote GPIO Control

0: Disable GPIO control from remote device (default)

1: Enable GPIO control from remote device. The

GPIO pin will be an output, and the value is received

from the remote device.

1

0

RW

GPIO1

Direction

Local GPIO Direction

1: Input

0: Output

GPIO1

Enable

GPIO function enable

1: Enable GPIO operation

0: Enable normal operation

31

0x1F GPIO3

Configuration

7:4

3

0x00

Reserved

RW

GPIO3

Output

Value

Local GPIO Output Value This value is output on the

GPIO pin when the GPIO function is enabled, the

local GPIO direction is Output, and remote GPIO

control is disabled.

0: Output LOW (default)

1: Output HIGH

2

GPIO3

Remote

Enable

Remote GPIO Control

0: Disable GPIO control from remote device (default)

1: Enable GPIO control from remote device. The

GPIO pin will be an output, and the value is received

from the remote device.

1

0

RW

GPIO3

Direction

Local GPIO Direction

0: Output (default)

1: Input

GPIO3

Enable

GPIO Function Enable

0: Enable normal operation (default)

1: Enable GPIO operation

41

DS90UB924-Q1

ZHCSEY4 –APRIL 2016

www.ti.com.cn

Register Maps (continued)

(1) (2)

Table 8. Serial Control Bus Registers

(continued)

ADD

(dec)

ADD

(hex)

Register

Type

Default

(hex)

Register Name

Bit

Function

Description

32

0x20 GPIO_REG5

and

7

RW

0x00

GPIO_REG Local GPIO Output Value This value is output on the

6 Output

Value

GPIO pin when the GPIO function is enabled, and the

local GPIO direction is Output.

0: Output LOW (default)

GPIO_REG6

Configuration

1: Output HIGH

6

5

Reserved

RW

GPIO_REG Local GPIO Direction

6 Direction 0: Output (default)

1: Input

4

3

GPIO_REG GPIO Function Enable

6 Enable

0: Enable normal operation (default)

1: Enable GPIO operation

GPIO_REG Local GPIO Output Value This value is output on the

5 Output

Value

GPIO pin when the GPIO function is enabled, and the

local GPIO direction is Output.

0: Output LOW (default)

1: Output HIGH

2

1

Reserved

RW

GPIO_REG Local GPIO Direction

5 Direction 0: Output (default)

1: Input

0

7

GPIO_REG GPIO Function Enable

5 Enable

0: Enable normal operation (default)

1: Enable GPIO operation

33

0x21 GPIO_REG7

and

0x00

GPIO_REG Local GPIO Output Value This value is output on the

8 Output

Value

GPIO pin when the GPIO function is enabled, and the

local GPIO direction is Output.

0: Output LOW (default)

GPIO_REG8

Configuration

1: Output HIGH

6

5

Reserved

RW

GPIO_REG Local GPIO Direction

8 Direction 0: Output (default)

1: Input

4

3

GPIO_REG GPIO Function Enable

8 Enable

0: Enable normal operation (default)

1: Enable GPIO operation

GPIO_REG Local GPIO Output Value This value is output on the

7 Output

Value

GPIO pin when the GPIO function is enabled, and the

local GPIO direction is Output.

0: Output LOW (default)

1: Output HIGH

2

1

Reserved

RW

GPIO_REG Local GPIO Direction

7 Direction 0: Output (default)

1: Input

0

GPO_REG GPIO Function Enable

7 Enable

0: Enable normal operation (default)

1: Enable GPIO operation

42

DS90UB924-Q1

www.ti.com.cn

ZHCSEY4 –APRIL 2016

Register Maps (continued)

(1) (2)

Table 8. Serial Control Bus Registers

(continued)

ADD

(dec)

ADD

(hex)

Register

Type

Default

(hex)

Register Name

Bit

Function

Description

34

0x22 Data Path

Control

7

RW

0x00

Override FC Override Configuration Loaded by Forward Channel

Configuratio 0: Allow forward channel loading of this register

n

(default)

1: Disable loading of this register from the forward

channel, keeping locally written values intact

Bits [6:0] are RW if this bit is set

6

5

Reserved

RW

DE Polarity This bit indicates the polarity of the DE (Data Enable)

signal.

0: DE is positive (active high, idle low) (default)

1: DE is inverted (active low, idle high)

4

3

I2S

Repeater

Regen

Regenerate I2S Data From Repeater I2S Pins

0: Output packetized audio on RGB video output pins.

(default)

1: Do not output packaged audio data on RGB video

output pins.

RW

I2S

I2S Channel B Override

Channel B

Enable

Override

0: Set I2S Channel B Disabled (default)

1: Set I2S Channel B Enable from register

2

1

RW

18-bit Video Video Color Depth Mode

Select

0: Select 24-bit video mode (default)

1: Select 18-bit video mode

I2S

Select I2S Transport Mode

Transport

Select

0: Enable I2S Data Island Transport (default)

1: Enable I2S Data Forward Channel Frame

Transport

0

RW

I2S

I2S Channel B Enable

Channel B

Enable

0: I2S Channel B disabled (default)

1: Enable I2S Channel B

35

0x23 Rx Mode Status

7

6:4

3

0x10

Reserved

RW

LFMODE

Status

Low Frequency Mode (LFMODE) pin status

0: 15 ≤ TxCLKOUT ≤ 96MHz (default)

1: 5 ≤ TxCLKOUT < 15MHz

2

1

0

REPEAT

Status

Repeater Mode (REPEAT) pin Status

0: Non-repeater (default)

1: Repeater

BKWD

Status

Backward Compatible Mode (BKWD) Status

0: Compatible to DS90UB925/7Q (default)

1: Backward compatible to DS90UR905/7Q

I2S

Channel B

Status

I2S Channel B Mode (I2S_DB) Status

0: I2S_DB inactive (default)

1: I2S_DB active

36

0x24 BIST Control

7:4

3

0x08

Reserved

RW

BIST Pin

Config

BIST Pin Configuration

0: BIST enabled from register

1: BIST enabled from pin (default)

2:1

OSC Clock Internal OSC clock select for Functional Mode or

Source

BIST. Functional Mode when PCLK is not present and

0x03[1]=1.

00: 33 MHz Oscillator (default)

01: 33 MHz Oscillator

Note: In LFMODE=1, the internal oscillator is

12.5MHz

0

RW

BIST

BIST Control

Enable

0: Disabled (default)

1: Enabled

43

DS90UB924-Q1

ZHCSEY4 –APRIL 2016

www.ti.com.cn

Register Maps (continued)

(1) (2)

Table 8. Serial Control Bus Registers

(continued)

ADD

(dec)

ADD

(hex)

Register

Type

Default

(hex)

Register Name

Bit

Function

Description

37

0x25 BIST Error

7:0

R

0x00

BIST Error Errors Detected During BIST

Count

Records the number (up to 255) of forward-channel

errors detected during BIST. The value stored in this

register is only valid after BIST terminates (BISTEN =

0). Resets on PDB = 0 or start of another BIST

(BISTEN = 1).

38

39

0x26 SCL High Time

0x27 SCL Low Time

7:0

RW

0x83

0x84

SCL High

Time

I2C Master SCL High Time

This field configures the high pulse width of the SCL

output when the deserializer is the Master on the local

I2C bus. Units are 50 ns for the nominal oscillator

clock frequency.

SCL Low

Time

I2C SCL Low Time

This field configures the low pulse width of the SCL

output when the deserializer is the Master on the local

I2C bus. This value is also used as the SDA setup

time by the I2C Slave for providing data prior to

releasing SCL during accesses over the Bidirectional

Control Channel. Units are 50 ns for the nominal

oscillator clock frequency.

40

0x28 Data Path

Control 2

7

RW

0x00

Block I2S

Override Forward Channel Configuration

Auto Config 0: Enable forward-channel loading of this register

1: Disable loading of this register from the forward

channel, keeping local values intact

6:4

3

Reserved

RW

Aux I2S

Enable

Auxiliary I2S Channel Enable

0: Normal GPIO[1:0] operation

1: Enable Aux I2S channel on GPIO1 (AUX word

select) and GPIO0 (AUX data)

2

I2S Disable Disable All I2S Outputs

0: I2S Outputs Enabled (default)

1: I2S Outputs Disabled

1

0

Reserved

RW

I2S

Surround

Enable 5.1- or 7.1-channel I2S audio transport

0: 2-channel or 4-channel I2S audio is enabled as

configured in register or MODE_SEL (default)

1: 5.1- or 7.1-channel audio is enabled

Note that I2S Data Island Transport is the only option

for surround audio. Also note that in a repeater, this

bit may be overridden by the in-band I2S mode

detection.

44

DS90UB924-Q1

www.ti.com.cn

ZHCSEY4 –APRIL 2016

Register Maps (continued)

(1) (2)

Table 8. Serial Control Bus Registers

(continued)

ADD

(dec)

ADD

(hex)

Register

Type

Default

(hex)

Register Name

Bit

Function

Description

41

0x29 FRC Control

7

RW

0x00

Timing

Mode

Select

Select Display Timing Mode

0: DE only Mode (default)

1: Sync Mode (VS,HS)

6

5

4

3

2

1

0

7

6

HS Polarity Horizontal Sync Polarity Select

0: Active High (default)

1: Active Low

VS Polarity Vertical Sync Polarity Select

0: Active High (default)

1: Active Low

DE Polarity Data Enable Sync Polarity Select

0: Active High (default)

1: Active Low

FRC2

Enable

FRC2 Enable

0: FRC2 disable (default)

1: FRC2 enable

FRC1

Enable

FRC1 Enable

0: FRC1 disable (default)

1: FRC1 enable

Hi-FRC2

Enable

Hi-FRC2 Enable

0: Hi-FRC2 enable (default)

1: Hi-FRC2 disable

Hi-FRC1

Enable

Hi-FRC1 Enable

0: Hi-FRC1 enable (default)

1: Hi-FRC1 disable

43

0x2B I2S Control

0x00

I2S PLL

Override

Override I2S PLL

0: PLL override disabled (default)

1: PLL override enabled

I2S PLL

Enable

Enable I2S PLL

0: I2S PLL is on for I2S data jitter cleaning (default)

1: I2S PLL is off. No jitter cleaning

5:1

0

Reserved

RW

I2S Clock

Edge

I2S Clock Edge Select

0: I2S Data is strobed on the Falling Clock Edge

(default)

1: I2S Data is strobed on the Rising Clock Edge

53

0x35 AEQ Control

7

6

0x00

Reserved

AEQ

Restart

Restart AEQ adaptation from initial (Floor) values

0: Normal operation (default)

1: Restart AEQ adaptation

Note: This bit is not self-clearing. It must be set, then

reset.

5

4

RW

LCBL

Override

Override LCBL Mode Set by MODE_SEL

0: LCBL controlled by MODE_SEL pin

1: LCBL controlled by register

LCBL

Set LCBL Mode

0: LCBL Mode disabled

1: LCBL Mode enabled. AEQ Floor value is controlled

from Adaptive EQ MIN/MAX register

3:0

7:2

1

Reserved

57

0x39 PG Internal

Clock Enable

0x00

RW

PG INT

CLK

Enable Pattern Generator Internal Clock

This bit must be set to use the Pattern Generator

Internal Clock Generation

0: Pattern Generator with external PCLK

1: Pattern Generator with internal PCLK

See TI Application Note AN-2198 for details

0

Reserved

45

DS90UB924-Q1

ZHCSEY4 –APRIL 2016

www.ti.com.cn

Register Maps (continued)

(1) (2)

Table 8. Serial Control Bus Registers

(continued)

ADD

(dec)

ADD

(hex)

Register

Type

Default

(hex)

Register Name

Bit

Function

Description

58

0x3A I2S DIVSEL

7

RW

0x00

MCLK Div

Override

Override MCLK Divider Setting

0: No override for MCLK divider (default)

1: Override divider select for MCLK

6:4

3:0

7:6

5:0

RW

MCLK Div

See Table 4

Reserved

59

65

0x3B Adaptive EQ

Status

R

Reserved

EQ Status

Equalizer Status

Current equalizer level set by AEQ or Override

Register

0x41 Link Error Count

7:5

4

0x03

Reserved

RW

Link Error

Count

Enable

Enable serial link data integrity error count.

1: Enable error count

0: Disable

3:0

Link Error

Count

Link error count threshold. Counter is pixel clock

based. CLK0, CLK1, and DCA are monitored for link

errors. If error count is enabled, Deserializer will lose

lock once error count reaches threshold. If disabled,

Deserializer will lose lock with one error. Video, audio,

GPIO, and I2C data bits are not checked for errors.

68

0x44 Adaptive

Equalizer

7:5

RW

0x60

EQ Stage 1 EQ Stage 1 select value. Used if adaptive EQ is

Select

Value

bypassed. Used if adaptive EQ is bypassed.

Bypass

4

Reserved

3:1

RW

EQ Stage 2 EQ Stage 2 select value. Used if adaptive EQ is

Select

Value

bypassed Used if adaptive EQ is bypassed.

0

Adaptive

Bypass Adaptive EQ

EQ Bypass Overrides Adaptive EQ search and sets the EQ to the

static value configured in this register

0: Enable adaptive EQ (default)

1: Disable adaptive EQ (to write EQ select values)

69

73

0x45 Adaptive EQ

MIN/MAX

7:4

3:0

RW

0x88

0x00

Reserved

Adaptive

EQ Floor

Adaptive Equalizer Floor Value

Sets the AEQ floor value when Long Cable Mode

(LCBL) is enabled by register or MODE_SEL

0x49 Map Select

7

6

R

MAPSEL

Pin Status

Returns Status of MAPSEL pin

RW

MAPSEL

Override

Map Select (MAPSEL) Setting Override

0: MAPSEL set from pin

1: MAPSEL set from register

5

RW

MAPSEL

Map Select (MAPSEL) Setting

0: LSBs on TxOUT3±

1: MSBs on TxOUT3±

4:0

7:2

1:0

Reserved

75

86

0x4B LVDS Driver

Setting

0x08

RW

LVDS V_OD

Control

00: 400mV differential (default)

01: 600mV differential

0x56 Loop-Through

Driver

7:4

3

Reserved

Loop-

Through

Driver

Enable CML Loop-Through Driver

(CMLOUTP/CMLOUTN)

0: Enable

Enable

1: Disable (default)

2:0

Reserved

46

DS90UB924-Q1

www.ti.com.cn

ZHCSEY4 –APRIL 2016

Register Maps (continued)

(1) (2)

Table 8. Serial Control Bus Registers

(continued)

ADD

(dec)

ADD

(hex)

Register

Type

Default

(hex)

Register Name

Bit

Function

Description

100

0x64 Pattern

Generator

Control

7:4

RW

0x10

Pattern

Generator

Select

Fixed Pattern Select

Selects the pattern to output when in Fixed Pattern

Mode. Scaled patterns are evenly distributed across

the horizontal or vertical active regions. This field is

ignored when Auto-Scrolling Mode is enabled.

xxxx: normal/inverted

0000: Checkerboard

0001: White/Black (default)

0010: Black/White

0011: Red/Cyan

0100: Green/Magenta

0101: Blue/Yellow

0110: Horizontal Black-White/White-Black

0111: Horizontal Black-Red/White-Cyan

1000: Horizontal Black-Green/White-Magenta

1001: Horizontal Black-Blue/White-Yellow

1010: Vertical Black-White/White— Black

1011: Vertically Scaled Black to Red/White to Cyan

1100: Vertical Black-Green/White-Magenta

1101: Vertical Black-Blue/White-Yellow

1110: Custom color (or its inversion) configured in

PGRS, PGGS, PGBS registers

1111: VCOM

See TI App Note AN-2198

3

2

Reserved

RW

Color Bars Enable Color Bars Pattern

Pattern

0: Color Bars disabled (default)

1: Color Bars enabled

Overrides the selection from bits [7:4]

1

0

RW

VCOM

Pattern

Reverse

Reverse order of color bands in VCOM pattern

0: Color sequence from top left is (YCBR) (default)

1: Color sequence from top left is (RBCY)

Pattern

Pattern Generator Enable

Generator

Enable

0: Disable Pattern Generator (default)

1: Enable Pattern Generator

See TI App Note AN-2198

47

DS90UB924-Q1

ZHCSEY4 –APRIL 2016

www.ti.com.cn

Register Maps (continued)

(1) (2)

Table 8. Serial Control Bus Registers

(continued)

ADD

(dec)

ADD

(hex)

Register

Type

Default

(hex)

Register Name

Bit

Function

Description

101

0x65 Pattern

Generator

Configuration

7

6

0x00

Reserved

RW

Checkerboa Scale Checkerboard Patterns:

rd Scale

0: Normal operation (each square is 1x1 pixel)

(default)

1: Scale checkered patterns (VCOM and

checkerboard) by 8 (each square is 8x8 pixels)

Setting this bit gives better visibility of the checkered

patterns.

5

4

RW

Custom

Use Custom Checkerboard Color

Checkerboa 0: Use white and black in the Checkerboard pattern

rd

(default)

1: Use the Custom Color and black in the

Checkerboard pattern

PG 18–bit

Mode

18-bit Mode Select:

0: Enable 24-bit pattern generation. Scaled patterns

use 256 levels of brightness. (default)

1: Enable 18-bit color pattern generation. Scaled

patterns will have 64 levels of brightness and the R,

G, and B outputs use the six most significant color

bits.

3

2

RW

External

Clock

Select External Clock Source:

0: Selects the internal divided clock when using

internal timing (default)

1: Selects the external pixel clock when using internal

timing. This bit has no effect in external timing mode

(PATGEN_TSEL = 0).

Timing

Select

Timing Select Control:

0: the Pattern Generator uses external video timing

from the pixel clock, Data Enable, Horizontal Sync,

and Vertical Sync signals. (default)

1: The Pattern Generator creates its own video timing

as configured in the Pattern Generator Total Frame

Size, Active Frame Size. Horizontal Sync Width,

Vertical Sync Width, Horizontal Back Porch, Vertical

Back Porch, and Sync Configuration registers.

1

0

RW

Color Invert Enable Inverted Color Patterns:

0: Do not invert the color output. (default)

1: Invert the color output.

Auto Scroll Auto Scroll Enable:

0: The Pattern Generator retains the current pattern.

(default)

1: The Pattern Generator will automatically move to

the next enabled pattern after the number of frames

specified in the Pattern Generator Frame Time

(PGFT) register.

See TI App Note AN-2198

102

103

0x66 PGIA

7:0

RW

0x00

PG Indirect This 8-bit field sets the indirect address for accesses

Address

to indirectly-mapped registers. It must be written prior

to reading or writing the Pattern Generator Indirect

Data register.

See TI App Note AN-2198

0x67 PGID

PG Indirect When writing to indirect registers, this register

Data

contains the data to be written. When reading from

indirect registers, this register contains the read back

value.

See TI App Note AN-2198 AN-2198

48

DS90UB924-Q1

www.ti.com.cn

ZHCSEY4 –APRIL 2016

Register Maps (continued)

(1) (2)

Table 8. Serial Control Bus Registers

(continued)

ADD

(dec)

ADD

(hex)

Register

Type

Default

(hex)

Register Name

Bit

Function

Description

110

0x6E GPI Pin Status

1

7

R

0x00

GPI7 Pin

Status

GPI7 Pin Status. Readable when REG_GPIO7 is set

as an input.

6

5

GPI6 Pin

Status

GPI6 Pin Status. Readable when REG_GPIO6 is set

as an input.

GPI5 Pin

Status

GPI5 Pin Status. Readable when REG_GPIO5 is set

as an input.

4

3

Reserved

R

GPI3 Pin

Status

GPI3 Pin Status. Readable when GPIO3 is set as an

input.

2

1

0

GPI2 Pin

Status

GPI2 Pin Status. Readable when GPIO2 is set as an

input.

GPI1 Pin

Status

GPI1 Pin Status. Readable when GPIO1 is set as an

input.

GPI0 Pin

Status

GPI0 Pin Status. Readable when GPIO0 is set as an

input.

111

0x6F GPI Pin Status

2

7:1

0

0x00

Reserved

R

GPI8 Pin

Status

GPI8 Pin Status. Readable when REG_GPIO8 is set

as an input.

49

DS90UB924-Q1

ZHCSEY4 –APRIL 2016

www.ti.com.cn

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers must

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The DS90UB924-Q1 deserializer, in conjunction with a DS90UB921-Q1, DS90UB925Q-Q1 or DS90UB927Q-Q1

serializer, provides a solution for distribution of digital video and audio within automotive infotainment systems. It

converts a high-speed serialized interface with an embedded clock, delivered over a single signal pair (FPD-Link

III), to four LVDS data/control streams, one LVDS clock pair (FPD-Link (OpenLDI)), and I2S audio data. The

serial bus scheme, FPD-Link III, supports high-speed forward channel data transmission, and low-speed full

duplex back channel communication over a single differential link. Consolidation of audio, video data, and control

over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and

simplifying system design.

8.2 Typical Application

Figure 37 shows a typical application of the DS90UB924-Q1 deserializer for an 96 MHz 24-bit color display

application. Inputs utilize 0.1-µF coupling capacitors to the line, and the deserializer provides internal termination.

The voltage rating of the coupling capacitors must be ≥50 V and must use a small body capacitor size, such as

0402 or 0602, to help ensure good signal integrity. The FPD-Link (OpenLDI) LVDS differential outputs require

100-Ω termination resistors at the receiving device or display.

Bypass capacitors must be placed near the power supply pins. At a minimum, three 4.7-μF capacitors, one

placed at each power supply pin, are required for local device bypassing. If additional bypass capacitors are

used, place the smaller value components closer to the pin. Ferrite beads are required on the two supplies

(V_DD33and V_DDIO) for effective noise suppression. Connect pins VDD33_A and VDD33_B directly to ensure ESD

performance. The interface to the display is FPD-Link (OpenLDI) LVDS. The VDDIO pin may be connected to 3.3

V or 1.8 V. Place a delay capacitor (>10 µF) and pullup resistor (10 kΩ) on the PDB signal to delay the enabling

of the device until power is stable.

50

DS90UB924-Q1

www.ti.com.cn

ZHCSEY4 –APRIL 2016

Typical Application (continued)

3.3V

DS90UB924-Q1

3.3V / 1.8V

VDDIO

VDD33_A

C6

FB1

FB2

C4

CAPLV25

VDD33_B

CAPL12

C7

C11

C12

C5

C8

CAPLV12

CAPP12

C9

CAPR12

C10

CAPI2S

C13

PASS

LOCK

C1

Serial

FPD-Link III

Interface

TxCLKOUT-

TxCLKOUT+

RIN+

RIN-

R_TERM

C2

CMF

TxOUT3-

TxOUT3+

TxOUT2-

TxOUT2+

R_TERM

C3

FPD-Link

Interface

R_TERM

CMLOUTP

CMLOUTN

TxOUT1-

TxOUT1+

R_TERM

OEN

OSS_SEL

LVCMOS

TxOUT0-

TxOUT0+

BISTEN

Control

R_TERM

MAPSEL

LFMODE

Interface

VDD33

R1

VDD33 or VDDIO=3.3V±0.3V

R5

IDx

SCL

SDA

INTB_IN

PDB

R2

NOTE:

FB1-FB2 (Optional): Impedance = 1kQ,

Low DC resistance (<1Q)

C14

VDD33

C1-C3 = 0.1 µF (50 WV; C1, C2: 0402; C3: 0603)

C4-C13 = 4.7 µF

C14 = > 10 µF

R1 and R2 (see IDx Resistor Value Table)

R3 and R4 (see MODE_SEL Resistor Value Table)

R5 = 10kQ

R3

R4

GPIO[1:0]

MCLK

I2S_CLK

I2S_WC

I2S_Dx

MODE_SEL

I2S / GPIO

Interface

4

RESx

DAP (GND)

R_PU= 4.7kQ

R_TERM= 100Q

Figure 37. Typical Connection Diagram

51

DS90UB924-Q1

ZHCSEY4 –APRIL 2016

www.ti.com.cn

Typical Application (continued)

FPD-Link

(Open LDI)

V_DD33

V_DDIO

V

DDIO

V

DD33

(3.3V) (1.8V or 3.3V)

(1.8Vor3.3V) (3.3V)

R[7:0]

G[7:0]

B[7:0]

HS

VS

DE

PCLK

TxOUT3+/-

TxOUT2+/-

FPD-Link III

1 Pair/AC Coupled

HOST

Graphics

Processor

LVDS Display

720p or

Graphic

DOUT+

RIN+

RIN-

TxOUT1+/-

TxOUT0+/-

DOUT-

Proccesor

100Q STP Cable

TxCLKOUT+/-

INTB_IN

DS90UB921-Q1

Serializer

PDB

DS90UB924-Q1

Deserializer

3

OEN

LOCK

PASS

I2S

MCLK

SCL

SDA

IDx

I2S AUDIO

(STEREO)

OSS_SEL

PDB

MAPSEL

LFMODE

BISTEN

6

MODE_SEL

INTB

SCL

SDA

IDx

DAP

MODE_SEL

Figure 38. Typical Display System Diagram

8.2.1 Design Requirements

For the typical design application, use the following as input parameters:

Table 9. Design Parameters

DESIGN PARAMETER

VDDIO

EXAMPLE VALUE

1.8 V or 3.3 V

3.3 V

VDD33

330nF for RIN+, 250nF for RIN-

(Single-ended)

100 nF for RIN+/- (Differential)

AC Coupling Capacitor for RIN±

PCLK Frequency

96 MHz

8.2.2 Detailed Design Procedure

8.2.2.1 Transmission Media

The DS90UB927Q-Q1/DS90UB921-Q1/DS90UB925Q-Q1 and DS90UB924-Q1 chipset is intended to be used in

a point-to-point configuration through a shielded twisted pair cable. The serializer and deserializer provide

internal termination to minimize impedance discontinuities. The interconnect (cable and connector) between the

serializer and deserializer must have a differential impedance of 100 Ω. The maximum length of cable that can

be used is dependant on the quality of the cable (gauge, impedance), connector, board (discontinuities, power

plane), the electrical environment (for example, power stability, ground noise, input clock jitter, PCLK frequency,

and so forth.) and the application environment.

The resulting signal quality at the receiving end of the transmission media may be assessed by monitoring the

differential eye opening of the serial data stream. The Receiver CML Monitor Driver Output Specifications define

the acceptable data eye opening width and eye opening height. use a differential probe to measure across the

termination resistor at the CMLOUTP/CMLOUTN pins.

52

DS90UB924-Q1

www.ti.com.cn

ZHCSEY4 –APRIL 2016

8.2.2.2 Display Application

The DS90UB924-Q1, in conjunction with the DS90UB921-Q1, is intended for interfacing with a host (graphics

processor) and a display supporting 24-bit color depth (RGB888) and high-definition (720p) digital video format. It

can receive an 8-bit RGB stream with a pixel clock rate up to 96 MHz together with three control bits (VS, HS,

and DE) and four I2S audio streams.

8.2.3 Application Curves

Time (1.25 ns/DIV)

Time (250 ps/DIV)

Figure 39. 96 MHz TxCLKOUT± and TxOUT0± Data Output

Figure 40. CMLOUT of Deserializer from 96 MHz Input

Clock

9 Power Supply Recommendations

9.1 Power Up Requirements and PDB Pin

When VDDIO and VDD33 are powered separately, the VDDIO supply (1.8V or 3.3V) should ramp 100us before

the other supply, VDD33. If VDDIO is tied with VDD33, both supplies may ramp at the same time. The VDDs

(VDD33 and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If the PDB pin is not

controlled by a microcontroller, a large capacitor on the pin is needed to ensure PDB arrives after all the VDDs

have settled to the recommended operating voltage. When PDB pin is pulled to VDDIO = 3.0V to 3.6V or

VDD33, it is recommended to use a 10 kΩ pull-up and a >10 uF cap to GND to delay the PDB input signal.

A minimum low pulse of 2ms is required when toggling the PDB pin to perform a hard reset.

All inputs must not be driven until VDD33 and VDDIO has reached its steady state value.

53

DS90UB924-Q1

ZHCSEY4 –APRIL 2016

www.ti.com.cn

Power Up Requirements and PDB Pin (continued)

t₀

VDDIO

GND

t₃

VDD33

GND

t₁

VDD33

t₄

V_{PDB_HIGH}

PDB^(*)

V_{PDB_LOW}

GND

^(*)It is recommended to assert PDB (active High) with a microcontroller rather than an RC filter

network to help ensure proper sequencing of PDB pin after settling of power supplies.

Figure 41. Power Sequence

Table 10. Power-Up Sequencing Constraints

Symbol

VDDIO

VDD33

Description

Test Conditions

Min

3.0

Typ

Max

3.6

Units

V

VDDIO voltage range

1.71

3.0

1.89

3.6

VDD33 voltage range

PDB LOW threshold

Note: V_PDBmust not exceed

limit for respective I/O voltage

before 90% voltage of VDD33

V_{PDB_LOW}

VDDIO = 3.3V ± 10%

0.8

V

V_{PDB_HIGH}

t₀

PDB HIGH threshold

2.0

1.5

V

These time constants are specified for

rise time of power supply voltage ramp

(10% - 90%)

VDDIO rise time

0.05

ms

These time constants are specified for

rise time of power supply voltage ramp

(10% - 90%)

t₃

VDD33 rise time

1.5

ms

V_ILof rising edge (VDDIO ) to V_ILof

rising edge (VDD33)

The power supplies may be ramped

simultaneously. If sequenced, VDDIO

must be first.

t₁

VDD33 delay time

0

The part is powered up after the startup

time has elapsed from the moment PDB

goes HIGH. Local I2C is available to

read/write 948/940 registers after this

time.

t₄

Startup time

1

ms

54

DS90UB924-Q1

www.ti.com.cn

ZHCSEY4 –APRIL 2016

9.2 Analog Power Signal Routing

All power inputs must be tied to the main VDD source (for example, battery), unless the user wishes to power it

from another source. (that is, external LDO output).

The analog VDD inputs power the internal bias and error amplifiers, so they must be tied to the main VDD. The

analog VDD inputs must have an input voltage between 2.8 V and 5.5 V, as specified in the Recommended

Operating Conditions table earlier in the datasheet.

The other VINs (VINLDO1, VINLDO2) can have inputs lower than 2.8 V, as long as the input it higher than the

programmed output (0.3 V).

The analog and digital grounds must be tied together outside of the chip to reduce noise coupling.

10 Layout

10.1 Layout Guidelines

Circuit board layout and stack-up for the LVDS serializer and deserializer devices must be designed to provide

low-noise power to the device. Good layout practice also separates high frequency or high-level inputs and

outputs to minimize unwanted stray noise, feedback, and interference. Power system performance may be

greatly improved by using thin dielectrics (2 to 4 mil) for power / ground sandwiches. This arrangement utilizes

the plane capacitance for the PCB power system and has low inductance, which has proven effectiveness

especially at high frequencies, and makes the value and placement of external bypass capacitors less critical.

External bypass capacitors must include both RF ceramic and tantalum electrolytic types. RF capacitors may use

values in the range of 0.01 μF to 10 μF. Tantalum capacitors may be in the 2.2 μF to 10 μF range. The voltage

rating of the capacitors must be at least 5X the power supply voltage being used.

TI recommends MLCC surface mount capacitors due to their smaller parasitic properties. When using multiple

capacitors per supply pin, locate the smaller value closer to the pin. TI recommends a large bulk capacitor

typically in the 50 μF to 100 μF range at the point of power entry, which smooths low frequency switching noise

connect power and ground pins directly to the power and ground planes with bypass capacitors connected to the

plane with via on both ends of the capacitor. Connecting power or ground pins to an external bypass capacitor

increases the inductance of the path. TI recommends a small body size X7R chip capacitor, such as 0603 or

0805, for external bypass. Because a small body sized capacitor has less inductance. The user must pay

attention to the resonance frequency of these external bypass capacitors, usually in the range of 20 MHz to 30

MHz. To provide effective bypassing, multiple capacitors are often used to achieve low impedance between the

supply rails over the frequency of interest. At high frequency, it is also a common practice to use two vias from

power and ground pins to the planes, reducing the impedance at high frequency.

Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate

switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not

required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power

pin pairs. In some cases, an external filter may be used to provide clean power to sensitive circuits such as

PLLs. This device requires only one common ground plane to connect all device related ground pins.

Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the LVDS

lines to prevent coupling from the LVCMOS lines to the LVDS lines. Closely coupled differential lines of 100 Ω

are typically recommended for LVDS interconnect. The closely coupled lines help to ensure that coupled noise

will appear as common mode and thus is rejected by the receivers. The tightly coupled lines also radiate less.

At least 9 thermal vias are necessary from the device center DAP to the ground plane. They connect the device

ground to the PCB ground plane, as well as conduct heat from the exposed pad of the package to the PCB

ground plane. More information on the WQFN package, including PCB design and manufacturing requirements,

is provided in AN-1187 Leadless Leadframe Package (LLP) (AN-2198).

Stencil parameters such as aperture area ratio and the fabrication process have a significant impact on paste

deposition. Inspection of the stencil prior to placement of the WQFN package is highly recommended to improve

board assembly yields. If the via and aperture openings are not carefully monitored, the solder may flow

unevenly through the DAP. Stencil parameters for aperture opening and via locations are shown below:

55

DS90UB924-Q1

ZHCSEY4 –APRIL 2016

www.ti.com.cn

Layout Guidelines (continued)

Table 11. No Pullback WQFN Stencil Aperture Summary

DEVICE

COUNT

MKT Dwg

PCB I/O

Pad Size

(mm)

PCB

PITCH

(mm)

PCB DAP

SIZE (mm)

STENCIL I/O

APERTURE

(mm)

STENCIL DAP

Aperture (mm)

NUMBER of

DAP

APERTURE

OPENINGS

DS90UB924-Q1

48

RHS0048A 0.25 x 0.4

0.5

5.1 x 5.1

0.25 x 0.6

5.1 x 5.1

1

Figure 42 shows the PCB layout example derived from the layout design of the DS90UB924QEVM evaluation

board. The graphic and layout description are used to determine both proper routing and proper solder

techniques when designing the Serializer board.

10.1.1 CML Interconnect Guidelines

See Application Note 1108 Channel-Link PCB and Interconnect Design-In Guidelines (SNLA008) and

Application Note 905 Transmission Line RAPIDESIGNER Operation and Applications Guide (SNLA035) for

full details.

•

Use 100 Ω coupled differential pairs

Use the S/2S/3S rule in spacings

–

– S = space between the pair

– 2S = space between pairs

– 3S = space to LVCMOS signal

•

Minimize the number of Vias

Use differential connectors when operating above 500 Mbps line speed

Maintain balance of the traces

Minimize skew within the pair

Terminate as close to the TX outputs and RX inputs as possible

Additional general guidance can be found in the LVDS Owner’s Manual (SNLA187).

56

DS90UB924-Q1

www.ti.com.cn

ZHCSEY4 –APRIL 2016

10.2 Layout Example

Length-Matched

OpenLDI Traces

High-Speed Traces

AC Capacitors

Figure 42. DS90UB924-Q1 Deserializer Example Layout

Figure 43. 48-Pin WQFN Stencil Example of Via and Opening Placement

57

DS90UB924-Q1

ZHCSEY4 –APRIL 2016

www.ti.com.cn

11 器件和文档支持

11.1 文档支持

11.1.1 相关文档ꢀ


型号：	DS90UB924TRHSTQ1
厂家：	TEXAS INSTRUMENTS
描述：	5MHz 至 96MHz 24 位彩色 FPD-Link III 转 OpenLDI 解串器 \| RHS \| 48 \| -40 to 105 光电二极管
文件：	总65页 (文件大小：1201K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DS90UB924TRHSTQ1 [TI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E