DS90UB933TRTVTQ1 [TI]
适用于 1MP/60fps 和 2MP/30fps 摄像头的 12 位 100MHz FPD-Link III 串行器 | RTV | 32 | -40 to 105;
| 型号： | DS90UB933TRTVTQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于 1MP/60fps 和 2MP/30fps 摄像头的 12 位 100MHz FPD-Link III 串行器 | RTV | 32 | -40 to 105 光电二极管 电视 |
| 文件： | 总55页 (文件大小：2500K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS90UB933-Q1
ZHCSFV6E –AUGUST 2016 –REVISED NOVEMBER 2020
DS90UB933-Q1 适用于1MP/60fps 摄像头10/12 位、100MHz 的FPD-Link III 串行器
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准，其中包括以
下特性：
– 器件温度等级2：–40°C 至+105°C 环境工作
温度范围
• 支持37.5MHz 至100MHz 输入像素时钟
• 稳健的同轴电缆供电(PoC) 运行
• 可编程数据有效载荷：
– 10 位有效载荷，高达100MHz
– 12 位有效载荷，高达100MHz
• 连续低延迟双向控制接口通道，带有I2C 接口，支
持400kHz 传输速率
• 嵌入式时钟具有DC 均衡编码，用于支持AC 耦合
互连
• 能够驱动长达15m 的同轴或屏蔽双绞线(STP) 电
缆
• 4 个专用通用输入/输出(GPIO)
• 串行器上提供1.8V、2.8V 或3.3V 兼容并行输入
• 1.8V 单电源
DS90UB933-Q1 器件提供一个具有高速正向通道和双
向控制通道的 FPD-Link III 接口，用于实现单一同轴电
缆或差分对上的数据传输。DS90UB933-Q1 器件的高
速正向通道和双向控制通道数据路径上均包含差分信
令。串行器/解串器对主要用于电子控制单元 (ECU) 中
成像器与视频处理器的连接。该器件非常适用于驱动需
要高达 12 位像素深度、2 个同步信号以及双向控制通
道总线的视频数据。
凭借德州仪器 (TI) 的嵌入式时钟技术，可在单一差分
对上进行透明的全双工通信，从而运载不对称的双向控
制通道信息。这个单个串行数据流通过消除并行数据与
时钟路径间的偏差，简化了印刷电路板 (PCB) 走线和
电缆上的宽数据总线传输。这样，通过限制数据路径的
宽度，大大节省了系统成本，相应地减少了 PCB 层
数、电缆宽度以及连接器尺寸和引脚数量。内部DC 均
衡编码/解码用于支持AC 耦合互连。
器件信息
器件型号(1)
封装尺寸（标称值）
封装
• 符合ISO 10605 和IEC 61000-4-2 ESD 标准
DS90UB933-Q1
WQFN (32)
5.00mm × 5.00mm
2 应用
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 汽车
– 环视系统(SVS)
– 前置摄像头(FC)
– 后视摄像头(RVC)
– 传感器融合
– 驾驶员监视摄像头(DMS)
– 远距卫星雷达、ToF 和激光雷达传感器
• 安全和监控
• 机器视觉应用
Parallel
Data In
Parallel
Data Out
FPD-Link III
10 or 12
10 or 12
2
2
Image Signal
Processor
(ISP)
DS90UB934-Q1
HSYNC,
VSYNC
4
HD Image
Sensor
HSYNC,
VSYNC
4
DS90UB933-Q1
or
DS90UB964-Q1
Bidirectional
GPO
2
Control Channel
GPIO
2
Bidirectional
Control Bus
Bidirectional
Control Bus
Serializer
Deserializer
简化原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNLS546
DS90UB933-Q1
ZHCSFV6E –AUGUST 2016 –REVISED NOVEMBER 2020
www.ti.com.cn
Table of Contents
7.1 Overview...................................................................17
7.2 Functional Block Diagram.........................................17
7.3 Feature Description...................................................17
7.4 Device Functional Modes..........................................22
7.5 Programming............................................................ 27
7.6 Register Maps...........................................................31
8 Application and Implementation..................................38
8.1 Application Information............................................. 38
8.2 Typical Applications.................................................. 40
9 Power Supply Recommendations................................43
10 Layout...........................................................................44
10.1 Layout Guidelines................................................... 44
10.2 Layout Example...................................................... 45
11 Device and Documentation Support..........................47
11.1 Documentation Support.......................................... 47
11.2 Receiving Notification of Documentation Updates..47
11.3 支持资源..................................................................47
11.4 Trademarks............................................................. 47
11.5 静电放电警告...........................................................47
11.6 术语表..................................................................... 47
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
Pin Functions.................................................................... 4
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings........................................ 6
6.2 ESD Ratings............................................................... 6
6.3 Recommended Operating Conditions.........................6
6.4 Thermal Information....................................................7
6.5 Electrical Characteristics.............................................7
6.6 Recommended Serializer Timing For PCLK............. 10
6.7 AC Timing Specifications (SCL, SDA) - I2C-
Compatible.................................................................. 11
6.8 Bidirectional Control Bus DC Timing
Specifications (SCL, SDA) - I2C-Compatible.............. 11
6.9 Serializer Switching Characteristics..........................12
6.10 Timing Diagrams.....................................................14
6.11 Typical Characteristics............................................ 16
7 Detailed Description......................................................17
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision D (January 2020) to Revision E (November 2020)
Page
• Added register 0x27[3] to register map.............................................................................................................31
• Clarified PDB voltage level for t3 and t4 in Power-Up Sequencing from 90% VPDB to PDB VIH ...................... 38
• Changed Power-Up Sequencing alternative programming steps (t3*) to add NCLK reset...............................38
• Clarified Power-Up Sequencing alternative programming steps (t3*) to remove delay between I2C
commands ....................................................................................................................................................... 38
Changes from Revision C (November 2019) to Revision D (January 2020)
Page
• Clarified GPO2 description by removing statement about leaving pin open if unused ......................................4
• Added maximum power up timing constraint between VDD_n and PDB ........................................................ 38
• Added recommended software programming steps if VDD_n to PDB maximum power up timing constraint
can not be met .................................................................................................................................................38
Changes from Revision B (September 2018) to Revision C (November 2019)
Page
• Added register 0x27[5] to register map ............................................................................................................31
Changes from Revision A (December 2016) to Revision B (September 2018)
Page
• Added recommendation to ensure GPO2 is low when PDB goes high..............................................................4
• Added external clock input frequency range ......................................................................................................6
• Added strap pin input current specification for MODE and IDX pins ................................................................. 7
• Updated TJIT1 PCLK input jitter in the external oscillator mode........................................................................10
• Added that 0.45UI TJIT2 maximum is when used with DS90UB934-Q1 and added new foot note ..................10
• Added clarification on MODE pin description in PCLK from imager mode ......................................................23
• Updated the MODE setting values to ratio from voltage...................................................................................23
• Updated IDX setting values to ratio from voltage............................................................................................. 29
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SNLS546
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• Added register "TYPE" column per legend ......................................................................................................31
• Added type and default value to the reserved register bits that were missing this information........................ 31
• Added that register 0x00[7:1] does not auto update IDX strapped address ....................................................31
• Added description for 0x05 bits 1 and 0 (TX_MODE_12b and TX_MODE_10b)............................................. 31
• Added reference to Power over Coax Application report..................................................................................38
• Clarified description on PDB pin usage during power up ................................................................................ 38
• Added paragraph to explain setting registers if GPO2 state is not determined when PDB goes high ............ 38
• Added GPO2 to suggested power-up sequencing diagram ............................................................................ 38
• timing constraint for PDB to GPO2 delay ........................................................................................................ 38
• Revised coax connection diagram to include pulldown resistor for GPO2 ...................................................... 40
• Revised STP connection diagram to include pulldown resistor for GPO2 .......................................................42
Changes from Revision * (August 2016) to Revision A (December 2016)
Page
• 将“产品预发布”更改为“量产数据发布”。....................................................................................................1
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5 Pin Configuration and Functions
24
23
22
21
20
19
18
17
VDDIO
DIN[6]
GPO[1]
GPO[0]
VDDCML
DOUT+
DOUT-
VDDT
DAP = GND
DIN[7]
VDDD
DS90UB933-Q1
Serializer
DIN[8]
DIN[9]
VDDPLL
DIN[10]
DIN[11]
PDB
1
2
3
4
5
6
7
8
图5-1. RTV Package 32-Pin WQFN Top View
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
LVCMOS PARALLEL INTERFACE
Parallel data Inputs. For 10-bit MODE, parallel inputs DIN[0:9] are active. DIN[10:11] are
inactive and should not be used. Any unused inputs (including DIN[10:11]) must be No
Connect. For 12-bit MODE, parallel inputs DIN[0:11] are active. Any unused inputs must be
No Connect.
19,20,21,22,
23,24,26,27,
29,30,31,32
Inputs,
LVCMOS
w/ pulldown
DIN[0:11]
Input,
LVCMOS
Horizontal SYNC input. Note: HS transition restrictions: 1. 12-bit mode: No HS restrictions
(raw) 2. 10-bit mode: HS restricted to no more than one transition per 10 PCLK cycles.
HSYNC
VSYNC
PCLK
1
2
3
w/ pulldown Leave open if unused.
Input,
LVCMOS
Vertical SYNC input. Note: VS transition restrictions: 1. 12-bit mode: No VS restrictions (raw)
2. 10-bit mode: VS restricted to no more than one transition per 10 PCLK cycles. Leave
w/ pulldown open if unused.
Input,
LVCMOS
Pixel clock input pin. Strobe edge set by TRFB control register 0x03[0].
w/ pulldown
GENERAL PURPOSE OUTPUT (GPO)
General-purpose output pins can be configured as outputs, used to control and respond to
various commands. GPO[1:0] can be configured to be the outputs for input signals coming
from GPIO[1:0] pins on the deserializer or can be configured to be outputs of the local
register on the serializer. Leave open if unused.
Output,
LVCMOS
GPO[1:0]
16,15
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English Data Sheet: SNLS546
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PIN
I/O
DESCRIPTION
NAME
NO.
GPO[2] pin can be configured to be the output for input signal coming from the GPIO[2] pin
on the deserializer or can be configured to be the output of the local register on the
Serializer. It can also be configured to be the output clock pin when the DS90UB933-Q1
device is used in the external oscillator mode. See 节7.4 for a detailed description of
External Oscillator mode. It is recommended to pull GPO2 to GND with a minimum 40-kΩ
resistor to ensure GPO2=LOW when PDB transitions from LOW to HIGH.
GPO[2]/
CLKOUT
Output,
LVCMOS
17
GPO[3] can be configured to be the output for input signals coming from the GPIO[3] pin on
the deserializer or can be configured to be the output of the local register setting on the
serializer. It can also be configured to be the input clock pin when the DS90UB933-Q1
serializer is working with an external oscillator. See 节7.4 for a detailed description of
external oscillator mode. Leave open if unused.
GPO[3]/
CLKIN
Input/Output,
LVCMOS
18
BIDIRECTIONAL CONTROL BUS - I2C-COMPATIBLE
Input/Output, Clock line for the bidirectional control bus communication
Open Drain SCL requires an external pullup resistor to V(VDDIO)
SCL
SDA
4
5
.
Input/Output, Data line for the bidirectional control bus communication
Open Drain SDA requires an external pullup resistor to V(VDDIO)
.
Device mode select
Resistor (Rmode) to ground and 10-kΩ pullup to 1.8 V rail. MODE pin on the serializer can
be used to select whether the system is running off the PCLK from the imager or an external
oscillator. See details in 表7-2.
MODE
8
Input, analog
Device ID Address Select
The IDX pin on the serializer is used to assign the I2C device address. Resistor (RID) to
IDX
6
Input, analog
Ground and 10-kΩ pullup to 1.8 V rail. See 表7-6.
CONTROL AND CONFIGURATION
Power-down mode input pin
Input,
LVCMOS
PDB = H, Serializer is enabled and is ON.
PDB = L, Serializer is in power down mode. When the serializer is in power down, the PLL is
PDB
9
w/ pulldown shut down, and IDD is minimized. Programmed control register data is NOT retained and
reset to default values.
Input,
Reserved
RES
7
LVCMOS
This pin MUST be tied LOW.
w/ pulldown
FPD–Link III INTERFACE
Input/Output, Non-inverting differential output, bidirectional control channel input. The interconnect must
DOUT+
13
CML
be AC coupled with a 0.1-µF capacitor.
Inverting differential output, bidirectional control channel input. The interconnect must be AC
coupled with a 0.1-µF capacitor. For applications using single-ended coaxial interconnect,
place a 0.047-µF AC-coupling capacitor in series with a 50-Ωresistor before terminating to
GND.
Input/Output,
CML
DOUT-
12
POWER AND GROUND(1)
Power,
Analog
VDDPLL
VDDT
10
11
PLL power, 1.8 V ±5%.
Power,
Analog
Tx analog power, 1.8 V ±5%.
Power,
Analog
VDDCML
VDDD
14
28
25
CML and bidirectional channel driver power, 1.8 V ±5%.
Power, Digital Digital Power, 1.8 V ±5%.
Power for I/O stage. The single-ended inputs and SDA, SCL are powered from V(VDDIO)
VDDIO can be connected to a 1.8 V ±5% or 2.8 V ±10% or 3.3 V ±10%.
.
VDDIO
Power, Digital
Ground, DAP
DAP must be grounded. DAP is the large metal contact at the bottom side, located at the
center of the WQFN package. Connected to the ground plane (GND) with at least 9 vias.
VSS
DAP
(1) See 节8.1.2.
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English Data Sheet: SNLS546
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
−0.3
−0.3
–0.3
MAX
UNIT
V
2.5
Supply voltage –V(VDD_n) (V(VDDPLL), V(VDDT), V(VDDCML), V(VDDD)
)
4
V
Supply voltage –V(VDDIO)
LVCMOS input voltage
V(VDDIO) + 0.3
V(VDD_n) + 0.3
150
V
V
FPD-Link III I/O voltage –V(VDD_n)
Junction temperature
°C
°C
Storage temperature, Tstg
150
−65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under 节6.3.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per AEC Q100-002(1)
HBM ESD Classification Level 3B
±8000
Charged device model (CDM), per AEC
Q100-011
CDM ESD Classification Level C6
Corner pins (1, 8, 9, 16, 17, 24, 25, 32)
±1000
Other pins
Air Discharge
(DOUT+, DOUT-, RIN+, RIN-)
±25000
±7000
Electrostatic
discharge
(IEC 61000-4-2)
D R = 330 Ω, Cs = 150 pF
V(ESD)
V
Contact Discharge
(DOUT+, DOUT-, RIN+, RIN-)
Air Discharge
(DOUT+, DOUT-, RIN+, RIN-)
±15000
±8000
(ISO10605)
RD = 330 Ω, Cs = 150/330 pF
RD = 2 KΩ, Cs = 150/330 pF
Contact Discharge
(DOUT+, DOUT-, RIN+, RIN-)
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.71
1.71
3
NOM
1.8
MAX
UNIT
Supply voltage, V(VDD_n)
LVCMOS supply voltage
1.89
1.89
3.6
3.08
25
V
V
V(VDDIO)= 1.8 V
V(VDDIO)= 3.3 V
V(VDDIO)= 2.8 V
V(VDD_n) = 1.8 V
V(VDDIO) = 1.8 V
V(VDDIO) = 3.3 V
1.8
3.3
2.52
2.8
Supply noise(1)
mVp-p
25
50
Power-Over-Coax Supply
Noise
ƒ= 30 Hz - 1 KHz, trise > 100 µs
Measured differentially between DOUT+ and DOUT–
(coax mode only)
35
35
mVp-p
mVp-p
ƒ= 1 KHz - 50 MHz
Measured differentially between DOUT+ and DOUT-
(coax mode only)
Operating free air temperature, TA
PCLK clock frequency - 10-bit mode
PCLK clock frequency - 12-bit mode
25
105
100
100
°C
–40
50
MHz
MHz
37.5
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over operating free-air temperature range (unless otherwise noted)
MIN
25
NOM
MAX
UNIT
MHz
MHz
External clock input frequency to GPO3 - 10-bit mode
External clock input frequency to GPO3 - 12-bit mode
50
66.67
25
(1) Supply noise testing was done with minimum capacitors (as shown on 图8-9, 图8-5 on the PCB. A sinusoidal signal is AC coupled to
the V(VDD_n) (1.8 V) supply with amplitude = 25 mVp-p measured at the device V(VDD_n) pins. Bit error rate testing of input to the
serializer and output of the deserializer with 10-meter cable shows no error when the noise frequency on the serializer is less than 1
MHz. The deserializer, on the other hand, shows no error when the noise frequency is less than 750 kHz.
6.4 Thermal Information
DS90UB933-Q1
THERMAL METRIC(1)
RTV (WQFN)
32 PINS
34.9
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJC(bot)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-case (bottom) thermal resistance
Junction-to-board thermal resistance
8.8
3.4
23.4
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.3
ψJT
8.8
ψJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
6.5 Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.(1) (2) (3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
LVCMOS DC SPECIFICATIONS 3.3 V I/O (SER INPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)
VIH
VIL
High level input voltage VIN = 3 V to 3.6 V
2
GND
–20
2.4
VIN
0.8
V
V
Low level input voltage
Input current
VIN = 3 V to 3.6 V
IIN
VIN = 0 V or 3.6 V, VIN = 3 V to 3.6 V
V(VDDIO) = 3 V to 3.6 V, IOH = −4 mA
±1
20
µA
V
VOH
VOL
High level output voltage
V(VDDIO)
0.4
Low level output voltage V(VDDIO) = 3 V to 3.6 V, IOL = 4 mA
GND
V
Output short-circuit
current
Serializer
GPO outputs
IOS
VOUT = 0 V
mA
–15
PDB = 0 V,
VOUT = 0 V or V(VDDIO)
Serializer
GPO outputs
IOZ
Tri-state output current
Pin capacitance
20
µA
pF
–20
CGPO
GPO [3:0]
1.5
LVCMOS DC SPECIFICATIONS 1.8 V I/O (SER INPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)
VIH
VIL
IIN
High level input voltage VIN = 1.71 V to 1.89 V
0.65 VIN
GND
VIN
0.35 VIN
20
V
Low level input voltage
Input current
VIN = 1.71 V to 1.89 V
VIN = 0 V or 1.89 V, VIN = 1.71 V to 1.89 V
±1
µA
V
–20
V(VDDIO)
–
VOH
VOL
IOS
High level output voltage
V(VDDIO)
0.45
V(VDDIO) = 1.71 V to 1.89 V, IOH = −4 mA
0.45
Low level output voltage V(VDDIO) = 1.71 V to 1.89 V IOL = 4 mA
GND
V
Output short-circuit
current
Serializer
GPO outputs
VOUT = 0 V
mA
–11
PDB = 0 V,
VOUT = 0 V or V(VDDIO)
Serializer
GPO outputs
IOZ
Tri-state output current
Pin capacitance
20
1
µA
–20
–1
CGPO
GPO [3:0]
1.5
pF
µA
IIN_STRAP Strap pin input current
VIN = 0 V to VDD_n
MODE, IDX
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MAX UNIT
Over recommended operating supply and temperature ranges unless otherwise specified.(1) (2) (3)
PARAMETER
TEST CONDITIONS
MIN
TYP
LVCMOS DC SPECIFICATIONS 2.8 V I/O (SER INPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)
VIH
VIL
High level input voltage VIN = 2.52 V to 3.08 V
0.7 VIN
GND
VIN
0.3 VIN
20
V
Low level input voltage
Input current
VIN = 2.52 V to 3.08 V
IIN
VIN = 0 V or 3.08 V, VIN = 2.52 V to 3.08 V
V(VDDIO) = 2.52 V to 3.08 V, IOH = −4 mA
±1
µA
V
–20
VOH
VOL
High level output voltage
V(VDDIO) - 0.4
GND
V(VDDIO)
0.4
Low level output voltage V(VDDIO) =2.52 V to 3.08V IOL = 4 mA
V
Output short-circuit
current
Serializer
GPO outputs
IOS
VOUT = 0 V
mA
–11
PDB = 0 V,
VOUT = 0 V or V(VDDIO)
Serializer
GPO outputs
IOZ
Tri-state output current
Pin capacitance
20
µA
pF
–20
CGPO
GPO [3:0]
1.5
CML DRIVER DC SPECIFICATIONS (DOUT+, DOUT–)
Differential output
voltage
VOD
640
320
824
412
50
RL = 100 Ω (图6-6)
RL = 50 Ω (图6-6)
RL = 100 Ω
mV
mV
Single-ended output
voltage
VOUT
ΔVOD
VOS
Differential output
voltage unbalance
1
V(VDD_n)
–
(VOD /2)
Output offset voltage
V
RL = 100 Ω (图6-6)
RL = 100 Ω
Offset voltage unbalance
1
50
mV
mA
ΔVOS
Output short-circuit
current
IOS
DOUT+ = 0 V or DOUT–= 0 V
Differential across DOUT+ and DOUT–
DOUT+ or DOUT–
–26
Differential internal
termination resistance
80
40
100
50
120
60
RT
Ω
Single-ended
termination resistance
Back channel differential
input voltage
VID-BC
VIN-BC
260
130
mV
mV
Back Channel Frequency = 5.5 MHz(4)
Back channel single-
ended input voltage
SERIALIZER SUPPLY CURRENT
V(VDD_n) = 1.89 V
V(VDDIO) = 3.6 V
ƒ= 100 MHz, 12-bit
mode
76
61
80
64
95
80
mA
mA
Serializer (Tx)
V(VDD_n) supply current
(includes load current)
RL = 100 Ω
Default registers
IDDT
WORST CASE pattern
(图6-2)
V(VDD_n) = 1.89 V
V(VDDIO) = 3.6 V
ƒ= 75 MHz, 12-bit
mode
Default registers
V(VDD_n) = 1.89 V
V(VDDIO) = 3.6 V
ƒ= 100 MHz, 12-bit
mode
Serializer (Tx)
V(VDD_n) supply current
(includes load current)
RL = 100 Ω
RANDOM PRBS-7
pattern
Default Registers
IDDT
mA
V(VDD_n) = 1.89 V
V(VDDIO) = 3.6 V
ƒ= 75 MHz, 12-bit
mode
Default Registers
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Over recommended operating supply and temperature ranges unless otherwise specified.(1) (2) (3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
V(VDDIO) = 1.89 V
ƒ= 75 MHz, 12-bit
mode
Default Registers
1.5
3
Serializer (Tx)
V(VDDIO) supply current
(includes load current)
RL = 100 Ω
WORST CASE pattern
(图6-2)
I(VDDIO)T
mA
V(VDDIO) = 3.6 V
ƒ= 75 MHz, 12-bit
mode
5
8
Default registers
V(VDDIO)=1.89 V
Default registers
300
300
15
1000
1000
100
µA
µA
µA
µA
Serializer (Tx) supply
current power down
PDB = 0 V; All other
LVCMOS inputs = 0 V
IDDTZ
V(VDDIO) = 3.6 V
Default registers
V(VDDIO) = 1.89 V
Default registers
Serializer (Tx) V(VDDIO)
I(VDDIO)TZ supply current power
down
PDB = 0 V; All other
LVCMOS inputs = 0 V
V(VDDIO) = 3.6 V
Default registers
15
100
(1) The Electrical Characteristics tables list verified specifications under the listed 节6.3 except as otherwise modified or specified by the
Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not verified.
(2) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD and ΔVOD which are differential voltages.
(3) Typical values represent most likely parametric norms at 1.8 V or 3.3 V, TA = 25°C, and at the 节6.3 at the time of product
characterization and are not verified.
(4) The back channel frequency (MHz) listed is the frequency of the internal clock used to generate the encoded back channel data
stream. The data rate (Mbps) of the encoded back channel stream is the back channel frequency divided by 2.
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6.6 Recommended Serializer Timing For PCLK
Over recommended operating supply and temperature ranges unless otherwise specified.(1) (2)
PARAMETER
TEST CONDITIONS
PIN / FREQ
MIN
NOM
MAX
UNIT
10-bit mode
50 MHz –100 MHz
7.52
T
20
26.67
0.6T
0.6T
0.3T
0.3T
ns
tTCP
Transmit clock period
12-bit mode
37.5 MHz - 100 MHz
10
0.4T
T
0.5T
ns
Transmit clock
input high time
tTCIH
tTCIL
Transmit clock
input low time
0.4T
0.5T
10-bit mode
50 MHz –100 MHz
0.05T
0.05T
0.25T
0.25T
PCLK input transition time
(图6-7)
tCLKT
12-bit mode
37.5 MHz –100 MHz
LPF = ƒ/20, CDR PLL Loop BW = ƒPCLK = 37.5
PCLK input jitter (3)
(PCLK from imager mode)
tJIT0
tJIT1
tJIT2
0.45
UI
ƒ/15, BER = 1E-10
–100
MHz(5)
ƒPCLK = 37.5
–100
PCLK input jitter(3)
(External oscillator mode)
LPF = ƒ/20, CDR PLL Loop BW =
ƒ/15, BER = 1E-10
1T
MHz(5)
LPF = ƒ/20, CDR PLL Loop BW = ƒOSC = 25 –
External oscillator jitter(3) (4)
66.67 MHz(6)
0.45
55%
UI
ƒ/15, BER = 1E-10, paired with
DS90UB934-Q1 deserializer
External Oscillator
Frequency Stability
ƒOSC = 25 –
±50
ppm
ΔOSC
66.67 MHz(6)
CLKOUT duty cycle
(external oscillator mode)
ƒOSC = 25 –
tDC
45%
50%
66.67 MHz(6)
(1) Recommended input timing requirements are input specifications and not tested in production.
(2) T is the period of the PCLK.
(3) Typical values represent most likely parametric norms at 1.8 V or 3.3 V, TA = 25°C, and at 节6.3 at the time of product characterization
and are not verified.
(4) 0.45UI maximum when used with DS90UB934-Q1 deserializer. When used with DS90UB914A-Q1 deserializer, the maximum is 0.3UI.
(5) ƒPCLK denotes input PCLK frequency to the device.
(6) ƒOSC denotes input external oscillator frequency to the device (GPO3/CLKIN).
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6.7 AC Timing Specifications (SCL, SDA) - I2C-Compatible
Over recommended supply and temperature ranges unless otherwise specified. (图6-1)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
RECOMMENDED INPUT TIMING REQUIREMENTS
Standard mode
100
400
kHz
kHz
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
µs
µs
ns
ns
ns
ns
SCL Clock Frequency
SCL Low Period
ƒSCL
Fast mode
Standard mode
Fast mode
4.7
1.3
4.0
0.6
4.0
0.6
4.7
0.6
0
tLOW
tHIGH
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tSU:STO
tBUF
Standard mode
Fast mode
SCL high period
Standard mode
Fast mode
Hold time for a start or a repeated start
condition
Standard mode
Fast mode
Setup time for a start or a repeated start
condition
Standard mode
Fast mode
3.45
900
Data hold time
0
Standard mode
Fast mode
250
100
4.0
0.6
4.7
1.3
Data setup time
Standard mode
Fast mode
Setup time for stop condition
Bus free time between stop and start
SCL and SDA rise time
SCL and SDA fall time
Standard mode
Fast mode
Standard mode
Fast mode
1000
300
300
300
tr
Standard mode
Fast mode
tf
6.8 Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I2C-Compatible
Over recommended supply and temperature ranges unless otherwise specified(1)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
RECOMMENDED INPUT TIMING REQUIREMENTS
VIH
VIL
Input high level
Input low level
Input hysteresis
SDA and SCL
0.7 × V(VDDIO)
GND
V(VDDIO)
V
V
SDA and SCL
0.3 ×
V(VDDIO)
VHY
> 50
mV
SDA, V(VDDIO) = 1.8 V, IOL= 0.9 mA
SDA, V(VDDIO) = 3.3 V, IOL= 1.6 mA
SDA or SCL, VIN= V(VDDIO) OR GND
0
0
0.36
0.4
10
VOL
Output low level(2)
V
IIN
tR
Input current
µA
ns
ns
pF
−10
SDA rise time-READ
SDA fall time-READ
430
20
SDA, RPU = 10 kΩ, Cb ≤400 pF (图
6-1)
tF
CIN
SDA or SCL
<5
(1) Specification is verified by design.
(2) FPD-Link device was designed primarily for point-to-point operation and a small number of attached slave devices. As such the
minimum IOL pullup current is targeted to lower value than the minimum IOL in the I2C specification.
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MAX UNIT
6.9 Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
NOM
CML low-to-high
transition time
tLHT
tHLT
tDIS
tDIH
tPLD
150
330
330
ps
ps
ns
ns
ms
RL = 100 Ω (图6-3)
RL = 100 Ω (图6-3)
CML high-to-low
transition time
150
Data input
Setup to PCLK
2
2
Serializer data inputs (图6-8)
RL = 100 Ω (图6-9)
Data input
Hold from PCLK
Serializer PLL lock
time(1) (2)
1
38T
13T
2
44T
15T
RT = 100 Ω, 10–bit mode
Register 0x03h b[0] (TRFB = 1) (图6-10)
32.5T
tSD
Serializer delay(2)
RT = 100 Ω, 12–bit mode
Register 0x03h b[0] (TRFB = 1) (图6-10)
11.75T
Serializer output
PRBS-7 test pattern, CDR PLL Loop
BW = ƒ/15, BER = 1E-10
tJIND
tJINR
tJINT
deterministic jitter (3)
DOUT±
0.17
0.016
0.4
UI
UI
UI
(4) (5)
PRBS-7 test pattern, CDR PLL Loop
BW = ƒ/15, BER = 1E-10
Serializer output
DOUT±
DOUT±
random jitter (3) (4) (5)
Peak-to-peak
PRBS-7 test pattern, CDR PLL Loop
BW = ƒ/15, BER = 1E-10
serializer output total
jitter(3) (5) (6)
10–bit mode
PCLK = 100 MHz, Default registers
2.2
2.2
Serializer jitter
transfer function
–3 dB bandwidth
λSTXB
MHz
W
12–bit mode
PCLK = 100 MHz, Default registers
10–bit mode
PCLK = 100 MHz, Default registers
1.06
1.09
Serializer jitter
Transfer Function
(peaking)
dB
δSTX
12–bit mode
PCLK = 100 MHz, Default registers
Serializer jitter
transfer function
(peaking frequency)
10–bit mode
PCLK = 100 MHz, Default registers
400
kHz
δSTXf
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Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX UNIT
12–bit mode
PCLK = 100 MHz, Default registers
500
(1) tPLD is the time required by the serializer to obtain lock when exiting power-down state with an active PCLK.
(2) Specification is verified by design.
(3) Typical values represent most likely parametric norms at 1.8 V or 3.3 V, TA = 25°C, and at 节6.3 at the time of product characterization
and are not verified.
(4) Specification is verified by characterization and is not tested in production.
(5) UI –Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.
10-bit mode: 1 UI = 1 / ( PCLK_Freq. /2 × 28 )
12-bit mode: 1 UI = 1 / ( PCLK_Freq. × 2/3 × 28 )
(6) Serializer output peak-to-peak total jitter includes deterministic jitter, random jitter, and jitter transfer from serializer input.
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6.10 Timing Diagrams
SDA
t
BUF
t
t
f
t
HD;STA
t
LOW
r
t
f
t
r
SCL
t
t
HD;STA
SU;STA
t
SU;STO
t
HIGH
t
t
SU;DAT
HD;DAT
STOP START
START
REPEATED
START
图6-1. Bidirectional Control Bus Timing
Signal Pattern
Device Pin Name
80%
80%
T
Vdiff
Vdiff = 0 V
PCLK
(RFB = H)
20%
20%
tLHT
tHLT
D
/R
IN OUT
Vdiff = (DOUT+) - (DOUT-)
图6-3. Serializer CML Output Load and Transition
图6-2. “Worst Case”Test Pattern for Power
Times
Consumption
100 nF
D
+
OUT
50 W
SCOPE
BW 8 4.0 GHz
Z
= 100 W
100 W
Diff
50 W
D
OUT
-
100 nF
Copyright © 2016, Texas Instruments Incorporated
图6-4. Measurement Setup Serializer CML Output Load and Transition Times
10/12,
HS,VS
D
D
+
-
OUT
R
L
D
IN
OUT
PCLK
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图6-5. Serializer VOD Setup
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Single-Ended
V
ö
OS
V
V
OUT
OUT
D
+ or D
OUT
-
OUT
Differential
V
OD
0V
(D
+) - (D
OUT
-)
OUT
图6-6. Serializer VOD Diagram
V
DD
t
TCP
80%
80%
PCLK
20%
20%
PCLK
V
DDIO
/2
V
/2
V
V
/2
DDIO
DDIO
0V
t
t
t
t
DIH
CLKT
CLKT
DIS
DDIO
图6-7. Serializer Input Clock Transition Times
DINn
Setup
Hold
V
/2
DDIO
V
/2
DDIO
0V
图6-8. Serializer Setup/Hold Times
VDDIO/2
PDB
PCLK
t
PLD
Output Active
TRI-STATE
TRI-STATE
D
OUT
图6-9. Serializer PLL Lock Time
SYMBOL N
SYMBOL N+1
SYMBOL N+2
SYMBOL N+3
D
IN
t
SD
VDDIO/2
PCLK
SYMBOL N-4
SYMBOL N-3
SYMBOL N-2
SYMBOL N-1
SYMBOL N
0V
DOUT+-
图6-10. Serializer Delay
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6.11 Typical Characteristics
4
2
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
- 2
- 4
- 6
- 8
-10
-12
-14
-16
-18
1.0E+05
1.0E+06
1.0E+07
1.0E+04
0.1
1
Jitter Frequency (MHz)
10
MODULATION FREQUENCY (Hz)
图6-11. Typical Serializer Jitter Transfer Function
图6-12. Typical System Input Jitter Tolerance
Curve - DS90UB933 Linked to DS90UB934
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7 Detailed Description
7.1 Overview
The DS90UB933-Q1 is optimized to interface with the DS90UB934-Q1 or DS90UB964-Q1 using a 50-Ω coax
interface. The DS90UB933-Q1 also works with the DS90UB934-Q1 or DS90UB964-Q1 using an STP interface.
The DS90UB933/934 FPD-Link III chipsets are intended to link mega-pixel camera imagers and video
processors in ECUs. The Serializer/Deserializer chipset can operate from 37.5 MHz to 100 MHz pixel clock
frequency. The DS90UB933-Q1 device transforms a 10/12-bit wide parallel LVCMOS data bus along with a
bidirectional control channel control bus into a single high-speed differential pair. The high-speed serial bit
stream contains an embedded clock and DC-balanced information which enhances signal quality to support AC
coupling. The DS90UB934-Q1 device receives the single serial data stream and converts it back into a 10/12-bit
wide parallel data bus together with the control channel data bus. The DS90UB933/934 chipsets can accept up
to:
• 12-bits of DATA + 2 SYNC bits for an input PCLK range of 37.5 MHz to 100 MHz in the 12-bit mode. Note: No
HS/VS restrictions (raw).
• 10-bits of DATA + 2 SYNC bits for an input PCLK range of 50 MHz to 100 MHz in the 10-bit mode. Note:
HS/VS restricted to no more than one transition per 10 PCLK cycles.
The DS90UB933/934 chipset offer customers the choice to work with different clocking schemes. The
DS90UB933/934 chipsets can use an external oscillator as the reference clock source for the PLL (see 节 7.4.1)
or PCLK from the imager as primary reference clock to the PLL (see 节7.4.2).
7.2 Functional Block Diagram
10 or
12
DIN
R
T
R
T
DOUT+
DOUT-
HSYNC
VSYNC
4
GPO[3:0]
Clock
Gen
PCLK
PLL
PDB
Timing and
Control
SDA
SCL
ID[x]
MODE
DS90UB933-Q1 - SERIALIZER
Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 Serial Frame Format
The high-speed forward channel is composed of 28 bits of data containing video data, sync signals, I2C, and
parity bits. This data payload is optimized for signal transmission over an AC-coupled link. Data is randomized,
balanced and scrambled. The 28-bit frame structure changes in the 12-bit mode and 10-bit mode internally and
is seamless to the customer. The bidirectional control channel data is transferred over the single serial link along
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with the high-speed forward data. This architecture provides a full-duplex low-speed forward and backward path
across the serial link together with a high-speed forward channel without the dependence on the video blanking
phase.
7.3.2 Line Rate Calculations for the DS90UB933/934
The DS90UB933-Q1 device divides the clock internally by divide-by-2 in the 10-bit mode and by divide-by-1.5 in
the 12-bit mode. Conversely, the DS90UB934-Q1 multiplies the recovered serial clock to generate the proper
pixel clock output frequency. The following are the formulae used to calculate the maximum line rate in the
different modes:
• For the 12-bit mode, Line rate = ƒPCLK × (2/3) × 28; for example, ƒPCLK = 100 MHz, line rate = (100 MHz) ×
(2/3) × 28 = 1.87 Gbps
• For the 10-bit mode, Line rate = ƒPCLK/2 × 28; for example, ƒPCLK = 100 MHz, line rate = (100 MHz/2) × 28 =
1.40 Gbps
7.3.3 Error Detection
The chipset provides error detection operations for validating data integrity in long distance transmission and
reception. The data error detection function offers users flexibility and usability of performing bit-by-bit data
transmission error checking. The error detection operating modes support data validation of the following
signals:
• Bidirectional control channel data across the serial link
• Parallel video/sync data across the serial link
The chipset provides 1 parity bit on the forward channel and 4 cyclic redundancy check (CRC) bits on the back
channel for error detection purposes. The DS90UB933/934 chipset checks the forward and back channel serial
links for errors and stores the number of detected errors in two 8-bit registers in the serializer and the
deserializer, respectively.
To check parity errors on the forward channel, monitor registers 0x55 and 0x56 on the DS90UB934. The parity
error counter registers return the number of data parity errors that have been detected on the FPD3 receiver
data since the last detection of valid lock or last read of these registers (0x55 and 0x56). These registers are
cleared on read.
To check CRC errors on the back channel, monitor registers 0x0A and 0x0B on the serializer.
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7.3.4 Synchronizing Multiple Cameras
For applications requiring multiple cameras for frame-synchronization, TI recommends using the general
purpose input/output (GPIO) pins to transmit control signals to synchronize multiple cameras together. To
synchronize the cameras properly, the system controller must provide a field sync output (such as a vertical or
frame sync signal), and the cameras must be set to accept an auxiliary sync input. The vertical synchronize
signal corresponds to the start and end of a frame and the start and end of a field. Note this form of
synchronization timing relationship has a non-deterministic latency. After the control data is reconstructed from
the bidirectional control channel, there is a time variation of the GPIO signals arriving at the different target
devices (between the parallel links). The maximum latency (t1) of the GPIO data transmitted across the link is 32
µs.
备注
The user must verify that the timing variations between the different links are within their system and
timing specifications.
See 图7-1 for an example of this function.
The maximum time (t2) between the time the GPIO signal arrives at Camera A and Camera B is 23 µs.
Serializer A
Camera A
Deserializer A
CMOS
Image
Sensor
DATA
PCLK
DATA
PCLK
FSYNC
FSYNC
I2C
I2C
ECU
Module
Camera B
Serializer B
Deserializer B
CMOS
Image
Sensor
DATA
PCLK
DATA
PCLK
FSYNC
FSYNC
I2C
I2C
mC
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图7-1. Synchronizing Multiple Cameras
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DES A
GPIO[n] Input
DES B
GPIO[n] Input
SER A
GPIO[n] Output
SER B
GPIO[n] Output
t2
t1
图7-2. GPIO Delta Latency
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7.3.5 General Purpose I/O (GPIO) Descriptions
There are 4 GPOs on the serializer and 4 GPIOs on the deserializer when the DS90UB933/934 chipsets are run
off the pixel clock from the imager as the reference clock source. The GPOs on the serializer can be configured
as outputs for the input signals that are fed into the deserializer GPIOs. In addition, the GPOs on the serializer
can behave as outputs of the local register on the serializer. The GPIOs on the deserializer can be configured to
be the input signals feeding the GPOs (configured as outputs) on the serializer. In addition the GPIOs on the
deserializer can be configured to behave as outputs of the local register on the deserializer. The DS90UB933-Q1
serializer GPOs cannot be configured as inputs for remote communication with deserializer. If the
DS90UB933/934 chipsets are run off the external oscillator source as the reference clock, then GPO3 on the
serializer is automatically configured to be the input for the external clock and GPO2 is configured to be the
output of the divide-by-2 clock which is fed into the imager as its reference clock. In this case, the GPIO2 and
GPIO3 on the deserializer can only behave as outputs of the local register on the deserializer. The GPIO
maximum switching rate is up to 66 kHz when configured for communication between deserializer GPIO to
serializer GPO.
7.3.6 LVCMOS V(VDDIO) Option
1.8 V/2.8 V/3.3 V Serializer inputs are user configurable to provide compatibility with 1.8 V, 2.8 V, and 3.3 V
system interfaces.
7.3.7 Pixel Clock Edge Select (TRFB / RRFB)
The TRFB/RRFB selects which edge of the pixel clock is used. For the SER, this register determines the edge
that the data is latched on. If TRFB register is 1, data is latched on the rising edge of the PCLK. If TRFB register
is 0, data is latched on the falling edge of the PCLK. For the DES, this register determines the edge that the data
is strobed on. If RRFB register is 1, data is strobed on the rising edge of the PCLK. If RRFB register is 0, data is
strobed on the falling edge of the PCLK.
PCLK
DIN/
ROUT
TRFB/RRFB: 0
TRFB/RRFB: 1
图7-3. Programmable PCLK Strobe Select
7.3.8 Power Down
The SER has a PDB input pin to ENABLE or power down the device. Enabling PDB on the SER disables the link
to save power. If PDB = HIGH, the SER operates at its internal default oscillator frequency when the input PCLK
stops. When the PCLK starts again, the SER locks to the valid input PCLK and transmit the data to the DES.
When PDB = LOW, the high-speed driver outputs are static HIGH. See 节8.1.2 for power-up requirements.
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7.4 Device Functional Modes
7.4.1 DS90UB933/934 Operation With External Oscillator as Reference Clock
In some applications, the pixel clock that comes from the imager can have jitter which exceeds the tolerance of
the DS90UB933/934/964 chipsets. In this case, operate the DS90UB933-Q1 device by using an external clock
source as the reference clock for the DS90UB933/934/964 chipsets. This is the recommended operating mode.
The external oscillator clock output goes through a divide-by-2 circuit in the DS90UB933-Q1 serializer, and this
divided clock output is used as the reference clock for the imager. The output data and pixel clock from the
imager are then fed into the DS90UB933-Q1 device. 图 7-4 shows the operation of the DS90UB33/934 chipsets
while using an external automotive grade oscillator.
Serializer
Deserializer
FPD Link III-
High Speed
Camera Data
Camera Data
DOUT+
RIN+
10 or 12
10 or 12
ROUT[11:0]
or
ROUT[9:0]
HSYNC,
VSYNC
DIN[11:0] or
DATA
Image
Sensor
DATA
DIN[9:0]
HSYNC,
VSYNC
HSYNC
HSYNC
DOUT-
RIN-
VSYNC
VSYNC
Bi-Directional
Control Channel
PCLK
PCLK
ECU Module
Pixel Clock
Pixel Clock
SDA
SCL
SDA
SCL
2
4
PLL
GPIO[3:0]
GPO[1:0]
GPO[3:0]
Microcontroller
GPO[1:0]
SDA
SCL
SDA
SCL
Camera Unit
GPO3
Reference Clock
(Ext. OSC/2)
÷2
GPO2
External
Oscillator
Copyright © 2016, Texas Instruments Incorporated
图7-4. DS90UB933-Q1/934-Q1 Operation in the External Oscillator Mode
When the DS90UB933-Q1 device is operated using an external oscillator, the GPO3 pin on the DS90UB933-Q1
is the input pin for the external oscillator. In applications where the DS90UB933-Q1 device is operated from an
external oscillator, the divide-by-2 circuit in the DS90UB933-Q1 device feeds back the divided clock output to the
imager device through GPO2 pin. The pixel clock to external oscillator ratios must be fixed for the 12–bit mode
and the 10–bit mode. In the 10-bit mode, the pixel clock frequency divided by the external oscillator frequency
must be 2. In the 12-bit mode, the pixel clock frequency divided by the external oscillator frequency must be 1.5.
For example, if the external oscillator frequency is 48 MHz in the 10-bit mode, the pixel clock frequency of the
imager must be twice of the external oscillator frequency, that is, 96 MHz. If the external oscillator frequency is
48 MHz in the 12-bit mode, the pixel clock frequency of the imager must be 1.5 times of the external oscillator
frequency, that is, 72 MHz. For the range of PCLK frequency and the external clock input frequency to GPO3 in
10-bit and 12-bit modes, see 节6.3.
When PCLK signal edge is detected, and 0x03[1] = 0, the DS90UB933-Q1 switches from internal oscillator
mode to an external PCLK. Upon removal of PCLK input, the device switches back into internal oscillator mode.
In external oscillator mode, GPO2 and GPO3 on the serializer cannot act as the output of the input signal
coming from GPIO2 or GPIO3 on the deserializer.
表7-1. Device Functional Mode With Example XCLKIN = 48 MHz
GPIO2 XCLKOUT =
XCLKIN / 2
INPUT PCLK FREQUENCY =
XLCKIN * RATIO
MODE
GPIO3 XCLKIN
RATIO
10-bit
48 MHz
24 MHz
2
96 MHz
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MODE
表7-1. Device Functional Mode With Example XCLKIN = 48 MHz (continued)
GPIO2 XCLKOUT =
XCLKIN / 2
INPUT PCLK FREQUENCY =
XLCKIN * RATIO
GPIO3 XCLKIN
RATIO
12-bit
48 MHz
24 MHz
1.5
72 MHz
7.4.2 DS90UB933/934 Operation With Pixel Clock From Imager as Reference Clock
The DS90UB933/934/964 chipsets can be operated by using the pixel clock from the imager as the reference
clock. 图 7-5 shows the operation of the DS90UB933/934/964 chipsets using the pixel clock from the imager. If
the DS90UB933-Q1 device is operated using the pixel clock from the imager as the reference clock, then the
imager uses an external oscillator as its reference clock. There are 4 GPIOs available in this mode (PCLK from
imager mode).
Serializer
Deserializer
Camera Data
Camera Data
FPD-Link III
DOUT+
DOUT-
10 or 12
RIN0+
RIN0-
10 or 12
ROUT[11:0]
or
ROUT[9:0]
FV, LV
Image
Sensor
DIN[11:0] or
DIN[9:0]
FV,LV
YUV
YUV
HSYNC
HSYNC
VSYNC
SDA
VSYNC
Bi-Directional
Back Channel
SDA
SCL
PCLK
ECU Module
Pixel Clock
SCL
RIN1+
RIN1-
4
4
GPO[3:0]
PCLK
GPIO[3:0]
GPO
GPIO
Microcontroller
PLL
SDA
SCL
Pixel Clock
SDA
SCL
Camera Unit
Ext.
Oscillator
Copyright © 2016, Texas Instruments Incorporated
图7-5. DS90UB933-Q1/934-Q1 Operation in PCLK mode
7.4.3 MODE Pin on Serializer
The MODE pin on the serializer can be configured to select if the DS90UB933-Q1 device is to be operated from
the external oscillator or the PCLK from the imager. The pin must be pulled to VDD_n(1.8 V, not VDDIO) with a
resistor R1 and a pulldown resistor R2 for external oscillator mode to create the ratio shown in 图 7-6. If the
device is to be operated from PCLK from imager mode, MODE pin can be pulled up to VDD_n (1.8V) with a 10-kΩ
resistor directly or use the ratio shown in 图 7-6 and 表 7-2. Suggested resistor values are given in 表 7-2. The
recommended maximum resistor tolerance is 1%. Other resistor values can be used as long as the ratio is met
under all conditions.
1.8 V
R
R
1
MODE
V
MODE
2
Serializer
图7-6. MODE Pin Configuration on DS90UB933-Q1
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表7-2. DS90UB933-Q1 Serializer
MODE Setting
DS90UB933-Q1 SERIALIZER MODE SETTING
SUGGESTED R1
RESISTOR VALUE (kΩ)
SUGGESTED R2 RESISTOR
MINIMUM RATIO
MAXIMUM RATIO
(VMODE/V(VDD_n))
MODE SELECT
(VMODE/V(VDD_n)
)
VALUE (kΩ)
PCLK from imager
mode
0.750
1.000
10
50
External oscillator
mode
0.292
0.339
10
4.7
7.4.4 Internal Oscillator
When a PCLK is not applied to the DS90UB933-Q1, the serializer establishes the FPD-III link using an internal
oscillator. During normal operation (not BIST) the frequency of the internal oscillator can be adjusted from
DS90UB933-Q1 register 0x14[2:1] according to 表 7-3. In BIST mode, the internal oscillator frequency should
only be adjusted from the DS90UB934-Q1. The BIST frequency can be set by either pin strapping (表 7-4) or
register (表 7-5). In BIST DS90UB933-Q1 register 0x14[2:1] is automatically loaded from the DS90UB934-Q1
through the bi-directional control channel.
表7-3. Clock Sources for Forward Channel Frame on the Serializer During Normal Operation
DS90UB933-Q1
Reg 0x14 [2:1]
10-BIT
MODE
12-BIT
MODE
00
01
10
11
50 MHz
100 MHz
50 MHz
37.5 MHz
75 MHz
37.5 MHz
Reserved
Reserved
7.4.5 Built-In Self Test
An optional at-speed built-in self test (BIST) feature supports the testing of the high-speed serial link and low-
speed back channel. This is useful in the prototype stage, equipment production, and in-system test and also for
system diagnostics.
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7.4.6 BIST Configuration and Status
The chipset can be programmed into BIST mode using either pins or registers on the DES only. By default, BIST
configuration is controlled through pins. BIST can be configured via registers using BIST Control register (0xB3).
Pin-based configuration is defined as follows:
• BISTEN = HIGH: Enable the BIST mode, BISTEN = LOW: Disable the BIST mode.
• Deserializer GPIO0 and GPIO1: Defines the BIST clock source (PCLK vs various frequencies of internal
OSC)
表7-4. BIST Pin Configuration
DESERIALIZER GPIO[0:1]
OSCILLATOR SOURCE
External PCLK
Internal
BIST FREQUENCY
PCLK or external oscillator
~50 MHz
00
01
10
Internal
~25 MHz
表7-5. BIST Register Configuration
DS90UB934-Q1
Reg 0xB3 [2:1]
10-BIT
MODE
12-BIT
MODE
00
01
10
11
PCLK
PCLK
100 MHz
50 MHz
75 MHz
37.5 MHz
Reserved
Reserved
BIST mode provides various options for the PCLK source. Either external pins (GPIO0 and GPIO1) or registers
can be used to program the BIST to use external PCLK or various OSC frequencies. Refer to 表 7-4 for pin
settings. The BIST status can be monitored real-time on the PASS pin. For every frame with error(s), the PASS
pin toggles low for one-half PCLK period. If two consecutive frames have errors, PASS toggles twice to allow
counting of frames with errors. Once the BIST is done, the PASS pin reflects the pass/fail status of the last BIST
run only for one PCLK cycle. The status can also be read through I2C for the number of frames in errors. BIST
status register retains results until it is reset by a new BIST session or a device reset. To evaluate BIST in
external oscillator mode, both the external oscillator and PCLK must be present. For all practical purposes, the
BIST status can be monitored from the BIST Error Count register 0x57 on the DS90UB934 deserializer.
7.4.7 Sample BIST Sequence
• Step 1: For the DS90UB933/934 FPD-Link III chipset, BIST mode is enabled via the BISTEN pin of
DS90UB934-Q1 FPD-Link III deserializer. The desired clock source is selected through the deserializer
GPIO0 and GPIO1 pins as shown in 表7-4.
• Step 2: The DS90UB933-Q1 serializer BIST pattern is enabled through the back channel. The BIST pattern
is sent through the FPD-Link III to the deserializer. Once the serializer and deserializer are in the BIST mode
and the deserializer acquires lock, the PASS pin of the deserializer goes high, and BIST starts checking the
FPD-Link III serial stream. If an error in the payload is detected, the PASS pin switches low for one half of the
clock period. During the BIST test, the PASS output can be monitored and counted to determine the payload
error rate.
• Step 3: To stop the BIST mode, the deserializer BISTEN pin is set LOW. The deserializer stops checking the
data. The final test result is not maintained on the PASS pin. To monitor the BIST status, check the BIST
Error Count register, 0x57 on the deserializer.
• Step 4: The link returns to normal operation after the deserializer BISTEN pin is low. 图7-8 shows the
waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with
multiple errors. In most cases, it is difficult to generate errors due to the robustness of the link (differential
data transmission, etc.); thus, they may be introduced by greatly extending the cable length, faulting the
interconnect, or by reducing signal condition enhancements (Rx equalization).
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Normal
Step 1: DES in BIST
BIST
Wait
Step 2: Wait, SER in BIST
BIST
start
Step 3: DES in Normal
Mode - check PASS
BIST
stop
Step 4: DES/SER in Normal
图7-7. At-Speed BIST System Flow Diagram
BISTEN
(DES)
LOCK
PCLK
(RFB = L)
ROUT[0:11],
HS, VS
DATA
(internal)
PASS
Prior Result
PASS
X = bit error(s)
DATA
(internal)
X
X
X
PASS
FAIL
Prior Result
Normal
BIST
Result
Held
Normal
BIST Test
BIST Duration
图7-8. BIST Timing Diagram
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7.5 Programming
7.5.1 Programmable Controller
An integrated I2C slave controller is embedded in the DS90UB933-Q1 serializer. It must be used to configure the
extra features embedded within the programmable registers or it can be used to control the set of programmable
GPIOs.
7.5.2 Description of Bidirectional Control Bus and I2C Modes
The I2C-compatible interface allows programming of the DS90UB933-Q1, DS90UB934-Q1, DS90UB964-Q1, or
an external remote device (such as image sensor) through the bidirectional control channel. Register
programming transactions to/from the DS90UB933/934/964 chipset are employed through the clock (SCL) and
data (SDA) lines. These two signals have open drain I/Os, and both lines must be pulled up to V(VDDIO) by an
external resistor. Pullup resistors or current sources are required on the SCL and SDA busses to pull them high
when they are not being driven low. A logic LOW is transmitted by driving the output low. Logic HIGH is
transmitted by releasing the output and allowing it to be pulled up externally. The appropriate pullup resistor
values depend upon the total bus capacitance and operating speed. The DS90UB933-Q1 I2C bus data rate
supports up to 400 kbps according to I2C fast mode specifications.
For further description of general I2C communication, refer to the Understanding the I2C Bus application note .
For more information on choosing appropriate pullup resistor values, see the I2C Bus Pullup Resistor Calculation
application note .
Bus Activity:
Master
Register
Address
Slave
Address
Data
SDA Line
7-bit Address
P
S
0
A
C
K
A
C
K
A
C
K
Bus Activity:
Slave
图7-9. Write Byte
N
A
C
K
Bus Activity:
Master
Register
Address
Slave
Address
Slave
Address
S
P
SDA Line
S
7-bit Address
7-bit Address
0
1
A
C
K
A
C
K
A
C
K
Data
Bus Activity:
Slave
图7-10. Read Byte
ACK
LSB
MSB
N/ACK
SDA
SCL
MSB
LSB
R/W
Direction
Bit
7-bit Slave Address
Data Byte
Acknowledge
from the Device
*Acknowledge
or Not-ACK
8
9
8
9
1
2
6
7
1
2
Repeated for the Lower Data Byte
and Additional Data Transfers
START
STOP
图7-11. Basic Operation
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SDA
SCL
S
P
STOP condition
START condition, or
START repeat condition
图7-12. Start and Stop Conditions
7.5.3 I2C Pass-Through
I2C pass-through provides a way to access remote devices at the other end of the FPD-Link III interface. This
option is used to determine if an I2C instruction is transferred over to the remote I2C bus. For example, when the
I2C master is connected to the deserializer and I2C pass-through is enabled on the deserializer, any I2C traffic
targeted for the remote serializer or remote slave is allowed to pass through the deserializer to reach those
respective devices.
If the master controller transmits an I2C transaction for address 0xA0, the DES A with I2C pass-through enabled
transfers I2C commands to remote Camera A. The DES B (with I2C pass-through disabled) will NOT pass I2C
commands on the I2C bus to Camera B.
DS90UB933-Q1
DS90UB934-Q1
CMOS
Image
Sensor
DIN[11:0]
,HS,VS
PCLK
ROUT[11:0],
HS,VS,
PCLK
2
I C
2
I C
SDA
SCL
SDA
SCL
Camera A
Slave ID: (0xA0)
SER A:
Remote I2C _MASTER Proxy
DES A: I2C_SLAVE
Local
I2C_PASS_THRU Enabled
ECU
Module
DS90UB933-Q1
DS90UB934-Q1
CMOS
Image
Sensor
DIN[11:0]
,HS,VS
PCLK
ROUT[11:0],
HS,VS,
PCLK
2
I C
2
I C
SDA
SCL
mC
Camera B
Slave ID: (0xA0)
SER B:
Remote I2C_MASTER Proxy
DES B: I2C_SLAVE
Local
I2C_PASS_THRU Disabled
Master
图7-13. I2C Pass-Through
7.5.4 Slave Clock Stretching
The I2C-compatible interface allows programming of the DS90UB933-Q1, DS90UB934-Q1, DS90UB964-Q1, or
an external remote device (such as image sensor) through the bidirectional control. To communicate and
synchronize with remote devices on the I2C bus through the bidirectional control channel/MCU, the chipset
utilizes bus clock stretching (holding the SCL line low) during data transmission; where the I2C slave pulls the
SCL line low on the 9th clock of every I2C transfer (before the ACK signal). The slave device does not control
the clock and only stretches it until the remote peripheral has responded. The I2C master must support clock
stretching to operate with the DS90UB933/934/964 chipset.
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7.5.5 IDX Address Decoder on the Serializer
The IDX pin on the serializer is used to decode and set the physical slave address of the serializer (I2C only) to
allow up to five devices on the bus connected to the serializer using only a single pin. The pin sets one of the 4
possible addresses for each serializer device. The pin must be pulled to V(VDD_n) (1.8 V, not V(VDDIO)) with a
resistor, R3, and a pulldown resistor R4. Suggested resistor values are given in 表 7-6. The recommended
maximum resistor tolerance is 1%. Other resistor values can be used as long as the ratio is met under all
conditions.
1.8V
R
3
V
DDIO
V
ID[x]
ID[x]
RPU
RPU
R
4
HOST
Serializer
SCL
SDA
SCL
SDA
To other Devices
Copyright © 2016, Texas Instruments Incorporated
图7-14. IDX Address Decoder on the Serializer
表7-6. IDX Setting for DS90UB933-Q1 Serializer
IDX SETTING —DS90UB933-Q1 SERIALIZER
SUGGESTED
R3 RESISTOR R4 RESISTOR
VALUE (kΩ)
SUGGESTED
MINIMUM
RATIO (VIDX
V(VDD_n)
MAXIMUM
RATIO (VIDX/
Address 8-bit
Address 7-bit 0 appended
(WRITE)
/
)
V(VDD_n)
)
VALUE (kΩ)
0
0
Open
10
0
2
0x58
0x59
0x5A
0x5D
0xB0
0xB2
0xB4
0xBA
0.114
0.297
0.742
0.186
0.347
1.0
10
4.7
100
10
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7.5.6 Multiple Device Addressing
Some applications require multiple camera devices with the same fixed address to be accessed on the same I2C
bus. The DS90UB933-Q1 provides slave ID matching/aliasing to generate different target slave addresses when
connecting more than two identical devices together on the same bus. This allows the slave devices to be
independently addressed. Each device connected to the bus is addressable through a unique ID by
programming of the slave alias register on deserializer. This remaps the slave alias address to the target
SLAVE_ID address; up to 8 ID aliases are supported in sensor mode when slaves are attached to the
DS90UB933-Q1 serializer. In display mode, when the external slaves are at the deserializer the DS90UB933-Q1
supports one ID alias. The ECU controller must keep track of the list of I2C peripherals in order to properly
address the target device.
See 图7-15 for an example of this function.
• ECU is the I2C master and has an I2C master interface.
• The I2C interfaces in DES A and DES B are both slave interfaces.
• The I2C protocol is bridged from DES A to SER A and from DES B to SER B.
• The I2C interfaces in SER A and SER B are both master interfaces.
If master controller transmits I2C slave 0xA0, DES A (address 0xC0), with pass-through enabled, forwards the
transaction to remote Camera A. If the controller transmits slave address 0xA4, the DES B 0xC2 recognizes that
0xA4 is mapped to 0xA0 and is transmitted to the remote Camera B. If controller sends command to address
0xA6, the DES B (address 0xC2), with pass-through enabled, forwards the transaction to slave device 0xA2.
Camera A
Slave ID: (0xA0)
DS90UB933-Q1
DS90UB934-Q1
ROUT[11:0],
HS, VS,
PCLK
CMOS
Image
Sensor
DIN[11:0]
, HS, VS,
PCLK
2
I C
2
I C
SDA
SCL
SDA
SCL
DES A: ID[x](0xC0)
SLAVE_ID0_ALIAS(0xA0)
SLAVE_ID0_ID(0xA0)
SLAVE_ID1_ALIAS(0xA2)
SLAVE_ID1_ID(0xA2)
DS90UB934-Q1
mC/
EEPROM
SER A: ID[x](0xB0)
ECU
Module
Slave ID: (0xA2)
Camera B
Slave ID: (0xA0)
DS90UB933-Q1
DIN[11:0]
, HS, VS,
PCLK
ROUT[11:0],
HS, VS,
PCLK
CMOS
Image
Sensor
2
I C
2
I C
SDA
SCL
SDA
SCL
mC
DES B: ID[x](0xC2)
mC/
EEPROM
SER B: ID[x](0xB2)
SLAVE_ID0_ALIAS(0xA4)
SLAVE_ID0_ID(0xA0)
SLAVE_ID1_ALIAS(0xA6)
SLAVE_ID1_ID(0xA2)
Master
Slave ID: (0xA2)
图7-15. Multiple Device Addressing
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7.6 Register Maps
See note(1)
In the register definitions under the TYPE and DEFAULT heading, the following definitions apply:
• R = Read only access
• R/W = Read / Write access
• R/RC = Read only access, Read to Clear
• (R/W)/SC = Read / Write access, Self-Clearing bit
• (R/W)/S = Read / Write access, Set based on strap pin configuration at startup
• LL = Latched Low and held until read
• LH = Latched High and held until read
• S = Set based on strap pin configuration at startup
表7-7. DS90UB933-Q1 Control Registers
Addr
(Hex)
Name
Bits Field
TYPE
Default
Description
7-bit address of serializer (0x58'h default). This field
does not auto update IDX strapped address.
7:1 DEVICE ID
0x00
I2C Device ID
R/W
0xB0
0: Device ID is from IDX
1: Register I2C Device ID overrides IDX
0
7
Serializer ID SEL
RSVD
RDS
R/W
R/W
0
0
Reserved
Digital output drive strength
1: High drive strength
0: Low drive strength
6
5
4
Auto voltage control
1: Enable
0: Disable
V(VDDIO) Control
V(VDDIO) MODE
R/W
R/W
1
1
V(VDDIO) voltage set
1: V(VDDIO) = 3.3 V
0: V(VDDIO) = 1.8 V
This register can be set only through local I2C access.
1: Analog power down. Powers down the analog block
in the serializer.
0x01
Power and Reset
3
2
1
ANAPWDN
RSVD
R/W
R/W
R/W
0
0
0
0: No effect
Reserved
1: Resets the digital block except for register values.
Does not affect device I2C bus or Device ID. This bit is
self-clearing.
DIGITAL
RESET1
0: Normal operation
1: Digital reset, resets the entire digital block including
all register values. This bit is self-clearing.
0: Normal operation.
DIGITAL
RESET0
0
R/W
0
0x02
Reserved
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表7-7. DS90UB933-Q1 Control Registers (continued)
Addr
(Hex)
Name
Bits Field
TYPE
Default
Description
Back-channel CRC checker enable
1: Enable
0: Disable
RX CRC Checker
Enable
7
6
R/W
1
Forward channel parity generator enable.
1: Enable
0: Disable
TX Parity
Generator Enable
R/W
R/W
1
0
Clear CRC error counters
This bit is NOT self-clearing.
1: Clear counters
5
4
CRC Error Reset
0: Normal operation
Automatically acknowledge I2C remote write
The mode works when the system is LOCKed.
1: Enable: When enabled, I2C writes to the
deserializer (or any remote I2C Slave, if I2C PASS
ALL is enabled) are immediately acknowledged
without waiting for the deserializer to acknowledge the
write. The accesses are then remapped to address
specified in 0x06.
I2C Remote Write
Auto Acknowledge
R/W
0
0: Disable
1: Enable Forward Control Channel pass-through of all
I2C accesses to I2C IDs that do not match the
serializer I2C ID. The I2C accesses are then
remapped to address specified in register 0x06.
0: Enable Forward Control Channel pass-through only
of I2C accesses to I2C IDs matching either the remote
deserializer ID or the remote I2C IDs.
General
Configuration
0x03
I2C Pass-Through
All
3
2
1
R/W
R/W
R/W
0
1
0
I2C Pass-through mode
1: Pass-through enabled. DES alias 0x07 and slave
alias 0x09
I2C Pass-Through
OV_CLK2PLL
0: Pass-through disabled
1:Enabled : When enabled this register overrides the
clock to PLL mode (External Oscillator mode or Direct
PCLK mode) defined through MODE pin and allows
selection through register 0x35 in the serializer.
0: Disabled : When disabled, Clock to PLL mode
(External Oscillator mode or Direct PCLK mode) is
defined through MODE pin on the Serializer.
Pixel clock edge select
1: Parallel interface data is strobed on the rising clock
0
TRFB
R/W
1
edge
0: Parallel interface data is strobed on the falling clock
edge
0x04
Reserved
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表7-7. DS90UB933-Q1 Control Registers (continued)
Addr
(Hex)
Name
Bits Field
TYPE
Default
Description
7
6
RSVD
RSVD
R/W
R/W
0
0
Reserved
Reserved
Allows overriding mode select bits coming from back-
channel.
1: Overrides MODE select bits
0: Does not override MODE select bits
MODE_
OVERRIDE
5
4
R/W
R
0
0
1: Status of mode select from deserializer is up-to-
date.
0: Status is NOT up-to-date.
MODE_UP_
TO_DATE
Pin_MODE_
12–bit mode
1: 12-bit mode is selected.
0: 12-bit mode is not selected.
3
2
R
R
0
0
Pin_MODE_
10–bit mode
1: 10-bit mode is selected.
0: 10-bit mode is not selected.
0x05
Mode Select
Selects 12 bit data-bus. This bit changes the Tx mode
settings if MODE_OVERRIDE is SET 0x05[5] = 1.
1: Enables 12 bit HF mode
1
0
TX_MODE_12b
TX_MODE_10b
R/W
R/W
0
0
0: Disables 12 bit HF mode
Note: This bit changes mode settings on TX. When
TX_MODE_12b is set TX_MODE_10b must be
cleared; 0x05[1:0] = 10.
Selects 10 bit data-bus. This bit changes the Tx mode
settings if MODE_OVERRIDE is SET 0x05[5] = 1.
1: Enables 10b mode
0: Disables 10b mode
Note: This bit changes mode settings on TX. When
TX_MODE_10b is set TX_MODE_12b must be
cleared; 0x05[1:0] = 01.
7-bit deserializer Device ID Configures the I2C Slave
ID of the remote deserializer. A value of 0 in this field
disables I2C access to the remote deserializer. This
field is automatically configured by the bidirectional
control channel once RX Lock has been detected.
Software may overwrite this value, but should also
assert the FREEZE DEVICE ID bit to prevent
Deserializer
Device ID
7:1
R/W
R/W
0x00
0x06
DES ID
overwriting by the bidirectional control channel.
1: Prevents auto-loading of the deserializer Device ID
by the bidirectional control channel. The ID is frozen at
the value written.
0
Freeze Device ID
0
0: Update
7-bit remote deserializer device alias ID Configures the
decoder for detecting transactions designated for an
I2C deserializer device. The transaction is remapped
to the address specified in the DES ID register.
A value of 0 in this field disables access to the remote
deserializer.
Deserializer ALIAS
ID
7:1
0
R/W
R/W
0x00
0
0x07
DES Alias
RSVD
Reserved
7-bit remote slave device ID Configures the physical
I2C address of the remote I2C slave device attached
to the remote deserializer. If an I2C transaction is
addressed to the slave alias ID, the transaction is
remapped to this address before passing the
transaction across the bidirectional control channel to
the deserializer and then to remote slave. A value of 0
in this field disables access to the remote I2C slave.
7:1 SLAVE ID
R/W
R/W
0x00
0x08
SlaveID
0
RSVD
0
Reserved
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表7-7. DS90UB933-Q1 Control Registers (continued)
Addr
(Hex)
Name
Bits Field
TYPE
Default
Description
7-bit remote slave device alias ID Configures the
decoder for detecting transactions designated for an
I2C slave device attached to the remote deserializer.
The transaction is remapped to the address specified
in the slave ID register. A value of 0 in this field
disables access to the remote I2C slave.
7:1 SLAVE ALIAS ID
R/W
0x00
0x09
Slave Alias
0
RSVD
R/W
R
0
Reserved
Number of back-channel CRC errors during normal
operation. Least significant byte.
0x0A
0x0B
CRC Errors
CRC Errors
7:0 CRC Error Byte 0
7:0 CRC Error Byte 1
7:5 Rev-ID
0x00
Number of back-channel CRC errors during normal
operation. Most significant byte
R
R
R
R
R
0x00
0x0
0
Revision ID
0x0: Production Revision ID
1: RX LOCKED
0: RX not LOCKED
4
3
2
RX Lock Detect
BIST CRC
Error Status
1: CRC errors in BIST mode
0: No CRC errors in BIST mode
0
1: Valid PCLK detected
0: Valid PCLK not detected
PCLK Detect
DES Error
0
1: CRC error is detected during communication with
deserializer.
This bit is cleared upon loss of link or assertion of CRC
ERROR RESET in register 0x03[5].
0: No effect
0x0C
General Status
1
0
R
R
0
0
1: Cable link detected
0: Cable link not detected
This includes any of the following faults:
—Cable open
LINK Detect
—'+' and '-' shorted
—Short to GND
—Short to battery
Local GPIO output value. This value is output on the
GPIO pin when the GPIO function is enabled. The
local GPIO direction is output, and remote GPIO
control is disabled.
GPO1 Output
Value
7
6
R/W
R/W
0
1
Remote GPIO Control
1: Enable GPIO control from remote deserializer. The
GPIO pin must be an output, and the value is received
from the remote Deserializer.
GPO1 Remote
Enable
0: Disable GPIO control from remote deserializer
5
4
RSVD
R/W
R/W
0
1
Reserved
1: GPIO enable
0: Tri-state
GPO1 Enable
GPO[0]
and GPO[1]
Configuration
0x0D
Local GPIO output value. This value is output on the
GPIO pin when the GPIO function is enabled. The
local GPIO direction is output, and remote GPIO
control is disabled.
GPO0 Output
Value
3
2
R/W
R/W
0
1
Remote GPIO Control
1: Enable GPIO control from remote deserializer. The
GPIO pin must be an output, and the value is received
from the remote Deserializer.
GPO0 Remote
Enable
0: Disable GPIO control from remote deserializer.
1
0
RSVD
R/W
R/W
0
1
Reserved
1: GPIO enable
0: Tri-state
GPO0 Enable
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表7-7. DS90UB933-Q1 Control Registers (continued)
Addr
(Hex)
Name
Bits Field
TYPE
Default
Description
Local GPIO output value. This value is output on the
GPIO pin when the GPIO function is enabled. The
local GPIO direction is output, and remote GPIO
control is disabled.
GPO3 Output
Value
7
6
R/W
0
Remote GPIO vontrol
1: Enable GPIO control from remote Deserializer. The
GPIO pin must be an output, and the value is received
from the remote deserializer.
GPO3 Remote
Enable
R/W
0
0: Disable GPIO control from remote Deserializer.
1: Input
0: Output
5
4
GPO3 Direction
GPO3 Enable
R/W
R/W
1
1
1: GPIO enable
0: Tri-state
GPO[2]
0x0E
and GPO[3]
Configuration
Local GPIO output value. This value is output on the
GPIO pin when the GPIO function is enabled. The
local GPIO direction is output, and remote GPIO
control is disabled.
GPO2 Output
Value
3
2
R/W
R/W
0
1
Remote GPIO Control
1: Enable GPIO control from remote deserializer. The
GPIO pin must be an output, and the value is received
from the remote deserializer.
GPO2 Remote
Enable
0: Disable GPIO control from remote deserializer.
1
0
RSVD
R/W
R/W
R
0
1
Reserved
1: GPIO enable
0: Tri-state
GPO2 Enable
7:5 RSVD
0x0
Reserved
SDA output delay This field configures output delay on
the SDA output. Setting this value increases output
delay in units of 50 ns. Nominal output delay values for
SCL to SDA are:
00: ~350 ns
01: ~400 ns
10: ~450 ns
11: ~500 ns
4:3 SDA Output Delay
R/W
00
Disable remote writes to local registers setting this bit
to a 1 prevents remote writes to local device registers
from across the control channel. This prevents writes
to the serializer registers from an I2C master attached
to the deserializer. setting this bit does not affect
remote access to I2C slaves at the serializer.
Local Write
Disable
2
R/W
R/W
0
0
I2C Master
Config
0x0F
Speed up I2C bus watchdog timer
1: Watchdog timer expires after approximately 50
microseconds.
0: Watchdog timer expires after approximately 1
second.
I2C Bus Timer
Speed up
1
1. Disable I2C bus watchdog timer when the I2C
watchdog timer may be used to detect when the I2C
bus is free or hung up following an invalid termination
of a transaction. If SDA is high and no signaling occurs
for approximately 1 second, the I2C bus is assumed to
be free. If SDA is low and no signaling occurs, the
device attempts to clear the bus by driving 9 clocks on
SCL.
I2C Bus Timer
Disable
0
R/W
0
0: No effect
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表7-7. DS90UB933-Q1 Control Registers (continued)
Addr
(Hex)
Name
Bits Field
RSVD
TYPE
Default
Description
7
R/W
0
Reserved
Internal SDA hold time. This field configures the
amount of internal hold time provided for the SDA
input relative to the SCL input. Units are 50 ns.
6:4 SDA Hold Time
3:0 I2C Filter Depth
R/W
R/W
0x1
0x7
0x10
I2C Control
I2C glitch filter depth. This field configures the
maximum width of glitch pulses on the SCL and SDA
inputs that will be rejected. Units are 10 ns.
I2C master SCL high time This field configures the
high pulse width of the SCL output when the serializer
is the master on the local I2C bus. Units are 50 ns for
the nominal oscillator clock frequency. The default
value is set to provide a minimum (4 µs + 1 µs of rise
time for cases where rise time is very fast) SCL high
time with the internal oscillator clock running at 26
MHz rather than the nominal 20 MHz.
0x11
SCL High Time
7:0 SCL High Time
R/W
0x82
I2C SCL low time This field configures the low pulse
width of the SCL output when the serializer is the
master on the local I2C bus. This value is also used as
the SDA setup time by the I2C slave for providing data
prior to releasing SCL during accesses over the
bidirectional control channel. Units are 50 ns for the
nominal oscillator clock frequency. The default value is
set to provide a minimum (4.7 µs + 0.3 µs of fall time
for cases where fall time is very fast) SCL low time
with the internal oscillator clock running at 26 MHz
rather than the nominal 20 MHz.
0x12
0x13
SCL LOW Time
7:0 SCL Low Time
R/W
R/W
0x82
0x00
General Purpose
Control
1: High
0: Low
7:0 GPCR[7:0]
7:5 RSVD
4:3 RSVD
R
0x0
0x0
Reserved
Reserved
R/W
Allows choosing different OSC clock frequencies for
forward channel frame.
OSC clock frequency in functional mode when OSC
mode is selected or when the selected clock source is
not present, for example, missing PCLK/ external
oscillator. See 表7-3 for oscillator clock frequencies
when PCLK/ external clock is missing.
0x14
BIST Control
2:1 Clock Source
R/W
R/W
0x0
0
RSVD
0
Reserved
0x15 -
0x1D
Reserved
The watchdog timer allows termination of a control
channel transaction if it fails to complete within a
programmed amount of time. This field sets the
bidirectional control channel watchdog timeout value in
units of 2 ms. This field should not be set to 0.
BCC Watchdog
Timer
7:1
0
R/W
R/W
0x7F
0
BCC Watchdog
Control
0x1E
BCC Watchdog
Timer Disable
1: Disables BCC watchdog timer operation
0: Enables BCC watchdog timer operation
0x1F -
0x26
Reserved
7:6
5
Reserved
Power Down PLL
Reserved
R
0
0
0
0
0
Reserved
1: Power down forward channel PLL
0: Normal operation
RW
RW
RW
RW
Analog Power
Down Control
0x27
4
Reserved
Power Down
NCLK
1: Power down NCLK
0: Normal operation
3
2:0
Reserved
Reserved
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表7-7. DS90UB933-Q1 Control Registers (continued)
Addr
(Hex)
Name
Bits Field
TYPE
Default
Description
0x28
Reserved
0x29
OSC Divider
7:6 RSVD
R/W
R/W
0x0
Reserved
Selects the OSC frequency to drive out on GPO2 in
external oscillator mode.
0: Divide by 2 (default)
5
OSC Divider
0
1: Divide by 4
4:0 RSVD
R/W
R
0x06
0x00
Reserved
BIST Mode CRC
Number of CRC errors in the back channel when in
BIST mode
0x2A
CRC Errors
7:0
Errors Count
0x2B -
0x2C
Reserved
1: Forces 1 (one) error over forward channel frame in
normal operating mode. Self-clearing bit.
0: No error
Force Forward
Channel Error
7
R/W
R/W
0
N: Forces N number of errors in BIST mode. This
register MUST be set BEFORE BIST mode is enabled.
BIST error count register on the deserializer must be
read AFTER BIST mode is disabled for the correct
number of errors incurred while in BIST mode.
0: No error
Inject Forward
Channel Error
0x2D
6:0
Force BIST Error
0x00
0x2E -
0x34
Reserved
7:4 RSVD
R/W
R
0x0
Reserved
Status of mode select pin
1: Indicates external oscillator mode is selected by
mode-resistor
0: External oscillator mode is not selected by mode-
resistor
PIN_LOCK to
3
0
External Oscillator
2
1
RSVD
R
0
0
Reserved
PLL Clock
Overwrite
0x35
LOCK to External
Oscillator
R/W
Affects only when 0x03[1] =1 (OV_CLK2PLL) and
0x35[0] = 0
1: Routes GPO3 directly to PLL
0: Allows PLL to lock to PCLK
R/W
1
Affects only when 0x03[1] = 1 (OV_CLK2PLL)
1: Allows internal OSC clock to feed into PLL
0: Allows PLL to lock to either PCLK or external clock
from GPO3
0
LOCK2OSC
(1) To ensure optimum device functionality, TI recommends to NOT write to any RESERVED registers.
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8 Application and Implementation
备注
以下应用部分的信息不属于TI 组件规范，TI 不担保其准确性和完整性。客户应负责确定 TI 组件是否适
用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The DS90UB933-Q1 was designed as a serializer to support automotive camera designs. Automotive cameras
are often located in remote positions such as bumpers or trunk lids, and a major component of the system cost is
the wiring. For this reason it is desirable to minimize the wiring to the camera. This chipset allows the video data,
along with a bidirectional control channel, and power to all be sent over a single coaxial cable. The chipset is
also able to transmit over STP and is pin-to-pin/backwards compatible with the DS90UB913A-Q1 and
DS90UB913Q-Q1.
8.1.1 Power Over Coax
See application report Sending Power Over Coax in DS90UB933 Designs for more details.
8.1.2 Power-Up Requirements and PDB Pin
Transition of the PDB pin from LOW to HIGH must occur after the VVDDIO and VVDD_n supplies have reached
their required operating voltage levels. Direct control of the PDB timing by processor GPIO is recommended if
possible. When direct control of PDB is not available, the PDB pin can be tied to the power supply rail with an
RC filter network to help ensure proper power up timing. GPO2 should be low when PDB goes high. Timing
constraints are noted in Suggested Power-Up Sequencing and Power-Up Sequencing Constraints. Please refer
to Power Down section for device operation when powered down.
If GPO2 state is not determined when PDB goes high, DS90UB933-Q1 registers must be programmed to
configure the transmission mode. Mode Select register 0x05[5] must be set to 1 and register 0x05 bit 1 and 0 are
to be selected based on desired 12-bit or 10-bit transmit data format.
Common applications tie the V(VDDIO) and V(VDD_n) supplies to the same power source of 1.8 V typically. This is
an acceptable method for ramping the V(VDDIO) and V(VDD_n) supplies. The main constraint here is that the
V(VDD_n) supply does not lead in ramping before the V(VDDIO) system supply. This is noted in Suggested Power-
Up Sequencing with the requirement of t1 ≥ 0. V(VDDIO) must reach the expected operating voltage earlier than
V(VDD_n) or at the same time.
t0
1.8 V or 3.3 V
VDDIO
GND
t2
1.8V
VDD_n
GND
t1
t3
t4
VDDIO
PDB
GND
Don‘t Care
GPO2
图8-1. Suggested Power-Up Sequencing
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表8-1. Power-Up Sequencing Constraints
SYMBOL
DESCRIPTION
TEST CONDITIONS
MIN
TYP
MAX Units
10% to 90% of nominal voltage on rising
edge. Monotonic signal ramp is required
t0
V(VDDIO) rise time
0.05
5
ms
ms
10% of rising edge (V(VDDIO)) to 10% of
t1
V(VDDIO) to V(VDD_n) delay
0
rising edge (V(VDD_n)
)
10% to 90% of nominal voltage on rising
edge. Monotonic signal ramp is required.
VPDB < 10% of V(VDDIO)
t2
V(VDD_n) rise time
0.05
5
ms
t3*
t4
V(VDD_n) to PDB VIH delay
PDB to GPO2 delay
90% rising edge (V(VDD_n)) to PDB VIH
PDB VIH to 10% of rising edge (GPO2)
0
16
ms
ms
1.3
* If timing constraint t3 cannot be assured, the following programming steps should be issued to the via local I2C
control (not via remote back channel). These programming steps should be completed > 10ms after the power
sequence is complete (VPDB > PDB VIH) with no delay between write commands. This step will cause a brief
restart of the forward channel output:
• Write Register 0x27 = 0x28
• Write Register 0x27 = 0x20
• Write Register 0x27 = 0x00
8.1.3 AC Coupling
The SER/DES supports only AC-coupled interconnects through an integrated DC-balanced decoding scheme.
External AC-coupling capacitors must be placed in series in the FPD-Link III signal path as shown in 图 8-2. For
applications utilizing single-ended 50-Ω coaxial cable, the unused data pin (DOUT–, RIN–) must utilize a
0.047-µF capacitor and must be terminated with a 50-Ω resistor. For high-speed FPD–Link III transmissions,
the smallest available package should be used for the AC-coupling capacitor. This helps minimize degradation of
signal quality due to package parasitics.
D
OUT
+
R
IN
+
SER
DES
R
IN
-
D
OUT
-
Copyright © 2016, Texas Instruments Incorporated
图8-2. AC-Coupled Connection (STP)
D
OUT
+
R
IN
+
SER
DES
R
IN
-
D
OUT
-
50Q
50Q
Copyright © 2016, Texas Instruments Incorporated
图8-3. AC-Coupled Connection (Coaxial)
8.1.4 Transmission Media
The DS90UB933/934/964 chipset is intended to be used in a point-to-point configuration through a shielded
coaxial cable. The serializer and deserializer provide internal termination to minimize impedance discontinuities.
The interconnect (cable and connectors) must have a differential impedance of 100 Ω, or a single-ended
impedance of 50 Ω. The maximum length of cable that can be used is dependent on the quality of the cable
(gauge, impedance), connector, board(discontinuities, power plane), the electrical environment (for example,
power stability, ground noise, input clock jitter, PCLK frequency, etc.). The resulting signal quality at the receiving
end of the transmission media may be assessed by monitoring the differential eye opening of the serial data
stream. A differential probe should be used to measure across the termination resistor at the CMLOUTP/N pins.
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Contact TI for a channel specification regarding cable loss parameters and further details on adaptive equalizer
loss compensation.
8.2 Typical Applications
8.2.1 Coax Application
VDDIO
DS90UB933-Q1
1.8 V
VDDT
VDDIO
C8
C3
C4
C9
C13
1.8 V
DIN0
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
VDDPLL
C5
C6
C10
C14
FB1
FB2
1.8 V
VDDCML
VDDD
C11
C7
C15
C12
1.8 V
LVCMOS
Parallel
Bus
DIN7
DIN8
DIN9
DIN10
DIN11
HS
C1
C2
Serial
FPD-Link III
Interface
1.8 V
VS
DOUT+
DOUT-
PCLK
RTERM
R1
1.8 V
VDDIO
MODE
PDB
R2
R3
10 kQ
ID[X]
R4
C18
NOTE:
GPO[0]
GPO[1]
GPO[2]
GPO[3]
C1 = 0.1 µF (50 WV)
C2 = 0.047 µF (50 WV)
C3:C7 = 0.01 µF
C8:C12 = 0.1 µF
C13, C14 = 4.7 µF
C15 = 22 µF
GPO
Control
Interface
RPD
C16 - C17 = >100 pF
C18 = 1 µF
RTERM = 50 Ω
RPU = 1 kΩ to 4.7 kΩ
RPD minimum =40 kΩ
R1, R2 (see MODE Setting Table)
R3, R4 (see ID[x] Setting Table)
FB1:FB4: Impedance = 1 kΩ (@ 100 MHz)
low DC resistance (<1 Ω)
VDDIO
RPU
RPU
C17
RES
I2C
Bus
SCL
DAP (GND)
FB3
Interface
SDA
FB4
Optional
C16
The "Optional" components shown are
provisions to provide higher system noise
immunity and will therefore result in higher
performance.
Optional
Copyright © 2016, Texas Instruments Incorporated
图8-4. Coax Application Connection Diagram
8.2.1.1 Design Requirements
For the typical coax design applications, use the following as input parameters:
表8-2. Coax Design Parameters
DESIGN PARAMETER
V(VDDIO)
EXAMPLE VALUE
1.8 V, 2.8 V, or 3.3 V
1.8 V
V(VDD_n)
AC-coupling capacitors for DOUT±
PCLK frequency
0.1 µF, 0.047 µF (For the unused data pin, DOUT–)
100 MHz (12-bit), 100 MHz (10-bit)
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8.2.1.2 Detailed Design Procedure
图8-5 shows the typical connection of a DS90UB933-Q1 serializer using a coax interface.
DS90UB933-Q1
Serializer
DS90UB934-Q1
Deserializer
FPD-Link III
Camera Data
10 or 12
Camera Data
10 or 12
DOUT+
DOUT-
RIN+
RIN-
ROUT[11:0]
or
ROUT[9:0]
HSYNC,
VSYNC
DIN[11:0] or
DIN[9:0]
HSYNC,
VSYNC
Image
Sensor
DATA
DATA
HSYNC
HSYNC
50Q
50Q
VSYNC
VSYNC
PCLK
PCLK
ECU Module
Pixel Clock
Pixel Clock
Bi-Directional
Control Channel
4
4
GPO[3:0]
GPIO[3:0]
GPO[3:0]
GPIO[3:0]
Microcontroller
SDA
SCL
SDA
SCL
SDA
SCL
SDA
SCL
Camera Unit
Copyright © 2016, Texas Instruments Incorporated
图8-5. Coax Application Block Diagram
8.2.1.3 Application Curves
Time (250 ps/DIV)
Time (250 ps/DIV)
图8-6. Coax Eye Diagram at 1.4-Gbps Line Rate
(100-MHz Pixel Clock, 10-bit Mode) from Serializer
Output (DOUT+)
图8-7. Coax Eye Diagram at 1.87-Gbps Line Rate
(100-MHz Pixel Clock, 12-bit Mode) from Serializer
Output (DOUT+)
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8.2.2 STP Application
VDDIO
DS90UB933-Q1
1.8 V
VDDT
VDDIO
C8
C3
C4
C9
C13
1.8 V
DIN0
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
VDDPLL
C5
C6
C10
C14
FB1
FB2
1.8 V
VDDCML
VDDD
C11
C7
C15
C12
1.8 V
LVCMOS
Parallel
Bus
DIN7
DIN8
DIN9
DIN10
DIN11
HS
C1
C2
Serial
FPD-Link III
Interface
1.8 V
VS
DOUT+
DOUT-
PCLK
R1
1.8 V
VDDIO
MODE
PDB
R2
R3
10 kQ
ID[X]
R4
C18
GPO[0]
GPO[1]
GPO[2]
GPO[3]
NOTE:
GPO
Control
Interface
C1, C2 = 0.1 µF (50 WV)
C3:C7 = 0.01 µF
C8:C12 = 0.1 µF
RPD
C13, C14 = 4.7 µF
C15 = 22 µF
C16 - C17 = >100 pF
C18 = 1 µF
RPU = 1 kΩ to 4.7 kΩ
RPD minimum =40 kΩ
R1, R2 (see MODE Setting Table)
R3, R4 (see ID[x] Setting Table)
FB1:FB4: Impedance = 1 kΩ (@ 100 MHz)
low DC resistance (<1 Ω)
VDDIO
RPU
RPU
C17
RES
I2C
Bus
SCL
DAP (GND)
FB3
Interface
SDA
FB4
Optional
The "Optional" components shown are
provisions to provide higher system noise
immunity and will therefore result in higher
performance.
C16
Optional
Copyright © 2016, Texas Instruments Incorporated
图8-8. STP Application Connection Diagram
8.2.2.1 Design Requirements
For the typical STP design applications, use the following as input parameters:
表8-3. STP Design Parameters
DESIGN PARAMETER
V(VDDIO)
EXAMPLE VALUE
1.8 V, 2.8 V, or 3.3 V
V(VDD_n)
1.8 V
0.1 µF
AC-coupling capacitors for DOUT±
PCLK frequency
100 MHz (12-bit), 100 MHz (10-bit)
8.2.2.2 Detailed Design Procedure
图8-9 shows a typical connection of a DS90UB933-Q1 Serializer using an STP interface.
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DS90UB933-Q1
Serializer
DS90UB934-Q1
Deserializer
Camera Data
FPD-Link III
Camera Data
10 or 12
DOUT+
DOUT-
10 or 12
RIN+
RIN-
ROUT[11:0]
or
ROUT[9:0]
DIN[11:0] or
DIN[9:0]
HSYNC,
VSYNC
Image
Sensor
DATA
DATA
HSYNC
HSYNC
HSYNC,
VSYNC
VSYNC
VSYNC
Bi-Directional
Control Channel
PCLK
PCLK
ECU Module
Pixel Clock
Pixel Clock
4
4
GPO[3:0]
GPIO[3:0]
GPO[3:0]
GPIO[3:0]
Microcontroller
SDA
SDA
SCL
SCL
SDA
SCL
SDA
SCL
Camera Unit
Copyright © 2016, Texas Instruments Incorporated
图8-9. STP Application Block Diagram
8.2.2.3
Eye diagrams in STP applications have roughly double the swing as with coax (图8-6 and 图8-7).
9 Power Supply Recommendations
This device is designed to operate from an input core voltage supply of 1.8 V. Some devices provide separate
power and ground terminals for different portions of the circuit. This is done to isolate switching noise effects
between different sections of the circuit. Separate planes on the PCB are typically not required. Pin description
tables typically provide guidance on which circuit blocks are connected to which power terminal pairs. In some
cases, an external filter may be used to provide clean power to sensitive circuits such as PLLs. The voltage
applied on V(VDDIO) (1.8 V, 2.8 V, 3.3 V) or other power supplies making up V(VDD_n) (1.8 V) must be at the input
pin - any board level DC drop must be compensated (that is, ferrite beads in the path of the power supply rails).
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10 Layout
10.1 Layout Guidelines
Design circuit board layout and stack-up for the serializer/deserializer devices to provide low-noise power feed to
the device. Good layout practice also separates high frequency or high-level inputs and outputs to minimize
unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved
by using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane
capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at
high frequencies, making the value and placement of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 µF to 0.1 µF. Tantalum capacitors may be in the 2.2-µF to 10-µF range. Voltage rating of the
tantalum capacitors should be at least 5× the power supply voltage being used.
TI recommends surface mount capacitors due to their smaller parasitics. When using multiple capacitors per
supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power
entry. This is typically in the 50-µF to 100-µF range and smooths low frequency switching noise. TI recommends
connecting power and ground pins directly to the power and ground planes with bypass capacitors connected to
the plane with via on both ends of the capacitor. Connecting power or ground pins to an external bypass
capacitor increases the inductance of the path.
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size
reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20 to 30 MHz. To provide effective bypassing, multiple
capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At
high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing
the impedance at high frequency.
Some devices provide separate power for different portions of the circuit. This is done to isolate switching noise
effects between different sections of the circuit. Separate planes on the PCB are typically not required. Pin
Description tables typically provide guidance on which circuit blocks are connected to which power pin pairs. In
some cases, an external filter many be used to provide clean power to sensitive circuits such as PLLs.
Use at least a four-layer board with a power and ground plane. Locate LVCMOS signals away from the
differential lines to prevent coupling from the LVCMOS lines to the differential lines. Closely-coupled differential
lines of 100 Ω are typically recommended for differential interconnect. The closely coupled lines help to ensure
that coupled noise appears as common-mode and thus is rejected by the receivers. The tightly coupled lines
also radiate less.
Information on the WQFN package is provided in AN-1187 Leadless Leadframe Package (LLP) (SNOA401).
10.1.1 Interconnect Guidelines
See Application Note 1108 Channel-Link PCB and Interconnect Design-In Guidelines (SNLA008) for full details.
• Use 100-Ωcoupled differential pairs
• Use the S/2S/3S rule in spacings
– –S = space between the pair
– –2S = space between pairs
– –3S = space to LVCMOS signal
• Minimize the number of Vias
• Use differential connectors when operating above 500-Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the
Texas Instrument web site at: www.ti.com/lvds.
Copyright © 2023 Texas Instruments Incorporated
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10.2 Layout Example
Stencil parameters such as aperture area ratio and the fabrication process have a significant impact on paste
deposition. Inspection of the stencil prior to placement of the WQFN package is highly recommended to improve
board assembly yields. If the via and aperture openings are not carefully monitored, the solder may flow
unevenly through the DAP. Stencil parameters for aperture opening and via locations are shown in the following:
图10-1. No Pullback WQFN, Single Row Reference Diagram
表10-1. No Pullback WQFN Stencil Aperture Summary for DS90UB933-Q1
GAP
BETWEEN
DAP
APERTURE
(Dim A mm)
STENCIL
DAP
APERTURE
(mm)
NUMBER OF
DAP
APERTURE
OPENINGS
PCB
PITCH
(mm)
STENCIL I/O
APERTURE
(mm)
PIN
COUNT
PCB I/O PAD
SIZE (mm)
PCB DAP
SIZE(mm)
DEVICE
MKT DWG
DS90UB933-Q1
32
RTV
0.25 × 0.6
0.5
3.1 × 3.1
0.25 × 0.7
1.4 × 1.4
4
0.2
AC-Coupling
Capacitor on
Top Layer
Buried FPD-Link III
High-speed Trace
on Signal Layer 1
图10-2. DS90UB933-Q1 Serializer DOUT+ Trace Layout
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Power-over-Coax
Network Placed
Close to Connector
Coax Connector
图10-3. DS90UB933-Q1 Power-over-Coax Layout
图 10-2 and 图 10-3 are derived from the layout design of the DS90UB933-Q1 evaluation module (EVM). The
EVM is designed for coax operation. The trace carrying high-speed serial signal DOUT+ is critical and must be
kept as short as possible. Burying this trace in an internal PCB layer may help reduce emissions. If Power-over-
Coax is used, the stub must be minimized by placing the filter network as close as possible to the coax
connector. These graphics and additional layout description are used to demonstrate both proper routing and
proper solder techniques when designing in this serializer.
Copyright © 2023 Texas Instruments Incorporated
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• I2C over DS90UB913/4 FPD-Link III with Bidirectional Control Channel (SNLA222)
• Sending Power Over Coax in DS90UB913A Designs (SNOA549)
• FPD-Link Learning Center
• Understanding the I2C Bus
• I2C Bus Pullup Resistor Calculation
• Soldering Specifications Application Report,
• IC Package Thermal Metrics Application Report,
• AN-1187 Leadless Leadframe Package (LLP) Application Report
• LVDS Owner's Manual
• An EMC/EMI System-Design and Testing Methodology for FPD-Link III SerDes
• Ten Tips for Successfully Designing with Automotive EMC/EMI Requirements
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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English Data Sheet: SNLS546
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS90UB933TRTVRQ1
DS90UB933TRTVTQ1
ACTIVE
ACTIVE
WQFN
WQFN
RTV
RTV
32
32
2500 RoHS & Green
250 RoHS & Green
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 105
-40 to 105
UB933Q
UB933Q
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS90UB933TRTVRQ1
DS90UB933TRTVTQ1
WQFN
WQFN
RTV
RTV
32
32
2500
250
330.0
178.0
12.4
12.4
5.3
5.3
5.3
5.3
1.3
1.3
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS90UB933TRTVRQ1
DS90UB933TRTVTQ1
WQFN
WQFN
RTV
RTV
32
32
2500
250
356.0
208.0
356.0
191.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
RTV0032A
WQFN - 0.8 mm max height
S
C
A
L
E
2
.
5
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.15
4.85
A
B
PIN 1 INDEX AREA
5.15
4.85
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
2X 3.5
SYMM
EXPOSED
THERMAL PAD
(0.1) TYP
9
16
8
17
SYMM
33
2X 3.5
3.1 0.1
28X 0.5
1
24
0.30
32X
0.18
32
25
PIN 1 ID
0.1
C A B
0.5
0.3
32X
0.05
4224386/B 04/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RTV0032A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(3.1)
SYMM
SEE SOLDER MASK
DETAIL
32
25
32X (0.6)
1
24
32X (0.24)
28X (0.5)
(3.1)
33
SYMM
(4.8)
(1.3)
8
17
(R0.05) TYP
(
0.2) TYP
VIA
9
16
(1.3)
(4.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224386/B 04/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RTV0032A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.775) TYP
25
32
32X (0.6)
1
32X (0.24)
28X (0.5)
24
(0.775) TYP
(4.8)
33
SYMM
(R0.05) TYP
4X (1.35)
17
8
9
16
4X (1.35)
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
EXPOSED PAD 33
76% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4224386/B 04/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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