DS90UH926Q-Q1 [TI]
具有 HDCP 的 5 - 85MHz 24 位彩色 FPD-Link III 解串器;
| 型号： | DS90UH926Q-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 HDCP 的 5 - 85MHz 24 位彩色 FPD-Link III 解串器 光电二极管 |
| 文件： | 总62页 (文件大小：1315K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Support &
Community
Reference
Design
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
DS90UH926Q-Q1
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
支持 HDCP 的 DS90UH926Q-Q1 720p 24 位彩色 FPD-Link III 解串器
1 特性
3 说明
1
•
符合 AEC-Q100 的汽车应用 标准
DS90UH926Q-Q1 解串器与 DS90UH925Q-Q1 串行
器配套使用，可针对汽车娱乐系统内的内容受保护数字
视频的安全分发提供一套解决方案。该芯片组可将并行
RGB 视频接口转换为单对高速串行化接口。数字视频
数据采用业界标准的 HDCP 复制保护方案加以保护。
FPD-Link III 串行总线方案支持通过单条差分链路实现
高速正向数据传输和低速反向通道通信的全双工控制。
通过单个差分对整合视频数据和控制可减小互连线尺寸
和重量，同时还消除了偏差问题并简化了系统设计。
–
器件温度等级 2 级：环境工作温度范围为
–40°C 至 +105°C
–
–
–
器件 HBM ESD 分类等级 3B
器件 CDM ESD 分类等级 C6
器件 MM ESD 分类等级 M3
•
•
具有片上密钥存储的集成型 HDCP 密码引擎
具有 I2C 兼容型串行控制总线的双向控制接口通道
接口
•
•
•
•
支持高清 (720p) 数字视频格式
DS90UH926Q-Q1 解串器具有一个 31 位并行
LVCMOS 输出接口，可针对 RGB、视频控制和音频数
据进行调整。器件会从高速串行数据流中提取出时钟。
LOCK 输出引脚会在传入数据流被锁定时提供链路状
态，而无需使用训练序列或特殊的 SYNC（同步）模
式，也不需要基准时钟。
支持 RGB888 + VS、HS、DE 和 I2S 音频
支持 5 至 85MHz 像素时钟 (PCLK)
通过 1.8V 或 3.3V 兼容 LVCMOS I/O 接口实现
3.3V 单电源运行
•
•
•
•
•
•
•
长达 10 米的交流耦合屏蔽双绞线 (STP) 互连
并行 LVCMOS 视频输出
具有嵌入式时钟的直流平衡和扰频数据
自适应电缆均衡
自适应均衡器优化了最大电缆长度。输出扩频时钟发生
器 (SSCG) 和增强型渐进接通 (EPTO) 功能大大降低
了电磁干扰 (EMI) 特性的反馈。
支持 HDCP 中继器应用
图像增强（白平衡和抖动）和内部模式生成
串化器和解串器上都执行 HDCP 密钥引擎。HDCP 密
钥被存储在片载存储器中。
EMI 最小化（展频时钟生成 (SSCG) 和增强型累进
接通 (EPTO)）
器件信息(1)
•
•
低功率模式大大减少了功率耗散
向后兼容模式
器件型号
封装
WQFN (60)
封装尺寸（标称值）
DS90UH926Q-Q1
9.00mm x 9.00mm
2 应用范围
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
•
•
汽车导航显示屏
后座娱乐系统
应用图表
V
DD33
V
DDIO
V
DDIO
V
DD33
(1.8V or3.3V) (3.3V)
(3.3V) (1.8V or3.3V)
R[7:0]
G[7:0]
R[7:0]
G[7:0]
FPD-Link III
1 Pair /AC Coupled
B[7:0]
B[7:0]
0.1 mF
0.1 mF
0.1 mF
0.1 mF
HOST
Graphics
Processor
RGB Display
720p
24-bit color depth
HS
HS
DOUT+
DOUT-
RIN+
RIN-
VS
DE
PCLK
VS
DE
PCLK
100 ohm STP Cable
DS90UH925Q
Serializer
DS90UH926Q
Deserializer
LOCK
PASS
PDB
PDB
OSS_SEL
OEN
MODE_SEL
3
/
I2S AUDIO
(STEREO)
3
/
I2S AUDIO
(STEREO)
MODE_SEL
INTB
INTB_IN
MCLK
SCL
SDA
IDx
SCL
SDA
IDx
DAP
DAP
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SNLS337
DS90UH926Q-Q1
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
www.ti.com.cn
目录
7.3 Feature Description................................................. 16
7.4 Device Functional Modes........................................ 28
7.5 Programming........................................................... 32
7.6 Register Maps......................................................... 33
Application and Implementation ........................ 47
8.1 Application Information............................................ 47
8.2 Typical Application .................................................. 47
Power Supply Recommendations...................... 50
9.1 Power-Up Requirements and PDB Pin................... 50
1
2
3
4
5
6
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 4
Specifications......................................................... 7
6.1 Absolute Maximum Ratings ..................................... 7
6.2 ESD Ratings.............................................................. 7
6.3 Recommended Operating Conditions....................... 7
6.4 Thermal Information.................................................. 8
6.5 DC Electrical Characteristics .................................... 8
6.6 AC Electrical Characteristics................................... 10
6.7 DC and AC Serial Control Bus Characteristics....... 10
8
9
10 Layout................................................................... 51
10.1 Layout Guidelines ................................................. 51
10.2 Layout Examples................................................... 53
11 器件和文档支持 ..................................................... 54
11.1 文档支持................................................................ 54
11.2 接收文档更新通知 ................................................. 54
11.3 社区资源................................................................ 54
11.4 商标....................................................................... 54
11.5 静电放电警告......................................................... 54
11.6 Glossary................................................................ 54
12 机械、封装和可订购信息....................................... 54
6.8 Recommended Timing Requirements for the Serial
Control Bus .............................................................. 11
6.9 Switching Characteristics........................................ 11
6.10 Timing Diagrams................................................... 12
6.11 Typical Characteristics.......................................... 15
Detailed Description ............................................ 16
7.1 Overview ................................................................. 16
7.2 Functional Block Diagram ....................................... 16
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision L (February 2017) to Revision M
Page
•
•
将修订版 L 中以前所做的所有 MLCK 内容更改恢复为修订版 K............................................................................................. 1
Removed disable jitter cleaner note ....................................................................................................................................... 5
Changes from Revision K (January 2015) to Revision L
Page
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Changed top view pin out diagram ........................................................................................................................................ 4
Changed CLK to RES2 .......................................................................................................................................................... 5
Added note to disable jitter cleaner ....................................................................................................................................... 5
Changed MCLK to RES2 ....................................................................................................................................................... 5
Deleted reference to MCLK in this section ............................................................................................................................ 8
Deleted reference to MCLK in this section .......................................................................................................................... 11
Deleted reference to MCLK ................................................................................................................................................. 25
Deleted I2S Jitter Cleaning section ..................................................................................................................................... 25
Deleted MCLK section ......................................................................................................................................................... 25
Deleted MCLK columns in the Audio Interface Frequencies table....................................................................................... 26
Changed values in columns 2 to 5 of Configuration Select (MODE_SEL) table.................................................................. 29
Changed values in columns 2 to 5 of IDx table ................................................................................................................... 32
Changed Removed register reference to MCLK .................................................................................................................. 42
Changed Typical Display System Diagram (removed MCLK) ............................................................................................. 47
Changed Power-Up Requirements and PDB pin description and added Power-Up Sequence graphic. ........................... 50
2
版权 © 2010–2017, Texas Instruments Incorporated
DS90UH926Q-Q1
www.ti.com.cn
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
Changes from Revision J (April 2013) to Revision K
Page
•
已添加 引脚配置和功能 部分、ESD 额定值 表、特性 说明 部分、器件功能模式、应用和实施 部分、电源相关建议 部
分、布局 部分、器件和文档支持 部分以及机械、封装和可订购信息 部分 ............................................................................. 1
Changes from Revision I (August 2012) to Revision J
Page
•
将美国国家半导体产品说明书的布局更改为 TI 格式............................................................................................................... 1
Changes from Revision H (March 2012) to Revision I
Page
•
：配置选择 (MODE_SEL) #6 I2S 通道 B（18 位模式）从 L 到 H，将“直流和交流串行控制总线特征”表中的拼写错误
从 VDDIO 纠正为 VDD33，添加了“推荐 FRC 设置表”，在“功能说明”部分下添加了“当向后兼容模式 = ON 时，
LFMODE 设置 = 0”。重新设置了表格 9 的格式，并添加了澄清说明。在“功能说明、降低 EMI 特性、扩频时钟发生器
(SSCG)”部分下添加了“有关串行控制总线寄存器，地址 0x02[3:0]（向后兼容和 LFMODE 寄存器）的澄清说明”，添
加了 “注意：如果进入 SER 的 PCLK 源 已经有一个 SSC 时钟，请勿启用 SSCG 功能。”................................................... 1
Changes from Revision G (February 2012) to Revision H
Page
•
删除了“直流电气特性”下的 PDB VDDIO = 1.71 至 1.89V，在“电源电流”下添加了 IDDZ、DDIOZ、IDDIOZ 最大值 =
10mA”，在“CML 显示器驱动程序输出交流规范”下，添加了 EW 最小值 = 0.3 UI 和 EH 最小值 = 200mV，在“功能说
明”部分添加了“中断引脚 — 功能 说明 及使用 (INTB)” ， 更新了“功能说明” 部分下的 “断电 (PDB) 说明” 将 VDDIO 更
新为 VDDIO = 3 至 3.6V 或 VDD33”，更新了图 24 ................................................................................................................. 1
Copyright © 2010–2017, Texas Instruments Incorporated
3
DS90UH926Q-Q1
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
www.ti.com.cn
5 Pin Configuration and Functions
NKB Package
60 Pin WQFN With Exposed Thermal Pad
Top View
OSS_SEL
RES0
46
47
48
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
I2S_WC/GPO_REG7
VDD33_B
VDD33_A
G0/GPIO2
RIN+
RIN-
G1/GPIO3
49
50
51
52
53
54
55
56
57
58
59
60
G2
G3
CMF
CMLOUTP
CMLOUTN
NC
VDDIO
DS90UH926Q-Q1
TOP VIEW
G4
G5
DAP = GND
CAPR12
IDx
G6
G7
CAPP12
CAPI2S
PDB
B0/GPO_REG4
B1/I2S_DB/GPO_REG5
B2
MCLK
BISTC/INTB_IN
Pin Functions
PIN
I/O, TYPE
DESCRIPTION
NAME
NO.
LVCMOS PARALLEL INTERFACE
RED Parallel Interface Data Output Pins
Leave open if unused
R0 can optionally be used as GPIO0 and R1 can optionally be used as GPIO1
33, 34, 35, 36, O, LVCMOS
37, 39, 40, 41 with pulldown
R[7:0]
G[7:0]
GREEN Parallel Interface Data Output Pins
Leave open if unused
G0 can optionally be used as GPIO2 and G1 can optionally be used as GPIO3.
20, 21, 22, 23, O, LVCMOS
25, 26, 27, 28 with pulldown
BLUE Parallel Interface Data Output Pins
9, 10, 11, 12,
O, LVCMOS Leave open if unused
B[7:0]
HS
14, 17, 18, 19 with pulldown B0 can optionally be used as GPO_REG4 and B1 can optionally be used as I2S_DB or
GPO_REG5.
Horizontal Sync Output Pin
Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the
O, LVCMOS
with pulldown
8
Control Signal Filter is enabled. There is no restriction on the minimum transition pulse
when the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130
PCLKs. See Table 11
4
Copyright © 2010–2017, Texas Instruments Incorporated
DS90UH926Q-Q1
www.ti.com.cn
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
Pin Functions (continued)
PIN
I/O, TYPE
DESCRIPTION
NAME
NO.
Vertical Sync Output Pin
Video control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse
width is 130 PCLKs.
O, LVCMOS
with pulldown
VS
DE
7
Data Enable Output Pin
Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the
Control Signal Filter is enabled. There is no restriction on the minimum transition pulse
when the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130
PCLKs. See Table 11
O, LVCMOS
with pulldown
6
O, LVCMOS
with pulldown
PCLK
5
1, 30, 45
60
Pixel Clock Output Pin. Strobe edge set by RFB configuration register. See Table 11
Digital Audio Interface Data Output Pins
I2S_CLK,
I2S_WC,
I2S_DA
O, LVCMOS Leave open if unused
with pulldown I2S_CLK can optionally be used as GPO_REG8, I2S_WC can optionally be used as
GPO_REG7, and I2S_DA can optionally be used as GPO_REG6.
O, LVCMOS I2S Master Clock Output
with pulldown x1, x2, or x4 of I2S_CLK Frequency
MCLK
OPTIONAL PARALLEL INTERFACE
Second Channel Digital Audio Interface Data Output pin at 18–bit color mode and set by
O, LVCMOS MODE_SEL or configuration register
with pulldown Leave open if unused
I2S_B can optionally be used as BI or GPO_REG5.
I2S_DB
18
Standard General Purpose IOs.
Available only in 18-bit color mode, and set by MODE_SEL or configuration register.
See Table 11
Leave open if unused
Shared with G1, G0, R1 and R0.
I/O, LVCMOS
with pulldown
GPIO[3:0]
27, 28, 40, 41
GPO_REG[8: 1, 30, 45, 18,
O, LVCMOS General Purpose Outputs and set by configuration register. See Table 11
with pulldown Shared with I2S_CLK, I2S_WC, I2S_DA, I2S_DB or B1, B0.
4]
19
Input,
Interrupt Input
INTB_IN
CONTROL
16
LVCMOS
with pulldown
Shared with BISTC
Power-down Mode Input Pin
PDB = H, device is enabled (normal operation)
I, LVCMOS Refer to Power Supply Recommendations.
with pulldown PDB = L, device is powered down.
PDB
OEN
59
31
When the device is in the POWER DOWN state, the LVCMOS Outputs are in TRI-STATE,
the PLL is shutdown and IDD is minimized.
Input,
LVCMOS
Output Enable Pin.
See Table 8
with pulldown
Input,
LVCMOS
Output Sleep State Select Pin.
See Table 8
OSS_SEL
MODE_SEL
BISTEN
46
15
44
with pulldown
I, Analog
Device Configuration Select. See Table 9
BIST Enable Pin.
0: BIST Mode is disabled.
1: BIST Mode is enabled.
I, LVCMOS
with pulldown
BIST Clock Select.
Shared with INTB_IN
0: PCLK; 1: 33 MHz
I, LVCMOS
with pulldown
BISTC
16
Copyright © 2010–2017, Texas Instruments Incorporated
5
DS90UH926Q-Q1
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
www.ti.com.cn
Pin Functions (continued)
PIN
I/O, TYPE
DESCRIPTION
NAME
NO.
I2C
I2C Serial Control Bus Device ID Address Select
External pull-up to VDD33 is required under all conditions, DO NOT FLOAT.
Connect to external pullup and pulldown resistor to create a voltage divider.
See Figure 23
IDx
56
I, Analog
I2C Clock Input / Output Interface
Must have an external pullup to VDD33, DO NOT FLOAT.
Recommended pullup: 4.7 kΩ.
I/O, LVCMOS
Open-Drain
SCL
3
2
I2C Data Input / Output Interface
Must have an external pullup to VDD33, DO NOT FLOAT.
Recommended pullup: 4.7 kΩ.
I/O, LVCMOS
Open-Drain
SDA
STATUS
LOCK Status Output Pin
O, LVCMOS 0: PLL is unlocked, RGB[7:0], I2S[2:0], HS, VS, DE and PCLK output states are controlled
with pulldown by OEN. May be used as Link Status or Display Enable
1: PLL is Locked, outputs are active
LOCK
PASS
32
42
PASS Output Pin
O, LVCMOS 0: One or more errors were detected in the received payload
with pulldown 1: ERROR FREE Transmission
Leave Open if unused. Route to test point (pad) recommended
FPD-LINK III SERIAL INTERFACE
True Input.
RIN+
49
50
52
I, LVDS
I, LVDS
O, LVDS
The interconnection should be AC-coupled to this pin with a 0.1 μF capacitor.
Inverting Input.
RIN–
The interconnection should be AC-coupled to this pin with a 0.1 μF capacitor.
True CML Output
Monitor point for equalized differential signal
CMLOUTP
Inverting CML Output
Monitor point for equalized differential signal
CMLOUTN
CMF
53
51
O, LVDS
Analog
Common Mode Filter. Connect 0.1-μF capacitor to GND.
POWER(1) AND GROUND
VDD33_A,
48, 29
Power
Power
Ground
Power to on-chip regulator 3 V – 3.6 V. Requires 4.7 uF to GND at each VDD pin.
VDD33_B
LVCMOS I/O Power 1.8 V ±5% OR 3 V – 3.6 V. Requires 4.7 uF to GND at each VDDIO
pin.
VDDIO
GND
13, 24, 38
DAP
DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connect to the ground plane (GND) with at least 9 vias.
REGULATOR CAPACITOR
CAPR12
CAPP12
CAPI2S
55
57
58
Decoupling capacitor connection for on-chip regulator. Requires a 4.7-µF to GND at each
CAP pin.
CAP
CAP
Decoupling capacitor connection for on-chip regulator. Requires two 4.7-µF to GND at this
CAP pin.
CAPL12
4
OTHERS
NC
54
NC
No connect. This pin may be left open or tied to any level.
Reserved - tie to Ground
RES[1:0]
43.47
GND
(1) The VDD (VDD33 and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise.
6
Copyright © 2010–2017, Texas Instruments Incorporated
DS90UH926Q-Q1
www.ti.com.cn
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
6 Specifications
6.1 Absolute Maximum Ratings
(1)(2)(3)
See
MIN
−0.3
−0.3
−0.3
−0.3
MAX
UNIT
V
Supply voltage – VDD33
Supply voltage – VDDIO
LVCMOS I/O voltage
Deserializer input voltage
Junction temperature
4
4
(VDDIO + 0.3)
2.75
V
V
V
150
°C
60-pin WQFN Package
Maximum power dissipation
capacity at 25°C
Derate above 25 °C
1/ RθJA
31
°C/W
°C/W
°C/W
°C
RθJA
RθJC
2.4
Storage temperature, Tstg
−65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) For soldering specifications, see product folder at www.ti.com and Absolute Maximum Ratings for Soldering (SNOA549).
6.2 ESD Ratings
VALUE
±8000
±1250
±250
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
Machine model, all pins
Air Discharge (Pin 49 and 50)
±15000
±8000
±15000
±8000
±15000
±8000
(IEC, powered-up only)
RD = 330 Ω, CS = 150 pF
Electrostatic
discharge
V(ESD)
Contact Discharge (Pin 49 and 50)
Air Discharge (Pin 49 and 50)
V
(ISO10605)
RD = 330 Ω, CS = 150 pF
Contact Discharge (Pin 49 and 50)
Air Discharge (Pin 49 and 50)
(ISO10605)
RD = 2 kΩ, CS = 150 & 330 pF
Contact Discharge (Pin 49 and 50)
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
3
NOM
3.3
3.3
1.8
25
MAX UNIT
Supply voltage (VDD33
)
3.6
3.6
V
V
LVCMOS supply voltage (VDDIO
)
Connect VDDIO to 3.3 V and use 3.3-V IOs
Connect VDDIO to 1.8 V and use 1.8-V IOs
3
1.71
−40
5
1.89
105
85
V
Operating free air temperature (TA)
PCLK frequency
°C
MHz
Supply noise(1)
100 mVP-P
(1) Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC-coupled to the VDD33 and VDDIO supplies
with amplitude = 100 mVp-p measured at the device VDD33 and VDDIO pins. Bit error rate testing of input to the Ser and output of the
Des with 10-meter cable shows no error when the noise frequency on the Ser is less than 50 MHz. The Des on the other hand shows
no error when the noise frequency is less than 50 MHz.
Copyright © 2010–2017, Texas Instruments Incorporated
7
DS90UH926Q-Q1
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
www.ti.com.cn
6.4 Thermal Information
DS90UH926Q-Q1
THERMAL METRIC(1)
NKB (WQFN)
UNIT
60 PINS
26.2
8.1
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
5.2
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.1
ψJB
5.2
RθJC(bot)
1.1
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
6.5 DC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)
PARAMETER
LVCMOS I/O DC SPECIFICATIONS
High Level Input
TEST CONDITIONS
PIN/FREQ.
MIN
TYP
MAX UNIT
VIH
VDDIO = 3 to 3.6 V
2
VDDIO
0.8
V
V
Voltage
Low Level Input
Voltage
PDB
VIL
IIN
VDDIO = 3 to 3.6 V
GND
Input Current
VIN = 0 V or VDDIO = 3 to 3.6 V
VDDIO = 3 to 3.6 V
−10
±1
10
μA
2
VDDIO
V
High Level Input
Voltage
VIH
0.65 ×
VDDIO
VDDIO = 1.71 to 1.89 V
VDDIO = 3 to 3.6 V
VDDIO
V
V
V
GND
0.8
Low Level Input
Voltage
OEN, OSS_SEL,
BISTEN, BISTC /
INTB_IN, GPIO[3:0]
VIL
0.35 ×
VDDIO
VDDIO = 1.71 to 1.89 V
GND
VDDIO = 3
to 3.6 V
−10
±1
±1
10
μA
IIN
Input Current
VIN = 0 V or VDDIO
VDDIO = 1.7
to 1.89 V
−10
10
VDDIO
VDDIO
0.4
μA
V
VDDIO = 3 to 3.6 V
2.4
High Level Output
Voltage
VOH
IOH = −4 mA
VDDIO = 1.7
to 1.89 V
VDDIO-
0.45
V
R[7:0], G[7:0], B[7:0],
HS, VS, DE, PCLK,
LOCK, PASS, MCLK,
I2S_CLK, I2S_WC,
I2S_DA, I2S_DB,
GPO_REG[8:4]
VDDIO = 3 to 3.6 V
GND
V
Low Level Output
Voltage
VOL
IOL = 4 mA
VOUT = 0 V
VDDIO = 1.7
to 1.89 V
GND
0.35
V
Output Short-Circuit
Current
IOS
IOZ
−60
mA
Tri-state Output Current VOUT = 0 V or VDDIO, PDB = L
−10
10
μA
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the electrical characteristics conditions and/or notes. Typical specifications are estimations only and
are not ensured.
(2) Typical values represent most likely parametric norms at VDD = 3.3 V, TA = 25 °C, and at Recommended Operating Conditions at the
time of product characterization and are not ensured.
(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD and ΔVOD, which are differential voltages.
8
Copyright © 2010–2017, Texas Instruments Incorporated
DS90UH926Q-Q1
www.ti.com.cn
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
DC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)
PARAMETER
TEST CONDITIONS
PIN/FREQ.
MIN
TYP
MAX UNIT
FPD-LINK III CML RECEIVER INPUT DC SPECIFICATIONS
Differential Threshold
VTH
50
mV
mV
V
High Voltage
VCM = 2.5 V
(Internal VBIAS
)
Differential Threshold
Low Voltage
VTL
VCM
RT
−50
RIN+, RIN–
Differential Common-
mode Voltage
1.8
Internal Termination
Resistor - Differential
80
100
120
Ω
CML MONITOR DRIVER OUTPUT DC SPECIFICATIONS
Differential Output
Voltage
CMLOUTP,
CMLOUTN
VODp-p
RL = 100 Ω
360
mVp-p
SUPPLY CURRENT
IDD1
VDD33= 3.6 V
VDD33
VDDIO
VDD33
VDDIO
VDD33
VDDIO
VDD33
VDDIO
125
110
60
145
118
75
145
85
65
115
5
mA
mA
mA
mA
mA
mA
mA
mA
Supply Current
(includes load current)
f = 85 MHz
CL = 12 pF,
Checker Board Pattern VDDIO= 3.6 V
IDDIO1
IDD2
IDDIO2
IDDS
IDDIOS
IDDZ
Figure 1
VDDIO = 1.89 V
VDD33 = 3.6 V
CL = 4 pF
Checker Board Pattern, VDDIO = 3.6 V
125
75
Supply Current
(includes load current)
f = 85 MHz
Figure 1
VDDIO = 1.89 V
50
VDD33 = 3.6 V
Without Input Serial
VDDIO = 3.6 V
Stream
90
Supply Current Sleep
Mode
3
VDDIO = 1.89 V
2
3
VDD33 = 3.6 V
2
10
10
10
PDB = L, All LVCMOS
inputs are floating or
tied to GND
Supply Current Power
Down
VDDIO = 3.6 V
VDDIO = 1.89 V
0.05
0.05
IDDIOZ
Copyright © 2010–2017, Texas Instruments Incorporated
9
DS90UH926Q-Q1
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
www.ti.com.cn
MAX UNIT
6.6 AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)
PARAMETER
GPIO BIT RATE
TEST CONDITIONS
PIN/FREQ.
MIN
TYP
Forward Channel Bit Rate
Back Channel Bit Rate
f = 5 – 85
MHz,
GPIO[3:0]
0.25 × f
> 75
Mbps
kbps
BR
See(4) (5)
> 50
CML MONITOR DRIVER OUTPUT AC SPECIFICATIONS
Differential Output Eye Opening
Width(6)
RL = 100 Ω,
CMLOUTP,
CMLOUTN,
f = 85 MHz
EW
0.3
0.4
UI
Jitter Freq > f / 40
(4)(5)
Figure 2
EH
Differential Output Eye Height
200
300
mV
BIST MODE
tPASS BIST PASS Valid Time
BISTEN = H
800
ns
PASS
(4)(5)
Figure 8
SSCG MODE
Spread Spectrum Clocking
Deviation Frequency
±0.5%
8
±2.5%
fDEV
SeeFigure 14, Table 1 and
Table 2
f = 85 MHz,
SSCG = ON
(4)(5)
Spread Spectrum Clocking
Modulation Frequency
100
kHz
fMOD
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the electrical characteristics conditions and/or notes. Typical specifications are estimations only and
are not ensured.
(2) Typical values represent most likely parametric norms at VDD = 3.3 V, TA = 25 °C, and at Recommended Operating Conditions at the
time of product characterization and are not ensured.
(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD and ΔVOD, which are differential voltages.
(4) Specification is ensured by characterization and is not tested in production.
(5) Specification is ensured by design and is not tested in production.
(6) UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1 / 35 × PCLK). The UI scales with PCLK frequency.
6.7 DC and AC Serial Control Bus Characteristics
Over 3.3-V supply and temperature ranges unless otherwise specified.(1)
(2) (3)
PARAMETER
Input High Level
TEST CONDITIONS
SDA and SCL
MIN
0.7 × VDD33
GND
TYP
MAX UNIT
VIH
VIL
VHY
VOL
IIN
VDD33
V
V
Input Low Level Voltage
Input Hysteresis
SDA and SCL
0.3 × VDD33
> 50
mV
V
SDA, IOL = 1.25 mA
0
0.36
10
SDA or SCL, VIN = VDD33 or GND
–10
µA
ns
ns
ns
ns
ns
pF
tR
SDA Rise Time – READ
SDA Fall Time – READ
430
20
SDA, RPU = 10 kΩ, Cb ≤ 400 pF, Figure 9
tF
tSU;DAT Setup Time — READ
tHD;DAT Holdup Time — READ
SeeFigure 9
SeeFigure 9
560
615
50
tSP
Input Filter
CIN
Input Capacitance
SDA or SCL
<5
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the electrical characteristics conditions and/or notes. Typical specifications are estimations only and
are not ensured.
(2) Typical values represent most likely parametric norms at VDD = 3.3 V, TA = 25 °C, and at Recommended Operating Conditions at the
time of product characterization and are not ensured.
(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD and ΔVOD, which are differential voltages.
10
Copyright © 2010–2017, Texas Instruments Incorporated
DS90UH926Q-Q1
www.ti.com.cn
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
6.8 Recommended Timing Requirements for the Serial Control Bus
Over 3.3-V supply and temperature ranges unless otherwise specified.
MIN
0
NOM
MAX UNIT
fSCL
Standard Mode
Fast Mode
100
400
kHz
kHz
µs
SCL Clock Frequency
SCL Low Period
0
tLOW
Standard Mode
Fast Mode
4.7
1.3
4
µs
tHIGH
Standard Mode
Fast Mode
µs
SCL High Period
0.6
4
µs
tHD;STA
Hold time for a start or a
repeated start condition
Figure 9
Standard Mode
µs
Fast Mode
0.6
4.7
0.6
µs
µs
µs
tSU:STA
Setup time for a start or a
repeated start condition
Figure 9
Standard Mode
Fast Mode
tHD;DAT
tSU;DAT
tSU;STO
tBUF
Standard Mode
Fast Mode
0
0
3.45
0.9
µs
µs
ns
ns
µs
µs
µs
Data Hold Time
Figure 9
Standard Mode
Fast Mode
250
100
4
Data Setup Time
Figure 9
Standard Mode
Fast Mode
Setup Time for STOP
Condition, Figure 9
0.6
4.7
Bus Free Time
Standard Mode
Between STOP and START,
Figure 9
Fast Mode
1.3
µs
tr
tf
Standard Mode
Fast Mode
1000
300
300
300
ns
ns
ns
ns
SCL and SDA Rise Time,
Figure 9
Standard Mode
Fast mode
SCL and SDA Fall Time,
Figure 9
6.9 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tRCP = tTCP
PIN/FREQ.
PCLK
MIN
TYP
MAX UNIT
tRCP
tRDC
PCLK Output Period
PCLK Output Duty Cycle
11.76
45%
T
200
ns
50%
55%
VDDIO = 1.71 to 1.89 V,
CL = 12 pF
2
2
2
2
3
3
3
3
ns
ns
ns
ns
ns
ns
ns
ns
LVCMOS Low-to-High Transition
Time
Figure 3
tCLH
tCHL
tROS
tROH
VDDIO = 3 to 3.6 V,
CL = 12 pF
VDDIO = 1.71 to 1.89 V,
CL = 12 pF
R[7:0], G[7:0],
B[7:0], HS,
VS, DE,
PCLK, LOCK,
PASS, MCLK,
I2S_CLK,
I2S_WC,
I2S_DA,
I2S_DB
LVCMOS High-to-Low Transition
Time
Figure 3
VDDIO = 3 to 3.6 V,
CL = 12 pF
VDDIO = 1.71 to 1.89 V,
CL = 12 pF
Data Valid before PCLK – Setup
Time
SSCG = OFF
Figure 6
2.2
2.2
3
VDDIO = 3 to 3.6 V,
CL = 12 pF
VDDIO = 1.71 to 1.89 V,
CL = 12 pF
Data Valid after PCLK – Hold
Time
SSCG = OFF
Figure 6
VDDIO = 3 to 3.6 V,
CL = 12 pF
3
Copyright © 2010–2017, Texas Instruments Incorporated
11
DS90UH926Q-Q1
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
www.ti.com.cn
Switching Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
PIN/FREQ.
MIN
TYP
MAX UNIT
R[7:0], G[7:0],
B[7:0]
10
ns
HS, VS, DE,
PCLK, LOCK,
PASS
15
60
ns
ns
Active to OFF Delay
tXZR
OEN = L, OSS_SEL = H
Figure 5(1)(2)
MCLK,I2S_CL
K, I2S_WC,
I2S_DA,
I2S_DB
Lock Time
tDDLT
tDD
SSCG = OFF
SSCG = OFF
f = 5 – 85 MHz
f = 5 – 85 MHz
5
147 × T
0.5
40
ms
ns
ns
Figure 5(1)(2)(3)
Delay – Latency(1)(2)
f = 5 to <15
MHz
f = 15 to 85
MHz
tDCCJ
Cycle-to-Cycle Jitter(1)(2)
0.2
±2
50
50
50
50
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
I2S_CLK = 1
to 12.28 MHz
VDDIO = 1.71 to 1.89 V,
CL = 12 pF
Data Valid After OEN = H
SetupTime
tONS
tONH
tSES
tSEH
Figure 7(1)(2)
VDDIO = 3 to 3.6 V,
CL = 12 pF
VDDIO = 1.71 to 1.89 V,
CL = 12 pF
R[7:0], G[7:0],
B[7:0], HS,
VS, DE,
Data Tri-State After OEN = L
SetupTime
(1) (2)
VDDIO = 3 to 3.6 V,
CL = 12 pF
Figure 7
PCLK,
MCLK,I2S_CL
K, I2S_WC,
I2S_DA,
VDDIO = 1.71 to 1.89 V,
CL = 12 pF
Data Tri-State after OSS_ SEL =
H, Setup Time
(1) (2)
VDDIO = 3 to 3.6 V,
CL = 12 pF
Figure 7
I2S_DB
5
VDDIO = 1.71 to 1.89 V,
CL = 12 pF
5
Data to Low after OSS_SEL = L
Setup Time
(1) (2)
VDDIO = 3 to 3.6 V,
CL = 12 pF
Figure 7
5
(1) Specification is ensured by characterization and is not tested in production.
(2) Specification is ensured by design and is not tested in production.
(3) tDDLT is the time required by the device to obtain lock when exiting power-down state with an active serial stream.
6.10 Timing Diagrams
V
DDIO
PCLK
GND
V
DDIO
RGB[n] (odd),
VS, HS
GND
V
DDIO
RGB[n] (even),
DE
GND
Figure 1. Checker Board Data Pattern
12
Copyright © 2010–2017, Texas Instruments Incorporated
DS90UH926Q-Q1
www.ti.com.cn
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
Timing Diagrams (continued)
EW
VOD (+)
CMLOUT
(Diff.)
EH
0V
EH
VOD (-)
t
(1 UI)
BIT
Figure 2. CML Output Driver
V
DDIO
80%
20%
GND
t
t
CHL
CLH
Figure 3. LVCMOS Transition Times
START
BIT
STOP
BIT
START
BIT
STOP
BIT
RIN
0
1
2
33
0
1
2
33
(Diff.)
SYMBOL N
SYMBOL N+1
t
DD
PCLK
(RFB = L)
RGB[7:0],
I2S[2:0],
SYMBOL N-2
SYMBOL N-1
SYMBOL N
HS, VS, DE
Figure 4. Delay - Latency
2.0ë
PDB
0.8ë
RIN
(Diff.)
5}v[š /ꢀŒꢁ
t
DDLT
TRI-STATE
or LOW
LOCK
ù or [
t
XZR
RGB[7:0],
HS, VS, DE,
I2S
ÇwL-{Ç!Ç9 or [hí or tulled Üp
ù or [ or tÜ
PCLK
(RFB = L)
ÇwL-{Ç!Ç9 or [hí
ù or [
OFF
IN LOCK TIME
ACTIVE
OFF
Figure 5. PLL Lock Times and PDB Tri-State Delay
Copyright © 2010–2017, Texas Instruments Incorporated
13
DS90UH926Q-Q1
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
www.ti.com.cn
Timing Diagrams (continued)
V
PCLK
DDIO
w/RFB = H
1/2 V
DDIO
GND
V
DDIO
RGB[7:0],
VS, HS, DE,
I2S
V
OHmin
V
OLmax
GND
t
t
ROH
ROS
Figure 6. Output Data Valid (Setup and Hold) Times With SSCG = OFF
PDB = H
ëLI
OSS_SEL
OEN
ëL[
ëLI
ëL[
RIN
(Diff.)
5}v[š /ꢀŒꢁ
t
SEH
t
SES
t
t
ONH
ONS
ÇwL-{Ç!Ç9
LOCK
(ILDI)
!/ÇLë9
PASS
ILDI
ILDI
RGB[7:0],
HS, VS, DE,
I2S[2:0]
ÇwL-{Ç!Ç9
ÇwL-{Ç!Ç9
[hí
ÇwL-{Ç!Ç9
ÇwL-{Ç!Ç9
!/ÇLë9
!/ÇLë9
[hí
[hí
PCLK
(RFB = L)
[hí
Figure 7. Output State (Setup and Hold) Times
BISTEN
1/2 V
DDIO
t
PASS
1/2 V
PASS
(w/errors)
DDIO
Result Held
Prior BIST Result
Current BIST Test - Toggle on Error
Figure 8. BIST PASS Waveform
14
Copyright © 2010–2017, Texas Instruments Incorporated
DS90UH926Q-Q1
www.ti.com.cn
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
Timing Diagrams (continued)
SDA
t
BUF
t
t
f
t
HD;STA
t
r
LOW
t
t
SP
t
f
r
SCL
t
t
HD;STA
SU;STA
t
SU;STO
t
HIGH
t
t
SU;DAT
HD;DAT
STOP START
START
REPEATED
START
Figure 9. Serial Control Bus Timing Diagram
6.11 Typical Characteristics
78 MHz TX
Pixel Clock
Input
(2 V/DIV)
78 MHz RX
Pixel Clock
Output
(2 V/DIV)
Time (1.25 ns/DIV)
Time (10 ns/DIV)
NOTE: On the rising edge of each clock period, the CML driver
outputs a low stop bit, high start bit, and 33 DC-scrambled data
bits.
Figure 11. Comparison of Deserializer LVCMOS RX PCLK
Output Locked to a 78-MHz TX PCLK
Figure 10. Serializer CML Driver Output
With 78-MHZ TX Pixel Clock
Copyright © 2010–2017, Texas Instruments Incorporated
15
DS90UH926Q-Q1
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
www.ti.com.cn
7 Detailed Description
7.1 Overview
The DS90UH926Q-Q1 deserializer receives a 35 bits symbol over a single serial FPD-Link III pair operating up to
a 2.975 Gbps application payload. The serial stream contains an embedded clock, video control signals and the
DC-balanced video data and audio data which enhance signal quality to support AC coupling.
The DS90UH926Q-Q1 deserializer attains lock to a data stream without the use of a separate reference clock
source, which greatly simplifies system complexity and overall cost. The deserializer also synchronizes to the
serializer regardless of the data pattern, delivering true automatic plug and lock performance. It can lock to the
incoming serial stream without the need of special training patterns or sync characters. The deserializer recovers
the clock and data by extracting the embedded clock information, validating then deserializing the incoming data
stream. It also applies decryption through a High-Bandwidth Digital Content Protection (HDCP) Cipher to this
video and audio data stream following reception of the data from the FPD-Link III decoder. The decrypted parallel
LVCMOS video bus is provided to the display. The deserializer is intended for use with the DS90UH925Q
serializer, but is also backward-compatible with DS90UR905Q or DS90UR907Q FPD-Link II serializer.
7.2 Functional Block Diagram
w9DÜ[!Çhw
SSCG
CMF
24
RGB [7:0]
HS
VS
DE
RIN+
RIN-
I2S_CLK
I2S_WC
I2S_DA
MCLK
4
CMLOUTP
CMLOUTN
Error
Detector
BISTEN
BISTC
PASS
PDB
SCL
Clock and
Data
Recovery
Timing and
Control
PCLK
LOCK
SCA
IDx
MODE_SEL
7.3 Feature Description
7.3.1 High-Speed Forward Channel Data Transfer
The high-speed forward channel (HS_FC) is composed of 35 bits of data containing RGB data, sync signals,
HDCP, I2C, and I2S audio transmitted from Serializer to Deserializer. Figure 12 illustrates the serial stream per
PCLK cycle. This data payload is optimized for signal transmission over an AC-coupled link. Data is randomized,
balanced and scrambled.
C1
C0
Figure 12. FPD-Link III Serial Stream
16
Copyright © 2010–2017, Texas Instruments Incorporated
DS90UH926Q-Q1
www.ti.com.cn
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
Feature Description (continued)
The device supports clocks in the range of 5 MHz to 85 MHz. The application payload rate is 2.975-Gbps
maximum (175 Mbps minimum) with the actual line rate of 2.975 Gbps maximum and 525 Mbps minimum.
7.3.2 Low-Speed Back Channel Data Transfer
The low-speed backward channel (LS_BC) of the DS90UH926Q-Q1 provides bidirectional communication
between the display and host processor. The information is carried back from the Deserializer to the Serializer
per serial symbol. The back channel control data is transferred over the single serial link along with the high-
speed forward data, DC balance coding, and embedded clock information. This architecture provides a backward
path across the serial link together with a high-speed forward channel. The back channel contains the I2C,
HDCP, CRC and 4 bits of standard GPIO information with 10-Mbps line rate.
7.3.3 Backward Compatible Mode
The DS90UH926Q-Q1 is also backward-compatible to DS90UR905Q and DS90UR907Q FPD Link II serializers
with 15- to 65-MHz pixel clock frequencies supported. It receives 28 bits of data over a single serial FPD-Link II
pair operating at the line rate of 420 Mbps to 1.82 Gbps. This backward-compatible mode is provided through the
MODE_SEL pin (Table 9) or the configuration register (Table 11). When backward-compatible mode = ON, set
LFMODE = 0.
7.3.4 Input Equalization Gain
FPD-Link III input adaptive equalizer provides compensation for transmission medium losses and reduces the
medium-induced deterministic jitter. It equalizes up to 10 meter STP cables with 3 connection breaks at
maximum serialized stream payload rate of 2.975 Gbps.
7.3.5 Common-Mode Filter Pin (CMF)
The deserializer provides access to the center tap of the internal termination. A capacitor must be placed on this
pin for additional common-mode filtering of the differential pair. This can be useful in high noise environments for
additional noise rejection capability. A 0.1-μF capacitor has to be connected to this pin to Ground.
7.3.6 Video Control Signal Filter
When operating the devices in Normal Mode, the Video Control Signals (DE, HS, VS) have the following
restrictions:
•
•
•
Normal Mode with Control Signal Filter Enabled: DE and HS — Only 2 transitions per 130 clock cycles are
transmitted, the transition pulse must be 3 PCLK or longer.
Normal Mode with Control Signal Filter Disabled: DE and HS — Only 2 transitions per 130 clock cycles are
transmitted, no restriction on minimum transition pulse.
VS — Only 1 transition per 130 clock cycles are transmitted, minimum pulse width is 130 clock cycles.
Video Control Signals are defined as low-frequency signals with limited transitions. Glitches of a control signal
can cause a visual display error. This feature allows for the chipset to validate and filter out any high-frequency
noise on the control signals. See Figure 13.
Copyright © 2010–2017, Texas Instruments Incorporated
17
DS90UH926Q-Q1
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
www.ti.com.cn
Feature Description (continued)
PCLK
IN
HS/VS/DE
IN
Latency
PCLK
OUT
Pulses 1 or 2
PCLKs wide
HS/VS/DE
OUT
Filetered OUT
Figure 13. Video Control Signal Filter Waveform
7.3.7 EMI Reduction Features
7.3.7.1 Spread Spectrum Clock Generation (SSCG)
The DS90UH926Q-Q1 provides an internally-generated spread spectrum clock (SSCG) to modulate its outputs.
Both clock and data outputs are modulated. This will aid to lower system EMI. Output SSCG deviations to ±2.5%
(5% total) at up to 100-kHz modulations are available. This feature may be controlled by register. See Table 1,
Table 2 and Table 11. Do not enable the SSCG feature if the source PCLK into the SER has a clock with spread
spectrum already.
Frequency
fdev(max)
F
PCLK+
F
PCLK
F
fdev(min)
Time
PCLK-
1/fmod
Figure 14. SSCG Waveform
Table 1. SSCG Configuration
LFMODE = L (15 to 85 MHz)
SSCG CONFIGURATION (0x2C) LFMODE = L (15 to 85 MHz)
SPREAD SPECTRUM OUTPUT
Fdev (%) Fmod (kHz)
SSC[2]
SSC[1]
SSC[0]
L
L
L
L
L
H
L
±0.9
±1.2
±1.9
±2.5
±0.7
±1.3
±2.0
±2.5
PCLK / 2168
L
H
H
L
L
H
L
H
H
H
H
PCLK / 1300
L
H
L
H
H
H
18
Copyright © 2010–2017, Texas Instruments Incorporated
DS90UH926Q-Q1
www.ti.com.cn
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
Table 2. SSCG Configuration
LFMODE = H (5 to < 15 MHz)
SSCG CONFIGURATION (0x2C) LFMODE = H (5 to <15 MHz)
SPREAD SPECTRUM OUTPUT
SSC[2]
SSC[1]
SSC[0]
Fdev (%)
±0.5
±1.3
±1.8
±2.5
±0.7
±1.2
±2
Fmod (kHz)
L
L
L
L
L
H
L
PCLK / 628
L
H
H
L
L
H
L
H
H
H
H
PCLK / 388
L
H
L
H
H
H
±2.5
7.3.8 Enhanced Progressive Turnon (EPTO)
The deserializer LVCMOS parallel outputs timing are delayed. Groups of 8-bit R, G and B outputs switch in a
different time. This minimizes the number of outputs switching simultaneously and helps to reduce supply noise.
In addition it spreads the noise spectrum out reducing overall EMI.
7.3.9 LVCMOS VDDIO Option
The deserializer parallel bus can operate with 1.8 V or 3.3 V levels (VDDIO) for target (Display) compatibility.
The 1.8 V levels will offer a lower noise (EMI) and also a system power savings.
7.3.10 Power Down (PDB)
The Serializer has a PDB input pin to ENABLE or POWER DOWN the device. This pin can be controlled by the
host or through the VDDIO, where VDDIO = 3 to 3.6 V or VDD33. To save power disable the link when the display is
not needed (PDB = LOW). When the pin is driven by the host, make sure to release it after VDD33 and VDDIO have
reached final levels; no external components are required. In the case of driven by the VDDIO = 3 to 3.6 V or
VDD33 directly, a 10 kΩ resistor to the VDDIO = 3 to 3.6 V or VDD33 , and a > 10 µF capacitor to the ground are
required (See Figure 24).
7.3.11 Stop Stream Sleep
The deserializer enters a low power SLEEP state when the input serial stream is stopped. A STOP condition is
detected when the embedded clock bits are not present. When the serial stream starts again, the deserializer will
then lock to the incoming signal and recover the data.
NOTE
In STOP STREAM SLEEP, the Serial Control Bus Registers values are retained.
7.3.12 Serial Link Fault Detect
The serial link fault detection is able to detect any of following 7 conditions
1. cable open
2. + to - short
3. + short to GND
4. - short to GND
5. + short to battery
6. - short to battery
7. Cable is linked incorrectly
If any one of the fault conditions occurs, The Link Detect Status is 0 (cable is not detected) on the Serial Control
Bus Register bit 0 of address 0x1C Table 11. The link errors can be monitored though Link Error Count of the
Serial Control Bus Register bit [4:0] of address 0x41 Table 11.
Copyright © 2010–2017, Texas Instruments Incorporated
19
DS90UH926Q-Q1
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
www.ti.com.cn
7.3.13 Oscillator Output
The deserializer provides an optional PCLK output when the input clock (serial stream) has been lost. This is
based on an internal oscillator. The frequency of the oscillator may be selected. This feature is controlled by
register Address 0x02, bit 5 (OSC Clock Enable). See Table 11.
7.3.14 Pixel Clock Edge Select (RFB)
The RFB determines the edge that the data is strobed on. If RFB is High (‘1’), output data is strobed on the
Rising edge of the PCLK. If RFB is Low (‘0’), data is strobed on the Falling edge of the PCLK. This allows for
inter-operability with downstream devices. The deserializer output does not need to use the same edge as the
Ser input. This feature may be controlled by register. See Table 11.
7.3.15 Built In Self Test (BIST)
An optional At-Speed, Built-In Self Test (BIST) feature supports the testing of the high speed serial link and the
low- speed back channel. This is useful in the prototype stage, equipment production, in-system test and also for
system diagnostics. The BIST is not available in backwards-compatible mode.
7.3.15.1 BIST Configuration and Status
The BIST mode is enabled at the deserializer by the Pin select (Pin 44 BISTEN and Pin 16 BISTC) or
configuration register (Table 11) through the deserializer. When LFMODE = 0, the pin based configuration
defaults to external PCLK or 33 MHz internal Oscillator clock (OSC) frequency. In the absence of PCLK, the user
can select the desired OSC frequency (default 33 MHz or 25 MHz) through the register bit. When LFMODE = 1,
the pin based configuration defaults to external PCLK or 12.5 MHz MHz internal Oscillator clock (OSC)
frequency.
When BISTEN of the deserializer is high, the BIST mode enable information is sent to the serializer through the
Back Channel. The serializer outputs a test pattern and drives the link at speed. The deserializer detects the test
pattern and monitors it for errors. The PASS output pin toggles to flag any payloads that are received with 1- to
35-bit errors.
The BIST status is monitored real time on PASS pin. The result of the test is held on the PASS output until reset
(new BIST test or Power Down). A High on PASS indicates NO ERRORS were detected. A Low on PASS
indicates one or more errors were detected. The duration of the test is controlled by the pulse width applied to
the deserializer BISTEN pin. This BIST feature also contains a Link Error Count and a Lock Status. If the
connection of the serial link is broken, then the link error count is shown in the register. When the PLL of the
deserializer is locked or unlocked, the lock status can be read in the register. See Table 11.
7.3.15.1.1 Sample BIST Sequence
See Figure 15 for the BIST mode flow diagram.
1. For the DS90UH925Q-Q1 and DS90UH926Q-Q1 FPD-Link III chipset, BIST Mode is enabled through the
BISTEN pin of DS90UH926Q-Q1 FPD-Link III deserializer. The desired clock source is selected through
BISTC pin.
2. The DS90UH925Q-Q1 serializer is woken up through the back channel if it is not already on. The all zero
pattern on the data pins is sent through the FPD-Link III to the deserializer. Once the serializer and the
deserializer are in BIST mode and the deserializer acquires Lock, the PASS pin of the deserializer goes high
and BIST starts checking the data stream. If an error in the payload (1 to 35) is detected, the PASS pin will
switch low for one half of the clock period. During the BIST test, the PASS output can be monitored and
counted to determine the payload error rate.
3. To Stop the BIST mode, the deserializer BISTEN pin is set Low. The deserializer stops checking the data.
The final test result is held on the PASS pin. If the test ran error free, the PASS output will be High. If there
was one or more errors detected, the PASS output will be Low. The PASS output state is held until a new
BIST is run, the device is RESET, or Powered Down. The BIST duration is user controlled by the duration of
the BISTEN signal.
4. The Link returns to normal operation after the deserializer BISTEN pin is low. Figure 16 shows the waveform
diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple errors.
In most cases it is difficult to generate errors due to the robustness of the link (differential data transmission
etc.), thus they may be introduced by greatly extending the cable length, faulting the interconnect, reducing
20
Copyright © 2010–2017, Texas Instruments Incorporated
DS90UH926Q-Q1
www.ti.com.cn
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
signal condition enhancements ( Rx Equalization).
Normal
Step 1: DES in BIST
BIST
Wait
Step 2: Wait, SER in BIST
BIST
start
Step 3: DES in Normal Mode -
check PASS
BIST
stop
Step 4: DES/SER in Normal
Figure 15. BIST Mode Flow Diagram
7.3.15.2 Forward-Channel and Back-Channel Error Checking
While in BIST mode, the serializer stops sampling RGB input pins and switches over to an internal all-zero
pattern. The internal all-zeroes pattern goes through scrambler, dc-balancing etc. and goes over the serial link to
the deserializer. The deserializer on locking to the serial stream compares the recovered serial stream with all-
zeroes and records any errors in status registers and dynamically indicates the status on PASS pin. The
deserializer then outputs a SSO pattern on the RGB output pins.
The back-channel data is checked for CRC errors once the serializer locks onto back-channel serial stream as
indicated by link detect status (register bit 0x0C[0]). The CRC errors are recorded in an 8-bit register. The
register is cleared when the serializer enters the BIST mode. As soon as the serializer exits BIST mode, the
functional mode CRC register starts recording the CRC errors. The BIST mode CRC error register is active in
BIST mode only and keeps the record of last BIST run until it clears or enters BIST mode again.
BISTEN
(DES)
PCLK
(RFB = L)
ROUT[23:0]
HS, VS, DE
DATA
(internal)
PASS
Prior Result
Prior Result
PASS
FAIL
X = bit error(s)
DATA
(internal)
X
X
X
PASS
BIST
Result
Held
Normal
SSO
Normal
BIST Test
BIST Duration
Figure 16. BIST Waveforms
Copyright © 2010–2017, Texas Instruments Incorporated
21
DS90UH926Q-Q1
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
www.ti.com.cn
7.3.16 Image Enhancement Features
Several image enhancement features are provided. White balance LUTs allow the user to define and target the
color temperature of the display. Adaptive Hi-FRC dithering enables the presentation of “true-color” images on an
18–bit color display.
7.3.16.1 White Balance
The White Balance feature enables similar display appearance when using LCDs from different vendors. It
compensates for native color temperature of the display, and adjusts relative intensities of R, G, B to maintain
specified color temperature. Programmable control registers are used to define the contents of three LUTs (8-bit
color value for Red, Green and Blue) for the white balance feature. The LUTs map input RGB values to new
output RGB values. There are three LUTs, one LUT for each color. Each LUT contains 256 entries, 8 bits per
entry with a total size of 6144 bits (3 x 256 x 8). All entries are readable and writable. Calibrated values are
loaded into registers through the I2C interface (deserializer is a slave device). This feature may also be applied
to lower color depth applications such as 18–bit (666) and 16–bit (565). White balance is enabled and configured
through that serial control bus register.
7.3.16.1.1 LUT Contents
The user must define and load the contents of the LUT for each color (R,G,B). Regardless of the color depth
being driven (888, 666, 656), the user must always provide contents for 3 complete LUTs - 256 colors x 8 bits x 3
tables. Unused bits - LSBs -shall be set to 0 by the user.
When 24-bit (888) input data is being driven to a 24-bit display, each LUT (R, G and B) must contain 256 unique
8-bit entries. The 8-bit white balanced data is then available at the output of the DS90UH926Q-Q1 deserializer,
and driven to the display.
When 18-bit (666) input data is being driven to an 18-bit display, the white balance feature may be used in one of
two ways. First, simply load each LUT with 256, 8-bit entries. Each 8-bit entry is a 6-bit value (6 MSBs) with the 2
LSBs set to 00. Thus as total of 64 unique 6-bit white balance output values are available for each color (R, G
and B). The 6-bit white balanced data is available at the output of the DS90UH926Q-Q1 deserializer, and driven
directly to the display.
Alternatively, with 6-bit input data the user may choose to load complete 8-bit values into each LUT. This mode
of operation provides the user with finer resolution at the LUT output to more closely achieve the desired white
point of the calibrated display. Although 8-bit data is loaded, only 64 unique 8-bit white balance output values are
available for each color (R, G and B). The result is 8-bit white balanced data. Before driving to the output of the
deserializer, the 8-bit data must be reduced to 6-bit with an FRC dithering function. To operate in this mode, the
user must configure the DS90UH926Q-Q1 to enable the FRC2 function.
Examples of the three types of LUT configurations described are shown in Figure 17
7.3.16.1.2 Enabling White Balance
The user must load all 3 LUTs prior to enabling the white balance feature. The following sequence must be
followed by the user.
To initialize white balance after power-on (Table 3):
1. Load contents of all 3 LUTs . This requires a sequential loading of LUTs - first RED, second GREEN, third
BLUE. 256, 8-bit entries must be loaded to each LUT. Page registers must be set to select each LUT.
2. Enable white balance.
By default, the LUT data may not be reloaded after initialization at power-on.
An option does exist to allow LUT reloading after power-on and initial LUT loading (as described above). This
option may only be used after enabling the white balance reload feature through the associated serial control bus
register. In this mode the LUTs may be reloaded by the master controller through the I2C. This provides the user
with the flexibility to refresh LUTs periodically , or upon system requirements to change to a new set of LUT
values. The host controller loads the updated LUT values through the serial bus interface. There is no need to
disable the white balance feature while reloading the LUT data. Refreshing the white balance to the new set of
LUT data will be seamless - no interruption of displayed data.
It is important to note that initial loading of LUT values requires that all three LUTs be loaded sequentially. When
reloading, partial LUT updates may be made.
22
Copyright © 2010–2017, Texas Instruments Incorporated
DS90UH926Q-Q1
www.ti.com.cn
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
8-bit in / 8 bit out
6-bit in / 6 bit out
6-bit in / 8 bit out
Gray level Data Out
Gray level Data Out
Gray level Data Out
Entry
(8-bits)
Entry
(8-bits)
Entry
(8-bits)
0
1
2
3
4
5
6
7
8
9
00000000b
00000001b
00000011b
00000011b
00000110b
00000110b
00000111b
00000111b
00001000b
00001010b
0
00000000b
0
00000001b
1 N/A
2 N/A
3 N/A
1 N/A
2 N/A
3 N/A
4
00000100b
4
00000110b
5 N/A
6 N/A
7 N/A
5 N/A
6 N/A
7 N/A
8
00001000b
8
00001011b
9 N/A
10 N/A
11 N/A
9 N/A
10 N/A
11 N/A
10 00001001b
11 00001011b
248 11111010b
249 11111010b
250 11111011b
251 11111011b
252 11111110b
253 11111101b
254 11111101b
255 11111111b
248 11111000b
249 N/A
248 11111010b
249 N/A
250 N/A
250 N/A
251 N/A
252 11111100b
253 N/A
251 N/A
252 11111111b
253 N/A
254 N/A
255 N/A
254 N/A
255 N/A
Figure 17. White Balance LUT Configurations
Table 3. White Balance Register Table
DEFAU
LT
(hex)
ADD
(dec)
ADD
(hex)
PAGE
REGISTER NAME BITS ACCESS
FUNCTION
DESCRIPTION
00: Configuration Registers
01: Red LUT
10: Green LUT
7:6
5
RW
Page Setting
11: Blue LUT
White Balance
Control
White Balance 0: White Balance Disable
0
42
0x2A
0x00
RW
RW
Enable
1: White Balance Enable
0: Reload Disable
1: Reload Enable
4
3:0
Reserved
0 –
255
White Balance Red
LUT
256 8–bit entries to be applied to the Red
subpixel data
1
2
3
00 – FF
00 – FF
00 – FF
FF:0
RW
RW
RW
N/A
N/A
N/A
Red LUT
Green LUT
Blue LUT
0 –
255
White Balance
Green LUT
256 8–bit entries to be applied to the Green
subpixel data
FF:0
FF:0
0 –
255
White Balance
Blue LUT
256 8–bit entries to be applied to the Blue
subpixel data
7.3.16.2 Adaptive HI-FRC Dithering
The Adaptive FRC Dithering Feature delivers product-differentiating image quality. It reduces 24-bit RGB (8 bits
per subpixel) to 18-bit RGB (6 bits per sub-pixel), smoothing color gradients, and allowing the flexibility to use
lower cost 18-bit displays. FRC (Frame Rate Control) dithering is a method to emulate “missing” colors on a
lower color depth LCD display by changing the pixel color slightly with every frame. FRC is achieved by
controlling on and off pixels over multiple frames (Temporal). Static dithering regulates the number of on and off
pixels in a small defined pixel group (Spatial). The FRC module includes both Temporal and Spatial methods and
also Hi-FRC. Conventional FRC can display only 16,194,277 colors with 6-bit RGB source. “Hi-FRC” enables full
(16,777,216) color on an 18-bit LCD panel. The “adaptive” FRC module also includes input pixel detection to
apply specific Spatial dithering methods for smoother gray level transitions. When enabled, the lower LSBs of
each RGB output are not active; only 18 bit data (6 bits per R,G and B) are driven to the display. This feature is
enabled through the serial control bus register.
Copyright © 2010–2017, Texas Instruments Incorporated
23
DS90UH926Q-Q1
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
www.ti.com.cn
Two FRC functional blocks are available, and may be independently enabled. FRC1 precedes the white balance
LUT, and is intended to be used when 24-bit data is being driven to an 18-bit display with a white balance LUT
that is calibrated for an 18-bit data source. The second FRC block, FRC2, follows the white balance block and is
intended to be used when fine adjustment of color temperature is required on an 18-bit color display, or when a
24-bit source drives an 18-bit display with a white balance LUT calibrated for 24-bit source data.
For proper operation of the FRC dithering feature, the user must provide a description of the display timing
control signals. The timing mode, “sync mode” (HS, VS) or “DE only” must be specified, along with the active
polarity of the timing control signals. All this information is entered to DS90UH926Q-Q1 control registers through
the serial bus interface.
Adaptive Hi-FRC dithering consists of several components. Initially, the incoming 8-bit data is expanded to 9-bit
data. This allows the effective dithered result to support a total of 16.7 million colors. The incoming 9-bit data is
evaluated, and one of four possible algorithms is selected. The majority of incoming data sequences are
supported by the default dithering algorithm. Certain incoming data patterns (black/white pixel, full on/off sub-
pixel) require special algorithms designed to eliminate visual artifacts associated with these specific gray level
transitions. Three algorithms are defined to support these critical transitions.
An example of the default dithering algorithm is illustrated in Figure 18. The 1 or 0 value shown in the table
describes whether the 6-bit value is increased by 1 (1) or left unchanged (0). In this case, the 3 truncated LSBs
are 001.
F0L0
PD1
Frame = 0, Line = 0
Pixel Data one
Cell Value 010
R[7:2]+0, G[7:2]+1, B[7:2]+0
LSB=001
three lsb of 9 bit data (8 to 9 for Hi-Frc)
Pixel Index
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
LSB = 001
F0L0
F0L1
F0L2
F0L3
010
101
000
000
000
000
000
000
000
000
010
101
000
000
000
000
000
101
010
000
000
000
000
000
010
000
000
101
000
000
000
000
R = 4/32
G = 4/32
B = 4/32
F1L0
F1L1
F1L2
F1L3
000
000
000
000
000
111
000
000
000
000
000
000
000
000
000
111
000
000
000
000
000
111
000
000
000
000
000
000
000
000
000
111
R = 4/32
G = 4/32
B = 4/32
F2L0
F2L1
F2L2
F2L3
000
000
010
101
000
000
000
000
010
101
000
000
000
000
000
000
010
000
000
101
000
000
000
000
000
101
010
000
000
000
000
000
R = 4/32
G = 4/32
B = 4/32
F3L0
F3L1
F3L2
F3L3
000
000
000
000
000
000
000
111
000
000
000
000
000
111
000
000
000
000
000
000
000
000
000
111
000
000
000
000
000
111
000
000
R = 4/32
G = 4/32
B = 4/32
Figure 18. Default FRC Algorithm
24
Copyright © 2010–2017, Texas Instruments Incorporated
DS90UH926Q-Q1
www.ti.com.cn
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
Table 4. Recommended FRC Settings
SOURCE
WHITE BALANCE LUT
DISPLAY
24–bit
18–bit
18–bit
24–bit
18–bit
18–bit
FRC1
FRC2
24–bit
24–bit
24–bit
18–bit
18–bit
18–bit
24–bit
24–bit
18–bit
24–bit
24–bit
18–bit
Disabled
Disabled
Enabled
Disabled
Disabled
Disabled
Disabled
Enabled
Disabled
Disabled
Enabled
Disabled
7.3.17 Internal Pattern Generation
The DS90UH926Q-Q1 serializer supports the internal pattern generation feature. It allows basic testing and
debugging of an integrated panel. The test patterns are simple and repetitive and allow for a quick visual
verification of panel operation. As long as the device is not in power down mode, the test pattern will be
displayed even if no parallel input is applied. If no PCLK is received, the test pattern can be configured to use a
programmed oscillator frequency. For detailed information, refer to AN-2198 Exploring the Internal Test Pattern
Generation Feature of 720p FPD-Link III Devices (SNLA132).
7.3.18 I2S Receiving
In normal 24-bit RGB operation mode, the DS90UH926Q-Q1 provides up to 3-bit of I2S. They are I2S_CLK,
I2S_WC and I2S_DA, as well as the Master I2S Clock (MCLK). The audio is received through the forward video
frame, or can be configured to receive during video blanking periods. A jitter cleaning feature reduces I2S_CLK
output jitter to +/- 2ns. The encrypted and packetized audio information is received during the video blanking
periods along with specific information about the clock frequency. The bit rates of any I2S input bits must
maintain one fourth of the PCLK rate. The audio decryption is supported per HDCP v1.3.
7.3.18.1 I2S Jitter Cleaning
In 18-bit RGB operation mode, the secondary I2S data (I2S_DB) can be used as the additional I2S audio
channel in additional to the 3–bit of I2S. The I2S_DB is synchronized to the I2S_CLK. To enable this
synchronization feature on this bit, set the MODE_SEL (Table 9) or program through the register bit ()
7.3.18.2 Secondary I2S Channel
In 18-bit RGB operation mode, the secondary I2S data (I2S_DB) can be used as the additional I2S audio
channel in additional to the 3–bit of I2S. The I2S_DB is synchronized to the I2S_CLK. To enable this
synchronization feature on this bit, set the MODE_SEL (Table 9) or program through the register bit (Table 11).
7.3.18.2.1 MCLK
The deserializer has an I2S Master Clock Output. It supports x1, x2, or x4 of I2S CLK Frequency. When the I2S
PLL is disabled, the MCLK output is off. Table 5 below covers the range of I2S sample rates and MCLK
frequencies. By default, all the MCLK output frequencies are x2 of the I2S CLK frequencies. The MCLK
frequencies can also be enabled through the register bit [7:4] (I2S MCLK Output) of 0x3A shown in Table 11. To
select desired MCLK frequency, write bit 7 (0x3A) = 1, then write to bit [6:4] accordingly.
Copyright © 2010–2017, Texas Instruments Incorporated
25
DS90UH926Q-Q1
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
www.ti.com.cn
Table 5. Audio Interface Frequencies
SAMPLE RATE
(kHz)
I2S DATA WORD SIZE
(BITS)
I2S CLK
(MHz)
MCLK OUTPUT
(MHz)
REGISTER 0x3A[6:4]'b
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
000
001
010
000
001
010
000
001
010
001
010
011
010
011
100
000
001
010
001
010
011
001
010
011
010
011
100
011
100
101
001
010
011
001
010
011
001
010
011
010
011
100
011
100
110
32
44.1
48
1.024
1.4112
1.536
3.072
6.144
1.536
2.117
2.304
4.608
9.216
2.048
2.8224
3.072
6.144
12.288
16
24
32
96
192
32
44.1
48
96
192
32
44.1
48
96
192
26
Copyright © 2010–2017, Texas Instruments Incorporated
DS90UH926Q-Q1
www.ti.com.cn
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
7.3.19 Interrupt Pin: Functional Description and Usage (INTB)
1. On DS90UH925Q-Q1, set register 0xC6[5] = 1 and 0xC6[0] = 1
2. DS90UH926Q-Q1 deserializer INTB_IN (pin 16) is set LOW by some downstream device.
3. DS90UH925Q-Q1 serializer pulls INTB (pin 31) LOW. The signal is active low, so a LOW indicates an
interrupt condition.
4. External controller detects INTB = LOW; to determine interrupt source, read HDCP_ISR register .
5. A read to HDCP_ISR will clear the interrupt at the DS90UH925, releasing INTB.
6. The external controller typically must then access the remote device to determine downstream interrupt
source and clear the interrupt driving INTB_IN. This would be when the downstream device releases the
INTB_IN (pin 16) on the DS90UH926Q-Q1. The system is now ready to return to step (1) at next falling edge
of INTB_IN.
7.3.20 GPIO[3:0] and GPO_REG[8:4]
In 18-bit RGB operation mode, the optional R[1:0] and G[1:0] of the DS90UH926Q-Q1 can be used as the
general purpose IOs GPIO[3:0] in either forward channel (Outputs) or back channel (Inputs) application.
7.3.20.1 GPIO[3:0] Enable Sequence
See Table 6 for the GPIO enable sequencing.
1. Enable the 18-bit mode either through the configuration register bit Table 11 on DS90UH925Q-Q1 only.
DS90UH926Q-Q1 is automatically configured as in the 18-bit mode.
2. To enable GPIO3 forward channel, write 0x03 to address 0x0F on DS90UH925Q-Q1, then write 0x05 to
address 0x1F on DS90UH926Q-Q1.
Table 6. GPIO Enable Sequencing Table
NO.
DESCRIPTION
DEVICE
FORWARD CHANNEL
0x12 = 0x04
BACK CHANNEL
0x12 = 0x04
1
Enable 18-bit mode
DS90UH925Q-Q1
DS90UH926Q-Q1
DS90UH925Q-Q1
DS90UH926Q-Q1
DS90UH925Q-Q1
DS90UH926Q-Q1
DS90UH925Q-Q1
DS90UH926Q-Q1
DS90UH925Q-Q1
DS90UH926Q-Q1
Auto Load from DS90UH925Q-Q1
0x0F = 0x03
Auto Load from DS90UH925Q-Q1
0x0F = 0x05
2
3
4
5
GPIO3
GPIO2
GPIO1
GPIO0
0x1F = 0x05
0x1F = 0x03
0x0E = 0x30
0x0E = 0x50
0x1E = 0x50
0x1E = 0x30
0x0E = 0x03
0x0E = 0x05
0x1E = 0x05
0x0E = 0x05
0x0D = 0x93
0x0D = 0x95
0x1D = 0x95
0x1D = 0x93
7.3.20.2 GPO_REG[8:4] Enable Sequence
GPO_REG[8:4] are the outputs only pins. They must be programmed through the local register bits. See
Table 11 for the GPO_REG enable sequencing.
1. Enable the 18-bit mode either through the configuration register bit Table 11 on DS90UH925Q-Q1 only.
DS90UH926Q-Q1 is automatically configured as in the 18-bit mode.
2. To enable GPO_REG8 outputs a 1, write 0x90 to address 0x11 on DS90UH925Q.
Table 7. GPO_REG Enable Sequencing Table
NO.
DESCRIPTION
DEVICE
LOCAL ACCESS
LOCAL OUTPUT VALUE
1
Enable 18-bit mode
DS90UH926Q-Q1
0x12 = 0x04
(on DS90UH925Q-Q1)
2
3
GPO_REG8
GPO_REG7
DS90UH926Q-Q1
DS90UH926Q-Q1
0x21 = 0x90
0x21 = 0x10
0x21 = 0x09
0x21 = 0x01
1
0
1
0
Copyright © 2010–2017, Texas Instruments Incorporated
27
DS90UH926Q-Q1
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
www.ti.com.cn
Table 7. GPO_REG Enable Sequencing Table (continued)
NO.
DESCRIPTION
DEVICE
LOCAL ACCESS
0x20 = 0x90
0x20 = 0x10
0x20 = 0x09
0x20 = 0x01
0x1F = 0x90
0x1F = 0x10
LOCAL OUTPUT VALUE
4
GPO_REG6
DS90UH926Q-Q1
1
0
1
0
1
0
5
6
GPO_REG5
GPO_REG4
DS90UH926Q-Q1
DS90UH926Q-Q1
7.4 Device Functional Modes
7.4.1 Clock-Data Recovery Status Flag (LOCK), Output Enable (OEN), and Output State Select
(OSS_SEL)
When PDB is driven HIGH, the CDR PLL begins locking to the serial input and LOCK is TRI-STATE or LOW
(depending on the value of the OEN setting). After the DS90UH926Q-Q1 completes its lock sequence to the
input serial data, the LOCK output is driven HIGH, indicating valid data and clock recovered from the serial input
is available on the parallel bus and PCLK outputs. The State of the outputs are based on the OEN and
OSS_SEL setting (Table 8) or register bit (Table 11). See Figure 7.
Table 8. Output States
INPUTS
OUTPUTS
Serial
input
PDB
OEN
OSS_SEL
Lock
Pass
Data, GPIO, I2S
CLK
X
X
X
0
1
1
X
0
0
X
0
1
Z
Z
L
Z
Z
L
Z
Z
L
Z
L or H
L or H
L/OSC (Register bit
enable)
Static
1
1
0
L
L
L
Static
Active
Active
1
1
1
1
1
1
1
0
1
L
H
H
Previous Status
L
L
L
L
L
Valid
Valid
Valid
7.4.2 Low Frequency Optimization (LFMODE)
The LFMODE is set through a register (Table 11) or MODE_SEL Pin 24 (Table 9). It controls the operating
frequency of the deserializer. If LFMODE is Low (default), the PCLK frequency is between 15 MHz and 85 MHz.
If LFMODE is High, the PCLK frequency is between 5 MHz and <15 MHz. Please note: when the device
LFMODE is changed, a PDB reset is required.
7.4.3 Configuration Select (MODE_SEL)
Configuration of the device may be done through the MODE_SEL input pin, or through the configuration register
bit. A pullup resistor and a pulldown resistor of suggested values may be used to set the voltage ratio of the
MODE_SEL input (VR4) and VDD33 to select one of the other 10 possible selected modes. See Figure 19 and
Table 9.
VDD33
R
R
3
4
MODE_SEL
VR4
DES
Figure 19. MODE_SEL Connection Diagram
28
Copyright © 2010–2017, Texas Instruments Incorporated
DS90UH926Q-Q1
www.ti.com.cn
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
Table 9. Configuration Select (MODE_SEL)
IDEAL
RATIO
VR4/VDD33
SUGGESTED SUGGESTED
IDEAL VR4
(V)
BACKWARD
I2S CHANNEL B
NO.
RESISTOR R3 RESISTOR R4 LFMODE(1) REPEATER(2)
COMPATIBLE(3) (18–bit MODE)(4)
kΩ (1% tol)
Open
115
kΩ (1% tol)
1
2
3
4
5
6
7
8
9
0
0
40.2
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L
0.123
0.167
0.227
0.291
0.366
0.458
0.542
0.611
0.407
0.552
0.748
0.960
1.209
1.510
1.790
2.016
16.2
121
24.3
L
H
H
L
162
47.5
L
H
L
137
56.2
H
H
H
H
L
107
61.9
L
H
L
113
95.3
H
H
L
95.3
113
H
L
73.2
115
(1) LFMODE:
L = frequency range is 15 MHz to 85 MHz (Default)
H = frequency range is 5 to < 15 MHz
(2) Repeater:
L = Repeater mode is OFF (Default)
H = Repeater mode is ON
(3) Backward Compatible:
L = Backward Compatible mode is OFF (Default)
H = Backward Compatible mode is ON; SER = DS90UR905Q or DS90UR907Q
– frequency range = 15 to 65 MHz, set LFMODE = L
(4) I2S Channel B:
L = I2S Channel B mode is OFF, normal 24-bit RGB Mode (Default)
H = I2S Channel B mode is ON, 18-bit RGB Mode with I2S_DB Enabled. Note: use of GPIO(s) on unused inputs must be enabled by
register.
7.4.4 HDCP Repeater
When DS90UH925Q-Q1 and DS90UH926Q-Q1 are configured as the HDCP Repeater application, it provides a
mechanism to extend HDCP transmission over multiple links to multiple display devices. This repeater
application provides a mechanism to authenticate all HDCP Receivers in the system and distribute protected
content to the HDCP Receivers using the encryption mechanisms provided in the HDCP specification.
In this document, the DS90UH925Q-Q1 is referred to as the HDCP Transmitter or transmit port (TX), and the
DS90UH926Q-Q1 is referred to as the HDCP Receiver (RX). Figure 20 shows the maximum configuration
supported for HDCP Repeater implementations using the DS90UH925Q-Q1 (TX) and DS90UH926Q-Q1 (RX).
Two levels of HDCP Repeaters are supported with a maximum of three HDCP Transmitters per HDCP Receiver.
Copyright © 2010–2017, Texas Instruments Incorporated
29
DS90UH926Q-Q1
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
www.ti.com.cn
1:3 Repeater
1:3 Repeater
Display
Display
RX
RX
TX
RX
TX
Source
TX
RX
TX
TX
TX
TX
Display
RX
1:3 Repeater
Display
Display
RX
RX
TX
TX
TX
RX
Display
RX
1:3 Repeater
Display
Display
RX
RX
TX
TX
TX
RX
Display
RX
Figure 20. HDCP Maximum Repeater Application
To support HDCP Repeater operation, the DS90UH926Q-Q1 Deserializer includes the ability to control the
downstream authentication process, assemble the KSV list for downstream HDCP Receivers, and pass the KSV
list to the upstream HDCP Transmitter. An I2C master within the DS90UH926Q-Q1 communicates with the I2C
slave within the DS90UH925Q-Q1 Serializer. The DS90UH925Q-Q1 Serializer handles authenticating with a
downstream HDCP Receiver and makes status available through the I2C interface. The DS90UH926Q-Q1
monitors the transmit port status for each DS90UH925Q-Q1 and reads downstream KSV and KSV list values
from the DS90UH925Q-Q1.
In addition to the I2C interface used to control the authentication process, the HDCP Repeater implementation
includes two other interfaces. A parallel LVCMOS interface provides the unencrypted video data in 24-bit RGB
format and includes the DE/VS/HS control signals. In addition to providing the RGB video data, the parallel
LVCMOS interface communicates control information and packetized audio data during video blanking intervals.
A separate I2S audio interface may optionally be used to send I2S audio data between the HDCP Receiver and
HDCP Transmitter in place of using the packetized audio over the parallel LVCMOS interface. All audio and
video data is decrypted at the output of the HDCP Receiver and is re-encrypted by the HDCP Transmitter.
Figure 21 provides more detailed block diagram of a 1:2 HDCP repeater configuration.
30
Copyright © 2010–2017, Texas Instruments Incorporated
DS90UH926Q-Q1
www.ti.com.cn
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
HDCP Transmitter
DS90UH925Q-Q1
downstream
Receiver
or
I2C
Slave
I2C
I2C
Master
Repeater
upstream
Transmitter
Parallel
LVCMOS
HDCP Transmitter
DS90UH925Q-Q1
HDCP Receiver
DS90UH926Q-Q1
I2S Audio
downstream
Receiver
or
I2C
Slave
Repeater
FPD-Link III interfaces
Figure 21. HDCP 1:2 Repeater Configuration
7.4.4.1 Repeater Connections
The HDCP Repeater requires the following connections between the HDCP Receiver and each HDCP
Transmitter Figure 22.
1. Video Data – Connect PCLK, RGB and control signals (DE, VS, HS).
2. I2C – Connect SCL and SDA signals. Both signals should be pulled up to VDD33 with 4.7-kΩ resistors
3. Audio – Connect I2S_CLK, I2S_WC, and I2S_DA signals.
4. IDx pin – Each HDCP Transmitter and Receiver must have an unique I2C address.
5. MODE_SEL pin – All HDCP Transmitter and Receiver must be set into the Repeater Mode.
6. Interrupt pin– Connect DS90UH926Q-Q1 INTB_IN pin to DS90UH925Q-Q1 INTB pin. The signal must be
pulled up to VDDIO
.
DS90UH926Q-Q1
DS90UH925Q-Q1
R[7:0]
G[7:0]
B[7:0]
R[7:0]
G[7:0]
B[7:0]
DE
VS
HS
DE
VS
HS
I2S_CLK
I2S_WC
I2S_DA
I2S_CLK
I2S_WC
I2S_DA
VDD33
VDD33
hptional
VDDIO
MODE_SEL
MODE_SEL
INTB_IN
INTB
VDD33
VDD33
VDD33
ID[x]
SDA
ID[x]
SDA
SCL
SCL
Figure 22. HDCP Repeater Connection Diagram
Copyright © 2010–2017, Texas Instruments Incorporated
31
DS90UH926Q-Q1
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
www.ti.com.cn
7.5 Programming
7.5.1 Serial Control Bus
The DS90UH926Q-Q1 is configured by the use of a serial control bus that is I2C protocol compatible. . Multiple
deserializer devices may share the serial control bus since 16 device addresses are supported. Device address
is set through the R1 and R2 values on IDx pin. See Figure 23.
The serial control bus consists of two signals and a configuration pin. The SCL is a Serial Bus Clock Input /
Output. The SDA is the Serial Bus Data Input / Output signal. Both SCL and SDA signals require an external
pull-up resistor to VDD33. For most applications a 4.7 kΩ pull-up resistor to VDD33 may be used. The resistor value
may be adjusted for capacitive loading and data rate requirements. The signals are either pulled High, or driven
Low.
V
DD33
R
R
1
2
V
DD33
IDx
VR2
4.7k
4.7k
HOST
or
SER
or
Salve
DES
SCL
SDA
SCL
SDA
To other
Devices
Figure 23. Serial Control Bus Connection
The configuration pin is the IDx pin. This pin sets one of 16 possible device addresses. A pull-up resistor and a
pull-down resistor of suggested values may be used to set the voltage ratio of the IDx input (VR2) and VDD33 to
select one of the other 16 possible addresses. See Table 10
Table 10. Serial Control Bus Addresses for IDx
SUGGESTED
RESISTOR R1 kΩ
(1% tol)
SUGGESTED
RESISTOR R2 kΩ
(1% tol)
IDEAL RATIO
VR2 / VDD33
IDEAL VR2
(V)
ADDRESS 8'b
APPENDED
NO.
ADDRESS 7'b
1
2
0
0
Open
124
107
133
113
137
102
115
102
115
115
56.2
93.1
82.5
73.2
57.6
40.2
17.4
19.1
29.4
30.1
43.2
37.4
49.9
53.6
73.2
86.6
51.1
102
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x58
0x5A
0x5C
0x5E
0x60
0x62
0x64
0x66
0x68
0x6A
0x6C
0x6E
0x70
0x72
0x74
0x76
0.123
0.151
0.181
0.210
0.240
0.268
0.303
0.344
0.389
0.430
0.476
0.523
0.565
0.611
0.677
0.406
0.500
0.597
0.694
0.791
0.885
0.999
1.137
1.284
1.418
1.572
1.725
1.863
2.016
2.236
3
4
5
6
7
8
9
10
11
12
13
14
15
16
107
115
121
32
Copyright © 2010–2017, Texas Instruments Incorporated
DS90UH926Q-Q1
www.ti.com.cn
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
7.6 Register Maps
Table 11. Serial Control Bus Registers
ADD
ADD Register
Bit(s)
7:1
0
Register
Type
Default Function
(hex)
Descriptions
(dec) (hex) Name
0
1
0x00 I2C Device ID
RW
Device ID
7–bit address of Deserializer
See Table 9
RW
ID Setting
I2C ID Setting
1: Register I2C Device ID (Overrides IDx pin)
0: Device ID is from IDx pin
0x01 Reset
7
RW
0x04 Remote
Remote Auto Power Down
Auto Power 1: Power down when no forward channel link is detected
Down
0: Do not power down when no forward channel link is
detected
6:3
2
Reserved.
RW
RW
BC Enable
Back channel enable
1: Enable
0: Disable
1
0
Digital
RESET1
Reset the entire digital block including registers
This bit is self-clearing.
1: Reset
0: Normal operation
RW
Digital
RESET0
Reset the entire digital block except registers
This bit is self-clearing
1: Reset
0: Normal operation
2
0x02 Configuration
[0]
7
6
5
RW
RW
RW
0x00 Output
LVCMOS Output Enable.
1: Enable
0: Disable. Tri-state Outputs
Enable
OEN and
OSS_SEL
Override
Overrides Output Enable Pin and Output State pin
1: Enable override
0: Disable - no override
OSC Clock OSC Clock Output Enable
Enable
If loss of lock OSC clock is output onto PCLK
0: Disable
1: Enable
4
3
RW
RW
Output
Sleep State Period
Select
(OSS_SEL) 0: Disable
OSS Select to Control Output State during Lock Low
1: Enable
Backward
Backward Compatible (BC) mode set by MODE_SEL pin
Compatible or register.
select by
pin or
1: BC is set by register bit. Use register bit reg_0x02[2] to
set BC Mode
register
control
0: Use MODE_SEL pin.
2
RW
Backward
Backward compatible (BC) mode to DS90UR905Q or
Compatible DS90UR907Q, if reg_0x02[3] = 1
Mode
1: Backward compatible with DS90UR905Q or
Select
DS90UR907Q
(Set LFMODE = 0)
0: Backward Compatible is OFF (default)
1
0
RW
RW
LFMODE
select by
pin or
register
control
Frequency range is set by MODE_SEL pin or register
1: Frequency range is set by register. Use register
bitreg_0x02[0] to set LFMODE
0: Frequency range is set by MODE_SEL pin.
LFMODE
Frequency range select
1: PCLK range = 5 to <15 MHz, if reg_0x02[1] = 1
0: PCLK range = 15 to 85 MHz (default)
Copyright © 2010–2017, Texas Instruments Incorporated
33
DS90UH926Q-Q1
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
www.ti.com.cn
Register Maps (continued)
Table 11. Serial Control Bus Registers (continued)
ADD
ADD Register
Bit(s)
Register
Type
Default Function
(hex)
Descriptions
(dec) (hex) Name
3
0x03 Configuration
7
6
0xF0
Reserved.
[1]
RW
RW
CRC
Generator
Enable
CRC Generator Enable (Back Channel)
1: Enable
0: Disable
5
4
Reserved
Filter
Enable
HS, VS, DE two clock filter When enabled, pulses less
than two full PCLK cycles on the DE, HS, and VS inputs
will be rejected
1: Filtering enable
0: Filtering disable
3
2
RW
RW
I2C Pass-
through
I2C Pass-Through Mode
1: Pass-Through Enabled
0: Pass-Through Disabled
Auto ACK
ACK Select
1: Auto ACK enable
0: Self ACK
1
0
Reserved
RW
RW
RRFB
Pixel Clock Edge Select
1: Parallel Interface Data is strobed on the Rising Clock
Edge.
0: Parallel Interface Data is strobed on the Falling Clock
Edge.
4
0x04 BCC
7:1
0xFE BCC
Watchdog
Timer
The watchdog timer allows termination of a control channel
transaction, if it fails to complete within a programmed
amount of time. This field sets the Bidirectional Control
Channel Watchdog Timeout value in units of 2
milliseconds.
Watchdog
Control
This field should not be set to 0
0
RW
BCC
Watchdog
Timer
Disable Bidirectional Control Channel Watchdog Timer
1: Disables BCC Watchdog Timer operation
0: Enables BCC Watchdog Timer operation"
Disable
5
0x05 I2C Control [1]
7
RW
RW
RW
0x2E I2C Pass
I2C Pass-Through All Transactions
Through All 1: Enabled
0: Disabled
6:4
3:0
I2C SDA
Hold Time
Internal I2C SDA Hold Time
It configures the amount of internal hold time provided for
the SDA input relative to the SCL input. Units are 50 ns.
I2C Filter
Depth
I2C Glitch Filter Depth
It configures the maximum width of glitch pulses on the
SCL and SDA inputs that will be rejected. Units are 5 ns.
34
Copyright © 2010–2017, Texas Instruments Incorporated
DS90UH926Q-Q1
www.ti.com.cn
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
Register Maps (continued)
Table 11. Serial Control Bus Registers (continued)
ADD
ADD Register
Bit(s)
Register
Type
Default Function
(hex)
Descriptions
(dec) (hex) Name
6 0x06 I2C Control [2]
7
R
0x00 Forward
Channel
Control Channel Sequence Error Detected It indicates a
sequence error has been detected in forward control
channel. It this bit is set, an error may have occurred in the
control channel operation.
Sequence
Error
6
RW
Clear
Sequence
Error
It clears the Sequence Error Detect bit
This bit is not self-clearing.
5
Reserved
4:3
RW
RW
SDA Output SDA Output Delay
Delay
This field configures output delay on the SDA output.
Setting this value will increase output delay in units of 50
ns. Nominal output delay values for SCL to SDA are:
00 : 250 ns
01: 300 ns
10: 350 ns
11: 400 ns
2
Local Write Disable Remote Writes to Local Registers through
Serializer (Does not affect remote access to I2C slaves at
Deserializer)
1: Stop remote write to local device registers
0: remote write to local device registers
1
0
RW
RW
I2C Bus
Timer
Speed
Speed up I2C Bus Watchdog Timer
1: Timer expires after approximately 50 ms
0: Timer expires after approximately 1 s
I2C Bus
Timer
Disable
Disable I2C Bus Timer When the I2C Timer may be used
to detect when the I2C bus is free or hung up following an
invalid termination of a transaction. If SDA is high and no
signalling occurs for approximately 1 s, the I2C bus is
assumed to be free. If SDA is low and no signaling occurs,
the device will try to clear the bus by driving 9 clocks on
SCL
7
0x07 Remote
Device ID
7:1
RW
0x18 Remote ID
Remote ID
Configures the I2C Slave ID of the remote Serializer. A
value of 0 in this field disables I2C access to remote
Serializer. This field is automatically configured through the
Serializer Forward Channel. Software may overwrite this
value, but should also set the FREEZE DEVICE ID bit to
prevent overwriting by the Forward Channel.
0
RW
RW
Freeze
Device ID
Freeze Serializer Device ID
1: Prevent auto-loading of the Serializer Device ID from the
Forward Channel. The ID will be frozen at the value
written.
0: Update
8
9
0x08 SlaveID[0]
7:1
0x00 Target
Slave
7-bit Remote Slave Device ID 0
Configures the physical I2C address of the remote I2C
Device ID0 Slave device attached to the remote Serializer. If an I2C
transaction is addressed to the Slave Alias ID0, the
transaction will be remapped to this address before
passing the transaction across the Bidirectional Control
Channel to the Serializer.
0
Reserved
0x09 SlaveID[1]
7:1
RW
0x00 Target
Slave
7-bit Remote Slave Device ID 1
Configures the physical I2C address of the remote I2C
Device ID1 Slave device attached to the remote Serializer. If an I2C
transaction is addressed to the Slave Alias ID1, the
transaction will be remapped to this address before
passing the transaction across the Bidirectional Control
Channel to the Serializer.
0
Reserved
Copyright © 2010–2017, Texas Instruments Incorporated
35
DS90UH926Q-Q1
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
www.ti.com.cn
Register Maps (continued)
Table 11. Serial Control Bus Registers (continued)
ADD
ADD Register
Bit(s)
Register
Type
Default Function
(hex)
Descriptions
(dec) (hex) Name
10
11
12
13
14
15
16
0x0A SlaveID[2]
0x0B SlaveID[3]
0x0C SlaveID[4]
0x0D SlaveID[5]
0x0E SlaveID[6]
0x0F SlaveID[7]
0x10 SlaveAlias[0]
7:1
RW
RW
RW
RW
RW
RW
RW
0x00 Target
Slave
7-bit Remote Slave Device ID 2
Configures the physical I2C address of the remote I2C
Device ID2 Slave device attached to the remote Serializer. If an I2C
transaction is addressed to the Slave Alias ID2, the
transaction will be remapped to this address before
passing the transaction across the Bidirectional Control
Channel to the Serializer.
0
Reserved
7:1
0x00 Target
Slave
7-bit Remote Slave Device ID 3
Configures the physical I2C address of the remote I2C
Device ID3 Slave device attached to the remote Serializer. If an I2C
transaction is addressed to the Slave Alias ID3, the
transaction will be remapped to this address before
passing the transaction across the Bidirectional Control
Channel to the Serializer.
0
Reserved
7:1
0x00 Target
Slave
7-bit Remote Slave Device ID 4
Configures the physical I2C address of the remote I2C
Device ID4 Slave device attached to the remote Serializer. If an I2C
transaction is addressed to the Slave Alias ID4, the
transaction will be remapped to this address before
passing the transaction across the Bidirectional Control
Channel to the Serializer.
0
Reserved
7:1
0x00 Target
Slave
7-bit Remote Slave Device ID 5
Configures the physical I2C address of the remote I2C
Device ID5 Slave device attached to the remote Serializer. If an I2C
transaction is addressed to the Slave Alias ID5, the
transaction will be remapped to this address before
passing the transaction across the Bidirectional Control
Channel to the Serializer.
0
Reserved
7:1
0x00 Target
Slave
7-bit Remote Slave Device ID 6
Configures the physical I2C address of the remote I2C
Device ID6 Slave device attached to the remote Serializer. If an I2C
transaction is addressed to the Slave Alias ID6, the
transaction will be remapped to this address before
passing the transaction across the Bidirectional Control
Channel to the Serializer.
0
Reserved
7:1
0x00 Target
Slave
7-bit Remote Slave Device ID 7
Configures the physical I2C address of the remote I2C
Device ID7 Slave device attached to the remote Serializer. If an I2C
transaction is addressed to the Slave Alias ID7, the
transaction will be remapped to this address before
passing the transaction across the Bidirectional Control
Channel to the Serializer.
0
Reserved
7:1
0x00 ID[0] Match 7-bit Remote Slave Device Alias ID 0
Configures the decoder for detecting transactions
designated for an I2C Slave device attached to the remote
Serializer. The transaction will be remapped to the address
specified in the Slave ID0 register.
A value of 0 in this field disables access to the remote I2C
Slave.
0
Reserved
36
Copyright © 2010–2017, Texas Instruments Incorporated
DS90UH926Q-Q1
www.ti.com.cn
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
Register Maps (continued)
Table 11. Serial Control Bus Registers (continued)
ADD
ADD Register
Bit(s)
Register
Type
Default Function
(hex)
Descriptions
(dec) (hex) Name
17
18
19
20
21
22
23
0x11 SlaveAlias[1]
7:1
RW
RW
RW
RW
RW
RW
0x00 ID[1] Match 7-bit Remote Slave Device Alias ID 1
Configures the decoder for detecting transactions
designated for an I2C Slave device attached to the remote
Serializer. The transaction will be remapped to the address
specified in the Slave ID1 register.
A value of 0 in this field disables access to the remote I2C
Slave.
0
Reserved
0x12 SlaveAlias[2]
0x13 SlaveAlias[3]
0x14 SlaveAlias[4]
0x15 SlaveAlias[5]
0x16 SlaveAlias[6]
0x17 SlaveAlias[7]
7:1
0x00 ID[2] Match 7-bit Remote Slave Device Alias ID 2
Configures the decoder for detecting transactions
designated for an I2C Slave device attached to the remote
Serializer. The transaction will be remapped to the address
specified in the Slave ID2 register.
A value of 0 in this field disables access to the remote I2C
Slave.
0
Reserved
7:1
0x10 ID[3] Match 7-bit Remote Slave Device Alias ID 3
Configures the decoder for detecting transactions
designated for an I2C Slave device attached to the remote
Serializer. The transaction will be remapped to the address
specified in the Slave ID3 register.
A value of 0 in this field disables access to the remote I2C
Slave.
0
Reserved
7:1
0x00 ID[4] Match 7-bit Remote Slave Device Alias ID 4
Configures the decoder for detecting transactions
designated for an I2C Slave device attached to the remote
Serializer. The transaction will be remapped to the address
specified in the Slave ID4 register.
A value of 0 in this field disables access to the remote I2C
Slave.
0
Reserved
7:1
0x00 ID[5] Match 7-bit Remote Slave Device Alias ID 5
Configures the decoder for detecting transactions
designated for an I2C Slave device attached to the remote
Serializer. The transaction will be remapped to the address
specified in the Slave ID5 register.
A value of 0 in this field disables access to the remote I2C
Slave.
0
Reserved
7:1
0x00 ID[6] Match 7-bit Remote Slave Device Alias ID 6
Configures the decoder for detecting transactions
designated for an I2C Slave device attached to the remote
Serializer. The transaction will be remapped to the address
specified in the Slave ID6 register.
A value of 0 in this field disables access to the remote I2C
Slave.
0
RW
RW
Reserved
7:1
0x00 ID[7] Match 7-bit Remote Slave Device Alias ID 7
Configures the decoder for detecting transactions
designated for an I2C Slave device attached to the remote
Serializer. The transaction will be remapped to the address
specified in the Slave ID7 register.
A value of 0 in this field disables access to the remote I2C
Slave.
0
Reserved
Copyright © 2010–2017, Texas Instruments Incorporated
37
DS90UH926Q-Q1
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
www.ti.com.cn
Register Maps (continued)
Table 11. Serial Control Bus Registers (continued)
ADD
ADD Register
Bit(s)
Register
Type
Default Function
(hex)
Descriptions
(dec) (hex) Name
28 0x1C General Status
7:4
3
RW
R
0x00
Reserved
I2S Locked I2S Lock Status
0: I2S PLL controller not locked
1: I2S PLL controller locked to input I2S clock
2
1
Reserved
R
R
Signal
Detect
Signal Detect
1: Serial input detected
0: Serial input not detected
0
Lock
Deserializer CDR, PLL's clock to recovered clock
frequency
1: Deserializer locked to recovered clock
0: Deserializer not locked
29
0x1D GPIO0 Config
7:4
3
R
0xA0 Rev-ID
Revision ID: 1010: Production Device
RW
GPIO0
Output
Value
Local GPIO Output Value
This value is output on the GPIO pin when the GPIO
function is enabled, the local GPIO direction is Output, and
remote GPIO control is disabled.
2
RW
GPIO0
Remote
Enable
Remote GPIO0 Control
1: Enable GPIO control from remote Serializer. The GPIO
pin will be an output, and the value is received from the
remote Deserializer.
0: Disable GPIO control from remote Serializer
1
0
7
RW
RW
RW
GPIO0
Direction
Local GPIO Direction
1: Input
0: Output
GPIO0
Enable
GPIO Function Enable
1: Enable GPIO operation
0: Enable normal operation
30
0x1E GPIO2 and
GPIO1 Config
0x00 GPIO2
Output
Local GPIO Output Value
This value is output on the GPIO when the GPIO function
is enabled, the local GPIO direction is Output, and remote
GPIO control is disabled.
Value
6
RW
GPIO2
Remote
Enable
Remote GPIO2 Control
1: Enable GPIO control from remote Serializer. The GPIO
pin will be an output, and the value is received from the
remote Deserializer.
0: Disable GPIO control from remote Serializer.
5
4
3
RW
RW
RW
GPIO2
Direction
Local GPIO Direction
1: Input
0: Output
GPIO2
Enable
GPIO Function Enable
1: Enable GPIO operation
0: Enable normal operation
GPIO1
Output
Value
Local GPIO Output Value
This value is output on the GPIO when the GPIO function
is enabled, the local GPIO direction is Output, and remote
GPIO control is disabled.
2
RW
GPIO1
Remote
Enable
Remote GPIO1 Control
1: Enable GPIO control from remote Serializer. The GPIO
pin will be an output, and the value is received from the
remote Deserializer.
0: Disable GPIO control from remote Serializer.
1
0
RW
RW
GPIO1
Direction
Local GPIO Direction
1: Input
0: Output
GPIO1
Enable
GPIO Function Enable
1: Enable GPIO operation
0: Enable normal operation
38
Copyright © 2010–2017, Texas Instruments Incorporated
DS90UH926Q-Q1
www.ti.com.cn
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
Register Maps (continued)
Table 11. Serial Control Bus Registers (continued)
ADD
ADD Register
Bit(s)
Register
Type
Default Function
(hex)
Descriptions
(dec) (hex) Name
31
0x1F GPO_REG4
7
RW
0x00 GPO_REG4 Local GPO_REG4 Output Value
and GPO3
Config
Output
Value
This value is output on the GPO when the GPO function is
enabled, the local GPO direction is Output, and remote
GPO control is disabled.
6:5
4
Reserved
RW
RW
RW
GPO_REG4 GPO_REG4 Function Enable
Enable
1: Enable GPO operation
0: Enable normal operation
3
2
GPIO3
Output
Value
Local GPIO Output Value This value is output on the GPIO
when the GPIO function is enabled, the local GPIO
direction is Output, and remote GPIO control is disabled.
GPIO3
Remote
Enable
Remote GPIO3 Control
1: Enable GPIO control from remote Serializer. The GPIO
pin will be an output, and the value is received from the
remote Deserializer.
0: Disable GPIO control from remote Serializer.
1
0
7
RW
RW
RW
GPIO3
Direction
Local GPIO Direction
1: Input
0: Output
GPIO3
Enable
GPIO Function Enable
1: Enable GPIO operation
0: Enable normal operation
32
0x20 GPO_REG6
and
0x00 GPO_REG6 Local GPO_REG6 Output Value
Output
Value
This value is output on the GPO when the GPO function is
enabled, the local GPO direction is Output, and remote
GPO control is disabled.
GPO_REG5
Config
6:5
4
Reserved
RW
RW
GPO_REG6 GPO_REG6 Function Enable
Enable
1: Enable GPO operation
0: Enable normal operation
3
GPO_REG5 Local GPO_REG5 Output Value
Output
Value
This value is output on the GPO when the GPO function is
enabled, the local GPO direction is Output, and remote
GPO control is disabled.
2:1
0
Reserved
RW
RW
GPO_REG5 GPO_REG5 Function Enable
Enable
1: Enable GPO operation
0: Enable normal operation
33
0x21 GPO8 and
GPO7 Config
7
0x00 GPO_REG8 Local GPO_REG8 Output Value
Output
Value
This value is output on the GPO when the GPO function is
enabled, the local GPO direction is Output, and remote
GPO control is disabled.
6:5
4
Reserved
RW
RW
GPO_REG8 GPO_REG8 Function Enable
Enable
1: Enable GPO operation
0: Enable normal operation
3
GPO_REG7 Local GPO_REG7 Output Value
Output
Value
This value is output on the GPO when the GPO function is
enabled, the local GPO direction is Output, and remote
GPO control is disabled.
2:1
0
Reserved
RW
GPO_REG7 GPO_REG7 Function Enable
Enable
1: Enable GPO operation
0: Enable normal operation
Copyright © 2010–2017, Texas Instruments Incorporated
39
DS90UH926Q-Q1
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
www.ti.com.cn
Register Maps (continued)
Table 11. Serial Control Bus Registers (continued)
ADD
ADD Register
Bit(s)
Register
Type
Default Function
(hex)
Descriptions
(dec) (hex) Name
34
0x22 Data Path
Control
7
RW
0x00 Override FC 1: Disable loading of this register from the forward channel,
Config
keeping locally written values intact
0: Allow forward channel loading of this register
6
RW
Pass RGB
Setting this bit causes RGB data to be sent independent of
DE. This allows operation in systems which may not use
DE to frame video data or send other data when DE is
deasserted. Note that setting this bit prevents HDCP
operation and blocks packetized audio. This bit does not
need to be set in DS90UB925 or in Backward Compatible
mode.
1: Pass RGB independent of DE
0: Normal operation
Note: this bit is automatically loaded from the remote
serializer unless bit 7 of this register is set.
5
4
RW
RW
DE Polarity This bit indicates the polarity of the DE (Data Enable)
signal.
1: DE is inverted (active low, idle high)
0: DE is positive (active high, idle low)
Note: this bit is automatically loaded from the remote
serializer unless bit 7 of this register is set.
I2S_Gen
This bit controls whether the HDCP Receiver outputs
packetized Auxiliary/Audio data on the RGB video output
pins.
1: Don't output packetized audio data on RGB video output
pins
0: Output packetized audio on RGB video output pins.
Note: this bit is automatically loaded from the remote
serializer unless bit 7 of this register is set.
3
2
RW
RW
I2S Channel 1: Set I2S Channel B Enable from reg_0x22[0]
B Enable
Override
0: Set I2S Channel B Enable from MODE_SEL pin
Note: this bit is automatically loaded from the remote
serializer unless bit 7 of this register is set.
18-bit Video 1: Select 18-bit video mode
Select
Note: use of GPIO(s) on unused inputs must be enabled
by register.
0: Select 24-bit video mode
Note: this bit is automatically loaded from the remote
serializer unless bit 7 of this register is set.
1
0
RW
RW
I2S
Transport
Select
1: Enable I2S Data Forward Channel Frame Transport
0: Enable I2S Data Island Transport
Note: this bit is automatically loaded from the remote
serializer unless bit 7 of this register is set.
I2S Channel I2S Channel B Enable
B Enable
1: Enable I2S Channel B on B1 output
0: I2S Channel B disabled
Note: this bit is automatically loaded from the remote
serializer unless bit 7 of this register is set.
35
0x23 General
Purpose
7
RW
0x10 Rx RGB
Checksum
RX RGB Checksum Enable Setting this bit enables the
Receiver to validate a one-byte checksum following each
video line. Checksum failures are reported in the
HDCP_STS register
Control
6:5
4
Reserved
Mode Status
R
R
R
R
R
Mode_Sel
LFMODE
Repeater
Backward
Mode Select is Done
3
Low Frequency Mode Status
Repeater Mode Status
Backward Compatible Mode Status
2
1
0
I2S Channel I2S Channel B Status
B
40
Copyright © 2010–2017, Texas Instruments Incorporated
DS90UH926Q-Q1
www.ti.com.cn
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
Register Maps (continued)
Table 11. Serial Control Bus Registers (continued)
ADD
ADD Register
Bit(s)
Register
Type
Default Function
(hex)
Descriptions
(dec) (hex) Name
36
0x24 BIST Control
7:4
3
0x08
Reserved
RW
RW
BIST Pin
Config
BIST Configured through Pin
1: BIST configured through pin
0: BIST configured through register bit
2:1
0
BIST Clock BIST Clock Source
Source
00: External Pixel Clock
01: 33 MHz Oscillator
10: Reserved
11: 25 MHz Oscillator
RW
BIST
Enable
BIST Control
1: Enabled
0: Disabled
37
38
0x25 BIST Error
7:0
7:0
R
0x00 BIST Error
Count
BIST Error Count
0x26 SCL High
Time
RW
0x83 SCL High
Time
I2C Master SCL High Time
This field configures the high pulse width of the SCL output
when the Deserializer is the Master on the local I2C bus.
Units are 50 ns for the nominal oscillator clock frequency.
The default value is set to provide a minimum 5 us SCL
high time with the internal oscillator clock running at 26
MHz rather than the nominal 20 MHz.
39
0x27 SCL Low Time
7:0
RW
0x84 SCL Low
Time
I2C SCL Low Time
This field configures the low pulse width of the SCL output
when the De-Serializer is the Master on the local I2C bus.
This value is also used as the SDA setup time by the I2C
Slave for providing data prior to releasing SCL during
accesses over the Bidirectional Control Channel. Units are
50 ns for the nominal oscillator clock frequency. The
default value is set to provide a minimum 5 us SCL low
time with the internal oscillator clock running at 26 MHz
rather than the nominal 20 MHz.
41
0x29 FRC Control
7
RW
0x00 Timing
Mode
Select display timing mode
0: DE only Mode
Select
1: Sync Mode (VS,HS)
6
5
RW
RW
RW
RW
RW
RW
RW
RW
VS Polarity 0: Active High
1: Active Low
HS Polarity 0: Active High
1: Active Low
4
DE Polarity 0: Active High
1: Active Low
3
FRC2
Enable
0: FRC2 Disable
1: FRC2 Enable
2
FRC1
Enable
0: FRC1 Disable
1: FRC1 Enable
1
Hi-FRC 2
Disable
0: Hi-FRC2 Enable
1: Hi-FRC2 Disable
0
Hi-FRC 1
Disable
0: Hi-FRC1 Enable
1: Hi-FRC1 Disable
42
0x2A White Balance
Control
7:6
0x00 Page
00: Configuration Registers
01: Red LUT
Setting
10: Green LUT
11: Blue LUT
5
RW
RW
White
Balance
Enable
0: White Balance Disable
1: White Balance Enable
4
LUT Reload 0: Reload Disable
Enable
1: Reload Enable
3:0
Reserved
Copyright © 2010–2017, Texas Instruments Incorporated
41
DS90UH926Q-Q1
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
www.ti.com.cn
Register Maps (continued)
Table 11. Serial Control Bus Registers (continued)
ADD
ADD Register
Bit(s)
Register
Type
Default Function
(hex)
Descriptions
(dec) (hex) Name
43
44
0x2B I2S Control
7
RW
0x00 I2S PLL
I2S PLL Control
0: I2S PLL is ON for I2S data jitter cleaning
1: I2S PLL is OFF. No jitter cleaning
6:1
0
Reserved
RW
I2S Clock
Edge
I2S Clock Edge Select
0: I2S Data is strobed on the Rising Clock Edge
1: I2S Data is strobed on the Falling Clock Edge
0x2C SSCG Control
7:4
3
0x00
Reserved
RW
RW
SSCG
Enable
Enable Spread Spectrum Clock Generator
0: Disable
1: Enable
2:0
SSCG
Selection
SSCG Frequency Deviation:
When LFMODE = H
fdev fmod
000: ±0.7 CLK / 628
001: ±1.3
010: ±1.8
011: ±2.5
100: ±0.7 CLK / 388
101: ±1.2
110: ±2.0
111: ±2.5
When LFMODE = L
fdev fmod
000: ±0.9 CLK / 2168
001: ±1.2
010: ±1.9
011: ±2.5
100: ±0.7 CLK / 1300
101: ±1.3
110: ±2.0
111: ±2.5
58
65
0x3A I2S DIVSEL
7
RW
RW
0x00 MCLK Div
Override
0: No override for MCLK divider (default)
1: Override divider select for MCLK
6:4
3:0
7:5
4
MCLK Div
See Table 5
Reserved
Reserved
0x41 Link Error
Count
0x03
RW
RW
Link Error
Count
Enable
Enable serial link data integrity error count
1: Enable error count
0: Disable
3:0
Link Error
Count
Link error count threshold.
Counter is pixel clock based. clk0, clk1 and DCA are
monitored for link errors, if error count is enabled,
deserializer loose lock once error count reaches threshold.
If disabled deserilizer loose lock with one error.
42
Copyright © 2010–2017, Texas Instruments Incorporated
DS90UH926Q-Q1
www.ti.com.cn
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
Register Maps (continued)
Table 11. Serial Control Bus Registers (continued)
ADD
ADD Register
Bit(s)
Register
Type
Default Function
(hex)
Descriptions
(dec) (hex) Name
68
0x44 Equalization
7:5
RW
0x60 EQ Stage 1 EQ select value.
Select Used if adaptive EQ is bypassed.
000 Min EQ 1st Stage
001
010
011
100
101
110
111 Max EQ 1st Stage
4
Reserved
3:1
RW
EQ Stage 2 EQ select value.
Select
Used if adaptive EQ is bypassed.
000 Min EQ 2nd Stage
001
010
011
100
101
110
111 Max EQ 2nd Stage
0
RW
RW
RW
Adaptive
EQ
1: Disable adaptive EQ (to write EQ select values)
0: Enable adaptive EQ
86
0x56 CML Output
7:4
3
0x08
Reserved
CMLOUT+/- 1: Disabled (Default)
Enable
0: Enabled
2:0
7:4
Reserved
100
0x64 Pattern
Generator
Control
0x10 Pattern
Generator
Fixed Pattern Select
This field selects the pattern to output when in Fixed
Pattern Mode. Scaled patterns are evenly distributed
across the horizontal or vertical active regions. This field is
ignored when Auto-Scrolling Mode is enabled. The
following table shows the color selections in non-inverted
followed by inverted color mode
Select
0000: Reserved 0001: White/Black
0010: Black/White
0011: Red/Cyan
0100: Green/Magenta
0101: Blue/Yellow
0110: Horizontally Scaled Black to White/White to Black
0111: Horizontally Scaled Black to Red/Cyan to White
1000: Horizontally Scaled Black to Green/Magenta to
White
1001: Horizontally Scaled Black to Blue/Yellow to White
1010: Vertically Scaled Black to White/White to Black
1011: Vertically Scaled Black to Red/Cyan to White
1100: Vertically Scaled Black to Green/Magenta to White
1101: Vertically Scaled Black to Blue/Yellow to White
1110: Custom color (or its inversion) configured in PGRS,
PGGS, PGBS registers
1111: Reserved
3:1
0
Reserved
RW
Pattern
Generator
Enable
Pattern Generator Enable
1: Enable Pattern Generator
0: Disable Pattern Generator
Copyright © 2010–2017, Texas Instruments Incorporated
43
DS90UH926Q-Q1
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
www.ti.com.cn
Register Maps (continued)
Table 11. Serial Control Bus Registers (continued)
ADD
ADD Register
Bit(s)
Register
Type
Default Function
(hex)
Descriptions
(dec) (hex) Name
101
0x65 Pattern
Generator
Configuration
7:5
4
0x00
Reserved
RW
RW
Pattern
Generator
18 Bits
18-bit Mode Select
1: Enable 18-bit color pattern generation. Scaled patterns
will have 64 levels of brightness and the R, G, and B
outputs use the six most significant color bits.
0: Enable 24-bit pattern generation. Scaled patterns use
256 levels of brightness.
3
2
Pattern
Generator
External
Clock
Select External Clock Source
1: Selects the external pixel clock when using internal
timing.
0: Selects the internal divided clock when using internal
timing
This bit has no effect in external timing mode
(PATGEN_TSEL = 0).
RW
Pattern
Generator
Timing
Timing Select Control
1: The Pattern Generator creates its own video timing as
configured in the Pattern Generator Total Frame Size,
Active Frame Size. Horizontal Sync Width, Vertical Sync
Width, Horizontal Back Porch, Vertical Back Porch, and
Sync Configuration registers.
Select
0: the Pattern Generator uses external video timing from
the pixel clock, Data Enable, Horizontal Sync, and Vertical
Sync signals.
1
0
RW
RW
Pattern
Generator
Enable Inverted Color Patterns
1: Invert the color output.
Color Invert 0: Do not invert the color output.
Pattern
Auto-Scroll Enable:
Generator
1: The Pattern Generator will automatically move to the
Auto-Scroll next enabled pattern after the number of frames specified
Enable
in the Pattern Generator Frame Time (PGFT) register.
0: The Pattern Generator retains the current pattern.
102
103
0x66 Pattern
7:0
7:0
RW
RW
0x00 Indirect
Address
This 8-bit field sets the indirect address for accesses to
indirectly-mapped registers. It should be written prior to
reading or writing the Pattern Generator Indirect Data
register.
See AN-2198 Exploring Int Test Patt Gen Feat of 720p
FPD-Link III Devices (SNLA132)
Generator
Indirect
Address
0x67 Pattern
0x00 Indirect
Data
When writing to indirect registers, this register contains the
data to be written. When reading from indirect registers,
this register contains the read back value.
Generator
Indirect Data
See AN-2198 Exploring Int Test Patt Gen Feat of 720p
FPD-Link III Devices (SNLA132)
128
129
130
131
132
144
145
146
147
148
0x80 RX_BKSV0
0x81 RX_BKSV1
0x82 RX_BKSV2
0x83 RX_BKSV3
0x84 RX_BKSV4
0x90 TX_KSV0
0x91 TX_KSV1
0x92 TX_KSV2
0x93 TX_KSV3
0x94 TX_KSV4
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
R
R
R
R
R
R
R
R
R
R
0x00 RX BKSV0 BKSV0: Value of byte 0 of the Deserializer KSV
0x00 RX BKSV1 BKSV1: Value of byte 1 of the Deserializer KSV
0x00 RX BKSV2 BKSV2: Value of byte 2 of the Deserializer KSV
0x00 RX BKSV3 BKSV3: Value of byte 3 of the Deserializer KSV.
0x00 RX BKSV4 BKSV4: Value of byte 4 of the Deserializer KSV.
0x00 TX KSV0
0x00 TX KSV1
0x00 TX KSV2
0x00 TX KSV3
0x00 TX KSV4
KSV0: Value of byte 0 of the Serializer KSV.
KSV1: Value of byte 1 of the Serializer KSV.
KSV2: Value of byte 2 of the Serializer KSV.
KSV3: Value of byte 3 of the Serializer KSV.
KSV4: Value of byte 4 of the Serializer KSV.
44
Copyright © 2010–2017, Texas Instruments Incorporated
DS90UH926Q-Q1
www.ti.com.cn
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
Register Maps (continued)
Table 11. Serial Control Bus Registers (continued)
ADD
ADD Register
Bit(s)
Register
Type
Default Function
(hex)
Descriptions
(dec) (hex) Name
192
0xC0 HDCP_DBG
7:4
3
0x00
Reserved
RGB_CHK Enable RBG video line checksum.
R
R
SUM_EN
1: Enables sending of ones-complement checksum for
each 8-bit RBG data channel following end of each video
data line.
0: Checksum disabled
Set via the HDCP_DBG register in the HDCP Transmitter.
2
FC_TEST
MODE
Frame Counter Testmode:
1: Speeds up frame counter used for Pj and Ri verification.
When set to a 1, Pj is computed every 2 frames and Ri is
computed every 16 frames.
0: Pj is computed every 16 frames and Ri is computed
every 128 frames.
Set via the HDCP_DBG register in the HDCP Transmitter.
1
0
R
R
TMR_
SPEEDUP
Timer Speedup:
1: Speed up HDCP authentication timers.
0: Standard authentication timing
Set via the HDCP_DBG register in the HDCP Transmitter.
HDCP_I2C HDCP I2C Fast mode Enable:
_FAST
1: Enable the HDCP I2C Master in the HDCP Receiver to
operation with Fast mode timing.
0:Tthe I2C Master will operate with Standard mode timing.
Set via the HDCP_DBG register in the HDCP Transmitter.
193
0xC1 HDCP_DBG2
7:2
1
0x00
Reserved
RW
NO_
No Decrypt:
DECRYPT
1: The HDCP Receiver outputs the encrypted data on the
RGB pins. All other functions will work normally. This
provides a simple way of showing that the link is
encrypted.
0: Normal Operation
0
7:2
1
Reserved
Reserved
196
0xC4 HDCP Status
0x00
R
R
RGB_CHK RGB Checksum Error Detected:
SUM_ERR If RGB Checksum in enabled through the HDCP
Transmitter HDCP_DBG register, this bit will indicate if a
checksum error is detected. This register may be cleared
by writing any value to this register.
0
HDCP
Status
HDCP Authenticated:
Indicates the HDCP authentication has completed
successfully. The controller may now send video data
requiring content protection. This bit will be cleared if
authentication is lost or if the controller restarts
authentication.
224
225
226
0xE0 RPTR TX0
0xE1 RPTR TX1
0xE2 RPTR TX2
7:1
0
R
R
0x0
HDCP
Serializer
Port 0
Serializer Port 0 I2C Address:
Indicates the I2C address for the Repeater Serializer Port.
Serializer Port 0 Valid:
Indicates that the HDCP Repeater has a Serializer port at
the I2C Address identified by upper 7 bits of this register.
Address
7:1
0
R
R
0x00 HDCP
Serializer
Serializer Port 1 I2C Address: Indicates the I2C address
for the Repeater Serializer Port.
Port 1
Address
Serializer Port 1 Valid: Indicates that the HDCP Repeater
has a Serializer port at the I2C Address identified by upper
7 bits of this register.
7:1
0
0x00 HDCP
Serializer
Port 2
Serializer Port 2 I2C Address: Indicates the I2C address
for the Repeater Serializer Port.
R
Serializer Port 2 Valid: Indicates that the HDCP Repeater
has a Serializer port at the I2C Address identified by upper
7 bits of this register.
Address
Copyright © 2010–2017, Texas Instruments Incorporated
45
DS90UH926Q-Q1
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
www.ti.com.cn
Register Maps (continued)
Table 11. Serial Control Bus Registers (continued)
ADD
ADD Register
Bit(s)
7:1
0
Register
Type
Default Function
(hex)
Descriptions
(dec) (hex) Name
227
0xE3 RPTR TX3
R
0x00 HDCP
Serializer
Port 3
Serializer Port 3 I2C Address: Indicates the I2C address
for the Repeater Serializer Port.
R
Serializer Port 3 Valid: Indicates that the HDCP Repeater
has a Serializer port at the I2C Address identified by upper
7 bits of this register
Address
240
241
242
0xF0 HDCP RX ID
7:0
7:0
7:0
R
R
R
0x5F ID0
0x55 ID1
0x48 ID2
First byte ID code: _
0xF1
0xF2
Second byte of ID code: U
Third byte of ID code, Value will be either ‘B’ or ‘H’. ‘H’
indicates an HDCP capable device.
243
244
245
0xF3
0xF4
0xF5
7:0
7:0
7:0
R
R
R
0x39 ID3
0x32 ID4
0x36 ID5
Fourth byte of ID code: 9
Fifth byte of ID code: 2
Sixth byte of ID code: 6
46
Copyright © 2010–2017, Texas Instruments Incorporated
DS90UH926Q-Q1
www.ti.com.cn
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DS90UH926Q-Q1, in conjunction with the DS90UH925Q-Q1, is intended for interface between a HDCP
compliant host (graphics processor) and a Display. It supports an 24-bit color depth (RGB888) and high definition
(720p) digital video format. It allows to receive a three 8-bit RGB stream with a pixel rate up to 85 MHz together
with three control bits (VS, HS and DE) and three I2S-bus audio stream with an audio sampling rate up to 192
kHz. The included HDCP 1.3 compliant cipher block allows the authentication of the DS90UH926Q, which
decrypts both video and audio contents. The keys are pre-loaded by TI into non-volatile memory (NVM) for
maximum security.
8.1.1 Display Application
The deserializer is expected to be located close to its target device. The interconnect between the deserializer
and the target device is typically in the 1-inch to 3-inch separation range. The input capacitance of the target
device is expected to be in the 5-pF to 10-pF range. Take care of the PCLK output trace as this signal is edge-
sensitive and strobes the data. It is also assumed that the fanout of the deserializer is up to three in the repeater
mode. If additional loads need to be driven, a logic buffer or mux device is recommended.
8.2 Typical Application
Figure 24 shows a typical application of the DS90UH926Q-Q1 deserializer for an 85 MHz 24-bit color display
application. Inputs utilize 0.1-μF coupling capacitors to the line and the deserializer provides internal termination.
Bypass capacitors are placed near the power supply pins. At a minimum, seven 0.1-μF capacitors and two 4.7-
μF capacitors should be used for local device bypassing. Ferrite beads are placed on the power lines for effective
noise suppression. Because the device in the Pin/STRAP mode, two 10 kΩ pull-up resistors are used on the
parallel output bus to select the desired device features.
The interface to the target display is with 3.3-V LVCMOS levels, thus the VDDIO pins are connected to the 3.3-V
rail. A delay cap is placed on the PDB signal to delay the enabling of the device until power is stable.
Copyright © 2010–2017, Texas Instruments Incorporated
47
DS90UH926Q-Q1
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
www.ti.com.cn
Typical Application (continued)
3.3V/1.8V
DS90UH926Q-Q1
3.3V
VDDIO
VDD33_A
C6
FB2
FB1
C4
C5
VDDIO
VDD33_B
C7
C8
VDDIO
CAPP12
C9
CAPR12
C13
CAPI2S
PASS
LOCK
C10
R7
CAPL12
R6
R5
R4
R3
R2
R1
C12
C11
C1
C2
Serial
FPD-Link III
Interface
RIN+
RIN-
R0
CMF
G7
G6
G5
C3
CMLOUTP
CMLOUTN
G4
G3
G2
G1
G0
VDD33_B*
R
5
LVCMOS
Parallel
Video / Audio
Interface
OSS_SEL
OEN
BISTEN
B7
B6
B5
B4
B3
B2
B1
B0
Host Control
BISTC / INTB_IN
PDB
C14
VDD33_B
HS
VS
DE
VDD33_B
SDA
SCL
PCLK
R
1
R
2
FB1 œ FB2: Impedance = 1 kW @ 100 MHz,
Low DC resistance (<1W)
C1 œ C3 = 0.1 mF (50 WV; C1, C2: 0402; C3: 0603)
C4 œ C13 = 4.7 mF
I2S_CLK
ID[X]
I2S_WC
I2S_DA
MCLK
VDD33_B
C14 =>10 mF
R
3
4
NC
RES
R
1
R
3
R
5
and R (see IDx Resistor Values Table 8)
2
2
MODE_SEL
and R (see MODE_SEL Resistor Values Table 4)
4
DAP (GND)
R
= 10 kW
* or VDDIO = 3.3V+0.3V
Figure 24. Typical Connection Diagram
48
Copyright © 2010–2017, Texas Instruments Incorporated
DS90UH926Q-Q1
www.ti.com.cn
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
Typical Application (continued)
V
DD33
V
DDIO
V
DDIO
V
DD33
(1.8V or3.3V)
(3.3V) (1.8V or3.3V)
(3.3V)
R[7:0]
G[7:0]
R[7:0]
G[7:0]
FPD-Link III
1 Pair /AC Coupled
B[7:0]
B[7:0]
0.1 mF
0.1 mF
0.1 mF
0.1 mF
HOST
Graphics
Processor
RGB Display
720p
24-bit color depth
HS
HS
DOUT+
DOUT-
RIN+
RIN-
VS
DE
PCLK
VS
DE
PCLK
100 ohm STP Cable
DS90UH925Q
Serializer
DS90UH926Q
Deserializer
LOCK
PASS
PDB
PDB
OSS_SEL
OEN
MODE_SEL
3
/
I2S AUDIO
(STEREO)
3
/
I2S AUDIO
(STEREO)
MODE_SEL
INTB
INTB_IN
MCLK
SCL
SDA
IDx
SCL
SDA
IDx
DAP
DAP
Figure 25. Typical Display System Diagram
8.2.1 Design Requirements
For the typical design application, use the following as input parameters:
Table 12. Design Parameters
DESIGN PARAMETER
VDDIO
EXAMPLE VALUE
1.8 V or 3.3 V
3.3 V
VDD33
AC-Coupling Capacitor for RIN±
PCLK Frequency
100 nF
78 MHz
8.2.2 Detailed Design Procedure
8.2.2.1 Transmission Media
The DS90UH925Q-Q1 and DS90UH926Q-Q1 chipset is intended to be used in a point-to-point configuration
through a shielded twisted pair cable. The serializer and deserializer provide internal termination to minimize
impedance discontinuities. The interconnect (cable and connector) between the serializer and deserializer should
have a differential impedance of 100 Ω. The maximum length of cable that can be used is dependant on the
quality of the cable (gauge, impedance), connector, board (discontinuities, power plane), the electrical
environment (for example, power stability, ground noise, input clock jitter, PCLK frequency, etc.) and the
application environment.
The resulting signal quality at the receiving end of the transmission media may be assessed by monitoring the
differential eye opening of the serial data stream. The Receiver CML Monitor Driver Output Specifications define
the acceptable data eye opening width and eye opening height. A differential probe should be used to measure
across the termination resistor at the CMLOUT± pin Figure 2.
Copyright © 2010–2017, Texas Instruments Incorporated
49
DS90UH926Q-Q1
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
www.ti.com.cn
8.2.3 Application Curves
Time (100 ps/DIV)
Time (2.5 ns/DIV)
Figure 26. Deserializer CMLOUT Eye Diagram With 78-MHz
TX Pixel Clock
Figure 27. Deserializer FPD-Link III Input With 78-MHz TX
Pixel Clock
9 Power Supply Recommendations
9.1 Power-Up Requirements and PDB Pin
When VDDIO and VDD33_X are powered separately, the VDDIO supply (1.8 V or 3.3 V) ramps up 100 µs before
the other supply (VDD33_X) begins to ramp. If VDDIO is tied with VDD33_X, both supplies may ramp at the
same time. The VDDs (VDD33_X and VDDIO) supply ramp must be faster than 1.5 ms with a monotonic rise.
Use a large capacitor on the PDB pin to ensure PDB arrives after all the VDDs have settled to the recommended
operating voltage. When PDB pin is pulled to VDDIO = 3 V to 3.6 V or VDD33_X, TI recommends using a 10-kΩ
pullup and a > 10-µF cap to GND to delay the PDB input signal.
All inputs must not be driven until VDD33_X and VDDIO has reached its steady-state value.
< 1.5 ms
1.8 V or 3.3 V
VDDIO
100 µs
3.3 V
VDD33_X
< 1.5 ms
3.3 V
PDB
PDB starts to ramp after all supplies have settled
Figure 28. Power-Up Sequence of DS90UH926Q-Q1
50
Copyright © 2010–2017, Texas Instruments Incorporated
DS90UH926Q-Q1
www.ti.com.cn
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
10 Layout
10.1 Layout Guidelines
Design the circuit board layout and stack-up for the FPD-Link III devices to provide low-noise power feed to the
device. Good layout practice also separates high-frequency or high-level inputs and outputs to minimize
unwanted stray noise pickup, feedback, and interference. Power system performance may be greatly improved
by using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane
capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at
high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 µF to 0.1 µF. Tantalum capacitors may be in the 2.2-µF to 10-µF range. Voltage rating of the
tantalum capacitors should be at least 5× the power supply voltage being used.
Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power
entry. This is typically in the 50 µF to 100 µF range and will smooth low-frequency switching noise. TI
recommends connecting the power and ground pins directly to the power and ground planes with bypass
capacitors connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an
external bypass capacitor will increase the inductance of the path.
TI recommends a small body size X7R chip capacitor, such as 0603 or 0402, for external bypass. Its small body
size reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20 to 30 MHz. To provide effective bypassing, multiple
capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At
high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing
the impedance at high frequency.
Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate
switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not
required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power
pin pairs. In some cases, an external filter may be used to provide clean power to sensitive circuits such as
PLLs.
Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the CML
lines to prevent coupling from the LVCMOS lines to the CML lines. Closely-coupled differential lines of 100 Ω are
typically recommended for CML interconnect. The closely coupled lines help to ensure that coupled noise will
appear as common-mode and thus is rejected by the receivers. The tightly coupled lines will also radiate less.
Information on the WQFN style package is provided in AN-1187 Leadless Leadframe Package (LLP)
(SNOA401).
Stencil parameters such as aperture area ratio and the fabrication process have a significant impact on paste
deposition. Inspection of the stencil prior to placement of the WQFN package is highly recommended to improve
board assembly yields. If the via and aperture openings are not carefully monitored, the solder may flow
unevenly through the DAP. Stencil parameters for aperture opening and via locations are shown in Table 13:
Table 13. No Pullback WQFN Stencil Aperture Summary
DEVICE
PIN
COUNT
MKT Dwg
PCB I/O
Pad Size
(mm)
PCB PITCH PCB DAP SIZE
STENCIL I/O
APERTURE (mm)
STENCIL DAP
Aperture (mm)
NUMBER of DAP
APERTURE
OPENINGS
(mm)
(mm)
DS90UH926Q-Q1
60
NKB0060B
0.25 × 0.6
0.5
6.3 × 6.3
0.25 × 0.8
6.3 × 6.3
1
Figure 29 shows the PCB layout example derived from the layout design of the DS90UH926QSEVB Evaluation
Board. The graphic and layout description are used to determine both proper routing and proper solder
techniques when designing the Serializer board.
Copyright © 2010–2017, Texas Instruments Incorporated
51
DS90UH926Q-Q1
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
www.ti.com.cn
10.1.1 CML Interconnect Guidelines
See AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines (SNLA008) and AN-905 Transmission
Line RAPIDESIGNER® Operation and Applications Guide (SNLA035) for full details.
•
•
Use 100-Ω coupled differential pairs
Use the S/2S/3S rule in spacings
–
–
–
S = space between the pair
2S = space between pairs
3S = space to LVCMOS signal
•
•
•
•
Minimize the number of Vias
Use differential connectors when operating above 500 Mbps line speed
Maintain balance of the traces
Minimize skew within the pair
Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the TI
web site at: www.ti.com/lvds.
52
Copyright © 2010–2017, Texas Instruments Incorporated
DS90UH926Q-Q1
www.ti.com.cn
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
10.2 Layout Examples
Length-Matched RGB
Output Traces
AC Capacitors
High-Speed Traces
Figure 29. DS90UH926Q-Q1 Deserializer Example Layout
Figure 30. 60-Pin WQFN Stencil Example of Via and Opening Placement
版权 © 2010–2017, Texas Instruments Incorporated
53
DS90UH926Q-Q1
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
www.ti.com.cn
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
•
•
•
•
《探索 AN-2198 720p FPD-Link III 器件的内部测试图案生成特性》(SNLA132)
《AN-1187 无引线框架封装 (LLP)》(SNOA401)
《AN-1108 通道链路 PCB 和互连设计指南》(SNLA008)
《AN-905 传输线路 RAPIDESIGNER® 操作和 应用 指南》(SNLA035)
11.2 接收文档更新通知
要接收文档更新通知，请导航至德州仪器 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每
周接收产品信息更改摘要。有关更改的详细信息，请查看任意已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包括机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据发生变化时，我们可能不
会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航栏。
54
版权 © 2010–2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
20-Jun-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS90UH926QSQ/NOPB
DS90UH926QSQE/NOPB
DS90UH926QSQX/NOPB
ACTIVE
ACTIVE
ACTIVE
WQFN
WQFN
WQFN
NKB
NKB
NKB
60
60
60
1000 RoHS & Green
250 RoHS & Green
2000 RoHS & Green
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 105
-40 to 105
-40 to 105
UH926QSQ
Samples
Samples
Samples
SN
SN
UH926QSQ
UH926QSQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
20-Jun-2022
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS90UH926QSQ/NOPB WQFN
DS90UH926QSQE/NOPB WQFN
DS90UH926QSQX/NOPB WQFN
NKB
NKB
NKB
60
60
60
1000
250
330.0
178.0
330.0
16.4
16.4
16.4
9.3
9.3
9.3
9.3
9.3
9.3
1.3
1.3
1.3
12.0
12.0
12.0
16.0
16.0
16.0
Q1
Q1
Q1
2000
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS90UH926QSQ/NOPB
DS90UH926QSQE/NOPB
DS90UH926QSQX/NOPB
WQFN
WQFN
WQFN
NKB
NKB
NKB
60
60
60
1000
250
356.0
208.0
356.0
356.0
191.0
356.0
35.0
35.0
35.0
2000
Pack Materials-Page 2
PACKAGE OUTLINE
NKB0060B
VQFN - 0.8 mm max height
S
C
A
L
E
1
.
5
0
0
PLASTIC QUAD FLATPACK - NO LEAD
9.1
8.9
A
B
PIN 1 INDEX AREA
9.1
8.9
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
2X 7
6.3 0.1
SYMM
EXPOSED
THERMAL PAD
(0.1) TYP
16
30
15
31
SYMM
61
2X 7
1
0.3
60X
45
0.2
56X 0.5
60
46
0.1
C A B
0.7
0.5
PIN 1 ID
0.05
60X
4214995/A 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
NKB0060B
VQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
6.3)
SYMM
SEE SOLDER MASK
DETAIL
60X (0.8)
60X (0.25)
46
60
1
45
56X (0.5)
(1.1) TYP
(1.2) TYP
SYMM
(R0.05) TYP
(
0.2) TYP
VIA
61
(0.6) TYP
(8.6)
15
31
30
16
(0.6) TYP
(1.2) TYP
(1.1) TYP
(8.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 8X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214995/A 03/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
NKB0060B
VQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
25X ( 1)
(1.2) TYP
46
60X (0.8)
60X (0.25)
60
1
45
56X (0.5)
(R0.05) TYP
(1.2) TYP
(8.6)
61
SYMM
15
31
16
30
SYMM
(8.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 8X
EXPOSED PAD 61
63% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4214995/A 03/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明