DS90UR905QSQXNOPB [TI]
LINE DRIVER, QCC48, 7 X 7 MM, 0.80 MM HEIGHT, 0.50 MM PITCH, LLP-48;
| 型号： | DS90UR905QSQXNOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LINE DRIVER, QCC48, 7 X 7 MM, 0.80 MM HEIGHT, 0.50 MM PITCH, LLP-48 驱动 接口集成电路 驱动器 |
| 文件： | 总54页 (文件大小：1078K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS90UR905Q, DS90UR906Q
www.ti.com
SNLS313G –SEPTEMBER 2009–REVISED APRIL 2013
DS90UR905Q/DS90UR906Q 5 - 65 MHz 24-bit Color FPD-Link II Serializer and Deserializer
Check for Samples: DS90UR905Q, DS90UR906Q
1
FEATURES
DESCRIPTION
The DS90UR905Q/906Q chipset translates a parallel
RGB Video Interface into a high-speed serialized
interface over a single pair. This serial bus scheme
greatly eases system design by eliminating skew
problems between clock and data, reduces the
number of connector pins, reduces the interconnect
size, weight, and cost, and overall eases PCB layout.
In addition, internal DC balanced decoding is used to
support AC-coupled interconnects.
2
•
5 – 65 MHz PCLK Support (140 Mbps – 1.82
Gbps)
•
AC Coupled STP Interconnect Cable up to 10
Meters
•
•
•
•
•
Integrated Terminations on Ser and Des
@ Speed Link BIST Mode and Reporting Pin
Optional I2C Compatible Serial Control Bus
RGB888 + VS, HS, DE Support
The DS90UR905Q Ser (serializer) embeds the clock,
balances the data payload, and level shifts the
signals to high-speed low voltage differential
signaling. Up to 24 inputs are serialized along with
the three video control signals. This supports full 24-
bit color or 18-bit color and 6 general purpose signals
(e.g. Audio I2S) applications.
Power Down Mode Minimizes Power
Dissipation
•
•
1.8V or 3.3V Compatible LVCMOS I/O Interface
Automotive Grade Product: AEC-Q100 Grade 2
Qualified
•
•
>8 kV HBM and ISO 10605 ESD Rating
The DS90UR906Q Des (deserializer) recovers the
data (RGB) and control signals and extracts the clock
from the serial stream. It is able to lock to the
incoming data stream without the use of a training
sequence or special SYNC patterns, and does not
require a reference clock. A link status (LOCK) output
signal is provided.
Backward Compatible Mode for Operation with
Older Generation Devices
SERIALIZER — DS90UR905Q
•
•
•
RGB888 + VS/HS/DE Serialized to 1 Pair FPD-
Link II
Randomizer/Scrambler — DC-Balanced Data
Stream
Serial transmission is optimized by a user selectable
de-emphasis, differential output level select features,
and receiver equalization. EMI is minimized by the
use of low voltage differential signaling, receiver drive
strength control, and spread spectrum clocking
compatibility. The Des may be configured to generate
Spread Spectrum Clock and Data on its parallel
outputs.
Selectable Output VOD and Adjustable De-
Emphasis
DESERIALIZER — DS90UR906Q
•
FAST Random Data Lock; No Reference Clock
Required
•
•
•
Adjustable Input Receiver Equalization
The DS90UR905Q (Ser) is offered in a 48-pin WQFN
and the DS90UR906Q (Des) is offered in a 60-pin
WQFN package. They are specified over the
automotive AEC-Q100 grade 2 temperature range of
-40°C to +105°C.
LOCK (Real Time Link Status) Reporting Pin
EMI Minimization on Output Parallel Bus
(SSCG)
•
Output Slew Control (OS)
APPLICATIONS
•
•
Automotive Display for Navigation
Automotive Display for Entertainment
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2013, Texas Instruments Incorporated
DS90UR905Q, DS90UR906Q
SNLS313G –SEPTEMBER 2009–REVISED APRIL 2013
www.ti.com
Applications Diagram
V
V
DDn
1.8V
V
V
DDIO
DDIO
(1.8Vor3.3V)
DDn
1.8V (1.8Vor3.3V)
R[7:0]
G[7:0]
R[7:0]
G[7:0]
FPD-Link II
1 Pair /AC Coupled
B[7:0]
B[7:0]
HS
VS
DE
PCLK
100 nF
100 nF
HOST
Graphics
Processor
RGB Display
QVGA to XGA
24-bit color depth
HS
DOUT+
DOUT-
RIN+
RIN-
VS
DE
PCLK
100 ohm STP Cable
CMF
PDB
DS90UR905Q
Serializer
DS90UR906Q
Deserializer
LOCK
PASS
PDB
CONFIG [1:0]
RFB
BISTEN
BISTEN
STRAP pins
not shown
VODSEL
DeEmph
SCL
SDA
ID[x]
SCL
SDA
ID[x]
Optional
Optional
DAP
DAP
Block Diagrams
VODSEL
De-Emph
24
RGB[7:0]
HS
VS
DE
DOUT+
DOUT-
RFB
Pattern
Generator
PCLK
PLL
CONFIG[1:0]
PDB
Timing and
Control
SCL
SCA
ID[x]
BISTEN
DS90UR905Q œ SERIALIZER
2
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SNLS313G –SEPTEMBER 2009–REVISED APRIL 2013
STRAP INPUT
SSCG
CONFIG [1:0]
LF_MODE
CMF
OS_PCLK/DATA
OSS_SEL
RFB
24
RGB [7:0]
HS
VS
DE
EQ [3:0]
RIN+
RIN-
OSC_SEL [2:0]
SSC [3:0]
MAPSEL [1:0]
STRAP INPUT
OP_LOW
Error
Detector
PASS
BISTEN
PDB
SCL
SCA
ID[x]
Clock and
Data
Recovery
PCLK
LOCK
Timing and
Control
DS90UR906Q œ DESERIALIZER
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SNLS313G –SEPTEMBER 2009–REVISED APRIL 2013
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DS90UR905Q Pin Diagram
G[2]
G[3]
G[4]
G[5]
G[6]
G[7]
B[0]
B[1]
B[2]
B[3]
B[4]
B[5]
VODSEL
De-Emph
VDDTX
PDB
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
DOUT+
DOUT-
RES2
DS90UR905Q
TOP VIEW
DAP = GND
VDDHS
RES1
RES0
VDDP
CONFIG[1]
Serializer - DS90UR905Q
48 Pin WQFN Package (Top View)
See Package Number RHS0048A
DS90UR905Q Serializer Pin Functions(1)
Pin Name
Pin #
I/O, Type
Description
LVCMOS Parallel Interface
R[7:0]
G[7:0]
B[7:0]
HS
34, 33, 32, 29,
28, 27, 26, 25
I, LVCMOS
w/ pull-down
RED Parallel Interface Data Input Pins
(MSB = 7, LSB = 0)
42, 41, 40, 39,
38, 37, 36, 35
I, LVCMOS
w/ pull-down
GREEN Parallel Interface Data Input Pins
(MSB = 7, LSB = 0)
2, 1, 48, 47, 46,
45, 44, 43
I, LVCMOS
w/ pull-down
BLUE Parallel Interface Data Input Pins
(MSB = 7, LSB = 0)
3
I, LVCMOS
w/ pull-down
Horizontal Sync Input
Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the
Control Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the
minimum transition pulse when the Control Signal Filter is disabled (CONFIG[1:0] =
00). The signal is limited to 2 transitions per 130 PCLKs.
VS
4
I, LVCMOS
w/ pull-down
Vertical Sync Input
Video control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse
width is 130 PCLKs.
(1) NOTE: 1 = HIGH, 0 = LOW.
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Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: DS90UR905Q DS90UR906Q
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SNLS313G –SEPTEMBER 2009–REVISED APRIL 2013
DS90UR905Q Serializer Pin Functions(1) (continued)
Pin Name
Pin #
I/O, Type
Description
DE
5
I, LVCMOS
w/ pull-down
Data Enable Input
Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the
Control Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the
minimum transition pulse when the Control Signal Filter is disabled (CONFIG[1:0] =
00). The signal is limited to 2 transitions per 130 PCLKs.
PCLK
10
I, LVCMOS
w/ pull-down
Pixel Clock Input
Latch edge set by RFB function.
Control and Configuration
PDB
21
I, LVCMOS
w/ pull-down
Power-down Mode Input
PDB = 1, Ser is enabled (normal operation).
Refer to ”POWER UP REQUIREMENTS AND PDB PIN” in the Applications Information
Section.
PDB = 0, Ser is powered down
When the Ser is in the power-down state, the driver outputs (DOUT+/-) are both logic
high, the PLL is shutdown, IDD is minimized. Control Registers are RESET.
VODSEL
De-Emph
RFB
24
23
11
I, LVCMOS
w/ pull-down
Differential Driver Output Voltage Select — Pin or Register Control
VODSEL = 1, LVDS VOD is ±420 mV, 840 mVp-p (typ) — Long Cable / De-E
Applications
VODSEL = 0, LVDS VOD is 280 mV, 560 mVp-p (typ)
I, Analog
w/ pull-up
De-Emphasis Control — Pin or Register Control
De-Emph = open (float) - disabled
To enable De-emphasis, tie a resistor from this pin to GND or control via register.
See Table 4.
I, LVCMOS
w/ pull-down
Pixel Clock Input Latch Edge Select — Pin or Register Control
RFB = 1, parallel interface data and control signals are latched on the rising clock
edge.
RFB = 0, parallel interface data and control signals are latched on the falling clock
edge.
CONFIG[1:0]
13, 12
I, LVCMOS
w/ pull-down
Operating Modes — Pin or Register Control
Determine the DS90UR905’s operating mode and interfacing device.
CONFIG[1:0] = 00: Interfacing to DS90UR906, Control Signal Filter DISABLED
CONFIG[1:0] = 01: Interfacing to DS90UR906, Control Signal Filter ENABLED
CONFIG[1:0] = 10: Interfacing to DS90UR124, DS99R124
CONFIG[1:0] = 11: Interfacing to DS90C124
ID[x]
6
8
I, Analog
Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 13.
SCL
I, LVCMOS
Serial Control Bus Clock Input - Optional
SCL requires an external pull-up resistor to VDDIO
.
SDA
9
I/O, LVCMOS Serial Control Bus Data Input / Output - Optional
Open Drain
SDA requires an external pull-up resistor VDDIO.
BISTEN
31
I, LVCMOS
w/ pull-down
BIST Mode — Optional
BISTEN = 1, BIST is enabled
BISTEN = 0, BIST is disabled
RES[2:0]
18, 16, 15
I, LVCMOS
w/ pull-down
Reserved - tie LOW
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SNLS313G –SEPTEMBER 2009–REVISED APRIL 2013
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DS90UR905Q Serializer Pin Functions(1) (continued)
Pin Name
Pin #
I/O, Type
Description
FPD-Link II Serial Interface
DOUT+
DOUT-
20
19
O, LVDS
O, LVDS
True Output.
The output must be AC Coupled with a 100 nF capacitor.
Inverting Output.
The output must be AC Coupled with a 100 nF capacitor.
Power and Ground(2)
VDDL
7
Power
Power
Power
Power
Power
Ground
Logic Power, 1.8 V ±5%
VDDP
14
17
22
30
PLL Power, 1.8 V ±5%
VDDHS
TX High Speed Logic Power, 1.8 V ±5%
Output Driver Power, 1.8 V ±5%
LVCMOS I/O Power, 1.8 V ±5% OR 3.3 V ±10%
VDDTX
VDDIO
GND
DAP
DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connect to the ground plane (GND) with at least 9 vias.
(2) The VDD (VDDn and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor on
the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
6
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SNLS313G –SEPTEMBER 2009–REVISED APRIL 2013
DS90UR906Q Pin Diagram
NC
RES
NC
46
47
48
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
VDDL
VDDIR
RIN+
G[0]/OSC_SEL[0]
G[1]/OSC_SEL[1]
G[2]/OSC_SEL[2]
G[3]
49
50
51
52
53
54
55
56
57
58
59
60
RIN-
CMF
CMLOUTP
CMLOUTN
VDDCMLO
VDDR
VDDIO
DS90UR906Q
TOP VIEW
G[4]/EQ[0]
G[5]/EQ[1]
G[6]/EQ[2]
G[7]/EQ[3]
B[0]
DAP = GND
ID[x]
BOLD PIN NAME œ indicates I/O strap
VDDPR
VDDSC
PDB
pin associated with output pin
B[1]/RFB
B[2]/OSS_SEL
NC
NC
Deserializer - DS90UR906Q
60 Pin WQFN Package (Top View)
See Package Number NKB0060B
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SNLS313G –SEPTEMBER 2009–REVISED APRIL 2013
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DS90UR906Q Deserializer Pin Functions(1)
Pin Name
Pin #
I/O, Type
Description
LVCMOS Parallel Interface
R[7:0]
G[7:0]
B[7:0]
HS
33, 34, 35,
I, STRAP,
RED Parallel Interface Data Output Pins (MSB = 7, LSB = 0)
36, 37, 39, O, LVCMOS In power-down (PDB = 0), outputs are controlled by the OSS_SEL (See Table 8). These pins
40, 41
are inputs during power-up (See STRAP Inputs).
20, 21, 22,
I, STRAP,
GREEN Parallel Interface Data Output Pins (MSB = 7, LSB = 0)
23, 25, 26, O, LVCMOS In power-down (PDB = 0), outputs are controlled by the OSS_SEL (See Table 8). These pins
27, 28
are inputs during power-up (See STRAP Inputs).
9, 10, 11,
I, STRAP,
BLUE Parallel Interface Data Output Pins (MSB = 7, LSB = 0)
12, 14, 17, O, LVCMOS In power-down (PDB = 0), outputs are controlled by the OSS_SEL (See Table 8). These pins
18, 19
are inputs during power-up (See STRAP Inputs).
8
O, LVCMOS Horizontal Sync Output
In power-down (PDB = 0), output is controlled by the OSS_SEL pin (See Table 8). Video
control signal pulse width must be 3 PCLKs or longer to be transmitted when the Control
Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition
pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00). The signal is limited to 2
transitions per 130 PCLKs.
VS
DE
7
6
O, LVCMOS Vertical Sync Output
In power-down (PDB = 0), output is controlled by the OSS_SEL pin (See Table 8). Video
control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse width is 130
PCLKs.
O, LVCMOS Data Enable Output
In power-down (PDB = 0), output is controlled by the OSS_SEL pin (See Table 8). Video
control signal pulse width must be 3 PCLKs or longer to be transmitted when the Control
Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition
pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00). The signal is limited to 2
transitions per 130 PCLKs.
PCLK
LOCK
5
O, LVCMOS Pixel Clock Output
In power-down (PDB = 0), output is controlled by the OSS_SEL pin (See Table 8). Strobe
edge set by RFB function.
32
O, LVCMOS LOCK Status Output
LOCK = 1, PLL is Locked, outputs are active LOCK = 0, PLL is unlocked, RGB[7:0], HS, VS,
DE and PCLK output states are controlled by OSS_SEL (See Table 8). May be used as Link
Status or to flag when Video Data is active (ON/OFF).
PASS
42
O, LVCMOS PASS Output (BIST Mode)
PASS = 1, error free transmission
PASS = 0, one or more errors were detected in the received payload
Route to test point for monitoring, or leave open if unused.
Control and Configuration — STRAP PINS
For a High State, use a 10 kΩ pull up to VDDIO; for a Low State, the IO includes an internal pull down. The STRAP pins are read upon
power-up and set device configuration. Pin Number listed along with shared RGB Output name in square brackets.
CONFIG[1:0]
10 [B6],
9 [B7]
STRAP
Operating Modes — Pin or Register Control
I, LVCMOS These pins determine the DS90UR906’s operating mode and interfacing device.
w/ pull-down CONFIG[1:0] = 00: Interfacing to DS90UR905, Control Signal Filter DISABLED
CONFIG[1:0] = 01: Interfacing to DS90UR905, Control Signal Filter ENABLED
CONFIG[1:0] = 10: Interfacing to DS90UR241
CONFIG[1:0] = 11: Interfacing to DS90C241
LF_MODE
12 [B4]
STRAP
SSCG Low Frequency Mode — Pin or Register Control
I, LVCMOS Only required when SSCG is enabled, otherwise LF_MODE condition is a DON’T CARE (X).
w/ pull-down LF_MODE = 1, SSCG in low frequency mode (PCLK = 5-20 MHz)
LF_MODE = 0, SSCG in high frequency mode (PCLK = 20-65 MHz)
OS_PCLK
OS_DATA
11 [B5]
14 [B3]
STRAP
PCLK Output Slew Select — Pin or Register Control
I, LVCMOS OS_PCLK = 1, increased PCLK slew
w/ pull-down OS_PCLK = 0, normal (default)
STRAP
Data Output Slew Select — Pin or Register Control
I, LVCMOS OS_DATA = 1, increased DATA slew
w/ pull-down OS_DATA = 0, normal (default)
(1) NOTE: 1 = HIGH, 0 = LOW.
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SNLS313G –SEPTEMBER 2009–REVISED APRIL 2013
DS90UR906Q Deserializer Pin Functions(1) (continued)
Pin Name
Pin #
I/O, Type
Description
OP_LOW
42 PASS
STRAP
Outputs held Low when LOCK = 1 — Pin or Register Control
I, LVCMOS NOTE: IT IS NOT RECOMMENDED TO USE ANY OTHER STRAP OPTIONS WITH THIS
w/ pull-down STRAP FUNCTION
OP_LOW = 1: all outputs are held LOW during power up until released by programming
OP_LOW release/set register HIGH
NOTE: Before the device is powered up, the outputs are in tri-state.
See Figure 26 and Figure 27.
OP_LOW = 0: all outputs toggle normally as soon as LOCK goes HIGH (default).
OSS_SEL
17 [B2]
18 [B1]
STRAP
Output Sleep State Select — Pin or Register Control
I, LVCMOS NOTE: OSS_SEL STRAP CANNOT BE USED IF OP_LOW =1
w/ pull-down OSS_SEL is used in conjunction with PDB to determine the state of the outputs in Power
Down (Sleep). (See Table 8).
RFB
STRAP
Pixel Clock Output Strobe Edge Select — Pin or Register Control
I, LVCMOS RFB = 1, parallel interface data and control signals are strobed on the rising clock edge.
w/ pull-down RFB = 0, parallel interface data and control signals are strobed on the falling clock edge.
EQ[3:0]
20 [G7],
21 [G6],
22 [G5],
23 [G4]
STRAP
I, LVCMOS (See Table 5).
w/ pull-down
Receiver Input Equalization — Pin or Register Control
OSC_SEL[2:0]
SSC[3:0]
26 [G2],
27 [G1],
28 [G0]
STRAP
Oscillator Select — Pin or Register Control
I, LVCMOS (See Table 9 and Table 10).
w/ pull-down
34 [R6],
35 [R5],
36 [R4],
37 R[3]
STRAP
Spread Spectrum Clock Generation (SSCG) Range Select — Pin or Register Control
I, LVCMOS (See Table 6 and Table 7).
w/ pull-down
MAP_SEL[1:0]
40 [R1],
41 [R0]
STRAP
Bit Mapping Backward Compatibility / DS90UR241 Options — Pin or Register Control
I, LVCMOS Normal setting to b'00. See (Table 11).
w/ pull-down
Control and Configuration
PDB
59
I, LVCMOS Power Down Mode Input
w/ pull-down PDB = 1, Des is enabled (normal operation).
Refer to “POWER UP REQUIREMENTS AND PDB PIN” in the Applications Information
Section.
PDB = 0, Des is in power-down.
When the Des is in the power-down state, the LVCMOS output state is determined by
Table 8. Control Registers are RESET.
ID[x]
56
3
I, Analog
Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. (See Table 12).
SCL
I, LVCMOS Serial Control Bus Clock Input - Optional
SCL requires an external pull-up resistor to VDDIO
.
SDA
2
I/O, LVCMOS Serial Control Bus Data Input / Output - Optional
Open Drain SDA requires an external pull-up resistor to VDDIO
.
BISTEN
44
I, LVCMOS BIST Enable Input — Optional
w/ pull-down BISTEN = 1, BIST is enabled
BISTEN = 0, BIST is disabled
RES
NC
47
I, LVCMOS Reserved - tie LOW
w/ pull-down
1, 15, 16,
30, 31, 45,
46, 60
Not Connected
Leave pin open (float)
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DS90UR906Q Deserializer Pin Functions(1) (continued)
Pin Name
Pin #
I/O, Type
Description
FPD-Link II Serial Interface
RIN+
RIN-
CMF
49
50
51
I, LVDS
I, LVDS
I, Analog
True Input. The input must be AC Coupled with a 100 nF capacitor.
Inverting Input. The input must be AC Coupled with a 100 nF capacitor.
Common-Mode Filter
VCM center-tap is a virtual ground which may be ac-coupled to ground to increase receiver
common mode noise immunity. Recommended value is 0.1μF or higher.
CMLOUTP
CMLOUTN
52
53
O, LVDS
O, LVDS
Test Monitor Pin — EQ Waveform
NC or connect to test point. Requires Serial Bus Control to enable.
Test Monitor Pin — EQ Waveform
NC or connect to test point. Requires Serial Bus Control to enable.
Power and Ground(2)
VDDL
29
Power
Power
Power
Power
Power
Power
Power
Ground
Logic Power, 1.8 V ±5%
VDDIR
VDDR
48
43, 55
4, 58
57
Input Power, 1.8 V ±5%
RX High Speed Logic Power, 1.8 V ±5%
SSCG Power, 1.8 V ±5%
VDDSC
VDDPR
VDDCMLO
VDDIO
GND
PLL Power, 1.8 V ±5%
54
RX High Speed Logic Power, 1.8 V ±5%
13, 24, 38
DAP
LVCMOS I/O Power, 1.8 V ±5% OR 3.3 V ±10% (VDDIO)
DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connected to the ground plane (GND) with at least 9 vias.
(2) The VDD (VDDn and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor on
the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
10
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SNLS313G –SEPTEMBER 2009–REVISED APRIL 2013
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)(3)
Supply Voltage – VDDn (1.8V)
Supply Voltage – VDDIO
LVCMOS I/O Voltage
Receiver Input Voltage
Driver Output Voltage
Junction Temperature
Storage Temperature
−0.3V to +2.5V
−0.3V to +4.0V
−0.3V to +(VDDIO + 0.3V)
−0.3V to (VDD + 0.3V)
−0.3V to (VDD + 0.3V)
+150°C
−65°C to +150°C
215mW
Maximum Power Dissipation Capacity at 25°C
Derate above 25°C
1/θJA mW / °C
27.1 °C/W
4.5 °C/W
48L RHS Package
60L NKB Package
θJA (based on 9 thermal vias)
θJC (based on 9 thermal vias)
Maximum Power Dissipation Capacity at 25°C
Derate above 25C
470mW
1/θJA mW / °C
24.6 °C/W
2.8 °C/W
θJA (based on 9 thermal vias)
θJC (based on 9 thermal vias)
ESD Rating (HBM)
ESD Rating (CDM)
ESD Rating (MM)
≥±8 kV
≥±1 kV
≥±250 V
Air Discharge (DOUT+, DOUT−
Contact Discharge (DOUT+, DOUT−
Air Discharge (RIN+, RIN−
Contact Discharge (RIN+, RIN−
Air Discharge (DOUT+, DOUT−
Contact Discharge (DOUT+, DOUT−
Air Discharge (RIN+, RIN−
Contact Discharge (RIN+, RIN−
Air Discharge (DOUT+, DOUT−
Contact Discharge (DOUT+, DOUT−
Air Discharge (RIN+, RIN−
Contact Discharge (RIN+, RIN−
)
≥±30 kV
ESD Rating (ISO10605), RD = 2kΩ, CS
150pF or RD = 2kΩ, CS = 330pF or RD = 330Ω,
CS = 150pF
=
)
)
)
≥±10 kV
)
≥±30 kV
)
≥±10 kV
)
≥±15 kV
≥±10 kV
ESD Rating (ISO10605), RD = 330Ω, CS
330pF
=
)
≥±15 kV
)
≥±10 kV
)
≥±25 kV
≥±8 kV
ESD Rating (IEC 61000-4-2), RD = 330Ω, CS
150pF
=
)
≥±25 kV
)
≥±8 kV
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) For soldering specifications see product folder at www.ti.com and http://www.ti.com/lit/an/snoa549c/snoa549c.pdf
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Recommended Operating Conditions
Min
1.71
1.71
3.0
Nom
1.8
Max
1.89
1.89
3.6
Units
Supply Voltage (VDDn
LVCMOS Supply Voltage (VDDIO
OR LVCMOS Supply Voltage (VDDIO
)
)
1.8
V
)
3.3
Operating Free Air Temperature (TA)
PCLK Clock Frequency
Supply Noise(1)
−40
5
+25
+105
65
°C
MHz
mVP-P
50
(1) Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC coupled to the VDDn (1.8V) supply with
amplitude = 100 mVp-p measured at the device VDDn pins. Bit error rate testing of input to the Ser and output of the Des with 10 meter
cable shows no error when the noise frequency on the Ser is less than 750 kHz. The Des on the other hand shows no error when the
noise frequency is less than 400 kHz.
Serializer DC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)
Symbol
Parameter
Conditions
Pin/Freq
Min
Typ
Max
Units
LVCMOS INPUT DC SPECIFICATIONS
VDDIO = 3.0 to 3.6V
VDDIO = 1.71 to 1.89V
2.2
VDDIO
VDDIO
0.8
V
V
V
V
High Level Input
Voltage
VIH
0.65*
VDDIO
R[7:0],
G[7:0],
B[7:0],
HS, VS, DE,
PCLK, PDB,
VODSEL,
RFB,
CONFIG[1:0],BIS
TEN
VDDIO = 3.0 to 3.6V
GND
VIL
Low Level Input Voltage
Input Current
VDDIO = 1.71 to 1.89V
0.35*
VDDIO
GND
VDDIO = 3.0
to 3.6V
-15
-15
±1
±1
+15
+15
μA
μA
IIN
VIN = 0V or VDDIO
VDDIO = 1.7
to 1.89V
LVDS DRIVER DC SPECIFICATIONS
VODSEL = 0
VODSEL = 1
VODSEL = 0
VODSEL = 1
±205
±320
±280
±420
560
±355
±520
Differential Output
VOD
DOUT+, DOUT-
DOUT+, DOUT-
mV
Voltage
RL = 100Ω,
De-emph = disabled,
Figure 2
Differential Output
Voltage
(DOUT+) – (DOUT-)
VODp-p
ΔVOD
VOS
mVp-p
mV
840
1
Output Voltage
Unbalance
RL = 100Ω, De-emph = disabled, VODSEL = L
50
DOUT+, DOUT-
DOUT+, DOUT-
Offset Voltage – Single- RL = 100Ω,
ended
VODSEL = 0
VODSEL = 1
1.65
De-emph = disabled
V
1.575
At TP A & B, Figure 1
Offset Voltage
Unbalance
Single-ended
ΔVOS
RL = 100Ω, De-emph = disabled
1
mV
At TP A & B, Figure 1
Output Short Circuit
Current
DOUT+/- = 0V,
De-emph = disabled
IOS
RT
VODSEL = 0
-36
mA
Internal Termination
Resistor
80
100
120
Ω
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(2) Typical values represent most likely parametric norms at VDD = 3.3V, Ta = +25 degC, and at the Recommended Operating Conditions at
the time of product characterization and are not ensured.
(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
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SNLS313G –SEPTEMBER 2009–REVISED APRIL 2013
Serializer DC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)
Symbol
Parameter
Conditions
Pin/Freq
Min
Typ
Max
Units
mA
SUPPLY CURRENT
Checker Board Pattern,
VDD= 1.89V
VDDIO= 1.89V
VDDIO = 3.6V
VDD= 1.89V
VDDIO= 1.89V
VDDIO = 3.6V
VDD= 1.89V
VDDIO= 1.89V
VDDIO = 3.6V
All VDD pins
VDDIO
75
3
85
5
IDDT1
De-emph = 3KΩ
VODSEL = H, Figure 9
Serializer
Supply Current
(includes load current)
RL = 100Ω, f = 65MHz
IDDIOT1
IDDT2
IDDIOT2
IDDZ
11
65
3
15
75
5
Checker Board Pattern,
De-emph = 6KΩ,
All VDD pins
VDDIO
mA
VODSEL = L, Figure 9
11
40
5
15
1000
10
20
All VDD pins
VDDIO
Serializer
Supply Current Power-
down
PDB = 0V , (All other
LVCMOS Inputs = 0V)
mA
IDDIOZ
10
Deserializer DC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
3.3 V I/O LVCMOS DC SPECIFICATIONS – VDDIO = 3.0 to 3.6V
VIH
VIL
IIN
High Level Input Voltage
Low Level Input Voltage
Input Current
2.2
GND
−15
VDDIO
0.8
V
V
PDB, BISTEN
VIN = 0V or VDDIO
±1
+15
μA
R[7:0], G[7:0],
B[7:0], HS,VS,
DE, PCLK,
IOH = −2 mA,
OS_PCLK/DATA = L
VOH
High Level Output Voltage
2.4
VDDIO
V
LOCK, PASS
R[7:0], G[7:0],
B[7:0], HS, VS,
DE,PCLK,
IOL = +2 mA,
OS_PCLK/DATA = L
VOL
Low Level Output Voltage
Output Short Circuit Current
GND
0.4
V
LOCK, PASS
VDDIO = 3.3V
VOUT = 0V,
OS_PCLK/DATA = L/H
PCLK
36
37
mA
IOS
VDDIO = 3.3V
VOUT = 0V,
OS_PCLK/DATA = L/H
Output Short Circuit Current
TRI-STATE Output Current
Des Outputs
Outputs
mA
uA
PDB = 0V, OSS_SEL =
0V, VOUT = H
IOZ
−15
+15
1.8 V I/O LVCMOS DC SPECIFICATIONS – VDDIO = 1.71 to 1.89V
VIH
VIL
IIN
High Level Input Voltage
Low Level Input Voltage
Input Current
1.235
GND
−15
VDDIO
0.595
+15
V
V
PDB, BISTEN
VIN = 0V or VDDIO
±1
μA
IOH = −2 mA,
OS_PCLK/DATA = L/H
VDDIO
−0.45
R[7:0], G[7:0],
B[7:0], HS, VS,
DE, PCLK,
VOH
VOL
High Level Output Voltage
Low Level Output Voltage
VDDIO
V
V
IOL = +2 mA,
OS_PCLK/DATA = L/H
GND
0.45
LOCK, PASS
VDDIO = 1.8V
VOUT = 0V,
OS_PCLK/DATA = L/H
PCLK
18
18
mA
IOS
Output Short Circuit Current
TRI-STATE Output Current
VDDIO = 1.8V
VOUT = 0V,
OS_PCLK/DATA = L/H
DATA
mA
µA
PDB = 0V, OSS_SEL =
0V, VOUT = 0V or VDDIO
IOZ
Outputs
-15
+15
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Units
Deserializer DC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
LVDS RECEIVER DC SPECIFICATIONS
Differential Input Threshold High
Voltage
VTH
+50
mV
mV
V
VCM = +1.2V (Internal
VBIAS
)
Differential Input Threshold Low
Voltage
VTL
−50
RIN+, RIN-
RIN+, RIN-
Common Mode Voltage, Internal
VBIAS
VCM
1.2
IIN
Input Current
VIN = 0V or VDDIO
-15
80
+15
120
µA
RT
Internal Termination Resistor
100
Ω
CMLOUTP/N DRIVER OUTPUT DC SPECIFICATIONS – EQ TEST PORT
VOD
Differential Output Voltage
RL = 100Ω,
542
1.4
mV
V
CMLOUTP,
CMLOUTN
Offset Voltage
Single-ended
VOS
RL = 100Ω
CMLOUTP,
CMLOUTN
RT
Internal Termination Resistor
80
100
120
Ω
SUPPLY CURRENT
IDD1
Checker Board Pattern,
OS_PCLK/DATA = H,
EQ = 001,
SSCG=ON
CMLOUTP/N = enabled
CL = 4pF, Figure 9
All VDD pins
93
33
110
45
mA
mA
Deserializer
Supply Current
(includes load current)
IDDIO1
VDDIO
62
75
mA
IDDZ
All VDD pins
VDDIO
40
5
3000
50
µA
µA
µA
Deserializer Supply Current Power
Down
PDB = 0V, All other
LVCMOS Inputs = 0V
IDDIOZ
10
100
Recommended Serializer Timing for PCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tTCP
Parameter
Conditions
Min
15.38
0.4T
0.4T
0.5
Typ
Max
200
Units
ns
Transmit Input PCLK Period
Transmit Input PCLK High Time
Transmit Input PCLK Low Time
PCLK Input Transition Time
T
tTCIH
0.5T
0.5T
0.6T
0.6T
2.4
35
ns
5 MHz to 65 MHz, Figure 4
tTCIL
ns
tCLKT
SSCIN
ns
PCLK Input – Spread Spectrum fmod
at PCLK = 65 MHz
kHz
%
fdev
±2
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SNLS313G –SEPTEMBER 2009–REVISED APRIL 2013
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
200
200
200
200
Max
Units
ps
tLHT
Ser Output Low-to-High
Transition Time, Figure 3
RL = 100Ω, De-emphasis = disabled, VODSEL = 0
RL = 100Ω, De-emphasis = disabled, VODSEL = 1
RL = 100Ω, De-emphasis = disabled, VODSEL = 0
RL = 100Ω, De-emphasis = disabled, VODSEL = 1
RGB[7:0], HS, VS, DE to PCLK
ps
tHLT
Ser Output High-to-Low
Transition Time, Figure 3
ps
ps
tDIS
tDIH
tXZD
Input Data - Setup Time,
Figure 4
2
2
ns
ns
Input Data - Hold Time,
Figure 4
PCLK to RGB[7:0], HS, VS, DE
Ser Ouput Active to OFF Delay,
Figure 6(1)
8
15
10
ns
(2)
tPLD
Serializer PLL Lock Time,
Figure 5(1)(3)
RL = 100Ω
RL = 100Ω
1.4
ms
ns
tSD
Serializer Delay - Latency,
Figure 7(1)
144*T 145 * T
tDJIT
Ser Output Total Jitter,
Figure 8
RL = 100Ω, De-Emph = disabled,
RANDOM pattern, PCLK = 65 MHz
0.28
0.27
0.35
UI(4)
UI
RL = 100Ω, De-Emph = disabled,
RANDOM pattern, PCLK = 43 MHz
RL = 100Ω, De-Emph = disabled,
RANDOM pattern, PCLK = 5 MHz
UI
λSTXBW Serializer Jitter Transfer
PCLK = 65 MHz
PCLK = 43 MHz
PCLK = 20 MHz
PCLK = 5 MHz
PCLK = 65 MHz
PCLK = 43 MHz
PCLK = 20 MHz
PCLK = 5 MHz
3
MHz
MHz
MHz
kHz
dB
Function -3 dB Bandwidth
2.3
1.3
650
δSTX
Serializer Jitter Transfer
Function Peaking
0.838
0.825
0.826
0.278
dB
dB
dB
(1) Specification is ensured by characterization and is not tested in production.
(2) tPLD is the time required by the serializer to obtain lock when exiting power-down state with an active PCLK.
(3) When the Serializer output is at TRI-STATE the Deserializer will lose PLL lock. Resynchronization / Relock must occur before data
transfer require tPLD
(4) UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1 / [28*PCLK]). The UI scales with PCLK frequency.
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Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tRCP
Parameter
PCLK Output Period
PCLK Output Duty Cycle
Conditions
tRCP = tTCP
Pin/Freq.
Min
15.38
43
Typ
T
Max
Units
ns
PCLK
PCLK
200
57
tRDC
SSCG=OFF, 5–65MHz
SSCG=ON, 5–20MHz
SSCG=ON, 20–65MHz
VDDIO = 1.8V, CL = 4 pF
VDDIO = 3.3V, CL = 4 pF
50
59
53
2.1
%
35
65
%
40
60
%
tCLH
LVCMOS
Low-to-High Transition Time,
Figure 10
PCLK/RGB[7:0], HS, VS,
DE
ns
2.0
ns
tCHL
LVCMOS
VDDIO = 1.8V
PCLK/RGB[7:0], HS, VS,
High-to-Low Transition Time,
Figure 10
CL = 4 pF, OS_PCLK/DATA DE
= L
1.6
ns
VDDIO = 3.3V
CL = 4 pF, OS_PCLK/DATA
= H
1.5
ns
T
tROS
Data Valid before PCLK – Set
Up Time, Figure 14
VDDIO = 1.71 to 1.89V or 3.0 RGB[7:0], HS, VS, DE
to 3.6V
CL = 4pF (lumped load)
0.27
0.40
0.45
0.55
tROH
Data Valid after PCLK – Hold
Time, Figure 14
VDDIO = 1.71 to 1.89V or 3.0 RGB[7:0], HS, VS, DE
to 3.6V
T
CL = 4pF (lumped load)
(1)
tDDLT
Deserializer Lock Time,
Figure 13
SSC[3:0] = 0000 (OFF)(2)
SSC[3:0] = 0000 (OFF)(2)
SSC[3:0] = ON(2)
PCLK = 5MHz
PCLK = 65 MHz
PCLK = 5MHz
PCLK = 65 MHz
3
4
ms
ms
ms
ms
ns
ps
ps
ps
ps
ps
ps
UI
30
SSC[3:0] = ON(2)
6
tDD
Des Delay - Latency, Figure 11 SSC[3:0] = 0000 (OFF)(2)
139*T
975
500
550
675
375
500
0.9
140*T
1700
1000
1250
1150
900
tDPJ
Des Period Jitter
SSC[3:0] = OFF(3)(4)(5)
SSC[3:0] = OFF(4)(6)(5)
PCLK = 5MHz
PCLK = 10MHz
PCLK = 65 MHz
PCLK = 5MHz
tDCCJ
Des Cycle-to-Cycle Jitter
PCLK = 10MHz
PCLK = 65 MHz
for jitter freq < 2MHz
for jitter freq > 6MHz
1150
tIJT
Des Input Jitter Tolerance,
Figure 16
EQ = OFF,
SSCG = OFF,
PCLK = 65MHz
0.5
UI
BIST Mode
tPASS BIST PASS Valid Time,
BISTEN = 1, Figure 17
SSCG Mode
1
10
us
fDEV
Spread Spectrum Clocking
Deviation Frequency
Under typical conditions
Under typical conditions
PCLK = 5 to 65 MHz,
SSC[3:0] = ON
±0.5
8
±2
%
fMOD
Spread Spectrum Clocking
Modulation Frequency
PCLK = 5 to 65 MHz,
SSC[3:0] = ON
100
kHz
(1) tDDLT is the time required by the deserializer to obtain lock when exiting power-down state with an active PCLK.
(2) tPLD is the time required by the serializer to obtain lock when exiting power-down state with an active PCLK.
(3) tDPJ is the maximum amount the period is allowed to deviate over many samples.
(4) Specification is ensured by characterization and is not tested in production.
(5) Specification is ensured by design and is not tested in production.
(6) tDCCJ is the maximum amount of jitter between adjacent clock cycles.
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SNLS313G –SEPTEMBER 2009–REVISED APRIL 2013
Recommended Timing for the Serial Control Bus
Over 3.3V supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
>0
Typ
Max
100
400
Units
kHz
kHz
us
fSCL
SCL Clock Frequency
Standard Mode
Fast Mode
>0
tLOW
SCL Low Period
SCL High Period
Standard Mode
Fast Mode
4.7
1.3
4.0
0.6
4.0
us
tHIGH
Standard Mode
Fast Mode
us
us
tHD;STA Hold time for a start or a
repeated start condition,
Figure 18
Standard Mode
Fast Mode
us
0.6
4.7
0.6
us
us
us
tSU:STA Set Up time for a start or a
repeated start condition,
Figure 18
Standard Mode
Fast Mode
tHD;DAT Data Hold Time,
Figure 18
Standard Mode
Fast Mode
0
3.45
0.9
us
us
ns
ns
us
us
us
us
ns
ns
ns
ns
0
tSU;DAT Data Set Up Time,
Figure 18
Standard Mode
Fast Mode
250
100
4.0
0.6
4.7
1.3
tSU;STO Set Up Time for STOP
Condition, Figure 18
Standard Mode
Fast Mode
tBUF
Bus Free Time Between STOP Standard Mode
and START, Figure 18
Fast Mode
tr
SCL & SDA Rise Time,
Figure 18
Standard Mode
Fast Mode
1000
300
300
300
tf
SCL & SDA Fall Time,
Figure 18
Standard Mode
Fast mode
DC and AC Serial Control Bus Characteristics
Over 3.3V supply and temperature ranges unless otherwise specified.
Symbol
VIH
VIL
Parameter
Input High Level
Conditions
Min
2.2
Typ
Max
VDDIO
0.8
Units
V
SDA and SCL
SDA and SCL
Input Low Level Voltage
Input Hysteresis
Output Low Level Voltage(1)
GND
V
VHY
VOL
Iin
>50
mV
V
SDA, IOL = 1.25mA
0
0.4
SDA or SCL, Vin = VDDIO or GND
-15
+15
µA
ns
ns
ns
ns
ns
pF
tR
SDA RiseTime – READ
SDA Fall Time – READ
40
25
SDA, RPU = 10kΩ, Cb ≤ 400pF
tF
tSU;DAT Set Up Time — READ
tHD;DAT Hold Up Time — READ
520
55
tSP
Cin
Input Filter
50
Input Capacitance
SDA or SCL
<5
(1) Specification is ensured by characterization and is not tested in production.
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AC Timing Diagrams and Test Circuits
A
A'
C
C
Scope
A
50W
50W
B
B
B'
50W
50W
Figure 1. Serializer Test Circuit
DOUT+
VOD-
VOD+
DOUT-
GND
VOS
VOD+
(DOUT+) - (DOUT+
)
0V
VODp-p
VOD-
Figure 2. Serializer Output Waveforms
+VOD
80%
20%
(DOUT+) - (DOUT-)
0V
-VOD
t
t
LHLT
LLHT
Figure 3. Serializer Output Transition Times
t
t
TCIL
t
TCIH
TCP
V
DDIO
PCLK
w/ RFB = L
80%
20%
1/2 V
DDIO
GND
tCLKT
tCLKT
V
DDIO
V
V
IHmin
ILmax
RGB[n],
VS, HS, DE
GND
t
t
DIH
DIS
Figure 4. Serializer Input PCLK Waveform and Set and Hold Times
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SNLS313G –SEPTEMBER 2009–REVISED APRIL 2013
PDB
1/2 V
DDIO
PCLK
"X"
active
t
PLD
DOUT
(Diff.)
Driver On
Driver OFF, V
OD
= 0V
Figure 5. Serializer Lock Time
1/2 V
DDIO
PDB
PCLK
active
"X"
t
XZD
DOUT
(Diff.)
active
Driver OFF, V
OD
= 0V
Figure 6. Serializer Disable Time
RGB[7:0],
SYMBOL N
SYMBOL N+1
HS, VS, DE
t
SD
PCLK
(RFB = L)
START
BIT
STOP START
BIT BIT
STOP
BIT
DOUT
(Diff.)
0
1
2
27
0
1
2
27
SYMBOL N-1
SYMBOL N
Figure 7. Serializer Latency Delay
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t
t
DJIT
DJIT
VOD (+)
DOUT
(Diff.)
TxOUT_E_O
0V
VOD (-)
t
(1 UI)
BIT
Figure 8. Serializer Output Jitter
V
DDIO
PCLK
w/ RFB = L
GND
V
DDIO
RGB[n] (odd),
VS, HS
GND
V
DDIO
RGB[n] (even),
DE
GND
Figure 9. Checkerboard Data Pattern
V
DDIO
80%
20%
GND
t
t
CHL
CLH
Figure 10. Deserializer LVCMOS Transition Times
START
BIT
STOP START
BIT BIT
STOP
BIT
RIN
0
1
2
27
0
1
2
27
(Diff.)
SYMBOL N
SYMBOL N+1
t
DD
PCLK
(RFB = L)
RGB[7:0],
SYMBOL N-2
SYMBOL N-1
SYMBOL N
HS, VS, DE
Figure 11. Deserializer Delay – Latency
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1/2 V
PDB
DDIO
RIN
(Diff.)
active
"X"
t
XZR
PCLK,
RGB[7:0],
DE, HS, VS,
PASS, LOCK
active
Z (TRI-STATE)
Figure 12. Deserializer Disable Time (OSS_SEL = 0)
2.0V
PDB
0.8V
RIN
(Diff.)
Don‘t Care
t
DDLT
TRI-STATE
or LOW
LOCK
Z or L
t
RxZ
RGB[7:0],
HS, VS, DE
TRI-STATE or LOW or Pulled Up
Z or L or PU
PCLK
(RFB = L)
TRI-STATE or LOW
IN LOCK TIME
Z or L
OFF
OFF
ACTIVE
Figure 13. Deserializer PLL Lock Times and PDB TRI-STATE Delay
V
DDIO
PCLK
w/ RFB = H
1/2 V
DDIO
GND
V
DDIO
RGB[n],
VS, HS, DE
1/2 V
DDIO
GND
t
t
ROH
ROS
Figure 14. Deserializer Output Data Valid (Setup and Hold) Times with SSCG = Off
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V
DDIO
PCLK
w/ RFB = H
1/2 V
DDIO
GND
RGB[n],
1/2 V
DDIO
1/2 V
V
DDIO
DDIO
VS, HS, DE
GND
t
t
ROH
ROS
Figure 15. Deserializer Output Data Valid (Setup and Hold) Times with SSCG = On
Ideal Data
Bit End
Sampling
Window
Ideal Data Bit
Beginning
V
TH
0V
RxIN_TOL
Left
RxIN_TOL
Right
V
TL
Ideal Center Position (t /2)
BIT
t
(1 UI)
BIT
t
RJIT = RxIN_TOL (Left + Right)
Sampling Window = 1 UI - t
RJIT
Figure 16. Receiver Input Jitter Tolerance
BISTEN
1/2 V
DDIO
tPASS
PASS
(w/ errors)
1/2 V
DDIO
Prior BIST Result
Current BIST Test - Toggle on Error
Result Held
Figure 17. BIST PASS Waveform
SDA
SCL
t
BUF
t
t
LOW
t
f
t
r
HD;STA
t
t
SP
t
f
r
t
t
SU;STA
t
HD;STA
SU;STO
t
HIGH
t
t
SU;DAT
HD;DAT
STOP START
START
REPEATED
START
Figure 18. Serial Control Bus Timing Diagram
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Functional Description
The DS90UR905Q / DS90UR906Q chipset transmits and receives 27-bits of data (24-high speed color bits and 3
low speed video control signals) over a single serial FPD-Link II pair operating at 140Mbps to 1.82Gbps. The
serial stream also contains an embedded clock, video control signals and the DC-balance information which
enhances signal quality and supports AC coupling. The pair is intended for use with each other but is backward
compatible with previous generations of FPD-Link II as well.
The Des can attain lock to a data stream without the use of a separate reference clock source, which greatly
simplifies system complexity and overall cost. The Des also synchronizes to the Ser regardless of the data
pattern, delivering true automatic “plug and lock” performance. It can lock to the incoming serial stream without
the need of special training patterns or sync characters. The Des recovers the clock and data by extracting the
embedded clock information, validating and then deserializing the incoming data stream providing a parallel
LVCMOS video bus to the display.
The DS90UR905Q / DS90UR906Q chipset can operate in 24-bit color depth (with VS,HS,DE encoded in the
DCA bit) or in 18-bit color depth (with VS, HS, DE encoded in DCA or mapped into the high-speed data bits). In
18–bit color applications, the three video signals maybe sent encoded via the DCA bit (restrictions apply) or sent
as “data bits” along with three additional general purpose signals.
Block Diagrams for the chipset are shown at the beginning of this datasheet.
Data Transfer
The DS90UR905Q / DS90UR906Q chipset will transmit and receive a pixel of data in the following format: C1
and C0 represent the embedded clock in the serial stream. C1 is always HIGH and C0 is always LOW. b[23:0]
contain the scrambled RGB data. DCB is the DC-Balanced control bit. DCB is used to minimize the short and
long-term DC bias on the signal lines. This bit determines if the data is unmodified or inverted. DCA is used to
validate data integrity in the embedded data stream and can also contain encoded control (VS,HS,DE). Both
DCA and DCB coding schemes are generated by the Ser and decoded by the Des automatically. Figure 19
illustrates* the serial stream per PCLK cycle. *Note: The figure only illustrates the bits but does not actually
represent the bit location as the bits are scrambled and balanced continuously.
b
1
0
b
1
1
D
C
A
b
0
b
1
b
2
b
3
b
5
b
9
C
1
b
4
b
6
b
7
b
8
D
C
B
b
1
2
b
1
3
b
1
4
b
1
5
b
1
6
b
1
7
b
1
8
b
1
9
b
2
0
b
2
1
b
2
2
b
2
3
C
0
Figure 19. FPD-Link II Serial Stream (905/906)
Ser & Des OPERATING MODES AND BACKWARD COMPATIBILITY (CONFIG[1:0])
The DS90UR905Q / DS90UR906Q chipset is also backward compatible with previous generations of FPD-Link
II. Configuration modes are provided for backwards compatibility with the DS90C241 / DS90C124 FPD-Link II
Generation 1, and also the DS90UR241 / DS90UR124 FPD-Link II Generation 2 chipset by setting the respective
mode with the CONFIG[1:0] pins on the Ser or Des as shown in Table 1 and Table 2. The selection also
determine whether the Video Control Signal filter feature is enabled or disabled in Normal mode. This feature
may be controlled by pin or by Register.
Table 1. DS90UR905Q Ser Modes
CONFIG1
CONFIG0
Mode
Des Device
L
L
L
H
L
Normal Mode, Control Signal Filter disabled
Normal Mode, Control Signal Filter enabled
Backwards Compatible GEN2
Backwards Compatible GEN1
DS90UR906Q
DS90UR906Q
DS90UR124, DS99R124
DS90C124
H
H
H
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Table 2. DS90UR906Q Des Modes
CONFIG1
CONFIG0
Mode
Ser Device
L
L
L
H
L
Normal Mode, Control Signal Filter disabled
Normal Mode, Control Signal Filter enabled
Backwards Compatible GEN2
DS90UR905Q
DS90UR905Q
DS90UR241
DS90C241
H
H
H
Backwards Compatible GEN1
VIDEO CONTROL SIGNAL FILTER — Ser and Des
When operating the devices in Normal Mode, the Video Control Signals (DE, HS, VS) have the following
restrictions:
•
•
•
Normal Mode with Control Signal Filter Enabled:
–
DE and HS — Only 2 transitions per 130 clock cycles are transmitted, the transition pulse must be 3
PCLK or longer.
Normal Mode with Control Signal Filter Disabled:
–
DE and HS — Only 2 transitions per 130 clock cycles are transmitted, no restriction on minimum transition
pulse.
VS — Only 1 transition per 130 clock cycles are transmitted, minimum pulse width is 130 clock cycles.
Video Control Signals are defined as low frequency signals with limited transitions. Glitches of a control signal
can cause a visual display error. This feature allows for the chipset to validate and filter out any high frequency
noise on the control signals. See Figure 20.
PCLK
IN
HS/VS/DE
IN
Latency
PCLK
OUT
Pulses 1 or 2
PCLKs wide
Filetered OUT
HS/VS/DE
OUT
Figure 20. Video Control Signal Filter Waveform
SERIALIZER FUNCTIONAL DESCRIPTION
The Ser converts a wide parallel input bus to a single serial output data stream, and also acts as a signal
generator for the chipset Built In Self Test (BIST) mode. The device can be configured via external pins or
through the optional serial control bus. The Ser features enhance signal quality on the link by supporting: a
selectable VOD level, a selectable de-emphasis signal conditioning and also the FPD-Link II data coding that
provides randomization, scrambling, and DC Balanacing of the video data. The Ser includes multiple features to
reduce EMI associated with display data transmission. This includes the randomization and scrambling of the
data and also the system spread spectrum PCLK support. The Ser features power saving features with a sleep
mode, auto stop clock feature, and optional LVCMOS (1.8 V) parallel bus compatibility.
See also the Functional Description of the chipset's serial control bus and BIST modes.
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EMI Reduction Features
Ser — Spread Spectrum Compatibility
The Ser PCLK is capable of tracking spread spectrum clocking (SSC) from a host source. The PCLK will accept
spread spectrum tracking up to 35kHz modulation and ±0.5, ±1 or ±2% deviations (center spread). The maximum
conditions for the PCLK input are: a modulation frequency of 35kHz and amplitude deviations of ±2% (4% total).
Signal Quality Enhancers
Ser — VOD Select (VODSEL)
The Ser differential output voltage may be increased by setting the VODSEL pin High. When VODSEL is Low,
the VOD is at the standard (default) level. When VODSEL is High, the DC VOD is increased in level. The
increased VOD is useful in extremely high noise environments and also on extra long cable length applications.
When using de-emphasis it is recommended to set VODSEL = H to avoid excessive signal attenuation especially
with the larger de-emphasis settings. This feature may be controlled by the external pin or by register.
Table 3. Differential Output Voltage
Input
Effect
VODSEL
VOD (mV)
±420
VOD (mVp-p)
H
L
840
560
±280
Ser — De-Emphasis (De-Emph)
The De-Emph pin controls the amount of de-emphasis beginning one full bit time after a logic transition that the
Ser drives. This is useful to counteract loading effects of long or lossy cables. This pin should be left open for
standard switching currents (no de-emphasis) or if controlled by register. De-emphasis is selected by connecting
a resistor on this pin to ground, with R value between 0.5 kΩ to 1 MΩ, or by register setting. When using De-
Emphasis it is recommended to set VODSEL = H.
Table 4. De-Emphasis Resistor Value
Resistor Value (kΩ)
De-Emphasis Setting
Disabled
- 12 dB
Open
0.6
1.0
- 9 dB
2.0
- 6 dB
5.0
- 3 dB
0.00
VDD = 1.8V,
= 25oC
T
A
-2.00
-4.00
-6.00
-8.00
-10.00
-12.00
-14.00
1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06
R VALUE - LOG SCALE (W)
Figure 21. De-Emph vs. R value
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Power Saving Features
Ser — Power Down Feature (PDB)
The Ser has a PDB input pin to ENABLE or POWER DOWN the device. This pin is controlled by the host and is
used to save power, disabling the link when the display is not needed. In the POWER DOWN mode, the high-
speed driver outputs are both pulled to VDD and present a 0V VOD state. Note – in POWER DOWN, the
optional Serial Bus Control Registers are RESET.
Ser — Stop Clock Feature
The Ser will enter a low power SLEEP state when the PCLK is stopped. A STOP condition is detected when the
input clock frequency is less than 3 MHz. The clock should be held at a static Low or high state. When the PCLK
starts again, the Ser will then lock to the valid input PCLK and then transmits the RGB data to the Des. Note – in
STOP CLOCK SLEEP, the optional Serial Bus Control Registers values are RETAINED.
1.8V or 3.3V VDDIO Operation
The Ser parallel bus and Serial Bus Interface can operate with 1.8 V or 3.3 V levels (VDDIO) for host compatibility.
The 1.8 V levels will offer lower noise (EMI) and also a system power savings.
Ser — Pixel Clock Edge Select (RFB)
The RFB pin determines the edge that the data is latched on. If RFB is High, input data is latched on the Rising
edge of the PCLK. If RFB is Low, input data is latched on the Falling edge of the PCLK. Ser and Des maybe set
differently. This feature may be controlled by the external pin or by register.
Optional Serial Bus Control
Please see the following section on the optional Serial Bus Control Interface.
Optional BIST Mode
Please see the following section on the chipset BIST mode for details.
DESERIALIZER FUNCTIONAL DESCRIPTION
The Des converts a single input serial data stream to a wide parallel output bus, and also provides a signal
check for the chipset Built In Self Test (BIST) mode. The device can be configured via external pins and strap
pins or through the optional serial control bus. The Des features enhance signal quality on the link by supporting:
an equalizer input and also the FPD-Link II data coding that provides randomization, scrambling, and DC
balanacing of the data. The Des includes multiple features to reduce EMI associated with display data
transmission. This includes the randomization and scrambling of the data and also the output spread spectrum
clock generation (SSCG) support. The Des features power saving features with a power down mode, and
optional LVCMOS (1.8 V) interface compatibility.
Signal Quality Enhancers
Des — Input Equalizer Gain (EQ)
The Des can enable receiver input equalization of the serial stream to increase the eye opening to the Des input.
Note this function cannot be seen at the RxIN+/- input but can be observed at the serial test port (CMLOUTP/N)
enabled via the Serial Bus control registers. The equalization feature may be controlled by the external pin or by
register.
Table 5. Receiver Equalization Configuration Table
INPUTS
Effect
EQ3
EQ2
L
EQ1
L
EQ0
H
L
L
L
~1.5 dB
~3 dB
L
H
H
H
L
H
~4.5 dB
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Table 5. Receiver Equalization Configuration Table (continued)
INPUTS
Effect
EQ3
L
EQ2
H
EQ1
H
EQ0
H
~6 dB
~7.5 dB
~9 dB
H
L
L
H
H
L
H
H
H
H
L
H
~10.5 dB
~12 dB
OFF*
H
H
H
H
X
X
X
L
* Default Setting is EQ = Off
EMI Reduction Features
Des — Output Slew (OS_PCLK/DATA)
The parallel bus outputs (RGB[7:0], VS, HS, DE and PCLK) of the Des feature a selectable output slew. The
DATA ((RGB[7:0], VS, HS, DE) are controlled by strap pin or register bit OS_DATA. The PCLK is controlled by
strap pin or register bit OS_PCLK. When the OS_PCLK/DATA = HIGH, the maximum slew rate is selected.
When the OS_PCLK/DATA = LOW, the minimum slew rate is selected. Use the higher slew rate setting when
driving longer traces or a heavier capacitive load.
Des — Common Mode Filter Pin (CMF) — Optional
The Des provides access to the center tap of the internal termination. A capacitor may be placed on this pin for
additional common-mode filtering of the differential pair. This can be useful in high noise environments for
additional noise rejection capability. A 0.1µF capacitor may be connected to this pin to Ground.
Des — SSCG Generation — Optional
The Des provides an internally generated spread spectrum clock (SSCG) to modulate its outputs. Both clock and
data outputs are modulated. This will aid to lower system EMI. Output SSCG deviations to ±2.0% (4% total) at up
to 35kHz modulations nominally are available. See Table 6. This feature may be controlled by external STRAP
pins or by register.
Table 6. SSCG Configuration (LF_MODE = L) — Des Output
SSC[3:0] Inputs
Result
LF_MODE = L (20 - 65 MHz)
SSC3
L
SSC2
L
SSC1
L
SSC0
L
fdev (%)
Off
fmod (kHz)
Off
L
L
L
H
L
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
L
L
H
H
L
PCLK/2168
PCLK/1300
L
L
H
L
L
H
H
H
H
L
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
H
H
H
H
L
L
H
L
L
H
H
L
PCLK/868
PCLK/650
L
H
L
H
H
H
H
L
H
L
H
H
H
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Table 7. SSCG Configuration (LF_MODE = H) — Des Output
SSC[3:0] Inputs
Result
LH_MODE = H (5 - 20 MHz)
SSC3
L
SSC2
L
SSC1
L
SSC0
L
fdev (%)
Off
fmod (kHz)
Off
L
L
L
H
L
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
L
L
H
H
L
PCLK/620
L
L
H
L
L
H
H
H
H
L
L
L
H
L
L
H
H
L
PCLK/370
L
H
L
H
H
H
H
H
H
H
H
L
L
H
L
L
H
H
L
PCLK/258
PCLK/192
L
H
L
H
H
H
H
L
H
L
H
H
H
Frequency
fdev(max)
F
F
PCLK+
F
PCLK
fdev(min)
Time
PCLK-
1/fmod
Figure 22. SSCG Waveform
1.8V or 3.3V VDDIO Operation
The Des parallel bus and Serial Bus Interface can operate with 1.8 V or 3.3 V levels (VDDIO) for target (Display)
compatibility. The 1.8 V levels will offer a lower noise (EMI) and also a system power savings.
Power Saving Features
Des — PowerDown Feature (PDB)
The Des has a PDB input pin to ENABLE or POWER DOWN the device. This pin can be controlled by the
system to save power, disabling the Des when the display is not needed. An auto detect mode is also available.
In this mode, the PDB pin is tied High and the Des will enter POWER DOWN when the serial stream stops.
When the serial stream starts up again, the Des will lock to the input stream and assert the LOCK pin and output
valid data. In POWER DOWN mode, the Data and PCLK output states are determined by the OSS_SEL status.
Note – in POWER DOWN, the optional Serial Bus Control Registers are RESET.
Des — Stop Stream SLEEP Feature
The Des will enter a low power SLEEP state when the input serial stream is stopped. A STOP condition is
detected when the embedded clock bits are not present. When the serial stream starts again, the Des will then
lock to the incoming signal and recover the data. Note – in STOP STREAM SLEEP, the optional Serial Bus
Control Registers values are RETAINED.
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Des — CLOCK-DATA RECOVERY STATUS FLAG (LOCK) and OUTPUT STATE SELECT (OSS_SEL)
When PDB is driven HIGH, the CDR PLL begins locking to the serial input and LOCK goes from TRI-STATE to
LOW (depending on the value of the OSS_SEL setting). After the DS90UR906Q completes its lock sequence to
the input serial data, the LOCK output is driven HIGH, indicating valid data and clock recovered from the serial
input is available on the parallel bus and PCLK outputs. The PCLK output is held at its current state at the
change from OSC_CLK (if this is enabled via OSC_SEL) to the recovered clock (or vice versa).
If there is a loss of clock from the input serial stream, LOCK is driven Low and the state of the RGB/VS/HS/DE
outputs are based on the OSS_SEL setting (STRAP PIN configuration or register).
Des — Oscillator Output — Optional
The Des provides an optional PCLK output when the input clock (serial stream) has been lost. This is based on
an internal oscillator. The frequency of the oscillator may be selected. This feature may be controlled by the
external pin or by register. See Table 9 and Table 10.
Table 8. OSS_SEL and PDB Configuration — Des Outputs
INPUTS
PDB
OUTPUTS
RGB/HS/VS/DE
Serial
Input
OSS_SEL
PCLK
LOCK
PASS
X
L
X
L
Z
L
Z
L
Z
L
Z
L
Static
Static
Active
H
H
H
H
X
Z
Z*
L
L
Active
Active
H
H
*NOTE — If pin is strapped HIGH, output will be pulled up
Table 9. OSC (Oscillator) Mode — Des Output
INPUTS
Embedded PCLK
NOTE *
OUTPUTS
PCLK
RGB/HS/VS/DE
LOCK
PASS
OSC
L
L
L
Output
Present
Toggling
Active
H
H
* NOTE — Absent and OSC_SEL ≠ 000
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PDB
(DES)
RIN
(Diff.)
active serial stream
X
H
H
LOCK
Z
L
L
L
L
L
Z
L
L
L
RGB[7:0],
HS, VS, DE
PCLK*
(DES)
H
H
PASS
L
L
Z
Z
C0 or C1 Error
In Bit Stream
Locking
Active
Active
OFF
OFF
(Loss of LOCK)
CONDITIONS: * RFB = L, and OSS_SEL = L
Figure 23. Des Outputs with Output State Select Low (OSS_SEL = L)
PDB
(DES)
RIN
(Diff.)
active serial stream
X
H
H
LOCK
L
Z
Z
Z
Z
Z
L
Z
Z
Z
RGB[7:0],
HS, VS, DE
PCLK*
(DES)
H
H
PASS
L
L
Z
Z
Locking
Active
C0 or C1 Error
In Bit Stream
Active
OFF
OFF
(Loss of LOCK)
CONDITIONS: * RFB = L, and OSS_SEL = H
Figure 24. Des Outputs with Output State Select High (OSS_SEL = H)
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Table 10. OSC_SEL (Oscillator) Configuration
OSC_SEL[2:0] INPUTS
PCLK Oscillator Output
OSC_SEL2
OSC_SEL1
OSC_SEL0
L
L
L
L
L
H
L
Off – Feature Disabled – Default
50 MHz ±40%
L
H
H
L
25 MHz ±40%
L
H
L
16.7 MHz ±40%
12.5 MHz ±40%
10 MHz ±40%
H
H
H
H
L
H
L
H
H
8.3 MHz ±40%
H
6.3 MHz ±40%
PDB
(DES)
RIN
(Diff.)
active serial stream
X
H
H
LOCK
Z
L
L
L
L
L
Z
L
L
RGB[7:0],
HS, VS, DE
PCLK*
(DES)
f
f
H
H
PASS
L
Z
L
Z
Locking
Active
C0 or C1 Error
In Bit Stream
Active
OFF
OFF
(Loss of LOCK)
CONDITIONS: * RFB = L, OSS_SEL = H , and OSC_SEL not equal to 000.
Figure 25. Des Outputs with Output State High and PCLK Output Oscillator Option Enabled
Des — OP_LOW — Optional
The OP_ LOW feature is used to hold the LVCMOS outputs (except the LOCK output) at a LOW state. The user
must toggle the OP_LOW Set/Reset register bit to release the outputs to the normal toggling state. Note that the
release of the outputs can only occur when LOCK is HIGH. When the OP_LOW feature is enabled, anytime
LOCK = LOW, the LVCMOS outputs will toggle to a LOW state again. The OP_ LOW strap pin feature is
assigned to output PASS pin 42.
Restrictions on other straps:
1) Other straps should not be used in order to keep RGB[7:0], HS, VS, DE, and PCLK at a true LOW state. Other
features should be selected thru I2C.
2) OSS_SEL function is not available when O/P_LOW is tied H.
Outputs RGB[7:0], HSYNC, VSYNC, DE, and PCLK are in TRI-STATE before PDB toggles HIGH because the
OP_LOW strap value has not been recognized until the DS90UR906 powers up. Figure 26 shows the user
controlled release of OP_LOW and automatic reset of OP_LOW set on the falling edge of LOCK. Figure 27
shows the user controlled release of OP_LOW and manual reset of OP_LOW set. Note manual reset of
OP_LOW can only occur when LOCK is H.
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2.0V
PDB
LOCK
OP_ LOW
SET
(Strap pin)
User
User
controlled
controlled
OP_ LOW
RELEASE/SET
(Register)
RGB[7:0],
HS, VS, DE
TRI-
STATE
ACTIVE
ACTIVE
ACTIVE
TRI-
STATE
ACTIVE
PCLK
Figure 26. OP_LOW Auto Set
2.0V
PDB
LOCK
OP_LOW
SET
(Strap pin)
User
User
controlled
controlled
OP_ LOW
RELEASE/SET
(Register)
RGB[7:0],
HS, VS, DE
TRI-
STATE
ACTIVE
ACTIVE
TRI-
STATE
PCLK
Figure 27. OP_LOW Manual Set/Reset
Des — Pixel Clock Edge Select (RFB)
The RFB pin determines the edge that the data is strobed on. If RFB is High, output data is strobed on the Rising
edge of the PCLK. If RFB is Low, data is strobed on the Falling edge of the PCLK. This allows for inter-
operability with downstream devices. The Des output does not need to use the same edge as the Ser input. This
feature may be controlled by the external pin or by register.
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Des — Control Signal Filter — Optional
The Des provides an optional Control Signal (VS, HS, DE) filter that monitors the three video control signals and
eliminates any pulses that are 1 or 2 PCLKs wide. Control signals must be 3 pixel clocks wide (in its HIGH or
LOW state, regardless of which state is active). This is set by the CONFIG[1:0] or by the Control Register. This
feature may be controlled by the external pin or by Register.
Des — Low Frequency Optimization (LF_Mode)
This feature may be controlled by the external pin or by Register.
Des — Map Select
This feature may be controlled by the external pin or by Register.
Table 11. Map Select Configuration
INPUTS
Effect
MAPSEL1
MAPSEL0
L
L
Bit 4, Bit 5 on LSB
DEFAULT
L
H
LSB 0 or 1
LSB 0
H
H or L
Des — Strap Input Pins
Configuration of the device maybe done via configuration input pins and the STRAP input pins, or via the Serial
Control Bus. The STRAP input pins share select parallel bus output pins. They are used to load in configuration
values during the initial power up sequence of the device. Only a pull-up on the pin is required when a HIGH is
desired. By default the pad has an internal pull down, and will bias Low by itself. The recommended value of the
pull up is 10 kΩ to VDDIO; open (NC) for Low, no pull-down is required (internal pull-down). If using the Serial
Control Bus, no pull ups are required.
Optional Serial Bus Control
Please see the following section on the optional Serial Bus Control Interface.
Optional BIST Mode
Please see the following section on the chipset BIST mode for details.
Built In Self Test (BIST)
An optional At-Speed Built In Self Test (BIST) feature supports the testing of the high-speed serial link. This is
useful in the prototype stage, equipment production, in-system test and also for system diagnostics. In the BIST
mode only a input clock is required along with control to the Ser and Des BISTEN input pins. The Ser outputs a
test pattern (PRBS7) and drives the link at speed. The Des detects the PRBS7 pattern and monitors it for errors.
A PASS output pin toggles to flag any payloads that are received with 1 to 24 errors. Upon completion of the
test, the result of the test is held on the PASS output until reset (new BIST test or Power Down). A high on PASS
indicates NO ERRORS were detected. A Low on PASS indicates one or more errors were detected. The duration
of the test is controlled by the pulse width applied to the Des BISTEN pin. During the BIST duration the
deserializer data outputs toggle with a checkerboard pattern.
Inter-operability is supported between this FPD-Link II device and all FPD-Link II generations (Gen 1/2/3) — see
respective datasheets for details on entering BIST mode and control.
Sample BIST Sequence
See Figure 28 for the BIST mode flow diagram.
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Step 1: Place the DS90UR905Q Ser in BIST Mode by setting Ser BISTEN = H. For the DS90UR905Q Ser or
DS99R421 FPD-Link II Ser BIST Mode is enabled via the BISTEN pin. For the DS90C241 Ser or DS90UR241
Ser, BIST mode is enetered by setting all the input data of the device to Low state. A PCLK is required for all the
Ser options. When the Des detects the BIST mode pattern and command (DCA and DCB code) the RGB and
control signal outputs are shut off.
Step 2: Place the DS90UR906Q Des in BIST mode by setting the BISTEN = H. The Des is now in the BIST
mode and checks the incoming serial payloads for errors. If an error in the payload (1 to 24) is detected, the
PASS pin will switch low for one half of the clock period. During the BIST test, the PASS output can be
monitored and counted to determine the payload error rate.
Step 3: To Stop the BIST mode, the Des BISTEN pin is set Low. The Des stops checking the data and the final
test result is held on the PASS pin. If the test ran error free, the PASS output will be High. If there was one or
more errors detected, the PASS output will be Low. The PASS output state is held until a new BIST is run, the
device is RESET, or Powered Down. The BIST duration is user controlled by the duration of the BISTEN signal.
Step 4: To return the link to normal operation, the Ser BISTEN input is set Low. The Link returns to normal
operation.
Figure 29 shows the waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2
shows one with multiple errors. In most cases it is difficult to generate errors due to the robustness of the link
(differential data transmission etc.), thus they may be introduced by greatly extending the cable length, faulting
the interconnect, reducing signal condition enhancements (De-Emphasis, VODSEL, or Rx Equalization).
Normal
Step 1: SER in BIST
BIST
Wait
Step 2: Wait, DES in BIST
BIST
start
Step 3: DES in Normal
Mode - check PASS
BIST
stop
Step 4: SER in Normal
Figure 28. BIST Mode Flow Diagram
BER Calculations
It is possible to calculate the approximate Bit Error Rate (BER). The following is required:
•
•
•
Pixel Clock Frequency (MHz)
BIST Duration (seconds)
BIST test Result (PASS)
The BER is less than or equal to one over the product of 24 times the PCLK rate times the test duration. If we
assume a 65MHz PCLK, a 10 minute (600 second) test, and a PASS, the BERT is ≤ 1.07 X 10E-12
The BIST mode runs a check on the data payload bits. The LOCK pin also provides a link status. It the recovery
of the C0 and C1 bits does not reconstruct the expected clock signal, the LOCK pin will switch Low. The
combination of the LOCK and At-Speed BIST PASS pin provides a powerful tool for system evaluation and
performance monitoring.
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BISTEN
(SER)
BISTEN
(DES)
PCLK
(RFB = L)
RGB[7:0]
HS, VS, DE
DATA
(internal)
PASS
Prior Result
Prior Result
PASS
FAIL
X = bit error(s)
DATA
(internal)
X
X
X
PASS
BIST
Result
Normal
PRBS
Normal
BIST Test
BIST Duration
Held
Figure 29. BIST Waveforms
Optional Serial Bus Control
The Ser and Des may also be configured by the use of a serial control bus that is I2C protocol compatible. By
default, the I2C reg_0x00'h is set to 00'h and all configuration is set by control/strap pins. A write of 01'h to
reg_0x00'h will enable/allow configuration by registers; this will override the control/strap pins. Multiple devices
may share the serial control bus since multiple addresses are supported. See Figure 30.
The serial bus is comprised of three pins. The SCL is a Serial Bus Clock Input. The SDA is the Serial Bus Data
Input / Output signal. Both SCL and SDA signals require an external pull up resistor to VDDIO. For most
applications a 4.7 k pull up resistor to VDDIO may be used. The resistor value may be adjusted for capacitive
loading and data rate requirements. The signals are either pulled High, or driven Low.
1.8V
10 k
V
DDIO
ID[X]
4.7k
4.7k
SER
or
R
ID
HOST
SCL
SDA
SCL
SDA
DES
To other
Devices
Figure 30. Serial Control Bus Connection
The third pin is the ID[X] pin. This pin sets one of four possible device addresses. Two different connections are
possible. The pin may be pulled to VDD (1.8V, NOT VDDIO)) with a 10 kΩ resistor; or a 10 kΩ pull up resistor (to
VDD1.8V, NOT VDDIO)) and a pull down resistor of the recommended value to set other three possible addresses
may be used. See Table 12 for the Ser and Table 13 for the Des. Do not tie ID[x] directly to VSS.
The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when
SCL transitions Low while SDA is High. A STOP occurs when SDA transition High while SCL is also HIGH. See
Figure 31.
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SDA
SCL
S
P
START condition, or
STOP condition
START repeat condition
Figure 31. START and STOP Conditions
To communicate with a remote device, the host controller (master) sends the slave address and listens for a
response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is
addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't
match a device's slave address, it Not-acknowledges (NACKs) the master by letting SDA be pulled High. ACKs
also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after
every data byte is successfully received. When the master is reading data, the master ACKs after every data
byte is received to let the slave know it wants to receive another data byte. When the master wants to stop
reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus
begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop
condition. A READ is shown in Figure 32 and a WRITE is shown in Figure 33.
Note: During initial power-up, a delay of 10ms will be required before the I2C will respond.
If the Serial Bus is not required, the three pins may be left open (NC).
Table 12. ID[x] Resistor Value – DS90UR905Q Ser
Resistor
RID* kΩ (5% tol)
Address
7'b
Address
8'b
0 appended
(WRITE)
0.47
2.7
7b' 110 1001 (h'69)
7b' 110 1010 (h'6A)
7b' 110 1011 (h'6B)
7b' 110 1110 (h'6E)
8b' 1101 0010 (h'D2)
8b' 1101 0100 (h'D4)
8b' 1101 0110 (h'D6)
8b' 1101 1100 (h'DC)
8.2
Open
Table 13. ID[x] Resistor Value – DS90UR906Q Des
Resistor
RID* kΩ (5% tol)
Address
7'b
Address
8'b
0 appended
(WRITE)
0.47
2.7
7b' 111 0001 (h'71)
7b' 111 0010 (h'72)
7b' 111 0011 (h'73)
7b' 111 0110 (h'76)
8b' 1110 0010 (h'E2)
8b' 1110 0100 (h'E4)
8b' 1110 0110 (h'E6)
8b' 1110 1100 (h'EC)
8.2
Open
*Note: RID ≠ 0 ohm, do not connect directly to VSS (GND), this is not a valid address.
Register Address
Slave Address
Slave Address
Data
a
c
k
a
c
k
a
c
k
a
c
k
A
2
A
1
A
0
A
2
A
1
A
0
0
S
S
1
P
Figure 32. Serial Control Bus — READ
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Register Address
Slave Address
Data
a
c
a
c
k
a
c
k
A
2
A
1
A
0
0
S
P
k
Figure 33. Serial Control Bus — WRITE
Table 14. SERIALIZER — Serial Bus Control Registers
ADD ADD Register Name
(dec) (hex)
Bit(s)
R/W Defau Function
Description
lt
(bin)
0
0
Ser Config 1
7
6
5
R/W
R/W
R/W
0
0
0
Reserved
Reserved
VODSEL
Reserved
Reserved
0: Low
1: High
4
R/W
R/W
0
RFB
0: Data latched on Falling edge of PCLK
1: Data latched on Rising edge of PCLK
3:2
00
CONFIG
00: Control Signal Filter Disabled
01: Control Signal Filter Enabled
10: DS90UR124, DS99R124 Mode
11: DS90C124 Mode
1
R/W
0
SLEEP
Note – not the same function as PowerDown (PDB)
0: normal mode
1: Sleep Mode – Register settings retained.
0
7
R/W
R/W
0
0
REG
0: Configurations set from control pins
1: Configuration set from registers (except I2C_ID)
1
2
1
2
Device ID
REG ID
0: Address from ID[x] Pin
1: Address from Register
6:0
R/W 11010 ID[X]
00
Serial Bus Device ID, Four IDs are:
7b '1101 001 (h'69)
7b '1101 010 (h'6A)
7b '1101 011 (h'6B)
7b '1101 110 (h'6E)
All other addresses are Reserved.
De-Emphasis
Control
7:5
R/W
000 De-E Setting
000: set by external Resistor
001: -1 dB
010: -2 dB
011: -3.3 dB
100: -5 dB
101: -6.7 dB
110: -9 dB
111: -12 dB
4
R/W
R/W
0
De-E EN
0: De-Emphasis Enabled
1: De-Emphasis Disabled
3:0
000 Reserved
Reserved
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Table 15. DESERIALIZER — Serial Bus Control Registers
ADD ADD Register Name
(dec) (hex)
Bit(s)
R/W Defau Function
Description
lt
(bin)
0
0
Des Config 1
7
6
R/W
R/W
R/W
R/W
R/W
0
LFMODE
OS_PCLK
OS_DATA
RFB
0: 20 to 65 MHz Operation
1: 5 to 20 MHz Operation
0
0: Normal PCLK Output Slew
1: Increased PCLK Slew
5
0
0: Normal DATA OUTPUT Slew
1: Increased Data Slew
4
0
0: Data strobed on Falling edge of PCLK
1: Data strobed on Rising edge of PCLK
3:2
00
CONFIG
00: Normal Mode, Control Signal Filter Disabled
01: Normal Mode, Control Signal Filter Enabled
10: Backwards Compatible (DS90UR241)
11: Backwards Compatible (DS90C241)
1
R/W
0
SLEEP
Note – not the same function as PowerDown (PDB)
0: normal mode
1: Sleep Mode – Register settings retained.
0
7
R/W
R/W
0
0
REG Control
0: Configurations set from control pins / STRAP pins
1: Configurations set from registers (except I2C_ID)
1
2
1
2
Slave ID
0: Address from ID[X] Pin
1: Address from Register
6:0
R/W 11100 ID[X]
00
Serial Bus Device ID, Four IDs are:
7b '1110 001 (h'71)
7b '1110 010 (h'72)
7b '1110 011 (h'73)
7b '1110 110 (h'76)
All other addresses are Reserved.
Des Features 1
7
6
R/W
R/W
0
0
OP_LOW
Release/Set
0: set outputs state LOW (except LOCK)
1: release output LOW state, outputs toggling normally
Note: This register only works during LOCK = 1.
OSS_SEL
Output Sleep State Select
0: PCLK/RGB[7:0]/HS/VS/DE = L, LOCK = Normal, PASS
= H
1: PCLK/RGB[7:0]/HS/VS/DE = Tri-State, LOCK = Normal,
PASS = H
5:4
R/W
00
MAP_SEL
Special for Backwards Compatible Mode
00: bit 4, 5 on LSB
01: LSB zero if all data is zero; one if any data is one
10: LSB zero
11: LSB zero
3
R/W
R/W
0
OP_LOW strap
bypass
0: strap will determine whether OP_LOW feature is ON or
OFF
1: Turns OFF OP_LOW feature
2:0
00
OSC_SEL
000: OFF
001: 50 MHz ±40%
010: 25 MHz ±40%
011: 16.7 MHz ±40%
100: 12.5 MHz ±40%
101: 10 MHz ±40%
110: 8.3 MHz ±40%
111: 6.3 MHz ±40%
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Table 15. DESERIALIZER — Serial Bus Control Registers (continued)
ADD ADD Register Name
(dec) (hex)
Bit(s)
R/W Defau Function
Description
lt
(bin)
3
3
Des Features 2
7:5
R/W
000 EQ Gain
000: ~1.625 dB
001: ~3.25 dB
010: ~4.87 dB
011: ~6.5 dB
100: ~8.125 dB
101: ~9.75 dB
110: ~11.375 dB
111: ~13 dB
4
R/W
R/W
0
EQ Enable
0: EQ = disabled
1: EQ = enabled
3:0
0000 SSC
IF LF_MODE = 0, then:
000: SSCG OFF
0001: fdev = ±0.5%, fmod = PCLK/2168
0010: fdev = ±1.0%, fmod = PCLK/2168
0011: fdev = ±1.5%, fmod = PCLK/2168
0100: fdev = ±2.0%, fmod = PCLK/2168
0101: fdev = ±0.5%, fmod = PCLK/1300
0110: fdev = ±1.0%, fmod = PCLK/1300
0111: fdev = ±1.5%, fmod = PCLK/1300
1000: fdev = ±2.0%, fmod = PCLK/1300
1001: fdev = ±0.5%, fmod = PCLK/868
1010: fdev = ±1.0%, fmod = PCLK/868
1011: fdev = ±1.5%, fmod = PCLK/868
1100: fdev = ±2.0%, fmod = PCLK/868
1101: fdev = ±0.5%, fmod = PCLK/650
1110: fdev = ±1.0%, fmod = PCLK/650
1111: fdev = ±1.5%, fmod = PCLK/650
IF LF_MODE = 1, then:
000: SSCG OFF
0001: fdev = ±0.5%, fmod = PCLK/620
0010: fdev = ±1.0%, fmod = PCLK/620
0011: fdev = ±1.5%, fmod = PCLK/620
0100: fdev = ±2.0%, fmod = PCLK/620
0101: fdev = ±0.5%, fmod = PCLK/370
0110: fdev = ±1.0%, fmod = PCLK/370
0111: fdev = ±1.5%, fmod = PCLK/370
1000: fdev = ±2.0%, fmod = PCLK/370
1001: fdev = ±0.5%, fmod = PCLK/258
1010: fdev = ±1.0%, fmod = PCLK/258
1011: fdev = ±1.5%, fmod = PCLK/258
1100: fdev = ±2.0%, fmod = PCLK/258
1101: fdev = ±0.5%, fmod = PCLK/192
1110: fdev = ±1.0%, fmod = PCLK/192
1111: fdev = ±1.5%, fmod = PCLK/192
4
4
CMLOUT Config
7
R/W
0
Repeater Enable 0: Output CMLOUTP/N = disabled
1: Output CMLOUTP/N = enabled
6:0
R/W 00000 Reserved
Reserved
00
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APPLICATIONS INFORMATION
DISPLAY APPLICATION
The DS90UR905Q/906Q chipset is intended for interface between a host (graphics processor) and a Display. It
supports an 24-bit color depth (RGB888) and up to 1024 X 768 display formats. In a RGB888 application, 24
color bits (R[7:0], G[7:0], B[7:0]), Pixel Clock (PCLK) and three control bits (VS, HS and DE) are supported
across the serial link with PCLK rates from 5 to 65 MHz. The chipset may also be used in 18-bit color
applications. In this application three to six general purpose signals may also be sent from host to display.
The Des is expected to be located close to its target device. The interconnect between the Des and the target
device is typically in the 1 to 3 inch separation range. The input capacitance of the target device is expected to
be in the 5 to 10 pF range. Care should be taken on the PCLK output trace as this signal is edge sensitive and
strobes the data. It is also assumed that the fanout of the Des is one. If additional loads need to be driven, a
logic buffer or mux device is recommended.
TYPICAL APPLICATION CONNECTION
Figure 34 shows a typical application of the DS90UR905Q Ser in Pin control mode for a 65 MHz 24-bit Color
Display Application. The LVDS outputs require 100 nF AC coupling capacitors to the line. The line driver includes
internal termination. Bypass capacitors are placed near the power supply pins. At a minimum, four 0.1 µF
capacitors and a 4.7 µF capacitor should be used for local device bypassing. System GPO (General Purpose
Output) signals control the PDB and BISTEN pins. In this application the RFB pin is tied Low to latch data on the
falling edge of the PCLK. The application assumes the companion Des (DS90UR906Q) therefore the
configuration pins are also both tied Low. In this example the cable is long, therefore the VODSEL pin is tied
High and a De-Emphasis value is selected by the resistor R1. The interface to the host is with 1.8 V LVCMOS
levels, thus the VDDIO pin is connected also to the 1.8V rail. The Optional Serial Bus Control is not used in this
example, thus the SCL, SDA and ID[x] pins are left open. A delay cap is placed on the PDB signal to delay the
enabling of the device until power is stable.
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DS90UR905Q (SER)
1.8V
VDDIO
VDDIO
VDDTX
VDDHS
C9
C7
C8
C10
FB1
C3
C4
FB2
R7
R6
R5
R4
R3
R2
R1
R0
VDDP
VDDL
C11
C5
C6
FB3
FB4
G7
G6
G5
G4
G3
G2
G1
G0
C1
C2
Serial
FPD-Link II
Interface
DOUT+
DOUT-
LVCMOS
Parallel
Video
Interface
B7
B6
B5
B4
B3
B2
B1
B0
VDDIO
PCLK
VODSEL
De-Emph
HS
1.8V
VS
DE
R1
LVCMOS
Control
Interface
10k
RID
BISTEN
PDB
ID[X]
SCL
SDA
C12
NOTE:
C1-C2 = 0.1 mF (50 WV)
C3-C8 = 0.1 mF
C9-11 = 4.7 mF
C12 = >10 mF
CONFIG1
CONFIG1
RFB
RES2
RES1
RES0
R1 (cable specific)
DAP (GND)
RID (see ID[x] Resistor Value Table 12)
FB1-FB4: Impedance = 1 kW,
low DC resistance (<1W)
Figure 34. DS90UR905Q Typical Connection Diagram — Pin Control
Figure 35 shows a typical application of the DS90UR906Q Des in Pin/STRAP control mode for a 65 MHz 24-bit
Color Display Application. The LVDS inputs utilize 100 nF coupling capacitors to the line and the Receiver
provides internal termination. Bypass capacitors are placed near the power supply pins. At a minimum, seven 0.1
µF capacitors and two 4.7 µF capacitors should be used for local device bypassing. System GPO (General
Purpose Output) signals control the PDB and the BISTEN pins. In this application the RRFB pin is tied Low to
strobe the data on the falling edge of the PCLK.
Since the device in the Pin/STRAP mode, four 10 kΩ pull up resistors are used on the parallel output bus to
select the desired device features. CONFIG[1:0] is set to 01'b for Normal Mode and Control Signal Filter ON, this
is accomplished with the STRAP pull-up on B7. The receiver input equalizer is also enabled and set to provide
7.5 dB of gain, this is accomplished with EQ[3:0] set to 1001'b with STRAP pull ups on G4 and G7. To reduce
parallel bus EMI, the SSCG feature is enabled and set to 30 kHz and ±1% with SSC[3:0] set to 0010'b and a
STRAP pull-up on R4. The desired features are set with the use of the four pull up resistors.
The interface to the target display is with 3.3V LVCMOS levels, thus the VDDIO pin is connected to the 3.3 V rail.
The optional Serial Bus Control is not used in this example, thus the SCL, SDA and ID[x] pins are left open. A
delay cap is placed on the PDB signal to delay the enabling of the device until power is stable.
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DS90UR906Q (DES)
1.8V
VDDIO
VDDL
VDDIO
VDDIO
VDDIO
C14
C11
C8
C12 C15
FB2
FB1
C3
C4
C5
VDDSC
VDDPR
VDDR
C9
FB3
FB4
FB5
C10
C16
C6
VDDIR
VDDIO
EXAMPLE:
STRAP
Input
VDDCMLO
C17
C7
FB6
Pull-Ups
(10k)
R7
R6
R5
R4
R3
R2
R1
R0
C1
C2
Serial
FPD-Link II
Interface
RIN+
RIN-
CMF
C13
G7
G6
G5
G4
G3
G2
G1
G0
TP_A
TP_B
CMLOUTP
CMLOUTN
LVCMOS
Parallel
Video
Host
Control
BISTEN
PDB
Interface
C18
B7
B6
B5
B4
B3
B2
B1
B0
1.8V
10k
RID
ID[X]
SCL
SDA
HS
VS
DE
C1 - C2 = 0.1 mF (50 WV)
C3 - C12 = 0.1 mF
C13 - C17 = 4.7 mF
C18 = >10 mF
RID (see ID[x] Resistor Value Table 13)
FB1-FB6: Impedance = 1 kW,
low DC resistance (<1W)
NC
8
PCLK
RES
DAP (GND)
LOCK
PASS
Figure 35. DS90UR906Q Typical Connection Diagram — Pin Control
POWER UP REQUIREMENTS AND PDB PIN
The VDD (VDDn and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms
then a capacitor on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the
recommended operating voltage. When PDB pin is pulled to VDDIO, it is recommended to use a 10 kΩ pull-up and
a >10 uF cap to GND to delay the PDB input signal.
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SNLS313G –SEPTEMBER 2009–REVISED APRIL 2013
TRANSMISSION MEDIA
The Ser/Des chipset is intended to be used in a point-to-point configuration, through a PCB trace, or through
twisted pair cable. The Ser and Des provide internal terminations providing a clean signaling environment. The
interconnect for LVDS should present a differential impedance of 100 Ohms. Use cables and connectors that
have matched differential impedance to minimize impedance discontinuities. Shielded or un-shielded cables may
be used depending upon the noise environment and application requirements.
LIVE LINK INSERTION
The Ser and Des devices support live pluggable applications. The automatic receiver lock to random data “plug &
go” hot insertion capability allows the DS90UR906Q to attain lock to the active data stream during a live insertion
event.
PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS
Circuit board layout and stack-up for the LVDS Ser/Des devices should be designed to provide low-noise power
feed to the device. Good layout practice will also separate high frequency or high-level inputs and outputs to
minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly
improved by using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane
capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at
high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the
tantalum capacitors should be at least 5X the power supply voltage being used.
Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power
entry. This is typically in the 50uF to 100uF range and will smooth low frequency switching noise. It is
recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors
connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external
bypass capacitor will increase the inductance of the path.
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size
reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20-30 MHz. To provide effective bypassing, multiple
capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At
high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing
the impedance at high frequency.
Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate
switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not
required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power
pin pairs. In some cases, an external filter many be used to provide clean power to sensitive circuits such as
PLLs.
Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the LVDS
lines to prevent coupling from the LVCMOS lines to the LVDS lines. Closely-coupled differential lines of 100
Ohms are typically recommended for LVDS interconnect. The closely coupled lines help to ensure that coupled
noise will appear as common-mode and thus is rejected by the receivers. The tightly coupled lines will also
radiate less.
Information on the WQFN style package is provided in SNOA401 “Leadless Leadframe Package (LLP)
Application Report” (literature number SNOA401).
LVDS INTERCONNECT GUIDELINES
See AN-1108 and AN-905 for full details.
•
•
Use 100Ω coupled differential pairs
Use the S/2S/3S rule in spacings
–
–
S = space between the pair
2S = space between pairs
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–
3S = space to LVCMOS signal
•
•
•
•
•
Minimize the number of Vias
Use differential connectors when operating above 500Mbps line speed
Maintain balance of the traces
Minimize skew within the pair
Terminate as close to the TX outputs and RX inputs as possible
Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the TI
web site at: www.ti.com/lvds
ALTERNATE COLOR / DATA MAPPING
Color Mapped data Pin names are provided to specify a recommended mapping for 24-bit Color Applications.
Seven [7] is assumed to be the MSB, and Zero [0] is assumed to be the LSB. While this is recommended it is not
required. When connecting to earlier generations of FPD-Link II Ser and Des devices, a color mapping review is
recommended to ensure the correct connectivity is obtained. Table 16 provides examples for interfacing to 18-bit
applications with or without the video control signals embedded. The DS90UR906Q Des also provides additional
flexibility with the MAP_SEL feature as well.
Table 16. Alternate Color / Data Mapping — See Text Below
18-bit RGB
LSB R0
R1
18-bit RGB
24-bit RGB
905 Pin Name 906 Pin Name
24-bit RGB
18-bit RGB
18-bit RGB
LSB R0
R1
GP0
GP1
R0
RO
R1
RO
R1
R2
R3
R4
R5
R6
R7
G0
G1
G2
G3
G4
G5
G6
G7
B0
B1
B2
B3
B4
B5
B6
B7
HS
VS
DE
R0
R1
R2
R3
R4
R5
R6
R7
G0
G1
G2
G3
G4
G5
G6
G7
B0
B1
B2
B3
B4
B5
B6
B7
HS
VS
DE
R0
R1
GP0
GP1
R0
R2
R2
R2
R2
R3
R1
R3
R3
R1
R3
R4
R2
R4
R4
R2
R4
MSB R5
LSB G0
G1
R3
R5
R5
R3
MSB R5
LSB G0
G1
R4
R6
R6
R4
R5
R7
R7
R5
G2
GP2
GP3
GO
G1
G0
G0
GP2
GP3
G0
G2
G3
G1
G1
G3
G4
G2
G2
G4
MSB G5
LSB B0
B1
G3
G3
G1
MSB G5
LSB0
B1
G2
G4
G4
G2
G3
G5
G5
G3
B2
G4
G6
G6
G4
B2
B3
G5
G7
G7
G5
B3
B4
GP4
GP5
B0
B0
B0
GP4
GP5
B0
B4
MSB B5
HS
B1
B1
MSB B5
HS
B2
B2
VS
B1
B3
B3
B1
VS
DE
B2
B4
B4
B2
DE
GP0
B3
B5
B5
B3
GP0
GP1
B4
B6
B6
B4
GP1
GP2
B5
B7
B7
B5
GP2
GND
GND
GND
Scenario 3(1)
HS
HS
HS
HS
GND
GND
GND
Scenario 3(1)
VS
VS
VS
VS
DE
DE
DE
DE
Scenario 2(2)
Scenario 1(3)
905 Pin Name 906 Pin Name
Scenario 1(3)
Scenario 2(2)
(1) Scenario 3 supports an 18-bit RGB color mapping, 3 un-embedded video control signals, and up to three general purpose signals.
(2) Scenario 2 supports an 18-bit RGB color mapping, 3 embedded video control signals, and up to six general purpose signals.
(3) Scenario 1 supports the 24-bit RGB color mapping, along with the 3 embedded video control signals. This is the native mode for the
chipset.
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DS90UR905Q, DS90UR906Q
www.ti.com
SNLS313G –SEPTEMBER 2009–REVISED APRIL 2013
Revision History
•
•
2/01/2010
DS90UR905Q DATASHEET LIMITS HAVE BEEN UPDATED PER CHARACTERIZATION RESULT AND
ARE THE FINAL LIMITS
•
•
•
•
Updated TABLE 12: deleted ID[x] Address 7'b 110 1000 (h'68) (8'b 1101 0000 (h'D0))
Updated TABLE 13: deleted ID[x] Address 7'b 111 0000 (h'70) (8'b 1110 0000 (h'E0))
Updated DS90UR906Q Pin Diagram: strap changes on pin11, pin14, and pin42
Updated DS90UR906Q Deserializer Pin Descriptions: RDS feature changed to OS_PCLK and OS_DATA.
Added OP_LOW feature.
•
•
•
•
Changed strap pin 14 feature from “RDS” to “OS_DATA” (Output Slew_DATA)
Added strap to pin 11 “OS_PCLK” (Output Slew_PCLK)
Added strap to pin 42 “OP_LOW” (Output LOW)
Changed Table 14: ADD \ 1 \ bit \ 6:0 \ ID[x]: deleted Device ID 7b'1101 00 (h'68). Only four (4) IDs will be
available.
•
Changed Table 15: ADD \ 0 \ bit \ 6 \ OSS_SEL: “OSS_SEL” changed feature to “OS_PCLK” (Output
Slew_PCLK). OSS_SEL moved to ADD \ 2 \ bit \ 6 \.
•
•
Changed Table 15: ADD \ 0 \ bit \ 5 \ RDS: changed “RDS” feature to OS_DATA (Output Slew_DATA)
Changed Table 15: ADD \ 1\ bit \ 6:0 \ ID[x]: deleted Device ID 7b'1110 00 (h'70). Only four (4) IDs will be
available.
•
•
•
•
•
•
•
•
•
Changed Table 15: ADD \ 2 \ bit \ 7 \ Reserved: changed “Reserved” to “OP_LOW”
Changed Table 15: ADD \ 2 \ bit \ 6 \ Reserved: changed “Reserved” to “OSS_SEL”
Updated DS90UR905Q Typical Connection Diagram — Pin Control. Ref 30102044
Updated DS90UR906Q Typical Connection Diagram — Pin Control. Ref 30102045
Created OP_LOW timing figure 26. Ref 30102065.
Created OP_LOW timing figure27. Ref 30102066.
Removed IDDT3 and IDDIOT3 (RANDOM pattern) because the limits are the same as checker board pattern.
2/08/2010
Minor corrections: Changed Iin from +/-10uA to +/-15uA in Serial Control bus section; added note 11 to: tXZR
tPLD, tSD, tDJIT and VOL (in Serial Control Bus Characteristics).
,
•
•
2/09/2010
Added “Note: During initial power-up, a delay of 10ms will be required before the I2C will respond.” in
Optional Serial Bus Control description section.
•
•
•
•
•
•
•
•
•
2/11/2010
Removed Note 11 on tDJIT and max values.
3/5/2010
Added reference to soldering profile.
Added ESD CDM and ESD MM values.
Updated θJA value.
5/25/2010
DS90UR906 DATASHEET LIMITS HAVE BEEN UPDATED PER CHARACTERIZATION RESULTS
Corrected TABLE 14. SERIALIZER — Serial Bus Control Registers: register 5 from RFB to VODSEL and
register 4 from VODSEL to RFB.
•
•
•
•
•
•
•
•
8/9/2010
Modified order information to include NOPB designation in NSPN column (replaced NSID column).
Corrected on Page 10. ESD Rating to IEC 61000–4–2 from ISO 10605 (duplication).
Added on Page 17. RPU = 10kΩ condition for the Serial Control Bus Characteristics of tR and tF.
Removed ”Data Randomization & Scrambling”, Noise Margin” and “Typical Performance Curves” sections.
1/13/2011
Modified ESD to include IEC condition (330 Ohm, 150pF).
Updated deserializer parameters: IDD1, IDDZ, IDDIOZ, IDDR, VOH, VOL, tROS, tRDC.
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•
•
•
Updated figures 14 and 15 to reflect data measurement at VDDIO/2
Updated fig 35 — C13 changed to 4.7uF
PASS pin functional change (Tables 8 & 9, Fig 23 & 24)
46
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SNLS313G –SEPTEMBER 2009–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision F (April 2013) to Revision G
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 46
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PACKAGE OPTION ADDENDUM
www.ti.com
16-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
DS90UR905QSQ/NOPB
DS90UR905QSQE/NOPB
DS90UR905QSQX/NOPB
DS90UR906QSQ/NOPB
DS90UR906QSQE/NOPB
DS90UR906QSQX/NOPB
ACTIVE
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
RHS
48
48
48
60
60
60
1000
Green (RoHS
& no Sb/Br)
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
UR905QSQ
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
RHS
RHS
NKB
NKB
NKB
250
2500
1000
250
Green (RoHS
& no Sb/Br)
UR905QSQ
UR905QSQ
UR906QSQ
UR906QSQ
UR906QSQ
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
2000
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Apr-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS90UR905QSQ/NOPB WQFN
DS90UR905QSQE/NOPB WQFN
DS90UR905QSQX/NOPB WQFN
DS90UR906QSQ/NOPB WQFN
DS90UR906QSQE/NOPB WQFN
DS90UR906QSQX/NOPB WQFN
RHS
RHS
RHS
NKB
NKB
NKB
48
48
48
60
60
60
1000
250
330.0
178.0
330.0
330.0
178.0
330.0
16.4
16.4
16.4
16.4
16.4
16.4
7.3
7.3
7.3
9.3
9.3
9.3
7.3
7.3
7.3
9.3
9.3
9.3
1.3
1.3
1.3
1.3
1.3
1.3
12.0
12.0
12.0
12.0
12.0
12.0
16.0
16.0
16.0
16.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
2500
1000
250
2000
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS90UR905QSQ/NOPB
DS90UR905QSQE/NOPB
DS90UR905QSQX/NOPB
DS90UR906QSQ/NOPB
DS90UR906QSQE/NOPB
DS90UR906QSQX/NOPB
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
RHS
RHS
RHS
NKB
NKB
NKB
48
48
48
60
60
60
1000
250
367.0
213.0
367.0
367.0
213.0
367.0
367.0
191.0
367.0
367.0
191.0
367.0
38.0
55.0
38.0
38.0
55.0
38.0
2500
1000
250
2000
Pack Materials-Page 2
MECHANICAL DATA
NKB0060B
SQA60B (Rev B)
www.ti.com
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相关型号：
DS90UR906QSQ/NOPB
IC LINE RECEIVER, QCC60, 9 X 9 MM, 0.80 MM HEIGHT, 0.50 MM PITCH, LLP-60, Line Driver or Receiver
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DS90UR906QSQENOPB
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