DS90UR910QSQX/NOPB [TI]
10 - 75MHz、24 位彩色 FPD-Link II 至 CSI-2 转换器 | RTA | 40 | -40 to 105;
| 型号： | DS90UR910QSQX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 10 - 75MHz、24 位彩色 FPD-Link II 至 CSI-2 转换器 | RTA | 40 | -40 to 105 光电二极管 转换器 |
| 文件： | 总35页 (文件大小：567K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DS90UR910-Q1
ZHCSDL5D –JUNE 2012–REVISED JULY 2015
DS90UR910-Q1 10MHz 至 75MHz、24 位彩色 FPD-Link II 至 CSI-2 转换
器
1 特性
2 说明
1
•
支持 10MHz 至 75MHz 像素时钟
(PCLK)（280Mbps 至 2.10Gbps FPD-Link II 线速
率）
DS90UR910-Q1 是一款接口桥接芯片，用于恢复
FPD-Link II 串行位流中的数据，并将其转换为符合移
动行业处理器接口 (MIPI) 规范的摄像机串行接口 (CSI-
2) 格式。该器件可从兼容 FPD-Link II 串行器的串行位
流中恢复 24 位或 18 位 RGB 数据以及 3 个视频同步
信号。恢复的数据在由符合 MIPI DPHY/CSI-2 规范的
半速率串行时钟所选通的两条数据通道中进行封包化和
串行化，每条数据通道的传输速率最高可达
•
•
兼容直流均衡以及交流耦合的 FPD-Link II 串行位
流
可对长达 10 米的屏蔽双绞线 (STP) 电缆进行数据
恢复
•
•
•
符合 v1.00.00 规范的 MIPI D-PHY 模块
与 MIPI CSI-2 版本 1.01 兼容
900Mbps。FPD-Link II 接收器支持频率最高可达
75MHz 的像素时钟。CSI-2 输出串行总线可显著降低
图形处理器 (GPU) 的互连和信号计数，同时面向多台
汽车驾驶员辅助摄像机的视频流简化系统设计。
支持双通道运行，每条数据通道支持的传输速率最
高可达 900Mbps
•
•
•
•
•
•
•
•
•
•
•
•
视频流数据包格式：RGB888
连续和非连续时钟模式
支持超低功耗、退出、高速和控制模式
集成输入端接和可调节接收均衡
快速随机锁定；无需基准时钟
CCI/I2C 兼容控制总线
DS90UR910-Q1 采用 40 引脚 WQFN 封装。电气性能
符合汽车级 AEC-Q100 2 级标准温度范围（-40°C 至
+105°C）。
(1)
器件信息
全速内置自检 (@Speed BIST) 和报告引脚
+1.8V 单电源
部件号
封装
WQFN (40)
封装尺寸
DS90UR910-Q1
6.00mm x 6.00mm
1.8V 或 3.3V 兼容 LVCMOS I/O 接口
汽车应用级产品：符合 AEC-Q100 2 级要求
8kV ISO 10605 静电放电 (ESD) 额定值
6mm x 6mm 超薄型四方扁平无引线 (WQFN)-40
封装
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
应用图
VDDIO
(1.8V or 3.3V)
VDD
1.8V
VDDIO
(1.8V or 3.3V) 1.8V
VDD
CSI-2
DATA1±
0.1 µF
0.1 µF
0.1 µF
0.1 µF
R[7:0]
G[7:0]
B[7:0]
DOUT+
RIN+
RIN-
DATA0±
CLK±
Video
sources
HS
DOUT-
VS
DE
Graphic
Processor
Application
Processor
FPD-Link II
1 pair 100Ω STP
Display
DS90UR905Q-Q1
Serializer
DS90UR910-Q1
Converter
PCLK
SCL
SDA
PDB
LOCK
CONFIG[1:0]
BISTEN
Control
pins
CONFIG[1:0]
RFB
EQ[3:1]
ID[1:0]
PDB
SCL
SDA
ID[x]
BISTEN
PASS
VODSEL
DeEmph
DAP GND
DAP
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SNLS414
DS90UR910-Q1
ZHCSDL5D –JUNE 2012–REVISED JULY 2015
www.ti.com.cn
目录
6.2 Functional Block Diagram ....................................... 17
6.3 Feature Description................................................. 18
6.4 Register Maps......................................................... 25
Application and Implementation ........................ 28
7.1 Typical Application Connection............................... 28
7.2 Design Requirements.............................................. 28
7.3 Application Performance Plots................................ 29
Power Supply Recommendations...................... 30
8.1 Power Up Requirements and PDB Pin................... 30
Layout ................................................................... 30
9.1 Layout Guidelines ................................................... 30
1
2
3
4
5
特性.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
5.1 Absolute Maximum Ratings ..................................... 5
5.2 ESD Ratings.............................................................. 5
5.3 Recommended Operating Conditions....................... 5
5.4 DC Electrical Characteristics .................................. 6
5.5 AC Switching Characteristics.................................... 8
7
8
9
5.6 Recommended Timing for the Serial Control Bus
(CCI/I2C) ................................................................. 10
10 器件和文档支持 ..................................................... 33
10.1 商标....................................................................... 33
10.2 静电放电警告......................................................... 33
10.3 Glossary................................................................ 33
11 机械、封装和可订购信息....................................... 33
5.7 DC and AC Serial Control Bus (CCI/I2C) ............... 11
5.8 Typical Characteristics............................................ 15
Detailed Description ............................................ 16
6.1 Overview ................................................................. 16
6
3 修订历史记录
修订
说明
2012 年 9 月 17 日 DS90UR910-Q1 数据表 - 最初发布版本
2012 年 10 月 23 日 更新了引脚图
2013 年 5 月 2 日
2013 年 5 月 17 日 明确了 VDDL 和 VDDA 电源引脚的编号
2015 年 4 月 16 日 将器件状态由“产品预览”更改为“量产数据”。添加了新的章节标题并更新至新的 TI 格式。
已将国家数据表的版面布局更改为 TI 格式
2
Copyright © 2012–2015, Texas Instruments Incorporated
DS90UR910-Q1
www.ti.com.cn
ZHCSDL5D –JUNE 2012–REVISED JULY 2015
4 Pin Configuration and Functions
40-Pin WQFN
Top View
29
28
27
26
25 24
23
22
30
21
VDDCSI
DATA1+
20
19
18
VDDA
GND
31
32
33
34
35
DATA1-
GND
RIN+
RIN-
17
16
DS90UR910-Q1
40-Pin WQFN
(Top View)
DATA0+
DATA0-
GND
CMF
15
14
13
12
11
36
37
38
39
40
GND
CMLOUT+
CLK+
CMLOUT-
CLK-
VDDA
VDDP
DAP = GND
CONFIG[0]
2
3
4
5
6
7
8
9
1
10
(1)
Pin Descriptions
Pin Name
Pin #
I/O, Type
Description
FPD-Link II Serial Interface
RIN+
RIN-
33
34
Inverting and non-inverting differential inputs. The inputs must be AC Coupled with a 100 nF
capacitor.
I, CML
Common mode filter pin for the differential inputs. CMP is the virtual ground of the differential
input stage. A bypass capacitor is connected from CMP to ground to increase the receiver’s
common mode noise immunity. A 4.7 µF ceramic capacitor is recommended.
CMF
35
I, Analog
Inverting and non-inverting differential outputs. Single 100Ω (1%) termination resistor must
be placed across the CMLOUT± pins. Optional loop-through output to monitor post equalizer
and requires use of the Serial Control Bus to enable.
CMLOUT+
CMLOUT-
37
38
O, CML
MIPI Interface
DATA1+
DATA1-
19
18
O, DPHY
O, DPHY
Inverting and non-inverting data output of DPHY Lane 1
Inverting and non-inverting data output of DPHY Lane 0
Inverting and non-inverting half-rate DPHY clock lane
DATA0+
DATA0-
16
15
O, DPHY
O, DPHY
CLK+
CLK-
13
12
O, DPHY
O, DPHY
(1) 1 = HIGH, 0 = LOW
Copyright © 2012–2015, Texas Instruments Incorporated
3
DS90UR910-Q1
ZHCSDL5D –JUNE 2012–REVISED JULY 2015
www.ti.com.cn
(1)
Pin Descriptions
(continued)
Pin Name
Pin #
I/O, Type
Description
Control and Configuration
Power Down Mode Input
PDB = 1, Device is enabled (normal operation)
PDB = 0, Device is in power-down
When the device is in the power-down, outputs are TRI-STATE, control registers are
RESET.
I, LVCMOS
w/ pull-down
PDB
30
I, LVCMOS Operating Mode Select
w/ pull-down CONFIG[1:0] selects compatibility to FPD-Link II serializers. See Table 1.
CONFIG[1:0]
EQ[3:1]
10, 11
1, 2, 3
Receive equalization control
I, LVCMOS EQ[3:1] provides 8 combinations of the receive equalization gain settings. See Table 2.
w/ pull-down EQ[3:1] optimizes the input equalizer’s ability to reduce inter-symbol interference from the
loss characteristics of different cable lengths.
BIST Enable Input
I, LVCMOS
BISTEN
LOCK
29
24
BISTEN = 1, BIST is enabled
w/ pull-down
BISTEN = 0, BIST is disabled
LOCK Status Output
O, LVCMOS LOCK = 1, PLL acquired lock to the reference clock input; DPHY outputs are active
LOCK = 0, PLL is unlocked
Normal mode status output pin (BISTEN = 0)
PASS = 1: No fault detected on input display timing
PASS = 0: Indicates an error condition or corruption in display timing. Fault condition occurs
if:
PASS
25
O, LVCMOS
1) DE length value mismatch measured once in succession
2) VSync length value mismatch measured twice in succession
BIST mode status output pin (BISTEN = 1)
PASS = 1: No error detected
PASS = 0: Error detected
CCI / I2C Serial Control Bus
I, LVCMOS, Serial Control Bus Clock Input
Open Drain SCL requires an external pull-up resistor to VDDIO
SCL
SDA
6
5
.
I/O, LVCMOS Serial Control Bus Data Input / Output
Open Drain SDA requires an external pull-up resistor to VDDIO
.
I, LVCMOS Serial Control Bus Device ID Address Select
w/ pull-down See Table 5.
ID[1:0]
8, 9
Reserved Pins
GPIO
General Purpose I/O
I/O
21
28
Note: Pin must be left floating during initial power-up.
I, LVCMOS
w/ pull-down
RES
Reserved pin. Must tie Low.
Power and Ground
VDDL
7, 26
31, 39
40
Power
Power
Power
Power
Power
Power to logic circuitry, 1.8V ±5%
VDDA
Power to analog circuitry, 1.8V ±5%
VDDP
Power to PLL, 1.8V ±5%
VDDCSI
VDDIO
20
Power to DPHY CSI-2 drivers, 1.8V ±5%
Power to LVCMOS I/O circuitry, 1.8V ±5% OR 3.3V ±10% (VDDIO
23
)
4, 14, 17,
22, 27, 32,
36
GND
Ground
Ground return.
DAP is the metal contact at the bottom side, located at the center of the WQFN package. It
should be connected to the GND plane with multiple via to lower the ground impedance and
improve the thermal performance of the package. Connected to the ground plane (GND) with
at least 9 vias.
GND
DAP
Ground
4
Copyright © 2012–2015, Texas Instruments Incorporated
DS90UR910-Q1
www.ti.com.cn
ZHCSDL5D –JUNE 2012–REVISED JULY 2015
5 Specifications
5.1 Absolute Maximum Ratings
(1) (2)
MIN
−0.3
−0.3
-0.3
MAX
2.5
UNIT
Supply Voltage – VDDA, VDDP, VDDL, VDDCSI (1.8V)
Supply Voltage – VDDIO (1.8V I/O)
Supply Voltage – VDDIO (3.3V I/O)
LVCMOS I/O Voltage
V
V
V
2.5
4.0
(VDDIO
0.3)
+
−0.3
−0.3
−0.3
V
V
Receiver Input Voltage
CSI-2 Output Voltage
(VDDA
0.3)
+
(VDDCSI
0.3V)
+
V
Junction Temperature
150
°C
4L WQFN Package Maximum Power Dissipation Capacity at 25°C
Storage temperature, Tstg
−65
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under . Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) For soldering specifications, see product folder at www.ti.com and SNOA549.
5.2 ESD Ratings
VALUE
±8000
UNIT
(1)
Human body model (HBM), per AEC Q100-002, all pins
Charged device model (CDM), per AEC Q100-011, all pins
Machine model (MM)
±1000
±250
Air Discharge (RIN+, RIN-
Contact Discharge (RIN+, RIN-
Air Discharge (RIN+, RIN-
Contact Discharge (RIN+, RIN-
Air Discharge (RIN+, RIN-
Contact Discharge (RIN+, RIN-
)
±30000
±10000
±30000
±10000
±30000
(IEC, powered-up only)
RD = 330 Ω, CS = 150 pF
Electrostatic
discharge
)
)
V(ESD)
V
)
(ISO10605)
RD = 330 Ω, CS = 150 pF
(ISO10605)
RD = 2 kΩ, CS = 150 pF or
330 pF
)
)
±10000
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
5.3 Recommended Operating Conditions
MIN
1.71
1.71
3.0
NOM
1.8
MAX
1.89
1.89
3.6
UNIT
Supply Voltage, VDDA, VDDP, VDDL, VDDCSI
LVCMOS Supply Voltage VDDIO (1.8V I/O)
LVCMOS Supply Voltage VDDIO (3.3V I/O)
Operating Free Air Temperature (TA)
PCLK Clock Frequency
1.8
V
3.3
-40
+25
+105
75
°C
10
MHz
Supply Noise
VDDn (1.8V)
25
25
50
VDDIO (1.8V I/O)
mVP-P
VDDIO (3.3V I/O)
Copyright © 2012–2015, Texas Instruments Incorporated
5
DS90UR910-Q1
ZHCSDL5D –JUNE 2012–REVISED JULY 2015
www.ti.com.cn
(1) (2) (3)
5.4 DC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
3.3V I/O LVCMOS DC SPECIFICATIONS – VDDIO = 3.0 to 3.6V (BISTEN, LOCK, PASS, PDB, EQ[3:1], ID[1:0], CONFIG[1:0], GPIO)
VIH
VIL
IIN
High Level Input Voltage
Low Level Input Voltage
Input Current
VIN = 3.0V to 3.6V
VIN = 3.0V to 3.6V
VIN = 0V or VDDIO
IOH = −2 mA
2.2
GND
−15
2.4
VDDIO
0.8
V
V
+15
μA
V
VOH
VOL
IOZ
High Level Output Voltage
Low Level Output Voltage
TRI-STATE Output Current
VDDIO
0.4
IOL = +2 mA
GND
−15
V
PDB = 0V
+15
uA
1.8V I/O LVCMOS DC SPECIFICATIONS – VDDIO = 1.71 to 1.89V (BISTEN, LOCK, PASS, PDB, EQ[3:1], ID[1:0], CONFIG[1:0], GPIO)
0.65*
VIH
High Level Input Voltage
VIN = 1.71V to 1.89V
VDDIO
V
VDDIO
GND
−15
0.35*
VDDIO
VIL
IIN
Low Level Input Voltage
Input Current
VIN = 1.71V to 1.89V
VIN = 0V or VDDIO
IOH = −2 mA
V
μA
V
+15
VDDIO
−0.45
VOH
High Level Output Voltage
VDDIO
VOL
IOZ
Low Level Output Voltage
TRI-STATE® Output Current
IOL = +2 mA
PDB = 0V
GND
0.45
+15
V
−15
µA
SUPPLY CURRENT
IDD1
Supply current
Supply current drawn from
1.8V rail (VDDL, VDDP, VDDA
Checker Board Pattern
VDDL, VDDP, VDDA
= 1.89V
f = 75 MHz
(900 Mbps)
)
88
38
95
65
mA
mA
VDDL, VDDP, VDDA
= 1.89V
f = 10 MHz
(120 Mbps)
IDDTX1
Supply current drawn at
VDDCSI
Checker Board Pattern
VDDCSI = 1.89V
f = 75 MHz
(900 Mbps)
50
22
mA
mA
mA
mA
VDDCSI = 1.89V
f = 10 MHz
(120 Mbps)
IDDIO1
Supply current drawn at VDDIO VDDIO = 1.89V
Checker Board Pattern
f = 75 MHz
(900 Mbps)
10
15
VDDIO = 3.6V
f = 75 MHz
(900 Mbps)
(1) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
(2) Typical values represent most likely parametric norms at VDD = 3.3V, Ta = +25 degC, and at the Recommended Operation Conditions at
the time of product characterization and are not ensured.
(3) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
6
Copyright © 2012–2015, Texas Instruments Incorporated
DS90UR910-Q1
www.ti.com.cn
ZHCSDL5D –JUNE 2012–REVISED JULY 2015
DC Electrical Characteristics (1) (2) (3) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
IDDZ
Parameter
Conditions
Min
Typ
Max
Units
Supply Current at Power down
mode
Supply current drawn from
VDDL, VDDP, VDDA
= 1.89V
1.8V rail (VDDL, VDDP, VDDA
)
PDB = 0V
5
mA
(All other LVCMOS Inputs
Low)
IDDTXZ
Supply current drawn at
VDDCSI
VDDCSI = 1.89V
PDB = 0V
5
mA
(All other LVCMOS Inputs
Low)
IDDIOZ
Supply current drawn at VDDIO VDDIO = 1.89V
PDB = 0V
3
3
mA
mA
(All other LVCMOS Inputs
VDDIO = 3.6V
Low)
IDDUPLS
Ultra Low Power State Current
Supply current drawn from
VDD = 1.89V
VDDIO = 3.6V
1.8V at (VDDL, VDDP, VDDA
VDDCSI) and VDDIO
PLL off, no change in all input
signals
,
20
mA
Register:
0x19h = 0x03h
0x01h = 0x02h
FPD-LINK II RECEIVER DC SPECIFICATIONS (RIN±)
Differential Input Threshold High
Voltage
VTH
+50
mV
mV
V
VCM = +1.2V (Internal VBIAS
)
Differential Input Threshold Low
Voltage
VTL
−50
Common Mode Voltage, Internal
VBIAS
VCM
1.2
IIN
Input Current
VIN = 0V or VDD
Differential across RIN+ and RIN-
−15
+15
120
µA
RT
Internal Termination Resistor
80
100
Ω
CMLOUT± DRIVER OUTPUT DC SPECIFICATIONS (CMLOUT±)
(4)
VOD
VOS
RT
Differential Output Voltage
Offset Voltage Single-ended
Internal Termination Resistor
RL = 100Ω
500
1.3
mV
V
RL = 100Ω
Differential across CMLOUT+ and CMLOUT-
80
100
120
250
Ω
HSTX DRIVER DC SPECIFICATIONS (DATA0±, DATA1±, CLK±) Section 8.1.1 of MIPI D-PHY Specification
HS transmit static common-mode
VCMTX
150
200
200
mV
voltage
VCMTX mismatch when output is
1 or 0 state
|ΔVCMTX(1,0)
|
5
mV
mV
mV
|VOD
|
HS transmit differential voltage
140
40
270
10
VOD mismatch when output is 1
or 0 state
|ΔVOD
|
VOHHS
ZOS
HS output high voltage
360
mV
Single ended output impedance
50
62.5
Ω
Mismatch in single ended output
impedance
ΔZOS
10
%
LPTX DRIVER DC SPECIFICATIONS (DATA0±, DATA1±, CLK±) Section 8.1.2 of MIPI D-PHY Specification
(5)
VOH
VOL
Output high level
Output low level
Output impedance
See
1.1
−50
110
1.2
1.3
50
V
mV
Ω
ZOLP
(4) Voltage difference compared to the DC average common-mode potential.
(5) Specification is ensured by characterization.
Copyright © 2012–2015, Texas Instruments Incorporated
7
DS90UR910-Q1
ZHCSDL5D –JUNE 2012–REVISED JULY 2015
www.ti.com.cn
5.5 AC Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
FPD-LINK II RECEIVER (RIN±)
(1)
tIJT
Input Jitter Tolerance, Figure 1
EQ = OFF,
PCLK = 65MHz
jitter freq < 2MHz
jitter freq > 6MHz
0.9
0.5
10
UI
UI
tDDLT
Deserializer Lock Time, Figure 2
PCLK = 75 MHz
ms
HSTX DRIVER AC SPECIFICATIONS (DATA0±, DATA1±, CLK±) Section 8.1.1 of MIPI D-PHY Specification
HSTXDBR
Data bit rate
DATA0±
DATA1±
PCLK = 10-75MHz
120
60
PCLK*12
PCLK*6
900
450
15
Mbps
MHz
(2)
fCLK
DDR Clock frequency
CLK±
ΔVCMTX(HF)
Common mode voltage variations
HF
Common-level variations above 450
mVRMS
(2)
MHz
ΔVCMTX(LF)
Common mode voltage variations LF Common-level variations between
25
mVPEAK
(2)
50–450 MHz
(3)
tRHS
Rise Time HS
20% to 80% rise time
20% to 80% rise time
0.3
UIINST
ps
150
150
(3)
tFHS
Fall Time HS
0.3
UIINST
ps
SDDTX
TX differential return loss
See Figure 33 of fLPMAX
MIPI D-PHY
–18
–12
–6
dB
fH
dB
(2)
Specification
fMAX
dB
SCCTX
TX common mode return loss
Section 7.7.2 of fLPMAX to fMAX
MIPI D-PHY
Specification
–6
dB
(2)
(4)
LPTX DRIVER AC SPECIFICATIONS (DATA0±, DATA1±, CLK±)
Section 8.1.2 of MIPI D-PHY Specification
tRLP
Rise Time
LP 15% to 85% rise time
Cload = 70pF lumped capacitance
25
ns
tFLP
Fall Time
LP 15% to 85% fall time
Cload = 70pF lumped capacitance
25
35
ns
ns
(2)
tREOT
Post-EoT Rise and Fall Time
30%-85% rise time and fall time
tLP-PULSE-TX
Pulse width of the LP exclusive-OR First LP exclusive-OR clock pulse
clock
after Stop state or last pulse before
Stop state
40
ns
(2)
(2)
All other pulses
20
90
ns
ns
(2)
tLP-PER-TX
Period of the LP exclusive-OR clock See
(1) UI is equivalent to one serialized data bit width (1UI = 1 / 28*PCLK). The UI scales with PCLK frequency.
(2) Specification is ensured by design and is not tested in production.
(3) Specification is ensured by characterization.
(4) CLOAD includes the low-frequency equivalent transmission line capacitance. The capacitance of TX and RX are assumed to always be
<10 pF. The distributed line capacitance can be up to 50 pF for a transmission line with 2ns delay.
8
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AC Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
σV/σtSR
Parameter
Conditions
Min
Typ
Max
500
300
250
150
Units
mV/ns
mV/ns
mV/ns
mV/ns
(3) (4) (5)
Slew rate
Cload = 0pF
Cload = 5pF
Cload = 20pF
Cload = 70pF
(3) (4) (5)
(3) (4) (5)
(3) (4) (5)
Cload = 0 to 70pF (Falling Edge Only)
30
30
mV/ns
mV/ns
(3) (4) (5) (6)
Cload = 0 to 70pF (Rising Edge Only)
(3) (4) (5)
Cload = 0 to 70pF (Rising Edge Only) 30 – 0.075
(3) (4) (7) (8)
*
mV/ns
pF
(VO,INST
700)
–
(4)
CLOAD
Load capacitance
See
0
70
Data-Clock Timing Specifications (DATA0±, DATA1±, CLK±) Section 9.2.1 of MIPI D-PHY Specification
(9)
UIINST
Instantaneous Unit Interval
Figure 3
PCLK = 10 – 75 MHz
1/
ns
(PCLK*12)
tSKEW(TX)
Data to Clock Skew
Figure 3
Skew between Clock and data from
ideal center
0.5-0.15
0.5
0.5+0.15 UIINST
(2)
CSI-2 Timing Specifications (DATA0±, DATA1±, CLK±) (2) ( Figure 4, Figure 5) Section 5.9 of MIPI D-PHY Specification
tCLK-POST
HS exit
60 +
52*UIINST
ns
tCLK-PRE
Time HS clock shall be driver prior
to any associated Data Lane
beginning the transition from LP to
HS mode
8
UIINST
tCLK-PREPARE Clock Lane HS Entry
38
95
95
ns
ns
tCLK-SETTLE
Time interval during which the HS
receiver shall ignore any Clock Lane
HS transitions
300
tCLK-TERM-EN
tCLK-TRAIL
Time-out at Clock Lane Display
Module to enable HS Termination
38
ns
ns
Time that the transmitter drives the
HS-0 state after the last payload
clock bit of a HS transmission burst
30
tCLK-PREPARE TCLK-PREPARE + time that the
+ tCLK-ZERO
tD-TERM-EN
tLPX
transmitter drives the HS-0 state
prior to starting the Clock
300
ns
(10)
Time for the Data Lane receiver to
enable the HS line termination
35 ns +
4*UIINST
ns
ns
ns
Transmitted length of LP state
Data Lane HS Entry
50
tHS-PREPARE
40 +
4*UIINST
85 +
6*UIINST
tHS-PREPARE
tHS-ZERO
+
tHS-PREPARE + time that the
transmitter drives the HS-0 state
prior to transmitting the Sync
sequence
145 +
10*UIINST
ns
ns
tHS-SETTLE
Interval HS receiver shall ignore any
Data Lane HS transitions
85 +
6*UIINST
145 +
10*UIINST
(5) Measured as average across any 50 mV segment of the output signal transition.
(6) When the output voltage is between 400 mV and 930 mV.
(7) Where VO,INST is the instantaneous output voltage, VDP or VDN, in millivolts.
(8) When the output voltage is between 700 mV and 930 mV.
(9) UIINST is equal to 1/(12*PCLK), where PCLK is the fundamental frequency for data transmission.
(10) This parameter value can be lower then TLPX due to differences in rise vs. fall signal slopes and trip levels and mismatches between
Dp and Dn LP transmitters. Any LP exclusive-OR pulse observed during HS EoT (transition from HS level to LP-11) is glitch behavior as
described in D-PHY ver 1.00.00.
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AC Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tHS-TRAIL
Parameter
Data Lane HS Exit
Conditions
Min
Typ
Max
Units
60 +
4*UIINST
ns
tEOT
Transmitted time interval from the
start of tHS-TRAIL to the start of the
LP-11 state following a HS burst
105 +
12*UIINST
ns
tHS-EXIT
tWAKEUP
Time that the transmitter drives LP-
11 following a HS burst.
100
1
ns
Recovery Time from Ultra Low
Power State (ULPS)
ms
5.6 Recommended Timing for the Serial Control Bus (CCI/I2C)
(1)
Over supply and temperature ranges unless otherwise specified. ( Figure 7)
Symbol
fSCL
Parameter
Conditions
Standard Mode
Min
>0
Typ
Max
100
400
Units
kHz
kHz
us
SCL Clock Frequency
Fast Mode
>0
tLOW
SCL Low Period
SCL High Period
Standard Mode
Fast Mode
4.7
1.3
4.0
0.6
4.0
0.6
4.7
0.6
0
us
tHIGH
tHD;STA
tSU;STA
tHD;DAT
tSU;DAT
tSU;STO
tBUF
Standard Mode
Fast Mode
us
us
Hold time for a start or a
repeated start condition
Standard Mode
Fast Mode
us
us
Set Up time for a start or a
repeated start condition
Standard Mode
Fast Mode
us
us
Data Hold Time
Standard Mode
Fast Mode
3.45
0.9
us
0
us
Data Set Up Time
Standard Mode
Fast Mode
250
100
4.0
0.6
4.7
1.3
ns
ns
Set Up Time for STOP
Condition
Standard Mode
Fast Mode
us
us
Bus Free Time
Between STOP and START
Standard Mode
Fast Mode
us
us
tr
SCL & SDA Rise Time
SCL & SDA Fall Time
Standard Mode
Fast Mode
1000
300
300
300
ns
ns
tf
Standard Mode
Fast mode
ns
ns
(1) Recommended Input Timing Requirements are input specifications and not tested in production.
10
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5.7 DC and AC Serial Control Bus (CCI/I2C)
Over supply and temperature ranges unless otherwise specified. ( Figure 7)
Symbol
VIH
Parameter
Input High Level
Conditions
Min
Typ
Max
Units
SDA and SCL
SDA and SCL
0.65*
VDDIO
VDDIO
V
VIL
Input Low Level Voltage
Input Hysteresis
0.35*
VDDIO
GND
V
(1)
VHY
Fast mode, 3.3V I/O
Fast mode, 1.8V I/O
SDA, IOL = +1.5 mA
0.05*
VDDIO
mV
0.1*
VDDIO
mV
V
VOL
tR
Output Low Level Voltage
SDA RiseTime – READ
0
0.4
Total capacitance of one bus line,
300
ns
Cb ≤ 400pF
tF
SDA Fall Time – READ
Set Up Time – READ
Standard mode
Fast mode
1000
300
ns
ns
ns
ns
ns
ns
pF
tSU;DAT
Standard mode
Fast mode
250
100
0
tHD;DAT
tSP
Hold Up Time – READ
Input Filter
Fast mode
50
5
Cin
Input Capacitance
SDA and SCL
(1) Specification is ensured by characterization.
Ideal Data
Bit End
Sampling
Window
Ideal Data Bit
Beginning
V
TH
0V
RxIN_TOL
Left
RxIN_TOL
Right
V
TL
Ideal Center Position (t /2)
BIT
t
(1 UI)
BIT
tIJT = RxIN_TOL (Left + Right)
Sampling Window = 1 UI - t
IJT
Figure 1. Receiver Input Jitter Tolerance
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PDB
(3.3V I/O)
2.2V
0.8V
RIN
(Diff.)
t
DDLT
LOCK
TRI-STATE
TRI-STATE
DATA0+/-
DATA1+/-
CLK+/-
OFF
IN LOCK TIME
ACTIVE
OFF
Figure 2. Deserializer PLL Lock Time
DATA1+
DATA1-
DATA0+
DATA0-
0.5UI +
tskew
CLK+
CLK-
1 UI
Figure 3. Clock and Data Timing in HS Transmission
Clock Lane
Data Lane
Dp/Dn
T
T
T
HS-SYNC
LPX
HS-ZERO
Disconnect
Terminator
THS-PREPARE
VIH(min)
VIL(max)
T
REOT
Capture
1st Data Bit
T
D-TERM-EN
LP-01
T
LP-11
HS-SKIP
LP-11
LP-00
T
EOT
HS-TRAIL
T
HS-SETTLE
T
T
HS-EXIT
Figure 4. High Speed Data Transmission Burst
12
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Disconnect
Terminator
Clock Lane
Dp/Dn
T
CLK-SETTLE
T
T
EOT
CLK-POST
TCLK-TERM-EN
T
CLK-MISS
VIH(min)
VIL(max)
T
T
T
LPX
T
T
CLK-PRE
CLK-TRAIL
HS-EXIT
CLK-ZERO
T
CLK-PREPARE
Data Lane
Dp/Dn
T
HS-PREPARE
Disconnect
Terminator
T
LPX
VIH(min)
VIL(max)
T
HS-SKIP
T
D-TERM-EN
T
HS-SETTLE
Figure 5. Switching the Clock Lane between Clock Transmission and Low-Power Mode
VS
(internal Node)
Vertical Blanking
1st
Line
2nd
Line
Last
Line
DE
(internal Node)
DATA1±
or
DATA0±
1 to 216
t
LPX
Line
Packet
Line
Packet
Line
Packet
Line
Packet
FS
FE
FS
LPS
LPS
LPS
LPS
LPS
LPS
LPS
LPS
Frame
Sync
Packet
Line
Packet
Figure 6. Long Line Packets and Short Frame Sync Packets
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SDA
t
BUF
t
t
LOW
t
f
t
HD;STA
r
t
t
SP
t
f
r
SCL
t
t
HD;STA
SU;STA
t
SU;STO
t
HIGH
t
t
SU;DAT
HD;DAT
STOP START
START
REPEATED
START
Figure 7. Serial Control Bus Timing Diagram
14
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5.8 Typical Characteristics
Time (50 ns/DIV)
Time (50 ns/DIV)
Figure 8. CSI-2 D0± End of Transmission
Figure 9. CSI-2 D0± Start of Transmission
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6 Detailed Description
6.1 Overview
The DS90UR910-Q1 recovers RBG data and sync signals from a FPD-Link II AC coupled serial bit stream, and
converts the recovered data into packetized CSI-2 data format. The CSI-2 output serial interface greatly reduces
the interconnect and signal count to a graphic processing unit and eases system designs for video streams from
multiple automotive driver assist cameras.
The DS90UR910-Q1 is based on the DS90UR906Q de-serializer core. Please refer to the DS90UR906Q
datasheet for the functionality and performance of the FPD-Link II interface can be found in the DS90UR906Q
datasheet.
The DS90UR910-Q1 conforms to the MIPI CSI-2 and DPHY standards for protocol and electrical specifications.
Compliant with standards:
•
•
Conforms with MIPI Alliance Specification for D-PHY, version 1.00.00, dated May 14, 2009
Compatible with MIPI Alliance Standard for Camera Serial Interface 2 (CSI-2) Version 1.01, dated Nov 9,
2010
The DS90UR910-Q1 receives 24-bit (or 18-bit) RGB data and 3 low speed control signals (VS, HS, DE) over a
serial FPD-Link II transmitted through a single twisted pair. It supports a pixel clock of 10 MHz to 75 MHz,
corresponding to the serial line rate of 280 Mb/s to 2100 Mb/s. The serial bit stream contains the scrambled 24-
bit data, an embedded clock, encoded control signals and DC balance information which enhances signal quality
and supports AC coupling.
The DS90UR910-Q1 is compatible with FPD-Link II serializers such as DS90UR905Q, DS90UR241Q,
DS90C241Q, DS90UR907Q, DS99R421Q and DS90UH/UB/92x FPD-Link III serializers in backward
compatibility mode. The serial bit stream is illustrated in Figure 10. In each pixel clock cycle, a 28-bit frame is
transmitted over the FPD-Link. The frame contains C1 and C0 representing the embedded clock information. C1
is always high and C0 is always low. Payload bits b[23:0] contain the scrambled 24-bit RGB data. DCB is the DC
balance bit and is used to minimize the DC offset on the signal line. DCA is used to validate the data integrity in
the embedded data stream and contain the encoded control signals VS, HS and DE (DS90UR905Q,
DS90UR907Q and DS90UH/UB/92x in backward compatible mode).
b
1
0
b
1
1
D
C
A
b
0
b
1
b
2
b
3
b
5
b
9
C
1
b
4
b
6
b
7
b
8
D
C
B
b
1
2
b
1
3
b
1
4
b
1
5
b
1
6
b
1
7
b
1
8
b
1
9
b
2
0
b
2
1
b
2
2
b
2
3
C
0
Figure 10. FPD-Link II Serial Stream
The DS90UR910-Q1 supports compatibility to FPD-Link II serializers and FPD-Link III serializers in backward
compatible mode as defined in Table 1.
Table 1. DS90UR910-Q1 Configuration Modes
CON
FIG1
CON
FIG0
Mode
FPD-Link II Compatibility
CSI-2 Data
Format
0
0
Normal Mode, Control Signal Filter disabled
DS90UR905Q 24-bit
RGB888
DS90UR907Q 24-bit
DS90UH/UB/92x Serializers 24-bit
0
1
Normal Mode, Control Signal Filter enabled
DS90UR905Q 24-bit
RGB888
DS90UR907Q 24-bit
DS90UH/UB/92x Serializers 24-bit
1
1
0
1
Backwards Compatible GEN2
Backwards Compatible GEN1
DS90UR241Q 18-bit
DS99R421Q 18-bit
RGB888
RGB888
DS90C241Q 18-bit
16
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6.2 Functional Block Diagram
CMF
DATA1+
D-PHY
Lane
Module
50W
50W
DATA1-
RIN+
RIN-
DATA0+
DATA0-
D-PHY
Lane
Module
EQ[3:1]
CLK+
CLK-
D-PHY
Lane
Module
Error
Detector
CONFIG[1:0]
PDB
PHY
Timing and Control
Timing
and
Control
SCL
SCA
Clock/Data
Recovery
ID[1:0]
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6.3 Feature Description
6.3.1 Input Receive Equalization
The input equalizer of the DS90UR910-Q1 is designed to compensate the attenuation distortion results from
cable of different length or wire gauge. The equalizer gain setting is controlled by the control pins EQ[3:1] or
through register programming. Users can optimize the equalizer’s gain setting along with the de-emphasis level
of the DS90UR905Q/907Q to achieve the optimum jitter performance.
Note this function cannot be seen at the RIN+/- input but can be observed at the serial test port (CMLOUT+/-)
enabled via the Serial Bus control registers. The equalization feature may be controlled by the external pin or by
register.
Table 2. Receiver Equalization Configuration
INPUTS EQ[3:1]
EQ Boost
EQ3
0
EQ2
0
EQ1
1
~3 dB
~4.5 dB
~6 dB
0
1
0
0
1
1
1
0
0
~7.5 dB
~9 dB
1
0
1
1
1
0
~10.5 dB
~12 dB
1
1
1
(1)
0
0
0
See
(1) Default Setting is EQ = Off
6.3.2 CSI-2 Interface
The DS90UR910-Q1 (in default mode) takes the RGB data bits R[7:0], G[7:0] and B[7:0] defined in the 24-bit
serializer pinout and directly maps to the RGB888 color space in the data frame. The DS90UR910-Q1 follows the
General Frame Format as described in Figure 49 of the CSI-2 standard (repeated here in Figure 11). Upon the
end of the vertical sync pulse (VS), the DS90UR910-Q1 generates the Frame End and Frame Start
synchronization packets within the vertical blanking period. The timing of the Frame Start will not reflect the
timing of the VS signal.
Upon the rising edge of the DE signal, each active line is output in a long data packet with the RGB888 data
format. At the end of each packet, the data lanes DATA0± and DATA1± return to the LP-11 state, while the clock
lane CLK± continue outputting the high speed clock.
18
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Frame Blanking
FS
Line Blanking
Line Data
FE
Frame Blanking
(1 to N) t
LPX
FS
Line Blanking
Line Data
FE
Frame Blanking
Figure 11. General Frame Format
6.3.3 High Speed Clock and Data
The high speed clock and data outputs are source synchronous interface. The half rate clock at CLK± is derived
from the pixel clock sourced by the clock/data recovery circuit of the DS90UR910-Q1. The clock frequency is 6
times the Pixel clock frequency. The 24-bit recovered RGB data is serialized and output at the 2 high speed data
lanes DATA0± and DATA1± in according to the CSI-2 protocol. The data rate of each lane is 12 times the Pixel
clock. As an example, at a pixel clock of 75 MHz, the CLK± runs at 450 MHz, and the data lanes run at 900
Mb/s.
The half-rate clock maintains a quadrature phase relationship to the data signals and allows receiver to sample
data at the rising and falling edges of the clock. Figure 3 shows the timing relationship of the clock and data
lines. The DS90UR910-Q1 supports continuous high speed clock.
High speed data are sent out at DATA0± and DATA1± in bursts. In between data bursts, the data lanes return to
Low Power States in according to protocol defined in D-PHY standard. The rising edge of the differential clock
(CLK+ – CLK-) is sent during the first payload bit of a transmission burst in the data lanes.
The DS90UR910-Q1 recovers the data bits R[7:0], G[7:0], B[7:0], VS, HS and DE from the serial FPD-Link II bit
stream at RIN±. During the vertical blanking period (VS goes low), it sends the short Frame End packet, followed
by a short Frame Start packet. User can program the time between Frame End to Frame Start packets from 0 to
(216-1) in units of 8*pclk_period/3.
6.3.4 Non-continuous/Continuous Clock
DS90UR910-Q1 D-PHY supports Continuous clock mode and Non-Continuous clock mode. Default mode is
Non-Continuous Clock mode, where the Clock Lane enters in LP mode between the transmissions of data
packets. Non-continuous clock mode will only be non-continuous during the vertical blanking period for lower
PCLK rates. For higher PCLK rates, the clock will be non-continuous between line and frame packets. Operating
modes are configurable through CCI.
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Clock lane enters LP11 during horizontal blanking if the horizontal blanking period is longer than the overhead
time to start/stop the clock lane. There is auto-detection of the length of the horizontal blank period. The
threshold is 70 PCLK cycles. Register bit available to disable off the non-continuous clock mode
6.3.5 Data Frame RGB Mapping
Table 3 shows the pixel data R[7:0], G[7:0 and B[7:0] defined in DS90UR905Q/907Q and DS90UH/UB/92x
Serializers pinout, which are recovered by the DS90UR910-Q1 and output in RGB888 format (data type 0x24) at
the CSI-2 interface.
Table 3. CSI-2 RGB888 Data Format with FPD-Link II Serializer (24-bit mode)
FPD-Link II (24-bit)
pin name
RGB888 Data bits
R[0]
R[1]
R[2]
R[3]
R[4]
R[5]
R[6]
R[7]
G[0]
G[1]
G[2]
G[3]
G[4]
G[5]
G[6]
G[7]
B[0]
B[1]
B[2]
B[3]
B[4]
B[5]
B[6]
B[7]
HS
R[0]
R[1]
R[2]
R[3]
R[4]
R[5]
R[6]
R[7]
G[0]
G[1]
G[2]
G[3]
G[4]
G[5]
G[6]
G[7]
B[0]
B[1]
B[2]
B[3]
B[4]
B[5]
B[6]
B[7]
VS
DE
DE
LANE1
DATA0±
CRC_byte0
Gn
. . .
SoT
SoT
ID
WC_byte1
B1
G1
R1
B2
G2
R2
Rn-1
EoT
EoT
LPS
LPS
LPS
LPS
LANE2
DATA1±
CRC_byte1
WC_byte0
ECC
. . .
Bn
Rn
Figure 12. DATA0± and DATA1± packet format in according to CSI-2 protocol for RGB888
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Table 4. CSI-2 Data Format with FPD-Link II Serializers (18-bit mode)
FPD-Link II (18-bit)
RGB Data bits
CSI-2 RGB888
Data bits
pin name
R[0]
R[1]
R[2]
R[3]
R[4]
R[5]
R[6]
R[7]
G[0]
G[1]
G[2]
G[3]
G[4]
G[5]
G[6]
G[7]
B[0]
B[1]
B[2]
B[3]
B[4]
B[5]
B[6]
B[7]
DIN[0]
DIN[1]
DIN[2]
DIN[3]
DIN[4]
DIN[5]
R[0]
R[1]
R[2]
R[3]
R[4]
R[5]
DIN[6]
DIN[7]
DIN[8]
DIN[9]
DIN[10]
DIN[11]
G[0]
G[1]
G[2]
G[3]
G[4]
G[5]
DIN[12]
DIN[13]
DIN[14]
DIN[15]
DIN[16]
DIN[17]
DIN[18]
DIN[19]
DIN[20]
B[0]
B[1]
B[2]
B[3]
B[4]
B[5]
HS
VS
DE
6.3.6 Serial Control Bus (CCI/I2C)
The DS90UR910-Q1 can be configured by the use of the I2C or CCI (Camera Control Interface) as defined by
MIPI, which is a bi-directional, half-duplex, serial control bus consists of SDA and SCL. The SDA is the bi-
directional data line. The SCL is the serial clock line. Both SCL and SDA are driven by open drain drivers and
required external pull-up resistors to VDDIO. The signals are either driven low or pulled high.
The DS90UR910-Q1 is a CCI slave. ID[1:0] pins select one of the four CCI slave addresses (see Table 5).
Table 5. CCI/I2C Slave Address
ID[1]
ID[0]
7-bit slave address
011 1100 (0x3C’h)
011 1101 (0x3D’h)
011 0110 (0x36’h)
011 0111 (0x37’h)
8-bit slave address (0 appended WRITE)
0111 1000 (0x78’h)
0
0
1
1
0
1
0
1
0111 1010 (0x7A’h)
0110 1100 (0x6C’h)
0110 1110 (0x6E’h)
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The Serial Bus protocol is initiated by START or START-REPEATED, and terminated by STOP condition. A
START occurs when SDA transitions low while SCL is high. A STOP occurs when SDA transitions high when
SCL is high. See Figure 13.
SDA
SCL
S
P
START condition, or
STOP condition
START repeat condition
Figure 13. START and STOP Conditions
To communicate with a remote device, the host controller (master) sends the 7-bit slave address followed by a
write-bit (0), and listens for a response from the slave. This response is referred to as an acknowledge bit. If the
slave on the bus is addressed correctly, it acknowledges the master by driving the SDA low (ACK). If the address
does not match a device’s slave address, it negative acknowledges the master by letting SDA be pulled high
(NACK). In a write operation from master to slave, the master sends the 8-bit index address of the register that it
wants to access. After the slave ACKs, the master sends the 8-bit data byte. The slave ACKs after each data
byte is successfully received and is ready to receive another byte into the next sequential index location. At the
end of the data transfer, the master ends the transaction with a STOP condition.
In a read operation, the master first sends the 8-bit index address of the register that it wants to access. After
receiving an ACK from the slave, it initiates a START-REPEAT condition, sends the 7-bit slave address followed
by the read-bit (1). The slave ACKs and sends out the 8-bit data byte. The master acknowledges an ACK when
another data byte will be sent to the next sequential index address. The master acknowledges an NACK when
no more data byte will be sent, and ends the transaction with a STOP condition.
The CCI interface of the DS90UR910-Q1 supports Standard mode (<100KHz) or Fast mode (<400KHz) with 8-bit
index addressing and 8-bit data transfer. It supports the following read/write operations between the
DS90UR910-Q1 and the CCI master:
•
•
•
•
•
•
Single read from random location
Single read from current location
Sequential read starting from a random location
Sequential read starting from the current location
Single write to a random location
Sequential write starting from a random location
22
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ZHCSDL5D –JUNE 2012–REVISED JULY 2015
Single Read from random location
SLAVE
ADDRESS
SUB
ADDRESS
SLAVE
ADDRESS
S
r
S
0 A
A
1 A
DATA
A P
Single Read from the current location
SLAVE
ADDRESS
S
1 A
DATA
A P
Sequential Read from a random location
SLAVE
ADDRESS
SUB
ADDRESS
SLAVE
ADDRESS
S
r
S
0 A
A
1 A
DATA
A
DATA
A P
Sequential Read from current location
SLAVE
ADDRESS
S
1 A
DATA
A
DATA
DATA
A
DATA
A P
Single Write from random location
SLAVE
ADDRESS
SUB
ADDRESS
A/
A
S
0 A
A
A
P
Sequential Write
SLAVE
ADDRESS
SUB
ADDRESS
A/
P
S
0 A
DATA
A
DATA
A
Figure 14. I2C/CCI Read/Write Operations
6.3.7 Ultra Low Power State
DS90UR910-Q1 D-PHY Lanes will enter ULPS mode upon software standby mode through CCI generated by
Application Processor. When ULPS is entered, all lanes including the clock and data lanes are put in ULPS
according to the MIPI D-PHY protocol. D-PHY can reduce power consumption by entering ULPS mode.
Ultra-Low Power State Entry Command is sent after an Escape mode Entry command through CCI, and then
Lane shall enter the Ultra-Low Power State (ULPS). When ULPS is entered, all lanes including the clock and
data lanes are put in ULPS according to the MIPI DPHY protocol. Typically an ULPS entry command is used but
other sequences can be used also. Ultra-Low Power State is exited by means of a Mark-1 state with a length
TWAKEUP followed by a Stop state. Reference: [1] D-PHY Specification, Section 5.6.3, Line 895
Frame
End
Stop
(LP11)
Escape
Mode
ULPS
(LP00)
Mark-1
(LP10)
Stop
(LP11)
Ultra-Low-Power-State Entry Command 00011110
Clock Lane
Dp/Dn
Data Lane
Dp/Dn
t
t
INIT
WAKEUP
t
LPX
Figure 15. Ultra-Low Power State
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6.3.8 Display Timing Requirements
Table 6 shows the supported display resolutions for the DS90UR910-Q1. The display timings assume an
estimated overall blanking rate of 1.2. The DS90UR910-Q1 will automatically detect the incoming data rate by
from the frame rate (by measuring VS). This timing is then mapped into a look up table. The lookup table is used
for any pixel rate from PCLK of 10 MHz to 65 MHz. The limitation that it assumes the frame rate is 60fps and
30fps. An override option will be available to set each of the parameter individually for a data rate that is not
listed in the table. Option is programmed through CCI. Operation of frequencies above 65 MHz require additional
I2C/CCI programming of CSI_TIMING registers.
Table 6. DS90UR910-Q1 Supported Resolution and Refresh Rates with Expected Blanking Period
Resolution
Hactive
(pixels)
Hblank
(pixels)
Htotal
(pixels)
Vactive
(lines)
Vblank
(lines)
Vtotal
(lines)
Frame size
(pixels)
Refresh
(Hz)
PClk (MHz)
400x240
640x240
800x480
1280x480
640x480
800x600
960x160
640x160
400
640
800
1280
640
800
960
640
40
40
440
680
240
240
480
480
480
600
160
160
5
5
245
245
485
485
509
628
165
165
107800
166600
407400
640200
399056
663168
165000
112200
60
60
60
60
60
60
60
60
6.468
9.996
40
840
5
24.444
38.412
23.94336
39.79008
9.9
40
1320
784
5
144
256
40
29
28
5
1056
1000
680
40
5
6.732
480x240
800x480
1280x480
960x540
1440x540
1000x600
480
800
96
576
960
240
480
480
540
540
600
24
48
48
54
54
60
264
528
528
594
594
660
152064
506880
811008
684288
1026432
792000
60
60
60
60
60
60
9.12384
30.4128
48.66048
41.05728
61.58592
47.52
160
256
192
288
200
1280
960
1536
1152
1728
1200
1440
1000
640x480
800x600
1024x768
1440x550
640
800
160
256
320
144
800
480
600
768
550
45
28
38
55
525
628
806
605
420000
663168
1083264
958320
60
60
60
60
25.2
1056
1344
1584
39.79008
64.99584
57.4992
1024
1440
800x480
800x480
800
800
256
256
52
1056
1056
1076
1076
1124
1124
1594
1594
480
480
480
480
480
480
550
550
45
45
24
24
48
48
55
55
525
525
504
504
528
528
605
605
554400
554400
542304
542304
593472
593472
964370
964370
60
30
60
30
60
30
60
30
33.264
16.632
1024x480
1024x480
1024x480
1024x480
1440x550
1440x550
1024
1024
1024
1024
1440
1440
32.53824
16.26912
35.60832
17.80416
57.8622
28.9311
52
100
100
154
154
24
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ZHCSDL5D –JUNE 2012–REVISED JULY 2015
6.4 Register Maps
Table 7. Serial Bus Control Registers
ADD
Register Name
Bit(s)
R/W
Default
Field
Description
(hex)
0x00
I2C_SLAVE_ID
7:1
0
R/W
R/W
0x30
0
DEVID
I2C slave ID
DEVID_EN
0: Address from ID[X] Pin
1: Address from Register
0x01
CONFIG1
7
R/W
0
LFMODE
If pin over write bit is one,
controls the LF Mode. Debug
only
6
5
R
0
0
Reserved
SLEW
Reserved
R/W
Control slew rate of LOCK,
PASS and GPIO
0: Normal slew
1: Increased Slew
4
R
0
0
Reserved
MODE
Reserved
3:2
R/W
00: Normal Mode, Control
Signal Filter Disabled
01: Normal Mode, Control
Signal Filter Enabled
10: Backwards Compatible
(GEN2)
11: Backwards Compatible
(GEN1)
(See Table 1)
1
0
R/W
R/W
0
0
SLEEP
Note – not the same function
as PowerDown (PDB pin)
0: Normal mode
1: Sleep Mode – Register
settings retained.
USEREG
0: Configurations set from
control pins / STRAP pins
1: Override EQ and CONFIG
strapped control inputs with
register settings
0x02
CONFIG2
7:6
5:4
R
0
Reserved
OMAP
Reserved
R/W
00
6 bits to 8 bits color mapping
00: bit 4, 5 repeated on LSB
01: LSB zero if all data is zero
10: LSB zero
11: LSB zero
3
R
0
Reserved
Reserved
EQ
Reserved
Reserved
2:0
7:4
R/W
R/W
3'b100
000
0x03
0x04
EQ Control
Override EQ pin input if
USEREG bit set
3:0
7
R
0
0
Reserved
CMLOUT
Reserved
CMLOUT Config
R/W
Loop through enable
0: Output CMLOUT+/- =
disabled
1: Output CMLOUT+/- =
enabled
6:0
R/W
R/W
0
0
VOD
VOD control
000000: min VOD
000001:
000011:
000111:
001111:
011111:
111111: max VOD
0x05->
0x10
NA
7:0
Reserved
Reserved
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www.ti.com.cn
Register Maps (continued)
Table 7. Serial Bus Control Registers (continued)
ADD
(hex)
Register Name
Bit(s)
R/W
R/W
R/W
Default
Field
Description
0x11
CSI config
7
6
0
0
CCI_INV_VS
CCI_CONT_CLOCK
0: VS is active low pulse
1: VS is active high pulse
0: CSI-2 non-continuous clock
1: CSI-2 continuous clock
5:2
1
R/W
R/W
0
0
Reserved
Reserved
CCI_EXTERNAL_TIMING
0: Use computed DPHY timing
based on frame length
1: Use manual override values
for DPHY timing
0
R/W
R/W
0
0
CCI_INV_DE
0: DE is active low pulse
1: DE is active high pulse
0x12
0x13
0x14
CSI_FRM_GAP_0
CSI_FRM_GAP_1
CSI_TIMING0
7:0
CSI_FRM_GAP_0
Defined the delay between the
start frame and end frame
packet (lower byte)
7:0
R/W
0
CSI_FRM_GAP_1
Defined the delay between the
start frame and end frame
packet (upper byte)
7:5
4:0
0
0
Reserved
Reserved
R/W
R/W
R/W
R/W
R/W
TCLK_PREPARE
Defines the Tclk_prepare
parameter if
CCI_EXTERNAL_TIMING is
set
0x15
0x16
0x17
CSI_TIMING1
CSI_TIMING2
CSI_TIMING3
7:3
2:0
7:4
3:0
0
0
0
0
TCLK_ZERO
TCLK_TRAIL
TCLK_POST
THS_ZERO
Defines the Tclk_zero
parameter if
CCI_EXTERNAL_TIMING is
set
Defines the Tclk_trail
parameter if
CCI_EXTERNAL_TIMING is
set
Defines the Tclk_post
parameter if
CCI_EXTERNAL_TIMING is
set
Defines the Ths_zero
parameter if
CCI_EXTERNAL_TIMING is
set
7
R/W
R/W
0
0
Reserved
Reserved
6:4
THS_TRAIL
Defines the Ths_trail
parameter if
CCI_EXTERNAL_TIMING is
set
3:0
7:3
2:0
R/W
R/W
R/W
0
0
0
THS_EXIT
THS_PREPARE
TLPX
Defines the Ths_exit
parameter if
CCI_EXTERNAL_TIMING is
set
0x18
CSI_TIMING4
Defines the Ths_prepare
parameter if
CCI_EXTERNAL_TIMING is
set
Defines the Ths_exit
parameter if
CCI_EXTERNAL_TIMING is
set
26
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ZHCSDL5D –JUNE 2012–REVISED JULY 2015
Register Maps (continued)
Table 7. Serial Bus Control Registers (continued)
ADD
Register Name
Bit(s)
R/W
Default
Field
Description
(hex)
0x19
CSI_ULPS
7:3
1
R/W
R/W
0
0
Reserved
Reserved
ULPS_MODE
0: In ULPS mode, data lane off
1: In ULPS mode, data lane
off, clock lane off, x6 PLL off
0
R/W
0
ULPS_EN
0: Disable UPLS mode
1: Enable ULPS mode
0x1A
0x1B
NA
7:0
7
R/W
R/W
R/W
0
0
Reserved
Reserved
Reserved
CSI_UNH1
Reserved
6:5
0x1
ACT_VERT_MSB
MSBs of active vertical UNH
image
4:3
R/W
0x2
TOT_VERT_MSB
MSBs of total vertical UNH
image
2:1
0
R/W
R/W
0
0
Reserved
PATGEN
Reserved
0: Normal mode
1: Enable pattern generator
mode
0x1C
0x1D
0x1E
CSI_UNH2
CSI_UNH3
CSI_UNH4
7:0
7:0
R/W
R/W
0x0F
0xDF
TOT_VERT_LSB
ACT_VERT_LSB
LSBs of total vertical UNH
image
LSBs of active vertical UNH
image
7:6
5:3
R/W
R/W
0
Reserved
Reserved
0x4
ACT_HORIZ_MSB
MSBs of active horizontal UNH
image
2:0
7:0
7:0
R/W
R/W
R/W
0x5
TOT_HORIZ_MSB
ACT_HORIZ_LSB
TOT_HORIZ_LSB
MSBs of total horizontal UNH
image
0x1F
0x20
CSI_UNH5
CSI_UNH6
0xFF
0xFF
LSBs of active horizontal UNH
image
LSBs of total horizontal UNH
image
0x21
0x22
0x23
CSI_UNH7
CSI_UNH8
CSI_UNH9
7:0
7:0
7:0
R/W
R/W
R/W
0x09
0x09
0x09
PORCH_VERT
SYNC_VERT
Vertical porch size UNH image
Vertical sync size UNH image
PORCH_HORIZ
Horizontal porch size UNH
image
0x24->
0x2F
NA
7:0
R/W
0
Reserved
Reserved
0x30
0x31
0x32
0x33
0x33
0x35
0x36
CSI_ID0
CSI_ID1
CSI_ID2
CSI_ID3
CSI_ID4
CSI_ID5
CSI_REVID
NA
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
R
R
R
R
R
R
R
R
0x5F
0x55
0x52
0x39
0x31
0x30
0x01
0
CID0
Chip ID, character "_"
Chip ID, character "U"
Chip ID, character "R"
Chip ID, character "9"
Chip ID, character "1"
Chip ID, character "0"
Revision ID of the design
Reserved
CID1
CID2
CID3
CID4
CID5
CID5
0x37->
0x3A
Reserved
0x3B
REVID
NA
7:0
7:0
R
R
0x01
0
REVID
Revision ID of the design
Reserved
0x3C->
0x3F
Reserved
0x40->
0xFF
Address range 0x00 to 0x3F
aliases into the full address
space.
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7 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
7.1 Typical Application Connection
Figure 16 shows a typical application of the DS90UR910-Q1 in Pin control mode for a 24-bit Color Display
Application. The LVDS signals require 100 nF AC coupling capacitors to the line. The line driver includes internal
termination. Bypass capacitors are placed near the power supply pins. At a minimum, four 0.1 µF capacitors and
a 4.7 µF capacitor should be used for local device bypassing. System GPO (General Purpose Output) signals
control the PDB and BISTEN pins. The interface to the host is with 1.8 V LVCMOS levels, thus the VDDIO pin is
connected also to the 1.8V rail. The Optional I2C/CCI is connected to the Host bus in this example, thus the SCL
and SDA pins are using pull-up resistors R to VDDIO. A delay cap is placed on the PDB signal to delay the
enabling of the device until power is stable.
1.8V
3.3V
1.8V
FB1
2.2 µF
ceramic
0.1 µF
0.1 µF
0.1 µF
FB1, FB2:
1 kΩ @100 MHz
DC R < 1Ω
FB2
VDDCSI VDDL
0.1 µF
VDDA
VDDP
VDDIO
2.2 µF
ceramic
0.1 µF
4.7 µF
ceramic
Data1+
Data1-
0.1 µF
Data0+
Data0-
RIN+
CMF
RIN-
GPU
From FPD-Link II
Serializer
CLK+
CLK-
100Ω STP
0.1 µF
4.7 µF
ceramic
VDDIO
DS90UR910-Q1
R
R
SCL
SDA
CMLOUT+
100W (1%)
CMLOUT-
CONFIG[1:0]
EQ[3:1]
Strap
High or Low
LOCK
Optional
Control pins
BISTEN
PASS
ID[1:0]
RES
GND
DAP
VDDIO
10 kW
PDB
10 µF
Figure 16. DS90UR910-Q1 Typical Connection Diagram — Pin Control
7.2 Design Requirements
For the typical design application, use the following as input parameters.
28
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ZHCSDL5D –JUNE 2012–REVISED JULY 2015
Design Requirements (continued)
Table 8. Design Parameters
Design Parameter
VDDIO
Example Value
1.8V or 3.3V
1.8V
VDDL, VDDA, VDDP, VDDCSI
AC Coupling Capacitor for RIN0± and RIN1±
100nF
The SER/DES supports only AC-coupled interconnects through an integrated DC-balanced decoding scheme.
External AC coupling capacitors must be placed in series in the FPD-Link II signal path as illustrated in
Figure 17.
D
+
OUT
R
IN
+
SER
DES
R
IN
-
D
-
OUT
Figure 17. AC-Coupled Connection
For high-speed FPD–Link II transmissions, the smallest available package should be used for the AC coupling
capacitor. This will help minimize degradation of signal quality due to package parasitics. The I/O’s require 100nF
AC coupling capacitors to the line.
7.3 Application Performance Plots
The plot below corresponds to 49MHz PCLK UNH pattern.
Time (250 ps/DIV)
Figure 18. Loop-through CML Output at 1.372 Gbps Serial Line Rate
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8 Power Supply Recommendations
8.1 Power Up Requirements and PDB Pin
The VDD (VDDn and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms
then a capacitor on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the
recommended operating voltage. When PDB pin is pulled to VDDIO, it is recommended to use a 10 kΩ pull-up and
a >10 uF cap to GND to delay the PDB input signal.
9 Layout
9.1 Layout Guidelines
9.1.1 Transmission Media
The Ser/Des chipset is intended to be used in a point-to-point configuration, through a PCB trace, or through
twisted pair cable. The Ser and Des provide internal terminations providing a clean signaling environment. The
interconnect for LVDS should present a differential impedance of 100 Ohms. Use cables and connectors that
have matched differential impedance to minimize impedance discontinuities. Shielded or un-shielded cables may
be used depending upon the noise environment and application requirements.
9.1.2 PCB Layout and Power System Considerations
Circuit board layout and stack-up for the LVDS Ser/Des devices should be designed to provide low-noise power
feed to the device. Good layout practice will also separate high frequency or high-level inputs and outputs to
minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly
improved by using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane
capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at
high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the
tantalum capacitors should be at least 5X the power supply voltage being used.
Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power
entry. This is typically in the 50uF to 100uF range and will smooth low frequency switching noise. It is
recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors
connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external
bypass capacitor will increase the inductance of the path.
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size
reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20-30 MHz. To provide effective bypassing, multiple
capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At
high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing
the impedance at high frequency.
Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate
switching noise effects between different circuit sections. Separate PCB planes are typically not required. Pin
Description tables typically provide guidance on which circuit blocks are connected to which power pin pairs. In
some cases, an external filter many be used to provide clean power to sensitive circuits such as PLLs.
Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the LVDS
lines to prevent coupling from the LVCMOS lines to the LVDS lines. Closely-coupled differential lines of 100
Ohms are typically recommended for LVDS interconnect. The closely coupled lines help to ensure that coupled
noise will appear as common-mode and thus is rejected by the receivers. The tightly coupled lines will also
radiate less.
Information on the WQFN style package is provided in Application Note: AN-1187 / SNOA401.
30
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ZHCSDL5D –JUNE 2012–REVISED JULY 2015
Layout Guidelines (continued)
9.1.3 CSI-2 Guidelines
1. CSI0_D*P/N and CSI1_D*P/N pairs should be routed with controlled 100-Ohm differential impedance (±
20%) or 50-Ohm single-ended impedance (±15%)
2. Keep away from other high speed signals
3. Keep length difference between a differential pair to 5 mils max
4. Length matching should be near the location of mismatch.
5. Match trace lengths between pairs to be < 25 mils.
6. Each pair should be separated at least by 3 times the signal trace width
7. The use of bends in differential traces should be kept to a minimum. When bends are used, the number of
left and right bends should be as equal as possible and the angle of the bend should be ≥ 135 degrees. This
arrangement minimizes any length mismatch caused by the bends and therefore minimizes the impact that
bends have on EMI.
8. Route all differential pairs on the same layer
9. The number of VIAS should be kept to a minimum. It is recommended to keep the VIA count to 2 or less
10. Keep traces on layers adjacent to ground plane
11. Do NOT route differential pairs over any plane split
12. Adding Test points will cause impedance discontinuity and will therefore negatively impact signal
performance. If test points are used, they should be placed in series and symmetrically. They must not be
placed in a manner that causes a stub on the differential pair
Copyright © 2012–2015, Texas Instruments Incorporated
31
DS90UR910-Q1
ZHCSDL5D –JUNE 2012–REVISED JULY 2015
www.ti.com.cn
Layout Guidelines (continued)
9.1.4 Layout Example
Figure 19 (PCB layout example) is derived from a layout design of the DS90UR910-Q1 EVM. This graphic and
additional layout description are used to demonstrate both proper routing and proper solder techniques when
designing in the Deserializer.
Length-Matched
CSI-2 Traces
AC-Coupling
Capacitors
Figure 19. DS90UR910-Q1 Deserializer Example Layout
32
Copyright © 2012–2015, Texas Instruments Incorporated
DS90UR910-Q1
www.ti.com.cn
ZHCSDL5D –JUNE 2012–REVISED JULY 2015
Layout Guidelines (continued)
9.1.5 LVDS Interconnect Guidelines
See AN-1108 and AN-905 for full details.
•
•
Use 100Ω coupled differential pairs
Use the S/2S/3S rule in spacings
–
–
–
S = space between the pair
2S = space between pairs
3S = space to LVCMOS signal
•
•
•
•
Minimize the number of Vias and skew within the pair
Use differential connectors when operating above 500 Mbps line speed
Maintain balance of the traces
Terminate as close to the TX outputs and RX inputs as possible
Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the Texas
Instruments web site at: www.ti.com/lvds
10 器件和文档支持
10.1 商标
TRI-STATE is a registered trademark of National Semiconductor Corporation.
All other trademarks are the property of their respective owners.
10.2 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
10.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
11 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。要获得这份数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2012–2015, Texas Instruments Incorporated
33
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JESD48 最新标准中止提供任何产品和服务。客户在下订单前应获取最新的相关信息, 并验证这些信息是否完整且是最新的。所有产品的销售
都遵循在订单确认时所提供的TI 销售条款与条件。
TI 保证其所销售的组件的性能符合产品销售时 TI 半导体产品销售条件与条款的适用规范。仅在 TI 保证的范围内，且 TI 认为 有必要时才会使
用测试或其它质量控制技术。除非适用法律做出了硬性规定，否则没有必要对每种组件的所有参数进行测试。
TI 对应用帮助或客户产品设计不承担任何义务。客户应对其使用 TI 组件的产品和应用自行负责。为尽量减小与客户产品和应 用相关的风险，
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TI 不对任何 TI 专利权、版权、屏蔽作品权或其它与使用了 TI 组件或服务的组合设备、机器或流程相关的 TI 知识产权中授予 的直接或隐含权
限作出任何保证或解释。TI 所发布的与第三方产品或服务有关的信息，不能构成从 TI 获得使用这些产品或服 务的许可、授权、或认可。使用
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及其后果、降低有可能造成人身伤害的故障的发生机率并采取适当的补救措施。客户将全额赔偿因 在此类安全关键应用中使用任何 TI 组件而
对 TI 及其代理造成的任何损失。
在某些场合中，为了推进安全相关应用有可能对 TI 组件进行特别的促销。TI 的目标是利用此类组件帮助客户设计和创立其特 有的可满足适用
的功能安全性标准和要求的终端产品解决方案。尽管如此，此类组件仍然服从这些条款。
TI 组件未获得用于 FDA Class III（或类似的生命攸关医疗设备）的授权许可，除非各方授权官员已经达成了专门管控此类使 用的特别协议。
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法律和法规要求。
TI 已明确指定符合 ISO/TS16949 要求的产品，这些产品主要用于汽车。在任何情况下，因使用非指定产品而无法达到 ISO/TS16949 要
求，TI不承担任何责任。
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www.ti.com/consumer-apps
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www.ti.com.cn/logic
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IMPORTANT NOTICE
邮寄地址： 上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122
Copyright © 2016, 德州仪器半导体技术（上海）有限公司
重要声明
德州仪器(TI) 及其下属子公司有权根据 JESD46 最新标准, 对所提供的产品和服务进行更正、修改、增强、改进或其它更改， 并有权根据
JESD48 最新标准中止提供任何产品和服务。客户在下订单前应获取最新的相关信息, 并验证这些信息是否完整且是最新的。所有产品的销售
都遵循在订单确认时所提供的TI 销售条款与条件。
TI 保证其所销售的组件的性能符合产品销售时 TI 半导体产品销售条件与条款的适用规范。仅在 TI 保证的范围内，且 TI 认为 有必要时才会使
用测试或其它质量控制技术。除非适用法律做出了硬性规定，否则没有必要对每种组件的所有参数进行测试。
TI 对应用帮助或客户产品设计不承担任何义务。客户应对其使用 TI 组件的产品和应用自行负责。为尽量减小与客户产品和应 用相关的风险，
客户应提供充分的设计与操作安全措施。
TI 不对任何 TI 专利权、版权、屏蔽作品权或其它与使用了 TI 组件或服务的组合设备、机器或流程相关的 TI 知识产权中授予 的直接或隐含权
限作出任何保证或解释。TI 所发布的与第三方产品或服务有关的信息，不能构成从 TI 获得使用这些产品或服 务的许可、授权、或认可。使用
此类信息可能需要获得第三方的专利权或其它知识产权方面的许可，或是 TI 的专利权或其它 知识产权方面的许可。
对于 TI 的产品手册或数据表中 TI 信息的重要部分，仅在没有对内容进行任何篡改且带有相关授权、条件、限制和声明的情况 下才允许进行
复制。TI 对此类篡改过的文件不承担任何责任或义务。复制第三方的信息可能需要服从额外的限制条件。
在转售 TI 组件或服务时，如果对该组件或服务参数的陈述与 TI 标明的参数相比存在差异或虚假成分，则会失去相关 TI 组件 或服务的所有明
示或暗示授权，且这是不正当的、欺诈性商业行为。TI 对任何此类虚假陈述均不承担任何责任或义务。
客户认可并同意，尽管任何应用相关信息或支持仍可能由 TI 提供，但他们将独力负责满足与其产品及在其应用中使用 TI 产品 相关的所有法
律、法规和安全相关要求。客户声明并同意，他们具备制定与实施安全措施所需的全部专业技术和知识，可预见 故障的危险后果、监测故障
及其后果、降低有可能造成人身伤害的故障的发生机率并采取适当的补救措施。客户将全额赔偿因 在此类安全关键应用中使用任何 TI 组件而
对 TI 及其代理造成的任何损失。
在某些场合中，为了推进安全相关应用有可能对 TI 组件进行特别的促销。TI 的目标是利用此类组件帮助客户设计和创立其特 有的可满足适用
的功能安全性标准和要求的终端产品解决方案。尽管如此，此类组件仍然服从这些条款。
TI 组件未获得用于 FDA Class III（或类似的生命攸关医疗设备）的授权许可，除非各方授权官员已经达成了专门管控此类使 用的特别协议。
只有那些 TI 特别注明属于军用等级或“增强型塑料”的 TI 组件才是设计或专门用于军事/航空应用或环境的。购买者认可并同 意，对并非指定面
向军事或航空航天用途的 TI 组件进行军事或航空航天方面的应用，其风险由客户单独承担，并且由客户独 力负责满足与此类使用相关的所有
法律和法规要求。
TI 已明确指定符合 ISO/TS16949 要求的产品，这些产品主要用于汽车。在任何情况下，因使用非指定产品而无法达到 ISO/TS16949 要
求，TI不承担任何责任。
产品
应用
www.ti.com.cn/telecom
数字音频
www.ti.com.cn/audio
www.ti.com.cn/amplifiers
www.ti.com.cn/dataconverters
www.dlp.com
通信与电信
计算机及周边
消费电子
能源
放大器和线性器件
数据转换器
DLP® 产品
DSP - 数字信号处理器
时钟和计时器
接口
www.ti.com.cn/computer
www.ti.com/consumer-apps
www.ti.com/energy
www.ti.com.cn/dsp
工业应用
医疗电子
安防应用
汽车电子
视频和影像
www.ti.com.cn/industrial
www.ti.com.cn/medical
www.ti.com.cn/security
www.ti.com.cn/automotive
www.ti.com.cn/video
www.ti.com.cn/clockandtimers
www.ti.com.cn/interface
www.ti.com.cn/logic
逻辑
电源管理
www.ti.com.cn/power
www.ti.com.cn/microcontrollers
www.ti.com.cn/rfidsys
www.ti.com/omap
微控制器 (MCU)
RFID 系统
OMAP应用处理器
无线连通性
www.ti.com.cn/wirelessconnectivity
德州仪器在线技术支持社区
www.deyisupport.com
IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2016, Texas Instruments Incorporated
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