DS91M040TSQE [TI]
IC,LINE TRANSCEIVER,4 DRIVER,4 RCVR,LLCC,32PIN,PLASTIC;
| 型号： | DS91M040TSQE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | IC,LINE TRANSCEIVER,4 DRIVER,4 RCVR,LLCC,32PIN,PLASTIC 驱动 驱动器 |
| 文件： | 总17页 (文件大小：455K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
National Semiconductor is now part of
Texas Instruments.
Search http://www.ti.com/ for the latest technical
information and details on our current products and services.
November 9, 2009
DS91M040
125 MHz Quad M-LVDS Transceiver
General Description
Features
■
The DS91M040 is a quad M-LVDS transceiver designed for
driving / receiving clock or data signals to / from up to four
multipoint networks.
DC - 125 MHz / 250 Mbps low jitter, low skew, low power
operation
Wide Input Common Mode Voltage Range allows up to
±1V of GND noise
■
M-LVDS (Multipoint LVDS) is a new family of bus interface
devices based on LVDS technology specifically designed for
multipoint and multidrop cable and backplane applications. It
differs from standard LVDS in providing increased drive cur-
rent to handle double terminations that are required in multi-
point applications. Controlled transition times minimize re-
flections that are common in multipoint configurations due to
unterminated stubs. M-LVDS devices also have a very large
input common mode voltage range for additional noise margin
in heavily loaded and noisy backplane environments.
Conforms to TIA/EIA-899 M-LVDS Standard
■
■
■
■
Pin selectable M-LVDS receiver type (1 or 2)
Controlled transition times (2.0 ns typ) minimize reflections
8 kV ESD on M-LVDS I/O pins protects adjoining
components
Flow-through pinout simplifies PCB layout
■
■
Small 5 mm x 5 mm LLP-32 space saving package
A single DS91M040 channel is a half-duplex transceiver that
accepts LVTTL/LVCMOS signals at the driver inputs and con-
verts them to differential M-LVDS signal levels. The receiver
inputs accept low voltage differential signals (LVDS, BLVDS,
M-LVDS, LVPECL and CML) and convert them to
3V LVCMOS signals. The DS91M040 supports both M-LVDS
type 1 and type 2 receiver inputs.
Applications
Multidrop / Multipoint clock and data distribution
■
■
High-Speed, Low Power, Short-Reach alternative to
TIA/EIA-485/422
Clock distribution in AdvancedTCA (ATCA) and
MicroTCA (μTCA, uTCA) backplanes
■
Typical Application
30042202
© 2009 National Semiconductor Corporation
300422
www.national.com
Ordering Information
Order Number
Receiver Input
Type 1 or 2
Function
Package Type
DS91M040TSQ
Quad M-LVDS Transciever
LLP-32
Connection Diagram
30042201
Logic Diagram
30042203
www.national.com
2
Pin Descriptions
Number
1, 3, 5, 7
Name
RO
I/O, Type
Description
O, LVCMOS Receiver output pin.
26, 28, 13, 15
RE
I, LVCMOS Receiver enable pin: When RE is high, the receiver is disabled.
When RE is low, the receiver is enabled. There is a 300 kΩ pullup
resistor on this pin.
25, 27, 14, 16
DE
I, LVCMOS Driver enable pin: When DE is low, the driver is disabled. When
DE is high, the driver is enabled. There is a 300 kΩ pulldown
resistor on this pin.
2, 4, 6, 8
31, DAP
DI
GND
A
I, LVCMOS Driver input pin.
Power
Ground pin and pad.
17, 19, 21, 23
18, 20, 22, 24
11, 12, 29, 30
32
I/O, M-LVDS Non-inverting driver output pin/Non-inverting receiver input pin
I/O, M-LVDS Inverting driver output pin/Inverting receiver input pin
B
VDD
FSEN1
Power
Power supply pin, +3.3V ± 0.3V
I, LVCMOS
Failsafe enable pin with a 300 kΩ pullup resistor. This pin
enables Type 2 receiver on inputs 0 and 2.
FSEN1 = L --> Type 1 receiver inputs
FSEN1 = H --> Type 2 receiver inputs
9
FSEN2
MDE
I, LVCMOS
Failsafe enable pin with a 300 kΩ pullup resistor. This pin
enables Type 2 receiver on inputs 1 and 3.
FSEN2 = L --> Type 1 receiver inputs
FSEN2 = H --> Type 2 receiver inputs
10
I, LVCMOS Master enable pin. When MDE is H, the device is powered up.
When MDE is L, the device overrides all other control and powers
down.
M-LVDS Receiver Types
The EIA/TIA-899 M-LVDS standard specifies two different
types of receiver input stages. A type 1 receiver has a con-
ventional threshold that is centered at the midpoint of the input
amplitude, VID/2. A type 2 receiver has a built in offset that is
100mV greater then VID/2. The type 2 receiver offset acts as
a failsafe circuit where open or short circuits at the input will
always result in the output stage being driven to a low logic
state.
30042240
FIGURE 1. M-LVDS Receiver Input Thresholds
3
www.national.com
Absolute Maximum Ratings (Note 4)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
ESD Susceptibility
HBM (Note 1)
≥8 kV
≥250V
≥1250V
MM (Note 2)
CDM (Note 3)
Power Supply Voltage
LVCMOS Input Voltage
LVCMOS Output Voltage
M-LVDS I/O Voltage
M-LVDS Output Short Circuit
Current Duration
Junction Temperature
Storage Temperature Range
Lead Temperature Range
Soldering (4 sec.)
Maximum Package Power Dissipation @ +25°C
SQ Package
−0.3V to +4V
−0.3V to (VDD + 0.3V)
−0.3V to (VDD + 0.3V)
−1.9V to +5.5V
Note 1: Human Body Model, applicable std. JESD22-A114C
Note 2: Machine Model, applicable std. JESD22-A115-A
Note 3: Field Induced Charge Device Model, applicable std.
JESD22-C101-C
Continuous
+140°C
−65°C to +150°C
Recommended Operating
Conditions
Min Typ Max Units
+260°C
Supply Voltage, VDD
3.0 3.3 3.6
V
V
Voltage at Any Bus Terminal
ꢀ(Separate or Common-Mode)
Differential Input Voltage VID
LVTTL Input Voltage High VIH
LVTTL Input Voltage Low VIL
Operating Free Air
−1.4
+3.8
3.91W
34 mW/°C above +25°C
Derate SQ Package
Package Thermal Resistance (4-Layer, 2 oz. Cu, JEDEC)
2.4
VDD
0.8
V
V
V
2.0
0
ꢀθJA
ꢀθJC
+29.4°C/W
+2.8°C/W
Temperature TA
−40 +25 +85
°C
DC Electrical Characteristics (Note 5, Note 6, Note 7, Note 9)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max Units
M-LVDS Driver
|VAB
|
Differential output voltage magnitude
480
650
mV
RL = 50Ω, CL = 5 pF
Figures 2, 4
Change in differential output voltage magnitude
between logic states
ΔVAB
−50
0.3
0
+50
2.1
mV
V
VOS(SS)
Steady-state common-mode output voltage
1.6
RL = 50Ω, CL = 5 pF
Figures 2, 3
Change in steady-state common-mode output
voltage between logic states
|ΔVOS(SS)
|
0
+50
mV
VA(OC)
VB(OC)
VP(H)
Maximum steady-state open-circuit output voltage Figure 5
0
0
2.4
2.4
V
V
Maximum steady-state open-circuit output voltage
Voltage overshoot, low-to-high level output
(Note 12)
RL = 50Ω, CL = 5pF, CD = 0.5 pF
Figures 7, 8
1.2VSS
V
V
VP(L)
Voltage overshoot, high-to-low level output
(Note 12)
−0.2VS
S
IIH
High-level input current (LVTTL inputs)
Low-level input current (LVTTL inputs)
Input Clamp Voltage (LVTTL inputs)
VIH = 3.6V
VIL = 0.0V
IIN = -18 mA
Figure 6
-15
15
15
μA
μA
V
IIL
-15
-1.5
-43
VCL
IOS
Differential short-circuit output current (Note 8)
43
mA
M-LVDS Receiver
VIT+
Positive-going differential input voltage threshold
See Function Tables
Type 1
Type 2
Type 1 −50
16
100
20
50
mV
mV
mV
mV
V
150
VIT−
Negative-going differential input voltage threshold See Function Tables
Type 2
50
94
VOH
VOL
IOZ
High-level output voltage (LVTTL output)
Low-level output voltage (LVTTL output)
TRI-STATE output current
IOH = −8mA
IOL = 8mA
2.4
2.7
0.28
0.4
10
V
VO = 0V or 3.6V
−10
μA
IOSR
Short-circuit receiver output current (LVTTL output) VO = 0V
-50
-90
mA
www.national.com
4
Symbol
Parameter
Conditions
Min
Typ
Max Units
M-LVDS Bus (Input and Output) Pins
IA
Transceiver input/output current
Transceiver input/output current
VA = 3.8V, VB = 1.2V
32
µA
µA
µA
µA
µA
µA
µA
VA = 0V or 2.4V, VB = 1.2V
VA = −1.4V, VB = 1.2V
VB = 3.8V, VA = 1.2V
−20
−32
+20
IB
32
VB = 0V or 2.4V, VA = 1.2V
VB = −1.4V, VA = 1.2V
−20
−32
−4
+20
IAB
Transceiver input/output differential current (IA − IB)
Transceiver input/output power-off current
+4
32
VA = VB, −1.4V ≤ V ≤ 3.8V
VA = 3.8V, VB = 1.2V,
IA(OFF)
DE = 0V
µA
µA
µA
µA
µA
µA
µA
0V ≤ VDD ≤ 1.5V
VA = 0V or 2.4V, VB = 1.2V,
DE = 0V
−20
−32
+20
0V ≤ VDD ≤ 1.5V
VA = −1.4V, VB = 1.2V,
DE = 0V
0V ≤ VDD ≤ 1.5V
VB = 3.8V, VA = 1.2V,
IB(OFF)
Transceiver input/output power-off current
DE = 0V
32
0V ≤ VDD ≤ 1.5V
VB = 0V or 2.4V, VA = 1.2V,
DE = 0V
−20
−32
−4
+20
0V ≤ VDD ≤ 1.5V
VB = −1.4V, VA = 1.2V,
DE = 0V
0V ≤ VDD ≤ 1.5V
IAB(OFF)
Transceiver input/output power-off differential
current (IA(OFF) − IB(OFF)
VA = VB, −1.4V ≤ V ≤ 3.8V,
DE = 0V
)
+4
0V ≤ VDD ≤ 1.5V
CA
Transceiver input/output capacitance
Transceiver input/output capacitance
Transceiver input/output differential capacitance
VDD = OPEN
7.8
7.8
3
pF
pF
pF
CB
CAB
CA/B
Transceiver input/output capacitance balance
(CA/CB)
1
SUPPLY CURRENT (VCC
)
ICCD
ICCZ
ICCR
ICCPD
Driver Supply Current
67
22
32
3
75
26
38
5
mA
mA
mA
mA
RL = 50Ω, DE = H, RE = H
DE = L, RE = H
DE = L, RE = L
MDE = L
TRI-STATE Supply Current
Receiver Supply Current
Power Down Supply Current
Note 4: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 5: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 6: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD and
ΔVOD
.
Note 7: Typical values represent most likely parametric norms for VDD = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 8: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
Note 9: CL includes fixture capacitance and CD includes probe capacitance.
5
www.national.com
Switching Characteristics (Note 10, Note 11, Note 17)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max Units
DRIVER AC SPECIFICATIONS
tPLH
Differential Propagation Delay Low to High
Differential Propagation Delay High to Low
Pulse Skew (Note 12, Note 13)
1.5
1.5
3.3
3.3
30
5.5
5.5
ns
ns
ps
ps
RL = 50Ω, CL = 5 pF,
CD = 0.5 pF
tPHL
Figures 7, 8
tSKD1
tSKD2
125
200
Channel-to-Channel Skew (Note 12, Note
14)
100
tSKD3
tSKD4
tTLH
tTHL
tPZH
tPZL
Part-to-Part Skew (Note 12, Note 15)
Part-to-Part Skew (Note 12, Note 16)
Rise Time (Note 12)
0.8
1.6
4
ns
ns
ns
ns
ns
ns
ns
ns
1.2
1.2
2.0
2.0
7.5
8.0
7.0
7.0
3.0
Fall Time (Note 12)
3.0
Enable Time (Z to Active High)
Enable Time (Z to Active Low )
Disable Time (Active Low to Z)
Disable Time (Active High to Z)
11.5
11.5
11.5
11.5
RL = 50Ω, CL = 5 pF,
CD = 0.5 pF
Figures 9, 10
tPLZ
tPHZ
RECEIVER AC SPECIFICATIONS
tPLH
Propagation Delay Low to High
CL = 15 pF
1.5
1.5
3.0
3.1
55
4.5
4.5
ns
ns
ps
Figures 11, 12, 13
tPHL
Propagation Delay High to Low
tSKD1A
Pulse Skew (Receiver Type 1)
325
(Note 12, Note 13)
tSKD1B
tSKD2
Pulse Skew (Receiver Type 2)
(Note 12, Note 13)
475
60
800
300
ps
ps
Channel-to-Channel Skew (Note 12, Note
14)
tSKD3
tSKD4
tTLH
tTHL
tPZH
tPZL
Part-to-Part Skew (Note 12, Note 15)
Part-to-Part Skew (Note 16)
Rise Time (Note 12)
0.6
1.2
3
ns
ns
ns
ns
ns
ns
ns
ns
0.3
0.3
1.1
0.65
3
1.6
1.6
5.5
5.5
5.5
5.5
Fall Time (Note 12)
Enable Time (Z to Active High)
Enable Time (Z to Active Low)
Disable Time (Active Low to Z)
Disable Time (Active High to Z)
RL = 500Ω, CL = 15 pF
Figures 14, 15
3
tPLZ
3.5
3.5
tPHZ
GENERIC AC SPECIFICATIONS
tWKUP Wake Up Time (Note 12)
500
ms
(Master Device Enable (MDE) time)
fMAX
Maximum Operating Frequency (Note 12)
125
MHz
Note 10: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 11: Typical values represent most likely parametric norms for VDD = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 12: Specification is guaranteed by characterization and is not tested in production.
Note 13: tSKD1, |tPLHD − tPHLD|, Pulse Skew, is the magnitude difference in differential propagation delay time between the positive going edge and the negative
going edge of the same channel.
Note 14: tSKD2, Channel-to-Channel Skew, is the difference in propagation delay (tPLHD or tPHLD) among all output channels.
Note 15: tSKD3, Part-to-Part Skew, is defined as the difference between the minimum and maximum differential propagation delays. This specification applies to
devices at the same VDD and within 5°C of each other within the operating temperature range.
Note 16: tSKD4, Part-to-Part Skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over
recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min| differential propagation delay.
Note 17: CL includes fixture capacitance and CD includes probe capacitance.
Note 18: Measured on a clock edge with a histogram and an acummulation of 1500 histogram hits. Input stimulus jitter is subracted geometrically.
www.national.com
6
Test Circuits and Waveforms
30042214
FIGURE 2. Differential Driver Test Circuit
30042244
FIGURE 3. Differential Driver Waveforms
30042222
FIGURE 4. Differential Driver Full Load Test Circuit
7
www.national.com
30042212
FIGURE 5. Differential Driver DC Open Test Circuit
30042225
FIGURE 6. Differential Driver Short-Circuit Test Circuit
30042216
FIGURE 7. Driver Propagation Delay and Transition Time Test Circuit
www.national.com
8
30042218
FIGURE 8. Driver Propagation Delays and Transition Time Waveforms
30042219
FIGURE 9. Driver TRI-STATE Delay Test Circuit
30042221
FIGURE 10. Driver TRI-STATE Delay Waveforms
9
www.national.com
30042215
FIGURE 11. Receiver Propagation Delay and Transition Time Test Circuit
30042217
FIGURE 12. Type 1 Receiver Propagation Delay and Transition Time Waveforms
30042223
FIGURE 13. Type 2 Receiver Propagation Delay and Transition Time Waveforms
www.national.com
10
30042213
FIGURE 14. Receiver TRI-STATE Delay Test Circuit
30042220
FIGURE 15. Receiver TRI-STATE Delay Waveforms
11
www.national.com
Truth Tables
DS91M040 Transmitting
Inputs
Outputs
RE
X
DE
H
DI
H
L
B
L
A
H
L
X
H
H
Z
X
L
X
Z
X — Don't care condition
Z — High impedance state
DS91M040 as Type 1 Receiving
DS91M040 as Type 2 Receiving
Inputs
Output
Inputs
Output
FSEN
RE
L
DE
X
A − B
RO
FSEN
RE
L
DE
X
A − B
RO
L
L
L
H
L
H
H
H
H
L
≥ +0.05V
≤ −0.05V
−0.05V
≥ +0.15V
≤ +0.05V
+0.05V
L
X
L
X
L
X
Undefined
L
X
Undefined
≤ A-B ≤
+0.05V
X
≤ A-B ≤
+0.15V
X
L
H
X
Z
H
H
X
Z
X — Don't care condition
Z — High impedance state
X — Don't care condition
Z — High impedance state
DS91M040 Type 1 Receiver Input Threshold Test Voltages
Applied Voltages
Resulting Differential Input
Voltage
Resulting Common-Mode
Receiver
Output
Input Voltage
VIA
VIB
VID
VICM
R
2.400V
0.000V
3.800V
3.750V
−1.350V
−1.400V
0.000V
2.400V
3.750V
3.800V
−1.400V
−1.350V
2.400V
−2.400V
0.050V
1.200V
1.200V
3.775V
3.775V
−1.375V
−1.375V
H
L
H
L
−0.050V
0.050V
H
L
−0.050V
H — High Level
L — Low Level
Output state assumes that the receiver is enabled (RE = L)
DS91M040 Type 2 Receiver Input Threshold Test Voltages
Applied Voltages
Resulting Differential Input
Voltage
Resulting Common-Mode
Input Voltage
Receiver
Output
VIA
VIB
VID
VIC
R
2.400V
0.000V
3.800V
3.800V
−1.250V
−1.350V
0.000V
2.400V
3.650V
3.750V
−1.400V
−1.400V
2.400V
−2.400V
0.150V
0.050V
0.150V
0.050V
1.200V
1.200V
3.725V
3.775V
−1.325V
−1.375V
H
L
H
L
H
L
H — High Level
L — Low Level
Output state assumes that the receiver is enabled (RE = L)
www.national.com
12
Typical Performance Characteristics
30042250
30042252
Driver Rise Time as a Function of Temperature
Driver Propagation Delay (tPLHD) as a Function of
Temperature
30042251
30042253
Driver Fall Time as a Function of Temperature
Driver Propagation Delay (tPHLD) as a Function of
Temperature
30042258
Driver Output Signal Amplitude as a Function of
Resistive Load
13
www.national.com
Driver Power Supply Current as a Function of3F00r42e2q54uency
30042256
Receiver Propagation Delay (tPLHD) as a Function of
Input Common Mode Voltage
30042255
Receiver Power Supply Current as a Function of
30042257
Frequency
Receiver Propagation Delay (tPHLD) as a Function of
Input Common Mode Voltage
www.national.com
14
Physical Dimensions inches (millimeters) unless otherwise noted
Order Number DS91M040TSQ
See NS package Number SQA32A
(See AN-1187 for PCB Design and Assembly Recommendations)
15
www.national.com
Notes
For more National Semiconductor product information and proven design tools, visit the following Web sites at:
Products
www.national.com/amplifiers
Design Support
www.national.com/webench
Amplifiers
WEBENCH® Tools
App Notes
Audio
www.national.com/audio
www.national.com/timing
www.national.com/adc
www.national.com/interface
www.national.com/lvds
www.national.com/power
www.national.com/appnotes
www.national.com/refdesigns
www.national.com/samples
www.national.com/evalboards
www.national.com/packaging
www.national.com/quality/green
www.national.com/contacts
www.national.com/quality
www.national.com/feedback
www.national.com/easy
Clock and Timing
Data Converters
Interface
Reference Designs
Samples
Eval Boards
LVDS
Packaging
Power Management
Green Compliance
Distributors
Switching Regulators www.national.com/switchers
LDOs
www.national.com/ldo
www.national.com/led
www.national.com/vref
www.national.com/powerwise
Quality and Reliability
Feedback/Support
Design Made Easy
Solutions
LED Lighting
Voltage Reference
PowerWise® Solutions
www.national.com/solutions
www.national.com/milaero
www.national.com/solarmagic
www.national.com/training
Serial Digital Interface (SDI) www.national.com/sdi
Mil/Aero
Temperature Sensors
Wireless (PLL/VCO)
www.national.com/tempsensors SolarMagic™
www.national.com/wireless
PowerWise® Design
University
THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION
(“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY
OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO
SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS,
IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS
DOCUMENT.
TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT
NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL
PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR
APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND
APPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE
NATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS.
EXCEPT AS PROVIDED IN NATIONAL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NATIONAL ASSUMES NO
LIABILITY WHATSOEVER, AND NATIONAL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE
AND/OR USE OF NATIONAL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR
PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY
RIGHT.
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and
whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected
to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform
can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.
National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other
brand or product names may be trademarks or registered trademarks of their respective holders.
Copyright© 2009 National Semiconductor Corporation
For the most current product information visit us at www.national.com
National Semiconductor
Americas Technical
Support Center
National Semiconductor Europe
Technical Support Center
Email: europe.support@nsc.com
National Semiconductor Asia
Pacific Technical Support Center
Email: ap.support@nsc.com
National Semiconductor Japan
Technical Support Center
Email: jpn.feedback@nsc.com
Email: support@nsc.com
Tel: 1-800-272-9959
www.national.com
相关型号：
DS91M047TMA/NOPB
IC QUAD LINE DRIVER, PDSO16, 0.150 INCH, ROHS COMPLIANT, SOIC-16, Line Driver or Receiver
NSC
DS91M047TMAX/NOPB
IC QUAD LINE DRIVER, PDSO16, 0.150 INCH, ROHS COMPLIANT, SOIC-16, Line Driver or Receiver
NSC
©2020 ICPDF网 联系我们和版权申明