DS92LV010ATM/NOPB [TI]
总线 LVDS 3.3/5.0V 单片收发器 | D | 8 | -40 to 85;
| 型号： | DS92LV010ATM/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 总线 LVDS 3.3/5.0V 单片收发器 | D | 8 | -40 to 85 ATM 异步传输模式 PC 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总20页 (文件大小：618K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS92LV010A
www.ti.com
SNLS007E –MAY 1998–REVISED APRIL 2013
DS92LV010A Bus LVDS 3.3/5.0V Single Transceiver
Check for Samples: DS92LV010A
1
FEATURES
DESCRIPTION
The DS92LV010A is one in a series of transceivers
designed specifically for the high speed, low power
proprietary bus backplane interfaces. The device
operates from a single 3.3V or 5.0V power supply
and includes one differential line driver and one
receiver. To minimize bus loading the driver outputs
and receiver inputs are internally connected. The
logic interface provides maximum flexibility as 4
separate lines are provided (DIN, DE, RE, and
ROUT). The device also features flow through which
allows easy PCB routing for short stubs between the
bus pins and the connector. The driver has 10 mA
drive capability, allowing it to drive heavily loaded
backplanes, with impedance as low as 27 Ohms.
2
•
•
•
•
•
•
•
•
•
Bus LVDS Signaling (BLVDS)
Designed for Double Termination Applications
Balanced Output Impedance
Lite Bus Loading 5pF Typical
Glitch Free Power Up/Down (Driver Disabled)
3.3V or 5.0V Operation
±1V Common Mode Range
±100mV Receiver Sensitivity
High Signaling Rate Capability (Above 100
Mbps)
•
•
•
Low Power CMOS Design
Product Offered in 8 Lead SOIC Package
Industrial Temperature Range Operation
The driver translates between TTL levels (single-
ended) to Low Voltage Differential Signaling levels.
This allows for high speed operation, while
consuming minimal power with reduced EMI. In
addition the differential signaling provides common
mode noise rejection of ±1V.
The receiver threshold is ±100mV over a ±1V
common mode range and translates the low voltage
differential levels to standard (CMOS/TTL) levels.
CONNECTION DIAGRAM
Figure 1. SOIC Package
See Package Number D0008A
BLOCK DIAGRAM
Figure 2.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1998–2013, Texas Instruments Incorporated
DS92LV010A
SNLS007E –MAY 1998–REVISED APRIL 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)(2)(3)
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VCC
)
6.0V
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
−0.3V to + 3.9V
Continuous
Enable Input Voltage (DE, RE)
Driver Input Voltage (DIN)
Receiver Output Voltage (ROUT
Bus Pin Voltage (DO/RI±)
)
Driver Short Circuit Current
ESD (HBM 1.5 kΩ, 100 pF)
>2.0 kV
Maximum Package Power Dissipation at 25°C
SOIC
1025 mW
Derate SOIC Package
8.2 mW/°C
Junction Temperature
+150°C
Storage Temperature Range
−65°C to +150°C
260°C
Lead Temperature
(Soldering, 4 sec.)
(1) All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground except
VOD, VID, VTH and VTL unless otherwise specified.
(2) Absolute Maximum Ratings are these beyond which the safety of the device cannot be ensured. They are not meant to imply that the
device should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
RECOMMENDED OPERATING CONDITIONS
Min
3.0
4.5
0.0
−40
Max Units
Supply Voltage (VCC), or
Supply Voltage (VCC
3.6
5.5
2.9
+85
V
V
)
Receiver Input Voltage
V
Operating Free Air Temperature
°C
2
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SNLS007E –MAY 1998–REVISED APRIL 2013
(1)(2)
3.3V DC ELECTRICAL CHARACTERISTICS
TA = −40°C to +85°C unless otherwise noted, VCC = 3.3V ± 0.3V
Parameter
Test Conditions
Pin
Min Typ Max Units
VOD
Output Differential Voltage
VOD Magnitude Change
Offset Voltage
RL = 27Ω, See Figure 3
DO+/RI+,
DO−/RI−
140 250 360
30
1.25 1.65
50
mV
mV
V
ΔVOD
VOS
3
1
ΔVOS
IOSD
VOH
Offset Magnitude Change
Output Short Circuit Current
Voltage Output High
5
mV
mA
V
VO = 0V, DE = VCC
VID = +100 mV
−12 −20
I OH = −400 µA
R OUT
2.8
2.8
2.8
2.8
3
3
3
3
Inputs Open
V
Inputs Shorted
V
Inputs Terminated, RL = 27Ω
IOL = 2.0 mA, VID = −100 mV
VOUT = 0V, VID = +100 mV
DE = 0V
V
VOL
IOS
VTH
VTL
IIN
Voltage Output Low
Output Short Circuit Current
Input Threshold High
Input Threshold Low
Input Current
0.1
0.4
V
−5
−35 −85
mA
mV
mV
µA
µA
V
DO+/RI+,
DO−/RI−
+100
−100
−20
−20
2.0
DE = 0V, VIN = +2.4V, or 0V
VCC = 0V, VIN = +2.4V, or 0V
±1
±1
+20
+20
VCC
0.8
VIH
Minimum Input High Voltage
Maximum Input Low Voltage
Input High Current
DIN,
DE,RE
VIL
GND
V
IIH
VIN = VCC or 2.4V
±1
±1
±10
±10
µA
µA
V
IIL
Input Low Current
VIN = GND or 0.4V
ICLAMP = −18 mA
VCL
ICCD
ICCR
ICCZ
ICC
Input Diode Clamp Voltage
Power Supply Current
−1.5 −0.8
DE = RE = VCC , RL = 27Ω
DE = RE = 0V
V CC
13
5
20
8
mA
mA
mA
mA
pF
DE = 0V, RE = VCC
DE = VCC, RE = 0V, RL = 27Ω
3
7.5
22
16
5
Coutput
Capacitance @ BUS Pins
DO+/RI+,
DO−/RI−
(1) All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground except
VOD, VID, VTH and VTL unless otherwise specified.
(2) All typicals are given for VCC = +3.3V or 5.0 V and TA = +25°C, unless otherwise stated.
Copyright © 1998–2013, Texas Instruments Incorporated
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(1)(2)
5V DC ELECTRICAL CHARACTERISTICS
TA = −40°C to +85°C unless otherwise noted, VCC = 5.0V ± 0.5V
Parameter
Test Conditions
Pin
Min Typ Max Units
VOD
Output Differential Voltage
VOD Magnitude Change
Offset Voltage
RL = 27Ω, See Figure 3
DO+/RI+,
DO−/RI−
145 270 390
30
1.35 1.65
50
mV
mV
V
ΔVOD
VOS
3
1
ΔVOS
IOSD
VOH
Offset Magnitude Change
Output Short Circuit Current
Voltage Output High
5
mV
mA
V
VO = 0V, DE = VCC
VID = +100 mV
−12 −20
IOH = −400 µA
ROUT
4.3
4.3
4.3
4.3
5.0
5.0
5.0
5.0
Inputs Open
V
Inputs Shorted
V
Inputs Terminated, RL = 27Ω
IOL = 2.0 mA, VID = −100 mV
VOUT = 0V, VID = +100 mV
DE = 0V
V
VOL
IOS
VTH
VTL
IIN
Voltage Output Low
Output Short Circuit Current
Input Threshold High
Input Threshold Low
Input Current
0.1
0.4
V
−35 −90 −130
mA
mV
mV
µA
µA
V
DO+/RI+,
DO−/RI−
+100
−100
DE = 0V, VIN = +2.4V, or 0V
VCC = 0V, VIN = +2.4V, or 0V
−20
−20
2.0
±1
±1
+20
+20
VCC
0.8
VIH
Minimum Input High Voltage
Maximum Input Low Voltage
Input High Current
DIN, DE,
RE
VIL
GND
V
IIH
VIN = VCC or 2.4V
±1
±1
±10
±10
µA
µA
V
IIL
Input Low Current
VIN = GND or 0.4V
ICLAMP = −18 mA
VCL
ICCD
ICCR
ICCZ
ICC
Input Diode Clamp Voltage
Power Supply Current
−1.5 −0.8
DE = RE = VCC, RL = 27Ω
DE = RE = 0V
V CC
17
6
25
10
8
mA
mA
mA
mA
pF
DE = 0V, RE = VCC
DE = VCC, RE = 0V, RL = 27Ω
3
20
5
25
Coutput
Capacitance @ BUS Pins
DO+/RI+,
DO−/RI−
(1) All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground except
VOD, VID, VTH and VTL unless otherwise specified.
(2) All typicals are given for VCC = +3.3V or 5.0 V and TA = +25°C, unless otherwise stated.
4
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SNLS007E –MAY 1998–REVISED APRIL 2013
(1)
3.3V AC ELECTRICAL CHARACTERISTICS
TA = −40°C to +85°C, VCC = 3.3V ± 0.3V
Parameter
Test Conditions
Min
Typ
Max
Units
DIFFERENTIAL DRIVER TIMING REQUIREMENTS
tPHLD
tPLHD
tSKD
Differential Prop. Delay High to RL = 27Ω, See Figure 4 and Figure 5
1.0
1.0
3.0
2.8
0.2
5.0
5.0
1.0
ns
ns
ns
Low
CL = 10 pF
Differential Prop. Delay Low to
High
Differential SKEW |t PHLD
tPLHD
-
|
tTLH
tTHL
tPHZ
tPLZ
tPZH
tPZL
Transition Time Low to High
Transition Time High to Low
Disable Time High to Z
Disable Time Low to Z
Enable Time Z to High
Enable Time Z to Low
0.3
0.3
4.5
5.0
5.0
4.5
2.0
2.0
ns
ns
ns
ns
ns
ns
RL = 27Ω, See Figure 6 and Figure 7
CL = 10 pF
0.5
0.5
2.0
1.0
9.0
10.0
7.0
9.0
DIFFERENTIAL RECEIVER TIMING REQUIREMENTS
tPHLD
tPLHD
tSKD
Differential Prop. Delay High to See Figure 8 and Figure 9
2.5
2.5
5.0
5.5
0.5
12.0
10.0
2.0
ns
ns
ns
Low
CL = 10 pF
Differential Prop. Delay Low to
High
Differential SKEW |t PHLD
tPLHD
-
|
tr
Rise Time
1.5
1.5
4.0
5.0
7.0
6.0
4.0
4.0
ns
ns
ns
ns
ns
ns
tf
Fall Time
tPHZ
tPLZ
tPZH
tPZL
Disable Time High to Z
Disable Time Low to Z
Enable Time Z to High
Enable Time Z to Low
RL = 500Ω, See Figure 10 and Figure 11
2.0
2.0
2.0
2.0
6.0
CL = 10 pF(2)
7.0
13.0
10.0
(1) Generator waveforms for all tests unless otherwise specified: f = 1MHz, ZO = 50Ω, tr, tf ≤ 6.0ns (0%–100%) on control pins and ≤ 1.0ns
for RI inputs.
(2) For receiver tri-state delays, the switch is set to VCC for tPZL, and tPLZ and to GND for tPZH, and tPHZ
.
Copyright © 1998–2013, Texas Instruments Incorporated
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(1)
5V AC ELECTRICAL CHARACTERISTICS
TA = −40°C to +85°C, VCC = 5.0V ± 0.5V
Parameter
Test Conditions
Min
Typ
Max
Units
DIFFERENTIAL DRIVER TIMING REQUIREMENTS
tPHLD
tPLHD
tSKD
Differential Prop. Delay High to RL = 27Ω, See Figure 4 and Figure 5
0.5
0.5
2.7
2.5
0.2
4.5
4.5
1.0
ns
ns
ns
Low
CL = 10 pF
Differential Prop. Delay Low to
High
Differential SKEW |t PHLD
tPLHD
-
|
tTLH
tTHL
tPHZ
tPLZ
tPZH
tPZL
Transition Time Low to High
Transition Time High to Low
Disable Time High to Z
Disable Time Low to Z
Enable Time Z to High
Enable Time Z to Low
0.3
0.3
3.0
5.0
4.0
4.0
2.0
2.0
7.0
10.0
7.0
9.0
ns
ns
ns
ns
ns
ns
RL = 27Ω, See Figure 6 and Figure 7
CL = 10 pF
0.5
0.5
2.0
1.0
DIFFERENTIAL RECEIVER TIMING REQUIREMENTS
tPHLD
tPLHD
tSKD
Differential Prop. Delay High to See Figure 8 and Figure 9
2.5
2.5
5.0
4.6
0.4
12.0
10.0
2.0
ns
ns
ns
Low
CL = 10 pF
Differential Prop. Delay Low to
High
Differential SKEW |t PHLD
tPLHD
-
|
tr
Rise Time
1.2
1.2
4.0
4.0
5.0
5.0
2.5
2.5
6.0
6.0
9.0
7.0
ns
ns
ns
ns
ns
ns
tf
Fall Time
tPHZ
tPLZ
tPZH
tPZL
Disable Time High to Z
Disable Time Low to Z
Enable Time Z to High
Enable Time Z to Low
RL = 500Ω, See Figure 10 and Figure 11
2.0
2.0
2.0
2.0
CL = 10 pF(2)
(1) Generator waveforms for all tests unless otherwise specified: f = 1MHz, ZO = 50Ω, tr, tf ≤ 6.0ns (0%–100%) on control pins and ≤ 1.0ns
for RI inputs.
(2) For receiver tri-state delays, the switch is set to VCC for tPZL, and tPLZ and to GND for tPZH, and tPHZ
.
TEST CIRCUITS AND TIMING WAVEFORMS
Figure 3. Differential Driver DC Test Circuit
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SNLS007E –MAY 1998–REVISED APRIL 2013
Figure 4. Differential Driver Propagation Delay and Transition Time Test Circuit
3V
0V
1.5V
1.5V
D
IN
t
t
PHLD
PLHD
DO-
0V
Differential
0V
DO+, DO-
DO+
80%
0V
20%
80%
20%
(DO+) - (DO-)
t
t
THL
TLH
V
= (DO+) - (DO-)
DIFF
Figure 5. Differential Driver Propagation Delay and Transition Time Waveforms
Figure 6. Driver TRI-STATE Delay Test Circuit
Figure 7. Driver TRI-STATE Delay Waveforms
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Figure 8. Receiver Propagation Delay and Transition Time Test Circuit
Figure 9. Receiver Propagation Delay and Transition Time Waveforms
Figure 10. Receiver TRI-STATE Delay Test Circuit
Figure 11. Receiver TRI-STATE Delay Waveforms TRI-STATE Delay Waveforms
TYPICAL BUS APPLICATION CONFIGURATIONS
Figure 12. Bi-Directional Half-Duplex Point-to-Point Applications
8
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SNLS007E –MAY 1998–REVISED APRIL 2013
Figure 13. Multi-Point Bus Applications
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SNLS007E –MAY 1998–REVISED APRIL 2013
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APPLICATION INFORMATION
There are a few common practices which should be implied when designing PCB for BLVDS signaling.
Recommended practices are:
•
•
•
Use at least 4 layer PCB board (BLVDS signals, ground, power and TTL signals).
Keep drivers and receivers as close to the (BLVDS port side) connector as possible.
Bypass each BLVDS device and also use distributed bulk capacitance. Surface mount capacitors placed
close to power and ground pins work best. Two or three multi-layer ceramic (MLC) surface mount capacitors
(0.1 µF, and 0.01 µF in parallel should be used between each VCC and ground. The capacitors should be as
close as possible to the VCC pin.
•
•
Use the termination resistor which best matches the differential impedance of your transmission line.
Leave unused LVDS receiver inputs open (floating)
Table 1. Functional Table
MODE SELECTED
DRIVER MODE
DE
H
L
RE
H
L
RECEIVER MODE
TRI-STATE MODE
LOOP BACK MODE
L
H
L
H
Table 2. Transmitter Mode(1)
INPUTS
OUTPUTS
DE
H
DI
L
DO+
L
DO−
H
H
H
H
L
H
2 > & > 0.8
X
X
Z
X
L
Z
(1) L = Low state
H = High state
Table 3. Receiver Mode(1)
INPUTS
OUTPUT
RE
L
(RI+)-(RI−)
L (< −100 mV)
H (> +100 mV)
100 mV > & > −100 mV
X
L
H
X
Z
L
L
H
(1) X = High or Low logic state
Z = High impedance state
L = Low state
H = High state
Table 4. Device Pin Descriptions
Pin Name
DIN
Pin No.
Input/Output
Description
2
6, 7
3
I
I/O
O
TTL Driver Input
DO±/RI±
ROUT
RE
LVDS Driver Outputs/LVDS Receiver Inputs
TTL Receiver Output
5
I
Receiver Enable TTL Input (Active Low)
Driver Enable TTL Input (Active High)
Ground
DE
1
I
GND
VCC
4
NA
NA
8
Power Supply
10
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SNLS007E –MAY 1998–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision D (April 2013) to Revision E
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 10
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PACKAGE OPTION ADDENDUM
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30-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS92LV010ATM
DS92LV010ATM/NOPB
DS92LV010ATMX
NRND
SOIC
SOIC
SOIC
SOIC
D
D
D
D
8
8
8
8
95
Non-RoHS
& Green
Call TI
Level-1-235C-UNLIM
Level-1-260C-UNLIM
Level-1-235C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
LV010
ATM
ACTIVE
NRND
95
RoHS & Green
SN
Call TI
SN
LV010
ATM
2500
Non-RoHS
& Green
LV010
ATM
DS92LV010ATMX/NOPB
ACTIVE
2500 RoHS & Green
LV010
ATM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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30-Sep-2021
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
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9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS92LV010ATMX
SOIC
D
D
8
8
2500
2500
330.0
330.0
12.4
12.4
6.5
6.5
5.4
5.4
2.0
2.0
8.0
8.0
12.0
12.0
Q1
Q1
DS92LV010ATMX/NOPB SOIC
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
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9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS92LV010ATMX
SOIC
SOIC
D
D
8
8
2500
2500
367.0
367.0
367.0
367.0
35.0
35.0
DS92LV010ATMX/NOPB
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
DS92LV010ATM
DS92LV010ATM
D
D
D
SOIC
SOIC
SOIC
8
8
8
95
95
95
495
495
495
8
8
8
4064
4064
4064
3.05
3.05
3.05
DS92LV010ATM/NOPB
Pack Materials-Page 3
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated
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