DSD1793DB [TI]
113dB SNR 立体声音频 DAC（软件控制） | DB | 28 | -25 to 85;
| 型号： | DSD1793DB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 113dB SNR 立体声音频 DAC（软件控制） | DB | 28 | -25 to 85 光电二极管 转换器 |
| 文件： | 总54页 (文件大小：1185K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ꢀ ꢁꢀ ꢂꢃ ꢄꢅ
SLES075B − MARCH 2003 − REVISED NOVEMBER 2006
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D
Dual Supply Operation:
FEATURES
− 5-V Analog, 3.3-V Digital
5-V Tolerant Digital Inputs
Small 28-Lead SSOP Package
D
D
D
Supports Both DSD and PCM Formats
24-Bit Resolution
D
D
Analog Performance:
− Dynamic Range: 113 dB
− THD+N: 0.001%
APPLICATIONS
− Full-Scale Output: 2.1 V rms (at
Postamplifier)
D
D
D
D
D
D
D
A/V Receivers
SACD Players
D
D
Differential Voltage Output: 3.2 V p-p
DVD Players
8× Oversampling Digital Filter:
− Stop-Band Attenuation: –82 dB
− Pass-Band Ripple: 0.002 dB
HDTV Receivers
Car Audio Systems
Digital Multitrack Recorders
Other Applications Requiring 24-Bit Audio
D
D
Sampling Frequency: 10 kHz to 200 kHz
System Clock: 128, 192, 256, 384, 512, or
768 f With Autodetect
S
Accepts 16-, 20-, and 24-Bit Audio Data
DESCRIPTION
D
2
D
PCM Data Formats: Standard, I S, and
Left-Justified
The DSD1793 is a monolithic CMOS integrated circuit that
includes stereo digital-to-analog converters and support
circuitry in a small 28-lead SSOP package. The data
converters use TI’s advanced-segment DAC architecture
to achieve excellent dynamic performance and improved
tolerance to clock jitter. The DSD1793 provides balanced
voltage outputs, allowing the user to optimize analog
performance externally. The DSD1793 accepts the PCM
and DSD audio data formats, providing easy interfacing to
audio DSP and decoder chips. The DSD1793 also accepts
interfaces to external digital filter devices (DF1704,
DF1706, PMD200). Sampling rates up to 200 kHz are
supported. A full set of user-programmable functions is
accessible through an I2C-compatible serial control port.
D
D
DSD Format Interface Available
Optional Interface to External Digital Filter or
DSP Available
2
D
I C-Compatible Serial Port
D
User-Programmable Mode Controls:
− Digital Attenuation: 0 dB to –120 dB,
0.5 dB/Step
− Digital De-Emphasis
− Digital Filter Rolloff: Sharp or Slow
− Soft Mute
− Zero Flags for Each Output in PCM and
DSD Formats
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
ꢒꢛ ꢚ ꢀꢙ ꢗ ꢋꢊ ꢚꢔ ꢀ ꢐꢋꢐ ꢜꢝ ꢞꢟ ꢠ ꢡꢢ ꢣꢜꢟꢝ ꢜꢤ ꢥꢦ ꢠ ꢠ ꢧꢝꢣ ꢢꢤ ꢟꢞ ꢨꢦꢩ ꢪꢜꢥ ꢢꢣꢜ ꢟꢝ ꢫꢢ ꢣꢧꢬ ꢒꢠ ꢟꢫꢦ ꢥꢣꢤ
ꢥ ꢟꢝ ꢞꢟꢠ ꢡ ꢣꢟ ꢤ ꢨꢧ ꢥ ꢜ ꢞꢜ ꢥ ꢢ ꢣꢜ ꢟꢝꢤ ꢨ ꢧꢠ ꢣꢭꢧ ꢣꢧ ꢠ ꢡꢤ ꢟꢞ ꢋꢧꢮ ꢢꢤ ꢊꢝꢤ ꢣꢠ ꢦꢡ ꢧꢝꢣ ꢤ ꢤꢣ ꢢꢝꢫ ꢢꢠ ꢫ ꢯ ꢢꢠ ꢠ ꢢ ꢝꢣꢰꢬ
ꢒꢠ ꢟ ꢫꢦꢥ ꢣ ꢜꢟ ꢝ ꢨꢠ ꢟ ꢥ ꢧ ꢤ ꢤ ꢜꢝ ꢱ ꢫꢟ ꢧ ꢤ ꢝꢟꢣ ꢝꢧ ꢥꢧ ꢤꢤ ꢢꢠ ꢜꢪ ꢰ ꢜꢝꢥ ꢪꢦꢫ ꢧ ꢣꢧ ꢤꢣꢜ ꢝꢱ ꢟꢞ ꢢꢪ ꢪ ꢨꢢ ꢠ ꢢꢡ ꢧꢣꢧ ꢠ ꢤꢬ
Copyright 2006, Texas Instruments Incorporated
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SLES075B − MARCH 2003 − REVISED NOVEMBER 2006
ORDERING INFORMATION
OPERATION
TEMPERATURE RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA
PRODUCT
PACKAGE
PACKAGE CODE
DSD1793DB
Tube
DSD1793DB
28-lead SSOP
28DB
–25°C to 85°C
DSD1793
DSD1793DBR
Tape and reel
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range unless otherwise noted
DSD1791
V
V
F, V L, V C, V
R
–0.3 V to 6.5 V
–0.3 V to 4 V
0.1 V
CC
DD
CC CC CC
Supply voltage
Supply voltage differences: V F, V L, V C, V
R
CC CC CC CC
Ground voltage differences: AGNDF, AGNDL, AGNDC, AGNDR, DGND
0.1 V
PLRCK, PDATA, PBCK, DSDL, DSDR, DBCK, ADR0, ADR1, SCK, SCL, SDA
ZEROL, ZEROR
–0.3 V to 6.5 V
Digital input voltage
Analog input voltage
–0.3 V to (V
+ 0.3 V) < 4 V
DD
–0.3 V to (V
+ 0.3 V) < 6.5 V
CC
Input current (any pins except supplies)
Ambient temperature under bias
Storage temperature
10 mA
–40°C to 125°C
–55°C to 150°C
150°C
Junction temperature
Lead temperature (soldering)
Package temperature (IR reflow, peak)
260°C, 5 s
260°C
(1)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
all specifications at T = 25°C, V
= 5 V, V = 3.3 V, f = 44.1 kHz, system clock = 256 f , and 24-bit data, unless otherwise noted
DD S S
A
CC
DSD1793DB
PARAMETER
UNIT
MIN
TYP
MAX
RESOLUTION
24
Bits
DATA FORMAT (PCM Mode)
2
Audio data interface format
Audio data bit length
Audio data format
Standard, I S, left justified
16-, 20-, 24-bit selectable
MSB first, 2s complement
f
S
Sampling frequency
System clock frequency
10
200
kHz
128, 192, 256, 384, 512, 768 f
S
DATA FORMAT (DSD Mode)
Audio data interface format
Audio data bit length
DSD (direct stream digital)
1 Bit
f
S
Sampling frequency
2.8224
MHz
MHz
System clock frequency
2.8224
11.2896
2
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SLES075B − MARCH 2003 − REVISED NOVEMBER 2006
ELECTRICAL CHARACTERISTICS (Continued)
all specifications at T = 25°C, V
= 5 V, V = 3.3 V, f = 44.1 kHz, system clock = 256 f , and 24-bit data, unless otherwise noted
DD S S
A
CC
PARAMETER
DIGITAL INPUT/OUTPUT
DSD1793DB
TYP
TEST CONDITIONS
UNIT
MIN
MAX
Logic family
TTL compatible
V
V
2
IH
IL
Input logic level
VDC
µA
0.8
I
I
V
V
= V
DD
= 0 V
10
IH
IN
IN
Input logic current
Output logic level
–10
IL
V
OH
V
OL
I
I
= –2 mA
= 2 mA
2.4
OH
OL
VDC
0.4
(1)
DYNAMIC PERFORMANCE (PCM MODE)
f
f
f
= 44.1 kHz
= 96 kHz
0.001%
0.0015%
0.003%
113
0.002%
S
S
S
THD+N at V
OUT
= 0 dB
= 192 kHz
EIAJ, A-weighted, f = 44.1 kHz
S
EIAJ, A-weighted, f = 96 kHz
S
110
110
106
113
Dynamic range
dB
dB
EIAJ, A-weighted, f = 192 kHz
113
S
EIAJ, A-weighted, f = 44.1 kHz
S
EIAJ, A-weighted, f = 96 kHz
S
113
113
Signal-to-noise ratio
Channel separation
EIAJ, A-weighted, f = 192 kHz
113
S
f
S
f
S
f
S
= 44.1 kHz
= 96 kHz
110
110
dB
dB
= 192 kHz
109
Level linearity error
V
OUT
= –120 dB
1
(1) (2)
DYNAMIC PERFORMANCE (DSD MODE)
THD+N at V
OUT
= 0 dB
2.1 V rms
0.001%
113
Dynamic range
Signal-to-noise ratio
ANALOG OUTPUT
–60 dB, EIAJ, A-weighted
EIAJ, A-weighted
dB
dB
113
Gain error
–8
–3
–2
3
0.5
0.5
3.2
1.4
8
3
2
% of FSR
% of FSR
% of FSR
V p-p
Gain mismatch, channel-to-channel
Bipolar zero error
At BPZ
(3)
Differential output voltage
Full scale (0 dB)
At BPZ
(3)
Bipolar zero voltage
V
(3)
Load impedance
R
1
= R
1.7
kΩ
2
(1)
Dynamic performance and dc accuracy are specified at the output of the postamplifier as shown in Figure 32. Analog performance specifications
are measured using the System Twot Cascade audio measurement system by Audio Precisiont in the averaging mode. For all
sampling-frequencyoperations, measurement bandwidth is limited with a 20-kHz AES17 filter.
(2)
(3)
Analog performance in the DSD mode is specified as the DSD modulation index of 100%. This is equilvalent to PCM mode performance at
44.1 kHz and 64 f .
S
These parameters are defined at the DSD1793 output pins. Load impedances, R and R , are input resistors of the postamplifier. They are defined
1
2
as dc-coupled loads.
Audio Precision and System Two are trademarks of Audio Precision, Inc.
Other trademarks are the property of their respective owners.
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SLES075B − MARCH 2003 − REVISED NOVEMBER 2006
ELECTRICAL CHARACTERISTICS (Continued)
all specifications at T = 25°C, V
= 5 V, V = 3.3 V, f = 44.1 kHz, system clock = 256 f , and 24-bit data, unless otherwise noted
DD S S
A
CC
DSD1793DB
TYP
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
DIGITAL FILTER PERFORMANCE
De-emphasis error
0.1
dB
FILTER CHARACTERISTICS-1: SHARP ROLLOFF
0.002 dB
–3 dB
0.454 f
S
S
Pass band
0.49 f
Stop band
0.546 f
S
Pass-band ripple
0.002
dB
dB
s
Stop band = 0.546 f
Stop band = 0.567 f
–75
–82
S
S
Stop-band attenuation
Delay time
29/f
S
FILTER CHARACTERISTICS-2: SLOW ROLLOFF
0.04 dB
–3 dB
0.274 f
S
S
Pass band
0.454 f
Stop band
0.732 f
S
Pass-band ripple
0.002
dB
dB
s
Stop-band attenuation
Delay time
Stop band = 0.732 f
–82
S
29/f
S
POWER SUPPLY REQUIREMENTS
V
V
3
3.3
5
3.6
5.5
8
VDC
VDC
DD
CC
Voltage range
4.5
f
S
f
S
f
S
f
S
f
S
f
S
f
S
f
S
f
S
= 44.1 kHz
= 96 kHz
6.5
13.5
28
I
mA
mA
mW
DD
= 192 kHz
= 44.1 kHz
= 96 kHz
(1)
Supply current
14
16
15
I
CC
= 192 kHz
= 44.1 kHz
= 96 kHz
16
90
110
(1)
120
170
Power dissipation
= 192 kHz
TEMPERATURE RANGE
Operation temperature
Thermal resistance
–25
85
°C
θ
JA
28-pin SSOP
100
°C/W
(1)
Input is BPZ data.
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SLES075B − MARCH 2003 − REVISED NOVEMBER 2006
PIN ASSIGNMENTS
DSD1793
(TOP VIEW)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
PLRCK
PBCK
PDATA
DBCK
SCK
ADR0
SCL
SDA
DSDL
DSDR
ZEROL
ZEROR
2
3
4
5
6
ADR1
7
V
DD
8
DGND
AGNDF
V
V
F
L
CC
9
CC
V
R
10
11
12
13
14
AGNDL
CC
AGNDR
V
V
L–
L+
OUT
V
V
R–
R+
OUT
OUT
AGNDC
OUT
V
V
C
COM
CC
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SLES075B − MARCH 2003 − REVISED NOVEMBER 2006
Terminal Functions
TERMINAL
I/O
DESCRIPTIONS
NAME
ADR0
PIN
28
6
2 (1)
I C address 0
I
I
2 (1)
I C address 1
ADR1
AGNDC
AGNDF
AGNDL
AGNDR
DBCK
DGND
DSDL
DSDR
PBCK
PDATA
PLRCK
SCK
16
9
–
–
–
–
I
Analog ground (internal bias and current DAC)
Analog ground (DACFF)
19
11
4
Analog ground (L-channel I/V)
Analog ground (R-channel I/V)
(1)
Bit clock input for DSD mode
Digital ground
8
–
I
(1)
(1)
25
24
2
L-channel audio data input for DSD mode
R-channel audio data input for DSD mode
I
(1)
I
Bit clock input for PCM mode
Serial audio data input for PCM mode
Left and right clock (f ) input for PCM mode
(1)
3
I
(1)
1
I
S
(1)
5
I
System clock input
(1)
2
SCL
27
26
15
21
20
10
14
7
I
I C clock
2 (2)
I C data
SDA
I/O
–
–
–
–
–
–
O
O
O
O
O
O
V
V
V
V
V
V
V
V
V
V
C
F
L
Analog power supply (internal bias and current DAC), 5 V
Analog power supply (DACFF), 5 V
Analog power supply (L-channel I/V), 5 V
Analog power supply (R-channel I/V), 5 V
Internal bias decoupling pin
CC
CC
CC
CC
R
COM
DD
Digital power supply, 3.3 V
L+
17
18
13
12
23
22
L-channel analog voltage output +
L-channel analog voltage output –
R-channel analog voltage output +
R-channel analog voltage output –
Zero flag for L-channel
OUT
OUT
OUT
OUT
L–
R+
R–
ZEROL
ZEROR
Zero flag for R-channel
(1)
(2)
Schmitt-trigger input, 5-V tolerant
Schmitt-trigger input and output. 5-V tolerant input, and open-drain, 3-state output
6
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SLES075B − MARCH 2003 − REVISED NOVEMBER 2006
FUNCTIONAL BLOCK DIAGRAM
PLRCK
Current
Segment
DAC
V
V
L–
L+
Audio
PBCK
OUT
Data Input
PDATA
I/F
OUT
and
I/V Buffer
D/S and Filter
8
Oversampling
Digital
Filter
and
Function
Control
DBCK
DSDL
DSDR
Advanced
Segment
DAC
Bias
and
Vref
V
COM
Modulator
SDA
Current
Segment
DAC
and
I/V Buffer
V
V
R+
R–
SCL
OUT
Function
Control
I/F
ADR0
ADR1
OUT
D/S and Filter
ZEROL
ZEROR
System
Clock
Manager
Zero
Detect
Power Supply
7
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SLES075B − MARCH 2003 − REVISED NOVEMBER 2006
TYPICAL PERFORMANCE CURVES
DIGITAL FILTER
Digital Filter Response
AMPLITUDE
AMPLITUDE
vs
vs
FREQUENCY
FREQUENCY
0
−20
0.003
0.002
−40
0.001
−60
−80
0
−100
−120
−140
−160
–0.001
–0.002
–0.003
0.0
0
1
2
3
4
0.1
0.2
0.3
0.4
0.5
Frequency[× f ]
Frequency[× f ]
S
S
Figure 1. Frequency Response, Sharp Rolloff
Figure 2. Pass-Band Ripple, Sharp Rolloff
AMPLITUDE
vs
AMPLITUDE
vs
FREQUENCY
FREQUENCY
0
−20
0
−2
−4
−40
−6
−8
−60
−10
−12
−14
−16
−18
−20
−80
−100
−120
−140
0
1
2
3
4
0.0
0.1
0.2
0.3
0.4
0.5
0.6
Frequency[× f ]
Frequency[× f ]
S
S
Figure 3. Frequency Response, Slow Rolloff
Figure 4. Transition Characteristics, Slow Rolloff
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SLES075B − MARCH 2003 − REVISED NOVEMBER 2006
De-Emphasis Filter
DE-EMPHASIS LEVEL
DE-EMPHASIS ERROR
vs
vs
FREQUENCY
FREQUENCY
0
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
0.5
0.4
0.3
0.2
0.1
f
= 32 kHz
f
S
= 32 kHz
S
0.0
−0.1
−0.2
−0.3
−0.4
−0.5
0
2
4
6
8
10
12
14
0
2
4
6
8
10
12
14
f – Frequency – kHz
f – Frequency – kHz
Figure 5
Figure 6
DE-EMPHASIS LEVEL
vs
DE-EMPHASIS ERROR
vs
FREQUENCY
FREQUENCY
0
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
0.5
0.4
f
= 44.1 kHz
f
S
= 44.1 kHz
S
0.3
0.2
0.1
−0.0
−0.1
−0.2
−0.3
−0.4
−0.5
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
f – Frequency – kHz
f – Frequency – kHz
Figure 7
Figure 8
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SLES075B − MARCH 2003 − REVISED NOVEMBER 2006
De-Emphasis Filter (Continued)
DE-EMPHASIS LEVEL
vs
DE-EMPHASIS ERROR
vs
FREQUENCY
FREQUENCY
0
0.5
0.4
f
S
= 48 kHz
f = 48 kHz
S
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
0.3
0.2
0.1
0.0
−0.1
−0.2
−0.3
−0.4
−0.5
0
2
4
6
8
10 12 14 16 18 20 22
0
2
4
6
8
10 12 14 16 18 20 22
f – Frequency – kHz
f – Frequency – kHz
Figure 9
Figure 10
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SLES075B − MARCH 2003 − REVISED NOVEMBER 2006
ANALOG DYNAMIC PERFORMANCE
Supply Voltage Characteristics
TOTAL HARMONIC DISTORTION + NOISE
DYNAMIC RANGE
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
118
116
114
112
110
108
0.01
f
= 192 kHz
= 96 kHz
S
f
f
= 96 kHz
S
S
f
S
= 44.1 kHz
0.001
f
S
= 44.1 kHz
f
S
= 192 kHz
0.0001
4.00 4.25 4.50 4.75 5.00 5.25 5.50 5.75 6.00
4.00 4.25 4.50 4.75 5.00 5.25 5.50 5.75 6.00
V
CC
– Supply Voltage – V
V
CC
– Supply Voltage – V
Figure 11
Figure 12
SIGNAL-to-NOISE RATIO
vs
CHANNEL SEPARATION
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
118
116
114
112
110
108
114
112
110
108
106
104
102
f
= 44.1 kHz
S
f
S
= 96 kHz
f
= 96 kHz
S
f
S
= 192 kHz
f
S
= 192 kHz
f
S
= 44.1 kHz
4.00 4.25 4.50 4.75 5.00 5.25 5.50 5.75 6.00
4.00 4.25 4.50 4.75 5.00 5.25 5.50 5.75 6.00
V
CC
– Supply Voltage – V
V
CC
– Supply Voltage – V
Figure 13
Figure 14
:
NOTE PCM mode, T = 25°C, V
DD
= 3.3 V.
A
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Temperature Characteristics
TOTAL HARMONIC DISTORTION + NOISE
DYNAMIC RANGE
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
118
116
114
112
110
108
0.01
f
= 192 kHz
S
f
= 96 kHz
S
f
= 96 kHz
S
f
= 44.1 kHz
S
f
S
= 192 kHz
0.001
f
= 44.1 kHz
S
0.0001
−50
−25
0
25
50
75
100
−50
−25
0
25
50
75
100
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 15
Figure 16
SIGNAL-to-NOISE RATIO
vs
CHANNEL SEPARATION
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
118
116
114
112
110
108
114
112
110
108
106
104
f
= 44.1 kHz
S
f
= 44.1 kHz
S
f
= 96 kHz
S
f
S
= 96 kHz
f = 192 kHz
S
f
S
= 192 kHz
−50
−25
0
25
50
75
100
−50
−25
0
25
50
75
100
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 17
Figure 18
:
NOTE PCM mode, V
= 3.3 V, V = 5 V.
CC
DD
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AMPLITUDE vs FREQUENCY
AMPLITUDE vs FREQUENCY
−50
−60
−50
−60
−70
−70
−80
−80
−90
−90
−100
−110
−120
−130
−140
−150
−100
−110
−120
−130
−140
−150
−160
−160
0
5
10
15
20
0
10 20 30 40 50 60 70 80 90 100
f – Frequency – kHz
f – Frequency – kHz
Figure 19. –60-dB Output Spectrum, BW = 20 kHz Figure 20. –60-dB Output Spectrum, BW = 100 kHz
:
NOTE PCM mode, f = 44.1 kHz, 32768 points, 8 average, T = 25°C, V
= 3.3 V, V = 5 V.
CC
S
A
DD
TOTAL HARMONIC DISTORTION + NOISE
vs
INPUT LEVEL
100
10
1
0.1
0.01
0.001
0.0001
−100
−80
−60
−40
−20
0
Input Level – dBFS
Figure 21. THD+N vs Input Level, PCM Mode
:
NOTE PCM mode, f = 44.1 kHz, T = 25°C, V
DD
= 3.3 V, V = 5 V.
CC
S
A
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AMPLITUDE
vs
FREQUENCY
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
−160
0
5
10
15
20
f – Frequency – kHz
Figure 22. –60-dB Output Spectrum, DSD Mode
TOTAL HARMONIC DISTORTION + NOISE
vs
INPUT LEVEL
100
10
1
0.1
0.01
0.001
0.0001
−90 −80 −70 −60 −50 −40 −30 −20 −10
0
Input Level – dBFS
Figure 23. THD+N vs Input Level, DSD Mode
:
NOTE DSD mode (FIR-2), T = 25°C, V
= 3.3 V, V = 5 V.
CC
A
DD
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SYSTEM CLOCK AND RESET FUNCTIONS
System Clock Input
The DSD1793 requires a system clock for operating the digital interpolation filters and advanced segment DAC
modulators. The system clock is applied at the SCK input (pin 5). The DSD1793 has a system clock detection circuit
that automatically senses which frequency the system clock is operating. Table 1 shows examples of system clock
frequencies for common audio sampling rates. If the oversampling rate of the delta-sigma modulator is selected as
128 f , the system clock frequency is over 256 f .
S
S
Figure 24 shows the timing requirements for the system clock input. For optimal performance, it is important to use
a clock source with low phase jitter and noise. One of the Texas Instruments PLL1700 family of multiclock generators
is an excellent choice for providing the DSD1793 system clock.
Table 1. System Clock Rates for Common Audio Sampling Frequencies
SYSTEM CLOCK FREQUENCY (f
) (MHz)
512 f
SCK
SAMPLING FREQUENCY
128 f
4.096
192 f
256 f
384 f
768 f
S
S
(1)
S
S
S
S
(1)
32 kHz
44.1 kHz
48 kHz
6.144
8.192
11.2896
12.288
24.576
12.288
16.9344
18.432
36.864
16.384
24.576
33.8688
36.864
(1)
5.6488
6.144
8.4672
9.216
22.5792
24.576
(1)
(1)
(1)
96 kHz
12.288
24.576
18.432
36.864
49.152
(2)
73.728
(2)
(1)
(1)
73.728
192 kHz
49.152
(1)
(2)
2
This system clock rate is not supported in I C fast mode.
This system clock rate is not supported for the given sampling frequency.
t
(SCKH)
H
2 V
0.8 V
System Clock (SCK)
L
t
t
(SCY)
(SCKL)
PARAMETERS
MIN MAX UNITS
t
System clock pulse cycle time
13
5
ns
ns
ns
(SCY)
t
System clock pulse duration, HIGH
System clock pulse duration, LOW
(SCKH)
t
5
(SCKL)
Figure 24. System Clock Input Timing
Power-On Reset Function
The DSD1793 includes a power-on reset function. Figure 25 shows the operation of this function. With V
> 2 V,
DD
the power-on reset function is enabled. The initialization sequence requires 1024 system clocks from the time
> 2 V. After the initialization period, the DSD1793 is set to its default reset state, as described in the MODE
V
DD
CONTROL REGISTERS section of this data sheet.
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V
DD
2.4 V (Max)
2 V (Typ)
1.6 V (Min)
Reset
Reset Removal
Internal Reset
System Clock
1024 System Clocks
Figure 25. Power-On Reset Timing
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AUDIO DATA INTERFACE
Audio Serial Interface
The audio interface port is a 3-wire serial port. It includes PLRCK (pin 1), PBCK (pin 2), and PDATA (pin 3). PBCK
is the serial audio bit clock, and it is used to clock the serial data present on PDATA into the serial shift register of
the audio interface. Serial data is clocked into the DSD1793 on the rising edge of PBCK. PLRCK is the serial audio
left/right word clock.
The DSD1793 requires the synchronization of PLRCK and the system clock, but does not need a specific phase
relation between PLRCK and the system clock.
If the relationship between PLRCK and the system clock changes more than 6 PBCK, internal operation is initialized
within 1/f and analog outputs are forced to the bipolar zero level until resynchronization between PLRCK and the
S
system clock is completed.
PCM Audio Data Formats and Timing
2
The DSD1793 supports industry-standard audio data formats, including standard right-justified, I S, and left-justified.
The data formats are shown in Figure 27. Data formats are selected using the format bits, FMT[2:0], in control register
2
18. The default data format is 24-bit I S. All formats require binary 2s complement, MSB-first audio data. Figure 26
shows a detailed timing diagram for the serial audio interface.
1.4 V
1.4 V
1.4 V
PLRCK
PBCK
t
t
(BCL)
t
(BCH)
(LB)
t
t
(BCY)
(BL)
PDATA
t
t
(DS)
(DH)
PARAMETERS
MIN MAX UNITS
t
t
t
t
t
t
t
PBCK pulse cycle time
PBCK pulse duration, LOW
PBCK pulse duration, HIGH
PBCK rising edge to PLRCK edge
PLRCK edge to PBCK rising edge
PDATA setup time
70
30
30
10
10
10
10
ns
ns
ns
ns
ns
ns
ns
(BCY)
(BCL)
(BCH)
(BL)
(LB)
(DS)
PDATA hold time
(DH)
—
PLRCK clock data
50% 2 bit clocks
Figure 26. Timing of Audio Interface
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(1) Standard Data Format (Right Justified) ; L-Channel = HIGH, R-Channel = LOW
1/f
S
PLRCK
R-Channel
L-Channel
PBCK
Audio Data Word = 16-Bit
14 15 16
1
2
15 16
LSB
1
2
15 16
PDATA
MSB
Audio Data Word = 20-Bit
18 19 20
1
2
19 20
LSB
1
2
19 20
23 24
PDATA
MSB
Audio Data Word = 24-Bit
22 23 24
1
2
23 24
LSB
1
2
PDATA
MSB
(2) Left Justified Data Format; L-Channel = HIGH, R-Channel = LOW
1/f
S
PLRCK
PBCK
R-Channel
L-Channel
Audio Data Word = 24-Bit
PDATA
1
2
23 24
LSB
1
2
23 24
1
2
MSB
2
(3) I S Data Format; L-Channel = LOW, R-Channel = HIGH
1/f
S
PLRCK
L-Channel
R-Channel
PBCK
Audio Data Word = 16-Bit
PDATA
1
1
2
2
15 16
LSB
1
2
2
15 16
1
1
2
2
MSB
MSB
Audio Data Word = 24-Bit
PDATA
23 24
LSB
1
23 24
Figure 27. Audio Data Input Formats
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External Digital Filter Interface and Timing
The DSD1793 supports an external digital filter interface with a 3- or 4-wire synchronous serial port, which allows
the use of an external digital filter. External filters include the Texas Instruments DF1704 and DF1706, the Pacific
Microsonics PMD200, or a programmable digital signal processor.
In the external DF mode, PLRCK (pin 1), PBCK (pin 2) and PDATA (pin 3) are defined as WDCK, the word clock;
BCK, the bit clock; and DATA, the monaural data, respectively. The external digital filter interface is selected by using
the DFTH bit of control register 20, which functions to bypass the internal digital filter of the DSD1793.
When the DFMS bit of control register 19 is set, the DSD1793 can process stereo data. In this case, DSDL (pin 25)
and DSDR (pin 24) are defined as L-channel data and R-channel data input, respectively.
Detailed information for the external digital filter interface mode is provided in the APPLICATION FOR EXTERNAL
DIGITAL FILTER INTERFACE section of this data sheet.
Direct Stream Digital (DSD) Format Interface and Timing
The DSD1793 supports the DSD format interface operation, which includes out-of-band noise filtering using an
internal analog FIR filter. The DSD format interface consists of a 3-wire synchronous serial port, which includes DBCK
(pin 4), DSDL (pin 25), and DSDR (pin 24). DBCK is the serial bit clock. DSDL and DSDR are L-channel and
R-channel DSD data input, respectively. They are clocked into the DSD1793 on the rising edge of DBCK. PLRCK
(pin 1) and PBCK (pin 2) must be connected to GND in the DSD mode. The DSD format (DSD mode) interface is
activated by setting the DSD bit of control register 20.
Detailed information for the DSD mode is provided in the APPLICATION FOR DSD FORMAT (DSD MODE)
INTERFACE section of this data sheet.
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FUNCTIONAL DESCRIPTIONS
Zero Detect
The DSD1793 has a zero-detect function. When the DSD1793 detects the zero conditions as shown in Table 2, the
DSD1793 sets ZEROL (pin 23) and ZEROR (pin 22) to HIGH.
Table 2. Zero Conditions
MODE
DETECTING CONDITION AND TIME
DATA is continuously LOW for 1024 LRCKs.
PCM
External DF mode DATA is continuously LOW for 1024 WDCKs.
DZ0
DZ1
There are an equal number of 1s and 0s in every 8 bits of DSD input data for 23 ms.
The input data is 1001 0110 continuously for 23 ms.
DSD
2
Serial Control Interface (I C)
2
The DSD1793 supports the I C serial bus and the data transmission protocol for standard and fast mode as a slave
2
device. This protocol is explained in I C specification 2.0.
Slave Address
MSB
1
LSB
R/W
0
0
1
1
ADR1
ADR0
The DSD1793 has 7 bits for its own slave address. The first five bits (MSBs) of the slave address are factory preset
to 10011. The next two bits of the address byte are the device select bits, which can be user-defined by the ADR1
and ADR0 terminals. A maximum of four DSD1793s can be connected on the same bus at one time. Each DSD1793
responds when it receives its own slave address.
Packet Protocol
A master device must control packet protocol, which consists of start condition, slave address, read/write bit, data
if write or acknowledge if read, and stop condition. The DSD1793 supports only slave receivers and slave
transmitters.
SDA
SCL
St
1−7
8
9
1−8
9
1−8
9
9
Sp
ACK
Slave Address R/W
ACK
DATA
DATA
ACK
ACK
R/W : Read Operation if 1, Otherwise Write Operation
DATA: 8 Bits (Byte)
ACK: Acknowledgement of a Byte if 0
NACK: Not Acknowledgement if 1
Start
Condition
Stop
Condition
Write operation
Transmitter
Data Type
M
M
M
S
M
S
M
S
…
…
S
M
St
Slave Address
W
ACK
DATA
ACK
DATA
ACK
ACK
Sp
Read operation
Transmitter
Data Type
M
M
M
S
S
M
S
M
…
…
M
M
St
Slave Address
R
ACK
DATA
ACK
DATA
ACK
NACK
Sp
:
NOTE M: Master Device
Sp: Stop Condition
S: Slave Device
W: Write
St: Start Condition
R: Read
2
Figure 28. Basic I C Framework
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Write Register
A master can write to any DSD1793 registers using single or multiple accesses. The master sends a DSD1793 slave
address with a write bit, a register address, and the data. If multiple access is required, the address is that of the
starting register, followed by the data to be transferred. When the data are received properly, the index register is
incremented automatically by 1. When the index register reaches 0x7F, the next value is 0x0. When undefined
registers are accessed, the DSD1793 does not send an acknowledgement. Figure 29 is a diagram of the write
operation.
Transmitter
M
M
M
S
M
S
M
S
M
S
…
…
S
M
Data Type St
Slave
Address
W
ACK
Register
Address
ACK
Write Data 1
ACK
Write Data 2
ACK
ACK
Sp
M: Master Device
S: Slave Device
Sp: Stop Condition
St: Start Condition
W: Write
ACK: Acknowledge
Figure 29. Write Operation
Read Register
A master can read the DSD1793 register. The value of the register address is stored in an indirect index register in
advance. The master sends a DSD1793 slave address with a read bit after storing the register address. Then the
DSD1793 transfers the data which the index register points to. When the data are transferred during a multiple
access, the index register is incremented by 1 automatically. (When first going into read mode immediately following
a write, the index register is not incremented. The master can read the register that was previously written.) When
the index register reaches 0x7F, the next value is 0x0. The DSD1793 outputs some data when the index register is
0x10 to 0x1F, even if it is not defined in Table 4. Figure 30 is a diagram of the read operation.
Transmitter
M
M
M
S
M
S
M
M
M
S
S
M
…
…
M
M
Data Type St
Slave
Address
W
ACK Register ACK
Address
Sr
Slave
Address
R
ACK
Data
ACK
NACK Sp
M: Master Device
S: Slave Device
St: Start Condition
Sr: Repeated Start Condition
W: Write
ACK: Acknowledge
Sp: Stop Condition
NACK: Not Acknowledge
R: Read
:
NOTE The slave address after the repeat start condition must be the same as the previous slave address.
Figure 30. Read Operation
Noise Suppression
The DSD1793 incorporates noise suppression using the system clock (SCK). However, there must be no more than
two noise spikes in 600 ns. The noise suppression works for SCK frequencies between 8 MHz and 40 MHz in fast
mode. However, it works incorrectly in the particular following conditions.
Case 1:
1. t
2. t
> 120 ns (t
: period of SCK)
(SCK)
(SCK)
+ t
< t
(D-HD)
× 5
(HI)
(SCK)
3. Spike noise exists on the first half of the SCL HIGH pulse.
4. Spike noise exists on the SDA HIGH pulse just before SDA goes LOW.
SCL
Noise
SDA
When these conditions occur at the same time, the data is recognized as LOW.
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Case 2:
1. t
2. t
> 120 ns
(SCK)
or t
< t
× 5
(SCK)
(S-HD)
(RS-HD)
3. Spike noise exists on both SCL and SDA during the hold time.
SCL
Noise
SDA
When these conditions occur at the same time, the DSD1793 fails to detect a start condition.
Case 3:
1. t
2. t
< 50 ns
(SCK)
(SP)
> t
(SCK)
3. Spike noise exists on SCL just after SCL goes LOW.
4. Spike noise exists on SDA just before SCL goes LOW.
SCL
SDA
Noise
When these conditions occur at the same time, the DSD1793 erroneously detects a start or stop condition.
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TIMING DIAGRAM
Repeated Start
Start
Stop
t
t
(SDA-F)
(D-HD)
t
t
t
t
(P-SU)
(BUF)
(D-SU)
(SDA-R)
SDA
t
t
t
(SP)
(SCL-R)
(RS-HD)
t
(LOW)
SCL
t
t
(S-HD)
t
(HI)
(RS-SU)
t
(SCL-F)
TIMING CHARACTERISTICS
PARAMETER
CONDITIONS
Standard
Fast
MIN MAX
100
400
4.7
UNIT
f
t
t
t
t
SCL clock frequency
kHz
(SCL)
(BUF)
(LOW)
(HI)
Standard
Fast
Bus free time between stop and start conditions
Low period of the SCL clock
High period of the SCL clock
Setup time for (repeated) start condition
Hold time for (repeated) start condition
Data setup time
µs
µs
1.3
Standard
Fast
4.7
1.3
Standard
Fast
4
µs
ns
µs
ns
µs
ns
600
4.7
Standard
Fast
(RS-SU)
600
4
t
t
Standard
Fast
(S-HD)
600
250
100
(RS-HD)
Standard
Fast
t(
ns
ns
ns
ns
ns
ns
ns
D-SU)
Standard
Fast
0
0
900
900
t
t
t
t
Data hold time
(D-HD)
Standard
Fast
20 + 0.1 C
20 + 0.1 C
20 + 0.1 C
20 + 0.1 C
20 + 0.1 C
20 + 0.1 C
20 + 0.1 C
20 + 0.1 C
20 + 0.1 C
20 + 0.1 C
1000
300
B
B
B
B
B
B
B
B
B
Rise time of SCL signal
(SCL-R)
(SCL-R1)
(SCL-F)
Standard
Fast
1000
300
Rise time of SCL signal after a repeated start condition and after an
acknowledge bit
Standard
Fast
1000
300
Fall time of SCL signal
Rise time of SDA signal
Fall time of SDA signal
Setup time for stop condition
Standard
Fast
1000
300
t(
SDA-R)
(SDA-F)
(P-SU)
Standard
Fast
1000
300
t
t
B
4
Standard
Fast
µs
ns
pF
ns
V
600
C
Capacitive load for SDA and SCL line
Pulse duration of suppressed spike
400
50
(B)
t
Fast
(SP)
V
NH
Noise margin at high level for each connected device (including hysteresis)
0.2 V
DD
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MODE CONTROL REGISTERS
User-Programmable Mode Controls
The DSD1793 includes a number of user-programmable functions which are accessed via mode control registers.
The registers are programmed using the serial control interface, which was previously discussed in this data sheet.
Table 3 lists the available mode-control functions, along with their default reset conditions and associated register
index.
Table 3. User-Programmable Function Controls
DF
BYPASS
FUNCTION
Digital attenuation control
DEFAULT
REGISTER
BIT
PCM
DSD
0 dB
Register 16 ATL[7:0] (for L-ch)
Register 17 ATR[7:0] (for R-ch)
yes
0 dB to –120 dB and mute, 0.5 dB step
Attenuation load control—Disabled, enabled
Attenuation disabled
Register 18 ATLD
yes
yes
2
Input audio data format selection
24-bit I S format
Register 18 FMT[2:0]
yes
16-, 20-, 24-bit standard (right-justified) format
24-bit MSB-first left-justified format
2
16-/24-bit I S format
(1)
yes
Sampling rate selection for de-emphasis
Disabled, 44.1 kHz, 48 kHz, 32 kHz
De-emphasis disabled
Register 18 DMF[1:0]
yes
De-emphasis control—Disabled, enabled
Soft mute control—Mute disabled, enabled
Output phase reversal—Normal, reverse
Attenuation speed selection
De-emphasis disabled
Mute disabled
Normal
Register 18 DME
Register 18 MUTE
Register 19 REV
Register 19 ATS[1:0]
yes
yes
yes
yes
yes
yes
×1 f
S
×1 f , ×(1/2)f , ×(1/4)f , ×(1/8)f
S
S
S
S
DAC operation control—Enabled, disabled
DAC operation enabled Register 19 OPE
yes
yes
yes
yes
Stereo DF bypass mode select
Monaural, stereo
Monaural
Register 19 DFMS
Digital filter rolloff selection
Sharp rolloff, slow rolloff
Sharp rolloff
Disabled
Register 19 FLT
yes
yes
yes
yes
yes
yes
yes
yes
yes
Infinite zero mute control
Disabled, enabled
Register 19 INZD
Register 20 SRST
Register 20 DSD
Register 20 DFTH
Register 20 MONO
Register 20 CHSL
Register 20 OS[1:0]
yes
yes
System reset control
Reset operation , normal operation
Normal operation
Disabled
yes
yes
DSD interface mode control
DSD enabled, disabled
Digital-filter bypass control
DF enabled, DF bypass
DF enabled
Stereo
yes
yes
yes
yes
yes
Monaural mode selection
Stereo, monaural
yes
yes
Channel selection for monaural mode data
L-channel, R-channel
L-channel
(2)
yes
Delta-sigma oversampling rate selection
×64 f
S
×64 f , ×128 f , ×32 f
S
S
S
PCM zero output enable
Enabled
Disabled
Register 21 PCMZ
Register 21 DZ[1:0]
DSD zero output enable
yes
yes
Function Available Only For Read
Zero detection flag
Not zero, zero detected
Not zero = 0
Zero detected = 1
Register 22 ZFGL (for L-ch)
ZFGR (for R-ch)
yes
yes
(1)
(2)
When in DSD mode, DMF[1:0] is defined as DSD filter (analog FIR) performance selection.
When in DSD mode, OS[1:0] is defined as DSD filter (analog FIR) operation rate selection.
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Register Map
The mode control register map is shown in Table 4. Registers 16–21 include an R/W bit, which determines whether
a register read (R/W = 1) or write (R/W = 0) operation is performed. Register 22 is read-only.
Table 4. Mode Control Register Map
B15
Register 16 R/W
Register 17 R/W
Register 18 R/W
Register 19 R/W
Register 20 R/W
Register 21 R/W
B14 B13
B12
1
B11
0
B10 B9 B8
B7
B6
B5
B4
B3
B2
B1
B0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
ATL7 ATL6 ATL5 ATL4
ATL3
ATL2
ATL1
ATL0
1
0
ATR7 ATR6 ATR5 ATR4 ATR3
ATLD FMT2 FMT1 FMT0 DMF1 DMF0 DME MUTE
ATR2 ATR1 ATR0
1
0
1
0
REV ATS1 ATS0 OPE
RSV
DFMS
FLT
OS1
DZ0
INZD
OS0
1
0
RSV SRST DSD DFTH MONO CHSL
1
0
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
DZ1
RSV
PCMZ
Register 22
R
1
0
ZFGR ZFGL
Register Definitions
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 16
R/W
0
0
1
0
0
0
0
ATL7 ATL6 ATL5 ATL4 ATL3 ATL2 ATL1 ATL0
Register 17 R/W
0
0
1
0
0
0
1
ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0
R/W: Read/Write Mode Select
When R/W = 0, a write operation is performed.
When R/W = 1, a read operation is performed.
Default value: 0
ATx[7:0]: Digital Attenuation Level Setting
These bits are available for read and write.
Default value: 1111 1111b
Each DAC output has a digital attenuator associated with it. The attenuator can be set from 0 dB to –120 dB, in 0.5-dB
steps. Alternatively, the attenuator can be set to infinite attenuation (or mute).
The attenuation data for each channel can be set individually. However, the data load control (the ATLD bit of control
register 18) is common to both attenuators. ATLD must be set to 1 in order to change an attenuator setting. The
attenuation level can be set using the following formula:
Attenuation level (dB) = 0.5 dB • (ATx[7:0]
– 255)
DEC
where ATx[7:0]
= 0 through 255
DEC
For ATx[7:0]
levels for various settings:
= 0 through 14, the attenuator is set to infinite attenuation. The following table shows attenuation
DEC
ATx[7:0]
1111 1111b
1111 1110b
1111 1101b
L
Decimal Value
Attenuation Level Setting
255
254
253
L
0 dB, no attenuation (default)
–0.5 dB
–1.0 dB
L
0001 0000b
0000 1111b
0000 1110b
L
16
15
14
L
–119.5 dB
–120.0 dB
Mute
L
0000 0000b
0
Mute
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B15 B14 B13 B12 B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 18
R/W
0
0
1
0
0
1
0
ATLD FMT2 FMT1 FMT0 DMF1 DMF0 DME MUTE
R/W: Read/Write Mode Select
When R/W = 0, a write operation is performed.
When R/W = 1, a read operation is performed.
Default value: 0
ATLD: Attenuation Load Control
This bit is available for read and write.
Default value: 0
ATLD = 0
ATLD = 1
Attenuation control disabled (default)
Attenuation control enabled
The ATLD bit enables loading of the attenuation data contained in registers 16 and 17. When ATLD = 0, the
attenuation settings remain at the previously programmed levels, ignoring new data loaded from registers 16 and
17. When ATLD = 1, attenuation data written to registers 16 and 17 is loaded normally.
FMT[2:0]: Audio Interface Data Format
These bits are available for read and write.
Default value: 101
FMT[2:0]
000
Audio Data Format Selection
16-bit standard format, right-justified data
20-bit standard format, right-justified data
24-bit standard format, right-justified data
24-bit MSB-first, left-justified format data
001
010
011
2
100
16-bit I S-format data
2
101
24-bit I S-format data (default)
110
Reserved
Reserved
111
The FMT[2:0] bits select the data format for the serial audio interface.
For the external digital filter interface mode (DFTH mode), this register is operated as shown in the APPLICATION
FOR EXTERNAL DIGITAL FILTER INTERFACE section of this data sheet.
DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function
These bits are available for read and write.
Default value: 00
DMF[1:0]
De-Emphasis Sampling Frequency Selection
00
01
10
11
Disabled (default)
48 kHz
44.1 kHz
32 kHz
The DMF[1:0] bits select the sampling frequency used by the digital de-emphasis function when it is enabled by
setting the DME bit. The de-emphasis curves are shown in the TYPICAL PERFORMANCE CURVES section of this
data sheet.
For the DSD mode, analog FIR filter performance can be selected using this register. A register map and filter
response plots are shown in the APPLICATION FOR DSD FORMAT (DSD MODE) INTERFACE section of this data
sheet.
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DME: Digital De-Emphasis Control
This bit is available for read and write.
Default value: 0
DME = 0
DME = 1
De-emphasis disabled (default)
De-emphasis enabled
The DME bit enables or disables the de-emphasis function for both channels.
MUTE: Soft Mute Control
This bit is available for read and write.
Default value: 0
MUTE = 0
MUTE = 1
MUTE disabled (default)
MUTE enabled
The MUTE bit enables or disables the soft mute function for both channels.
Soft mute is operated as a 256-step attenuator. The speed for each step to –∞ dB (mute) is determined by the
attenuation rate selected in the ATS register.
B15 B14 B13 B12 B11 B10
Register 19 R/W
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
0
0
1
0
0
1
1
REV ATS1 ATS0 OPE
RSV DFMS
FLT
INZD
R/W: Read/Write Mode Select
When R/W = 0, a write operation is performed.
When R/W = 1, a read operation is performed.
Default value: 0
REV: Output Phase Reversal
This bit is available for read and write.
Default value: 0
REV = 0
REV = 1
Normal output (default)
Inverted output
The REV bit inverts the output phase for both channels.
ATS[1:0]: Attenuation Rate Select
These bits are available for read and write.
Default value: 00
ATS[1:0]
Attenuation Rate Selection
Every PLRCK (default)
PLRCK/2
00
01
10
11
PLRCK/4
PLRCK/8
The ATS[1:0] bits select the rate at which the attenuator is decremented/incremented during level transitions.
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OPE: DAC Operation Control
This bit is available for read and write.
Default value: 0
OPE = 0
OPE = 1
DAC operation enabled (default)
DAC operation disabled
The OPE bit enables or disables the analog output for both channels. Disabling the analog outputs forces them to
the bipolar zero level (BPZ) even if digital audio data is present on the input.
DFMS: Stereo DF Bypass Mode Select
This bit is available for read and write.
Default value: 0
DFMS = 0
DFMS = 1
Monaural (default)
Stereo input enabled
The DFMS bit enables stereo operation in the DF bypass mode. In the DF bypass mode, when DFMS is set to 0,
the pin for the input data is PDATA (pin 3) only, therefore the DSD1793 operates as a monaural DAC. When DFMS
is set to 1, the DSD1793 can operate as a stereo DAC with inputs of L-channel and R-channel data on DSDL (pin
25) and DSDR (pin 24), respectively.
FLT: Digital Filter Rolloff Control
This bit is available for read and write.
Default value: 0
FLT = 0
FLT = 1
Sharp rolloff (default)
Slow rolloff
The FLT bit selects the digital filter rolloff characteristic. The filter responses for these selections are shown in the
TYPICAL PERFORMANCE CURVES section of this data sheet.
INZD: Infinite Zero Detect Mute Control
This bit is available for read and write.
Default value: 0
INZD = 0
INZD = 1
Infinite zero detect mute disabled (default)
Infinite zero detect mute enabled
The INZD bit enables or disables the zero detect mute function. Setting INZD to 1 forces muted analog outputs to
hold a bipolar zero level when the DSD1793 detects zero condition in both channels. The infinite zero detect mute
function is not available in the DSD mode.
B15 B14 B13 B12 B11 B10
Register 20 R/W
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
0
0
1
0
1
0
0
RSV SRST DSD DFTH MONO CHSL OS1
OS0
R/W: Read/Write Mode Select
When R/W = 0, a write operation is performed.
When R/W = 1, a read operation is performed.
Default value: 0
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SRST: System Reset Control
This bit is available for write only.
Default value: 0
SRST = 0
SRST = 1
Normal operation (default)
System reset operation (generate one reset pulse)
The SRST bit resets the DSD1793 to the initial system condition.
DSD: DSD Interface Mode Control
This bit is available for read and write.
Default value: 0
DSD = 0
DSD = 1
DSD interface mode disabled (default)
DSD interface mode enabled
The DSD bit enables or disables the DSD interface mode.
DFTH: Digital Filter Bypass (or Through Mode) Control
This bit is available for read and write.
Default value: 0
DFTH = 0
DFTH = 1
Digital filter enabled (default)
Digital filter bypassed for the external digital filter
The DFTH bit enables or disables the external digital filter interface mode.
MONO: Monaural Mode Selection
This bit is available for read and write.
Default value: 0
MONO = 0
MONO = 1
Stereo mode (default)
Monaural mode
The MONO function changes the operation mode from the normal stereo mode to the monaural mode. When the
monaural mode is selected, both DACs operate in a balanced mode for one channel of audio input data. Channel
selection is available for L-channel or R-channel data, determined by the CHSL bit as described immediately
following.
CHSL: Channel Selection for Monaural Mode
This bit is available for read and write.
Default value: 0
CHSL = 0
CHSL = 1
L-channel selected (default)
R-channel selected
This bit is available when MONO = 1.
The CHSL bit selects L-channel or R-channel data to be used in monaural mode.
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OS[1:0]: Delta-Sigma Oversampling Rate Selection
These bits are available for read and write.
Default value: 00
OS[1:0]
00
Operation Speed Select
64 times f (default)
S
01
32 times f
S
10
128 times f
Reserved
S
11
The OS bits change the oversampling rate of delta-sigma modulation. Use of this function enables the designer to
stabilize the conditions at the post low-pass filter for different sampling rates. As an application example,
programming to set 128 times in 44.1-kHz operation, 64 times in 96-kHz operation, and 32 times in 192-kHz operation
allows the use of only a single type (cutoff frequency) of post low-pass filter. The 128-f oversampling rate is not
S
available at sampling rates above 100 kHz. If the 128-f oversampling rate is selected, a system clock of more than
S
256 f is required.
S
In DSD mode, these bits select the speed of the bit clock for DSD data coming into the analog FIR filter.
B15 B14 B13 B12 B11 B10
R/W
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 21
0
0
1
0
1
0
1
RSV
RSV
RSV
RSV
RSV
DZ1
DZ0 PCMZ
R/W: Read/Write Mode Select
When R/W = 0, a write operation is performed.
When R/W = 1, a read operation is performed.
Default value: 0
DZ[1:0]: DSD Zero Output Enable
These bits are available for read and write.
Default value: 00
DZ[1:0]
00
Zero Output Enable
Disabled (default)
01
Even pattern detect
1x
96 pattern detect
H
The DZ bits enable or disable the output zero flags, and select the zero pattern in the DSD mode.
PCMZ: PCM Zero Output Enable
This bit is available for read and write.
Default value: 1
PCMZ = 0
PCMZ = 1
PCM zero output disabled
PCM zero output enabled (default)
The PCMZ bit enables or disables the output zero flags in the PCM mode and the external DF mode.
B15 B14 B13 B12 B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 22
R
0
0
1
0
1
1
0
RSV
RSV
RSV
RSV
RSV
RSV ZFGR ZFGL
R: Read Mode Select
Value is always 1, specifying the readback mode.
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ZFGx: Zero-Detection Flag
Where x = L or R, corresponding to the DAC output channel. These bits are available only for readback.
Default value: 00
ZFGx = 0
ZFGx = 1
Not zero
Zero detected
These bits show zero conditions. Their status is the same as that of the zero flags on ZEROL (pin 23) and ZEROR
(pin 22). See Zero Detect in the FUNCTIONAL DESCRIPTIONS section of this data sheet.
TYPICAL CONNECTION DIAGRAM
PCM Decoder
L/R Clock (f )
S
PLRCK
PBCK
PDATA
DBCK
SCK
ADR0
SCL
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Bit Clock
Audio Data
SDA
3
Controller
DSDL
DSDR
ZEROL
ZEROR
4
System Clock
5
ADR1
6
V
DD
7
3.3 V
+
DSD1793
DSD Decoder
DGND
V
V
F
L
8
CC
AGNDF
9
CC
Rch Data
Lch Data
Bit Clock
V R
CC
AGNDL
L–
10
11
12
13
14
Analog
Output Stage
(See Figure 32)
Analog
AGNDR
V
OUT
Output Stage
(See Figure 32)
V
V
V
R–
V
L+
OUT
OUT
AGNDC
R+
OUT
V C
CC
COM
Figure 31. Typical Application Circuit
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APPLICATION INFORMATION
ANALOG OUTPUTS
PLRCK
PBCK
PDATA
DBCK
SCK
ADR0
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SCL
SDA
3
DSDL
4
DSDR
ZEROL
ZEROR
5
ADR1
6
V
DD
7
DSD1793
DGND
V
V
F
L
8
0.1 µF
CC
5 V
+
AGNDF
9
CC
10 µF
R L
R L
4
V R
CC
AGNDL
10
11
12
13
14
C L
3
R L
6
2
AGNDR
V
L–
L+
OUT
C L
1
V
V
V
R–
V
OUT
OUT
–
+
V
OUT
L-Channel
R L
1
R L
5
AGNDC
R+
OUT
V C
CC
C L
2
COM
R L
3
+
1 µF
R R
4
C R
3
R R
2
R R
6
C R
1
–
+
V
OUT
R-Channel
R R
1
R R
5
C R
2
R R
3
:
NOTE Example R and C values for f = 77 kHz – R , R : 1.8 kΩ, R ,R : 3.3 kΩ, R ,R : 680 Ω, C : 1800 pF, C , C : 560 pF.
C
1
2
3
4
5
6
1
2
3
Figure 32. Typical Application for Analog Output Stage
Analog Output Level and LPF
The signal level of the DAC differential-voltage output {(V
L+)–(V
L–), (V
R+)–(V
R–)} is 3.2 V p-p
OUT
OUT
OUT
OUT
at 0 dB (full scale). The voltage output of the LPF is given by following equation:
V
= 3.2 V p-p × (R /R )
OUT
f
i
Here, R is the feedback resistor in the LPF, and R = R in a typical application circuit. R is the input resistor
f
3
4
i
in the LPF, and R = R in a typical application circuit.
1
2
Operational Amplifier for LPF
An OPA2134 or 5532 type operational amplifier is recommended for the LPF circuit to obtain the specified audio
performance. Dynamic performance such as gain bandwidth, settling time, and slew rate of the operational
amplifier largely determines the audio dynamic performance of the LPF section. The input noise specification
of the operational amplifier should be considered to obtain a 113-dB S/N ratio.
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Analog Gain of Balanced Amplifier
The DAC voltage outputs are followed by balanced amplifier stages, which sum the differential signals for each
channel, creating a single-ended voltage output. In addition, the balanced amplifiers provide a third-order
low-pass filter function, which band limits the audio output signal. The cutoff frequency and gain are determined
by external R and C component values. In this case, the cutoff frequency is 77 kHz with a gain of 1.83. The
output voltage for each channel is 5.9 V p-p, or 2.1 V rms.
Application for Monaural-Mode Operation
A single-channel signal from the stereo audio data input is output from both V
L and V
R as a differential
OUT
OUT
output. The channel to be output is selected by setting the CHSL bit in register 20. The advantage of monaural
operation is to provide over 115 dB of dynamic range for high-end audio applications.
L/R Clock
Bit Clock
Analog
V
OUT
L-Channel
Output
Stage
System Clock
Audio Data
DSD1793
Controller
Analog
Output
Stage
V
OUT
R-Channel
DSD1793
Analog Output Stage
R
6
R
R
2
V
L–
OUT
18
17
C
3
R
R
4
8
V L+
OUT
DSD1793
C
1
–
+
R
R
1
7
V
R+
R–
13
12
OUT
3
R
5
C
2
V
OUT
:
NOTE Example R and C values for f = 77 kHz, R1–R4: 3.6 kΩ, R5, R6: 3.3 kΩ, R7, R8: 680 Ω, C1: 1800 pF, C2, C3: 560 pF.
C
Figure 33. Connection Diagram for Monaural Mode Interface
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APPLICATION FOR EXTERNAL DIGITAL FILTER INTERFACE
DFMS = 0
ADR0
SDL
WDCK (Word Clock)
PLRCK
PBCK
PDATA
DBCK
SCK
1
2
3
4
5
28
27
26
25
24
BCK
DATA
SDA
DSDL
DSDR
SCK
External Filter Device
DSD1793
DFMS = 1
WDCK (Word Clock)
BCK
PLRCK
PBCK
PDATA
DBCK
SCK
ADR0
SDL
1
28
2
3
4
5
27
26
25
24
SDA
DSDL
DSDR
SCK
DSD1793
DATA_L
DATA_R
External Filter Device
Figure 34. Connection Diagram for External DIgital Filter (Internal DF Bypass Mode) Application
Application for Interfacing With an External Digital Filter
For some applications, it may be desirable to use an external digital filter to perform the interpolation function, as it
can provide improved stop-band attenuation when compared to the internal digital filter of the DSD1793.
The DSD1793 supports several external digital filters, including:
D Texas Instruments DF1704 and DF1706
D Pacific Microsonics PMD200 HDCD filter/decoder IC
D Programmable digital signal processors
The external digital filter application mode is accessed by programming the following bit in the corresponding control
register:
D DFTH = 1 (register 20)
The pins used to provide the serial interface for the external digital filter are shown in the connection diagram of
Figure 34. The word clock (WDCK) signal must be operated at 8× or 4× the desired sampling frequency, f .
S
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Pin Assignments When Using the External Digital Filter Interface
D PLRCK (pin 1): WDCK as word clock input
D PBCK (pin 2): BCK as bit clock for audio data
D PDATA (pin 3): DATA as monaural audio data input when the DFMS bit is not set to 1
D DSDL (pin 25): DATAL as L-channel audio data input when the DFMS bit is set to 1
D DSDR (pin 24): DATAR as R-channel audio data input when the DFMS bit is set to 1
Audio Format
The DSD1793 in the external digital filter interface mode supports right-justified audio formats including 16-bit, 20-bit,
and 24-bit audio data, as shown in Figure 35. The audio format is selected by the FMT[2:0] bits of control register 18.
1/4 f or 1/8 f
S
S
WDCK
BCK
Audio Data Word = 16-Bit
DATA
15 16
1
2
3
4
8
5
9
6
7
8
9
10 11 12 13 14 15 16
LSB
DATAL
DATAR
MSB
Audio Data Word = 20-Bit
DATA
19 20
1
5
2
6
3
4
8
5
9
6
7
10 11 12 13 14 15 16 17 18 19 20
LSB
DATAL
DATAR
MSB
Audio Data Word = 24-Bit
DATA
23 24
1
2
3
4
7
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
LSB
DATAL
DATAR
MSB
Figure 35. Audio Data Input Format for External Digital Filter (Internal DF Bypass Mode) Application
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System Clock (SCK) and Interface Timing
The DSD1793 in an application using an external digital filter requires the synchronization of WDCK and the system
clock. The system clock is phase-free with respect to WDCK. Interface timing among WDCK, BCK, DATA, DATAL,
and DATAR is shown in Figure 36.
WDCK
1.4 V
1.4 V
1.4 V
t
t
t
(LB)
(BCH)
(BCL)
BCK
t
t
(BCY)
(BL)
DATA
DATAL
DATAR
t
t
(DS)
(DH)
PARAMETER
MIN
20
7
MAX UNITS
t
t
t
t
t
t
t
BCK pulse cycle time
ns
ns
ns
ns
ns
ns
ns
(BCY)
(BCL)
(BCH)
(BL)
BCK pulse duration, LOW
BCK pulse duration, HIGH
7
BCK rising edge to WDCK falling edge
WDCK falling edge to BCK rising edge
DATA, DATAL, DATAR setup time
DATA, DATAL, DATAR hold time
5
5
(LB)
5
(DS)
5
(DH)
Figure 36. Audio Interface Timing for External Digital Filter (Internal DF Bypass Mode) Application
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Functions Available in the External Digital Filter Mode
The external digital filter mode allows access to the majority of the DSD1793 mode control functions.
The following table shows the register mapping available when the external digital filter mode is selected, along with
descriptions of functions which are modified when using this mode selection.
B15 B14 B13 B12 B11 B10
B9
0
B8
0
B7
B6
–
B5
–
B4
–
B3
–
B2
B1
–
B0
–
Register 16 R/W
Register 17 R/W
Register 18 R/W
Register 19 R/W
Register 20 R/W
Register 21 R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
–
–
–
0
1
–
–
–
–
–
–
–
–
1
0
–
FMT2 FMT1 FMT0
–
–
–
1
1
REV
–
–
SRST
–
–
0
–
–
OPE
–
DFMS
–
INZD
OS0
PCMZ
0
0
1
–
–
MONO CHSL OS1
0
1
–
–
–
–
–
–
Register 22
R
1
0
–
–
ZFGR ZFGL
:
NOTE –: Function is disabled. No operation even if data bit is set
FMT[2:0]: Audio Data Format Selection
Default value: 000
FMT[2:0]
000
Audio Data Format Select
16-bit right-justified format (default)
20-bit right-justified format
24-bit right-justified format
N/A
001
010
Other
OS[1:0]: Delta-Sigma Modulator Oversampling Rate Selection
Default value: 00
OS[1:0]
00
Operation Speed Select
8 times WDCK (default)
4 times WDCK
01
10
16 times WDCK
11
Reserved
The effective oversampling rate is determined by the oversampling performed by both the external digital filter and
the delta-sigma modulator. For example, if the external digital filter is 8× oversampling, and the user selects
OS[1:0] = 00, then the delta-sigma modulator oversamples by 8×, resulting in an effective oversampling rate of 64×.
The 16× WDCK oversampling rate is not available above a 100-kHz sampling rate. If the oversampling rate selected
is 16× WDCK, the system clock frequency must be over 256 f .
S
37
ꢀꢁ ꢀꢂ ꢃ ꢄ ꢅ
www.ti.com
SLES075B − MARCH 2003 − REVISED NOVEMBER 2006
APPLICATION FOR DSD FORMAT (DSD MODE) INTERFACE
PLRCK
PBCK
PDATA
DBCK
SCK
ADR0
SCL
1
2
3
4
5
28
27
26
25
24
SDA
Bit Clock
DSDL
DSDR
1
System Clock
DATA_L
DATA_R
DSD Decoder
DSD1793
(1)
2
The system clock is necessary for the initialization sequence and the I C interface operation.
Figure 37. Connection Diagram in DSD Mode
Feature
This mode is used for interfacing directly to a DSD decoder, which is found in Super Audio CDt (SACD) applications.
The DSD mode is accessed by programming the following bit in the corresponding control register:
D DSD = 1 (register 20)
The DSD mode provides a low-pass filtering function. The filtering is provided using an analog FIR filter structure.
Four FIR responses are available, and are selected via DMF[1:0] of control register 18.
Pin Assignment When Using the DSD Format Interface
D DSDL (pin 25): L-channel DSD data input
D DSDR (pin 24): R-channel DSD data input
D DBCK (pin 4): Bit clock (BCK) for DSD data
Super Audio CD is a trademark of Sony Kabushiki Kaisha TA Sony Corporation, Japan.
38
ꢀ ꢁꢀ ꢂꢃ ꢄꢅ
www.ti.com
SLES075B − MARCH 2003 − REVISED NOVEMBER 2006
Requirements for Bit Clock and System Clock
The bit clock (DBCK) for DSD mode is required at pin 4 of the DSD1793. The frequency of the bit clock can be N
times the sampling frequency. Generally, N is 64 in DSD applications.
The interface timing between the bit clock and DSDL, DSDR is required to meet the setup and hold time specifications
shown in Figure 39.
2
The system clock is necessary for the initialization sequence and the I C interface operation.
t = 1/(64 × 44.1 kHz)
DBCK
DSDL
DSDR
D0
D1
D2
D3
D4
Figure 38. Normal Data Output Form From DSD Decoder
t
t
(BCL)
(BCH)
1.4 V
1.4 V
DBCK
t
(BCY)
DSDL
DSDR
t
t
(DH)
(DS)
PARAMETER
MIN
MAX UNITS
(1)
t
DBCK pulse cycle time
DBCK high-level time
DBCK low-level time
85
ns
ns
ns
ns
ns
(BCY)
t
30
30
10
10
(BCH)
t
(BCL)
(DS)
(DH)
t
t
DSDL, DSDR setup time
DSDL, DSDR hold time
(1)
2.8224 MHz × 4. (2.8224 MHz = 64 × 44.1 kHz. This value is specified as a
sampling rate of DSD.)
Figure 39. Timing for DSD Audio Interface
39
ꢀ
ꢁ
ꢀ
ꢂ
ꢃ
ꢄ
ꢅ
www.ti.com
SLES075B − MARCH 2003 − REVISED NOVEMBER 2006
ANALOG FIR FILTER PERFORMANCE IN DSD MODE
GAIN
vs
GAIN
vs
FREQUENCY
FREQUENCY
0
−1
−2
−3
−4
−5
−6
0
−10
−20
−30
−40
−50
−60
f
= 185 kHz
c
(1)
Gain = –6.6 dB
0
50
100
150
200
0
500
1000
1500
f – Frequency – kHz
f – Frequency – kHz
Figure 40. DSD Filter-1, Low BW
Figure 41. DSD Filter-1, High BW
GAIN
vs
GAIN
vs
FREQUENCY
FREQUENCY
0
−1
−2
−3
−4
−5
−6
0
−10
−20
−30
−40
−50
−60
f
= 77 kHz
c
(1)
Gain
= –6 dB
0
50
100
150
200
0
500
1000
1500
f – Frequency – kHz
f – Frequency – kHz
Figure 42. DSD Filter-2, Low BW
Figure 43. DSD Filter-2, High BW
(1)
This gain is in comparison to PCM 0 dB, when the DSD input signal efficiency is 50%.
All specifications at DBCK = 2.8224 MHz (44.1 kHz × 64 f ), and 50% modulation DSD data input, unless otherwise noted.
S
40
ꢀ ꢁꢀ ꢂꢃ ꢄꢅ
www.ti.com
SLES075B − MARCH 2003 − REVISED NOVEMBER 2006
ANALOG FIR FILTER PERFORMANCE IN DSD MODE (CONTINUED)
GAIN
vs
GAIN
vs
FREQUENCY
FREQUENCY
0
−10
−20
−30
−40
−50
−60
0
−1
−2
−3
−4
−5
−6
f
= 85 kHz
c
(1)
Gain = –1.5 dB
0
500
1000
1500
0
50
100
150
200
f – Frequency – kHz
f – Frequency – kHz
Figure 44. DSD Filter-3, Low BW
Figure 45. DSD Filter-3, High BW
GAIN
vs
GAIN
vs
FREQUENCY
FREQUENCY
0
−1
−2
−3
−4
−5
−6
0
−10
−20
−30
−40
−50
−60
f
= 94 kHz
c
(1)
Gain = –3.3 dB
0
50
100
150
200
0
500
1000
1500
f – Frequency – kHz
f – Frequency – kHz
Figure 46. DSD Filter-4, Low BW
Figure 47. DSD Filter-4, High BW
(1)
This gain is in comparison to PCM 0 dB, when the DSD input signal efficiency is 50%.
All specifications at DBCK = 2.8224 MHz (44.1 kHz × 64 f ), and 50% modulation DSD data input, unless otherwise noted.
S
41
ꢀꢁ ꢀꢂ ꢃ ꢄ ꢅ
www.ti.com
SLES075B − MARCH 2003 − REVISED NOVEMBER 2006
DSD MODE CONFIGURATION AND FUNCTION CONTROLS
Configuration for the DSD Interface Mode
DSD = 1 (Register 20, B5)
B15 B14 B13 B12 B11 B10
B9
0
B8
0
B7
B6
B5
–
B4
B3
–
B2
–
B1
–
B0
Register 16 R/W
Register 17 R/W
Register 18 R/W
Register 19 R/W
Register 20 R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
–
–
–
–
–
–
–
0
1
–
–
–
–
–
1
0
–
–
–
–
DMF1 DMF0
–
–
1
1
REV
–
–
SRST
–
–
OPE
–
–
–
–
–
0
0
1
MONO CHSL OS1
OS0
–
Register 21
Register 22
R
R
0
1
–
–
–
–
–
DZ1
–
DZ0
1
0
–
–
–
–
ZFGR ZFGL
:
NOTE –: Function is disabled. No operation even if data bit is set
DMF[1:0]: Analog FIR Performance Selection
Default value: 00
DMF[1:0]
Analog FIR Performance Select
00
01
10
11
FIR-1 (default)
FIR-2
FIR-3
FIR-4
Plots for the four analog FIR filter responses are shown in the ANALOG FIR FILTER PERFORMANCE IN DSD
MODE section of this data sheet.
OS[1:0]: Analog-FIR Operation Speed Selection
Default value: 00
OS[1:0]
00
Operation Speed Select
f
f
(default)
DBCK
DBCK
01
/2
10
Reserved
f /4
DBCK
11
The OS bits in the DSD mode select the operating rate of the analog FIR. The OS bits must be set before setting
the DSD bit to 1.
42
ꢀ ꢁꢀ ꢂꢃ ꢄꢅ
www.ti.com
SLES075B − MARCH 2003 − REVISED NOVEMBER 2006
THEORY OF OPERATION
Upper
6 Bits
0–62
Level
ICOB
Decoder
0–66
Current
Segment
DAC
Analog
Voltage
Output
Digital
Input
Advanced
DWA
I/V
Converter
24 Bits
rd
3 -Order
8 f
S
5-Level
Sigma-Delta
0–4
Level
MSB
and
Lower 18 Bits
Figure 48. Advanced Segment DAC With I/V Converter
The DSD1793 uses TI’s advanced segment DAC architecture to achieve excellent dynamic performance and
improved tolerance to clock jitter. The DSD1793 provides balanced voltage outputs.
Digital input data via the digital filter is separated into 6 upper bits and 18 lower bits. The 6 upper bits are converted
to inverted complementary offset binary (ICOB) code. The lower 18 bits, in association with the MSB, are processed
by a five-level third-order delta-sigma modulator operated at 64 f by default. The 1 level of the modulator is equivalent
S
to the 1 LSB of the ICOB code converter. The data groups processed in the ICOB converter and third-order
delta-sigma modulator are summed together to an up to 66-level digital code, and then processed by data-weighted
averaging (DWA) to reduce the noise produced by element mismatch. The data of up to 66 levels from the DWA is
converted to an analog output in the differential-current segment section.
This architecture has overcome the various drawbacks of conventional multibit processing and also achieves
excellent dynamic performance.
43
ꢀꢁ ꢀꢂ ꢃ ꢄ ꢅ
www.ti.com
SLES075B − MARCH 2003 − REVISED NOVEMBER 2006
CONSIDERATIONS FOR APPLICATION CIRCUITS
PCB Layout Guidelines
A typical PCB floor plan for the DSD1793 is shown in Figure 49. A ground plane is recommended, with the analog
and digital sections being isolated from one another using a split or cut in the circuit board. The DSD1793 must be
oriented with the digital I/O pins facing the ground plane split/cut to allow for short, direct connections to the digital
audio interface and control signals originating from the digital section of the board. Separate power supplies are
recommended for the digital and analog sections of the board. This prevents the switching noise present on the digital
supply from contaminating the analog power supply and degrading the dynamic performance of the D/A converters.
In cases where a common 5-V supply would be used for the analog and digital sections, an inductance (RF choke,
ferrite bead) must be placed between the analog and digital 5-V supply connections to avoid coupling of the digital
switching noise into the analog circuitry. Figure 50 shows the recommended approach for single-supply applications.
Digital Power
+V DGND
Analog Power
AGND +5VA
+V
S
–V
S
D
REG
V
CC
Digital Logic
and
Audio
Processor
V
DD
DGND
Output
Circuits
DSD1793
AGND
Digital
Ground
Analog
Ground
Digital Section
Analog Section
Return Path for Digital Signals
Figure 49. Recommended PCB Layout
44
ꢀ ꢁꢀ ꢂꢃ ꢄꢅ
www.ti.com
SLES075B − MARCH 2003 − REVISED NOVEMBER 2006
Power Supplies
+5V AGND +V
RF Choke or Ferrite Bead
–V
S
S
REG
V
CC
V
DD
V
DD
DGND
Output
Circuits
DSD1793
AGND
Common
Ground
Digital Section
Analog Section
Figure 50. Single-Supply PCB Layout
Bypass and Decoupling Capacitor Requirements
Various sized decoupling capacitors can be used, with no special tolerances being required. All capacitors must be
located as close as possible to the appropriate pins of the DSD1793 to reduce noise pickup from surrounding circuitry.
Aluminum electrolytic capacitors that are designed for hi-fi audio applications are recommended for larger values,
while metal film or monolithic ceramic capacitors are used for smaller values.
Post-LPF Design
By proper choice of the operational amplifier and resistors used in the post-LPF circuit, excellent performance of the
DSD1793 should be achieved. To obtain 0.001% THD+N and 113 dB signal-to-noise-ratio audio performance, the
THD+N and input noise performance of the operational amplifier should be considered. This is because the input
noise of the operational amplifier contributes directly to the output noise level of the application. The V
DSD1793 and the input resistor of the post-LPF circuit must be connected as closely as possible.
pin of the
OUT
Out-of-band noise level and attenuated sampling spectrum level are much lower than for typical delta-sigma type
DACs due to the combination of a high-performance digital filter and advanced segment DAC architecture. The use
of a second-order or third-order post-LPF is recommended for the post-LPF of the DSD1793. The cutoff frequency
of the post-LPF depends on the application. For example, there are many sampling-rate operations such as f = 44.1
S
kHz on CDDA, f = 96 kHz on DVD-M, f = 192 kHz on DVD-A, f = 64 f on DSD (SACD).
S
S
S
S
45
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DSD1793DB
ACTIVE
ACTIVE
SSOP
SSOP
DB
DB
28
28
47
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-25 to 85
-25 to 85
DSD1793
DSD1793
DSD1793DBR
2000 RoHS & Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DSD1793DBR
SSOP
DB
28
2000
330.0
17.4
8.5
10.8
2.4
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SSOP DB 28
SPQ
Length (mm) Width (mm) Height (mm)
336.6 336.6 28.6
DSD1793DBR
2000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
DB SSOP
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
DSD1793DB
28
47
500
10.6
500
9.6
Pack Materials-Page 3
PACKAGE OUTLINE
DB0028A
SSOP - 2 mm max height
S
C
A
L
E
1
.
5
0
0
SMALL OUTLINE PACKAGE
C
8.2
7.4
TYP
A
0.1 C
SEATING
PIN 1 INDEX AREA
PLANE
26X 0.65
28
1
2X
10.5
9.9
8.45
NOTE 3
14
15
0.38
0.22
28X
0.15
C A B
5.6
5.0
B
NOTE 4
2 MAX
0.25
GAGE PLANE
(0.15) TYP
SEE DETAIL A
0.95
0.55
0.05 MIN
0 -8
A
15
DETAIL A
TYPICAL
4214853/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.
www.ti.com
EXAMPLE BOARD LAYOUT
DB0028A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
SYMM
28X (1.85)
(R0.05) TYP
28
1
28X (0.45)
26X (0.65)
SYMM
14
15
(7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4214853/B 03/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DB0028A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
28X (1.85)
SYMM
(R0.05) TYP
28
1
28X (0.45)
26X (0.65)
SYMM
14
15
(7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4214853/B 03/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated
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SI9122E
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