DSLVDS1001DBVT [TI]
400Mbps LVDS 单路高速差动驱动器 | DBV | 5 | -40 to 85;
| 型号： | DSLVDS1001DBVT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 400Mbps LVDS 单路高速差动驱动器 | DBV | 5 | -40 to 85 驱动 驱动器 |
| 文件： | 总27页 (文件大小：1435K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DSLVDS1001
ZHCSIL1A –JULY 2018–REVISED DECEMBER 2018
DSLVDS1001 400Mbps 单通道 LVDS 驱动器
1 特性
3 说明
1
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旨在用于信号传输速率高达 400Mbps 的应用
DSLVDS1001 器件是一款单通道、低电压差动信号
(LVDS) 驱动器，专为需要低功耗、低噪声和高数据速
率的 应用 而设计。此外，它还可以尽可能减小短路故
障电流。该器件旨在使用 LVDS 技术支持高达
400Mbps (200MHz) 的数据速率。
单个 3.3V 电源（3V 至 3.6V 的范围）
700ps（100ps 典型值）最大差动偏斜
1.5ns 最大传播延迟
驱动小摆幅 (±350mV) 差动信号电平
断电保护（TRI-STATE 中的输出）
直通引脚排列可简化 PCB 布局
低功耗（3.3V 典型电压下为 23mW）
5 引脚 SOT-23 封装
DSLVDS1001 接受 3.3V LVCMOS/LVTTL 输入电平，
输出具有低电磁干扰 (EMI) 的低电压（±350mV 典型
值）差动信号。该器件采用旨在轻松实施 PCB 布局的
5 引脚 SOT-23 封装。DSLVDS1001 可与配套的单线
接收器 DSLVDS1002 或任何 LVDS 接收器配对，提
供高速 LVDS 接口。
符合或超出 ANSI TIA/EIA-644-A 标准
工业工作温度范围（–40°C 至 +85°C）
器件信息(1)
2 应用
器件型号
封装
SOT-23 (5)
封装尺寸（标称值）
•
•
•
•
•
•
•
•
•
•
板对板通信
DSLVDS1001
2.90mm × 1.60mm
测试和测量
电机驱动器
LED 视频墙
无线基础设施
电信基础设施
多功能打印机
NIC 卡
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
功能图
OUT +
LVCMOS/LVTLL IN
机架式服务器
超声波扫描仪
OUT -
典型应用
VCC
GND
OUT +
OUT -
LVCMOS/LVTTL IN
Driver
Receiver
DSLVDS1001
DSLVDS1002
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNLS622
DSLVDS1001
ZHCSIL1A –JULY 2018–REVISED DECEMBER 2018
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics.......................................... 5
6.7 Typical Characteristics ............................................. 6
Parameter Measurement Information .................. 7
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 8
8.3 Feature Description................................................... 8
8.4 Device Functional Modes.......................................... 8
9
Application and Implementation .......................... 9
9.1 Application Information.............................................. 9
9.2 Typical Application .................................................... 9
9.3 Design Requirements................................................ 9
9.4 Detailed Design Procedure ..................................... 10
9.5 Application Curve.................................................... 13
10 Power Supply Recommendations ..................... 14
10.1 Power Supply Considerations............................... 14
11 Layout................................................................... 14
11.1 Layout Guidelines ................................................. 14
11.2 Layout Example .................................................... 18
12 器件和文档支持 ..................................................... 19
12.1 文档支持................................................................ 19
12.2 接收文档更新通知 ................................................. 19
12.3 社区资源................................................................ 19
12.4 商标....................................................................... 19
12.5 静电放电警告......................................................... 19
12.6 术语表 ................................................................... 19
13 机械、封装和可订购信息....................................... 19
7
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (July 2018) to Revision A
Page
•
•
将器件状态从“预告信息”更改为“生产数据” ............................................................................................................................. 1
添加了文档支持 部分 ............................................................................................................................................................ 19
2
Copyright © 2018, Texas Instruments Incorporated
DSLVDS1001
www.ti.com.cn
ZHCSIL1A –JULY 2018–REVISED DECEMBER 2018
5 Pin Configuration and Functions
DVB Package
5-Pin SOT-23
Top View
(1) See Package Number DBV (R-PDSO-G5)
Pin Functions
PIN
I/O
DESCRIPTION
NO.
1
NAME
VDD
I
I
Power Supply Pin, +3.3 V ± 0.3 V
Ground Pin
2
GND
3
OUT-
O
O
I
Inverting Driver Output Pin
Noninverting Driver Output Pin
LVCMOS/LVTTL Driver Input Pin
4
OUT+
5
LVCMOS/LVTTL IN
Copyright © 2018, Texas Instruments Incorporated
3
DSLVDS1001
ZHCSIL1A –JULY 2018–REVISED DECEMBER 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
MAX
4
UNIT
V
Supply Voltage
VDD
LVCMOS input voltage (TTL IN)
LVDS output voltage (OUT±)
LVDS output short circuit current
Lead Temperature – Soldering
Maximum Junction Temperature
Storage temperature, Tstg
3.6
3.9
24
V
V
mA
°C
°C
°C
260
150
150
−65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±9000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±2000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±9000
V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±2000
V may actually have higher performance.
6.3 Recommended Operating Conditions
MIN
3
TYP
3.3
MAX
3.6
UNIT
V
Supply Voltage (VDD
)
Temperature (TA)
–40
+25
+85
°C
6.4 Thermal Information
DSLVDS1001
DBV (SOT-23)
5 PINS
179.4
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
88.7
36.2
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
4.6
ψJB
35.7
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
4
Copyright © 2018, Texas Instruments Incorporated
DSLVDS1001
www.ti.com.cn
ZHCSIL1A –JULY 2018–REVISED DECEMBER 2018
6.5 Electrical Characteristics
Over Recommended Supply Voltage and Operating Temperature ranges, unless otherwise specified.(1)(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
|VOD
|
Output Differential Voltage
RL = 100 Ω
(图 7)
250
350
450
mV
OUT+, OUT– Pins
ΔVOD
VOD Magnitude Change
Offset Voltage
RL = 100 Ω
(图 8)
OUT+, OUT– Pins
3
35
1.375
25
mV
V
VOS
RL = 100 Ω
(图 7)
OUT+, OUT– Pins
1.125
1.25
ΔVOS
Offset Magnitude Change
Power-off Leakage
RL = 100 Ω
(图 7)
OUT+, OUT– Pins
mV
IOFF
IOS
VOUT = 3.6 V or GND, VDD = 0 V
OUT+, OUT– Pins
±2
−5
−5
±15
−20
−12
μA
mA
mA
Output Short Circuit
Current(3)
VOUT+ and VOUT− = 0 V
OUT+, OUT– Pins
IOSD
Differential Output Short
Circuit Current(3)
VOD = 0 V
OUT+, OUT– Pins
VIH
VIL
IIH
Input High Voltage
Input Low Voltage
Input High Current
TTL IN Pin
TTL IN Pin
2
VDD
0.8
V
V
GND
VIN = 3.3 V or 2.4 V
TTL IN Pin
±2
±2
±15
μA
IIL
Input Low Current
VIN = GND or 0.5 V
TTL IN Pin
±15
μA
CIN
IDD
Input Capacitance
TTL IN Pin
3
5
7
pF
Power Supply Current
No Load
VIN = VDD or GND
VIN = VDD or GND
8
mA
RL = 100 Ω
10
(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except VOD
.
(2) All typicals are given for: VDD = +3.3 V and TA = +25°C.
(3) Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
6.6 Switching Characteristics
Over Recommended Supply Voltage and Operating Temperature Ranges, unless otherwise specified.(1)(2)(3)(4)
PARAMETER
TEST CONDITIONS
RL = 100Ω, CL = 15 pF
(图 9 and 图 10)
MIN
0.5
0.5
0
TYP
1
MAX UNIT
tPHLD
tPLHD
tSKD1
tSKD4
tr
Differential Propagation Delay High to Low
1.5
1.5
0.7
1.2
1
ns
ns
Differential Propagation Delay Low to High
1.1
0.1
0.4
0.5
0.5
250
(5)
Differential Pulse Skew |tPHLD − tPLHD
Differential Part to Part Skew(6)
Rise Time
|
ns
0
ns
0.2
0.2
200
ns
tf
Fall Time
1
ns
fMAX
Maximum Operating Frequency(7)
MHz
(1) All typicals are given for: VDD = +3.3 V and TA = +25°C.
(2) These parameters are specified by design, and not tested in production. The limits are based on statistical analysis of the device
performance over PVT (process, voltage, temperature) ranges.
(3) CL includes probe and fixture capacitance.
(4) Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50 Ω, tr ≤ 1 ns, tf ≤ 1 ns (10%-90%).
(5) tSKD1, |tPHLD − tPLHD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative
going edge of the same channel.
(6) tSKD2, part to part skew, is the differential channel to channel skew of any event between devices. This specification applies to devices
over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min|
differential propagation delay.
(7) fMAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, 0V to 3V. Output criteria: duty cycle = 45%/55%, VOD > 250
mV. The parameter is specified by design. The limit is based on the statistical analysis of the device over the PVT range by the
transitions times (tTLH and tTHL).
Copyright © 2018, Texas Instruments Incorporated
5
DSLVDS1001
ZHCSIL1A –JULY 2018–REVISED DECEMBER 2018
www.ti.com.cn
6.7 Typical Characteristics
图 1. Loaded Supply Current vs Power Supply Voltage
图 2. No Load Supply Current vs Power Supply Voltage
图 3. Output Short-Circuit Current vs Power Supply Voltage
图 4. Differential Output Short-Circuit Current vs Power
Supply Voltage
图 5. Output Differential Voltage vs Power Supply Voltage
图 6. Offset Voltage vs Power Supply Voltage
6
版权 © 2018, Texas Instruments Incorporated
DSLVDS1001
www.ti.com.cn
ZHCSIL1A –JULY 2018–REVISED DECEMBER 2018
7 Parameter Measurement Information
图 7. Differential Driver DC Test Circuit
图 8. Differential Driver Full Load DC Test Circuit
图 9. Differential Driver Propagation Delay and Transition Time Test Circuit
图 10. Differential Driver Propagation Delay and Transition Time Waveforms
版权 © 2018, Texas Instruments Incorporated
7
DSLVDS1001
ZHCSIL1A –JULY 2018–REVISED DECEMBER 2018
www.ti.com.cn
8 Detailed Description
8.1 Overview
The DSLVDS1001 device is a single-channel, low-voltage differential signaling (LVDS) line driver. It operates
from a single supply that is nominally 3.3-V, but can be as low as 3-V and as high as 3.6-V. The input signal to
the DSLVDS1001 is an LVCMOS/LVTTL signal. The output of the device is a differential signal complying with
the LVDS standard (TIA/EIA-644). The differential output signal operates with a signal level of 350 mV,
nominally, at a common-mode voltage of 1.2 V. This low differential output voltage results in low emmsions
durning electromagnetic compatability (EMC) testing. The differential nature of the output provides immunity to
common-mode coupled signals that the driven signal may experience. The DSLVDS1001 device is intended to
drive a 100-Ω transmission line. This transmission line may be a printed-circuit board (PCB) or cabled
interconnect. With transmission lines, the optimum signal quality and power delivery is reached when the
transmission line is terminated with a load equal to the characteristic impedance of the interconnect. Likewise,
the driven 100-Ω transmission line should be terminated with a matched resistance.
8.2 Functional Block Diagram
OUT +
LVCMOS/LVTLL IN
OUT -
8.3 Feature Description
8.3.1 DSLVDS1001 Driver Functionality
As can be seen in 表 1, the driver single-ended input to differential output relationship is defined. When the driver
input is left open, the differential output is undefined.
表 1. DSLVDS1001 Driver Functionality
INPUT
OUTPUTS
LVCMOS/LVTTL IN
OUT +
OUT -
H
L
H
L
?
L
H
?
Open
8.3.2 Driver Output Voltage and Power-On Reset
The DSLVDS1001 driver operates and meets all the specified performance requirements for supply voltages in
the range of 3 V to 3.6 V. When the supply voltage drops below 1.5-V (or is turning on and has not yet reached
1.5-V), power-on reset circuitry set the driver output to a high-impedance state.
8.3.3 Driver Offset
An LVDS-compliant driver is required to maintain the common-mode output voltage at 1.2 V (±75 mV). The
DSLVDS1001 incorporates sense circuitry and a control loop to source common-mode current and keep the
output signal within specified values. Further, the device maintains the output common-mode voltage at this set
point over the full 3-V to 3.6-V supply range.
8.4 Device Functional Modes
The device has one mode of operation that applies when operated within the Recommended Operating
Conditions.
8
版权 © 2018, Texas Instruments Incorporated
DSLVDS1001
www.ti.com.cn
ZHCSIL1A –JULY 2018–REVISED DECEMBER 2018
9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The DSLVDS1001 device is a single-channel LVDS driver. The functionality of this device is simple, yet
extremely flexible, leading to its use in designs ranging from wireless base stations to desktop computers. The
varied class of potential applications share features and applications discussed in the paragraphs below.
9.2 Typical Application
9.2.1 Point-to-Point Communications
The most basic application for LVDS buffers, as found in this data sheet, is for point-to-point communications of
digital data, as shown in 图 11.
VCC
GND
OUT +
OUT -
LVCMOS/LVTTL IN
Driver
Receiver
DSLVDS1001
DSLVDS1002
图 11. Typical Application
A point-to-point communications channel has a single transmitter (driver) and a single receiver. This
communications topology is often referred to as simplex. In 图 11, the driver receives a single-ended input signal
and the receiver outputs a single-ended recovered signal. The LVDS driver converts the single-ended input to a
differential signal for transmission over a balanced interconnecting media of 100-Ω characteristic impedance. The
conversion from a single-ended signal to an LVDS signal retains the digital data payload while translating to a
signal whose features are more appropriate for communication over extended distances or in a noisy
environment.
9.3 Design Requirements
表 2 shows the design parameters for this example.
表 2. Design Parameters
DESIGN PARAMETERS
Driver Supply Voltage (VCC
Driver Input Voltage
EXAMPLE VALUE
3 to 3.6 V
0 to 3.6 V
DC to 400 Mbps
100 Ω
)
Driver Signaling Rate
Interconnect Characteristic Impedance
Termination Resistance
100 Ω
Number of Receiver Nodes
1
Ground shift between driver and receiver
±1 V
版权 © 2018, Texas Instruments Incorporated
9
DSLVDS1001
ZHCSIL1A –JULY 2018–REVISED DECEMBER 2018
www.ti.com.cn
9.4 Detailed Design Procedure
9.4.1 Driver Supply Voltage
The DSLVDS1001 driver is operated from a single supply. The device can support operation with a supply as low
as 3 V and as high as 3.6 V. The driver output voltage is dependent upon the chosen supply voltage. The
minimum output voltage stays within the specified LVDS limits (247 mV to 450 mV) for a 3.3 V supply. If the
supply range is between 3 V and 3.6 V, the minimum output voltage may be as low as 150 mV. If a
communication link is designed to operate with a supply within this lower range, the channel noise margin must
be looked at carefully to ensure error-free operation.
9.4.2 Driver Bypass Capacitance
Bypass capacitors play a key role in power distribution circuitry. Specifically, they create low-impedance paths
between power and ground. At low frequencies, a good digital power supply offers very low-impedance paths
between its terminals. However, as higher frequency currents propagate through power traces, the source is
quite often incapable of maintaining a low-impedance path to ground. Bypass capacitors are used to address this
shortcoming. Usually, large bypass capacitors (10 μF to 1000 μF) at the board-level do a good job up into the
kHz range. Due to their size and length of their leads, they tend to have large inductance values at the switching
frequencies of modern digital circuitry. To solve this problem, one must resort to the use of smaller capacitors
(nF to μF range) installed locally next to the integrated circuit.
Multilayer ceramic chip or surface-mount capacitors (size 0603 or 0805) minimize lead inductances of bypass
capacitors in high-speed environments, because their lead inductance is about 1 nH. For comparison purposes,
a typical capacitor with leads has a lead inductance around 5 nH.
The value of the bypass capacitors used locally with LVDS chips can be determined by the following formula
according to Johnson(1), equations 8.18 to 8.21. A conservative rise time of 200 ps and a worst-case change in
supply current of 1 A covers the whole range of LVDS devices offered by Texas Instruments. In this example, the
maximum power supply noise tolerated is 200 mV. This figure varies, however, depending on the noise budget
(1)
available in the design.
DIMaximum Step Change Supply Current
æ
ö
Cchip
=
´ TRise Time
ç
÷
DVMaximum Power Supply Noise
è
ø
(1)
(2)
1A
æ
ö
CLVDS
=
´ 200 ps = 0.001mF
ç
è
÷
ø
0.2V
图 12 lowers lead inductance and covers intermediate frequencies between the board-level capacitor (>10 µF)
and the value of capacitance found above (0.001 µF). Place the smallest value of capacitance as close to the
chip as possible.
3.3 V
0.1 µF
0.001 µF
图 12. Recommended LVDS Bypass Capacitor Layout
9.4.3 Driver Input Voltage
The DSLVDS1001 input is designed to support a wide input voltage range. The input stage can accept signals as
high as 3.6 V.
9.4.4 Driver Output Voltage
The DSLVDS1001 driver output is a 1.2-V common-mode voltage, with a nominal differential output signal of 350
mV. This 350 mV is the absolute value of the differential swing (VOD = |V+– V–|). The peak-to-peak differential
voltage is twice this value, or 700 mV.
(1) Howard Johnson & Martin Graham.1993. High Speed Digital Design – A Handbook of Black Magic. Prentice Hall PRT. ISBN number
013395724.
10
版权 © 2018, Texas Instruments Incorporated
DSLVDS1001
www.ti.com.cn
ZHCSIL1A –JULY 2018–REVISED DECEMBER 2018
Detailed Design Procedure (接下页)
In this example, the LVDS receiver thresholds are ±100 mV. With these receiver decision thresholds, it is clear
that the disadvantage of operating the driver with a lower supply will be noise margin. With fully-compliant LVDS
drivers and receivers, TI expects a minimum noise margin of approximately 150 mV (247-mV minimum output
voltage – 100-mV maximum input requirement). If the DSLVDS1001 operates within the 3 V to 3.6 V supply
range, the minimum noise margin will drop to 150 mV.
9.4.5 Interconnecting Media
The physical communication channel between the driver and the receiver may be any balanced paired metal
conductors meeting the requirements of the LVDS standard, with the key points included here. This media may
be a twisted pair, a twinax cable, a flat ribbon cable, or PCB traces.
The nominal characteristic impedance of the interconnect should be between 100 Ω and 120 Ω with a variation
no more than 10% (90 Ω to 132 Ω).
9.4.6 PCB Transmission Lines
As per the LVDS Owner's Manual Design Guide, 4th Edition (SNLA187), 图 13 depicts several transmission line
structures commonly used in printed-circuit boards (PCBs). Each structure has a signal line and a return path
with a uniform cross-section along its length. A microstrip is a signal trace on the top (or bottom) layer, separated
by a dielectric layer from its return path in a ground or power plane. A stripline is a signal trace in the inner layer,
with a dielectric layer in between a ground plane above and below the signal trace. The dimensions of the
structure and the dielectric material properties determine the characteristic impedance of the transmission line
(also called controlled-impedance transmission line).
When two signal lines are placed close by, they form a pair of coupled transmission lines. 图 13 shows examples
of edge-coupled microstrip lines, and edge-coupled or broad-side-coupled striplines. When excited by differential
signals, the coupled transmission line is referred to as a differential pair. The characteristic impedance of each
line is called odd-mode impedance. The sum of the odd-mode impedances of each line is the differential
impedance of the differential pair. In addition to the trace dimensions and dielectric material properties, the
spacing between the two traces determines the mutual coupling and impacts the differential impedance. When
the two lines are immediately adjacent (like when S is less than 2W, for example), the differential pair is called a
tightly-coupled differential pair. To maintain constant differential impedance along the length, it is important to
keep the trace width and spacing uniform along the length, as well as maintain good symmetry between the two
lines.
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11
DSLVDS1001
ZHCSIL1A –JULY 2018–REVISED DECEMBER 2018
www.ti.com.cn
Detailed Design Procedure (接下页)
Single-Ended Microstrip
Single-Ended Stripline
W
W
T
H
H
T
H
≈
’
≈
∆
«
5.98 H
0.8 W + T
’
÷
◊
1.9 2 H+ T
87
[
]
60
Z0
=
ln
Z0
=
ln
∆
∆
÷
÷
er +1.41
0.8 W + T
[
]
er
«
◊
Edge-Coupled
Edge-Coupled
S
S
H
H
Differential Microstrip
Differential Stripline
s
s
≈
’
÷
≈
’
÷
-0.96 ì
-2.9 ì
H
H
∆
∆
Zdiff = 2 ì Z0
ì
1- 0.48 ì e
Zdiff = 2 ì Z0
ì
1- 0.347e
∆
«
÷
◊
∆
«
÷
◊
Co-Planar Coupled
Microstrips
Broad-Side Coupled
Striplines
W
W
W
G
S
G
H
S
H
图 13. Controlled-Impedance Transmission Lines
9.4.7 Termination Resistor
As shown earlier, an LVDS communication channel employs a current source driving a transmission line that is
terminated with a resistive load. This load serves to convert the transmitted current into a voltage at the receiver
input. To ensure incident wave switching (which is necessary to operate the channel at the highest signaling
rate), the termination resistance should be matched to the characteristic impedance of the transmission line. The
designer should ensure that the termination resistance is within 10% of the nominal media characteristic
impedance. If the transmission line is targeted for 100-Ω impedance, the termination resistance should be
between 90 Ω and 110 Ω.
The line termination resistance should be placed as close to the receiver as possible to minimize the stub length
from the resistor to the receiver.
Remember to only place line termination resistors at the end(s) of the transmission line in these multidrop
topologies.
12
版权 © 2018, Texas Instruments Incorporated
DSLVDS1001
www.ti.com.cn
ZHCSIL1A –JULY 2018–REVISED DECEMBER 2018
9.5 Application Curve
图 14. DSLVDS1001 Performance: Data Rate vs Cable Length
版权 © 2018, Texas Instruments Incorporated
13
DSLVDS1001
ZHCSIL1A –JULY 2018–REVISED DECEMBER 2018
www.ti.com.cn
10 Power Supply Recommendations
10.1 Power Supply Considerations
The DSLVDS1001 driver is designed to operate from a single power supply with supply voltage in the range of 3
V to 3.6 V. In a typical application, a driver and a receiver may be on separate boards, or even separate
equipment. In these cases, separate supplies would be used at each location. The expected ground potential
difference between the driver power supply and the receiver power supply would be less than |±1 V|. Board level
and local device level bypass capacitance should be used.
11 Layout
11.1 Layout Guidelines
11.1.1 Microstrip vs. Stripline Topologies
As per the LVDS Application and Data Handbook (SLLD009), printed-circuit boards usually offer designers two
transmission line options: microstrip and stripline. Microstrips are traces on the outer layer of a PCB, as shown in
图 15.
图 15. Microstrip Topology
On the other hand, striplines are traces between two ground planes. Striplines are less prone to emissions and
susceptibility problems because the reference planes effectively shield the embedded traces. However, from the
standpoint of high-speed transmission, juxtaposing two planes creates additional capacitance. TI recommends
routing LVDS signals on microstrip transmission lines, if possible. The PCB traces allow designers to specify the
necessary tolerances for ZO based on the overall noise budget and reflection allowances. Footnotes 1(2), 2(3)
,
and 3(4) provide formulas for ZO and tPD for differential and single-ended traces.
(2) (3) (4)
图 16. Stripline Topology
(2) Howard Johnson & Martin Graham.1993. High Speed Digital Design – A Handbook of Black Magic. Prentice Hall PRT. ISBN number
013395724.
(3) Mark I. Montrose. 1996. Printed Circuit Board Design Techniques for EMC Compliance. IEEE Press. ISBN number 0780311310.
(4) Clyde F. Coombs, Jr. Ed, Printed Circuits Handbook, McGraw Hill, ISBN number 0070127549.
14
版权 © 2018, Texas Instruments Incorporated
DSLVDS1001
www.ti.com.cn
ZHCSIL1A –JULY 2018–REVISED DECEMBER 2018
Layout Guidelines (接下页)
11.1.2 Dielectric Type and Board Construction
The speeds at which signals travel across the board dictates the choice of dielectric. FR-4, or equivalent, usually
provides adequate performance for use with LVDS signals. If rise or fall times of LVCMOS/LVTTL signals are
less than 500 ps, empirical results indicate that a material with a dielectric constant near 3.4, such as Rogers™
4350 or Nelco N4000-13 is better suited. When the designer chooses the dielectric, there are several parameters
pertaining to the board construction that can affect performance. The following set of guidelines were developed
experimentally through several designs involving LVDS devices:
•
•
•
•
Copper weight: 15 g or 1/2 oz start, plated to 30 g or 1 oz
All exposed circuitry should be solder-plated (60/40) to 7.62 μm or 0.0003 in (minimum).
Copper plating should be 25.4 μm or 0.001 in (minimum) in plated-through-holes.
Solder mask over bare copper with solder hot-air leveling
11.1.3 Recommended Stack Layout
Following the choice of dielectrics and design specifications, the designer must decide how many levels to use in
the stack. To reduce the LVCMOS/LVTTL to LVDS crosstalk, it is a good practice to have at least two separate
signal planes as shown in 图 17.
Layer 1: Routed Plane (LVDS Signals)
Layer 2: Ground Plane
Layer 3: Power Plane
Layer 4: Routed Plane (TTL/CMOS Signals)
图 17. Four-Layer PCB
注
The separation between layers 2 and 3 should be 127 μm (0.005 in). By keeping the
power and ground planes tightly coupled, the increased capacitance acts as a bypass for
transients.
One of the most common stack configurations is the six-layer board, as shown in 图 18.
Layer 1: Routed Plane (LVDS Signals)
Layer 2: Ground Plane
Layer 3: Power Plane
Layer 4: Ground Plane
Layer 5: Ground Plane
Layer 4: Routed Plane (TTL Signals)
图 18. Six-Layer PCB
In this particular configuration, it is possible to isolate each signal layer from the power plane by at least one
ground plane. The result is improved signal integrity, but fabrication is more expensive. Using the 6-layer board is
preferable, because it offers the layout designer more flexibility in varying the distance between signal layers and
referenced planes, in addition to ensuring reference to a ground plane for signal layers 1 and 6.
11.1.4 Separation Between Traces
The separation between traces can depend on several factors, but the amount of coupling that can be tolerated
usually dictates the actual separation. Low-noise coupling requires close coupling between the differential pair of
an LVDS link to benefit from the electromagnetic field cancellation. The traces should be 100-Ω differential and
thus coupled in the manner that best fits this requirement. In addition, differential pairs should have the same
electrical length to ensure that they are balanced, thus minimizing problems with skew and signal reflection.
版权 © 2018, Texas Instruments Incorporated
15
DSLVDS1001
ZHCSIL1A –JULY 2018–REVISED DECEMBER 2018
www.ti.com.cn
Layout Guidelines (接下页)
In the case of two adjacent single-ended traces, one should use the 3-W rule: the distance between two traces
must be greater than two times the width of a single trace, or three times its width measured from trace center to
trace center. This increased separation effectively reduces the potential for crosstalk. The same rule should be
applied to the separation between adjacent LVDS differential pairs, whether the traces are edge-coupled or
broad-side-coupled.
W
LVDS
Pair
Minimum spacing as
defined by PCB vendor
Differential Traces
S =
W
í 2 W
Single-Ended Traces
TTL/CMOS
Trace
W
图 19. 3-W Rule for Single-Ended and Differential Traces (Top View)
注
Exercise caution when using autorouters, because they do not always account for all
factors affecting crosstalk and signal reflection. For instance, it is best to avoid sharp 90°
turns to prevent discontinuities in the signal path. Using successive 45° turns tends to
minimize reflections.
11.1.5 Crosstalk and Ground Bounce Minimization
To reduce crosstalk, it is important to provide a return path to high-frequency currents that is as close as possible
to its originating trace. A ground plane usually achieves this. Because the returning currents always choose the
path of lowest inductance, they are most likely to return directly under the original trace, thus minimizing
crosstalk. Lowering the area of the current loop lowers the potential for crosstalk. Traces kept as short as
possible with an uninterrupted ground plane running beneath them emit the minimum amount of electromagnetic
field strength. Discontinuities in the ground plane increase the return path inductance and should be avoided.
11.1.6 Decoupling
Each power or ground lead of a high-speed device should be connected to the PCB through a low inductance
path. For best results, one or more vias are used to connect a power or ground pin to the nearby plane. Ideally,
via placement is immediately adjacent to the pin to avoid adding trace inductance. Placing a power plane closer
to the top of the board reduces the effective via length and its associated inductance.
V
Via
GND
Via
CC
TOP signal layer + GND fill
1 plane
4 mil
6 mil
V
DD
2 mil
Buried capacitor
>
GND plane
Signal layer
GND plane
Signal layers
V
plane
CC
Signal layer
GND plane
Buried capacitor
>
V
2 plane
DD
4 mil
6 mil
BOTTOM signal layer + GND fill
Typical 12-Layer PCB
图 20. Low-Inductance, High-Capacitance Power Connection
16
版权 © 2018, Texas Instruments Incorporated
DSLVDS1001
www.ti.com.cn
ZHCSIL1A –JULY 2018–REVISED DECEMBER 2018
Layout Guidelines (接下页)
Bypass capacitors should be placed close to VDD pins. They can be placed conveniently near the corners or
underneath the package to minimize the loop area. This extends the useful frequency range of the added
capacitance. Small-physical-size capacitors, such as 0402 or even 0201, or X7R surface-mount capacitors
should be used to minimize body inductance of capacitors. Each bypass capacitor is connected to the power and
ground plane through vias tangent to the pads of the capacitor as shown in 图 21(a).
An X7R surface-mount capacitor of size 0402 has about 0.5-nH body inductance. At frequencies above 30 MHz
or so, X7R capacitors behave as low-impedance inductors. To extend the operating frequency range to a few
hundred MHz, an array of different capacitor values like 100 pF, 1 nF, 0.03 μF, and 0.1 μF are commonly used in
parallel. The most effective bypass capacitor can be built using sandwiched layers of power and ground at a
separation of 2 to 3 mils. With a 2-mil FR4 dielectric, there is approximately 500 pF per square inch of PCB.
Refer back to 图 13 for some examples. Many high-speed devices provide a low-inductance GND connection on
the backside of the package. This center dap must be connected to a ground plane through an array of vias. The
via array reduces the effective inductance to ground and enhances the thermal performance of the small Surface
Mount Technology (SMT) package. Placing vias around the perimeter of the dap connection ensures proper heat
spreading and the lowest possible die temperature. Placing high-performance devices on opposing sides of the
PCB using two GND planes (as shown in 图 13) creates multiple paths for heat transfer. Often thermal PCB
issues are the result of one device adding heat to another, resulting in a very high local temperature. Multiple
paths for heat transfer minimize this possibility. In many cases, the GND dap that is so important for heat
dissipation makes the optimal decoupling layout impossible to achieve due to insufficient pad-to-dap spacing as
shown in 图 21(b). When this occurs, placing the decoupling capacitor on the backside of the board keeps the
extra inductance to a minimum. It is important to place the VDD via as close to the device pin as possible while
still allowing for sufficient solder mask coverage. If the via is left open, solder may flow from the pad and into the
via barrel. This will result in a poor solder connection.
V
DD
INœ
0402
(a)
IN+
0402
(b)
图 21. Typical Decoupling Capacitor Layouts
At least two or three times the width of an individual trace should separate single-ended traces and differential
pairs to minimize the potential for crosstalk. Single-ended traces that run in parallel for less than the wavelength
of the rise or fall times usually have negligible crosstalk. Increase the spacing between signal paths for long
parallel runs to reduce crosstalk. Boards with limited real estate can benefit from the staggered trace layout, as
shown in 图 22.
Layer 1
Layer 6
图 22. Staggered Trace Layout
This configuration lays out alternating signal traces on different layers. Thus, the horizontal separation between
traces can be less than 2 or 3 times the width of individual traces. To ensure continuity in the ground signal path,
TI recommends that the designer have an adjacent ground via for every signal via, as shown in 图 23. Note that
vias create additional capacitance. For example, a typical via has a lumped capacitance effect of 1/2 pF to 1 pF
in FR4.
版权 © 2018, Texas Instruments Incorporated
17
DSLVDS1001
ZHCSIL1A –JULY 2018–REVISED DECEMBER 2018
www.ti.com.cn
Layout Guidelines (接下页)
Signal Via
Signal Trace
Uninterrupted Ground Plane
Signal Trace
Uninterrupted Ground Plane
Ground Via
图 23. Ground Via Location (Side View)
Short and low-impedance connection of the device ground pins to the PCB ground plane reduces ground
bounce. Holes and cutouts in the ground planes can adversely affect current return paths if they create
discontinuities that increase returning current loop areas.
To minimize EMI problems, TI recommends avoiding discontinuities below a trace (for example, holes, slits, and
so on) and keeping traces as short as possible. Zoning the board wisely by placing all similar functions in the
same area, as opposed to mixing them together, helps reduce susceptibility issues.
11.2 Layout Example
图 24. Layout Example
18
版权 © 2018, Texas Instruments Incorporated
DSLVDS1001
www.ti.com.cn
ZHCSIL1A –JULY 2018–REVISED DECEMBER 2018
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
请参阅如下相关文档：
•
•
•
《LVDS 接口的 AN-1194 失效防护偏置》(SNLA051)
《LVDS 用户手册设计指南（第 4 版）》(SNLA187)
《LVDS 应用和数据手册》(SLLD009)
12.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.4 商标
E2E is a trademark of Texas Instruments.
Rogers is a trademark of Rogers Corporation.
All other trademarks are the property of their respective owners.
12.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.6 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2018, Texas Instruments Incorporated
19
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
1000
250
(1)
(2)
(3)
(4/5)
(6)
DSLVDS1001DBVR
DSLVDS1001DBVT
ACTIVE
SOT-23
SOT-23
DBV
5
5
Non-RoHS
& Green
Call TI
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
1TBX
1TBX
ACTIVE
DBV
Non-RoHS
& Green
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DSLVDS1001DBVR
DSLVDS1001DBVT
SOT-23
SOT-23
DBV
DBV
5
5
1000
250
178.0
178.0
8.4
8.4
3.2
3.2
3.2
3.2
1.4
1.4
4.0
4.0
8.0
8.0
Q3
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DSLVDS1001DBVR
DSLVDS1001DBVT
SOT-23
SOT-23
DBV
DBV
5
5
1000
250
210.0
210.0
185.0
185.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
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这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
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Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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