DSLVDS1047PWR [TI]
3.3V LVDS 四通道高速差动线路驱动器 | PW | 16 | -40 to 85;
| 型号： | DSLVDS1047PWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3V LVDS 四通道高速差动线路驱动器 | PW | 16 | -40 to 85 驱动 驱动器 |
| 文件： | 总29页 (文件大小：1078K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DSLVDS1047
ZHCSIV3 –SEPTEMBER 2018
DSLVDS1047 3.3V LVDS 四通道高速差动线路驱动器
1 特性
3 说明
1
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•
•
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•
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旨在用于信号传输速率高达 400Mbps 的应用
DSLVDS1047 器件是一款四路 CMOS 直通差动线路
驱动器，专为需要超低功耗和高数据速率的 应用 而设
计。该器件旨在使用低电压差动信号 (LVDS) 技术支持
超过 400Mbps (200MHz) 的数据速率。
3.3V 电源设计
300ps 典型差动偏斜
400ps 最大差动偏斜
1.7ns 最大传播延迟
DSLVDS1047 接受低电压 TTL/CMOS 输入电平，并
将其转换为低电压 (350mV) 差动输出信号。
此外，该驱动器支持可用于禁用输出级的 TRI-STAT
功能，可禁用负载电流，从而将器件降至功率为
13mW（典型值）的超低空闲功耗状态。
DSLVDS1047 采用了直通引脚排列，可简化 PCB 布
局。
±350mV 差动信号传输
低功耗（3.3V 静态条件下为 13mW）
能够与现有 5V LVDS 接收器交互操作
在断电模式下，LVDS 输出端具有高阻抗
直通引脚排列可简化 PCB 布局
符合或超出 TIA/EIA-644 LVDS 标准
工业工作温度范围
EN 和 EN* 输入将接受 AND 运算并控制 TRI-STATE
输出。这些使能端由四个驱动器共用。 和配套的线路
接收器 (DSLVDS1048) 为高速点对点接口应用提供了
大功率伪 ECL 器件的替代 产品。
（−40°C 至 +85°C）
•
可采用 TSSOP 封装
2 应用
•
•
•
•
•
•
•
多功能打印机
器件信息(1)
板对板通信
测试和测量
打印机
器件型号
封装
封装尺寸（标称值）
DSLVDS1047
TSSOP (16)
5.00mm × 4.40mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
数据中心互连
实验室仪表
超声波扫描仪
图 1. 703A I2C
DSLVDS1047
DSLVDS1048
Receiver
RIN1+
RIN1-
DOUT1+
DOUT1-
DIN1
DIN2
DIN3
Driver
ROUT1
DOUT2+
DOUT2-
RIN2+
RIN2-
Driver
Receiver
ROUT2
DOUT3+
DOUT3-
RIN3+
RIN3-
Driver
Receiver
ROUT3
DOUT4+
DOUT4-
RIN4+
RIN4-
DIN4
ROUT4
Driver
Receiver
EN
EN
EN*
EN*
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNLS623
DSLVDS1047
ZHCSIV3 –SEPTEMBER 2018
www.ti.com.cn
目录
8.3 Feature Description................................................. 13
8.4 Device Functional Modes........................................ 14
Application and Implementation ........................ 15
9.1 Application Information............................................ 15
9.2 Typical Application ................................................. 15
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics .......................................... 5
6.6 Switching Characteristics ......................................... 6
6.7 Typical Characteristics.............................................. 7
Parameter Measurement Information .................. 9
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 13
9
10 Power Supply Recommendations ..................... 18
11 Layout................................................................... 18
11.1 Layout Guidelines ................................................. 18
11.2 Layout Example .................................................... 19
12 器件和文档支持 ..................................................... 20
12.1 接收文档更新通知 ................................................. 20
12.2 社区资源................................................................ 20
12.3 商标....................................................................... 20
12.4 静电放电警告......................................................... 20
12.5 术语表 ................................................................... 20
13 机械、封装和可订购信息....................................... 21
7
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
日期
修订版本
说明
2018 年 9 月
*
最初发布版本。
2
Copyright © 2018, Texas Instruments Incorporated
DSLVDS1047
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ZHCSIV3 –SEPTEMBER 2018
5 Pin Configuration and Functions
PW Package
16-Pin TSSOP
Top View
EN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
D
OUT1Þ
D
OUT1+
D
OUT2+
D
OUT2Þ
D
OUT3Þ
D
OUT3+
D
OUT4+
D
OUT4Þ
D
IN1
IN2
D
VCC
GND
D
D
IN3
IN4
EN*
Not to scale
Pin Functions
PIN
NAME
I/O
DESCRIPTION
NO.
2
DIN1
3
DIN2
I
Driver input pin, TTL/CMOS compatible
Non-inverting driver output pin, LVDS levels
Inverting driver output pin, LVDS levels
6
DIN3
7
DIN4
10
11
14
15
9
DOUT4+
DOUT3+
DOUT2+
DOUT1+
DOUT4−
DOUT3−
DOUT2−
DOUT1−
O
O
12
13
16
Driver enable pin: When EN is low, the driver is disabled. When EN is high and EN* is low
or open, the driver is enabled. If both EN and EN* are open circuit, then the driver is
disabled.
1
8
EN
I
I
Driver enable pin: When EN* is high, the driver is disabled. When EN* is low or open and
EN is high, the driver is enabled. If both EN and EN* are open circuit, then the driver is
disabled.
EN*
5
4
GND
VCC
—
—
Ground pin
Power supply pin, +3.3 V ± 0.3 V
Copyright © 2018, Texas Instruments Incorporated
3
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ZHCSIV3 –SEPTEMBER 2018
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6 Specifications
6.1 Absolute Maximum Ratings
(1)
See
MIN
−0.3
−0.3
−0.3
−0.3
MAX
4
UNIT
Supply voltage (VCC
Input voltage (DIN
Enable input voltage (EN, EN*)
Output voltage (DOUT+, DOUT–
)
V
V
V
V
)
VCC + 0.3
VCC + 0.3
3.9
)
Short-circuit duration
(DOUT+, DOUT–
)
Continuous
PW0016A package
Derate PW0016A package
Soldering (4 s)
866
6.9
mW
mW/°C
°C
Maximum package power
dissipation at +25°C
above +25°C
Lead temperature
260
150
150
Maximum junction temperature
Storage temperature, Tstg
°C
−65
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(2)
±1200
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(3)
V(ESD)
Electrostatic discharge(1)
±200
Machine Model
±1200
(1) ESD Ratings:
HBM (1.5 kΩ, 100 pF)
EIAJ (0 Ω, 200 pF)
(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
3
NOM
3.3
MAX
3.6
UNIT
V
Supply voltage, VCC
Operating free air temperature, TA
−40
25
85
°C
6.4 Thermal Information
DSLVDS1047
THERMAL METRIC(1)
PW (TSSOP)
UNIT
16 PINS
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
114
51
59
8
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
ψJB
58
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
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ZHCSIV3 –SEPTEMBER 2018
6.5 Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified(1)(2)(3)
PARAMETER
TEST CONDITIONS
PIN
MIN
TYP
MAX
UNIT
VOD1
ΔVOD1
VOS
Differential output voltage
250
310
450
mV
Change in magnitude of VOD1 for
complementary output states
1
1.17
1
35
1.375
25
|mV|
V
Offset voltage
1.125
DOUT−
DOUT+
RL = 100 Ω (Figure 18)
Change in magnitude of VOS for
complementary output states
ΔVOS
|mV|
VOH
VOL
VIH
VIL
IIH
Output high voltage
Output low voltage
Input high voltage
Input low voltage
Input high current
Input low current
Input clamp voltage
1.33
1.02
1.6
V
V
0.9
2
VCC
0.8
15
V
GND
V
DIN
EN,
EN*
,
VIN = VCC or 2.5 V
VIN = GND or 0.4 V
ICL = −18 mA
2
2
µA
µA
V
IIL
15
VCL
−1.5
−0.8
ENABLED,
DIN = VCC, DOUT+ = 0 V or
DIN = GND, DOUT− = 0 V
IOS
Output short-circuit current(4)
−4
−8
mA
Differential output short-circuit
current(4)
IOSD
IOFF
ENABLED, VOD = 0 V
−4.2
−9
mA
µA
DOUT−
DOUT+
VOUT = 0 V or 3.6 V, VCC = 0 V or
Open
Power-off leakage
−20
−10
±1
20
EN = 0.8 V and EN* = 2.0 V
VOUT = 0 V or VCC
IOZ
Output TRI-STATE current
±1
4
10
8
µA
mA
mA
ICC
ICCL
No load supply current drivers enabled DIN = VCC or GND
RL = 100 Ω all channels, DIN = VCC
or GND (all inputs)
Loaded supply current drivers enabled
20
30
VCC
DIN = VCC or GND, EN = GND,
EN* = VCC
No load supply current drivers
disabled
ICCZ
2.2
6
mA
(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except: VOD1 and ΔVOD1
.
(2) All typicals are given for: VCC = 3.3 V, TA = +25°C.
(3) The DSLVDS1047 is a current mode device and only functions within datasheet specifications when a resistive load is applied to the
driver outputs typical range is (90 Ω to 110 Ω).
(4) Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
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6.6 Switching Characteristics
VCC = +3.3V ± 10%, TA = −40°C to +85°C(1)(2)(3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Differential propagation delay high to
low
tPHLD
tPLHD
0.5
0.9
1.7
1.7
ns
Differential propagation delay low to
high
0.5
1.2
ns
(4)
tSKD1
tSKD2
tSKD3
tSKD4
tTLH
Differential pulse skew |tPHLD − tPLHD
Channel-to-channel skew(5)
Differential part-to-part skew(6)
Differential part-to-part skew(7)
Rise time
|
0.3
0.4
0.4
0.5
1
ns
ns
RL = 100 Ω, CL = 15 pF
(Figure 19 and Figure 20)
0
0
ns
1.2
1.5
1.5
5
ns
0.5
0.5
2
ns
tTHL
Fall time
ns
tPHZ
tPLZ
tPZH
tPZL
Disable time high to Z
Disable time low to Z
ns
2
5
ns
RL = 100 Ω, CL = 15 pF
(Figure 21 and Figure 22)
Enable time Z to high
3
7
ns
Enable time Z to low
3
7
ns
fMAX
Maximum operating frequency(8)
200
250
MHz
(1) All typicals are given for: VCC = 3.3 V, TA = +25°C.
(2) Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50 Ω, tr ≤ 1 ns, and tf ≤ 1 ns.
(3) CL includes probe and jig capacitance.
(4) tSKD1 |tPHLD – tPLHD| is the magnitude difference in differential propagation delay time between the positive going edge and the negative
going edge of the same channel.
(5) tSKD2 is the differential channel-to-channel skew of any event on the same device.
(6) tSKD3, differential part-to-part skew, is defined as the difference between the minimum and maximum specified differential propagation
delays. This specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
(7) tSKD4, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices
over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min|
differential propagation delay.
(8) fMAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% / 55%,
VOD > 250 mV, all channels switching.
6
Copyright © 2018, Texas Instruments Incorporated
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ZHCSIV3 –SEPTEMBER 2018
6.7 Typical Characteristics
Figure 2. Output High Voltage vs Power Supply Voltage
Figure 3. Output Low Voltage vs Power Supply Voltage
Figure 5. Output TRI-STATE Current vs
Power Supply Voltage
Figure 4. Output Short Circuit Current vs
Power Supply Voltage
Figure 6. Differential Output Voltage vs
Power Supply Voltage
Figure 7. Differential Output Voltage vs Load Resistor
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Typical Characteristics (continued)
Figure 8. Offset Voltage vs Power Supply Voltage
Figure 9. Power Supply Current vs Power Supply Voltage
Figure 11. Differential Propagation Delay vs
Power Supply Voltage
Figure 10. Power Supply Current vs Ambient Temperature
Figure 13. Differential Skew vs Power Supply Voltage
Figure 12. Differential Propagation Delay vs
Ambient Temperature
8
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ZHCSIV3 –SEPTEMBER 2018
Typical Characteristics (continued)
Figure 14. Differential Skew vs Ambient Temperature
Figure 15. Transition Time vs Power Supply Voltage
Figure 16. Transition Time vs Ambient Temperature
Figure 17. Data Rate vs Cable Length
7 Parameter Measurement Information
Figure 18. Driver VOD and VOS Test Circuit
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Parameter Measurement Information (continued)
Figure 19. Driver Propagation Delay and Transition Time Test Circuit
Figure 20. Driver Propagation Delay and Transition Time Waveforms
Figure 21. Driver TRI-STATE Delay Test Circuit
10
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ZHCSIV3 –SEPTEMBER 2018
Parameter Measurement Information (continued)
Figure 22. Driver TRI-STATE Delay Waveform
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8 Detailed Description
8.1 Overview
LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as
is shown in Figure 24. This configuration provides a clean signaling environment for the fast edge rates of the
drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair
cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic differential impedance of the media
is in the range of 100 Ω. A termination resistor of 100 Ω (selected to match the media), and is located as close to
the receiver input pins as possible. The termination resistor converts the driver output current (current mode) into
a voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver
configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as
well as ground shifting, noise margin limits, and total termination loading must be taken into account.
The DSLVDS1047 differential line driver is a balanced current source design. A current mode driver, generally
speaking has a high output impedance and supplies a constant current for a range of loads (a voltage mode
driver on the other hand supplies a constant voltage for a range of loads). Current is switched through the load in
one direction to produce a logic state and in the other direction to produce the other logic state. The output
current is typically 3.1 mA, a minimum of 2.5 mA, and a maximum of 4.5 mA. The current mode driver requires
that a resistive termination be employed to terminate the signal and to complete the loop as shown in Figure 24.
AC or unterminated configurations are not allowed. The 3.1-mA loop current develops a differential voltage of
310 mV across the 100-Ω termination resistor which the receiver detects with a 250-mV minimum differential
noise margin, (driven signal minus receiver threshold (250 mV – 100 mV = 150 mV). The signal is centered
around +1.2 V (Driver Offset, VOS) with respect to ground as shown in Figure 23.
NOTE
The steady-state voltage (VSS) peak-to-peak swing is twice the differential voltage (VOD
)
and is typically 620 mV.
The current mode driver provides substantial benefits over voltage mode drivers, such as an RS-422 driver. Its
quiescent current remains relatively flat versus switching frequency. Whereas the RS-422 voltage mode driver
increases exponentially in most case from 20 MHz to 50 MHz. This is due to the overlap current that flows
between the rails of the device when the internal gates switch. Whereas the current mode driver switches a fixed
current between its output without any substantial overlap current. This is similar to some ECL and PECL
devices, but without the heavy static ICC requirements of the ECL/PECL designs. LVDS requires > 80% less
current than similar PECL devices. AC specifications for the driver are a tenfold improvement over other existing
RS-422 drivers.
The TRI-STATE function allows the driver outputs to be disabled, thus obtaining an even lower power state when
the transmission of data is not required.
12
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ZHCSIV3 –SEPTEMBER 2018
8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 LVDS Fail-Safe
This section addresses the common concern of fail-safe biasing of LVDS interconnects, specifically looking at the
DSLVDS1047 driver outputs and the DSLVDS1048 receiver inputs.
The LVDS receiver is a high-gain, high-speed device that amplifies a small differential signal (20 mV) to CMOS
logic levels. Due to the high gain and tight threshold of the receiver, take care to prevent noise from appearing as
a valid signal.
The internal fail-safe circuitry of the receiver is designed to source or sink a small amount of current, providing
fail-safe protection (a stable known state of HIGH output voltage) for floating, terminated, or shorted receiver
inputs.
1. Open Input Pins. The DSLVDS1048 is a quad receiver device, and if an application requires only 1, 2, or 3
receivers, the unused channel(s) inputs must be left OPEN. Do not tie unused receiver inputs to ground or
any other voltages. The input is biased by internal high value pullup and pulldown resistors to set the output
to a HIGH state. This internal circuitry ensures a HIGH, stable output state for open inputs.
2. Terminated Input. If the DSLVDS1047 driver is disconnected (cable unplugged), or if the DSLVDS1047
driver is in a TRI-STATE or power-off condition, the receiver output is again in a HIGH state, even with the
end of cable 100-Ω termination resistor across the input pins. The unplugged cable can become a floating
antenna which can pick up noise. If the cable picks up more than 10 mV of differential noise, the receiver
may see the noise as a valid signal and switch. To insure that any noise is seen as common-mode and not
differential, a balanced interconnect must be used. Twisted pair cable offers better balance than flat ribbon
cable.
3. Shorted Inputs. If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0-V
differential input voltage, the receiver output remains in a HIGH state. Shorted input fail-safe is not supported
across the common-mode range of the device (GND to 2.4 V). It is only supported with inputs shorted and no
external common-mode voltage applied.
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Feature Description (continued)
External lower value pullup and pulldown resistors (for a stronger bias) may be used to boost fail-safe in the
presence of higher noise levels. The pullup and pulldown resistors should be in the 5-kΩ to 15-kΩ range to
minimize loading and waveform distortion to the driver. The common-mode bias point should be set to
approximately 1.2 V (less than 1.75 V) to be compatible with the internal circuitry.
Figure 23. Driver Output Levels
8.4 Device Functional Modes
Table 1 lists the functional modes DSLVDS1047.
Table 1. Truth Table
ENABLES
INPUT
OUTPUTS
EN
EN*
DIN
L
DOUT+
DOUT−
L
H
Z
H
L
H
L or Open
H
All other combinations of ENABLE inputs
X
Z
14
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ZHCSIV3 –SEPTEMBER 2018
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The DSLVDS1047 has a flow-through pinout that allows for easy PCB layout. The LVDS signals on one side of
the device easily allows for matching electrical lengths of the differential pair trace lines between the driver and
the receiver as well as allowing the trace lines to be close together to couple noise as common-mode. Noise
isolation is achieved with the LVDS signals on one side of the device and the TTL signals on the other side.
9.2 Typical Application
DSLVDS1047
DSLVDS1048
RIN1+
RIN1-
DOUT1+
DOUT1-
DIN1
DIN2
DIN3
Driver
Driver
Driver
Receiver
Receiver
Receiver
ROUT1
DOUT2+
DOUT2-
RIN2+
RIN2-
ROUT2
DOUT3+
DOUT3-
RIN3+
RIN3-
ROUT3
DOUT4+
DOUT4-
RIN4+
RIN4-
DIN4
ROUT4
Driver
Receiver
EN
EN
EN*
EN*
Figure 24. Point-to-Point Application
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Typical Application (continued)
9.2.1 Design Requirements
When using LVDS devices, it is important to remember to specify controlled impedance PCB traces, cable
assemblies, and connectors. All components of the transmission media should have a matched differential
impedance of about 100 Ω. They should not introduce major impedance discontinuities.
Balanced cables (for example, twisted pair) are usually better than unbalanced cables (ribbon cable) for noise
reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects and also
tend to pick up electromagnetic radiation as common-mode (not differential mode) noise which is rejected by the
LVDS receiver.
For cable distances < 0.5 M, most cables can be made to work effectively. For distances 0.5 M ≤ d ≤ 10 M,
CAT5 (Category 5) twisted pair cable works well, is readily available and relatively inexpensive.
Table 2. Design Requirements
DESIGN PARAMETERS
Driver Supply Voltage (VCC
Driver Input Voltage
EXAMPLE VALUE
3.0 to 3.6 V
0 to 3.6 V
DC to 400 Mbps
100 Ω
)
Driver Signaling Rate
Interconnect Characteristic Impedance
Termination Resistance
100 Ω
Number of Receiver Nodes
1
Ground shift between driver and receiver
±1 V
9.2.2 Detailed Design Procedure
9.2.2.1 Probing LVDS Transmission Lines
Always use high impedance (> 100 kΩ), low capacitance (< 2 pF) scope probes with a wide bandwidth (1 GHz)
scope. Improper probing gives deceiving results.
9.2.2.2 Data Rate vs Cable Length Graph Test Procedure
A pseudo-random bit sequence (PRBS) of 29−1 bits was programmed into a function generator (Tektronix
HFS9009) and connected to the driver inputs through 50-Ω cables and SMB connectors. An oscilloscope
(Tektronix 11801B) was used to probe the resulting eye pattern, measured differentially at the input to the
receiver. A 100-Ω resistor was used to terminate the pair at the far end of the cable. The measurements were
taken at the far end of the cable, at the input of the receiver, and used for the jitter analysis for this graph
(Figure 17). The frequency of the input signal was increased until the measured jitter (ttcs) equaled 20% with
respect to the unit interval (ttui) for the particular cable length under test. Twenty percent jitter is a reasonable
place to start with many system designs. The data used was NRZ. Jitter was measured at the 0-V differential
voltage of the differential eye pattern. The DSLVDS1047 and DSLVDS1048 can be evaluated using the new
DS90LV047-048AEVM.
Figure 25 shows very good typical performance that can be used as a design guideline for data rate vs cable
length. Increasing the jitter percentage increases the curve respectively, allowing the device to transmit faster
over longer cable lengths. This relaxes the jitter tolerance of the system allowing more jitter into the system,
which could reduce the reliability and efficiency of the system. Alternatively, decreasing the jitter percentage has
the opposite effect on the system. The area under the curve is considered the safe operating area based on the
above signal quality criteria. For more information on eye pattern testing, please see AN-808 Long Transmission
Lines and Data Signal Quality (SNLA028).
16
Copyright © 2018, Texas Instruments Incorporated
DSLVDS1047
www.ti.com.cn
ZHCSIV3 –SEPTEMBER 2018
9.2.3 Application Curve
Figure 25. Power Supply Current vs Frequency
Copyright © 2018, Texas Instruments Incorporated
17
DSLVDS1047
ZHCSIV3 –SEPTEMBER 2018
www.ti.com.cn
10 Power Supply Recommendations
Although the DSLVDS1047 draws very little power while at rest. At higher switching frequencies there is a
dynamic current component which increases the overall power consumption. The DSLVDS1047 power supply
connection must take this additional current consumption into consideration for maximum power requirements.
11 Layout
11.1 Layout Guidelines
•
•
Use at least 4 PCB layers (top to bottom); LVDS signals, ground, power, TTL signals.
Isolate TTL signals from LVDS signals, otherwise the TTL may couple onto the LVDS lines. It is best to put
TTL and LVDS signals on different layers which are isolated by a power/ground plane(s).
•
Keep drivers and receivers as close to the (LVDS port side) connectors as possible.
11.1.1 Power Decoupling Recommendations
Bypass capacitors must be used on power pins. Use high frequency ceramic (surface mount is recommended)
0.1-µF and 0.001-µF capacitors in parallel at the power supply pin with the smallest value capacitor closest to the
device supply pin. Additional scattered capacitors over the printed-circuit board improves decoupling. Multiple
vias must be used to connect the decoupling capacitors to the power planes. A 10-µF (35-V) or greater solid
tantalum capacitor must be connected at the power entry point on the printed-circuit board between the supply
and ground.
11.1.2 Differential Traces
Use controlled impedance traces which match the differential impedance of your transmission medium (that is,
cable) and termination resistor. Run the differential pair trace lines as close together as possible as soon as they
leave the IC (stubs must be < 10 mm long). This helps eliminate reflections and ensure noise is coupled as
common-mode. In fact, we have seen that differential signals which are 1 mm apart radiate far less noise than
traces 3 mm apart since magnetic field cancellation is much better with the closer traces. In addition, noise
induced on the differential lines is much more likely to appear as common-mode which is rejected by the
receiver.
Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase
difference between signals, which destroys the magnetic field cancellation benefits of differential signals and
EMI, results.
NOTE
The velocity of propagation, v = c/Er where c (the speed of light) = 0.2997mm/ps or
0.0118 in/ps
Do not rely solely on the autoroute function for differential traces. Carefully review dimensions to match
differential impedance and provide isolation for the differential lines. Minimize the number or vias and other
discontinuities on the line.
Avoid 90° turns (these cause impedance discontinuities). Use arcs or 45° bevels.
Within a pair of traces, the distance between the two traces must be minimized to maintain common-mode
rejection of the receivers. On the printed-circuit board, this distance must remain constant to avoid discontinuities
in differential impedance. Minor violations at connection points are allowable.
11.1.3 Termination
Use a termination resistor which best matches the differential impedance or your transmission line. The resistor
must be between 90 Ω and 130 Ω. Remember that the current mode outputs need the termination resistor to
generate the differential voltage. LVDS does not work without resistor termination. Typically, connecting a single
resistor across the pair at the receiver end will suffice.
18
Copyright © 2018, Texas Instruments Incorporated
DSLVDS1047
www.ti.com.cn
ZHCSIV3 –SEPTEMBER 2018
Layout Guidelines (continued)
Surface mount 1% to 2% resistors are best. PCB stubs, component lead, and the distance from the termination
to the receiver inputs must be minimized. The distance between the termination resistor and the receiver should
be < 10 mm (12 mm maximum).
11.2 Layout Example
DS90LV048A
DS90LV047A
1
2
3
16
15
14
13
12
11
10
9
1
2
3
16
15
14
13
12
11
10
9
DOUT1-
DOUT1+
DOUT2+
DOUT2-
DOUT3-
DOUT3+
RIN1-
RIN1+
RIN2+
RIN2-
RIN3-
RIN3+
EN
EN
DIN1
DIN2
Series Termination (optional)
ROUT1
ROUT2
LVCMOS
Inputs
LVCMOS
Outputs
Decoupling Cap
4
5
4
5
VCC
GND
VCC
GND
Decoupling Cap
6
7
6
7
ROUT3
ROUT4
EN*
DIN3
DIN4
EN*
DOUT4+
DOUT4-
RIN4+
RIN4-
Series Termination (optional)
8
8
Input Termination
(Required)
Figure 26. Layout Recommendation
版权 © 2018, Texas Instruments Incorporated
19
DSLVDS1047
ZHCSIV3 –SEPTEMBER 2018
www.ti.com.cn
12 器件和文档支持
12.1 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.2 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.5 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
20
版权 © 2018, Texas Instruments Incorporated
DSLVDS1047
www.ti.com.cn
ZHCSIV3 –SEPTEMBER 2018
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2018, Texas Instruments Incorporated
21
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DSLVDS1047PWR
DSLVDS1047PWT
ACTIVE
TSSOP
TSSOP
PW
16
16
2500 RoHS & Green
250 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
DSLVDS
1047
ACTIVE
PW
SN
DSLVDS
1047
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DSLVDS1047PWR
DSLVDS1047PWT
TSSOP
TSSOP
PW
PW
16
16
2500
250
330.0
178.0
12.4
12.4
6.95
6.95
5.6
5.6
1.6
1.6
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DSLVDS1047PWR
DSLVDS1047PWT
TSSOP
TSSOP
PW
PW
16
16
2500
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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