ESD1LIN24-Q1 [TI]
适用于 LIN 接口且采用 SOD-323 封装的汽车类 3pF、±24V、±30kV ESD 保护二极管;
| 型号： | ESD1LIN24-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于 LIN 接口且采用 SOD-323 封装的汽车类 3pF、±24V、±30kV ESD 保护二极管 二极管 |
| 文件： | 总30页 (文件大小：1856K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ESD1LIN24-Q1, ESD751-Q1, ESD761-Q1
ZHCSR11C –SEPTEMBER 2022 –REVISED DECEMBER 2022
ESD1LIN24-Q1、ESD751-Q1 和ESD761-Q1 用于车载网络的汽车类24V 单通道
ESD 保护二极管
1 特性
3 说明
• IEC 61000-4-2 4 级ESD 保护：
ESD1LIN24-Q1、ESD751-Q1 和 ESD761-Q1 是适用
于本地互连网络 (LIN) 的单通道低电容双向 ESD 保护
器件。这些器件旨在耗散超过 IEC 61000-4-2 国际标
准所规定最高水平（分别为 ±30kV 接触放电、±30kV
气隙放电，±22kV 接触放电、±22kV 气隙放电以及
±15kV 接触放电、±15kV 气隙放电）的接触 ESD 冲
击。低动态电阻和低钳位电压有助于保护系统免受瞬态
事件的影响。这种保护很关键，因为汽车系统在控制安
全设备时需要高度的稳健性和可靠性。
– ±30kV、±22kV 或±15kV 接触放电
– ±30kV、±22kV 或±15kV 气隙放电
• ISO 10605（330pF，330Ω）ESD 保护：
– ±30kV、±22kV 或±15kV 接触放电
– ±30kV、±22kV 或±15kV 气隙放电
• 24V 工作电压
• 双向ESD 保护
• 低钳位电压可保护下游元件
• 符合AEC-Q101 标准
ESD1LIN24-Q1 和 ESD751-Q1 均采用引线式封装，
可轻松实现直通式布线。
• 温度范围：–55°C 至+150°C
• I/O 电容= 2.3pF、1.6pF 或1.1pF（典型值）
• 采用业界通用封装：SOD-323 (DYF)、SOD-523
(DYA) 和0402 尺寸无引线封装(DPY)
• 引线式封装，用于自动光学检测(AOI)
封装信息(1)
器件型号
封装
封装尺寸（标称值）
ESD1LIN24-Q1
ESD751-Q1
ESD761-Q1
DYF（SOD-323，2） 2.50mm × 1.20mm
DYA（SOD-523，2） 1.60mm × 0.80mm
2 应用
DPY（X1SON，2）
1.00mm × 0.60mm
• 汽车车载网络：
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
– 本地互连网络(LIN)
– 单线CAN ESD 保护
• 工业控制网络：
– DeviceNet
– 智能配电系统
A
(for exa
典型应用
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSGS4
ESD1LIN24-Q1, ESD751-Q1, ESD761-Q1
ZHCSR11C –SEPTEMBER 2022 –REVISED DECEMBER 2022
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Table of Contents
7.3 Feature Description...................................................10
7.4 Device Functional Modes..........................................11
8 Application and Implementation..................................12
8.1 Application Information............................................. 12
8.2 Typical Application.................................................... 12
9 Power Supply Recommendations................................13
10 Layout...........................................................................13
10.1 Layout Guidelines................................................... 13
10.2 Layout Example...................................................... 14
11 Device and Documentation Support..........................15
11.1 Documentation Support.......................................... 15
11.2 接收文档更新通知................................................... 15
11.3 支持资源..................................................................15
11.4 Trademarks............................................................. 15
11.5 Electrostatic Discharge Caution..............................15
11.6 术语表..................................................................... 15
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings—AEC Specification...............................4
6.3 ESD Ratings—IEC Specification................................ 4
6.4 ESD Ratings - ISO Specification.................................5
6.5 Recommended Operating Conditions.........................5
6.6 Thermal Information....................................................5
6.7 Electrical Characteristics.............................................5
6.8 Typical Characteristics –ESD751.............................7
6.9 Typical Characteristics –ESD1LIN24....................... 8
6.10 Typical Characteristics - ESD761............................. 9
7 Detailed Description......................................................10
7.1 Overview...................................................................10
7.2 Functional Block Diagram.........................................10
Information.................................................................... 15
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision B (November 2022) to Revision C (December 2022)
Page
• 将ESD1LIN24-Q1 和ESD761-Q1 器件的状态从预告信息更改为“量产数据”..............................................1
Changes from Revision A (September 2022) to Revision B (November 2022)
Page
• 将ESD751-Q1 器件的状态从预告信息更改为量产数据....................................................................................1
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5 Pin Configuration and Functions
1
2
图5-1. DPY Package, 2-Pin X1SON (Top View)
ID Area
1
2
图5-2. DYF Package, 2-Pin SOD-323 (Top View)
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
IO
1
I/O
G
ESD protected IO
Connect to ground.
GND
2
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
DEVICE
MIN
MAX
UNIT
ESD1LIN24-Q1
ESD751-Q1
ESD761-Q1
ESD1LIN24-Q1
ESD751-Q1
ESD761-Q1
159
102
65
PPP
IEC 61000-4-5 Power (tp - 8/20 µs) at 25°C
IEC 61000-4-5 current (tp - 8/20 µs) at 25°C
W
4.3
2.8
1.8
150
150
155
IPP
A
TA
Operating free-air temperature
Junction temperature
-55
-55
-65
TJ
°C
Tstg
Storage temperature
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings—AEC Specification
VALUE
UNIT
Human body model (HBM), per AEC Q101-001(1)
± 2500
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per AEC
Q101-005
± 1000
(1) AEC Q100-002 indicates that HBM stressing must be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 ESD Ratings—IEC Specification
DEVICE
ESD1LIN24-Q1
ESD751-Q1
VALUE
UNIT
±30000
±22000
±15000
±30000
±22000
±15000
IEC 61000-4-2 Contact Discharge, all pins
IEC 61000-4-2 Air-gap Discharge, all pins
ESD761-Q1
V(ESD)
Electrostatic discharge
V
ESD1LIN24-Q1
ESD751-Q1
ESD761-Q1
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6.4 ESD Ratings - ISO Specification
DEVICE
ESD1LIN24-Q1
ESD751-Q1
ESD761-Q1
ESD1LIN24-Q1
ESD751-Q1
ESD761-Q1
ESD1LIN24-Q1
ESD751-Q1
ESD761-Q1
ESD1LIN24-Q1
ESD751-Q1
ESD761-Q1
VALUE UNIT
± 30000
± 22000
ISO 10605, 150-pF, 330-Ω, IO
ISO 10605, 330-pF, 330-Ω, IO
ISO 10605, 150-pF, 330-Ω, IO
ISO 10605, 330-pF, 330-Ω, IO
± 15000
Contact discharge
± 30000
± 22000
± 15000
V
± 30000
V(ESD) Electrostatic discharge
± 22000
± 15000
± 30000
± 22000
± 15000
Air-gap discharge
6.5 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
-24
-55
NOM
MAX
24
UNIT
V
VIN
TA
Input voltage
Operating free-air temperature
150
°C
6.6 Thermal Information
ESD1LIN24-Q1
DYF (SOD-323)
2 PINS
705.4
ESD751-Q1
ESD761-Q1
THERMAL METRIC(1)
DYA (SOD-523)
2 PINS
746.3
DPY (X1SON)
2 PINS
282.3
150.6
98.3
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
315
301.2
RθJB
ΨJT
Junction-to-board thermal resistance
561.5
509.6
Junction-to-top characterization parameter
Junction-to-board characterization parameter
145
81.8
9.6
550.2
503.0
97.7
ΨJB
RθJC(bot) Junction-to-case (bottom) thermal resistance
N/A
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.7 Electrical Characteristics
over TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DEVICE
MIN
–24
TYP
MAX
24
UNIT
VRWM
VBRF
VBRR
Reverse stand-off voltage
Breakdown voltage(1)
Breakdown voltage(1)
V
V
V
IIO = 10 mA, IO to GND
25.5
35.5
IIO = –10 mA, IO to GND
–35.5
–25.5
IPP = 4.3 A, tp = 8/20 µs, IO to GND and
GND to IO
ESD1LIN24-Q1
ESD751-Q1
ESD761-Q1
37
36.5
36.3
IPP = 2.8 A, tp = 8/20 µs, IO to GND and
GND to IO
VCLAMP Clamping voltage(2)
V
IPP = 1.8 A, tp = 8/20 µs, IO to GND and
GND to IO
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6.7 Electrical Characteristics (continued)
over TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DEVICE
MIN
TYP
40
MAX
UNIT
ESD1LIN24-Q1
V
VCLAMP Clamping voltage(3)
IPP = 16 A, TLP, IO to GND and GND to IO ESD751-Q1
41.5
42.5
1
ESD761-Q1
V
ILEAK
Leakage current
VIO = ±24 V, IO to GND
ESD1LIN24-Q1
ESD751-Q1
-50
50
nA
0.5
0.6
0.53
2.3
1.6
1.1
RDYN
Dynamic resistance(3)
Ω
ESD761-Q1
ESD1LIN24-Q1
3.8
2.7
1.8
VIO = 0 V, f = 1 MHz, Vpp = 30 mV, IO to
CL
Line capacitance
ESD751-Q1
pF
GND
ESD761-Q1
(1) VBRF and VBRR are defined as the voltage when ±10 mA is applied in the positive-going direction, before the device latches into the
snapback state.
(2) Device stressed with 8/20 μs exponential decay waveform according to IEC 61000-4-5.
(3) Non-repetitive current pulse, Transmission Line Pulse (TLP); square pulse; ANSI / ESD STM5.5.1-2008
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6.8 Typical Characteristics –ESD751
32
30
28
26
24
22
20
18
16
14
12
10
8
32
30
28
26
24
22
20
18
16
14
12
10
8
6
6
4
4
2
2
0
0
0
5
10
15
20
25
30
35
40
45
0
5
10
15
20
25
30
35
40
45
Vclamp (V)
Vclamp (V)
图6-1. Positive TLP Curve
图6-2. Negative TLP Curve
图6-4. -8-kV Clamped IEC Waveform
图6-3. +8-kV Clamped IEC Waveform
2.17
2.165
2.16
12
11
10
9
2.155
2.15
8
2.145
2.14
7
2.135
2.13
6
5
2.125
2.12
4
3
2.115
2.11
2
1
2.105
2.1
0
0
2.5
5
7.5
10 12.5 15 17.5 20 22.5 25
VR (V)
-50 -30 -10
10
30
50
70
90 110 130 150
Temperature (ꢀC)
图6-5. Capacitance vs. Bias Voltage
图6-6. Leakage Current vs. Temperature
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6.9 Typical Characteristics –ESD1LIN24
图6-7. Positive TLP Curve
图6-8. Negative TLP Curve
图6-10. −8-kV Clamped IEC Waveform
图6-9. +8-kV Clamped IEC Waveform
图6-12. DC Voltage Sweep I-V Curve
图6-11. Capacitance vs. Bias Voltage
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6.10 Typical Characteristics - ESD761
图6-13. Positive TLP Curve
图6-14. Negative TLP Curve
图6-15. Capacitance vs. Bias Voltage
图6-16. DC Voltage Sweep I-V Curve
图6-17. Insertion Loss
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7 Detailed Description
7.1 Overview
The ESD1LIN24-Q1, ESD751-Q1, and ESD761-Q1 are single-channel ESD diodes available in industry
standard packages (SOD-323 and SOD-523) which are convenient for automatic optical inspection as well as a
smaller leadless package X1SON (DPY). These products offer ISO 10605 ESD ratings of (±30- kV Contact, ±30-
kV Airgap), (±22-kV Contact, ±22- kV Airgap), and (±15-kV Contact, ±15-kV Airgap), respectively. The 2.3 pF,
1.6 pF, and 1.1 pF line capacitance of these ESD protection diodes are suitable for LIN applications that support
data rates from 20 Kbps to 10 Mbps.
Typical application of these products is the ESD circuit protection for LIN transceivers used in automotive
applications. These devices are commonly used for ESD protection inside automotive electronic control units
(ECUs) for head lights, door modules, climate control, roof control, wipers, cluster, audio, and many other
automotive applications.
7.2 Functional Block Diagram
1
2
7.3 Feature Description
The ESD1LIN24-Q1, ESD751-Q1, and ESD761-Q1 are single-channel bidirectional ESD diodes with a high ESD
protection level. These devices have a small dynamic resistance, which makes the clamping voltage low when
the device is actively protecting other circuits. The breakdown is bidirectional so these protection devices can
prevent system damage if battery leads are swapped. Low leakage allows the diodes to conserve power when
working below the VRWM. The temperature range of −55°C to +150°C makes these ESD devices work at
extensive temperatures in most environments.
7.3.1 IEC 61000-4-5 Surge Protection
The I/O pins of the ESD1LIN24-Q1, ESD751-Q1, ESD761-Q1 have the following surge ratings (8/20 µs
waveform): 4.3A, 2.8 A, and 1.8 A, respectively. An ESD-surge clamp diverts this current to ground.
7.3.2 IO Capacitance
The capacitance between the I/O pins of the ESD1LIN24-Q1, ESD751-Q1, and ESD761-Q1 devices are as
follows: 2.3 pF, 1.6 pF, and 1.1 pF, respectively. The capacitance of these devices support data rates for LIN up
to 10 Mbps.
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7.3.3 Dynamic Resistance
The I/O pins feature an ESD clamp that have a low RDYN of 0.48 Ω for the ESD1LIN24-Q1, 0.6 Ω for the
ESD751-Q1, and 0.58 Ωfor the ESD761-Q1.
7.3.4 DC Breakdown Voltage
The DC breakdown voltage between the I/O pins is a minimum of ± 25.5 V. This shields sensitive equipment
from surges above the reverse standoff voltage of ± 24 V.
7.3.5 Ultra Low Leakage Current
The I/O pins feature an ultra-low leakage current of 50 nA (maximum) with a bias of ± 24 V.
7.3.6 Clamping Voltage
The I/O pins of the ESD1LIN24-Q1 feature an ESD clamp that is capable of clamping the voltage to 37 V ( IPP
=
4.3 A) and 37.7 V (IPP = 16 A for TLP). The I/O pins of the ESD751-Q1 feature an ESD clamp that is capable of
clamping the voltage to 36.5 V (IPP = 2.8 A) and 39.7 V (IPP = 16 A for TLP). The I/O pins of the ESD761-Q1
feature an ESD clamp that is capable of clamping the voltage to 36.3 V (IPP = 1.8 A) and 39.3 V (IPP = 16 A for
TLP).
7.3.7 Industry Standard Packages
The ESD1LIN24-Q1 and ESD751-Q1 feature industry standard SOD-323 (DYF) and SOD-523 (DYA) leaded
packages for automatic optical inspection (AOI). The ESD761-Q1 is offered in the leadless X1SON (DPY)
package
7.4 Device Functional Modes
The ESD1LIN24-Q1, ESD751-Q1, and ESD761-Q1 are single channel passive clamps that have low leakage
during normal operation when the voltage between I/O and GND is below VRWM, and activate when the voltage
between I/O and GND goes above VBR. During ISO 10605 ESD events, transient voltages from ±30 kV to ±15
kV can be clamped on either channel. When the voltages on the protected lines fall below the VHOLD, the device
reverts back to the low leakage passive state
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8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The ESD1LIN24-Q1, ESD751-Q1, and ESD761-Q1 are single channel TVS diodes which are used to provide a
path to ground for dissipating ESD events on LIN signal lines. The LIN signal lines are typically routed
throughout the automobile to connect between the different ECUs. As the current from ESD passes through the
TVS, only a small voltage drop is present across the diode. This is the voltage presented to the protected IC.
The low RDYN of the triggered TVS holds this voltage, VCLAMP, to a safe level for the protected IC.
8.2 Typical Application
A
(for exa
图8-1. Typical Application
8.2.1 Design Requirements
For this design example, the ESD1LIN24-Q1 is used to provide ESD protection to a LIN transceiver. The
parameters listed in 表8-1 are the known design parameters for this application.
表8-1. Design Parameters for Typical Applications
Design Parameter
Diode configuration
VIO signal range
Value
Bidirectional
Up to 18 V
±24 V
VRWM
Jumpstart short to battery event on VIO
Data rate
±24 V
Up to 10 Mbps
1 kΩ
Pullup resistor
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8.2.2 Detailed Design Procedure
The ESD1LIN24-Q1, ESD751-Q1, and ESD761-Q1 have a VRWM of ±24 V to protect the diode from being
damaged during a short to battery event that can occur by reversing the terminal connections during jumpstart.
The bidirectional characteristic ensures both positive and negative polarity are protected. The low capacitance of
5 pF or less permits data rates up to 10 Mbps, which allows the designer to meet the requirements for LIN. The 1
kΩ and VSUP diode allows the LIN signal to be pulled up to a diode drop below the battery voltage.
8.2.3 Application Curves
图8-3. −8-kV Clamped IEC Waveform
图8-2. +8-kV Clamped IEC Waveform
9 Power Supply Recommendations
This device is a passive TVS diode-based ESD protection device, therefore there is no requirement to power it.
Ensure that the maximum voltage specifications for each pin is not violated.
10 Layout
10.1 Layout Guidelines
• The optimum placement is as close to the connector as possible.
– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
– The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away
from the protected traces which are between the TVS and the connector.
• Route the protected traces as straight as possible.
• Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
– Electric fields tend to build up on corners, increasing EMI coupling.
• If pin 1 or 2 is connected to ground, use a thick and short trace for this return path.
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Product Folder Links: ESD1LIN24-Q1 ESD751-Q1 ESD761-Q1
ESD1LIN24-Q1, ESD751-Q1, ESD761-Q1
ZHCSR11C –SEPTEMBER 2022 –REVISED DECEMBER 2022
www.ti.com.cn
10.2 Layout Example
VBUS
To power supply
ESD1LIN24-Q1
CC1
CC2
ESD1LIN24-Q1
ESD751-Q1
SBU1
SBU2
D+
ESD751-Q1
ESD761-Q1
D-
ESD761-Q1
Legend
Pin to GND
GND
图10-1. Layout Recommendation
Copyright © 2022 Texas Instruments Incorporated
14
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Product Folder Links: ESD1LIN24-Q1 ESD751-Q1 ESD761-Q1
ESD1LIN24-Q1, ESD751-Q1, ESD761-Q1
ZHCSR11C –SEPTEMBER 2022 –REVISED DECEMBER 2022
www.ti.com.cn
11 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, ESD Layout Guide application reports
• Texas Instruments, Generic ESD Evaluation Module user's guide
• Texas Instruments, Picking ESD Diodes for Ultra High-Speed Data Lines application reports
• Texas Instruments, Reading and Understanding an ESD Protection data sheet
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
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Product Folder Links: ESD1LIN24-Q1 ESD751-Q1 ESD761-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Feb-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ESD1LIN24DYFRQ1
ESD751DYARQ1
ESD761DPYRQ1
ACTIVE
ACTIVE
ACTIVE
SOT
DYF
DYA
DPY
2
2
2
3000 RoHS & Green
8000 RoHS & Green
10000 RoHS & Green
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-1-260C-UNLIM
-55 to 150
-55 to 150
-55 to 150
2QKF
1MO
NF
Samples
Samples
Samples
SOT-5X3
X1SON
SN
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Feb-2023
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ESD1LIN24-Q1, ESD751-Q1, ESD761-Q1 :
Catalog : ESD1LIN24, ESD751, ESD761
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ESD1LIN24DYFRQ1
ESD751DYARQ1
ESD761DPYRQ1
SOT
SOT-5X3 DYA
X1SON DPY
DYF
2
2
2
3000
8000
178.0
178.0
178.0
9.5
9.5
8.4
1.48
0.5
3.3
1.25
0.73
0.47
4.0
2.0
2.0
8.0
8.0
8.0
Q1
Q1
Q1
1.94
1.15
10000
0.7
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ESD1LIN24DYFRQ1
ESD751DYARQ1
ESD761DPYRQ1
SOT
DYF
DYA
DPY
2
2
2
3000
8000
210.0
210.0
205.0
200.0
200.0
200.0
42.0
42.0
33.0
SOT-5X3
X1SON
10000
Pack Materials-Page 2
PACKAGE OUTLINE
DYA0002A
SOT (SOD-523) - 0.77 mm max height
PLASTIC SMALL OUTLINE
1.7
1.5
PIN 1
ID AREA
A
0.85
0.75
NOTE 3
2
1
1.3
1.1
0.3
0.1
0.7
0.5
B
2X
TYP
0.77 MAX
C
SEATING PLANE
0.05 C
0.15
2X
0.08
SYMM
SYMM
0.35
0.25
2X
0.1
0.05
C A B
0.4
0.2
2X
4224978/B 09/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEITA SC-79 registration except for package height
www.ti.com
EXAMPLE BOARD LAYOUT
DYA0002A
SOT (SOD-523) - 0.77 mm max height
PLASTIC SMALL OUTLINE
SYMM
2X (0.67)
(R0.05) TYP
SYMM
2
1
2X (0.4)
(1.48)
LAND PATTERN EXAMPLE
SCALE:40X
0.05 MIN
AROUND
0.05 MAX
AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDERMASK DETAILS
4224978/B 09/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DYA0002A
SOT (SOD-523) - 0.77 mm max height
PLASTIC SMALL OUTLINE
SYMM
2X (0.67)
(R0.05) TYP
SYMM
2
1
2X (0.4)
(1.48)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
4224978/B 09/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DPY0002A
X1SON - 0.45 mm max height
S
C
A
L
E
1
1
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD
1.1
0.9
B
A
PIN 1 INDEX AREA
0.7
0.5
0.45
0.30
C
SEATING PLANE
0.08 C
0.05
0.00
0.65
1
2
SYMM
0.55
0.45
2X
0.1
C A B
SYMM
0.3
0.2
2X
0.05
C A B
4224561/B 03/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DPY0002A
X1SON - 0.45 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (0.3)
SYMM
1
2
SYMM
2X (0.5)
(R0.05) TYP
(0.7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:60X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL EDGE
METAL UNDER
SOLDER MASK
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
(PREFERRED)
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4224561/B 03/2021
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view.
It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DPY0002A
X1SON - 0.45 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0)
2X (0.3)
2X (0.5)
SYMM
PCB PAD METAL
UNDER SOLDER PASTE
SYMM
2
1
(R0.05) TYP
(0.7)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:60X
4224561/B 03/2021
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DYF0002A
SOT(SOD-323) - 1 mm max height
S
C
A
L
E
6
.
0
0
0
SMALL OUTLINE TRANSISTOR
2.75
2.55
1.8
1.6
1 MAX
1.4
1.2
1 (-)
2 (+)
0.35
0.25
2X
PIN 1 ID
0.1
0.0
(0.85)
TYP
(0.475)
0.2
GAGE PLANE
0.15
0.08
TYP
0.40
0.25
TYP
0 -8 TYP
4228484/A 02/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DYF0002A
SOT(SOD-323) - 1 mm max height
SMALL OUTLINE TRANSISTOR
2X (0.9)
PKG
PKG
2
2X (0.5)
1
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:25X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
METAL
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4228484/A 02/2022
NOTES: (continued)
3. Publication IPC-7351 may have alternate designs.
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DYF0002A
SOT(SOD-323) - 1 mm max height
SMALL OUTLINE TRANSISTOR
PKG
2X (0.9)
PKG
2
2X (0.5)
1
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:25X
4228484/A 02/2022
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
6. Board assembly site may have different recommendations for stencil design.
www.ti.com
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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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