ESD401 [TI]
采用 0402 封装的单通道 0.77pF、±5.5V、±24kV ESD 保护二极管;
| 型号： | ESD401 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 0402 封装的单通道 0.77pF、±5.5V、±24kV ESD 保护二极管 二极管 |
| 文件： | 总21页 (文件大小：1277K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ESD401
ZHCSGK5A –JULY 2017–REVISED JULY 2017
具有稳定可靠的 IEC ESD 性能的 ESD401 1 通道 ESD 保护二极管
1 特性
3 说明
1
•
稳定可靠的 IEC 61000-4-2 4 级 ESD 保护
ESD401 是一种双向 TVS ESD 保护二极管，具有低
R
DYN 和低钳位电压。ESD401 旨在消除超出 IEC
–
–
±24kV 接触放电
±30kV 气隙放电
61000-4-2（4 级）国际标准所规定的最高限量水平的
ESD 冲击。低动态电阻 (0.7Ω) 可确保系统级抗瞬变事
件保护。该器件 采用 0.77pF IO 电容，非常适合用于
保护 USB 2.0 之类的接口。该器件可在高达 ±5.5V 的
电压运行，具有超低泄漏电流，并能承受高达 8.3V 的
直流故障。
•
IEC 61000-4-5 浪涌保护
–
–
4.5A (8/20µs)
1.8A IPP (8/20µs) 时，具有 12V 的低 Vclamp
•
•
IEC 61000-4-4 瞬态放电 (EFT) 保护
80A (5/50ns)
–
具有可在高达 ± 5.5V 的电压下保护接口的双向
ESD 二极管
ESD401 采用符合行业标准的 0402 (DPY) 封装。
器件信息(1)
•
•
•
•
•
•
IO 电容：0.77pF（典型值）
高直流击穿电压：8.3V（典型值）
超低泄漏电流：30pA（典型值）
低动态电阻：0.7Ω（典型值）
工业温度范围：-40°C 至 +125°C
行业标准的 0402 封装
器件型号
封装
X1SON (2)
封装尺寸（标称值）
ESD401DPY
0.60mm x 1.00mm
(1) 要了解所有可用封装，请参阅数据表末尾的可订购产品附录。
典型的 USB 2.0 应用原理图
5-V Source
2 应用
•
终端设备
VBUS
D-
–
–
–
–
–
可穿戴产品
便携式计算机和台式机
手机和平板电脑
机顶盒
D+
USB Transceiver
GND
1
2
1
数字视频录像机 (DVR) 和网络视频录像机
(NVR)
2
–
–
电视和监视器
Copyright © 2017, Texas Instruments Incorporated
EPOS（电子销售终端）
•
接口
–
–
–
–
–
1Gbps 以太网
USB 2.0/1.1（5.5V 容差）
通用输入/输出 (GPIO)
按钮/键盘
音频
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSE49
ESD401
ZHCSGK5A –JULY 2017–REVISED JULY 2017
www.ti.com.cn
目录
7.4 Device Functional Modes.......................................... 9
Application and Implementation ........................ 10
8.1 Application Information............................................ 10
8.2 Typical Application ................................................. 10
Power Supply Recommendations...................... 12
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings — JEDEC Specification ..................... 4
6.3 ESD Ratings—IEC Specification .............................. 4
6.4 Recommended Operating Conditions....................... 4
6.5 Thermal Information.................................................. 4
6.6 Electrical Characteristics........................................... 5
6.7 Typical Characteristics.............................................. 6
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 8
8
9
10 Layout................................................................... 12
10.1 Layout Guidelines ................................................. 12
10.2 Layout Example .................................................... 12
11 器件和文档支持 ..................................................... 13
11.1 文档支持................................................................ 13
11.2 接收文档更新通知 ................................................. 13
11.3 社区资源................................................................ 13
11.4 商标....................................................................... 13
11.5 静电放电警告......................................................... 13
11.6 Glossary................................................................ 13
12 机械、封装和可订购信息....................................... 13
7
4 修订历史记录
Changes from Original (July 2017) to Revision A
Page
•
Updated 图 9 and图 13 .......................................................................................................................................................... 6
2
Copyright © 2017, Texas Instruments Incorporated
ESD401
www.ti.com.cn
ZHCSGK5A –JULY 2017–REVISED JULY 2017
5 Pin Configuration and Functions
DPY Package
2-Pin X1SON
Top View
1
2
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
IO
1
2
I/O
I/O
ESD Protected Channel. If used as ESD IO, connect pin 2 to ground
ESD Protected Channel. If used as ESD IO, connect pin 1 to ground
IO
Copyright © 2017, Texas Instruments Incorporated
3
ESD401
ZHCSGK5A –JULY 2017–REVISED JULY 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
80
UNIT
A
Electrical fast transient
Peak pulse
IEC 61000-4-4 (5/50 ns) at 25°C
IEC 61000-4-5 power (tp - 8/20 µs) at 25°C
IEC 61000-4-5 current (tp - 8/20 µs) at 25°C
Operating free-air temperature
67
W
4.5
A
TA
–40
–65
125
155
°C
°C
Tstg
Storage temperature
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings — JEDEC Specification
VALUE
±2500
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 ESD Ratings—IEC Specification
VALUE
UNIT
IEC 61000-4-2 contact discharge
IEC 61000-4-2 air-gap discharge
±24000
±30000
V(ESD)
Electrostatic discharge
V
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
–5.5
–40
MAX
5.5
UNIT
VIO
TA
Input pin voltage
V
Operating free-air temperature
125
°C
6.5 Thermal Information
ESD401
THERMAL METRIC(1)
DPY (X1SON)
2 PINS
420
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
169.3
276.1
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
122.1
ψJB
157.3
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2017, Texas Instruments Incorporated
ESD401
www.ti.com.cn
ZHCSGK5A –JULY 2017–REVISED JULY 2017
6.6 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VRWM
VBRF
Reverse stand-off voltage
IIO < 10 nA
–5.5
5.5
V
Breakdown voltage, Pin 1 to Pin 2
IIO =1 mA, at TA = 25°C
7.5
7.5
9.1
9.1
V
(1)
Breakdown voltage, Pin 2 to Pin 1
VBRR
IIO =1 mA, at TA = 25°C
IIO =1 mA
V
V
(1)
(2)
VHOLD
Holding voltage
8.3
11
IPP = 1 A, TLP, from Pin 1 to Pin 2
and Pin 2 to Pin 1, TA = 25°C
IPP = 5 A, TLP, from Pin 1 to Pin 2
and Pin 2 to Pin 1, TA = 25°C
16
24
IPP = 16 A, TLP, from Pin 1 to Pin 2
and Pin 2 to Pin 1, TA = 25°C
VCLAMP
Clamping voltage
V
IPP = 1.8 A, IEC-61000-4-5 (tp - 8/20
µs) from Pin 1 to Pin 2 and Pin 2 to
Pin 1, TA = 25°C
12
IPP = 4.5 A, IEC-61000-4-5 (tp - 8/20
µs) from Pin 1 to Pin 2 and Pin 2 to
Pin 1, TA = 25°C
15
0.03
0.7
Leakage current, Pin 1 to Pin2 and
PIn2 to Pin 1
ILEAK
RDYN
CL
VIO = ±2.5 V
10
nA
Ω
Measured between TLP IPP of 10 A
and 20 A, Pin 2 to Pin 1 and Pin 1 to
Pin2, TA = 25°C
Dynamic resistance
Line capacitance
VIO = 0 V, f = 1 MHz, Pin 1 to Pin 2
and Pin2 to Pin1, TA = 25°C
0.77
0.95
pF
(1) VBRF and VBRR are defined as the voltage obtained at 1 mA when sweeping the voltage up, before the device latches into the snapback
state.
(2) VHOLD is defined as the voltage when 1 mA is applied, after the device has successfully latched into the snapback state.
版权 © 2017, Texas Instruments Incorporated
5
ESD401
ZHCSGK5A –JULY 2017–REVISED JULY 2017
www.ti.com.cn
6.7 Typical Characteristics
32
28
24
20
16
12
8
32
28
24
20
16
12
8
4
4
0
0
0
4
8
12
16
20
24
28
32
36
0
4
8
12
16
20
24
28
32
36
Voltage (V)
Voltage (V)
D001
D002
图 1. Positive TLP Curve, Pin 1 to Pin 2
图 2. Negative TLP Curve, Pin 1 to Pin 2 (Plotted as Positive
TLP Curve Pin 2 to Pin 1
70
60
50
40
30
20
10
0
10
0
-10
-20
-30
-40
-50
-60
-70
-10
-15
0
15 30 45 60 75 90 105 120 135 150
Time (ns)
-15
0
15 30 45 60 75 90 105 120 135 150
Time (ns)
D003
D004
图 3. 8-kV IEC 61000-4-2 Waveform, Pin1 to Pin 2
图 4. –8-kV IEC 61000-4-2 Waveform, Pin 1 to Pin 2
5
4.5
4
80
1
0.95
0.9
Current (A)
Power (W)
72
64
56
48
40
32
24
16
8
3.5
3
0.85
0.8
2.5
2
0.75
0.7
1.5
1
0.65
0.6
-40
25
85
0.5
0
0.55
0.5
125
0
-25
0
25
50
75
100
125
150
0
0.5
1
1.5
2
2.5
3
3.5
Time (ms)
Bias Voltage (V)
D005
D006
图 5. Surge (IEC 61000-4-5) Curve (tp = 8/20 µs), Pin 1 to Pin
图 6. Capacitance vs Bias Voltage, Pin 1 to Pin 2
2
6
版权 © 2017, Texas Instruments Incorporated
ESD401
www.ti.com.cn
ZHCSGK5A –JULY 2017–REVISED JULY 2017
Typical Characteristics (接下页)
0.001
2
1.8
1.6
1.4
1.2
1
0.0005
0
0.8
0.6
0.4
0.2
0
-0.0005
-0.001
-10
-8
-6
-4
-2
0
2
4
6
8
10
-40
-20
0
20
40
60
80
100 120 140
Voltage (V)
Temperature (èC)
D007
D008
图 7. DC Voltage Sweep I-V Curve, Pin 1 to Pin 2
图 8. Leakage Current vs. Temperature, Pin 1 to Pin 2
1
0
1.6
1.4
1.2
1
-1
-2
-3
-4
-5
-6
-7
-8
-9
0.8
0.6
0.4
0.2
0
0.001
0.01
0.1
1
10
1
2
3
4
5
6
7
8
Frequency (GHz)
Frequency (GHz)
D009
D010
图 9. Insertion Loss
图 10. Capacitance vs. Frequency, Pin 1 to Pin 2
版权 © 2017, Texas Instruments Incorporated
7
ESD401
ZHCSGK5A –JULY 2017–REVISED JULY 2017
www.ti.com.cn
7 Detailed Description
7.1 Overview
The ESD401 is a bidirectional ESD Protection Diode with ultra-low clamping voltage. This device can dissipate
ESD strikes above the maximum level specified by the IEC 61000-4-2 International Standard. The ultra-low
clamping makes this device ideal for protecting any sensitive signal pins.
7.2 Functional Block Diagram
IO
GND
Copyright © 2017, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 IEC 61000-4-2 ESD Protection
The I/O pins can withstand ESD events up to ±24-kV contact and ±30-kV air gap. An ESD-surge clamp diverts
the current to ground.
7.3.2 IEC 61000-4-4 EFT Protection
The I/O pins can withstand an electrical fast transient burst of up to 80 A (5/50 ns waveform, 4 kV with 50-Ω
impedance). An ESD-surge clamp diverts the current to ground.
7.3.3 IEC 61000-4-5 Surge Protection
The I/O pins can withstand surge events up to 4.5 A and 67W (8/20 µs waveform). An ESD-surge clamp diverts
this current to ground.
7.3.4 IO Capacitance
The capacitance between each I/O pin to ground is 0.77 pF (typical) and 0.95 pF (maximum).
7.3.5 DC Breakdown Voltage
The DC breakdown voltage of each I/O pin is ±8.3 V typical. This ensures that sensitive equipment is protected
from surges above the reverse standoff voltage of ±5.5 V.
7.3.6 Low Leakage Current
The I/O pins feature an low leakage current of 10 nA (maximum) with a bias of ±2.5 V.
7.3.7 Low ESD Clamping Voltage
The I/O pins feature an ESD clamp that is capable of clamping the voltage to 24 V (TLP IPP = 16 A).
7.3.8 Industrial Temperature Range
This device features an industrial operating range of –40°C to +125°C.
7.3.9 Industry Standard Footprint
The layout of this device makes it simple and easy to add protection to an existing layout. The packages offers
flow-through routing, requiring minimal modification to an existing layout.
8
版权 © 2017, Texas Instruments Incorporated
ESD401
www.ti.com.cn
ZHCSGK5A –JULY 2017–REVISED JULY 2017
7.4 Device Functional Modes
The ESD401 is a passive integrated circuit that triggers when voltages are above VBRF or below VBRR. During
ESD events, voltages as high as ±24 kV (contact) or ±30 kV ( air) can be directed to ground via the internal
diode network. When the voltages on the protected line fall below the trigger levels of ESD401 (usually within
10s of nano-seconds) the device reverts to passive.
图 11 shows typical TLP behavior of bi-directional ESD device that does not exhibit snapback.
+ ve
Ipp
RDYN
+
-Vhold-TLP
-VBR-TLP
-Vclamp-Ipp
-Vrwm
- ve
+ ve
Vrwm
Vclamp-Ipp
VBR-TLP
Vhold-TLP
RDYN
-
Note 1: VBR-TLP and Vhold-TLP shown here are from
the TLP measurements and not to be confused with
the DC measurements of VBRF,VBRR, and VHOLD in
Table 6.6
-Ipp
Note 2: Vrwm is not measured from the TLP curve.
It‘s shown here only to show that Vrwm < VBR-TLP
- ve
图 11. Typical TlpLP Behavior Of Bi-directional ESD Device that Does Not Exhibit Snapback
版权 © 2017, Texas Instruments Incorporated
9
ESD401
ZHCSGK5A –JULY 2017–REVISED JULY 2017
www.ti.com.cn
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The ESD401 is a diode type TVS which is used to provide a path to ground for dissipating ESD events on high-
speed signal lines between a human interface connector and a system. As the current from ESD passes through
the TVS, only a small voltage drop is present across the diode. This is the voltage presented to the protected IC.
The low RDYN of the triggered TVS holds this voltage, VCLAMP, to a safe level for the protected IC.
8.2 Typical Application
5-V Source
VBUS
D-
D+
USB Transceiver
GND
1
2
1
2
Copyright © 2017, Texas Instruments Incorporated
图 12. USB 2.0 ESD Schematic
8.2.1 Design Requirements
For this design example, two ESD401 devices are being used in a USB 2.0 application. This provides a complete
ESD protection scheme.
Given the USB 2.0 application, the parameters listed in 表 1 are known.
表 1. Design Parameters
DESIGN PARAMETER
Signal range on DP-DM lines
VALUE
0 V to 3.6 V
Operating frequency on DP-DM lines
up to 240 MHz or 480 Mbps
8.2.2 Detailed Design Procedure
8.2.2.1 Signal Range
The ESD401 supports signal ranges between –5.5 V and 5.5 V, which supports the USB 2.0 signal range of 0 to
3.6 V on the DM/DP lines..
8.2.2.2 Operating Frequency
The ESD401 has a 0.85 pF (typical) capacitance, which supports the USB 2.0 data rates of 480 Mbps.
10
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ESD401
www.ti.com.cn
ZHCSGK5A –JULY 2017–REVISED JULY 2017
8.2.3 Application Curves
1
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
0.001
0.01
0.1
1
10
Frequency (GHz)
D009
图 13. Insertion Loss
图 14. Eye Diagram - 3-Gbps Signal No Device
图 15. Eye Diagram - 3-Gbps Signal With ESD401
版权 © 2017, Texas Instruments Incorporated
11
ESD401
ZHCSGK5A –JULY 2017–REVISED JULY 2017
www.ti.com.cn
9 Power Supply Recommendations
The ESD401 is a passive ESD device so there is no need to power it. Take care not to violate the recommended
I/O specification (–5.5 V to 5.5 V) to ensure the device functions properly.
10 Layout
10.1 Layout Guidelines
•
The optimum placement is as close to the connector as possible.
–
EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
–
The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away
from the protected traces which are between the TVS and the connector.
•
•
Route the protected traces as straight as possible.
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
–
Electric fields tend to build up on corners, increasing EMI coupling.
10.2 Layout Example
VBUS
To Power Supply
ESD401
D-
To USB Transceiver
D+
ESD401
Legend
GND
Pin to GND
USB2.0 Connector
图 16. USB 2.0 ESD Layout
12
版权 © 2017, Texas Instruments Incorporated
ESD401
www.ti.com.cn
ZHCSGK5A –JULY 2017–REVISED JULY 2017
11 器件和文档支持
11.1 文档支持
相关文档请参见以下部分：
《ESD401DPY 评估模块》
11.2 接收文档更新通知
如需接收文档更新通知，请访问 ti.com 上的器件产品文件夹。请单击右上角的通知我 进行注册，即可收到任意产
品信息更改每周摘要。有关更改的详细信息，请查看任意已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
E2E is a trademark of Texas Instruments.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包括机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据发生变化时，我们可能不
会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航栏。
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13
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ESD401DPYR
ACTIVE
X1SON
DPY
2
10000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
8I
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ESD401DPYR
ESD401DPYR
X1SON
X1SON
DPY
DPY
2
2
10000
10000
180.0
178.0
9.5
8.4
0.73
0.7
1.13
1.15
0.5
2.0
2.0
8.0
8.0
Q1
Q1
0.47
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ESD401DPYR
ESD401DPYR
X1SON
X1SON
DPY
DPY
2
2
10000
10000
189.0
205.0
185.0
200.0
36.0
33.0
Pack Materials-Page 2
PACKAGE OUTLINE
DPY0002A
X1SON - 0.45 mm max height
S
C
A
L
E
1
1
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD
1.1
0.9
B
A
PIN 1 INDEX AREA
0.7
0.5
0.45
0.30
C
SEATING PLANE
0.08 C
0.05
0.00
0.65
1
2
SYMM
0.55
0.45
2X
0.1
C A B
SYMM
0.3
0.2
2X
0.05
C A B
4224561/B 03/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DPY0002A
X1SON - 0.45 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (0.3)
SYMM
1
2
SYMM
2X (0.5)
(R0.05) TYP
(0.7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:60X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL EDGE
METAL UNDER
SOLDER MASK
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
(PREFERRED)
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4224561/B 03/2021
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view.
It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DPY0002A
X1SON - 0.45 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0)
2X (0.3)
2X (0.5)
SYMM
PCB PAD METAL
UNDER SOLDER PASTE
SYMM
2
1
(R0.05) TYP
(0.7)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:60X
4224561/B 03/2021
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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