ESDS314 [TI]
适用于 USB 和以太网且具有 25A 8/20us 浪涌额定值的四路 4.5pF、3.6V、±30kV ESD 保护二极管;
| 型号： | ESDS314 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于 USB 和以太网且具有 25A 8/20us 浪涌额定值的四路 4.5pF、3.6V、±30kV ESD 保护二极管 以太网 二极管 |
| 文件： | 总20页 (文件大小：1428K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ESDS312, ESDS314
ZHCSIH2B –MAY 2018–REVISED SEPTEMBER 2018
ESDS312、ESDS314 数据线路浪涌和 ESD 保护二极管矩阵
1 特性
3 说明
1
•
IEC 61000-4-2 4 级静电放电 (ESD) 保护
ESDS314、ESDS312 是一种单向 TVS ESD 保护二极
管阵列，用于高达 25A (8/20μs) 的以太网、USB 和通
用数据线路浪涌保护。ESDS314、ESDS312 器件的
额定 ESD 冲击消散值达到了 IEC 61000-4-2（4 级）
国际标准中规定的最高水平。
–
–
±30kV 接触放电
±30kV 气隙放电
•
•
IEC 61000-4-4 瞬态放电 (EFT) 保护
80A (5/50ns)
IEC 61000-4-5 浪涌保护
–
这些器件 每通道 具有 4.5pF IO 电容，因此非常适合
用于保护高速接口，如以太网 10/100/1000、USB 2.0
和 GPIO。低动态电阻和低钳位电压确保系统级抗瞬变
事件保护。
–
–
25A (8/20μs)
低浪涌钳位电压在 25A Ipp 下为 6.5V
•
IO 电容：
–
4.5pF（典型值）
ESDS314、ESDS312 器件采用符合行业标准的 5 引
脚 SOT23 封装。
•
•
•
•
•
直流击穿电压：5.5V（最小值）
超低泄漏电流：5nA（典型值）
支持速率高达 5Gbps 的高速接口
工业温度范围：-40°C 至 +125°C
简易直通布线封装 (ESDS312)
器件信息(1)
器件编号
ESDS314
ESDS312
封装
封装尺寸（标称值）
2.9mm x 1.6mm x
1.25mm
SOT23 (5)
SOT23 (5)；2 NC
引脚
2.9mm x 1.6mm x
1.25mm
2 应用
•
终端设备
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
–
–
–
–
–
以太网交换机
接入点
典型应用原理图
网关
TP1+
打印机
RJ-45
Connector
TP1-
数字视频录像机 (DVR) 和网络视频录像机
(NVR)
ESDS314
TP2+
•
接口
TP2-
–
–
–
以太网 10/100/1000Mbps
Ethernet
PHY
TP3+
TP3-
USB 2.0
通用输入/输出 (GPIO)
ESDS314
TP4+
TP4-
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSEG9
ESDS312, ESDS314
ZHCSIH2B –MAY 2018–REVISED SEPTEMBER 2018
www.ti.com.cn
目录
7.3 Feature Description................................................... 8
7.4 Device Functional Modes.......................................... 8
Application and Implementation .......................... 9
8.1 Application Information.............................................. 9
8.2 Typical Application ................................................... 9
Power Supply Recommendations...................... 11
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings -JEDEC Specifications ........................ 4
6.3 ESD Ratings - IEC Specifications............................. 4
6.4 Recommended Operating Conditions....................... 4
6.5 Thermal Information.................................................. 4
6.6 Electrical Characteristics........................................... 5
6.7 Typical Characteristics.............................................. 6
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
8
9
10 Layout................................................................... 11
10.1 Layout Guidelines ................................................. 11
10.2 Layout Example .................................................... 11
11 器件和文档支持 ..................................................... 12
11.1 接收文档更新通知 ................................................. 12
11.2 社区资源................................................................ 12
11.3 商标....................................................................... 12
11.4 静电放电警告......................................................... 12
11.5 术语表 ................................................................... 12
12 机械、封装和可订购信息....................................... 12
7
4 修订历史记录
Changes from Revision A (July 2018) to Revision B
Page
•
已更改 将“预告信息”更改成了“生产数据” ................................................................................................................................ 1
Changes from Original (May 2018) to Revision A
Page
•
已更改 将“产品预览”更改成了“预告信息” ................................................................................................................................ 1
2
Copyright © 2018, Texas Instruments Incorporated
ESDS312, ESDS314
www.ti.com.cn
ZHCSIH2B –MAY 2018–REVISED SEPTEMBER 2018
5 Pin Configuration and Functions
ESDS312 DBV Package
5-Pin SOT23
ESDS314 DBV Package
5-Pin SOT23
Top View
Top View
2.8
1.6
2.8
1.6
1
5
1
5
NC
I/O2
I/O1
I/O4
2
2.9
2
2.9
GND
GND
3
4
3
4
I/O1
NC
I/O3
I/O2
Pin Functions for ESDS312
PIN
TYPE
DESCRIPTION
NAME
NO.
I/O1
4
5
2
1
3
I/O
GND
NC
Surge/ESD protected channels. Connect to the lines being protected.
Ground. Connect to ground.
I/O2
GND
NC
Not connected; Used for optional straight-through routing. Can be left floating or
grounded
NC
Pin Functions for ESDS314
PIN
TYPE
DESCRIPTION
Name
I/O1
No.
1
I/O2
3
I/O
Surge/ESD protected channels. Connect to the lines being protected.
Ground. Connect to ground
I/O3
4
I/O4
5
GND
2
GND
Copyright © 2018, Texas Instruments Incorporated
3
ESDS312, ESDS314
ZHCSIH2B –MAY 2018–REVISED SEPTEMBER 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
IEC 61000-4-4
Electrical Fast
Transient
Peak Power at 25 °C
80
A
IEC 61000-4-5
Surge (tp 8/20
µs
Peak Power at 25 °C
Peak Current at 25 °C
170
25
W
A
TA
Operating free-air temperature
Storage temperature
–40
–65
125
155
°C
°C
Tstg
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings -JEDEC Specifications
VALUE
UNIT
Human body model (HBM), per
±2500
ANSI/ESDA/JEDEC JS-001, allpins(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specificationJESD22-C101, all pins(2)
±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. [Following sentence
optional; see the wiki.] Manufacturing with less than 500-V HBM is possible with the necessary precautions. [Following sentence
optional; see the wiki.] Pins listed as ±WWW V and/or ±XXX V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. [Following sentence
optional; see the wiki.] Manufacturing with less than 250-V CDM is possible with the necessary precautions. [Following sentence
optional; see the wiki.] Pins listed as ±YYY V and/or ±ZZZ V may actually have higher performance.
6.3 ESD Ratings - IEC Specifications
VALUE
±30000
±30000
UNIT
IEC 61000-4-2 Contact Discharge, all pins
IEC 61000-4-2 Air Discharge, all pins
V(ESD)
Electrostatic discharge
V
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
0
NOM
MAX
UNIT
V
VIN
TA
Input voltage
3.6
Operating Free Air Temperature
–40
125
°C
6.5 Thermal Information
ESDS312
DBV (SOT-23)
5 PINS
163.9
ESDS314
DBV (SOT-23)
5 PINS
127.6
(1)
THERMAL METRIC
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
113.4
78.9
76.9
43.9
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
59.8
24.5
ΨJB
76.8
43.7
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2018, Texas Instruments Incorporated
ESDS312, ESDS314
www.ti.com.cn
ZHCSIH2B –MAY 2018–REVISED SEPTEMBER 2018
6.6 Electrical Characteristics
At TA = 25°C unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IIO < 500 nA, across operating
temperature range
VRWM
Reverse stand-off voltage
3.6
V
ILEAKAGE
VBRF
Leakage current at 3.6 V
VIO = 3.6 V, Any IO pin to GND
IIO = 1 mA
5
50
nA
V
(1)
Breakdown voltage, IO to GND
Forward Voltage, GND to IO
4.5
7.5
VFWD
IIO = 1 mA
0.8
5
V
(2)
VHOLD
Holding Voltage, IO to GND
IIO = 1 mA
V
VCLAMP
VCLAMP
VCLAMP
VCLAMP
VCLAMP
VCLAMP
VCLAMP
VCLAMP
CLINE
IPP = 1 A, Any IO pin to GND
IPP = 12 A, Any IO pin to GND
IPP = 25 A, Any IO pin to GND
IPP = 1 A, GND to any IO pin
IPP = 12 A, GND to any IO pin
IPP = 25 A, GND to any IO pin
IPP = 16 A, Any IO pin to GND
IPP = 16 A, GND to any IO pin
VIO = 0 V, Vp-p = 30 mV, f = 1 MHz
5
V
5.6
6.5
1
V
V
Surge Clamping voltage, tp = 8/20 µs
V
2.1
3.6
5.5
2.2
4.5
V
V
V
TLP Clamping Voltage, tp = 100 ns
V
Line capacitance, Any IO to GND
Variation of line capacitance
Line-to-line capacitance
5.5
0.1
pF
CLINE1 - CLINE2, VIO = 0 V, Vp-p = 30
mV, f = 1 MHz
ΔCLINE
0.05
2.25
pF
pF
CCROSS
VIO = 0V, Vrms = 30 mV, f = 1 MHz
2.75
(1) VBRF and VBRR are defined as the voltage obtained at 1 mA when sweeping the voltage up, before the device latches into the
snapback state
(2) VHOLD is defined as the voltage when 1 mA is applied, after the device has successfully latched into the snapback state.
版权 © 2018, Texas Instruments Incorporated
5
ESDS312, ESDS314
ZHCSIH2B –MAY 2018–REVISED SEPTEMBER 2018
www.ti.com.cn
6.7 Typical Characteristics
5
4
3
2
1
0
7
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
0
5
10
15
20
25
30
0
5
10
15
20
25
30
Peak Pulse Cuurent (A)
Peak Pulse Current (A)
D001
D002
图 1. Clamping Voltage vs. Peak Pulse Current (tp= 8/20 µs),
图 2. Clamping Voltage vs. Peak Pulse Current (tp= 8/20 µs),
Any IO Pin to GND
GND to Any IO Pin
27.5
25
220
200
180
160
140
120
100
80
0.001
0.0008
0.0006
0.0004
0.0002
0
Voltage (V)
Current (A)
Power (W)
22.5
20
17.5
15
12.5
10
-0.0002
-0.0004
-0.0006
-0.0008
-0.001
-0.0012
7.5
5
60
40
2.5
0
20
0
-2.5
-20
-1
0
1
2
3
4
5
6
0
20
40
60
80 100 120 140 160 180 200
Voltage (V)
Time (ms)
D004
D003
D004_DC_Plot.grf
图 3. Surge Current, Clamping Voltage and Power Curve (tp
= 8/20 µs), Any IO Pin to GND
图 4. DC I-V Curve
32
28
24
20
16
12
8
4
0
-4
-8
-12
-16
-20
-24
-28
-32
4
0
-4
0
1
2
3
4
5
6
7
-3.5
-3
-2.5
-2
-1.5
-1
-0.5
0
Voltage (V)
Voltage (V)
D005
D006
D005_TLP_Pos.grf
D006_TLP_Neg.grf
图 5. TLP I-V Curve, IO to GND, tp = 100 ns
图 6. TLP I-V Curve, IO to GND Negative, tp=100 ns
80
70
60
50
40
30
20
10
0
40
30
20
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-10
-20
-30
-40
-10
0
10
20
30
40
50
60
70
80
90
-10
0
10
20
30
40
50
60
70
80
90
Time (ns)
Time (ns)
D007
D008
D007_IEC_Pos.grf
D008_IEC_Neg.grf
图 7. +8 kV IEC 61000-4-2 Clamping Voltage Waveform
图 8. -8 kV IEC 61000-4-2 Clamping Voltage Waveform
版权 © 2018, Texas Instruments Incorporated
6
ESDS312, ESDS314
www.ti.com.cn
ZHCSIH2B –MAY 2018–REVISED SEPTEMBER 2018
Typical Characteristics (接下页)
8
7.5
7
100
90
80
70
60
50
40
30
20
10
0
6.5
6
5.5
5
4.5
4
-50
-25
0
25
50
75
100
125
0
0.5
1
1.5
2
2.5
3
3.5
4
Temperature (èC)
Voltage (V)
D009
D010
D009_Leakage.grf
D010_Cap_Vbias.grf
图 9. DC Leakage vs. Ambient Temperature, Bias Voltage =
图 10. Capacitance vs. Bias Voltage at 25°C
3.6 V
0
-1
105
-2
100
95
90
85
80
75
-3
-4
-5
-6
-7
-8
-9
-10
-11
-12
0
25
50
75
100
125
0.1
0.2
0.3 0.4 0.5 0.60.7
Frequency (GHz)
1
2
Temperature (èC)
D011
D012
D011_Power_Derating.grf
D012_S21.grf
图 11. Surge Power Derating with Respect To Ambient
图 12. Differential Insertion Loss
Temperature
版权 © 2018, Texas Instruments Incorporated
7
ESDS312, ESDS314
ZHCSIH2B –MAY 2018–REVISED SEPTEMBER 2018
www.ti.com.cn
7 Detailed Description
7.1 Overview
The ESDS314, ESDS312 devices are unidirectional ESD Protection Diode with a low capacitance. These
devices can dissipate high surge currents upto 25 A (8/20 µs) and ESD strikes above the maximum level
specified by the IEC 61000-4-2 International Standard. The low capacitance makes this device ideal for
protecting high-speed signal interfaces such as Ethernet 10/100/1000 Mbps and general purpose high speed
data lines.
7.2 Functional Block Diagram
ESDS312
I/O1 I/O2
ESDS314
I/O1 I/O3
I/O1
I/O4
GND
GND
7.3 Feature Description
7.3.1 IEC 61000-4-4 EFT Protection
The I/O pins of ESDS314 and ESDS312 can withstand surge events (IEC 61000-4-5, 8/20 µs waveform) up to
25 A and 170 W. These devices also provide ESD protection up to ±30-kV contact and ±30-kV air gap per IEC
61000-4-2 standard. The I/O pins can withstand an electrical fast transient burst of up to 80 A (IEC 61000-4-4
5/50 ns waveform, 4 kV with 50-Ω impedance). The capacitance between each I/O pin to ground is 4.5 pF
(typical) and 5.5 pF (maximum). This device supports data rates up to 1 Gbps.
The reverse DC breakdown voltage of each I/O pin is a minimum of 4.5 V. This ensures that sensitive equipment
is protected from surges above the reverse standoff voltage of 3.6 V. The I/O pins feature an ultra-low leakage
current of 100 nA (maximum) with a bias of 3.6 V. This device features an industrial operating range of –40°C to
+125°C.
7.4 Device Functional Modes
The ESDS314, ESDS312 devices are a passive integrated circuit that triggers when voltages are above VBRF or
below 0.7 V. During ESD events, voltages as high as ±30 kV (air) can be directed to ground via the internal
diode network. When the voltages on the protected line fall below the trigger levels of ESDS314, ESDS312
(usually within a few nano-seconds) the devices reverts to passive.
8
版权 © 2018, Texas Instruments Incorporated
ESDS312, ESDS314
www.ti.com.cn
ZHCSIH2B –MAY 2018–REVISED SEPTEMBER 2018
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The ESDS314, ESDS312 devices are diode type TVS which is used to provide a path to ground for dissipating
surge and ESD events on high-speed signal lines between a human interface connector and a system. As the
current from surge or ESD passes through the TVS, only a small voltage drop is present across the diode. This
is the voltage presented to the protected IC. The low RDYN of the triggered TVS holds this voltage, VCLAMP, to a
safe level for the protected IC.
8.2 Typical Application
TP1+
RJ-45
Connector
TP1-
ESDS314
TP2+
TP2-
Ethernet
PHY
TP3+
TP3-
ESDS314
TP4+
TP4-
图 13. ESDS314 Protecting the Ethernet 1Gbps Interface
8.2.1 Design Requirements
A typical operation for the ESDS314 would be protecting a high speed dataline similar to one shown in 图 13. In
this example, the ESDS314 is protecting an Ethernet PHY's data lines that has a nominal operating voltage of
3.6 V. Many of the Ethernet interfaces that connect to long cables require protection against ±1 kV surge test
through a 42-Ω coupling resistor and a 0.5 µF capacitor, equaling roughly 24 A of surge current. Without any
input protection, if a surge event is caused by lightning, coupling, ringing, or any other fault condition, this input
voltage will rise to hundreds of volts for multiple microseconds, harming the device.
For Ethernet 1000Base-T (1Gbps), application design parameters listed in 表 1 are known.
表 1. Design Parameters
DESIGN PARAMETER
Signal range on differential data line pairs
Operating frequency
VALUE
0 to 3.6 V
125 MHz
版权 © 2018, Texas Instruments Incorporated
9
ESDS312, ESDS314
ZHCSIH2B –MAY 2018–REVISED SEPTEMBER 2018
www.ti.com.cn
8.2.2 Detailed Design Procedure
8.2.2.1 Signal Range
The ESDS314 has 4 identical surge protection channels with each channel supporting a signal range of 0 to 3.6
V. The device will work well with any Ethernet PHY that drives the single ended voltage on the data line up to a
3.6 V.
8.2.2.2 Operating Frequency
The ESDS314 has a capacitance of 4.5 pF (typical) and can support the 125 MHz operation of Ethernet
1000Base-T application
8.2.3 Application Curves
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
-11
-12
0.1
0.2
0.3 0.4 0.5 0.60.7
Frequency (GHz)
1
2
D012
D012_S21.grf
图 14. Differential Insertion Loss vs. Frequency
10
版权 © 2018, Texas Instruments Incorporated
ESDS312, ESDS314
www.ti.com.cn
ZHCSIH2B –MAY 2018–REVISED SEPTEMBER 2018
9 Power Supply Recommendations
The ESDS314, ESDS312 devices are passive ESD devices and there is no need to power it. Take care not to
violate the recommended I/O specification (0 V to 3.6 V) to ensure the device functions properly.
10 Layout
10.1 Layout Guidelines
•
The optimum placement is as close to the connector as possible.
–
EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
–
The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away
from the protected traces which are between the TVS and the connector.
•
•
Route the protected traces as straight as possible.
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
–
Electric fields tend to build up on corners, increasing EMI coupling.
10.2 Layout Example
图 15. Layout Example for 4-channel Device
版权 © 2018, Texas Instruments Incorporated
11
ESDS312, ESDS314
ZHCSIH2B –MAY 2018–REVISED SEPTEMBER 2018
www.ti.com.cn
11 器件和文档支持
11.1 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.2 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.3 商标
E2E is a trademark of Texas Instruments.
11.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.5 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
12
版权 © 2018, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ESDS312DBVR
ESDS314DBVR
ACTIVE
ACTIVE
SOT-23
SOT-23
DBV
DBV
5
5
3000 RoHS & Green
3000 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
1R4B
1R2B
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Sep-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ESDS312DBVR
ESDS314DBVR
SOT-23
SOT-23
DBV
DBV
5
5
3000
3000
178.0
178.0
9.0
9.0
3.3
3.3
3.2
3.2
1.4
1.4
4.0
4.0
8.0
8.0
Q3
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Sep-2018
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ESDS312DBVR
ESDS314DBVR
SOT-23
SOT-23
DBV
DBV
5
5
3000
3000
180.0
180.0
180.0
180.0
18.0
18.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
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这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
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