F280025PMQR [TI]
TMS320F28002x Microcontrollers;
| 型号： | F280025PMQR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TMS320F28002x Microcontrollers 微控制器 |
| 文件： | 总180页 (文件大小：3359K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Support &
Community
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
TMS320F28002x Microcontrollers
1 Device Overview
1.1 Features
1
• TMS320C28x 32-bit DSP core at 100 MHz
– IEEE 754 Floating-Point Unit (FPU)
– Support for Fast Integer Division (FINTDIV)
– Trigonometric Math Unit (TMU)
• Analog system
– Two 3.45-MSPS, 12-bit Analog-to-Digital
Converters (ADCs)
– Up to 16 external channels
– Four integrated Post-Processing Blocks
(PPB) per ADC
– Support for Nonlinear Proportional Integral
Derivative (NLPID) control
– Four windowed comparators (CMPSS) with
12-bit reference Digital-to-Analog Converters
(DACs)
– CRC Engine and Instructions (VCRC)
– Ten hardware breakpoints (with ERAD)
• On-chip memory
– Digital glitch filters
• Enhanced control peripherals
– 128KB (64KW) of flash (ECC-protected)
– 24KB (12KW) of RAM (ECC or parity-protected)
– Dual-zone security
– 14 ePWM channels with eight channels that
have high-resolution capability (150-ps
resolution)
• Clock and system control
– Two internal zero-pin 10-MHz oscillators
– On-chip crystal oscillator or external clock input
– Windowed watchdog timer module
– Missing clock detection circuitry
– Dual-clock Comparator (DCC)
• Single 3.3-V supply
– Internal VREG generation
– Brownout reset (BOR) circuit
• System peripherals
– Integrated dead-band support
– Integrated hardware trip zones (TZs)
– Three Enhanced Capture (eCAP) modules
– High-resolution Capture (HRCAP) available
on one of the three eCAP modules
– Two Enhanced Quadrature Encoder Pulse
(eQEP) modules with support for CW/CCW
operation modes
• Configurable Logic Block (CLB)
– Augments existing peripheral capability
– Supports position manager solutions
• Host Interface Controller (HIC)
– Access to internal memory from an external host
• Background CRC (BGCRC)
– 6-channel Direct Memory Access (DMA)
controller
– 39 individually programmable multiplexed
General-Purpose Input/Output (GPIO) pins
– 16 digital inputs on analog pins
– Enhanced Peripheral Interrupt Expansion (ePIE)
– Multiple low-power mode (LPM) support
– One cycle CRC computation on 32 bits of data
• Diagnostic features
– Embedded Real-time Analysis and Diagnostic
(ERAD)
– Unique Identification (UID) number
– Memory Power On Self Test (MPOST)
– Hardware Built-in Self Test (HWBIST)
• Package options:
– 80-pin Low-profile Quad Flatpack (LQFP)
[PN suffix]
– 64-pin LQFP [PM suffix]
– 48-pin LQFP [PT suffix]
• Temperature options:
• Communications peripherals
– One Power-Management Bus (PMBus) interface
– Two Inter-integrated Circuit (I2C) interfaces
– One Controller Area Network (CAN) bus port
– Two Serial Peripheral Interface (SPI) ports
– One Serial Communication Interface (SCI)
– Two Local Interconnect Network (LIN) interfaces
– S: –40°C to 125°C junction
– Q: –40ºC to 125ºC free-air
(AEC Q100 qualification for automotive
applications)
– Fast Serial Interface (FSI) with one transmitter
and one receiver (up to 200Mbps)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to
change without notice.
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
1.2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Air conditioner outdoor unit
Door operator drive control
Automated sorting equipment
Textile machine
•
•
•
•
•
•
•
•
•
•
•
•
•
•
On-board (OBC) & wireless charger
AC drive control module
AC drive position feedback
AC drive power stage module
Linear motor power stage
Servo drive position feedback
Servo drive power stage module
AC-input BLDC motor drive
DC-input BLDC motor drive
Industrial AC-DC
AC charging (pile) station
DC charging (pile) station
EV charging station power module
Wireless vehicle charging module
Energy storage power conversion system (PCS)
Central inverter
Micro inverter
Three phase UPS
Solar power optimizer
Merchant DC/DC
String inverter
Merchant network & server PSU
Merchant telecom rectifiers
DC/DC converter
Inverter & motor control
1.3 Description
C2000™ 32-bit microcontrollers are optimized for processing, sensing, and actuation to improve closed-
loop performance in real-time control applications such as industrial motor drives; solar inverters and
digital power; electrical vehicles and transportation; motor control; and sensing and signal processing.
The TMS320F28002x (F28002x) is a powerful 32-bit floating-point microcontroller unit (MCU) that lets
designers incorporate crucial control peripherals, differentiated analog, and nonvolatile memory on a
single device.
The real-time control subsystem is based on TI’s 32-bit C28x DSP core, which provides 100 MHz of signal
processing performance. The C28x CPU is further boosted by the new TMU extended instruction set,
which enables fast execution of algorithms with trigonometric operations commonly found in transforms
and torque loop calculations; and the VCRC extended instruction set, which reduces the latency for
complex math operations commonly found in encoded applications.
The F28002x supports up to 128KB (64KW) of flash memory in one bank. Up to 24KB (12KW) of on-chip
SRAM is also available in blocks of 4KB (2KW) for efficient system partitioning. Flash ECC, SRAM
ECC/parity, and dual-zone security are also supported.
High-performance analog blocks are integrated on the F28002x MCU to further enable system
consolidation. Two separate 12-bit ADCs provide precise and efficient management of multiple analog
signals, which ultimately boosts system throughput. Four analog comparator modules provide continuous
monitoring of input voltage levels for trip conditions.
The TMS320C2000™ devices contain industry-leading control peripherals with frequency-independent
ePWM/HRPWM and eCAP allow for a best-in-class level of control to the system.
Connectivity is supported through various industry-standard communication ports (such as SPI, SCI, I2C,
PMBus, LIN, and CAN) and offers multiple muxing options for optimal signal placement in a variety of
applications. New to the C2000™ platform is Host Interface Controller (HIC), a high throughput interface
that allows an external host to access resources of the TMS320F28002x. Additionally, in an industry first,
the FSI enables high-speed, robust communication to complement the rich set of peripherals that are
embedded in the device.
A specially enabled device variant, TMS320F28002xC, allows access to the Configurable Logic Block
(CLB) for additional interfacing features and allows access to the secure ROM. See Device Comparison
for more information.
2
Device Overview
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
The Embedded Real-Time Analysis and Diagnostic (ERAD) module enhances the debug and system
analysis capabilities of the device by providing additional hardware breakpoints and counters for profiling.
To learn more about the C2000 MCUs, visit the C2000 Overview at www.ti.com/c2000.
Device Information(1)
PART NUMBER
TMS320F280025PN
PACKAGE
LQFP (80)
LQFP (80)
LQFP (80)
LQFP (80)
LQFP (64)
LQFP (64)
LQFP (64)
LQFP (64)
LQFP (64)
LQFP (64)
LQFP (64)
LQFP (48)
LQFP (48)
LQFP (48)
LQFP (48)
LQFP (48)
BODY SIZE
12.0 mm × 12.0 mm
12.0 mm × 12.0 mm
12.0 mm × 12.0 mm
12.0 mm × 12.0 mm
10.0 mm × 10.0 mm
10.0 mm × 10.0 mm
10.0 mm × 10.0 mm
10.0 mm × 10.0 mm
10.0 mm × 10.0 mm
10.0 mm × 10.0 mm
10.0 mm × 10.0 mm
7.0 mm × 7.0 mm
7.0 mm × 7.0 mm
7.0 mm × 7.0 mm
7.0 mm × 7.0 mm
7.0 mm × 7.0 mm
TMS320F280025CPN
TMS320F280023PN
TMS320F280023CPN
TMS320F280025PM
TMS320F280025CPM
TMS320F280024PM
TMS320F280024CPM
TMS320F280023PM
TMS320F280023CPM
TMS320F280022PM
TMS320F280025PT
TMS320F280025CPT
TMS320F280023PT
TMS320F280023CPT
TMS320F280021PT
(1) For more information on these devices, see Mechanical, Packaging, and Orderable Information.
Copyright © 2020, Texas Instruments Incorporated
Device Overview
3
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
1.4 Functional Block Diagram
Figure 1-1 shows the CPU system and associated peripherals.
Boot ROM
Secure ROM
C28x CPU
FPU32
Flash Bank0
16 Sectors
64 KW (128 KB)
FINTDIV
TMU
VCRC
CPU Timers
DCC
DCSM
ePIE
ERAD
M0-M1 RAM
2 KW (4 KB)
BGCRC
HIC
LS4-LS7 RAM
8 KW (16 KB)
Crystal Oscillator
INTOSC1, INTOSC2
PLL
GS0 RAM
2 KW (4 KB)
DMA
6 Channles
PF1
PF3
PF4
PF2
PF7
PF8
PF9
Result
2x 12-Bit ADC
Data
14x ePWM Chan.
(8 Hi-Res Capable)
1x PMBUS
2x SPI
1x CAN
2x LIN
1x SCI
2x I2C
4x CMPSS
39x GPIO
Input XBAR
Output XBAR
ePWM XBAR
3x eCAP
(1 HRCAP Capable)
1x FSI RX
1x FSI TX
NMI
Watchdog
2x eQEP
(CW/CCW Support)
Windowed
Watchdog
Figure 1-1. Functional Block Diagram
4
Device Overview
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Table of Contents
1
Device Overview ......................................... 1
1.1 Features .............................................. 1
6.3 Memory ............................................ 141
6.4 Identification........................................ 146
1.2 Applications........................................... 2
1.3 Description............................................ 2
1.4 Functional Block Diagram ............................ 4
Revision History ......................................... 5
Device Comparison ..................................... 6
3.1 Related Products ..................................... 7
Terminal Configuration and Functions.............. 8
4.1 Pin Diagrams ......................................... 8
4.2 Pin Attributes ........................................ 12
4.3 Signal Descriptions.................................. 26
4.4 Pin Multiplexing...................................... 36
4.5 Pins With Internal Pullup and Pulldown............. 41
4.6 Connections for Unused Pins ....................... 42
Specifications ........................................... 43
5.1 Absolute Maximum Ratings......................... 43
5.2 ESD Ratings – Commercial......................... 44
5.3 ESD Ratings – Automotive.......................... 44
5.4 Recommended Operating Conditions............... 45
5.5 Power Consumption Summary...................... 46
5.6 Electrical Characteristics............................ 48
5.7 Thermal Design Considerations .................... 48
5.8 System .............................................. 49
5.9 Analog Peripherals .................................. 76
5.10 Control Peripherals.................................. 94
5.11 Communications Peripherals ...................... 109
Detailed Description.................................. 139
6.1 Overview ........................................... 139
6.2 Functional Block Diagram ......................... 140
6.5
Bus Architecture – Peripheral Connectivity........ 147
6.6 C28x Processor .................................... 148
6.7
Embedded Real-Time Analysis and Diagnostic
(ERAD)............................................. 150
2
3
6.8 Background CRC-32 (BGCRC).................... 150
6.9 Direct Memory Access (DMA) ..................... 151
6.10 Device Boot Modes ................................ 153
6.11 Dual Code Security Module ....................... 159
6.12 Watchdog .......................................... 160
6.13 C28x Timers ....................................... 161
6.14 Dual-Clock Comparator (DCC) .................... 161
6.15 Configurable Logic Block (CLB) ................... 163
Applications, Implementation, and Layout ...... 165
7.1 TI Reference Design............................... 165
Device and Documentation Support.............. 166
4
7
8
5
8.1
Device and Development Support Tool
Nomenclature ...................................... 166
8.2 Markings ........................................... 167
8.3 Tools and Software ................................ 168
8.4 Documentation Support............................ 169
8.5 Related Links ...................................... 170
8.6 Support Resources ................................ 170
8.7 Trademarks ........................................ 171
8.8 Electrostatic Discharge Caution ................... 171
8.9 Glossary............................................ 171
9
Mechanical, Packaging, and Orderable
6
Information............................................. 172
9.1 Packaging Information ............................. 172
2 Revision History
DATE
REVISION
NOTES
March 2020
*
Initial Release
Copyright © 2020, Texas Instruments Incorporated
Revision History
5
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
3 Device Comparison
Table 3-1 lists the features of the TMS320F28002x devices.
Table 3-1. Device Comparison
F280025
F280025C
F280024
F280024C
F280023
F280023C
FEATURE(1)
F280022
F280021
PROCESSOR AND ACCELERATORS
Frequency (MHz)
100
FPU32
Yes (with new instructions for Fast Integer Division)
C28x
VCRC
Yes
TMU – Type 1
Fast Integer Division
Yes (with new instructions supporting NLPID)
Yes
Yes
DMA – Type 0
Flash
MEMORY
128KB (64KW)
64KB (32KW)
20KB (10KW)
32KB (16KW)
Dedicated and Local Shared
RAM
RAM
Global Shared RAM
TOTAL RAM
4KB (2KW)
24KB (12KW)
Yes
Code security for on-chip flash and RAM
SYSTEM
Configurable Logic Block (CLB)(2)
32-bit CPU timers
F280025C
F280024C
F280023C
-
3
1
Watchdog timer
Nonmaskable Interrupt Watchdog (NMIWD) timers
Crystal oscillator/External clock input
0-pin internal oscillator
1
1
2
80-pin PN
39
26
14
–
24
–
39
26
14
–
24
–
39
26
14
GPIO pins
64-pin PM
48-pin PT
4 (When cJTAG is used, TDI and TDO can be GPIO;
When INTOSC is used as clock source, X1 and X2 can be GPIO)
Additional GPIO
80-pin PN
64-pin PM
48-pin PT
16
16
14
5
AIO inputs
External interrupts
ANALOG PERIPHERALS
Number of ADCs
MSPS
Conversion Time (ns)(3)
2
3.45
290
16
16
14
1
ADC 12-bit
80-pin PN
ADC channels (single-ended) 64-pin PM
48-pin PT
Temperature sensor
CMPSS (each has two comparators and two internal DACs)
4
(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor
differences between devices that do not affect the basic functionality of the module.
(2) C devices include additional Motor Control libraries in ROM. Contact TI for more information.
(3) Time between start of sample-and-hold window to start of sample-and-hold window of the next conversion.
6
Device Comparison
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Table 3-1. Device Comparison (continued)
F280025
F280025C
F280024
F280024C
F280023
F280023C
FEATURE(1)
F280022
F280021
CONTROL PERIPHERALS(4)
eCAP/HRCAP modules – Type 2
ePWM/HRPWM channels – Type 4
eQEP modules – Type 2
3 (1 with HRCAP capability)
14 (8 with HRPWM capability)
2
COMMUNICATION PERIPHERALS(4)
CAN – Type 0
I2C – Type 1
SCI – Type 0
SPI – Type 2
LIN – Type 1
PMBus – Type 0
FSI – Type 1
1
2
1
2
2
1
1 (1 RX and 1 TX)
PACKAGE, TEMPERATURE, AND QUALIFICATION OPTIONS
80-pin PN
Yes
Yes
Yes
–
–
–
Yes
Yes
Yes
–
–
–
–
–
S: –40°C to 125°C (TJ)
64-pin PM
48-pin PT
Yes
Yes
(F280023)
80-pin PN
64-pin PM
48-pin PT
Yes
–
–
Yes
–
–
Yes
–
–
–
Q: –40°C to 125°C (TA)(5)
–
Yes
(F280023)
Yes
Yes
(4) For devices that are available in more than one package, the peripheral count listed in the smaller package is reduced because the
smaller package has less device pins available. The number of peripherals internally present on the device is not reduced co
(5) The letter Q refers to AEC Q100 qualification for automotive applications.
3.1 Related Products
TMS320F2803x Microcontrollers
The F2803x series increases the pin-count and memory size options. The F2803x series also introduces
the parallel control law accelerator (CLA) option.
TMS320F2807x Microcontrollers
The F2807x series offers the most performance, largest pin counts, flash memory sizes, and peripheral
options. The F2807x series includes the latest generation of accelerators, ePWM peripherals, and analog
technology.
TMS320F28004x Microcontrollers
The F28004x series is a reduced version of the F2807x series with the latest generational enhancements.
TMS320F2838x Microcontrollers
The F2838x series offers more performance, larger pin counts, flash memory sizes, peripheral and wide
variety of connectivity options. The F2838x series includes the latest generation of accelerators, ePWM
peripherals, and analog technology. Configurable logic block (CLB) versions are available.
Copyright © 2020, Texas Instruments Incorporated
Device Comparison
7
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
4 Terminal Configuration and Functions
4.1 Pin Diagrams
Figure 4-1 shows the pin assignments on the 80-pin PN low-profile quad flatpack (Q temperature).
Figure 4-2 shows the pin assignments on the 64-pin PM low-profile quad flatpack. Figure 4-3 shows the
pin assignments on the 64-pin PM low-profile quad flatpack (Q temperature). Figure 4-4 shows the pin
assignments on the 48-Pin PT low-profile quad flatpack.
GPIO2
GPIO1
GPIO0
GPIO40
GPIO23
GPIO41
GPIO22
GPIO7
GPIO44
VSS
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
GPIO17
GPIO16
GPIO33
GPIO11
GPIO12
GPIO13
FLT1
FLT2
VDDIO
VDD
VDD
VSS
VDDIO
GPIO45
GPIO5
GPIO9
GPIO10
GPIO34
GPIO15
GPIO14
GPIO6
A10,C10
A9,C8
A4,C14
VDDA
VSSA
A8,C11
A7,C3
A12,C1
VREFLO
Not to scale
A. Only the GPIO function is shown on GPIO terminals. See Section 4.2 for the complete, muxed signal name.
Figure 4-1. 80-Pin PN Low-Profile Quad Flatpack (Top View)
8
Terminal Configuration and Functions
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
GPIO3
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
GPIO33
GPIO11
GPIO12
GPIO13
VDDIO
VDD
GPIO2
GPIO1
GPIO0
GPIO40
GPIO23
GPIO41
GPIO22
GPIO7
VSS
VSS
A10,C10
A9,C8
A4,C14
VDDA
VDD
VDDIO
GPIO5
GPIO9
GPIO10
GPIO6
VSSA
A8,C11
A7,C3
A12,C1
VREFLO
Not to scale
A. Only the GPIO function is shown on GPIO terminals. See Section 4.2 for the complete, muxed signal name.
Figure 4-2. 64-Pin PM Low-Profile Quad Flatpack (Top View)
Copyright © 2020, Texas Instruments Incorporated
Terminal Configuration and Functions
9
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
GPIO3
GPIO2
GPIO1
GPIO0
GPIO40
GPIO23
GPIO41
GPIO22
GPIO7
VSS
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
GPIO33
GPIO11
FLT1
FLT2
VDDIO
VDD
VSS
A10,C10
A9,C8
A4,C14
VDDA
VSSA
VDD
VDDIO
GPIO5
GPIO9
GPIO10
GPIO6
A8,C11
A7,C3
A12,C1
VREFLO
Not to scale
A. Only the GPIO function is shown on GPIO terminals. See Section 4.2 for the complete, muxed signal name.
Figure 4-3. 64-Pin PM Low-Profile Quad Flatpack – Q-Temperature (Top View)
10
Terminal Configuration and Functions
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
VSS
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
GPIO7
VSS
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
FLT1
FLT2
VSS
A10,C10
A9,C8
A4,C14
VDDA
VSSA
VDD
A8,C11
A7,C3
A12,C1
VREFLO
VDDIO
GPIO5
GPIO6
Not to scale
A. Only the GPIO function is shown on GPIO terminals. See Section 4.2 for the complete, muxed signal name.
Figure 4-4. 48-Pin PT Low-Profile Quad Flatpack (Top View)
Copyright © 2020, Texas Instruments Incorporated
Terminal Configuration and Functions
11
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
4.2 Pin Attributes
Table 4-1. Pin Attributes
MUX
64
PIN
TYPE
SIGNAL NAME
80 QFP 64 QFP 48 QFP
ANALOG
DESCRIPTION
POSITION QFP-Q
A0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
ADC-A Input 0
ADC-C Input 15
C15
CMP3_HP2
CMP3_LP2
AIO231
15
19
18
15
14
11
10
CMPSS-3 High Comparator Positive Input 2
CMPSS-3 Low Comparator Positive Input 2
Analog Pin Used For Digital Input 231
ADC-A Input 1
A1
CMP1_HP4
CMP1_LP4
AIO232
CMPSS-1 High Comparator Positive Input 4
CMPSS-1 Low Comparator Positive Input 4
Analog Pin Used For Digital Input 232
ADC-A Input 10
14
25
A10
C10
ADC-C Input 10
CMP2_HP3
CMP2_HN0
CMP2_LP3
CMP2_LN0
AIO230
CMPSS-2 High Comparator Positive Input 3
CMPSS-2 High Comparator Negative Input 0
CMPSS-2 Low Comparator Positive Input 3
CMPSS-2 Low Comparator Negative Input 0
Analog Pin Used For Digital Input 230
ADC-A Input 11
29
25
21
A11
C0
ADC-C Input 0
CMP1_HP1
CMP1_HN1
CMP1_LP1
CMP1_LN1
AIO237
CMPSS-1 High Comparator Positive Input 1
CMPSS-1 High Comparator Negative Input 1
CMPSS-1 Low Comparator Positive Input 1
CMPSS-1 Low Comparator Negative Input 1
Analog Pin Used For Digital Input 237
ADC-A Input 12
12
16
12
8
A12
C1
ADC-C Input 1
CMP2_HP1
CMP4_HP2
CMP2_HN1
CMP2_LP1
CMP4_LP2
CMP2_LN1
AIO238
CMPSS-2 High Comparator Positive Input 1
CMPSS-4 High Comparator Positive Input 2
CMPSS-2 High Comparator Negative Input 1
CMPSS-2 Low Comparator Positive Input 1
CMPSS-4 Low Comparator Positive Input 2
CMPSS-2 Low Comparator Negative Input 1
Analog Pin Used For Digital Input 238
ADC-A Input 14
18
22
18
14
A14
C4
ADC-C Input 4
CMP3_HP4
CMP3_LP4
AIO239
11
10
15
14
11
10
CMPSS-3 High Comparator Positive Input 4
CMPSS-3 Low Comparator Positive Input 4
Analog Pin Used For Digital Input 239
ADC-A Input 15
A15
C7
ADC-C Input 7
CMP1_HP3
CMP1_HN0
CMP1_LP3
CMP1_LN0
AIO233
CMPSS-1 High Comparator Positive Input 3
CMPSS-1 High Comparator Negative Input 0
CMPSS-1 Low Comparator Positive Input 3
CMPSS-1 Low Comparator Negative Input 0
Analog Pin Used For Digital Input 233
7
12
Terminal Configuration and Functions
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Table 4-1. Pin Attributes (continued)
MUX
64
PIN
TYPE
SIGNAL NAME
80 QFP 64 QFP 48 QFP
DESCRIPTION
POSITION QFP-Q
A2
I
I
I
I
I
I
I
ADC-A Input 2
ADC-C Input 9
C9
CMP1_HP0
CMP1_LP0
AIO224
A3
9
13
9
6
CMPSS-1 High Comparator Positive Input 0
CMPSS-1 Low Comparator Positive Input 0
Analog Pin Used For Digital Input 224
ADC-A Input 3
C5
ADC-C Input 5
Optional external reference voltage for on-chip
CMPSS DACs. There is an internal capacitor to
VSSA on this pin whether used for ADC input or
CMPSS DAC reference which cannot be
disabled. If this pin is being used as a reference
for the CMPSS DACs, place at least a 1-µF
capacitor on this pin.
VDAC
I
8
12
8
5
CMP3_HP3
CMP3_HN0
CMP3_LP3
CMP3_LN0
AIO242
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
CMPSS-3 High Comparator Positive Input 3
CMPSS-3 High Comparator Negative Input 0
CMPSS-3 Low Comparator Positive Input 3
CMPSS-3 Low Comparator Negative Input 0
Analog Pin Used For Digital Input 242
ADC-A Input 4
A4
C14
ADC-C Input 14
CMP2_HP0
CMP4_HP3
CMP4_HN0
CMP2_LP0
CMP4_LP3
CMP4_LN0
AIO225
CMPSS-2 High Comparator Positive Input 0
CMPSS-4 High Comparator Positive Input 3
CMPSS-4 High Comparator Negative Input 0
CMPSS-2 Low Comparator Positive Input 0
CMPSS-4 Low Comparator Positive Input 3
CMPSS-4 Low Comparator Negative Input 0
Analog Pin Used For Digital Input 225
ADC-A Input 5
23
27
23
19
A5
C2
ADC-C Input 2
CMP3_HP1
CMP3_HN1
CMP3_LP1
CMP3_LN1
AIO244
CMPSS-3 High Comparator Positive Input 1
CMPSS-3 High Comparator Negative Input 1
CMPSS-3 Low Comparator Positive Input 1
CMPSS-3 Low Comparator Negative Input 1
Analog Pin Used For Digital Input 244
ADC-A Input 6
13
17
10
23
13
9
4
A6
CMP1_HP2
CMP1_LP2
AIO228
CMPSS-1 High Comparator Positive Input 2
CMPSS-1 Low Comparator Positive Input 2
Analog Pin Used For Digital Input 228
ADC-A Input 7
6
6
A7
C3
ADC-C Input 3
CMP4_HN1
CMP4_LP1
CMP4_LP1
CMP4_LN1
AIO245
CMPSS-4 High Comparator Negative Input 1
CMPSS-4 Low Comparator Positive Input 1
CMPSS-4 Low Comparator Positive Input 1
CMPSS-4 Low Comparator Negative Input 1
Analog Pin Used For Digital Input 245
19
19
15
Copyright © 2020, Texas Instruments Incorporated
Terminal Configuration and Functions
13
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Table 4-1. Pin Attributes (continued)
MUX
64
PIN
TYPE
SIGNAL NAME
80 QFP 64 QFP 48 QFP
DESCRIPTION
POSITION QFP-Q
A8
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
ADC-A Input 8
ADC-C Input 11
C11
CMP2_HP4
CMP4_HP4
CMP2_LP4
CMP4_LP4
AIO241
CMPSS-2 High Comparator Positive Input 4
CMPSS-4 High Comparator Positive Input 4
CMPSS-2 Low Comparator Positive Input 4
CMPSS-4 Low Comparator Positive Input 4
Analog Pin Used For Digital Input 241
ADC-A Input 9
20
24
20
16
A9
C8
ADC-C Input 8
CMP2_HP2
CMP4_HP0
CMP2_LP2
CMP4_LP0
AIO227
CMPSS-2 High Comparator Positive Input 2
CMPSS-4 High Comparator Positive Input 0
CMPSS-2 Low Comparator Positive Input 2
CMPSS-4 Low Comparator Positive Input 0
Analog Pin Used For Digital Input 227
ADC-C Input 6
24
28
11
24
20
C6
CMP3_HP0
CMP3_LP0
AIO226
CMPSS-3 High Comparator Positive Input 0
CMPSS-3 Low Comparator Positive Input 0
Analog Pin Used For Digital Input 226
7
7
4
ADC- High Reference. In external reference
mode, externally drive the high reference voltage
onto this pin. In internal reference mode, a
voltage is driven onto this pin by the device. In
either mode, place at least a 2.2-µF capacitor on
this pin. This capacitor should be placed as close
to the device as possible between the VREFHI
and VREFLO pins.
VREFHI
VREFLO
16
17
20
21
16
17
12
13
I
I
ADC- Low Reference
GPIO
GPIO0
0, 4, 8, 12
I/O
O
General-Purpose Input Output 0
ePWM-1 Output A
EPWM1_A
1
6
I2CA_SDA
I/OD
I/O
I
I2C-A Open-Drain Bidirectional Data
SPI-A Slave Transmit Enable (STE)
FSIRX-A Input Clock
SPIA_STE
7
52
63
52
42
FSIRXA_CLK
CLB_OUTPUTXBAR8
HIC_BASESEL1
GPIO1
9
11
O
CLB Output X-BAR Output 8
HIC Base Address Range Select 1
General-Purpose Input Output 1
ePWM-1 Output B
15
I
0, 4, 8, 12
I/O
O
EPWM1_B
1
6
I2CA_SCL
I/OD
I/O
O
I2C-A Open-Drain Bidirectional Clock
SPI-A Slave Out, Master In (SOMI)
CLB Output X-BAR Output 7
HIC Address 2
SPIA_SOMI
CLB_OUTPUTXBAR7
HIC_A2
7
51
62
51
41
11
13
14
15
I
FSITXA_TDM_D1
HIC_D10
O
FSITX-A_TDM Data Output 1
HIC Data 10
I/O
14
Terminal Configuration and Functions
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Table 4-1. Pin Attributes (continued)
MUX
64
PIN
TYPE
SIGNAL NAME
80 QFP 64 QFP 48 QFP
DESCRIPTION
POSITION QFP-Q
GPIO2
0, 4, 8, 12
I/O
O
General-Purpose Input Output 2
ePWM-2 Output A
EPWM2_A
OUTPUTXBAR1
PMBUSA_SDA
SPIA_SIMO
SCIA_TX
1
5
6
7
O
Output X-BAR Output 1
PMBus-A Open-Drain Bidirectional Data
SPI-A Slave In, Master Out (SIMO)
SCI-A Transmit Data
I/OD
I/O
O
9
50
61
50
40
FSIRXA_D1
I2CB_SDA
HIC_A1
10
I
FSIRX-A Data Input 1
I2C-B Open-Drain Bidirectional Data
HIC Address 1
11
I/OD
I
13
CANA_TX
14
O
CAN-A Transmit
HIC_D9
15
I/O
I/O
O
HIC Data 9
GPIO3
0, 4, 8, 12
General-Purpose Input Output 3
ePWM-2 Output B
EPWM2_B
OUTPUTXBAR2
PMBUSA_SCL
SPIA_CLK
SCIA_RX
1
2, 5
O
Output X-BAR Output 2
PMBus-A Open-Drain Bidirectional Clock
SPI-A Clock
6
I/OD
I/O
I
7
9
49
60
49
39
SCI-A Receive Data
FSIRXA_D0
I2CB_SCL
10
I
FSIRX-A Data Input 0
I2C-B Open-Drain Bidirectional Clock
HIC Output Enable
11
I/OD
O
HIC_NOE
13
CANA_RX
14
I
CAN-A Receive
HIC_D4
15
I/O
I/O
O
HIC Data 4
GPIO4
0, 4, 8, 12
General-Purpose Input Output 4
ePWM-3 Output A
EPWM3_A
OUTPUTXBAR3
CANA_TX
1
5
O
Output X-BAR Output 3
CAN-A Transmit
6
O
SPIB_CLK
EQEP2_STROBE
FSIRXA_CLK
CLB_OUTPUTXBAR6
HIC_BASESEL2
HIC_NWE
7
I/O
I/O
I
SPI-B Clock
48
59
48
38
9
eQEP-2 Strobe
10
FSIRX-A Input Clock
11
O
CLB Output X-BAR Output 6
HIC Base Address Range Select 2
HIC Data Write Enable
General-Purpose Input Output 5
ePWM-3 Output B
13
I
15
I
GPIO5
0, 4, 8, 12
I/O
O
EPWM3_B
OUTPUTXBAR3
CANA_RX
1
3
O
Output X-BAR Output 3
CAN-A Receive
6
I
SPIA_STE
FSITXA_D1
CLB_OUTPUTXBAR5
HIC_A7
7
I/O
O
SPI-A Slave Transmit Enable (STE)
FSITX-A Data Output 1
CLB Output X-BAR Output 5
HIC Address 7
61
74
61
47
9
10
13
14
15
O
I
HIC_D4
I/O
I/O
HIC Data 4
HIC_D15
HIC Data 15
Copyright © 2020, Texas Instruments Incorporated
Terminal Configuration and Functions
15
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Table 4-1. Pin Attributes (continued)
MUX
64
PIN
TYPE
SIGNAL NAME
GPIO6
80 QFP 64 QFP 48 QFP
DESCRIPTION
POSITION QFP-Q
0, 4, 8, 12
I/O
O
General-Purpose Input Output 6
ePWM-4 Output A
EPWM4_A
1
2
3
5
OUTPUTXBAR4
SYNCOUT
O
Output X-BAR Output 4
External ePWM Synchronization Pulse
eQEP-1 Input A
O
EQEP1_A
I
SPIB_SOMI
FSITXA_D0
FSITXA_D1
HIC_NBE1
7
64
80
64
48
I/O
O
SPI-B Slave Out, Master In (SOMI)
FSITX-A Data Output 0
FSITX-A Data Output 1
HIC Byte Enable 1
9
11
O
13
I
CLB_OUTPUTXBAR8
HIC_D14
14
O
CLB Output X-BAR Output 8
HIC Data 14
15
I/O
I/O
O
GPIO7
0, 4, 8, 12
General-Purpose Input Output 7
ePWM-4 Output B
EPWM4_B
1
OUTPUTXBAR5
EQEP1_B
3
O
Output X-BAR Output 5
eQEP-1 Input B
5
I
SPIB_SIMO
FSITXA_CLK
CLB_OUTPUTXBAR2
HIC_A6
7
57
68
57
43
I/O
O
SPI-B Slave In, Master Out (SIMO)
FSITX-A Output Clock
CLB Output X-BAR Output 2
HIC Address 6
9
10
O
13
I
HIC_D14
15
I/O
I/O
O
HIC Data 14
GPIO8
0, 4, 8, 12
General-Purpose Input Output 8
ePWM-5 Output A
EPWM5_A
1
ADCSOCAO
EQEP1_STROBE
SCIA_TX
3
O
ADC Start of Conversion A for External ADC
eQEP-1 Strobe
5
I/O
O
6
SCI-A Transmit Data
SPIA_SIMO
I2CA_SCL
7
I/O
I/OD
O
SPI-A Slave In, Master Out (SIMO)
I2C-A Open-Drain Bidirectional Clock
FSITX-A Data Output 1
CLB Output X-BAR Output 5
HIC Address 0
47
58
47
9
FSITXA_D1
CLB_OUTPUTXBAR5
HIC_A0
10
11
O
13
I
FSITXA_TDM_CLK
HIC_D8
14
O
FSITX-A_TDM Output Clock
HIC Data 8
15
I/O
I/O
O
GPIO9
0, 4, 8, 12
General-Purpose Input Output 9
ePWM-5 Output B
EPWM5_B
1
3
OUTPUTXBAR6
EQEP1_INDEX
SCIA_RX
O
Output X-BAR Output 6
eQEP-1 Index
5
I/O
I
6
SCI-A Receive Data
SPIA_CLK
7
62
75
62
I/O
O
SPI-A Clock
FSITXA_D0
LINB_RX
10
11
13
14
15
FSITX-A Data Output 0
LIN-B Receive
I
HIC_BASESEL0
I2CB_SCL
I
HIC Base Address Range Select 0
I2C-B Open-Drain Bidirectional Clock
HIC Ready
I/OD
O
HIC_NRDY
16
Terminal Configuration and Functions
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Table 4-1. Pin Attributes (continued)
MUX
64
PIN
TYPE
SIGNAL NAME
80 QFP 64 QFP 48 QFP
DESCRIPTION
POSITION QFP-Q
GPIO10
0, 4, 8, 12
I/O
O
General-Purpose Input Output 10
ePWM-6 Output A
EPWM6_A
ADCSOCBO
EQEP1_A
1
3
5
O
ADC Start of Conversion B for External ADC
eQEP-1 Input A
I
SPIA_SOMI
I2CA_SDA
FSITXA_CLK
LINB_TX
7
I/O
I/OD
O
SPI-A Slave Out, Master In (SOMI)
I2C-A Open-Drain Bidirectional Data
FSITX-A Output Clock
LIN-B Transmit
63
76
63
9
10
11
O
HIC_NWE
FSITXA_TDM_D0
GPIO11
13
I
HIC Data Write Enable
FSITX-A_TDM Data Output 0
General-Purpose Input Output 11
ePWM-6 Output B
14
O
0, 4, 8, 12
I/O
O
EPWM6_B
OUTPUTXBAR7
EQEP1_B
1
3
5
7
O
Output X-BAR Output 7
eQEP-1 Input B
I
SPIA_STE
FSIRXA_D1
LINB_RX
I/O
I
SPI-A Slave Transmit Enable (STE)
FSIRX-A Data Input 1
9
31
37
31
10
I
LIN-B Receive
EQEP2_A
11
I
eQEP-2 Input A
SPIA_SIMO
HIC_D6
13
I/O
I/O
I
SPI-A Slave In, Master Out (SIMO)
HIC Data 6
14
HIC_NBE0
GPIO12
15
HIC Byte Enable 0
0, 4, 8, 12
I/O
O
General-Purpose Input Output 12
ePWM-7 Output A
EPWM7_A
EQEP1_STROBE
1
5
I/O
eQEP-1 Strobe
PMBus-A Control Signal - Slave Input/Master
Output
PMBUSA_CTL
7
I/O
FSIRXA_D0
LINB_TX
9
I
O
FSIRX-A Data Input 0
LIN-B Transmit
36
30
10
SPIA_CLK
CANA_RX
HIC_D13
11
I/O
I
SPI-A Clock
13
CAN-A Receive
14
I/O
O
HIC Data 13
HIC_INT
15
HIC Device Interrupt
General-Purpose Input Output 13
ePWM-7 Output B
eQEP-1 Index
GPIO13
0, 4, 8, 12
I/O
O
EPWM7_B
EQEP1_INDEX
PMBUSA_ALERT
FSIRXA_CLK
LINB_RX
1
5
I/O
I/OD
I
7
PMBus-A Open-Drain Bidirectional Alert
FSIRX-A Input Clock
LIN-B Receive
9
35
29
10
11
13
14
15
I
SPIA_SOMI
CANA_TX
HIC_D11
I/O
O
SPI-A Slave Out, Master In (SOMI)
CAN-A Transmit
I/O
I/O
HIC Data 11
HIC_D5
HIC Data 5
Copyright © 2020, Texas Instruments Incorporated
Terminal Configuration and Functions
17
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Table 4-1. Pin Attributes (continued)
MUX
64
PIN
TYPE
SIGNAL NAME
GPIO14
80 QFP 64 QFP 48 QFP
DESCRIPTION
POSITION QFP-Q
0, 4, 8, 12
I/O
I/OD
O
General-Purpose Input Output 14
I2C-B Open-Drain Bidirectional Data
Output X-BAR Output 3
I2CB_SDA
5
OUTPUTXBAR3
PMBUSA_SDA
SPIB_CLK
6
7
I/OD
I/O
I
PMBus-A Open-Drain Bidirectional Data
SPI-B Clock
9
79
EQEP2_A
10
eQEP-2 Input A
LINB_TX
11
O
LIN-B Transmit
EPWM3_A
13
O
ePWM-3 Output A
CLB_OUTPUTXBAR7
HIC_D15
14
O
CLB Output X-BAR Output 7
HIC Data 15
15
I/O
I/O
I/OD
O
GPIO15
0, 4, 8, 12
General-Purpose Input Output 15
I2C-B Open-Drain Bidirectional Clock
Output X-BAR Output 4
PMBus-A Open-Drain Bidirectional Clock
SPI-B Slave Transmit Enable (STE)
eQEP-2 Input B
I2CB_SCL
5
OUTPUTXBAR4
PMBUSA_SCL
SPIB_STE
6
7
I/OD
I/O
I
9
78
EQEP2_B
10
LINB_RX
11
I
LIN-B Receive
EPWM3_B
13
O
ePWM-3 Output B
CLB_OUTPUTXBAR6
HIC_D12
14
O
CLB Output X-BAR Output 6
HIC Data 12
15
I/O
I/O
I/O
O
GPIO16
0, 4, 8, 12
General-Purpose Input Output 16
SPI-A Slave In, Master Out (SIMO)
Output X-BAR Output 7
ePWM-5 Output A
SPIA_SIMO
OUTPUTXBAR7
EPWM5_A
1
3
5
6
9
O
SCIA_TX
O
SCI-A Transmit Data
EQEP1_STROBE
PMBUSA_SCL
I/O
I/OD
eQEP-1 Strobe
33
39
33
26
10
PMBus-A Open-Drain Bidirectional Clock
External Clock Output. This pin outputs a
divided-down version of a chosen clock signal
from within the device.
XCLKOUT
11
O
EQEP2_B
13
I
I/O
I/O
I/O
I/O
O
eQEP-2 Input B
SPIB_SOMI
HIC_D1
14
SPI-B Slave Out, Master In (SOMI)
HIC Data 1
15
GPIO17
0, 4, 8, 12
General-Purpose Input Output 17
SPI-A Slave Out, Master In (SOMI)
Output X-BAR Output 8
ePWM-5 Output B
SPIA_SOMI
OUTPUTXBAR8
EPWM5_B
SCIA_RX
1
3
5
O
6
34
40
34
I
SCI-A Receive Data
EQEP1_INDEX
PMBUSA_SDA
CANA_TX
9
I/O
I/OD
O
eQEP-1 Index
10
11
15
PMBus-A Open-Drain Bidirectional Data
CAN-A Transmit
HIC_D2
I/O
HIC Data 2
18
Terminal Configuration and Functions
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Table 4-1. Pin Attributes (continued)
MUX
64
PIN
TYPE
SIGNAL NAME
80 QFP 64 QFP 48 QFP
DESCRIPTION
POSITION QFP-Q
GPIO18_X2
SPIA_CLK
CANA_RX
EPWM6_A
I2CA_SCL
EQEP2_A
0, 4, 8, 12
I/O
I/O
I
General-Purpose Input Output 18_X2
SPI-A Clock
1
3
5
6
9
CAN-A Receive
O
ePWM-6 Output A
I/OD
I
I2C-A Open-Drain Bidirectional Clock
eQEP-2 Input A
PMBus-A Control Signal - Slave Input/Master
Output
PMBUSA_CTL
10
41
I/O
50
41
33
External Clock Output. This pin outputs a
divided-down version of a chosen clock signal
from within the device.
XCLKOUT
11
O
LINB_TX
13
O
O
LIN-B Transmit
FSITXA_TDM_CLK
HIC_INT
14
FSITX-A_TDM Output Clock
HIC Device Interrupt
15
O
X2
ALT
O
Crystal oscillator output.
General-Purpose Input Output 19_X1
SPI-A Slave Transmit Enable (STE)
CAN-A Transmit
GPIO19_X1
SPIA_STE
0, 4, 8, 12
I/O
I/O
O
1
3
CANA_TX
EPWM6_B
5
O
ePWM-6 Output B
I2CA_SDA
6
I/OD
I
I2C-A Open-Drain Bidirectional Data
eQEP-2 Input B
EQEP2_B
9
PMBUSA_ALERT
CLB_OUTPUTXBAR1
LINB_RX
10
I/OD
O
PMBus-A Open-Drain Bidirectional Alert
CLB Output X-BAR Output 1
LIN-B Receive
11
42
13
51
42
34
I
FSITXA_TDM_D0
HIC_NBE0
14
15
O
FSITX-A_TDM Data Output 0
HIC Byte Enable 0
I
Crystal oscillator input or single-ended clock
input. The device initialization software must
configure this pin before the crystal oscillator is
enabled. To use this oscillator, a quartz crystal
circuit must be connected to X1 and X2. This pin
can also be used to feed a single-ended 3.3-V
level clock.
X1
ALT
I
GPIO22
0, 4, 8, 12
I/O
I/O
I/O
O
General-Purpose Input Output 22
eQEP-1 Strobe
EQEP1_STROBE
SPIB_CLK
LINA_TX
1
6
9
SPI-B Clock
LIN-A Transmit
CLB_OUTPUTXBAR1
LINB_TX
10
11
13
14
15
56
67
56
O
CLB Output X-BAR Output 1
LIN-B Transmit
O
HIC_A5
I
HIC Address 5
EPWM4_A
HIC_D13
O
ePWM-4 Output A
HIC Data 13
I/O
Copyright © 2020, Texas Instruments Incorporated
Terminal Configuration and Functions
19
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Table 4-1. Pin Attributes (continued)
MUX
64
PIN
TYPE
SIGNAL NAME
GPIO23
80 QFP 64 QFP 48 QFP
DESCRIPTION
POSITION QFP-Q
0, 4, 8, 12
I/O
I/O
I/O
I
General-Purpose Input Output 23
eQEP-1 Index
EQEP1_INDEX
SPIB_STE
LINA_RX
1
6
SPI-B Slave Transmit Enable (STE)
LIN-A Receive
9
54
11
65
54
LINB_RX
I
LIN-B Receive
HIC_A3
13
I
HIC Address 3
EPWM4_B
HIC_D11
14
O
ePWM-4 Output B
15
I/O
I/O
O
HIC Data 11
GPIO24
0, 4, 8, 12
General-Purpose Input Output 24
Output X-BAR Output 1
eQEP-2 Input A
OUTPUTXBAR1
EQEP2_A
SPIB_SIMO
LINB_TX
1
2
6
I
I/O
O
SPI-B Slave In, Master Out (SIMO)
LIN-B Transmit
9
35
41
35
27
PMBUSA_SCL
SCIA_TX
10
11
I/OD
O
PMBus-A Open-Drain Bidirectional Clock
SCI-A Transmit Data
Error Status Output. When used, this signal
requires an external pulldown.
ERRORSTS
13
O
HIC_D3
15
I/O
I/O
O
HIC Data 3
GPIO25
0, 4, 8, 12
General-Purpose Input Output 25
Output X-BAR Output 2
eQEP-2 Input B
OUTPUTXBAR2
EQEP2_B
1
2
I
EQEP1_A
5
I
eQEP-1 Input A
SPIB_SOMI
FSITXA_D1
PMBUSA_SDA
SCIA_RX
6
42
43
44
I/O
O
SPI-B Slave Out, Master In (SOMI)
FSITX-A Data Output 1
PMBus-A Open-Drain Bidirectional Data
SCI-A Receive Data
9
10
I/OD
I
11
HIC_BASESEL0
GPIO26
14
I
HIC Base Address Range Select 0
General-Purpose Input Output 26
Output X-BAR Output 3
eQEP-2 Index
0, 4, 8, 12
I/O
O
OUTPUTXBAR3
EQEP2_INDEX
SPIB_CLK
1, 5
2
I/O
I/O
O
6
SPI-B Clock
FSITXA_D0
9
FSITX-A Data Output 0
PMBus-A Control Signal - Slave Input/Master
Output
PMBUSA_CTL
10
I/O
I2CA_SDA
HIC_D0
11
I/OD
I/O
I
I2C-A Open-Drain Bidirectional Data
HIC Data 0
14
HIC_A1
15
HIC Address 1
GPIO27
0, 4, 8, 12
I/O
O
General-Purpose Input Output 27
Output X-BAR Output 4
eQEP-2 Strobe
OUTPUTXBAR4
EQEP2_STROBE
SPIB_STE
FSITXA_CLK
PMBUSA_ALERT
I2CA_SCL
HIC_D1
1, 5
2
I/O
I/O
O
6
SPI-B Slave Transmit Enable (STE)
FSITX-A Output Clock
9
10
11
14
15
I/OD
I/OD
I/O
I
PMBus-A Open-Drain Bidirectional Alert
I2C-A Open-Drain Bidirectional Clock
HIC Data 1
HIC_A4
HIC Address 4
20
Terminal Configuration and Functions
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Table 4-1. Pin Attributes (continued)
MUX
64
PIN
TYPE
SIGNAL NAME
80 QFP 64 QFP 48 QFP
DESCRIPTION
POSITION QFP-Q
GPIO28
0, 4, 8, 12
I/O
I
General-Purpose Input Output 28
SCI-A Receive Data
ePWM-7 Output A
Output X-BAR Output 5
eQEP-1 Input A
SCIA_RX
1
3
5
6
EPWM7_A
OUTPUTXBAR5
EQEP1_A
O
O
I
EQEP2_STROBE
LINA_TX
9
I/O
O
eQEP-2 Strobe
2
4
2
2
10
11
LIN-A Transmit
SPIB_CLK
I/O
SPI-B Clock
Error Status Output. When used, this signal
requires an external pulldown.
ERRORSTS
13
O
I2CB_SDA
HIC_NOE
14
I/OD
O
I2C-B Open-Drain Bidirectional Data
HIC Output Enable
15
GPIO29
0, 4, 8, 12
I/O
O
General-Purpose Input Output 29
SCI-A Transmit Data
SCIA_TX
1
3
5
6
EPWM7_B
OUTPUTXBAR6
EQEP1_B
EQEP2_INDEX
LINA_RX
O
ePWM-7 Output B
O
Output X-BAR Output 6
eQEP-1 Input B
I
9
I/O
I
eQEP-2 Index
1
3
1
1
10
11
LIN-A Receive
SPIB_STE
I/O
SPI-B Slave Transmit Enable (STE)
Error Status Output. When used, this signal
requires an external pulldown.
ERRORSTS
13
O
I2CB_SCL
14
I/OD
I
I2C-B Open-Drain Bidirectional Clock
HIC Chip Select
HIC_NCS
15
GPIO30
0, 4, 8, 12
I/O
I
General-Purpose Input Output 30
CAN-A Receive
CANA_RX
1
SPIB_SIMO
OUTPUTXBAR7
EQEP1_STROBE
FSIRXA_CLK
EPWM1_A
HIC_D8
3
I/O
O
SPI-B Slave In, Master Out (SIMO)
Output X-BAR Output 7
eQEP-1 Strobe
5
1
6
I/O
I
9
FSIRX-A Input Clock
ePWM-1 Output A
11
O
14
I/O
I/O
O
HIC Data 8
GPIO31
0, 4, 8, 12
General-Purpose Input Output 31
CAN-A Transmit
CANA_TX
1
3
SPIB_SOMI
OUTPUTXBAR8
EQEP1_INDEX
FSIRXA_D1
EPWM1_B
HIC_D10
I/O
O
SPI-B Slave Out, Master In (SOMI)
Output X-BAR Output 8
eQEP-1 Index
5
2
6
I/O
I
9
FSIRX-A Data Input 1
ePWM-1 Output B
11
14
O
I/O
HIC Data 10
Copyright © 2020, Texas Instruments Incorporated
Terminal Configuration and Functions
21
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Table 4-1. Pin Attributes (continued)
MUX
64
PIN
TYPE
SIGNAL NAME
GPIO32
80 QFP 64 QFP 48 QFP
DESCRIPTION
POSITION QFP-Q
0, 4, 8, 12
I/O
I/OD
I/O
O
General-Purpose Input Output 32
I2C-A Open-Drain Bidirectional Data
SPI-B Clock
I2CA_SDA
SPIB_CLK
LINA_TX
1
3
6
LIN-A Transmit
40
49
40
32
FSIRXA_D0
CANA_TX
ADCSOCBO
HIC_INT
9
I
FSIRX-A Data Input 0
CAN-A Transmit
10
O
13
O
ADC Start of Conversion B for External ADC
HIC Device Interrupt
15
O
GPIO33
0, 4, 8, 12
I/O
I/OD
I/O
O
General-Purpose Input Output 33
I2C-A Open-Drain Bidirectional Clock
SPI-B Slave Transmit Enable (STE)
Output X-BAR Output 4
I2CA_SCL
SPIB_STE
OUTPUTXBAR4
LINA_RX
1
3
5
6
I
LIN-A Receive
32
38
32
25
FSIRXA_CLK
CANA_RX
EQEP2_B
ADCSOCAO
HIC_D0
9
I
FSIRX-A Input Clock
10
I
CAN-A Receive
11
I
eQEP-2 Input B
13
O
ADC Start of Conversion A for External ADC
HIC Data 0
15
I/O
I/O
O
GPIO34
0, 4, 8, 12
General-Purpose Input Output 34
Output X-BAR Output 1
OUTPUTXBAR1
PMBUSA_SDA
HIC_NBE1
I2CB_SDA
HIC_D9
1
6
I/OD
I
PMBus-A Open-Drain Bidirectional Data
HIC Byte Enable 1
77
13
14
I/OD
I/O
I/O
I
I2C-B Open-Drain Bidirectional Data
HIC Data 9
15
GPIO35
0, 4, 8, 12
General-Purpose Input Output 35
SCI-A Receive Data
SCIA_RX
1
3
5
6
7
I2CA_SDA
CANA_RX
PMBUSA_SCL
LINA_RX
I/OD
I
I2C-A Open-Drain Bidirectional Data
CAN-A Receive
I/OD
I
PMBus-A Open-Drain Bidirectional Clock
LIN-A Receive
EQEP1_A
9
I
eQEP-1 Input A
39
48
39
31
PMBus-A Control Signal - Slave Input/Master
Output
PMBUSA_CTL
HIC_NWE
10
14
I/O
I
HIC Data Write Enable
JTAG Test Data Input (TDI) - TDI is the default
mux selection for the pin. The internal pullup is
disabled by default. The internal pullup should be
enabled or an external pullup added on the board
if this pin is used as JTAG TDI to avoid a floating
input.
TDI
15
I
22
Terminal Configuration and Functions
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Table 4-1. Pin Attributes (continued)
MUX
64
PIN
TYPE
SIGNAL NAME
80 QFP 64 QFP 48 QFP
DESCRIPTION
POSITION QFP-Q
GPIO37
0, 4, 8, 12
I/O
O
General-Purpose Input Output 37
Output X-BAR Output 2
I2C-A Open-Drain Bidirectional Clock
SCI-A Transmit Data
OUTPUTXBAR2
I2CA_SCL
SCIA_TX
1
3
5
6
7
I/OD
O
CANA_TX
O
CAN-A Transmit
LINA_TX
O
LIN-A Transmit
EQEP1_B
9
I
eQEP-1 Input B
37
10
46
37
29
PMBUSA_ALERT
HIC_NRDY
I/OD
O
PMBus-A Open-Drain Bidirectional Alert
HIC Ready
14
15
JTAG Test Data Output (TDO) - TDO is the
default mux selection for the pin. The internal
pullup is disabled by default. The TDO function
will tristate when there is no JTAG activity,
leaving this pin floating; the internal pullup should
be enabled or an external pullup added on the
board to avoid a floating GPIO input.
TDO
O
GPIO39
0, 4, 8, 12
I/O
I
General-Purpose Input Output 39
FSIRX-A Input Clock
FSIRXA_CLK
EQEP2_INDEX
CLB_OUTPUTXBAR2
SYNCOUT
EQEP1_INDEX
HIC_D7
7
9
I/O
O
eQEP-2 Index
11
46
56
46
CLB Output X-BAR Output 2
External ePWM Synchronization Pulse
eQEP-1 Index
13
O
14
I/O
I/O
I/O
I/O
O
15
HIC Data 7
GPIO40
0, 4, 8, 12
General-Purpose Input Output 40
SPI-B Slave In, Master Out (SIMO)
ePWM-2 Output B
SPIB_SIMO
EPWM2_B
PMBUSA_SDA
FSIRXA_D0
EQEP1_A
1
5
6
I/OD
I
PMBus-A Open-Drain Bidirectional Data
FSIRX-A Data Input 0
eQEP-1 Input A
7
53
64
53
10
I
LINB_TX
11
O
LIN-B Transmit
HIC_NBE1
HIC_D5
14
I
HIC Byte Enable 1
15
I/O
I/O
O
HIC Data 5
GPIO41
0, 4, 8, 12
General-Purpose Input Output 41
ePWM-2 Output A
EPWM2_A
PMBUSA_SCL
FSIRXA_D1
EQEP1_B
5
6
I/OD
I
PMBus-A Open-Drain Bidirectional Clock
FSIRX-A Data Input 1
eQEP-1 Input B
7
10
11
13
14
15
55
66
55
I
LINB_RX
I
LIN-B Receive
HIC_A4
I
HIC Address 4
SPIB_SOMI
HIC_D12
I/O
I/O
SPI-B Slave Out, Master In (SOMI)
HIC Data 12
Copyright © 2020, Texas Instruments Incorporated
Terminal Configuration and Functions
23
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Table 4-1. Pin Attributes (continued)
MUX
64
PIN
TYPE
SIGNAL NAME
GPIO42
80 QFP 64 QFP 48 QFP
DESCRIPTION
POSITION QFP-Q
0, 4, 8, 12
I/O
I
General-Purpose Input Output 42
LIN-A Receive
LINA_RX
2
3
OUTPUTXBAR5
O
Output X-BAR Output 5
PMBus-A Control Signal - Slave Input/Master
Output
PMBUSA_CTL
5
I/O
57
I2CA_SDA
6
I/OD
I/O
O
I2C-A Open-Drain Bidirectional Data
eQEP-1 Strobe
EQEP1_STROBE
CLB_OUTPUTXBAR3
HIC_D2
10
11
CLB Output X-BAR Output 3
HIC Data 2
14
I/O
I
HIC_A6
15
HIC Address 6
GPIO43
0, 4, 8, 12
I/O
O
General-Purpose Input Output 43
Output X-BAR Output 6
PMBus-A Open-Drain Bidirectional Alert
I2C-A Open-Drain Bidirectional Clock
eQEP-1 Index
OUTPUTXBAR6
PMBUSA_ALERT
I2CA_SCL
3
5
I/OD
I/OD
I/O
O
6
54
EQEP1_INDEX
CLB_OUTPUTXBAR4
HIC_D3
10
11
CLB Output X-BAR Output 4
HIC Data 3
14
I/O
I
HIC_A7
15
HIC Address 7
GPIO44
0, 4, 8, 12
I/O
O
General-Purpose Input Output 44
Output X-BAR Output 7
eQEP-1 Input A
OUTPUTXBAR7
EQEP1_A
3
5
I
FSITXA_CLK
CLB_OUTPUTXBAR3
HIC_D7
7
69
O
FSITX-A Output Clock
CLB Output X-BAR Output 3
HIC Data 7
10
O
13
I/O
I/O
I/O
O
HIC_D5
15
HIC Data 5
GPIO45
0, 4, 8, 12
General-Purpose Input Output 45
Output X-BAR Output 8
FSITX-A Data Output 0
CLB Output X-BAR Output 4
HIC Data 6
OUTPUTXBAR8
FSITXA_D0
CLB_OUTPUTXBAR4
HIC_D6
3
7
73
O
10
15
O
I/O
I/O
O
GPIO46
0, 4, 8, 12
3
General-Purpose Input Output 46
LIN-A Transmit
LINA_TX
6
FSITXA_D1
HIC_NWE
7
O
FSITX-A Data Output 1
HIC Data Write Enable
General-Purpose Input Output 61
General-Purpose Input Output 62
General-Purpose Input Output 63
15
I
GPIO61
0, 4, 8, 12
0, 4, 8, 12
0, 4, 8, 12
I/O
I/O
I/O
GPIO62
GPIO63
TEST, JTAG, AND RESET
Flash test pin 1. Reserved for TI. Must be left
unconnected.
FLT1
30
34
24
I/O
Flash test pin 2. Reserved for TI. Must be left
unconnected.
FLT2
TCK
29
36
33
45
23
28
I/O
I
36
JTAG test clock with internal pullup.
24
Terminal Configuration and Functions
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Table 4-1. Pin Attributes (continued)
MUX
64
PIN
TYPE
SIGNAL NAME
80 QFP 64 QFP 48 QFP
DESCRIPTION
POSITION QFP-Q
JTAG test-mode select (TMS) with internal
pullup. This serial control input is clocked into the
TAP controller on the rising edge of TCK. This
device does not have a TRSTn pin. An external
pullup resistor (recommended 2.2 kΩ) on the
TMS pin to VDDIO should be placed on the
board to keep JTAG in reset during normal
operation.
TMS
38
47
38
30
I/O
Device Reset (in) and Watchdog Reset (out).
During a power-on condition, this pin is driven
low by the device. An external circuit may also
drive this pin to assert a device reset. This pin is
also driven low by the MCU when a watchdog
reset occurs. During watchdog reset, the XRSn
pin is driven low for the watchdog reset duration
of 512 OSCCLK cycles. A resistor between 2.2
kΩ and 10 kΩ should be placed between XRSn
and VDDIO. If a capacitor is placed between
XRSn and VSS for noise filtering, it should be
100 nF or smaller. These values will allow the
watchdog to properly drive the XRSn pin to VOL
within 512 OSCCLK cycles when the watchdog
reset is asserted. This pin is an open-drain output
with an internal pullup. If this pin is driven by an
external device, it should be done using an open-
drain device.
XRSn
3
5
3
3
I/OD
POWER AND GROUND
1.2-V Digital Logic Power Pins. TI recommends
placing a decoupling capacitor near each VDD
pin with a total capacitance of approximately 22
µF.
4, 27,
44, 59
8, 31,
53, 71
4, 27,
44, 59
VDD
36, 45
3.3-V Analog Power Pins. Place a minimum 2.2-
µF decoupling capacitor on each pin.
VDDA
22
26
22
18
28, 43,
60
7, 32,
52, 72
28, 43,
60
3.3-V Digital I/O Power Pins. Place a minimum
0.1-µF decoupling capacitor on each pin.
VDDIO
35, 46
5, 26,
45, 58
9, 30,
55, 70
5, 26,
45, 58
22, 37,
44
VSS
Digital Ground
Analog Ground
VSSA
21
25
21
17
Copyright © 2020, Texas Instruments Incorporated
Terminal Configuration and Functions
25
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
4.3 Signal Descriptions
4.3.1 Analog Signals
Table 4-2. Analog Signals
PIN
TYPE
64
QFP-Q
SIGNAL NAME
DESCRIPTION
GPIO
80 QFP 64 QFP 48 QFP
A0
ADC-A Input 0
ADC-A Input 1
ADC-A Input 2
ADC-A Input 3
ADC-A Input 4
ADC-A Input 5
ADC-A Input 6
ADC-A Input 7
ADC-A Input 8
ADC-A Input 9
ADC-A Input 10
ADC-A Input 11
ADC-A Input 12
ADC-A Input 14
ADC-A Input 15
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
15
14
9
19
18
13
12
27
17
10
23
24
28
29
16
22
15
14
13
27
11
28
10
29
19
18
14
16
22
15
24
12
17
23
16
22
17
23
15
12
11
14
28
13
29
24
15
14
9
11
10
6
A1
A2
A3
8
8
5
A4
23
13
6
23
13
6
19
9
A5
A6
4
A7
19
20
24
25
12
18
11
10
9
19
20
24
25
12
18
11
10
9
15
16
20
21
8
A8
A9
A10
A11
A12
14
A14
A15
7
6
AIO224
AIO225
AIO226
AIO227
AIO228
AIO230
AIO231
AIO232
AIO233
AIO237
AIO238
AIO239
AIO241
AIO242
AIO244
AIO245
C0
Analog Pin Used For Digital Input 224
Analog Pin Used For Digital Input 225
Analog Pin Used For Digital Input 226
Analog Pin Used For Digital Input 227
Analog Pin Used For Digital Input 228
Analog Pin Used For Digital Input 230
Analog Pin Used For Digital Input 231
Analog Pin Used For Digital Input 232
Analog Pin Used For Digital Input 233
Analog Pin Used For Digital Input 237
Analog Pin Used For Digital Input 238
Analog Pin Used For Digital Input 239
Analog Pin Used For Digital Input 241
Analog Pin Used For Digital Input 242
Analog Pin Used For Digital Input 244
Analog Pin Used For Digital Input 245
ADC-C Input 0
23
7
23
7
19
4
24
6
24
6
20
4
25
15
14
10
12
18
11
20
8
25
15
14
10
12
18
11
20
8
21
11
10
7
8
14
16
5
13
19
12
18
13
19
11
8
13
19
12
18
13
19
11
8
9
15
8
C1
ADC-C Input 1
14
9
C2
ADC-C Input 2
C3
ADC-C Input 3
15
C4
ADC-C Input 4
C5
ADC-C Input 5
5
4
C6
ADC-C Input 6
7
7
C7
ADC-C Input 7
10
24
9
10
24
9
7
C8
ADC-C Input 8
20
6
C9
ADC-C Input 9
C10
ADC-C Input 10
25
20
25
20
21
16
C11
ADC-C Input 11
26
Terminal Configuration and Functions
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Table 4-2. Analog Signals (continued)
PIN
TYPE
64
QFP-Q
SIGNAL NAME
DESCRIPTION
GPIO
80 QFP 64 QFP 48 QFP
C14
ADC-C Input 14
ADC-C Input 15
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
23
15
10
12
9
27
19
14
16
13
16
10
14
18
14
16
13
16
10
14
18
29
22
27
22
28
29
24
29
22
27
22
28
29
24
12
17
11
17
19
12
15
12
17
11
17
19
12
15
27
23
28
23
15
10
12
9
19
11
7
C15
CMP1_HN0
CMP1_HN1
CMP1_HP0
CMP1_HP1
CMP1_HP2
CMP1_HP3
CMP1_HP4
CMP1_LN0
CMP1_LN1
CMP1_LP0
CMP1_LP1
CMP1_LP2
CMP1_LP3
CMP1_LP4
CMP2_HN0
CMP2_HN1
CMP2_HP0
CMP2_HP1
CMP2_HP2
CMP2_HP3
CMP2_HP4
CMP2_LN0
CMP2_LN1
CMP2_LP0
CMP2_LP1
CMP2_LP2
CMP2_LP3
CMP2_LP4
CMP3_HN0
CMP3_HN1
CMP3_HP0
CMP3_HP1
CMP3_HP2
CMP3_HP3
CMP3_HP4
CMP3_LN0
CMP3_LN1
CMP3_LP0
CMP3_LP1
CMP3_LP2
CMP3_LP3
CMP3_LP4
CMP4_HN0
CMP4_HN1
CMP4_HP0
CMPSS-1 High Comparator Negative Input 0
CMPSS-1 High Comparator Negative Input 1
CMPSS-1 High Comparator Positive Input 0
CMPSS-1 High Comparator Positive Input 1
CMPSS-1 High Comparator Positive Input 2
CMPSS-1 High Comparator Positive Input 3
CMPSS-1 High Comparator Positive Input 4
CMPSS-1 Low Comparator Negative Input 0
CMPSS-1 Low Comparator Negative Input 1
CMPSS-1 Low Comparator Positive Input 0
CMPSS-1 Low Comparator Positive Input 1
CMPSS-1 Low Comparator Positive Input 2
CMPSS-1 Low Comparator Positive Input 3
CMPSS-1 Low Comparator Positive Input 4
CMPSS-2 High Comparator Negative Input 0
CMPSS-2 High Comparator Negative Input 1
CMPSS-2 High Comparator Positive Input 0
CMPSS-2 High Comparator Positive Input 1
CMPSS-2 High Comparator Positive Input 2
CMPSS-2 High Comparator Positive Input 3
CMPSS-2 High Comparator Positive Input 4
CMPSS-2 Low Comparator Negative Input 0
CMPSS-2 Low Comparator Negative Input 1
CMPSS-2 Low Comparator Positive Input 0
CMPSS-2 Low Comparator Positive Input 1
CMPSS-2 Low Comparator Positive Input 2
CMPSS-2 Low Comparator Positive Input 3
CMPSS-2 Low Comparator Positive Input 4
CMPSS-3 High Comparator Negative Input 0
CMPSS-3 High Comparator Negative Input 1
CMPSS-3 High Comparator Positive Input 0
CMPSS-3 High Comparator Positive Input 1
CMPSS-3 High Comparator Positive Input 2
CMPSS-3 High Comparator Positive Input 3
CMPSS-3 High Comparator Positive Input 4
CMPSS-3 Low Comparator Negative Input 0
CMPSS-3 Low Comparator Negative Input 1
CMPSS-3 Low Comparator Positive Input 0
CMPSS-3 Low Comparator Positive Input 1
CMPSS-3 Low Comparator Positive Input 2
CMPSS-3 Low Comparator Positive Input 3
CMPSS-3 Low Comparator Positive Input 4
CMPSS-4 High Comparator Negative Input 0
CMPSS-4 High Comparator Negative Input 1
CMPSS-4 High Comparator Positive Input 0
8
6
12
6
12
6
8
4
10
14
10
12
9
10
14
10
12
9
7
10
7
8
6
12
6
12
6
8
4
10
14
25
18
23
18
24
25
20
25
18
23
18
24
25
20
8
10
14
25
18
23
18
24
25
20
25
18
23
18
24
25
20
8
7
10
21
14
19
14
20
21
16
21
14
19
14
20
21
16
5
13
7
13
7
9
4
13
15
8
13
15
8
9
11
5
11
8
11
8
5
9
13
7
13
7
4
13
15
8
13
15
8
9
11
5
11
23
19
24
11
23
19
24
19
15
20
Copyright © 2020, Texas Instruments Incorporated
Terminal Configuration and Functions
27
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Table 4-2. Analog Signals (continued)
PIN
TYPE
64
QFP-Q
SIGNAL NAME
CMP4_HP2
DESCRIPTION
GPIO
80 QFP 64 QFP 48 QFP
CMPSS-4 High Comparator Positive Input 2
CMPSS-4 High Comparator Positive Input 3
CMPSS-4 High Comparator Positive Input 4
CMPSS-4 Low Comparator Negative Input 0
CMPSS-4 Low Comparator Negative Input 1
CMPSS-4 Low Comparator Positive Input 0
CMPSS-4 Low Comparator Positive Input 1
CMPSS-4 Low Comparator Positive Input 2
CMPSS-4 Low Comparator Positive Input 3
CMPSS-4 Low Comparator Positive Input 4
I
I
I
I
I
I
I
I
I
I
18
23
20
23
19
24
19
18
23
20
22
27
24
27
23
28
23
22
27
24
18
23
20
23
19
24
19
18
23
20
14
19
16
19
15
20
15
14
19
16
CMP4_HP3
CMP4_HP4
CMP4_LN0
CMP4_LN1
CMP4_LP0
CMP4_LP1
CMP4_LP2
CMP4_LP3
CMP4_LP4
Optional external reference voltage for on-
chip CMPSS DACs. There is an internal
capacitor to VSSA on this pin whether used
for ADC input or CMPSS DAC reference
which cannot be disabled. If this pin is being
used as a reference for the CMPSS DACs,
place at least a 1-μF capacitor on this pin.
VDAC
I
8
12
8
5
ADC- High Reference. In external reference
mode, externally drive the high reference
voltage onto this pin. In internal reference
mode, a voltage is driven onto this pin by the
device. In either mode, place at least a 2.2-µF
capacitor on this pin. This capacitor should be
placed as close to the device as possible
between the VREFHI and VREFLO pins.
VREFHI
VREFLO
I
I
16
17
20
21
16
17
12
13
ADC- Low Reference
28
Terminal Configuration and Functions
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
4.3.2 Digital Signals
Table 4-3. Digital Signals
PIN
TYPE
64
QFP-Q
SIGNAL NAME
DESCRIPTION
GPIO
80 QFP 64 QFP 48 QFP
ADCSOCAO
ADCSOCBO
ADC Start of Conversion A for External ADC
ADC Start of Conversion B for External ADC
O
O
33, 8
32, 47
40, 63
38, 58
49, 76
32, 47
40, 63
25
32
10, 32
12, 18,
3, 30,
33, 35,
5
1, 36,
38, 48,
50, 60,
74
32, 39,
41, 49,
61
30, 32, 25, 31,
39, 41, 33, 39,
CANA_RX
CANA_TX
CAN-A Receive
CAN-A Transmit
I
49, 61
47
13, 17,
19, 2,
31, 32,
37, 4
2, 35,
40, 46, 37, 40,
49, 51, 42, 48,
29, 34,
34, 37,
40, 42,
48, 50
29, 32,
34, 38,
40
O
59, 61
51, 67
56, 68
57, 69
54, 73
58, 74
59, 78
62, 79
63, 80
1, 63
50
CLB_OUTPUTXBAR1
CLB_OUTPUTXBAR2
CLB_OUTPUTXBAR3
CLB_OUTPUTXBAR4
CLB_OUTPUTXBAR5
CLB_OUTPUTXBAR6
CLB_OUTPUTXBAR7
CLB_OUTPUTXBAR8
EPWM1_A
CLB Output X-BAR Output 1
CLB Output X-BAR Output 2
CLB Output X-BAR Output 3
CLB Output X-BAR Output 4
CLB Output X-BAR Output 5
CLB Output X-BAR Output 6
CLB Output X-BAR Output 7
CLB Output X-BAR Output 8
ePWM-1 Output A
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
19, 22
39, 7
42, 44
43, 45
5, 8
42, 56
46, 57
42, 56
46, 57
34
43
47, 61
48
47, 61
48
47
38
15, 4
1, 14
0, 6
51
51
41
52, 64
52
52, 64
52
42, 48
42
0, 30
1, 31
2, 41
3, 40
14, 4
15, 5
22, 6
23, 7
16, 8
17, 9
10, 18
11, 19
12, 28
13, 29
EPWM1_B
ePWM-1 Output B
51
2, 62
51
41
EPWM2_A
ePWM-2 Output A
50, 55
49, 53
48
61, 66
60, 64
59, 79
74, 78
67, 80
65, 68
39, 58
40, 75
50, 76
37, 51
36, 4
50, 55
49, 53
48
40
EPWM2_B
ePWM-2 Output B
39
EPWM3_A
ePWM-3 Output A
38
EPWM3_B
ePWM-3 Output B
61
61
47
EPWM4_A
ePWM-4 Output A
56, 64
54, 57
33, 47
34, 62
41, 63
31, 42
2
56, 64
54, 57
33, 47
34, 62
41, 63
31, 42
2, 30
1, 29
48
EPWM4_B
ePWM-4 Output B
43
EPWM5_A
ePWM-5 Output A
26
EPWM5_B
ePWM-5 Output B
EPWM6_A
ePWM-6 Output A
33
34
2
EPWM6_B
ePWM-6 Output B
EPWM7_A
ePWM-7 Output A
EPWM7_B
ePWM-7 Output B
1
3, 35
1
10, 25,
28, 35,
40, 44,
6
4, 42,
48, 64,
69, 76,
80
2, 39,
53, 63,
64
2, 39,
53, 63,
64
2, 31,
48
EQEP1_A
eQEP-1 Input A
eQEP-1 Input B
eQEP-1 Index
I
I
11, 29,
1, 31,
3, 37,
1, 31,
1, 29,
43
EQEP1_B
37, 41, 37, 55, 46, 66, 37, 55,
7
57
68
57
13, 17,
23, 31, 34, 46, 40, 54,
39, 43, 54, 62 56, 65,
2, 35,
29, 34,
46, 54,
62
EQEP1_INDEX
I/O
9
75
12, 16,
22, 30,
42, 8
1, 36,
39, 57,
58, 67
33, 47,
56
30, 33,
47, 56
EQEP1_STROBE
EQEP2_A
eQEP-1 Strobe
eQEP-2 Input A
eQEP-2 Input B
I/O
26
11, 14, 31, 35, 37, 41, 31, 35,
18, 24
I
I
27, 33
41
50, 79
41
15, 16,
19, 25,
33
38, 39,
42, 51,
78
32, 33,
42
32, 33, 25, 26,
42 34
EQEP2_B
Copyright © 2020, Texas Instruments Incorporated
Terminal Configuration and Functions
29
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Table 4-3. Digital Signals (continued)
PIN
TYPE
64
QFP-Q
SIGNAL NAME
EQEP2_INDEX
DESCRIPTION
GPIO
80 QFP 64 QFP 48 QFP
26, 29,
39
3, 43,
eQEP-2 Index
eQEP-2 Strobe
I/O
1, 46
2, 48
1, 46
2, 48
1
56
27, 28,
4
4, 44,
59
EQEP2_STROBE
ERRORSTS
I/O
O
2, 38
Error Status Output. When used, this signal
requires an external pulldown.
24, 28,
29
1, 2, 35 3, 4, 41 1, 2, 35 1, 2, 27
0, 13,
30, 33,
39, 4
1, 35,
38, 56, 46, 48,
59, 63 52
29, 32,
32, 46,
48, 52
25, 38,
42
FSIRXA_CLK
FSIRX-A Input Clock
I
12, 3,
32, 40
40, 49, 36, 49, 30, 40,
FSIRXA_D0
FSIRXA_D1
FSITXA_CLK
FSITXA_D0
FSIRX-A Data Input 0
FSIRX-A Data Input 1
FSITX-A Output Clock
FSITX-A Data Output 0
I
32, 39
40
53
60, 64
49, 53
11, 2,
31, 41
31, 50,
55
2, 37,
61, 66
31, 50,
55
I
10, 27,
44, 7
44, 68,
69, 76
O
O
57, 63
62, 64
57, 63
62, 64
43
26, 45,
6, 9
43, 73,
75, 80
48
42, 58,
6, 74,
80
25, 46, 47, 61,
47, 61,
64
FSITXA_D1
FSITX-A Data Output 1
O
47, 48
5, 6, 8
64
FSITXA_TDM_CLK
FSITXA_TDM_D0
FSITXA_TDM_D1
GPIO0
FSITX-A_TDM Output Clock
O
18, 8
10, 19
1
41, 47
42, 63
51
50, 58
51, 76
62
63
62
61
60
59
74
80
68
58
75
76
37
36
35
79
78
39
40
50
51
67
65
41
42
43
44
4
41, 47
42, 63
51
33
34
41
42
41
40
39
38
47
48
43
FSITX-A_TDM Data Output 0
O
FSITX-A_TDM Data Output 1
O
General-Purpose Input Output 0
General-Purpose Input Output 1
General-Purpose Input Output 2
General-Purpose Input Output 3
General-Purpose Input Output 4
General-Purpose Input Output 5
General-Purpose Input Output 6
General-Purpose Input Output 7
General-Purpose Input Output 8
General-Purpose Input Output 9
General-Purpose Input Output 10
General-Purpose Input Output 11
General-Purpose Input Output 12
General-Purpose Input Output 13
General-Purpose Input Output 14
General-Purpose Input Output 15
General-Purpose Input Output 16
General-Purpose Input Output 17
General-Purpose Input Output 18_X2
General-Purpose Input Output 19_X1
General-Purpose Input Output 22
General-Purpose Input Output 23
General-Purpose Input Output 24
General-Purpose Input Output 25
General-Purpose Input Output 26
General-Purpose Input Output 27
General-Purpose Input Output 28
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
52
52
GPIO1
1
51
51
GPIO2
2
50
50
GPIO3
3
49
49
GPIO4
4
48
48
GPIO5
5
61
61
GPIO6
6
64
64
GPIO7
7
57
57
GPIO8
8
47
47
GPIO9
9
62
62
GPIO10
10
11
12
13
14
15
16
17
18
19
22
23
24
25
26
27
28
63
63
GPIO11
31
31
GPIO12
30
GPIO13
29
GPIO14
GPIO15
GPIO16
33
34
41
42
56
54
35
33
34
41
42
56
54
35
26
GPIO17
GPIO18_X2
GPIO19_X1
GPIO22
33
34
GPIO23
GPIO24
27
GPIO25
GPIO26
GPIO27
GPIO28
2
2
2
30
Terminal Configuration and Functions
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Table 4-3. Digital Signals (continued)
PIN
TYPE
64
QFP-Q
SIGNAL NAME
DESCRIPTION
GPIO
80 QFP 64 QFP 48 QFP
GPIO29
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
GPIO35
GPIO37
GPIO39
GPIO40
GPIO41
GPIO42
GPIO43
GPIO44
GPIO45
GPIO46
GPIO61
GPIO62
GPIO63
HIC_A0
General-Purpose Input Output 29
General-Purpose Input Output 30
General-Purpose Input Output 31
General-Purpose Input Output 32
General-Purpose Input Output 33
General-Purpose Input Output 34
General-Purpose Input Output 35
General-Purpose Input Output 37
General-Purpose Input Output 39
General-Purpose Input Output 40
General-Purpose Input Output 41
General-Purpose Input Output 42
General-Purpose Input Output 43
General-Purpose Input Output 44
General-Purpose Input Output 45
General-Purpose Input Output 46
General-Purpose Input Output 61
General-Purpose Input Output 62
General-Purpose Input Output 63
HIC Address 0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
29
30
1
3
1
1
1
31
2
32
40
32
49
38
77
48
46
56
64
66
57
54
69
73
6
40
32
32
25
33
34
35
39
37
46
53
55
39
37
46
53
55
31
29
37
39
40
41
42
43
44
45
46
61
62
63
8
47
50
58
47
50
HIC_A1
HIC Address 1
I
2, 26
1
43, 61
62
40
41
HIC_A2
HIC Address 2
I
51
51
HIC_A3
HIC Address 3
I
23
54
65
54
HIC_A4
HIC Address 4
I
27, 41
22
55
44, 66
67
55
HIC_A5
HIC Address 5
I
56
56
HIC_A6
HIC Address 6
I
42, 7
43, 5
25, 9
0
57
57, 68
54, 74
42, 75
63
57
43
47
HIC_A7
HIC Address 7
I
61
61
HIC_BASESEL0
HIC_BASESEL1
HIC_BASESEL2
HIC_D0
HIC_D1
HIC_D2
HIC_D3
HIC_D4
HIC Base Address Range Select 0
HIC Base Address Range Select 1
HIC Base Address Range Select 2
HIC Data 0
I
62
62
I
52
52
42
38
25
26
I
4
48
59
48
I/O
I/O
I/O
I/O
I/O
26, 33
16, 27
17, 42
24, 43
3, 5
32
38, 43
39, 44
40, 57
41, 54
60, 74
32
HIC Data 1
33
33
HIC Data 2
34
34
HIC Data 3
35
35
27
HIC Data 4
49, 61
49, 61
39, 47
13, 40,
44
35, 64,
69
HIC_D5
HIC Data 5
I/O
53
29, 53
HIC_D6
HIC_D7
HIC_D8
HIC_D9
HIC_D10
HIC_D11
HIC_D12
HIC_D13
HIC_D14
HIC_D15
HIC Data 6
HIC Data 7
HIC Data 8
HIC Data 9
HIC Data 10
HIC Data 11
HIC Data 12
HIC Data 13
HIC Data 14
HIC Data 15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
11, 45
39, 44
30, 8
2, 34
1, 31
13, 23
15, 41
12, 22
6, 7
31
46
37, 73
56, 69
1, 58
31
46
47
47
50
61, 77
2, 62
50
40
41
51
51
54
35, 65
66, 78
36, 67
68, 80
74, 79
29, 54
55
55
56
30, 56
57, 64
61
57, 64
61
43, 48
47
14, 5
Copyright © 2020, Texas Instruments Incorporated
Terminal Configuration and Functions
31
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Table 4-3. Digital Signals (continued)
PIN
TYPE
64
QFP-Q
SIGNAL NAME
HIC_INT
DESCRIPTION
HIC Device Interrupt
GPIO
80 QFP 64 QFP 48 QFP
12, 18,
32
36, 49, 30, 40,
32, 33
O
I
40, 41
31, 42
53, 64
50
41
HIC_NBE0
HIC_NBE1
HIC Byte Enable 0
HIC Byte Enable 1
11, 19
37, 51
31, 42
34
48
34, 40,
6
64, 77,
80
I
53, 64
HIC_NCS
HIC_NOE
HIC_NRDY
HIC Chip Select
HIC Output Enable
HIC Ready
I
29
1
3
1
1
O
O
28, 3
37, 9
2, 49
37, 62
4, 60
46, 75
2, 49
37, 62
2, 39
29
10, 35, 39, 48, 48, 59, 39, 48,
HIC_NWE
HIC Data Write Enable
I
31, 38
4, 46
63
6, 76
63
1, 18,
27, 33,
37, 43,
8
38, 44,
46, 50,
54, 58,
62
32, 37,
41, 47,
51
32, 37,
41, 47,
51
25, 29,
33, 41
I2CA_SCL
I2C-A Open-Drain Bidirectional Clock
I/OD
0, 10,
19, 26,
32, 35,
42
43, 48,
49, 51,
57, 63,
76
39, 40,
42, 52,
63
39, 40,
42, 52,
63
31, 32,
34, 42
I2CA_SDA
I2C-A Open-Drain Bidirectional Data
I/OD
15, 29,
3, 9
1, 49,
62
3, 60,
75, 78
1, 49,
62
I2CB_SCL
I2CB_SDA
I2C-B Open-Drain Bidirectional Clock
I2C-B Open-Drain Bidirectional Data
I/OD
I/OD
1, 39
2, 40
14, 2,
28, 34
4, 61,
77, 79
2, 50
2, 50
23, 29,
33, 35,
42
3, 38,
48, 57,
65
1, 32,
39, 54
1, 32,
39, 54
1, 25,
31
LINA_RX
LINA_TX
LIN-A Receive
LIN-A Transmit
I
22, 28,
32, 37,
46
4, 46,
49, 6,
67
2, 37,
40, 56
2, 37,
40, 56
2, 29,
32
O
11, 13,
15, 19,
23, 41,
9
35, 37,
51, 65,
66, 75,
78
31, 42,
54, 55,
62
29, 31,
42, 54,
55, 62
LINB_RX
LINB_TX
LIN-B Receive
LIN-B Transmit
I
34
10, 12,
14, 18,
22, 24,
40
36, 41,
50, 64,
67, 76,
79
35, 41,
53, 56,
63
30, 35,
41, 53, 27, 33
56, 63
O
2, 24,
34
41, 61,
77
OUTPUTXBAR1
OUTPUTXBAR2
OUTPUTXBAR3
OUTPUTXBAR4
OUTPUTXBAR5
OUTPUTXBAR6
OUTPUTXBAR7
OUTPUTXBAR8
Output X-BAR Output 1
Output X-BAR Output 2
Output X-BAR Output 3
Output X-BAR Output 4
Output X-BAR Output 5
Output X-BAR Output 6
Output X-BAR Output 7
Output X-BAR Output 8
O
O
O
O
O
O
O
O
35, 50
37, 49
48, 61
32, 64
2, 57
1, 62
31, 33
34
35, 50
37, 49
48, 61
32, 64
2, 57
1, 62
31, 33
34
27, 40
29, 39
38, 47
25, 48
2, 43
1
25, 3,
37
42, 46,
60
14, 26,
4, 5
43, 59,
74, 79
15, 27,
33, 6
38, 44,
78, 80
28, 42,
7
4, 57,
68
29, 43,
9
3, 54,
75
11, 16,
30, 44
1, 37,
39, 69
26
17, 31,
45
2, 40,
73
13, 19,
27, 37, 37, 42 46, 51,
43 54
35, 44,
29, 37,
42
PMBUSA_ALERT
PMBus-A Open-Drain Bidirectional Alert
I/OD
29, 34
32
Terminal Configuration and Functions
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Table 4-3. Digital Signals (continued)
PIN
TYPE
64
QFP-Q
SIGNAL NAME
DESCRIPTION
GPIO
80 QFP 64 QFP 48 QFP
12, 18,
26, 35, 39, 41 48, 50,
42
36, 43,
30, 39,
PMBus-A Control Signal - Slave Input/Master
Output
PMBUSA_CTL
PMBUSA_SCL
PMBUSA_SDA
SCIA_RX
I/O
I/OD
I/OD
I
31, 33
41
57
15, 16, 33, 35, 39, 41, 33, 35,
24, 3,
35, 41
26, 27,
31, 39
PMBus-A Open-Drain Bidirectional Clock
PMBus-A Open-Drain Bidirectional Data
SCI-A Receive Data
39, 49, 48, 60, 39, 49,
55
66, 78
55
14, 17,
2, 25,
34, 40
40, 42,
61, 64,
77, 79
34, 50,
53
34, 50,
53
40
17, 25,
28, 3,
35, 9
2, 34,
4, 40,
2, 34,
2, 31,
39
39, 49, 42, 48, 39, 49,
62
60, 75
62
16, 2,
1, 33,
3, 39,
1, 33,
1, 26,
SCIA_TX
SCI-A Transmit Data
O
24, 29, 35, 37, 41, 46, 35, 37, 27, 29,
37, 8
12, 18, 41, 49, 36, 50, 30, 41,
3, 9 62 60, 75 49, 62
11, 16, 31, 33, 37, 39, 31, 33,
47, 50
58, 61
47, 50
40
SPIA_CLK
SPIA_SIMO
SPIA_SOMI
SPIA_STE
SPI-A Clock
I/O
I/O
I/O
I/O
33, 39
SPI-A Slave In, Master Out (SIMO)
SPI-A Slave Out, Master In (SOMI)
SPI-A Slave Transmit Enable (STE)
26, 40
41
2, 8
47, 50
34, 51, 35, 40, 29, 34,
63 62, 76 51, 63
58, 61
47, 50
1, 10,
13, 17
0, 11,
19, 5
31, 42, 37, 51, 31, 42, 34, 42,
52, 61
63, 74
52, 61
47
14, 22,
26, 28,
32, 4
4, 43,
49, 59,
67, 79
2, 40,
48, 56
2, 40,
48, 56
2, 32,
38
SPIB_CLK
SPIB_SIMO
SPIB_SOMI
SPI-B Clock
I/O
I/O
I/O
24, 30, 35, 53,
40, 7
1, 41,
64, 68
35, 53,
57
SPI-B Slave In, Master Out (SIMO)
SPI-B Slave Out, Master In (SOMI)
27, 43
26, 48
57
16, 25,
31, 41,
6
2, 39,
42, 66,
80
33, 55,
64
33, 55,
64
15, 23,
27, 29,
33
3, 38,
44, 65,
78
1, 32,
54
1, 32,
54
SPIB_STE
SYNCOUT
SPI-B Slave Transmit Enable (STE)
External ePWM Synchronization Pulse
I/O
O
1, 25
48
39, 6
46, 64
56, 80
46, 64
JTAG Test Data Input (TDI) - TDI is the
default mux selection for the pin. The internal
pullup is disabled by default. The internal
pullup should be enabled or an external pullup
added on the board if this pin is used as
JTAG TDI to avoid a floating input.
TDI
I
35
39
48
39
31
JTAG Test Data Output (TDO) - TDO is the
default mux selection for the pin. The internal
pullup is disabled by default. The TDO
function will tristate when there is no JTAG
activity, leaving this pin floating; the internal
pullup should be enabled or an external pullup
added on the board to avoid a floating GPIO
input.
TDO
O
37
19
37
42
46
51
37
42
29
Crystal oscillator input or single-ended clock
input. The device initialization software must
configure this pin before the crystal oscillator
is enabled. To use this oscillator, a quartz
crystal circuit must be connected to X1 and
X2. This pin can also be used to feed a
single-ended 3.3-V level clock.
X1
I
34
X2
Crystal oscillator output.
O
O
18
41
50
41
33
External Clock Output. This pin outputs a
divided-down version of a chosen clock signal
from within the device.
XCLKOUT
16, 18
33, 41
39, 50
33, 41
26, 33
Copyright © 2020, Texas Instruments Incorporated
Terminal Configuration and Functions
33
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
4.3.3 Power and Ground
Table 4-4. Power and Ground
PIN
TYPE
64
QFP-Q
SIGNAL NAME
DESCRIPTION
GPIO
80 QFP 64 QFP 48 QFP
1.2-V Digital Logic Power Pins. TI
recommends placing a decoupling capacitor
near each VDD pin with a total capacitance of
approximately 22 µF.
27, 4,
44, 59
31, 53,
71, 8
27, 4,
44, 59
VDD
36, 45
3.3-V Analog Power Pins. Place a minimum
2.2-µF decoupling capacitor on each pin.
VDDA
22
26
22
18
3.3-V Digital I/O Power Pins. Place a
minimum 0.1-µF decoupling capacitor on each
pin.
28, 43, 32, 52, 28, 43,
60 7, 72 60
VDDIO
35, 46
26, 45, 30, 55, 26, 45, 22, 37,
VSS
Digital Ground
Analog Ground
5, 58
70, 9
5, 58
44
VSSA
21
25
21
17
34
Terminal Configuration and Functions
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
4.3.4 Test, JTAG, and Reset
Table 4-5. Test, JTAG, and Reset
PIN
TYPE
64
QFP-Q
SIGNAL NAME
DESCRIPTION
GPIO
80 QFP 64 QFP 48 QFP
Flash test pin 1. Reserved for TI. Must be left
unconnected.
FLT1
I/O
30
34
24
Flash test pin 2. Reserved for TI. Must be left
unconnected.
FLT2
TCK
I/O
I
29
36
33
45
23
28
JTAG test clock with internal pullup.
36
38
JTAG test-mode select (TMS) with internal
pullup. This serial control input is clocked into
the TAP controller on the rising edge of TCK.
This device does not have a TRSTn pin. An
external pullup resistor (recommended 2.2
kΩ) on the TMS pin to VDDIO should be
placed on the board to keep JTAG in reset
during normal operation.
TMS
I/O
38
47
30
Device Reset (in) and Watchdog Reset (out).
During a power-on condition, this pin is driven
low by the device. An external circuit may also
drive this pin to assert a device reset. This pin
is also driven low by the MCU when a
watchdog reset occurs. During watchdog
reset, the XRSn pin is driven low for the
watchdog reset duration of 512 OSCCLK
cycles. A resistor between 2.2 kΩ and 10 kΩ
should be placed between XRSn and VDDIO.
If a capacitor is placed between XRSn and
VSS for noise filtering, it should be 100 nF or
smaller. These values will allow the watchdog
to properly drive the XRSn pin to VOL within
512 OSCCLK cycles when the watchdog reset
is asserted. This pin is an open-drain output
with an internal pullup. If this pin is driven by
an external device, it should be done using an
open-drain device.
XRSn
I/OD
3
5
3
3
Copyright © 2020, Texas Instruments Incorporated
Terminal Configuration and Functions
35
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
4.4 Pin Multiplexing
4.4.1 GPIO Muxed Pins
Table 4-6 lists the GPIO muxed pins. The default mode for each GPIO pin is the GPIO function, except
GPIO35 and GPIO37, which default to TDI and TDO, respectively. Secondary functions can be selected
by setting both the GPyGMUXn.GPIOz and GPyMUXn.GPIOz register bits. The GPyGMUXn register
should be configured before the GPyMUXn to avoid transient pulses on GPIOs from alternate mux
selections. Columns that are not shown and blank cells are reserved GPIO Mux settings. GPIO ALT
functions cannot be configured with the GPyMUXn and GPyGMUXn registers. These are special functions
that need to be configured from the module.
NOTE
GPIO20, GPIO21, GPIO36 and GPIO38 do not exist on this device. GPIO61 to GPIO63 exist
but are not pinned out on any packages. Boot ROM enables pullups on GPIO61 to GPIO63.
For more details, see Section 4.5.
36
Terminal Configuration and Functions
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Table 4-6. GPIO Muxed Pins
0, 4, 8, 12
1
2
3
5
6
7
9
10
11
13
14
15
ALT
CLB_OUTPUTXB
AR8
GPIO0
EPWM1_A
I2CA_SDA
SPIA_STE
FSIRXA_CLK
HIC_BASESEL1
CLB_OUTPUTXB
AR7
GPIO1
EPWM1_B
I2CA_SCL
SPIA_SOMI
HIC_A2
FSITXA_TDM_D1
HIC_D10
GPIO2
GPIO3
EPWM2_A
EPWM2_B
OUTPUTXBAR1
OUTPUTXBAR2
PMBUSA_SDA
PMBUSA_SCL
SPIA_SIMO
SPIA_CLK
SCIA_TX
SCIA_RX
FSIRXA_D1
FSIRXA_D0
I2CB_SDA
I2CB_SCL
HIC_A1
CANA_TX
CANA_RX
HIC_D9
HIC_D4
OUTPUTXBAR2
OUTPUTXBAR4
HIC_NOE
CLB_OUTPUTXB
AR6
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
EPWM3_A
EPWM3_B
EPWM4_A
EPWM4_B
EPWM5_A
OUTPUTXBAR3
CANA_TX
CANA_RX
SPIB_CLK
SPIA_STE
SPIB_SOMI
SPIB_SIMO
SPIA_SIMO
EQEP2_STROBE
FSITXA_D1
FSIRXA_CLK
HIC_BASESEL2
HIC_A7
HIC_NWE
HIC_D15
HIC_D14
HIC_D14
CLB_OUTPUTXB
AR5
OUTPUTXBAR3
SYNCOUT
HIC_D4
CLB_OUTPUTXB
AR8
EQEP1_A
EQEP1_B
FSITXA_D0
FSITXA_D1
HIC_NBE1
HIC_A6
CLB_OUTPUTXB
AR2
OUTPUTXBAR5
ADCSOCAO
FSITXA_CLK
I2CA_SCL
CLB_OUTPUTXB
AR5
FSITXA_TDM_CL
K
EQEP1_STROBE
SCIA_TX
SCIA_RX
FSITXA_D1
HIC_A0
HIC_D8
GPIO9
EPWM5_B
EPWM6_A
EPWM6_B
EPWM7_A
EPWM7_B
OUTPUTXBAR6
ADCSOCBO
EQEP1_INDEX
EQEP1_A
SPIA_CLK
SPIA_SOMI
FSITXA_D0
FSITXA_CLK
LINB_RX
LINB_RX
LINB_TX
HIC_BASESEL0
HIC_NWE
I2CB_SCL
FSITXA_TDM_D0
HIC_D6
HIC_NRDY
GPIO10
GPIO11
GPIO12
GPIO13
I2CA_SDA
FSIRXA_D1
FSIRXA_D0
FSIRXA_CLK
OUTPUTXBAR7
EQEP1_B
SPIA_STE
EQEP2_A
SPIA_CLK
SPIA_SOMI
SPIA_SIMO
CANA_RX
HIC_NBE0
HIC_INT
HIC_D5
EQEP1_STROBE
EQEP1_INDEX
PMBUSA_CTL
PMBUSA_ALERT
LINB_TX
HIC_D13
LINB_RX
CANA_TX
HIC_D11
CLB_OUTPUTXB
AR7
GPIO14
GPIO15
I2CB_SDA
I2CB_SCL
OUTPUTXBAR3
OUTPUTXBAR4
PMBUSA_SDA
PMBUSA_SCL
SPIB_CLK
SPIB_STE
EQEP2_A
EQEP2_B
LINB_TX
LINB_RX
EPWM3_A
HIC_D15
HIC_D12
CLB_OUTPUTXB
AR6
EPWM3_B
EQEP2_B
GPIO16
GPIO17
SPIA_SIMO
SPIA_SOMI
OUTPUTXBAR7
OUTPUTXBAR8
EPWM5_A
EPWM5_B
SCIA_TX
SCIA_RX
EQEP1_STROBE PMBUSA_SCL
XCLKOUT
CANA_TX
SPIB_SOMI
HIC_D1
HIC_D2
EQEP1_INDEX
EQEP2_A
PMBUSA_SDA
PMBUSA_CTL
FSITXA_TDM_CL
K
GPIO18_X2
GPIO19_X1
GPIO22
SPIA_CLK
SPIA_STE
CANA_RX
CANA_TX
EPWM6_A
EPWM6_B
I2CA_SCL
I2CA_SDA
SPIB_CLK
XCLKOUT
LINB_TX
LINB_RX
HIC_A5
HIC_INT
HIC_NBE0
HIC_D13
X2
X1
CLB_OUTPUTXB
AR1
EQEP2_B
LINA_TX
PMBUSA_ALERT
FSITXA_TDM_D0
CLB_OUTPUTXB
AR1
EQEP1_STROBE
LINB_TX
EPWM4_A
EPWM4_B
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
GPIO32
EQEP1_INDEX
OUTPUTXBAR1
OUTPUTXBAR2
OUTPUTXBAR3
SPIB_STE
SPIB_SIMO
SPIB_SOMI
SPIB_CLK
SPIB_STE
EQEP1_A
EQEP1_B
LINA_RX
LINB_TX
LINB_RX
SCIA_TX
HIC_A3
HIC_D11
HIC_D3
EQEP2_A
EQEP2_B
PMBUSA_SCL
PMBUSA_SDA
PMBUSA_CTL
PMBUSA_ALERT
LINA_TX
ERRORSTS
EQEP1_A
FSITXA_D1
SCIA_RX
I2CA_SDA
I2CA_SCL
SPIB_CLK
SPIB_STE
EPWM1_A
EPWM1_B
HIC_BASESEL0
HIC_D0
EQEP2_INDEX
OUTPUTXBAR3
OUTPUTXBAR4
OUTPUTXBAR5
OUTPUTXBAR6
FSITXA_D0
HIC_A1
HIC_A4
OUTPUTXBAR4 EQEP2_STROBE
FSITXA_CLK
EQEP2_STROBE
EQEP2_INDEX
FSIRXA_CLK
FSIRXA_D1
FSIRXA_D0
HIC_D1
SCIA_RX
SCIA_TX
CANA_RX
CANA_TX
I2CA_SDA
EPWM7_A
EPWM7_B
SPIB_SIMO
SPIB_SOMI
SPIB_CLK
ERRORSTS
ERRORSTS
I2CB_SDA
I2CB_SCL
HIC_D8
HIC_NOE
HIC_NCS
LINA_RX
OUTPUTXBAR7 EQEP1_STROBE
OUTPUTXBAR8
EQEP1_INDEX
LINA_TX
HIC_D10
CANA_TX
ADCSOCBO
HIC_INT
Copyright © 2020, Texas Instruments Incorporated
Terminal Configuration and Functions
37
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Table 4-6. GPIO Muxed Pins (continued)
0, 4, 8, 12
GPIO33
GPIO34
GPIO35
GPIO37
1
2
3
5
6
7
9
10
11
13
14
15
ALT
I2CA_SCL
SPIB_STE
OUTPUTXBAR4
LINA_RX
FSIRXA_CLK
CANA_RX
EQEP2_B
ADCSOCAO
HIC_NBE1
HIC_D0
HIC_D9
TDI
OUTPUTXBAR1
SCIA_RX
PMBUSA_SDA
PMBUSA_SCL
CANA_TX
I2CB_SDA
HIC_NWE
HIC_NRDY
I2CA_SDA
I2CA_SCL
CANA_RX
SCIA_TX
LINA_RX
LINA_TX
EQEP1_A
EQEP1_B
PMBUSA_CTL
OUTPUTXBAR2
PMBUSA_ALERT
TDO
CLB_OUTPUTXB
AR2
GPIO39
FSIRXA_CLK
EQEP2_INDEX
SYNCOUT
HIC_A4
EQEP1_INDEX
HIC_D7
GPIO40
GPIO41
SPIB_SIMO
EPWM2_B
EPWM2_A
PMBUSA_SDA
PMBUSA_SCL
FSIRXA_D0
FSIRXA_D1
EQEP1_A
EQEP1_B
LINB_TX
LINB_RX
HIC_NBE1
HIC_D5
SPIB_SOMI
HIC_D12
CLB_OUTPUTXB
AR3
GPIO42
GPIO43
GPIO44
GPIO45
LINA_RX
OUTPUTXBAR5
PMBUSA_CTL
I2CA_SDA
I2CA_SCL
EQEP1_STROBE
EQEP1_INDEX
HIC_D2
HIC_D3
HIC_A6
HIC_A7
HIC_D5
CLB_OUTPUTXB
AR4
OUTPUTXBAR6 PMBUSA_ALERT
CLB_OUTPUTXB
AR3
OUTPUTXBAR7
EQEP1_A
FSITXA_CLK
HIC_D7
CLB_OUTPUTXB
AR4
OUTPUTXBAR8
LINA_TX
FSITXA_D0
FSITXA_D1
HIC_D6
GPIO46
GPIO61
GPIO62
GPIO63
HIC_NWE
38
Terminal Configuration and Functions
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
4.4.2 Digital Inputs on ADC Pins (AIOs)
GPIOs on port H (GPIO224–GPIO245) are multiplexed with analog pins. These are also referred to as
AIOs. These pins can only function in input mode. By default, these pins will function as analog pins and
the GPIOs are in a high-Z state. The GPHAMSEL register is used to configure these pins for digital or
analog operation.
NOTE
If digital signals with sharp edges (high dv/dt) are connected to the AIOs, cross-talk can
occur with adjacent analog signals. The user should therefore limit the edge rate of signals
connected to AIOs if adjacent channels are being used for analog functions.
4.4.3 GPIO Input X-BAR
The Input X-BAR is used to route signals from a GPIO to many different IP blocks such as the ADCs,
eCAPs, ePWMs, and external interrupts (see Figure 4-5). Table 4-7 lists the input X-BAR destinations. For
details on configuring the Input X-BAR, see the Crossbar (X-BAR) chapter of the TMS320F28002x
Microcontrollers Technical Reference Manual.
GPIO0
Asynchronous
Synchronous
Sync. + Qual.
Input X-BAR
Other Sources
127:16
GPIOx
eCAP
Modules
15:0
INPUT[16:1]
DCCx Clock Source-1
DCCx Clock Source-0
TZ1,TRIP1
TZ2,TRIP2
TZ3,TRIP3
TRIP6
XINT1
TRIP4
TRIP5
XINT2
XINT3
XINT4
XINT5
ePWM
Modules
CPU PIE
TRIP7
TRIP8
TRIP9
TRIP10
TRIP11
TRIP12
ePWM
X-BAR
Other
Sources
ADCEXTSOC
Other Sources
ADC
EXTSYNCIN1
EXTSYNCIN2
ePWM and eCAP
Sync Scheme
Output X-BAR
Figure 4-5. Input X-BAR
Copyright © 2020, Texas Instruments Incorporated
Terminal Configuration and Functions
39
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Table 4-7. Input X-BAR Destinations
INPUT
1
2
3
4
5
6
7
8
9
10 11 12
13
14
15
Yes
16
ECAP / HRCAP
EPWM X-BAR
CLB X-BAR
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes Yes Yes Yes Yes Yes Yes
Yes Yes Yes Yes Yes Yes Yes
Yes Yes Yes Yes Yes Yes Yes
Yes
Yes
Yes
Yes
Yes
Yes
OUTPUT X-BAR
CPU XINT
Yes
XINT1 XINT2
XINT3
XINT4 XINT5
TZ1,
TZ2,
TZ3,
EPWM TRIP
TRIP6
TRIP1 TRIP2 TRIP3
ADC START OF
CONVERSION
ADCEX
TSOC
EPWM / ECAP
SYNC
EXTSY EXTSY
NCIN1 NCIN2
DCCx
CLK1 CLK0
4.4.4 GPIO Output X-BAR and ePWM X-BAR
The Output X-BAR has eight outputs which are routed to the GPIO module. The ePWM X-BAR has eight
outputs which are routed to each ePWM module. Figure 4-6 shows the sources for both the Output X-BAR
and ePWM X-BAR. For details on the Output X-BAR and ePWM X-BAR, see the Crossbar (X-BAR)
chapter of the TMS320F28002x Microcontrollers Technical Reference Manual.
CTRIPOUTH
CTRIPOUTL
(Output X-BAR only)
CMPSSx
CTRIPH
CTRIPL
(ePWM X-BAR only)
ePWM and eCAP
EXTSYNCOUT
Sync Chain
OUTPUT1
OUTPUT2
OUTPUT3
ADCSOCAO
Select Ckt
ADCSOCAO
GPIO
Mux
OUTPUT4
OUTPUT5
OUTPUT6
OUTPUT7
OUTPUT8
Output
X-BAR
ADCSOCBO
Select Ckt
ADCSOCBO
ECAPxOUT
eCAPx
ADCx
EVT1
EVT2
EVT3
EVT4
TRIP4
TRIP5
TRIP7
TRIP8
TRIP9
TRIP10
TRIP11
TRIP12
All
ePWM
Modules
ePWM
X-BAR
INPUT1-6
Input X-BAR
INPUT7-14
(ePWM X-BAR only)
X-BAR Flags
(shared)
Figure 4-6. Output X-BAR and ePWM X-BAR Sources
40
Terminal Configuration and Functions
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
4.5 Pins With Internal Pullup and Pulldown
Some pins on the device have internal pullups or pulldowns. Table 4-8 lists the pull direction and when it
is active. The pullups on GPIO pins are disabled by default and can be enabled through software. To
avoid any floating unbonded inputs, the Boot ROM will enable internal pullups on GPIO pins that are not
bonded out in a particular package. Other pins noted in Table 4-8 with pullups and pulldowns are always
on and cannot be disabled.
Table 4-8. Pins With Internal Pullup and Pulldown
RESET
(XRSn = 0)
PIN
DEVICE BOOT
APPLICATION
GPIOx
Pullup disabled
Pullup disabled(1)
Application defined
Application defined
Application defined
GPIO35/TDI
GPIO37/TDO
TCK
Pullup disabled
Pullup disabled
Pullup active
Pullup active
Pullup active
TMS
XRSn
Other pins (including AIOs)
No pullup or pulldown present
(1) Pins not bonded out in a given package will have the internal pullups enabled by the Boot ROM.
Copyright © 2020, Texas Instruments Incorporated
Terminal Configuration and Functions
41
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
4.6 Connections for Unused Pins
For applications that do not need to use all functions of the device, Table 4-9 lists acceptable conditioning
for any unused pins. When multiple options are listed in Table 4-9, any option is acceptable. Pins not
listed in Table 4-9 must be connected according to Section 4.
Table 4-9. Connections for Unused Pins
SIGNAL NAME
ACCEPTABLE PRACTICE
ANALOG
VREFHI
VREFLO
Tie to VDDA (applies only if ADC is not used in the application)
Tie to VSSA
DIGITAL
•
•
No Connect
FLT1 (Flash Test pin 1)
FLT2 (Flash Test pin 2)
Tie to VSS through 4.7-kΩ or larger resistor
•
•
No Connect
Tie to VSS through 4.7-kΩ or larger resistor
•
•
•
No connection (input mode with internal pullup enabled)
GPIOx
No connection (output mode with internal pullup disabled)
Pullup or pulldown resistor (any value resistor, input mode, and with internal pullup disabled)
When TDI mux option is selected (default), the GPIO is in Input mode.
GPIO35/TDI
•
•
Internal pullup enabled
External pullup resistor
When TDO mux option is selected (default), the GPIO is in Output mode only during JTAG activity;
otherwise, it is in a tri-state condition. The pin must be biased to avoid extra current on the input buffer.
GPIO37/TDO
•
•
Internal pullup enabled
External pullup resistor
•
•
No Connect
TCK
TMS
Pullup resistor
Pullup resistor
Turn XTAL off and:
•
•
•
Input mode with internal pullup enabled
GPIO19/X1
GPIO18/X2
Input mode with external pullup or pulldown resistor
Output mode with internal pullup disabled
Turn XTAL off and:
•
•
•
Input mode with internal pullup enabled
Input mode with external pullup or pulldown resistor
Output mode with internal pullup disabled
POWER AND GROUND
VDD
All VDD pins must be connected per Section 4.3. Pins should not be used to bias any external circuits.
If a dedicated analog supply is not used, tie to VDDIO.
VDDA
VDDIO
VSS
All VDDIO pins must be connected per Section 4.3.
All VSS pins must be connected to board ground.
VSSA
If an analog ground is not used, tie to VSS.
42
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5 Specifications
5.1 Absolute Maximum Ratings(1)(2)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.3
–0.3
–0.3
–0.3
MAX
4.6
UNIT
VDDIO with respect to VSS
Supply voltage
V
VDDA with respect to VSSA
4.6
Input voltage
VIN (3.3 V)
VO
4.6
V
V
Output voltage
4.6
Digital/analog input (per pin), IIK (VIN < VSS/VSSA or VIN
VDDIO/VDDA)(3)
>
–20
–20
20
20
Input clamp current
mA
Total for all inputs, IIKTOTAL
(VIN < VSS/VSSA or VIN > VDDIO/VDDA)
Output current
Digital output (per pin), IOUT
–20
–40
–40
–65
20
125
150
150
mA
°C
°C
°C
Free-Air temperature
Operating junction temperature
Storage temperature(4)
TA
TJ
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device beyond the Recommended Operating Conditions is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
(3) Continuous clamp current per pin is ±2 mA. Do not operate in this condition continuously as VDDIO/VDDA voltage may internally rise and
impact other electrical specifications.
(4) Long-term high-temperature storage or extended use at maximum temperature conditions may result in a reduction of overall device life.
For additional information, see the Semiconductor and IC Package Thermal Metrics Application Report.
Copyright © 2020, Texas Instruments Incorporated
Specifications
43
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.2 ESD Ratings – Commercial
VALUE
UNIT
F280023C in 80-pin PN package
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-
±2000
±500
001(1)
Electrostatic discharge
(ESD)
V(ESD)
V
Charged-device model (CDM), per JEDEC specification
JESD22-C101 or ANSI/ESDA/JEDEC JS-002(2)
F280025, F280025C, F280023, F280023C in 64-pin PM package
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-
±2000
±500
001(1)
Electrostatic discharge
(ESD)
V(ESD)
V
V
Charged-device model (CDM), per JEDEC specification
JESD22-C101 or ANSI/ESDA/JEDEC JS-002(2)
F280023C in 48-pin PT package
V(ESD)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-
001(1)
±2000
±500
Electrostatic discharge
(ESD)
Charged-device model (CDM), per JEDEC specification
JESD22-C101 or ANSI/ESDA/JEDEC JS-002(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
5.3 ESD Ratings – Automotive
VALUE
UNIT
F280025, F280025C, F280023 in 80-pin PN package
Human body model (HBM), per
All pins
All pins
±2000
AEC Q100-002(1)
V(ESD)
Electrostatic discharge
Charged device model (CDM),
per AEC Q100-011
±500
±750
V
Corner pins on 80-pin PN:
1, 20, 21, 40, 41, 60, 61, 80
F280024, F280024C, F280022 in 64-pin PM package
Human body model (HBM), per
All pins
All pins
±2000
AEC Q100-002(1)
V(ESD)
Electrostatic discharge
Charged device model (CDM),
per AEC Q100-011
±500
±750
V
V
Corner pins on 64-pin PM:
1, 16, 17, 32, 33, 48, 49, 64
F280025, F280025C, F280023, F280021 in 48-pin PT package
Human body model (HBM), per
All pins
All pins
±2000
AEC Q100-002(1)
V(ESD)
Electrostatic discharge
Charged device model (CDM),
per AEC Q100-011
±500
±750
Corner pins on 48-pin PT:
1, 12, 13, 24, 25, 36, 37, 48
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
44
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.4 Recommended Operating Conditions
NO
M
UNI
T
MIN
MAX
(2)
Internal BOR enabled(1)
Device supply voltage, VDDIO and VDDA
Internal BOR disabled
VBOR-VDDIO(MAX) + VBOR-GB
3.3
3.63
3.63
V
2.8 3.3
Device ground, VSS
Analog ground, VSSA
0
0
V
V
Supply ramp rate of VDDIO, VDD, VDDA
105
SRSUPPLY
V/s
with respect to VSS.(3)
VDDIO supply ramp time from
1 V to VBOR-VDDIO(MAX)
tVDDIO-RAMP
10 ms
Digital input voltage
Analog input voltage
VDDIO BOR guard band(4)
S version(5)
Q version(5)
(AEC Q100 qualification)
VSS – 0.3
VDDIO + 0.3
VDDA + 0.3
V
V
V
VIN
VSSA – 0.3
VBOR-GB
0.1
Junction temperature, TJ
–40
–40
125 °C
125 °C
Free-Air temperature, TA
(1) Internal BOR is enabled by default.
(2) The VDDIO BOR voltage (VBOR-VDDIO[MAX]) in Electrical Characteristics determines the lower voltage bound for device operation. TI
recommends that system designers budget an additional guard band (VBOR-GB) as shown in Figure 5-1.
(3) Supply ramp rate faster than this can trigger the on-chip ESD protection.
(4) TI recommends VBOR-GB to avoid BOR resets due to normal supply noise or load-transient events on the 3.3-V VDDIO system regulator.
Good system regulator design and decoupling capacitance (following the system regulator specifications) are important to prevent
activation of the BOR during normal device operation. The value of VBOR-GB is a system-level design consideration; the voltage listed
here is typical for many applications.
(5) Operation above TJ = 105°C for extended duration will reduce the lifetime of the device. See Calculating Useful Lifetimes of Embedded
Processors for more information.
3.63 V
+10%
Recommended
System Voltage
Regulator Range
3.3 V
0%
F28002x
VDDIO
Operating
Range
3.1 V
3.0 V
–6.1%
–9.1%
VBOR-GB
BOR Guard Band
VBOR-VDDIO
Internal BOR Threshold
–14.8%
–15.1%
2.81 V
2.80 V
Figure 5-1. Supply Voltages
Copyright © 2020, Texas Instruments Incorporated
Specifications
45
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.5 Power Consumption Summary
Current values listed in this section are representative for the test conditions given and not the absolute
maximum possible. The actual device currents in an application will vary with application code and pin
configurations. Table 5-1 lists the system current consumption values.
Table 5-1. System Current Consumption
over operating free-air temperature range (unless otherwise noted).
TYP : Vnom, 30℃
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPERATING MODE
VDDIO current consumption during
operational usage
This is an estimation of current
for a typical heavily loaded
application. Actual currents will
vary depending on system
activity, I/O electrical loading and
switching frequency.
IDDIO
35
3
65
5
mA
mA
VDDA current consumption during
operational usage
IDDA
IDLE MODE
VDDIO current consumption while
device is in Idle mode
IDDIO
16
25
mA
mA
- CPU is in IDLE mode
- Flash is powered down
- XCLKOUT is turned off
VDDA current consumption while
device is in Idle mode
IDDA
0.01
0.1
STANDBY MODE
VDDIO current consumption while
device is in Standby mode
IDDIO
8
15
mA
mA
- CPU is in STANDBY mode
- Flash is powered down
- XCLKOUT is turned off
VDDA current consumption while
device is in Standby mode
IDDA
0.01
0.1
HALT MODE
IDDIO
VDDIO current consumption while
device is in Halt mode
1
10
mA
mA
- CPU is in HALT mode
- Flash is powered down
- XCLKOUT is turned off
VDDA current consumption while
device is in Halt mode
IDDA
0.01
0.1
FLASH ERASE/PROGRAM
VDDIO current consumption during
- CPU is running from RAM.
- SYSCLK at 100 MHz.
- I/Os are inputs with pullups
enabled.
IDDIO
72
106
2.5
mA
mA
Erase/Program cycle(1)
VDDA current consumption during
Erase/Program cycle
- Peripheral clocks are turned off.
IDDA
0.1
RESET MODE
VDDIO current consumption while
reset is active(2)
IDDIO
8.6
0.1
mA
mA
VDDA current consumption while reset
is active(2)
IDDA
(1) Brownout events during flash programming can corrupt flash data and permanently lock the device. Programming environments using
alternate power sources (such as a USB programmer) must be capable of supplying the rated current for the device and other system
components with sufficient margin to avoid supply brownout conditions.
(2) This is the current consumption while reset is active, i.e XRSn is low.
46
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.5.1 Operating Mode Test Description
Table 5-1 and Table 5-2 list the current consumption values for the operational mode of the device. The
operational mode provides an estimation of what an application might encounter. The test condition for
these measurements has the following properties:
•
•
•
•
•
•
Code is executing from RAM.
FLASH is read and kept in active state.
No external components are driven by I/O pins.
All peripherals have clocks enabled.
All CPUs are actively executing code.
All analog peripherals are powered up. ADCs and DACs are periodically converting.
5.5.2 Reducing Current Consumption
All C2000™ microcontrollers provide some methods to reduce the device current consumption:
•
Any one of the three low-power modes—IDLE, STANDBY and HALT—could be entered to reduce the
current consumption even further during idle periods in the application.
•
•
•
The flash module may be powered down if the code is run from RAM.
Disable the pullups on pins that assume an output function.
Each peripheral has an individual clock-enable bit (PCLKCRx). Reduced current consumption may be
achieved by turning off the clock to any peripheral that is not used in a given application. Table 5-2 lists
the typical current reduction value per disabled peripheral at 100-MHz SYSCLK.
•
To realize the lowest VDDA current consumption in an LPM, see the respective analog chapter of the
TMS320F28002x Microcontrollers Technical Reference Manual to ensure each module is powered
down as well.
Table 5-2. Typical Current Reduction per Disabled Peripheral
PERIPHERAL
IDDIO CURRENT REDUCTION (mA)
ADC(1)
CAN
0.8
1.1
1.1
0.4
0.1
0.5
0.1
0.4
0.7
0.1
0.7
0.8
0.3
0.4
0.3
0.2
0.2
0.1
CLB
CMPSS(1)
CPU TIMER
DMA
eCAP1 and eCAP2
eCAP3(2)
ePWM
eQEP
FSI
HRPWM
I2C
LIN
PMBUS
SCI
SPI
DCC
(1) This current represents the current drawn by the digital portion of the each module.
(2) eCAP3 can also be configured as HRCAP.
Copyright © 2020, Texas Instruments Incorporated
Specifications
47
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.6 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
TEST
PARAMETER
CONDITIONS
MIN
TYP
MAX UNIT
Digital and Analog IO
IOH = IOH MIN
IOH = –100 μA
IOL = IOL MAX
IOL = 100 µA
VDDIO * 0.8
VDDIO – 0.2
VOH
High-level output voltage
Low-level output voltage
V
0.4
V
VOL
IOH
0.2
High-level output source current for all output
pins
–4
mA
IOL
Low-level output sink current for all output pins
High-level output impedance for all output pins
Low-level output impedance for all output pins
High-level input voltage
4
mA
Ω
ROH
70
70
ROL
Ω
VIH
2.0
V
VIL
Low-level input voltage
0.8
V
VHYSTERESIS
Input hysteresis
125
mV
VDDIO = 3.3 V
VIN = VDDIO
IPULLDOWN
IPULLUP
Input current
Input current
Pins with pulldown
120
160
µA
µA
Digital inputs with
pullup enabled(1)
VDDIO = 3.3 V
VIN = 0 V
Pullups and
Digital inputs
outputs disabled
0 V ≤ VIN ≤ VDDIO
0.1
ILEAK
Pin leakage
µA
Analog pins (except
ADCINA3/VDAC)
Analog drivers
disabled
0 V ≤ VIN ≤ VDDA
0.1
11
ADCINA3/VDAC
Digital inputs
Analog pins(2)
2
2
CI
Input capacitance
pF
V
VREG and BOR
VDDIO power on reset VDDIO power on reset
voltage voltage
VDDIO brown out reset voltage(3)
VPOR-VDDIO
2.3
1.2
VBOR-VDDIO
VVREG
2.81
1.14
3.0
V
V
Internal voltage regulator output
1.32
(1) See Table 4-8 for a list of pins with a pullup or pulldown.
(2) The analog pins are specified separately; see Table 5-40.
(3) See the Supply Voltages figure in the Recommended Operating Conditions section.
5.7 Thermal Design Considerations
Based on the end application design and operational profile, the IDD and IDDIO currents could vary.
Systems that exceed the recommended maximum power dissipation in the end product may require
additional thermal enhancements. Ambient temperature (TA) varies with the end application and product
design. The critical factor that affects reliability and functionality is TJ, the junction temperature, not the
ambient temperature. Hence, care should be taken to keep TJ within the specified limits. Tcase should be
measured to estimate the operating junction temperature TJ. Tcase is normally measured at the center of
the package top-side surface. The thermal application report Semiconductor and IC Package Thermal
Metrics helps to understand the thermal metrics and definitions.
48
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.8 System
5.8.1 Power Management
TMS320F28002x MCUs use an internal 1.2-V LDO Voltage Regulator (VREG) to supply the required
1.2 V to the core (VDD).
5.8.1.1 Internal 1.2-V LDO Voltage Regulator (VREG)
The internal VREG is supplied by VDDIO and generates the 1.2 V required to power the VDD pins. The
internal VREG is always enabled and, as such, is the required supply source for the VDD pins. Although
the internal VREG eliminates the need to use an external power supply for VDD, decoupling capacitors
are required on each VDD pin for VREG stability. There are two recommended capacitor configurations
(described in the list that follows) for the VDD rail when using the internal VREG. The signal description
for VDD can be found in Table 4-4.
•
Configuration 1: Place a small decoupling capacitor to VSS on each pin as close to the device as
possible. In addition, a bulk capacitance must be placed on the VDD node to VSS (one 20-µF
capacitor or two parallel 10-µF capacitors).
•
Configuration 2: Distribute the total capacitance to VSS evenly across all VDD pins (total capacitance
divided by number of available VDD pins).
5.8.1.2 Power Sequencing
Signal Pin Requirements: Before powering the device, no voltage larger than 0.3 V above VDDIO can
be applied to any digital pin, and no voltage larger than 0.3 V above VDDA can be applied to any analog
pin (including VREFHI).
VDDIO and VDDA Requirements: The 3.3-V supplies VDDIO and VDDA should be powered up together
and kept within 0.3 V of each other during functional operation.
VDD Requirements: The VDD sequencing requirements are handled by the device.
5.8.1.3 Power-On Reset (POR)
An internal power-on reset (POR) circuit holds the device in reset and keeps the I/Os in a high-impedance
state during power up. The POR is in control and forces XRSn low internally until the voltage on VDDIO
crosses the POR threshold. When the voltage crosses the POR threshold, the internal brownout-reset
(BOR) circuit takes control and holds the device in reset until the voltage crosses the BOR threshold (for
internal BOR details, see Section 5.8.1.4).
5.8.1.4 Brownout Reset (BOR)
An internal BOR circuit monitors the VDDIO rail for dips in voltage which result in the supply voltage
dropping out of operational range. When the VDDIO voltage drops below the BOR threshold, the device is
forced into reset, and XRSn is pulled low. XRSn will remain in reset until the voltage returns to the
operational range. The BOR is enabled by default. To disable the BOR, set the BORLVMONDIS bit in the
VMONCTL register. The internal BOR circuit monitors only the VDDIO rail. See Section 5.6 for BOR
characteristics. External supply voltage supervisor (SVS) devices can be used to monitor the voltage on
the 3.3-V rail and to drive XRSn low if supplies fall outside operational specifications.
Copyright © 2020, Texas Instruments Incorporated
Specifications
49
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.8.2 Reset Timing
XRSn is the device reset pin. It functions as an input and open-drain output. The device has a built-in
power-on reset (POR). During power up, the POR circuit drives the XRSn pin low. A watchdog or NMI
watchdog reset will also drive the pin low. An external open-drain circuit may drive the pin to assert a
device reset.
A resistor with a value from 2.2 kΩ to 10 kΩ should be placed between XRSn and VDDIO. A capacitor
should be placed between XRSn and VSS for noise filtering, it should be 100 nF or smaller. These values
will allow the watchdog to properly drive the XRSn pin to VOL within 512 OSCCLK cycles when the
watchdog reset is asserted. Figure 5-2 shows the recommended reset circuit.
VDDIO
2.2 kW to 10 kW
Optional open-drain
Reset source
XRSn
£100 nF
Figure 5-2. Reset Circuit
5.8.2.1 Reset Sources
Table 5-3 summarizes the various reset signals and their effect on the device.
Table 5-3. Reset Signals
CPU CORE
JTAG/
RESET
(C28x, FPU,
VCU)
PERIPHERALS
RESET
RESET SOURCE
DEBUG LOGIC
RESET
I/Os
XRSn OUTPUT
POR
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Yes
–
XRSn Pin
WDRS
Yes
Yes
No
No
NMIWDRS
SYSRS (Debugger Reset)
SCCRESET
The parameter th(boot-mode) must account for a reset initiated from any of these sources.
See the Resets section of the System Control chapter in the TMS320F28002x Microcontrollers Technical
Reference Manual.
CAUTION
Some reset sources are internally driven by the device. Some of these sources
will drive XRSn low, use this to disable any other devices driving the boot pins.
The SCCRESET and debugger reset sources do not drive XRSn; therefore, the
pins used for boot mode should not be actively driven by other devices in the
system. The boot configuration has a provision for changing the boot pins in
OTP; for more details, see the TMS320F28002x Microcontrollers Technical
Reference Manual.
50
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.8.2.2 Reset Electrical Data and Timing
Table 5-4 lists the reset (XRSn) timing requirements. Table 5-5 lists the reset (XRSn) switching
characteristics. Figure 5-3 shows the power-on reset. Figure 5-4 shows the warm reset.
Table 5-4. Reset (XRSn) Timing Requirements
MIN
1.5
MAX
UNIT
ms
th(boot-mode)
tw(RSL2)
Hold time for boot-mode pins
Pulse duration, XRSn low on warm reset
3.2
µs
Table 5-5. Reset (XRSn) Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
100
MAX
UNIT
Pulse duration, XRSn driven low by device after supplies are
tw(RSL1)
tw(WDRS)
µs
stable
Pulse duration, reset pulse generated by watchdog
512tc(OSCCLK)
cycles
VDDIO VDDA
(3.3V)
VDD (1.2V)
tw(RSL1)
XRSn(A)
Boot ROM
CPU
Execution
Phase
User code
(B)
th(boot-mode)
User code dependent
Boot-Mode
Pins
GPIO pins as input
Peripheral/GPIO function
Based on boot code
Boot-ROM execution starts
GPIO pins as input (pullups are disabled)
User code dependent
I/O Pins
A. The XRSn pin can be driven externally by a supervisor or an external pullup resistor, see Table 4-1. On-chip POR
logic will hold this pin low until the supplies are in a valid range.
B. After reset from any source (see Section 5.8.2.1), the boot ROM code samples Boot Mode pins. Based on the status
of the Boot Mode pin, the boot code branches to destination memory or boot code function. If boot ROM code
executes after power-on conditions (in debugger environment), the boot code execution time is based on the current
SYSCLK speed. The SYSCLK will be based on user environment and could be with or without PLL enabled.
Figure 5-3. Power-on Reset
Copyright © 2020, Texas Instruments Incorporated
Specifications
51
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
tw(RSL2)
XRSn
User code
CPU
Execution
Phase
Boot ROM
User code
Boot ROM execution starts
(initiated by any reset source)
(A)
th(boot-mode)
Boot-Mode
Pins
Peripheral/GPIO function
GPIO Pins as Input
Peripheral/GPIO function
User-Code Execution Starts
I/O Pins
GPIO Pins as Input (Pullups are Disabled)
User-Code Dependent
User-Code Dependent
A. After reset from any source (see Section 5.8.2.1), the Boot ROM code samples BOOT Mode pins. Based on the
status of the Boot Mode pin, the boot code branches to destination memory or boot code function. If Boot ROM code
executes after power-on conditions (in debugger environment), the Boot code execution time is based on the current
SYSCLK speed. The SYSCLK will be based on user environment and could be with or without PLL enabled.
Figure 5-4. Warm Reset
52
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.8.3 Clock Specifications
5.8.3.1 Clock Sources
Table 5-6 lists clock sources. Figure 5-5 shows the clocking system. Figure 5-6 shows the PLL.
Table 5-6. Possible Reference Clock Sources
CLOCK SOURCE
INTOSC1
DESCRIPTION
Internal oscillator 1.
Zero-pin overhead 10-MHz internal oscillator.
INTOSC2(1)
X1 (XTAL)
Internal oscillator 2.
Zero-pin overhead 10-MHz internal oscillator.
External crystal or resonator connected between the X1 and X2 pins or single-ended clock connected to the X1
pin.
(1) On reset, internal oscillator 2 (INTOSC2) is the default clock source for the PLL (OSCCLK).
Copyright © 2020, Texas Instruments Incorporated
Specifications
53
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
SYSCLKDIVSEL
PLLSYSCLK
CPUCLK
NMIWD
Watchdog
Timer
SYS
Divider
PLLRAWCLK
FPU
TMU
Flash
SYSPLL
INTOSC1
INTOSC2
X1 (XTAL)
OSCCLK
SYSPLLCLKEN
OSCCLKSRCSEL
CPU
ePIE
Boot ROM
GPIO
Mx RAMs
Lx RAMs
DCSM
System Control
WD
SYSCLK
SYSCLK
GSx RAMs
XINT
CPUTIMERs
CLB
ECAP
I2C
ADC
CMPSS
CAN
HIC
DCC
HWBIST
BGCRC
One per SYSCLK peripheral
PCLKCRx
EQEP
PERx.SYSCLK
EPWM
HRCAL
PMBUS
LIN
FSI
ERAD
One per LSPCLK peripheral
PCLKCRx
LOSPCP
PERx.LSPCLK
SCI
SPI
LSPCLK
LSP
Divider
CLKSRCCTL2.CANxBCLKSEL
CAN Bit Clock
Figure 5-5. Clocking System
54
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
SYSPLL
OSCCLK
INTCLK
VCOCLK
PLLRAWCLK
÷
÷
VCO
(REFDIV+1)
(ODIV+1)
÷
IMULT
B15%%.-
+/7.6
fPLLRAWCLK =
×
(4'(&+8+1)
(1&+8+1)
Figure 5-6. System PLL
Copyright © 2020, Texas Instruments Incorporated
Specifications
55
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.8.3.2 Clock Frequencies, Requirements, and Characteristics
This section provides the frequencies and timing requirements of the input clocks, PLL lock times,
frequencies of the internal clocks, and the frequency and switching characteristics of the output clock.
5.8.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
Table 5-7 lists the frequency requirements for the input clocks. Table 5-8 lists the XTAL oscillator
characteristics. Table 5-9 lists the X1 timing requirements. Table 5-10 lists the APLL characteristics.
Table 5-11 lists the switching characteristics of the output clock, XCLKOUT. Table 5-12 provides the clock
frequencies for the internal clocks.
Table 5-7. Input Clock Frequency
MIN
10
MAX
20
UNIT
MHz
MHz
f(XTAL)
f(X1)
Frequency, X1/X2, from external crystal or resonator
Frequency, X1, from external oscillator
10
25
Table 5-8. XTAL Oscillator Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
–0.3
TYP
MAX
0.3 * VDDIO
VDDIO + 0.3
UNIT
X1 VIL
X1 VIH
Valid low-level input voltage
Valid high-level input voltage
V
V
0.7 * VDDIO
Table 5-9. X1 Timing Requirements
MIN
MAX UNIT
tf(X1)
Fall time, X1
Rise time, X1
6
6
ns
ns
tr(X1)
tw(X1L)
tw(X1H)
Pulse duration, X1 low as a percentage of tc(X1)
Pulse duration, X1 high as a percentage of tc(X1)
45%
45%
55%
55%
Table 5-10. APLL Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
PLL Lock time
SYS PLL Lock Time(1)
(1) The PLL lock time here defines the typical time that takes for the PLL to lock once PLL is enabled (SYSPLLCTL1[PLLENA]=1).
5µs + (1024 * (REFDIV + 1) * tc(OSCCLK)
)
us
Additional time to verify the PLL clock using Dual Clock Comparator (DCC) is not accounted here. TI recommends using the latest
example software from C2000Ware for initializing the PLLs. For the system PLL, see InitSysPll() or SysCtl_setClock().
Table 5-11. XCLKOUT Switching Characteristics(1)(2)
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
5
UNIT
ns
tf(XCO)
Fall time, XCLKOUT
Rise time, XCLKOUT
tr(XCO)
tw(XCOL)
tw(XCOH)
f(XCO)
5
ns
Pulse duration, XCLKOUT low
Pulse duration, XCLKOUT high
Frequency, XCLKOUT
H – 2
H – 2
H + 2
H + 2
50
ns
ns
MHz
(1) A load of 40 pF is assumed for these parameters.
(2) H = 0.5tc(XCO)
56
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Table 5-12. Internal Clock Frequencies
MIN
2
NOM
MAX
100
500
20
UNIT
MHz
ns
f(SYSCLK)
tc(SYSCLK)
f(INTCLK)
f(VCOCLK)
f(PLLRAWCLK)
f(PLL)
Frequency, device (system) clock
Period, device (system) clock
10
10
220
6
Frequency, system PLL going into VCO (after REFDIV)
Frequency, system PLL VCO (before ODIV)
Frequency, system PLL output (before SYSCLK divider)
Frequency, PLLSYSCLK
MHz
MHz
MHz
MHz
MHz
MHz
ns
500
200
100
2
(1)
f(PLL_LIMP)
f(LSP)
Frequency, PLL Limp Frequency
45/(ODIV+1)
Frequency, LSPCLK
Period, LSPCLK
2
100
500
tc(LSPCLK)
10
Frequency, OSCCLK (INTOSC1 or INTOSC2 or XTAL or
X1)
f(OSCCLK)
See respective clock
MHz
f(EPWM)
Frequency, EPWMCLK
Frequency, HRPWMCLK
100
100
MHz
MHz
f(HRPWM)
60
(1) PLL output frequency when OSCCLK is dead (Loss of OSCCLK causes PLL to Limp).
Copyright © 2020, Texas Instruments Incorporated
Specifications
57
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.8.3.3 Input Clocks and PLLs
In addition to the internal 0-pin oscillators, three types of external clock sources are supported:
•
•
•
A single-ended 3.3-V external clock. The clock signal should be connected to X1, as shown in
Figure 5-7, with the XTALCR.SE bit set to 1.
An external crystal. The crystal should be connected across X1 and X2 with its load capacitors
connected to VSS as shown in Figure 5-8.
An external resonator. The resonator should be connected across X1 and X2 with its ground
connected to VSS as shown in Figure 5-9.
Microcontroller
Microcontroller
GPIO19
X1
GPIO18
X2
GPIO18*
X2
GPIO19
X1
VSS
VSS
* Available as a
GPIO when X1 is
used as a clock
+3.3 V
VDD
Out
3.3-V Oscillator
Gnd
Figure 5-8. External Crystal
Figure 5-7. Single-ended 3.3-V External Clock
Microcontroller
GPIO18
X2
GPIO19
X1
VSS
Figure 5-9. External Resonator
58
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.8.3.4 Crystal Oscillator
When using a quartz crystal, it may be necessary to include a damping resistor (RD) in the crystal circuit to
prevent overdriving the crystal (drive level can be found in the crystal data sheet). In higher-frequency
applications (10 MHz or greater), RD is generally not required. If a damping resistor is required, RD should
be as small as possible because the size of the resistance affects start-up time (smaller RD = faster start-
up time). TI recommends that the crystal manufacturer characterize the crystal with the application board.
Table 5-13 lists the crystal oscillator parameters. Table 5-14 lists the crystal equivalent series resistance
(ESR) requirements. Table 5-15 lists the crystal oscillator electrical characteristics.
Table 5-13. Crystal Oscillator Parameters
MIN
MAX UNIT
CL1, CL2
C0
Load capacitance
12
24
7
pF
pF
Crystal shunt capacitance
Table 5-14. Crystal Equivalent Series Resistance (ESR) Requirements(1)(2)
MAXIMUM ESR (Ω)
(CL1 = CL2 = 12 pF)
MAXIMUM ESR (Ω)
(CL1 = CL2 = 24 pF)
CRYSTAL FREQUENCY (MHz)
10
12
14
16
18
20
55
50
50
45
45
45
110
95
90
75
65
50
(1) Crystal shunt capacitance (C0) should be less than or equal to 7 pF.
(2) ESR = Negative Resistance/3
Table 5-15. Crystal Oscillator Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ms
f = 20 MHz
ESR MAX = 50 Ω
CL1 = CL2 = 24 pF
C0 = 7 pF
Start-up time(1)
2
Crystal drive level (DL)
1
mW
(1) Start-up time is dependent on the crystal and tank circuit components. TI recommends that the crystal vendor characterize the
application with the chosen crystal.
Copyright © 2020, Texas Instruments Incorporated
Specifications
59
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.8.3.5 Internal Oscillators
To reduce production board costs and application development time, all F28002x devices contain two
independent internal oscillators, referred to as INTOSC1 and INTOSC2. By default, both oscillators are
enabled at power up. INTOSC2 is set as the source for the system reference clock (OSCCLK) and
INTOSC1 is set as the backup clock source. INTOSC1 can also be manually configured as the system
reference clock (OSCCLK). Table 5-16 provides the electrical characteristics of the internal oscillators to
determine if this module meets the clocking requirements of the application.
Table 5-16. INTOSC Characteristics
over recommended operating conditions (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
MIN
TYP
10
MAX
UNIT
MHz
%
Frequency, INTOSC1 and
INTOSC2
fINTOSC
9.7
10.3
Frequency stability at room
temperature
30°C, Nominal
VDD
±0.1
fINTOSC-STABILITY
Frequency stability
–3
3
%
tINT0SC-ST
Start-up and settling time
20
µs
60
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.8.4 Flash Parameters
Table 5-17 lists the minimum required Flash wait states with different clock sources and frequencies.
Table 5-17. Minimum Required Flash Wait States with Different Clock Sources and Frequencies(1)
EXTERNAL OSCILLATOR OR CRYSTAL
INTOSC1 OR INTOSC2
PROGRAM, ERASE,
PROGRAM, ERASE,
CPUCLK (MHz)
FLASH READ OR
BANK SLEEP, OR PUMP
EXECUTE
FLASH READ OR
EXECUTE
BANK SLEEP, OR PUMP
(2)
SLEEP
SLEEP
97 < CPUCLK ≤ 100
80 < CPUCLK ≤ 97
77 < CPUCLK ≤ 80
60 < CPUCLK ≤ 77
58 < CPUCLK ≤ 60
40 < CPUCLK ≤ 58
38 < CPUCLK ≤ 40
20 < CPUCLK ≤ 38
19 < CPUCLK ≤ 20
CPUCLK ≤ 19
5
4
4
3
3
2
2
1
1
0
4
3
2
1
0
4
3
2
1
0
(1) Minimum required FRDCNTL[RWAIT].
(2) PROGRAM, ERASE, or SLEEP operations require an extra wait state when using INTOSC as the clock source for the frequency ranges
indicated. Any wait state FRDCNTL[RWAIT] change must be made before beginning a PROGRAM, ERASE, or SLEEP mode operation.
This setting impacts both flash banks. Applications which perform simultaneous READ of one bank and PROGRAM or ERASE of the
other bank must use the higher RWAIT setting during the PROGRAM or ERASE operation or use a clock source or frequency with a
common wait state setting.
The F28002x devices have an improved 128-bit prefetch buffer that provides high flash code execution
efficiency across wait states. Figure 5-10 and Figure 5-11 illustrate typical efficiency across wait-state
settings compared to previous-generation devices with a 64-bit prefetch buffer. Wait-state execution
efficiency with a prefetch buffer will depend on how many branches are present in application software.
Two examples of linear code and if-then-else code are provided.
100%
90%
80%
70%
60%
50%
40%
30%
100%
95%
90%
85%
80%
75%
70%
65%
60%
55%
Flash with 64-Bit Prefetch
Flash with 128-Bit Prefetch
Flash with 64-Bit Prefetch
Flash with 128-Bit Prefetch
0
1
2
3
4
5
0
1
2
3
4
5
Wait State
Wait State
D005
D006
Figure 5-10. Application Code With Heavy 32-Bit Floating-Point
Math Instructions
Figure 5-11. Application Code With 16-Bit If-Else Instructions
Copyright © 2020, Texas Instruments Incorporated
Specifications
61
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Table 5-18 lists the Flash parameters.
Table 5-18. Flash Parameters
PARAMETER
MIN
TYP
150
50
MAX
300
UNIT
µs
128 data bits + 16 ECC bits
Program Time(1)
8KB sector
100
ms
EraseTime(2) at < 25 cycles
EraseTime(2) at 1000 cycles
EraseTime(2) at 2000 cycles
EraseTime(2) at 20K cycles
8KB sector
8KB sector
8KB sector
8KB sector
15
100
ms
25
350
ms
30
600
ms
120
4000
20000
ms
Nwec Write/Erase Cycles
tretention Data retention duration at TJ = 85oC
cycles
years
20
(1) Program time is at the maximum device frequency. Program time includes overhead of the flash state machine but does not include the
time to transfer the following into RAM:
• Code that uses flash API to program the flash
• Flash API itself
• Flash data to be programmed
In other words, the time indicated in this table is applicable after all the required code/data is available in the device RAM, ready for
programming. The transfer time will significantly vary depending on the speed of the JTAG debug probe used.
Program time calculation is based on programming 144 bits at a time at the specified operating frequency. Program time includes
Program verify by the CPU. The program time does not degrade with write/erase (W/E) cycling, but the erase time does.
Erase time includes Erase verify by the CPU and does not involve any data transfer.
(2) Erase time includes Erase verify by the CPU.
NOTE
The Main Array flash programming must be aligned to 64-bit address boundaries and each
64-bit word may only be programmed once per write/erase cycle.
The DCSM OTP programming must be aligned to 128-bit address boundaries and each 128-
bit word may only be programmed once. The exceptions are:
1. The DCSM Zx-LINKPOINTER1 and Zx-LINKPOINTER2 values in the DCSM OTP should
be programmed together, and may be programmed 1 bit at a time as required by the
DCSM operation.
2. The DCSM Zx-LINKPOINTER3 values in the DCSM OTP may be programmed 1 bit at a
time on a 64-bit boundary to separate it from Zx-PSWDLOCK, which must only be
programmed once.
62
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.8.5 Emulation/JTAG
The JTAG (IEEE Standard 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture) port
has four dedicated pins: TMS, TDI, TDO, and TCK. The cJTAG (IEEE Standard 1149.7-2009 for
Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture) port is a
compact JTAG interface requiring only two pins (TMS and TCK), which allows other device functionality to
be muxed to the traditional GPIO35 (TDI) and GPIO37 (TDO) pins.
Typically, no buffers are needed on the JTAG signals when the distance between the MCU target and the
JTAG header is smaller than 6 inches (15.24 cm), and no other devices are present on the JTAG chain.
Otherwise, each signal should be buffered. Additionally, for most JTAG debug probe operations at
10 MHz, no series resistors are needed on the JTAG signals. However, if high emulation speeds are
expected (35 MHz or so), 22-Ω resistors should be placed in series on each JTAG signal.
The PD (Power Detect) terminal of the JTAG debug probe header should be connected to the board's 3.3-
V supply. Header GND terminals should be connected to board ground. TDIS (Cable Disconnect Sense)
should also be connected to board ground. The JTAG clock should be looped from the header TCK output
terminal back to the RTCK input terminal of the header (to sense clock continuity by the JTAG debug
probe). This MCU does not support the EMU0 and EMU1 signals that are present on 14-pin and 20-pin
emulation headers. These signals should always be pulled up at the emulation header through a pair of
board pullup resistors ranging from 2.2 kΩ to 4.7 kΩ (depending on the drive strength of the debugger
ports). Typically, a 2.2-kΩ value is used.
Header terminal RESET is an open-drain output from the JTAG debug probe header that enables board
components to be reset through JTAG debug probe commands (available only through the 20-pin header).
Figure 5-12 shows how the 14-pin JTAG header connects to the MCU’s JTAG port signals. Figure 5-13
shows how to connect to the 20-pin JTAG header. The 20-pin JTAG header terminals EMU2, EMU3, and
EMU4 are not used and should be grounded.
For more information about hardware breakpoints and watchpoints, see Hardware Breakpoints and
Watchpoints for C28x in CCS.
For more information about JTAG emulation, see the XDS Target Connection Guide.
NOTE
JTAG Test Data Input (TDI) is the default mux selection for the pin. The internal pullup is
disabled by default. If this pin is used as JTAG TDI, the internal pullup should be enabled or
an external pullup added on the board to avoid a floating input. In the cJTAG option, this pin
can be used as GPIO.
JTAG Test Data Output (TDO) is the default mux selection for the pin. The internal pullup is
disabled by default. The TDO function will be in a tri-state condition when there is no JTAG
activity, leaving this pin floating. The internal pullup should be enabled or an external pullup
added on the board to avoid a floating GPIO input. In the cJTAG option, this pin can be used
as GPIO.
Copyright © 2020, Texas Instruments Incorporated
Specifications
63
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Distance between the header and the target
should be less than 6 inches (15.24 cm).
3.3 V
4.7 kΩ
3.3 V
10 kΩ
3.3 V
10 kΩ
2
1
TMS
TMS
TRST
TDI(A)
TDI
TDIS
KEY
3
5
4
GND
MCU
100 Ω
6
3.3 V
PD
TDO(A)
TCK
TDO
RTCK
TCK
EMU0
GND
GND
GND
EMU1
7
8
9
10
12
14
11
13
4.7 kΩ
4.7 kΩ
3.3 V
3.3 V
A. TDI and TDO connections are not required for cJTAG option and these pins can be used as GPIOs instead.
Figure 5-12. Connecting to the 14-Pin JTAG Header
Distance between the header and the target
should be less than 6 inches (15.24 cm).
3.3 V
4.7 kΩ
2
1
TMS
TMS
TRST
3.3 V
10 kΩ
3.3 V
10 kΩ
TDI(A)
TDI
TDIS
KEY
GND
3
5
4
MCU
100 Ω
6
3.3V
PD
TDO(A)
TDO
GND
GND
GND
EMU1
GND
EMU3
GND
7
8
9
10
12
14
16
18
20
RTCK
TCK
11
13
15
17
19
TCK
Ω
4.7 kΩ
4.7 k
3.3 V
EMU0
RESET
EMU2
EMU4
3.3 V
Open
Drain
A low pulse from the JTAG debug probe
can be tied with other reset sources
to reset the board.
GND
GND
A. TDI and TDO connections are not required for cJTAG option and these pins can be used as GPIOs instead.
Figure 5-13. Connecting to the 20-Pin JTAG Header
64
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.8.5.1 JTAG Electrical Data and Timing
Table 5-19 lists the JTAG timing requirements. Table 5-20 lists the JTAG switching characteristics.
Figure 5-14 shows the JTAG timing.
Table 5-19. JTAG Timing Requirements
NO.
MIN
66.66
26.66
26.66
13
MAX
UNIT
ns
1
tc(TCK)
Cycle time, TCK
1a
1b
tw(TCKH)
Pulse duration, TCK high (40% of tc)
Pulse duration, TCK low (40% of tc)
Input setup time, TDI valid to TCK high
Input setup time, TMS valid to TCK high
Input hold time, TDI valid from TCK high
Input hold time, TMS valid from TCK high
ns
tw(TCKL)
ns
tsu(TDI-TCKH)
tsu(TMS-TCKH)
th(TCKH-TDI)
th(TCKH-TMS)
3
4
ns
ns
13
7
7
Table 5-20. JTAG Switching Characteristics
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER
MIN
MAX
UNIT
2
td(TCKL-TDO)
Delay time, TCK low to TDO valid
6
25
ns
1
1a
1b
TCK
TDO
2
3
4
TDI/TMS
Figure 5-14. JTAG Timing
Copyright © 2020, Texas Instruments Incorporated
Specifications
65
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.8.5.2 cJTAG Electrical Data and Timing
Table 5-21 lists the cJTAG timing requirements. Table 5-22 lists the cJTAG switching characteristics.
Figure 5-15 shows the cJTAG timing.
Table 5-21. cJTAG Timing Requirements
NO.
MIN
100
40
40
15
15
2
MAX
UNIT
ns
1
tc(TCK)
Cycle time, TCK
1a
1b
tw(TCKH)
Pulse duration, TCK high (40% of tc)
Pulse duration, TCK low (40% of tc)
Input setup time, TMS valid to TCK high
Input setup time, TMS valid to TCK low
Input hold time, TMS valid from TCK high
Input hold time, TMS valid from TCK low
ns
tw(TCKL)
ns
tsu(TMS-TCKH)
tsu(TMS-TCKL)
th(TCKH-TMS)
th(TCKL-TMS)
ns
3
4
ns
ns
2
ns
Table 5-22. cJTAG Switching Characteristics
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER
MIN
MAX
20
UNIT
ns
2
5
td(TCKL-TMS)
Delay time, TCK low to TMS valid
Delay time, TCK high to TMS disable
6
tdis(TCKH-TMS)
20
ns
1
1a
1b
2
3
3
4
4
5
TCK
TMS Input
TMS Output
TMS Input
TMS
Figure 5-15. cJTAG Timing
66
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.8.6 GPIO Electrical Data and Timing
The peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. On reset, GPIO
pins are configured as inputs. For specific inputs, the user can also select the number of input qualification
cycles to filter unwanted noise glitches.
The GPIO module contains an Output X-BAR which allows an assortment of internal signals to be routed
to a GPIO in the GPIO mux positions denoted as OUTPUTXBARx. The GPIO module also contains an
Input X-BAR which is used to route signals from any GPIO input to different IP blocks such as the ADCs,
eCAPs, ePWMs, and external interrupts. For more details, see the X-BAR chapter in the TMS320F28002x
Microcontrollers Technical Reference Manual.
5.8.6.1 GPIO – Output Timing
Table 5-23 lists the general-purpose output switching characteristics. Figure 5-16 shows the general-
purpose output timing.
Table 5-23. General-Purpose Output Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
Rise time, GPIO switching low to high
MIN
MAX
8(1)
8(1)
25
UNIT
ns
tr(GPIO)
tf(GPIO)
fGPIO
All GPIOs
All GPIOs
Fall time, GPIO switching high to low
Toggling frequency, all GPIOs
ns
MHz
(1) Rise time and fall time vary with load. These values assume a 40-pF load.
GPIO
tr(GPIO)
tf(GPIO)
Figure 5-16. General-Purpose Output Timing
Copyright © 2020, Texas Instruments Incorporated
Specifications
67
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.8.6.2 GPIO – Input Timing
Table 5-24 lists the general-purpose input timing requirements. Figure 5-17 shows the sampling mode.
Table 5-24. General-Purpose Input Timing Requirements
MIN
1tc(SYSCLK)
MAX
UNIT
cycles
cycles
cycles
QUALPRD = 0
tw(SP)
Sampling period
QUALPRD ≠ 0
2tc(SYSCLK) * QUALPRD
tw(SP) * (n(1) – 1)
tw(IQSW)
Input qualifier sampling window
Pulse duration, GPIO low/high
Synchronous mode
With input qualifier
2tc(SYSCLK)
(2)
tw(GPI)
tw(IQSW) + tw(SP) + 1tc(SYSCLK)
(1) "n" represents the number of qualification samples as defined by GPxQSELn register.
(2) For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.
(A)
GPIO Signal
GPxQSELn = 1,0 (6 samples)
1
1
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
tw(SP)
Sampling Period determined
by GPxCTRL[QUALPRD](B)
tw(IQSW)
(SYSCLK cycle * 2 * QUALPRD) * 5(C)
Sampling Window
SYSCLK
QUALPRD = 1
(SYSCLK/2)
(D)
Output From
Qualifier
A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It
can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLK cycle. For any other value "n",
the qualification sampling period in 2n SYSCLK cycles (that is, at every 2n SYSCLK cycles, the GPIO pin will be
sampled).
B. The qualification period selected through the GPxCTRL register applies to groups of eight GPIO pins.
C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is
used.
D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLK cycles or
greater. In other words, the inputs should be stable for (5 × QUALPRD × 2) SYSCLK cycles. This would ensure
5 sampling periods for detection to occur. Because external signals are driven asynchronously, an 13-SYSCLK-wide
pulse ensures reliable recognition.
Figure 5-17. Sampling Mode
68
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.8.6.3 Sampling Window Width for Input Signals
The following section summarizes the sampling window width for input signals for various input qualifier
configurations.
Sampling frequency denotes how often a signal is sampled with respect to SYSCLK.
Sampling frequency = SYSCLK/(2 × QUALPRD), if QUALPRD ≠ 0
Sampling frequency = SYSCLK, if QUALPRD = 0
Sampling period = SYSCLK cycle × 2 × QUALPRD, if QUALPRD ≠ 0
In the previous equations, SYSCLK cycle indicates the time period of SYSCLK.
Sampling period = SYSCLK cycle, if QUALPRD = 0
In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of
the signal. This is determined by the value written to GPxQSELn register.
Case 1:
Qualification using 3 samples
Sampling window width = (SYSCLK cycle × 2 × QUALPRD) × 2, if QUALPRD ≠ 0
Sampling window width = (SYSCLK cycle) × 2, if QUALPRD = 0
Case 2:
Qualification using 6 samples
Sampling window width = (SYSCLK cycle × 2 × QUALPRD) × 5, if QUALPRD ≠ 0
Sampling window width = (SYSCLK cycle) × 5, if QUALPRD = 0
Figure 5-18 shows the general-purpose input timing.
SYSCLK
GPIOxn
tw(GPI)
Figure 5-18. General-Purpose Input Timing
Copyright © 2020, Texas Instruments Incorporated
Specifications
69
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.8.7 Interrupts
The C28x CPU has fourteen peripheral interrupt lines. Two of them (INT13 and INT14) are connected
directly to CPU timers 1 and 2, respectively. The remaining twelve are connected to peripheral interrupt
signals through the enhanced Peripheral Interrupt Expansion (ePIE) module. The ePIE multiplexes up to
sixteen peripheral interrupts into each CPU interrupt line. It also expands the vector table to allow each
interrupt to have its own ISR. This allows the CPU to support a large number of peripherals.
An interrupt path is divided into three stages—the peripheral, the ePIE, and the CPU. Each stage has its
own enable and flag registers. This system allows the CPU to handle one interrupt while others are
pending, implement and prioritize nested interrupts in software, and disable interrupts during certain
critical tasks.
Figure 5-19 shows the interrupt architecture for this device.
TINT0
TIMER0
LPMINT
WDINT
LPM Logic
WD
WAKEINT
NMI module
ERAD
NMI
RTOSINT
CPU
INPUTXBAR4
XINT1 Control
INPUTXBAR5
INPUTXBAR6
INPUTXBAR13
INPUTXBAR14
XINT2 Control
XINT3 Control
XINT4 Control
XINT5 Control
GPIO0
to
GPIOx
ePIE
INT1
to
INT12
Input
X-BAR
TIMER1
TIMER2
INT13
INT14
Peripherals
See ePIE Table
Figure 5-19. Device Interrupt Architecture
70
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.8.7.1 External Interrupt (XINT) Electrical Data and Timing
Table 5-25 lists the external interrupt timing requirements. Table 5-26 lists the external interrupt switching
characteristics. Figure 5-20 shows the external interrupt timing.
Table 5-25. External Interrupt Timing Requirements(1)
MIN
2tc(SYSCLK)
MAX
UNIT
Synchronous
With qualifier
tw(INT)
Pulse duration, INT input low/high
cycles
tw(IQSW) + tw(SP) + 1tc(SYSCLK)
(1) For an explanation of the input qualifier parameters, see Table 5-24.
Table 5-26. External Interrupt Switching Characteristics(1)
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
td(INT) Delay time, INT low/high to interrupt-vector fetch(2)
tw(IQSW) + 14tc(SYSCLK)
tw(IQSW) + tw(SP) + 14tc(SYSCLK)
cycles
(1) For an explanation of the input qualifier parameters, see Table 5-24.
(2) This assumes that the ISR is in a single-cycle memory.
tw(INT)
XINT1, XINT2, XINT3,
XINT4, XINT5
td(INT)
Address bus
(internal)
Interrupt Vector
Figure 5-20. External Interrupt Timing
Copyright © 2020, Texas Instruments Incorporated
Specifications
71
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.8.8 Low-Power Modes
This device has HALT, IDLE and STANDBY as clock-gating low-power modes.
Further details, as well as the entry and exit procedure, for all of the low-power modes can be found in the
Low Power Modes section of the TMS320F28002x Microcontrollers Technical Reference Manual.
5.8.8.1 Clock-Gating Low-Power Modes
IDLE and HALT modes on this device are similar to those on other C28x devices. Table 5-27 describes
the effect on the system when any of the clock-gating low-power modes are entered.
Table 5-27. Effect of Clock-Gating Low-Power Modes on the Device
MODULES/
CLOCK DOMAIN
IDLE
STANDBY
HALT
SYSCLK
Active
Gated
Active
Gated
Gated
Gated
Gated
Gated
Gated
CPUCLK
Clock to modules
connected to
PERx.SYSCLK
WDCLK
PLL
Active
Active
Gated if CLKSRCCTL1.WDHALTI = 0
Software must power down PLL before entering HALT.
Powered down if CLKSRCCTL1.WDHALTI = 0
Powered down if CLKSRCCTL1.WDHALTI = 0
Powered
Powered
Powered
Powered
Powered
Powered
Powered
Powered
Powered
Powered
Powered
INTOSC1
INTOSC2
Flash(1)
XTAL(2)
Powered
(1) The Flash module is not powered down by hardware in any LPM. It may be powered down using software if required by the application.
For more information, see the Flash and OTP Memory section of the System Control chapter in the TMS320F28002x Microcontrollers
Technical Reference Manual.
(2) The XTAL is not powered down by hardware in any LPM. It may be powered down by software setting the XTALCR.OSCOFF bit to 1.
This can be done at any time during the application if the XTAL is not required.
72
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.8.8.2 Low-Power Mode Wake-up Timing
Table 5-28 lists the IDLE mode timing requirements, Table 5-29 lists the switching characteristics, and
Figure 5-21 shows the timing diagram for IDLE mode.
Table 5-28. IDLE Mode Timing Requirements(1)
MIN
2tc(SYSCLK)
MAX
UNIT
Without input qualifier
With input qualifier
tw(WAKE)
Pulse duration, external wake-up signal
cycles
2tc(SYSCLK) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Table 5-24.
Table 5-29. IDLE Mode Switching Characteristics(1)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Without input qualifier
With input qualifier
MIN
MAX UNIT
40tc(SYSCLK) cycles
From Flash (active state)
40tc(SYSCLK) + tw(WAKE) cycles
(3)
Without input qualifier
6700tc(SYSCLK)
cycles
cycles
Delay time, external wake signal to
(3)
td(WAKE-IDLE)
From Flash (sleep state)
From RAM
program execution resume(2)
6700tc(SYSCLK)
+
With input qualifier
tw(WAKE)
Without input qualifier
With input qualifier
25tc(SYSCLK) cycles
25tc(SYSCLK) + tw(WAKE) cycles
(1) For an explanation of the input qualifier parameters, see Table 5-24.
(2) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered
by the wake-up signal) involves additional latency.
(3) This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and
FPAC1[PSLEEP]. This value can be realized when SYSCLK is 200 MHz, RWAIT is 3, and FPAC1[PSLEEP] is 0x860.
td(WAKE-IDLE)
Address/Data
(internal)
XCLKOUT
tw(WAKE)
WAKE(A)
A. WAKE can be any enabled interrupt, WDINT or XRSn. After the IDLE instruction is executed, a delay of five OSCCLK
cycles (minimum) is needed before the wake-up signal could be asserted.
Figure 5-21. IDLE Entry and Exit Timing Diagram
Copyright © 2020, Texas Instruments Incorporated
Specifications
73
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Table 5-30 lists the STANDBY mode timing requirements, Table 5-31 lists the switching characteristics,
and Figure 5-22 shows the timing diagram for STANDBY mode.
Table 5-30. STANDBY Mode Timing Requirements
MIN
MAX
UNIT
QUALSTDBY = 0 | 2tc(OSCCLK)
QUALSTDBY > 0 |
(2 + QUALSTDBY)tc(OSCCLK)
3tc(OSCCLK)
Pulse duration, external
wake-up signal
tw(WAKE-INT)
cycles
(2 + QUALSTDBY) * tc(OSCCLK)
(1)
(1) QUALSTDBY is a 6-bit field in the LPMCR register.
Table 5-31. STANDBY Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
Delay time, IDLE instruction executed to
XCLKOUT stop
td(IDLE-XCOS)
16tc(INTOSC1) cycles
Wakeup from flash
(Flash module in
active state)
td(WAKE-
STBY)
175tc(SYSCLK) + tw(WAKE-INT) cycles
Delay time, external wake signal to program Wakeup from flash
td(WAKE-
STBY)
execution resume(1)
(Flash module in
sleep state)
6700tc(SYSCLK)(2) + tw(WAKE-INT) cycles
td(WAKE-
STBY)
Wakeup from RAM
3tc(OSC) + 15tc(SYSCLK) + tw(WAKE-INT) cycles
(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered
by the wake-up signal) involves additional latency.
(2) This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and
FPAC1[PSLEEP]. This value can be realized when SYSCLK is 200 MHz, RWAIT is 3, and FPAC1[PSLEEP] is 0x860.
(C)
(F)
(A)
(B)
(D)(E)
(G)
Device
Status
STANDBY
STANDBY
Normal Execution
Flushing Pipeline
Wake-up
Signal
tw(WAKE-INT)
td(WAKE-STBY)
OSCCLK
XCLKOUT
td(IDLE-XCOS)
A. IDLE instruction is executed to put the device into STANDBY mode.
B. The LPM block responds to the STANDBY signal, SYSCLK is held for a maximum 16 INTOSC1 clock cycles before
being turned off. This delay enables the CPU pipeline and any other pending operations to flush properly.
C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in
STANDBY mode. After the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum) is needed before
the wake-up signal could be asserted.
D. The external wake-up signal is driven active.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement.
Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wakeup behavior of the
device will not be deterministic and the device may not exit low-power mode for subsequent wakeup pulses.
F. After a latency period, the STANDBY mode is exited.
G. Normal execution resumes. The device will respond to the interrupt (if enabled).
Figure 5-22. STANDBY Entry and Exit Timing Diagram
74
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Table 5-32 lists the HALT mode timing requirements, Table 5-33 lists the switching characteristics, and
Figure 5-23 shows the timing diagram for HALT mode.
Table 5-32. HALT Mode Timing Requirements
MIN
toscst + 2tc(OSCCLK)
toscst + 8tc(OSCCLK)
MAX
UNIT
cycles
cycles
tw(WAKE-GPIO)
tw(WAKE-XRS)
Pulse duration, GPIO wake-up signal(1)
Pulse duration, XRS wake-up signal(1)
(1) For applications using X1/X2 for OSCCLK, the user must characterize their specific oscillator start-up time as it is dependent on
circuit/layout external to the device. See Table 5-15 for more information. For applications using INTOSC1 or INTOSC2 for OSCCLK,
see Section 5.8.3.5 for toscst. Oscillator start-up time does not apply to applications using a single-ended crystal on the X1 pin, as it is
powered externally to the device.
Table 5-33. HALT Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
Delay time, IDLE instruction executed to XCLKOUT
stop
td(IDLE-XCOS)
16tc(INTOSC1)
cycles
Delay time, external wake signal end to CPU1
program execution resume
Wakeup from Flash - Flash module in active state
Wakeup from Flash - Flash module in sleep state
Wakeup from RAM
75tc(OSCCLK)
td(WAKE-HALT)
cycles
(1)
17500tc(OSCCLK)
75tc(OSCCLK)
(1) This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and
FPAC1[PSLEEP]. This value can be realized when SYSCLK is 200 MHz, RWAIT is 3, and FPAC1[PSLEEP] is 0x860.
(C)
(F)
(A)
(B)
(D)(E)
HALT
(G)
Device
Status
HALT
Flushing Pipeline
Normal
Execution
GPIOn
td(WAKE-HALT)
tw(WAKE-GPIO)
OSCCLK
Oscillator Start-up Time
XCLKOUT
td(IDLE-XCOS)
A. IDLE instruction is executed to put the device into HALT mode.
B. The LPM block responds to the HALT signal, SYSCLK is held for a maximum 16 INTOSC1 clock cycles before being
turned off. This delay enables the CPU pipeline and any other pending operations to flush properly.
C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as
the clock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes very
little power. It is possible to keep the zero-pin internal oscillators (INTOSC1 and INTOSC2) and the watchdog alive in
HALT MODE. This is done by writing 1 to CLKSRCCTL1.WDHALTI. After the IDLE instruction is executed, a delay of
five OSCCLK cycles (minimum) is needed before the wake-up signal could be asserted.
D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator
wake-up sequence is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This
enables the provision of a clean clock signal during the PLL lock sequence. Because the falling edge of the GPIO pin
asynchronously begins the wake-up procedure, care should be taken to maintain a low noise environment before
entering and during HALT mode.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement.
Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the
device will not be deterministic and the device may not exit low-power mode for subsequent wake-up pulses.
F. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after some latency. The
HALT mode is now exited.
G. Normal operation resumes.
H. The user must relock the PLL upon HALT wakeup to ensure a stable PLL lock.
Figure 5-23. HALT Entry and Exit Timing Diagram
Copyright © 2020, Texas Instruments Incorporated
Specifications
75
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.9 Analog Peripherals
The analog subsystem module is described in this section.
The analog modules on this device include the ADC, temperature sensor, and CMPSS.
The analog subsystem has the following features:
•
Flexible voltage references
–
The ADCs are referenced to VREFHI and VSSA pins
•
VREFHI pin voltage can be driven in externally or can be generated by an internal bandgap
voltage reference
•
The internal voltage reference range can be selected to be 0V to 3.3V or 0V to 2.5V
–
The comparator DACs are referenced to VDDA and VSSA
Alternately, these DACs can be referenced to the VDAC pin and VSSA
Flexible pin usage
•
•
–
–
Comparator subsystem inputs and digital inputs are multiplexed with ADC inputs
Internal connection to VREFLO on all ADCs for offset self-calibration
Figure 5-24 shows the Analog Subsystem Block Diagram for the 80-pin PN and 64-pin PM LQFPs.
Figure 5-25 shows the Analog Subsystem Block Diagram for the 48-pin PT LQFP.
Table 5-34 lists the analog pins and internal connections. Table 5-35 lists descriptions of analog signals.
Figure 5-24. Analog Subsystem Block Diagram (80-Pin PN and 64-Pin PM LQFPs)
76
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Figure 5-25. Analog Subsystem Block Diagram (48-Pin PT LQFP)
Copyright © 2020, Texas Instruments Incorporated
Specifications
77
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
AIO Input
Table 5-34. Analog Pins and Internal Connections
Package Pin
ADC
Comparator Subsystem (MUX)
Pin Name
VREFHI
High
Positive
High
Low
Low
Negative
80 QFP 64 QFP 48 QFN
A
C
Negative
Positive
20
21
16
17
12
13
VREFLO
Analog Group 1
A6
A13
C13
CMP1
10
13
14
16
18
6
4(1)
6
A6
A2
-
CMP1 (HPMXSEL=2)
CMP1 (HPMXSEL=0)
CMP1 (HPMXSEL=3)
CMP1 (HPMXSEL=1)
CMP1 (HPMXSEL=4)
CMP1 (LPMXSEL=2)
CMP1 (LPMXSEL=0)
CMP1 (LPMXSEL=3)
CMP1 (LPMXSEL=1)
CMP1 (LPMXSEL=4)
CMP2
AIO228
AIO224
AIO233
AIO237
AIO232
A2/C9
9
C9
C7
C0
-
A15/C7
10
12
14
7
A15
A11
A1
CMP1 (HNMXSEL=0)
CMP1 (HNMXSEL=1)
CMP1 (LNMXSEL=0)
CMP1 (LNMXSEL=1)
A11/C0
8
A1
10
Analog Group 2
A10/C10
Analog Group 3
C6
29
25
21
A10
C10
CMP2 (HPMXSEL=3)
CMP2 (HNMXSEL=0)
CMP2 (LPMXSEL=3)
CMP3
CMP2 (LNMXSEL=0)
AIO230
11
12
15
17
19
7
4(1)
5
-
C6
C5
CMP3 (HPMXSEL=0)
CMP3 (HPMXSEL=3)
CMP3 (HPMXSEL=4)
CMP3 (HPMXSEL=1)
CMP3 (HPMXSEL=2)
CMP3 (LPMXSEL=0)
CMP3 (LPMXSEL=3)
CMP3 (LPMXSEL=4)
CMP3 (LPMXSEL=1)
CMP3 (LPMXSEL=2)
CMP4
AIO226
AIO242
AIO239
AIO244
AIO231
A3/C5/VDAC(2)
8
A3
A14
A5
A0
CMP3 (HNMXSEL=0)
CMP3 (HNMXSEL=1)
CMP3 (LNMXSEL=0)
CMP3 (LNMXSEL=1)
A14/C4
11
13
15
-
C4
A5/C2
9
C2
A0/C15
11
C15
Analog Group 4
A7/C3
23
19
15
A7
C3
CMP4 (HPMXSEL=1)
CMP4 (HNMXSEL=1)
CMP2 (HNMXSEL=1)
CMP4 (LPMXSEL=1)
CMP2/4
CMP4 (LNMXSEL=1)
CMP2 (LNMXSEL=1)
AIO245
Combined Analog Group 2/4
CMP2 (HPMXSEL=1)
CMP4 (HPMXSEL=2)
CMP2 (LPMXSEL=1)
CMP4 (LPMXSEL=2)
A12/C1
A8/C11
A4/C14
A9/C8
22
24
27
28
18
20
23
24
14
16
19
20
A12
A8
C1
C11
C14
C8
AIO238
AIO241
AIO225
AIO227
CMP2 (HPMXSEL=4)
CMP4 (HPMXSEL=4)
CMP2 (LPMXSEL=4)
CMP4 (LPMXSEL=4)
CMP2 (HPMXSEL=0)
CMP4 (HPMXSEL=3)
CMP2 (LPMXSEL=0)
CMP4 (LPMXSEL=3)
A4
CMP4 (HNMXSEL=0)
CMP4 (LNMXSEL=0)
CMP2 (HPMXSEL=2)
CMP4 (HPMXSEL=0)
CMP2 (LPMXSEL=2)
CMP4 (LPMXSEL=0)
A9
Other Analog
TempSensor(3)
-
-
-
-
C12
(1) A6 and C6 is double bonded as pin # 4.
(2) Optional external reference voltage for on-chip COMPDACs. There is an internal capacitance to VSSA on this pin whether used for ADC input or COMPDAC reference. If used as a VDAC
reference, place at least a 1-µF capacitor on this pin.
(3) Internal connection only; does not come to a device pin.
78
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Table 5-35. Analog Signal Descriptions
SIGNAL NAME
DESCRIPTION
AIOx
Digital input on ADC pin
Ax
ADC A Input
Cx
ADC C Input
CMPx_HNy
CMPx_HPy
CMPx_LNy
CMPx_LPy
TempSensor
Comparator subsystem high comparator negative input
Comparator subsystem high comparator positive input
Comparator subsystem low comparator negative input
Comparator subsystem low comparator positive input
Internal temperature sensor
Optional external reference voltage for on-chip COMPDACs. There is an internal capacitance to VSSA on this
pin whether used for ADC input or COMPDAC reference which cannot be disabled. If this pin is being used as
a reference for the on-chip COMPDACs, place at least a 1-uF capacitor on this pin.
VDAC
Copyright © 2020, Texas Instruments Incorporated
Specifications
79
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.9.1 Analog-to-Digital Converter (ADC)
The ADC module described here is a successive approximation (SAR) style ADC with resolution of
12 bits. This section refers to the analog circuits of the converter as the “core,” and includes the channel-
select MUX, the sample-and-hold (S/H) circuit, the successive approximation circuits, voltage reference
circuits, and other analog support circuits. The digital circuits of the converter are referred to as the
“wrapper” and include logic for programmable conversions, result registers, interfaces to analog circuits,
interfaces to the peripheral buses, post-processing circuits, and interfaces to other on-chip modules.
Each ADC module consists of a single sample-and-hold (S/H) circuit. The ADC module is designed to be
duplicated multiple times on the same chip, allowing simultaneous sampling or independent operation of
multiple ADCs. The ADC wrapper is start-of-conversion (SOC)-based (see the SOC Principle of Operation
section of the Analog-to-Digital Converter (ADC) chapter in the TMS320F28002x Microcontrollers
Technical Reference Manual).
Each ADC has the following features:
•
•
•
•
•
•
•
•
Resolution of 12 bits
Ratiometric external reference set by VREFHI/VREFLO
Selectable internal reference of 2.5 V or 3.3 V
Single-ended signaling
Input multiplexer with up to 16 channels
16 configurable SOCs
16 individually addressable result registers
Multiple trigger sources
–
–
–
–
–
S/W: software immediate start
All ePWMs: ADCSOC A or B
GPIO XINT2
CPU Timers 0/1/2
ADCINT1/2
•
•
•
Four flexible PIE interrupts
Burst-mode triggering option
Four post-processing blocks, each with:
–
–
–
–
Saturating offset calibration
Error from setpoint calculation
High, low, and zero-crossing compare, with interrupt and ePWM trip capability
Trigger-to-sample delay capture
NOTE
Not every channel may be pinned out from all ADCs. See to determine which channels are
available.
80
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
The block diagram for the ADC core and ADC wrapper are shown in Figure 5-26.
Analog-to-Digital Core
Analog-to-Digital Wrapper Logic
Input Circuit
SOCx (0-15)
CHSEL
[15:0]
[15:0]
[15:0]
SOC Arbitration
& Control
ACQPS
CHSEL
ADCIN0
ADCIN1
ADCIN2
ADCIN3
ADCIN4
ADCIN5
ADCIN6
ADCIN7
ADCIN8
ADCIN9
ADCIN10
ADCIN11
ADCIN12
ADCIN13
ADCIN14
ADCIN15
0
1
ADCSOC
2
3
4
5
ADCCOUNTER
TRIGGER[15:0]
6
VIN
+
DOUT
7
8
VIN-
9
10
11
12
13
14
15
SOC Delay
Timestamp
Trigger
Timestamp
Converter
S/H Circuit
RESULT
-
+
ADCPPBxOFFCAL
ꢀ
saturate
+
ADCPPBxOFFREF
-
ADCPPBxRESULT
ADCEVT
ꢀ
VREFHI
Event
Logic
CONFIG
ADCEVTINT
Bandgap
Reference Circuit
1.65-V Output
(3.3-V Range)
or
1
Post Processing Block (1-4)
Interrupt Block (1-4)
0
2.5-V Output
(2.5-V Range)
ADCINT1-4
VREFLO
Analog System Control
ANAREFSEL
ANAREFx2PSSEL
Reference Voltage Levels
Figure 5-26. ADC Module Block Diagram
Copyright © 2020, Texas Instruments Incorporated
Specifications
81
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.9.1.1 ADC Configurability
Some ADC configurations are individually controlled by the SOCs, while others are globally controlled per
ADC module. Table 5-36 summarizes the basic ADC options and their level of configurability.
Table 5-36. ADC Options and Configuration Levels
OPTIONS
CONFIGURABILITY
Clock
Per module(1)
Resolution
Signal mode
Not configurable (12-bit resolution only)
Not configurable (single-ended signal mode only)
Reference voltage source
Trigger source
Common for both ADC modules
Per SOC(1)
Converted channel
Acquisition window duration
EOC location
Per SOC
Per SOC(1)
Per module
Burst mode
Per module(1)
(1) Writing these values differently to different ADC modules could cause the ADCs to operate
asynchronously. For guidance on when the ADCs are operating synchronously or asynchronously, see
the Ensuring Synchronous Operation section of the Analog-to-Digital Converter (ADC) chapter in the
TMS320F28002x Microcontrollers Technical Reference Manual.
5.9.1.1.1 Signal Mode
The ADC supports single-ended signaling. The input voltage to the converter is sampled through a single
pin (ADCINx), referenced to VREFLO. Figure 5-27 shows the single-ended signaling mode.
Pin Voltage
VREFHI
VREFHI
ADCINx
ADCINx
ADC
VREFHI/2
VREFLO
VREFLO
(VSSA)
Digital Output
2n - 1
ADC Vin
0
Figure 5-27. Single-ended Signaling Mode
82
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.9.1.2 ADC Electrical Data and Timing
Table 5-37 lists the ADC operating conditions. Table 5-38 lists the ADC electrical characteristics.
Table 5-37. ADC Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
ADCCLK (derived from PERx.SYSCLK)
Sample rate
TEST CONDITIONS
MIN
TYP
MAX
50
UNIT
MHz
5
100-MHz SYSCLK
3.45
MSPS
Sample window duration (set by ACQPS and
PERx.SYSCLK)(1)
With 50 Ω or less Rs
75
ns
VREFHI
External Reference
2.4 2.5 or 3.0
VDDA
V
V
V
V
V
V
V
V
Internal Reference = 3.3V Range
Internal Reference = 2.5V Range
1.65
2.5
VREFHI(2)
VREFLO
VSSA
VSSA
VDDA
3.3
VREFHI - VREFLO
2.4
Internal Reference = 3.3 V Range
Internal Reference = 2.5 V Range
External Reference
0
0
Conversion range
2.5
VREFLO
VREFHI
(1) The sample window must also be at least as long as 1 ADCCLK cycle for correct ADC operation.
(2) In internal reference mode, the reference voltage is driven out of the VREFHI pin by the device. The user should not drive a voltage into
the pin in this mode.
NOTE
The ADC inputs should be kept below VDDA + 0.3 V during operation. If an ADC input
exceeds this level, the VREF internal to the device may be disturbed, which can impact results
for other ADC inputs using the same VREF
.
NOTE
The VREFHI pin must be kept below VDDA + 0.3 V to ensure proper functional operation. If
the VREFHI pin exceeds this level, a blocking circuit may activate, and the internal value of
VREFHI may float to 0 V internally, giving improper ADC conversion.
Copyright © 2020, Texas Instruments Incorporated
Specifications
83
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Table 5-38. ADC Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
General
ADCCLK Conversion Cycles
100-MHz SYSCLK
10.1
11 ADCCLKs
External Reference mode
Internal Reference mode
500
µs
µs
5000
Power Up Time
Internal Reference mode, when switching between
2.5-V range and 3.3-V range.
5000
µs
µA
µF
VREFHI input current(1)
130
Internal Reference Capacitor
Value(2)
2.2
2.2
External Reference Capacitor
Value(2)
µF
DC Characteristics
Internal reference
External reference
–45
–5
45
5
Gain Error
LSB
±3
±2
2
Offset Error
Channel-to-Channel Gain Error(3)
–5
5
LSB
LSB
Channel-to-Channel Offset
Error(3)
2
LSB
ADC-to-ADC Gain Error(4)
ADC-to-ADC Offset Error(4)
DNL Error
Identical VREFHI and VREFLO for all ADCs
Identical VREFHI and VREFLO for all ADCs
4
2
LSB
LSB
LSB
LSB
LSBs
>–1
–2
±0.5
±1.0
1
2
1
INL Error
ADC-to-ADC Isolation
AC Characteristics
VREFHI = 2.5 V, synchronous ADCs
–1
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from X1
68.8
60.1
SNR(5)
dB
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from
INTOSC
THD(5)
SFDR(5)
VREFHI = 2.5 V, fin = 100 kHz
–80.6
79.2
68.5
dB
dB
VREFHI = 2.5 V, fin = 100 kHz
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from X1
SINAD(5)
dB
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from
INTOSC
60.0
11.0
11.0
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from
X1, Single ADC
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from
X1, synchronous ADCs
ENOB(5)
bits
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from
X1, asynchronous ADCs
Not
Supported
VDD = 1.2-V DC + 100mV
DC up to Sine at 1 kHz
60
57
60
57
VDD = 1.2-V DC + 100 mV
DC up to Sine at 300 kHz
PSRR
dB
VDDA = 3.3-V DC + 200 mV
DC up to Sine at 1 kHz
VDDA = 3.3-V DC + 200 mV
Sine at 900 kHz
(1) Load current on VREFHI increases when ADC input is greater than VDDA. This causes inaccurate conversions.
(2) A ceramic capacitor with package size of 0805 or smaller is preferred. Up to ±20% tolerance is acceptable.
(3) Variation across all channels belonging to the same ADC module.
(4) Worst case variation compared to other ADC modules.
(5) IO activity is minimized on pins adjacent to ADC input and VREFHI pins as part of best practices to reduce capacitive coupling and
crosstalk.
84
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.9.1.2.1 ADC Input Model
The ADC input characteristics are given by Table 5-39 and Figure 5-28.
Table 5-39. Input Model Parameters
DESCRIPTION
REFERENCE MODE
VALUE
Cp
Parasitic input capacitance
All
See Table 5-40
External Reference, 2.5-V Internal
Reference
500 Ω
860 Ω
Ron
Sampling switch resistance
3.3-V Internal Reference
External Reference, 2.5-V Internal
Reference
12.5 pF
Ch
Rs
Sampling capacitor
3.3-V Internal Reference
All
7.5 pF
Nominal source impedance
50 Ω
ADC
ADCINx
Rs
Switch
Ron
AC
Cp
Ch
VREFLO
Figure 5-28. Input Model
This input model should be used with actual signal source impedance to determine the acquisition window
duration. For more information, see the Choosing an Acquisition Window Duration section of the Analog-
to-Digital Converter (ADC) chapter in the TMS320F28002x Microcontrollers Technical Reference Manual.
Table 5-40 lists the parasitic capacitance on each channel.
Table 5-40. Per-Channel Parasitic Capacitance
Cp (pF)
ADC CHANNEL
COMPARATOR DISABLED
COMPARATOR ENABLED
ADCINA0/ADCINC15
ADCINA1
3.3
2.4
2.9
71.4
4.5
2.7
2.6
4.2
4.5
3.4
2.9
2.9
4.7
2.5
3.3
2.9
15.8
4.9
5.4
73.9
7
ADCINA2/ADCINC9
ADCINA3/ADCINC5(1)
ADCINA4/ADCINC14
ADCINA5/ADCINC2
ADCINA6
5.2
5.1
6.7
7
ADCINA7/ADCINC3
ADCINA8/ADCINC11
ADCINA9/ADCINC8
ADCINA10/ADCINC10
ADCINA11/ADCINC0
ADCINA12/ADCINC1
ADCINA14/ADCINC4
ADCINA15/ADCINC7
ADCINC6
5.9
5.4
5.4
7.2
5
5.8
5.4
(1) Pin also used to supply reference voltage for COMPDAC and includes an internal decoupling
capacitor.
Copyright © 2020, Texas Instruments Incorporated
Specifications
85
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.9.1.2.2 ADC Timing Diagrams
Figure 5-29 shows the ADC conversion timings for two SOCs given the following assumptions:
•
•
•
•
SOC0 and SOC1 are configured to use the same trigger.
No other SOCs are converting or pending when the trigger occurs.
The round-robin pointer is in a state that causes SOC0 to convert first.
ADCINTSEL is configured to set an ADCINT flag upon end of conversion for SOC0 (whether this flag
propagates through to the CPU to cause an interrupt is determined by the configurations in the PIE
module).
Table 5-41 lists the descriptions of the ADC timing parameters. Table 5-42 lists the ADC timings.
Sample n
Input on SOC0.CHSEL
Input on SOC1.CHSEL
Sample n+1
ADC S+H
SOC0
SOC1
SYSCLK
ADCCLK
ADCTRIG
ADCSOCFLG.SOC0
ADCSOCFLG.SOC1
ADCRESULT0
Sample n
(old data)
(old data)
ADCRESULT1
Sample n+1
ADCINTFLG.ADCINTx
tSH
tLAT
tEOC
tINT
Figure 5-29. ADC Timings
86
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Table 5-41. ADC Timing Parameters
PARAMETER
DESCRIPTION
The duration of the S+H window.
At the end of this window, the value on the S+H capacitor becomes the voltage to be converted into a digital
value. The duration is given by (ACQPS + 1) SYSCLK cycles. ACQPS can be configured individually for each
SOC, so tSH will not necessarily be the same for different SOCs.
tSH
Note: The value on the S+H capacitor will be captured approximately 5 ns before the end of the S+H window
regardless of device clock settings.
The time from the end of the S+H window until the ADC results latch in the ADCRESULTx register.
tLAT
If the ADCRESULTx register is read before this time, the previous conversion results will be returned.
The time from the end of the S+H window until the S+H window for the next ADC conversion can begin. The
subsequent sample can start before the conversion results are latched.
tEOC
The time from the end of the S+H window until an ADCINT flag is set (if configured).
If the INTPULSEPOS bit in the ADCCTL1 register is set, tINT will coincide with the conversion results being
latched into the result register.
If the INTPULSEPOS bit is 0, tINT will coincide with the end of the S+H window. If tINT triggers a read of the
ADC result register (directly through DMA or indirectly by triggering an ISR that reads the result), care must be
taken to ensure the read occurs after the results latch (otherwise, the previous results will be read).
tINT
If the INTPULSEPOS bit is 0, and the OFFSET field in the ADCINTCYCLE register is not 0, then there will be a
delay of OFFSET SYSCLK cycles before the ADCINT flag is set. This delay can be used to enter the ISR or
trigger the DMA at exactly the time the sample is ready.
Table 5-42. ADC Timings
ADCCLK PRESCALE
SYSCLK CYCLES
ADCCLK CYCLES
RATIO
ADCCLK:SYSCLK
(1)
(2)
ADCCTL2 [PRESCALE]
tEOC
tLAT
tINT(EARLY)
tINT(LATE)
tEOC
0
2
1
2
3
4
5
6
7
8
11
21
31
41
51
61
71
81
13
23
34
44
55
65
76
86
1
1
1
1
1
1
1
1
11
21
31
41
51
61
71
81
11
10.5
10.3
10.3
10.2
10.2
10.1
10.1
4
6
8
10
12
14
(1) Refer to the "ADC: DMA Read of Stale Result" advisory in the TMS320F28002x MCUs Silicon Errata.
(2) By default, tINT occurs one SYSCLK cycle after the S+H window if INTPULSEPOS is 0. This can be changed by writing to the OFFSET
field in the ADCINTCYCLE register.
Copyright © 2020, Texas Instruments Incorporated
Specifications
87
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.9.2 Temperature Sensor
5.9.2.1 Temperature Sensor Electrical Data and Timing
The temperature sensor can be used to measure the device junction temperature. The temperature
sensor is sampled through an internal connection to the ADC and translated into a temperature through
TI-provided software. When sampling the temperature sensor, the ADC must meet the acquisition time in
Table 5-43.
Table 5-43. Temperature Sensor Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
External reference
MIN
TYP
MAX
UNIT
Tacc
tstartup
tacq
Temperature Accuracy
±15
°C
Start-up time
(TSNSCTL[ENABLE] to
sampling temperature
sensor)
500
µs
ns
ADC acquisition time
450
88
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.9.3 Comparator Subsystem (CMPSS)
Each CMPSS contains two comparators, two reference 12-bit DACs, two digital filters, and one ramp
generator. Comparators are denoted "H" or "L" within each module, where “H” and “L” represent high and
low, respectively. Each comparator generates a digital output that indicates whether the voltage on the
positive input is greater than the voltage on the negative input. The positive input of the comparator can
be driven from an external pin or by the PGA. The negative input can be driven by an external pin or by
the programmable reference 12-bit DAC. Each comparator output passes through a programmable digital
filter that can remove spurious trip signals. An unfiltered output is also available if filtering is not required.
A ramp generator circuit is optionally available to control the reference 12-bit DAC value for the high
comparator in the subsystem. There are two outputs from each CMPSS module. These two outputs pass
through the digital filters and crossbar before connecting to the ePWM modules or GPIO pin. Figure 5-30
shows the CMPSS connectivity.
Comparator Subsystem1
CTRIP1H
CTRIP1L
CTRIP2H
CTRIP2L
CMP1_HP
CMP1_HN
CTRIP1H
Digital
Filter
VDDA or VDAC
CTRIPOUT1H
DAC12
DAC12
Digital
Filter
CTRIP1L
CMP1_LN
CMP1_LP
CTRIPOUT1L
ePWM X- BAR
ePWMs
Comparator Subsystem2
CMP2_HP
CMP2_HN
CTRIP2H
Digital
Filter
VDDA or VDAC
CTRIPOUT2H
DAC12
DAC12
CTRIP4H
CTRIP4L
Digital
Filter
CTRIP2L
CMP2_LN
CMP2_LP
CTRIPOUT2L
CTRIPOUT1H
CTRIPOUT1L
CTRIPOUT2H
CTRIPOUT2L
Comparator Subsystem4
CMP4_HP
CMP4_HN
CTRIP4H
Digital
Filter
VDDA or VDAC
CTRIPOUT4H
Output X- BAR
GPIO Mux
DAC12
DAC12
Digital
Filter
CTRIP4L
CMP4_LN
CMP4_LP
CTRIPOUT4L
CTRIPOUT4H
CTRIPOUT4L
Figure 5-30. CMPSS Connectivity
Copyright © 2020, Texas Instruments Incorporated
Specifications
89
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.9.3.1 CMPSS Electrical Data and Timing
Table 5-44 lists the comparator electrical characteristics. Figure 5-31 shows the CMPSS comparator input
referred offset. Figure 5-32 shows the CMPSS comparator hysteresis.
Table 5-44. Comparator Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
500
UNIT
µs
TPU
Power-up time
Comparator input (CMPINxx) range
Input referred offset error
0
VDDA
V
Low common mode, inverting
input set to 50mV
–20
20
mV
1x
12
24
36
48
21
26
30
46
2x
Hysteresis(1)
LSB
3x
4x
Step response
60
ns
Response time (delay from CMPINx input change
to output on ePWM X-BAR or Output X-BAR)
Ramp response (1.65V/µs)
Ramp response (8.25mV/µs)
Up to 250 kHz
ns
dB
dB
PSRR
CMRR
Power Supply Rejection Ratio
Common Mode Rejection Ratio
40
(1) The CMPSS DAC is used as the reference to determine how much hysteresis to apply. Therefore, hysteresis will scale with the CMPSS
DAC reference voltage. Hysteresis is available for all comparator input source configurations.
NOTE
The CMPSS inputs must be kept below VDDA + 0.3 V to ensure proper functional operation.
If a CMPSS input exceeds this level, an internal blocking circuit isolates the internal
comparator from the external pin until the external pin voltage returns below VDDA + 0.3 V.
During this time, the internal comparator input is floating and can decay below VDDA within
approximately 0.5 µs. After this time, the comparator could begin to output an incorrect result
depending on the value of the other comparator input.
Input Referred Offset
CTRIPx
Logic Level
CTRIPx = 1
CTRIPx = 0
COMPINxP
Voltage
0
CMPINxN or
DACxVAL
Figure 5-31. CMPSS Comparator Input Referred Offset
90
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Hysteresis
CTRIPx
Logic Level
CTRIPx = 1
CTRIPx = 0
COMPINxP
Voltage
0
CMPINxN or
DACxVAL
Figure 5-32. CMPSS Comparator Hysteresis
Table 5-45 lists the CMPSS DAC static electrical characteristics.
Table 5-45. CMPSS DAC Static Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
0
TYP
MAX
UNIT
Internal reference
VDDA
VDAC(1)
CMPSS DAC output range
V
External reference
0
Static offset error(2)
Static gain error(2)
Static DNL
–25
–2
25
2
mV
% of FSR
LSB
Endpoint corrected
>–1
–16
4
Static INL
Endpoint corrected
16
1
LSB
Settling time
Resolution
Settling to 1LSB after full-scale output change
µs
12
bits
Error induced by comparator trip or CMPSS
DAC code change within the same CMPSS
module
CMPSS DAC output disturbance(3)
–100
100
LSB
CMPSS DAC disturbance time(3)
VDAC reference voltage
VDAC load(4)
200
VDDA
10
ns
V
When VDAC is reference
When VDAC is reference
2.4
6
2.5 or 3.0
8
kΩ
(1) The maximum output voltage is VDDA when VDAC > VDDA.
(2) Includes comparator input referred errors.
(3) Disturbance error may be present on the CMPSS DAC output for a certain amount of time after a comparator trip.
(4) Per active CMPSS module.
Copyright © 2020, Texas Instruments Incorporated
Specifications
91
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.9.3.1.1 CMPSS Illustrative Graphs
Figure 5-33 shows the CMPSS DAC static offset. Figure 5-34 shows the CMPSS DAC static gain.
Figure 5-35 shows the CMPSS DAC static linearity.
Offset Error
Figure 5-33. CMPSS DAC Static Offset
Ideal Gain
Actual Gain
Figure 5-34. CMPSS DAC Static Gain
92
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Linearity Error
Figure 5-35. CMPSS DAC Static Linearity
Copyright © 2020, Texas Instruments Incorporated
Specifications
93
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.10 Control Peripherals
5.10.1 Enhanced Pulse Width Modulator (ePWM)
The ePWM peripheral is a key element in controlling many of the power electronic systems found in both
commercial and industrial equipment. The ePWM type-4 module is able to generate complex pulse width
waveforms with minimal CPU overhead by building the peripheral up from smaller modules with separate
resources that can operate together to form a system. Some of the highlights of the ePWM type-4 module
include complex waveform generation, dead-band generation, a flexible synchronization scheme,
advanced trip-zone functionality, and global register reload capabilities.
Figure 5-36 shows the ePWM module. Figure 5-37 shows the ePWM trip input connectivity.
94
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Time-Base (TB)
TBPRD Shadow (24)
ePWM
SYNC
Scheme
EXTSYNCIN
EXTSYNCOUT
TBPRDHR (8)
TBPRD Active (24)
CTR=PRD
EPWMxSYNCI
TBCTL[PHSEN]
TBCTL[SWFSYNC]
DCAEVT1/sync(A)
DCBEVT1/sync(A)
Counter
Up/Down
(16 bit)
CTR=ZERO
CTR_Dir
TBCTR
Active (16)
CTR=PRD
EPWMx_INT
CTR=ZERO
TBPHSHR (8)
EPWMxSOCA
EPWMxSOCB
CTR=PRD or ZERO
CTR=CMPA
16
8
On-chip
ADC
Event
Trigger
And
Interrupt
(ET)
Phase
Control
TBPHS Active (24)
CTR=CMPB
CTR=CMPC
CTR=CMPD
CTR_Dir
DCAEVT1.soc(A)
DCBEVT1.soc(A)
ADCSOCOUTSELECT
Counter Compare (CC)
Action
Qualifier
(AQ)
CTR=CMPA
CMPAHR (8)
Select and pulse stretch
for external ADC
16
HiRes PWM (HRPWM)
CMPAHR (8)
EPWMA
ADCSOCAO
ADCSOCBO
CMPA Active (24)
CMPA Shadow (24)
ePWMxA
Trip
Zone
(TZ)
Dead
Band
(DB)
PWM
Chopper
(DB)
CTR=CMPA
CMPAHR (8)
16
CMPC Active (16)
EPWMB
ePWMxB
CMPC Shadow (16)
CMPBHR (8)
CTR=CMPC
EPWMx_TZ_INT
TZ1 to TZ3
TBCNT (16)
CMPC[15-0]
CTR=ZERO
DCAEVT1.inter
DCBEVT1.inter
DCAEVT2.inter
EMUSTOP
16
CLOCKFAIL
CMPC Active (16)
EQEPxERR
DCBEVT2.inter
DCAEVT1.force(A)
DCBEVT1.force(A)
DCAEVT2.force(A)
CMPC Shadow (16)
TBCNT (16)
CTR=CMPC
DCBEVT2.force(A)
CMPD[15-0]
16
CMPC Active (16)
CMPC Shadow (16)
A. These events are generated by the ePWM digital compare (DC) submodule based on the levels of the TRIPIN inputs.
Figure 5-36. ePWM Submodules and Critical Internal Signal Interconnects
Copyright © 2020, Texas Instruments Incorporated
Specifications
95
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
GPIO0
Async/
Sync/
Input X-Bar
Sync+Filter
GPIOx
Other Sources
INPUT[1:16]
16:127
0:15
eCAPx
XINT1
XINT2
XINT3
XINT4
XINT5
ADC
Wrapper(s)
PIE
ePWM
eCAP
Sync Mux
EXTSYNCIN1
EXTSYNCIN2
TZ1
TZ2
TZ3
EPWMINT
TZINT
TRIP1
TRIP2
TRIP3
TRIP6
EPWMx.EPWMCLK
PCLKCR2[EPWMx]
TBCLKSYNC
PCLKCR0[TBCLKSYNC]
TRIP4
TRIP5
TRIP7
TRIP8
TRIP9
TRIP10
TRIP11
TRIP12
INPUT[1:14]
CMPSSx.TRIPH
CMPSSx.TRIPHORL
CMPSSx.TRIPL
ADCx.EVT1-4
ECAPx.OUT
All
ePWM
Modules
ePWM
X-Bar
ADCSOCAO Select
ADCSOCBO Select
EXTSYNCOUT
ADCSOCx
SOCA
SOCB
ADC
Wrapper(s)
Reserved
ECCERR
TRIP13
TRIP14
TRIP15
TZ4
TZ5
TZ6
PIEVECTERROR
EQEPERR
CLKFAIL
EMUSTOP
EPWMSYNCPER
Blanking Window
CMPSS
Figure 5-37. ePWM Trip Input Connectivity
96
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.10.1.1 Control Peripherals Synchronization
The ePWM and eCAP synchronization scheme on the device provides flexibility in partitioning the ePWM
and eCAP modules and allows localized synchronization within the modules. Like the other peripherals,
the partitioning of the ePWM and eCAP modules needs to be done using the CPUSELx registers.
Figure 5-38 shows the synchronization scheme.
TBCTL
SWFSYNC
CTR=ZERO
CTR=CMPB
CTR=CMPC
CTR=CMPD
CLR
DCAEVT1.sync
One Shot
Latch
DCBEVT1.sync
0
Set
Q
EPWMSYNCOUTEN
1
SWEN
ZEROEN
0
0
1
CMPBEN
EPWMxSYNCOUT
1
0
OR
CMPCEN
CMPDEN
DCARVT1EN
DCBEVT1EN
TBCTL2[SELFCLRTRREM]
Clear
Register
Disable
0
EPWM1SYNCOUT
|
|
|
EPWMxSYNCOUT
ECAP1SYNCOUT
HRPCTL[PWMSYNCSELX]
CTR=CMPC UP
EPWMxSYNCIN
|
|
|
CTR=CMPC DOWN
CTR=CMPD UP
ECAPySYNCOUT
Other Sources
EPWMxSYNCPER
CTR=CMPD DOWN
HRPCTL[PWMSYNCSEL]
CTR=PRD
CMPSS
DAC
EPWMSYNCINSEL
Note: SYNCO and SYNCOUT are used interchangeably
CTR=ZERO
Figure 5-38. Synchronization Chain Architecture
Copyright © 2020, Texas Instruments Incorporated
Specifications
97
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.10.1.2 ePWM Electrical Data and Timing
Table 5-46 lists the PWM timing requirements and Table 5-47 lists the PWM switching characteristics.
Table 5-46. ePWM Timing Requirements(1)
MIN
2tc(EPWMCLK)
MAX
UNIT
Asynchronous
Synchronous
tw(SYNCIN)
Sync input pulse width
2tc(EPWMCLK)
cycles
With input qualifier
1tc(EPWMCLK) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Table 5-24.
Table 5-47. ePWM Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
20
MAX
UNIT
ns
tw(PWM)
Pulse duration, PWMx output high/low
Sync output pulse width
tw(SYNCOUT)
8tc(SYSCLK)
cycles
Delay time, trip input active to PWM forced high
Delay time, trip input active to PWM forced low
Delay time, trip input active to PWM Hi-Z
td(TZ-PWM)
25
ns
5.10.1.2.1 Trip-Zone Input Timing
Table 5-48 lists the trip-zone input timing requirements. Figure 5-39 shows the PWM Hi-Z characteristics.
Table 5-48. Trip-Zone Input Timing Requirements(1)
MIN
1tc(EPWMCLK)
MAX UNIT
cycles
Asynchronous
Synchronous
tw(TZ)
Pulse duration, TZx input low
2tc(EPWMCLK)
cycles
With input qualifier
1tc(EPWMCLK) + tw(IQSW)
cycles
(1) For an explanation of the input qualifier parameters, see Table 5-24.
EPWMCLK
tw(TZ)
TZ(A)
td(TZ-PWM)
PWM(B)
A. TZ: TZ1, TZ2, TZ3, TRIP1–TRIP12
B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM
recovery software.
Figure 5-39. PWM Hi-Z Characteristics
98
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.10.1.3 External ADC Start-of-Conversion Electrical Data and Timing
Table 5-49 lists the external ADC start-of-conversion switching characteristics. Figure 5-40 shows the
ADCSOCAO or ADCSOCBO timing.
Table 5-49. External ADC Start-of-Conversion Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
tw(ADCSOCL)
Pulse duration, ADCSOCxO low
32tc(SYSCLK)
cycles
tw(ADCSOCL)
ADCSOCAO
or
ADCSOCBO
Figure 5-40. ADCSOCAO or ADCSOCBO Timing
Copyright © 2020, Texas Instruments Incorporated
Specifications
99
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.10.2 High-Resolution Pulse Width Modulator (HRPWM)
The HRPWM combines multiple delay lines in a single module and a simplified calibration system by using
a dedicated calibration delay line. For each ePWM module, there are two HR outputs:
•
•
HR Duty and Deadband control on Channel A
HR Duty and Deadband control on Channel B
The HRPWM module offers PWM resolution (time granularity) that is significantly better than what can be
achieved using conventionally derived digital PWM methods. The key points for the HRPWM module are:
•
•
Significantly extends the time resolution capabilities of conventionally derived digital PWM
This capability can be used in both single edge (duty cycle and phase-shift control) as well as dual
edge control for frequency/period modulation.
•
Finer time granularity control or edge positioning is controlled through extensions to the Compare A, B,
phase, period and deadband registers of the ePWM module.
NOTE
The minimum HRPWMCLK frequency allowed for HRPWM is 60 MHz.
5.10.2.1 HRPWM Electrical Data and Timing
Table 5-50 lists the high-resolution PWM switching characteristics.
Table 5-50. High-Resolution PWM Characteristics
PARAMETER
MIN
TYP
MAX UNIT
310 ps
Micro Edge Positioning (MEP) step size(1)
150
(1) The MEP step size will be largest at high temperature and minimum voltage on VDD. MEP step size will increase with higher
temperature and lower voltage and decrease with lower temperature and higher voltage.
Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI
software libraries for details of using SFO functions in end applications. SFO functions help to estimate the number of MEP steps per
SYSCLK period dynamically while the HRPWM is in operation.
5.10.3 Enhanced Capture and High-Resolution Capture (eCAP, HRCAP)
The eCAP module can be used in systems where accurate timing of external events is important.
eCAP/HRCAP on this device is Type-2.
Applications for eCAP include:
•
Speed measurements of rotating machinery (for example, toothed sprockets sensed through Hall
sensors)
•
•
•
Elapsed time measurements between position sensor pulses
Period and duty cycle measurements of pulse train signals
Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors
The eCAP module includes the following features:
•
•
•
•
•
•
•
•
•
4-event time-stamp registers (each 32 bits)
Edge-polarity selection for up to four sequenced time-stamp capture events
Interrupt on either of the four events
Single shot capture of up to four event timestamps
Continuous mode capture of timestamps in a four-deep circular buffer
Absolute time-stamp capture
Difference (Delta) mode time-stamp capture
All of the above resources dedicated to a single input pin
When not used in capture mode, the eCAP module can be configured as a single-channel PWM output
(APWM).
100
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
The capture functionality of the Type-1 eCAP is enhanced from the Type-0 eCAP with the following added
features:
•
•
•
Event filter reset bit
–
Writing a 1 to ECCTL2[CTRFILTRESET] will clear the event filter, the modulo counter, and any
pending interrupts flags. Resetting the bit is useful for initialization and debug.
Modulo counter status bits
–
The modulo counter (ECCTL2 [MODCTRSTS]) indicates which capture register will be loaded next.
In the Type-0 eCAP, it was not possible to know current state of modulo counter.
DMA trigger source
–
eCAPxDMA is added as a DMA trigger. CEVT[1–4] can be configured as the source for
eCAPxDMA.
•
•
Input multiplexer
ECCTL0 [INPUTSEL] selects one of 128 input signals.
EALLOW protection
–
–
EALLOW protection is added to critical registers. To maintain software compatibility with the Type-0
eCAP, configure DEV_CFG_REGS.ECAPTYPE to make these registers unprotected.
The capture functionality of the Type-2 eCAP is enhanced from the Type-1 eCAP with the following added
features:
•
ECAPxSYNCINSEL register
–
The ECAPSxYNCINSEL register is added for each eCAP to select an external SYNCIN. Every
eCAP can have a separate SYNCIN signal.
The eCAP inputs connect to any GPIO input through the Input X-BAR. The APWM outputs connect to
GPIO pins through the Output X-BAR to OUTPUTx positions in the GPIO mux. See and .
The eCAP module is clocked by PERx.SYSCLK.
The clock enable bits (ECAP1–ECAP3) in the PCLKCR3 register turn off the eCAP module individually
(for low-power operation). Upon reset, ECAP1ENCLK is set to low, indicating that the peripheral clock
is off.
5.10.3.1 High-Resolution Capture (HRCAP)
eCAP3 module can be configured as high-resolution capture (HRCAP) submodules. The HRCAP
submodule measures the difference, in time, between pulses asynchronously to the system clock. This
submodule is new to the eCAP Type 1 module, and features many enhancements over the Type 0
HRCAP module.
Applications for the HRCAP include:
•
•
•
•
•
•
•
Capacitive touch applications
High-resolution period and duty-cycle measurements of pulse train cycles
Instantaneous speed measurements
Instantaneous frequency measurements
Voltage measurements across an isolation boundary
Distance/sonar measurement and scanning
Flow measurements
The HRCAP submodule includes the following features:
•
•
•
•
•
Pulse-width capture in either non-high-resolution or high-resolution modes
Absolute mode pulse-width capture
Continuous or "one-shot" capture
Capture on either falling or rising edge
Continuous mode capture of pulse widths in 4-deep buffer
Copyright © 2020, Texas Instruments Incorporated
Specifications
101
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
•
•
Hardware calibration logic for precision high-resolution capture
All of the resources in this list are available on any pin using the Input X-BAR.
The HRCAP submodule includes one high-resolution capture channel in addition to a calibration block.
The calibration block allows the HRCAP submodule to be continually recalibrated, at a set interval, with no
“down time”. Because the HRCAP submodule now uses the same hardware as its respective eCAP, if the
HRCAP is used, the corresponding eCAP will be unavailable.
Each high-resolution-capable channel has the following independent key resources.
•
•
•
All hardware of the respective eCAP
High-resolution calibration logic
Dedicated calibration interrupt
Figure 5-41 shows the eCAP and HRCAP block diagram.
102
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
ECCTL2 [ SYNCI_EN, SYNCOSEL, SWSYNC]
ECCTL2[CAP/APWM]
APWM Mode
CTRPHS
(phase register−32 bit)
ECAPxSYNCIN
OVF
RST
CTR_OVF
CTR [0−31]
PRD [0−31]
CMP [0−31]
TSCTR
ECAPxSYNCOUT
PWM
Compare
Logic
Output
X-Bar
(counter−32 bit)
Delta−Mode
32
CTR=PRD
CTR=CMP
CTR [0−31]
PRD [0−31]
32
ECCTL1 [ CAPLDEN, CTRRSTx]
HRCTRL[HRE]
32
32
LD1
CAP1
Polarity
Select
LD
(APRD Active)
APRD
32
shadow
CMP [0−31]
32
HRCTRL[HRE]
32
HRCTRL[HRE]
32
CAP2
Polarity
Select
LD2
LD
Other
Sources
(ACMP Active)
[127:16]
[15:0]
Event
Prescale
Event
32
ACMP
16
qualifier
Input
shadow
LD
ECCTL1[PRESCALE]
HRCTRL[HRE]
32
X-Bar
32
Polarity
Select
LD3
LD4
CAP3
(APRD Shadow)
HRCTRL[HRE]
32
32
CAP4
Polarity
Select
LD
(ACMP Shadow)
Edge Polarity Select
ECCTL1[CAPxPOL]
4
Capture Events
4
CEVT[1:4]
ECAPxDMA_INT
ECCTL2[CTRFILTRESET]
Interrupt
Continuous /
Oneshot
Trigger
and
MODCNTRSTS
CTR_OVF
CTR=PRD
CTR=CMP
Capture Control
ECCTL2[DMAEVTSEL]
Flag
Control
ECAPx
(to ePIE)
ECCTL2 [ REARM, CONT_ONESHT, STOP_WRAP]
Registers: ECEINT, ECFLG, ECCLR, ECFRC
Capture Pulse
HR Input
SYSCLK
HRCLK
(A)
HR Submodule
ECAPx_HRCAL
(to ePIE)
Copyright © 2018, Texas Instruments Incorporated
A. The HRCAP submodule is not available on all eCAP modules; in this case, the high-resolution muxes and hardware
are not implemented.
Figure 5-41. eCAP and HRCAP Block Diagram
Copyright © 2020, Texas Instruments Incorporated
Specifications
103
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.10.3.2 eCAP/HRCAP Synchronization
The eCAP modules can be synchronized with each other by selecting a common SYNCIN source.
SYNCIN source for eCAP can be either software sync-in or external sync-in. The external sync-in signal
can come from EPWM, eCAP, or X-Bar. The SYNC signal is defined by the selection in the
ECAPxSYNCINSEL[SEL] bit for ECAPx as shown in Figure 5-42.
ECAPx
Disable
EPWM[1..7]SYNCOUT
0x0
0x1
ECAPxSYNCIN
ECAPxSYNCOUT
EPWMxSYNCOUT
ECCTL2[SWSYNC]
CTR=PRD
EXTSYNCOUT
ECAP[1..3]SYNCOUT
INPUT5 (Input X-Bar)
Disable
Disable
INPUT6 (Input X-Bar)
0x19
SYNCSELECT[SYNCOUT]
ECCTL2[SYNCOSEL]
ECAPSYNCINSEL[SEL]
Figure 5-42. eCAPSynchronization Scheme
104
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.10.3.3 eCAP Electrical Data and Timing
Table 5-51 lists the eCAP timing requirements and Table 5-52 lists the eCAP switching characteristics.
Table 5-51. eCAP Timing Requirements
MIN
2tc(SYSCLK)
NOM
MAX
UNIT
Asynchronous
Synchronous
tw(CAP)
Capture input pulse width
2tc(SYSCLK)
ns
With input qualifier
1tc(SYSCLK) + tw_(IQSW)
Table 5-52. eCAP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
ns
tw(APWM)
Pulse duration, APWMx output high/low
20
5.10.3.4 HRCAP Electrical Data and Timing
Table 5-53 lists the HRCAP switching characteristics. Figure 5-43 shows the HRCAP accuracy precision
and resolution. Figure 5-44 shows the HRCAP standard deviation characteristics.
Table 5-53. HRCAP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
Input pulse width
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ns
110
Measurement length ≤ 5 µs
±390
±450
540
ps
Accuracy(1)(2)(3)(4)
Measurement length > 5 µs
1450
ps
Standard deviation
Resolution
See Figure 5-44
300
ps
(1) Value obtained using an oscillator of 100 PPM, oscillator accuracy directly affects the HRCAP accuracy.
(2) Measurement is completed using rising-rising or falling-falling edges
(3) Opposite polarity edges will have an additional inaccuracy due to the difference between VIH and VIL. This effect is dependent on the
signal’s slew rate.
(4) Accuracy only applies to time-converted measurements.
HRCAP’s Mean
Accuracy
Resolution
(Step Size)
Precision
(Standard Deviation)
Actual
Input Signal
A. The HRCAP has some variation in performance, this results in a probability distribution which is described using the
following terms:
•
•
•
Accuracy: The time difference between the input signal and the mean of the HRCAP’s distribution.
Precision: The width of the HRCAP’s distribution, this is given as a standard deviation.
Resolution: The minimum measurable increment.
Figure 5-43. HRCAP Accuracy Precision and Resolution
Copyright © 2020, Texas Instruments Incorporated
Specifications
105
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
2
7.4
Typical Core Conditions
Noisy Core Supply
1.8
1.6
1.4
1.2
1
6.66
5.92
5.18
4.44
3.7
0.8
0.6
0.4
0.2
2.96
2.22
1.48
0.74
0
1000
2000
3000
4000
5000
Time Between Edges(nS)
6000
7000
8000
9000
10000
A. Typical core conditions: All peripheral clocks are enabled.
B. Noisy core supply: All core clocks are enabled and disabled with a regular period during the measurement.
C. Fluctuations in current and voltage on the 1.2-V rail cause the standard deviation of the HRCAP to rise. Care should
be taken to ensure that the 1.2-V supply is clean, and that noisy internal events, such as enabling and disabling clock
trees, have been minimized while using the HRCAP.
Figure 5-44. HRCAP Standard Deviation Characteristics
106
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.10.4 Enhanced Quadrature Encoder Pulse (eQEP)
The eQEP module on this device is Type-2. The eQEP interfaces directly with linear or rotary incremental
encoders to obtain position, direction, and speed information from rotating machines used in high-
performance motion and position control systems.
The eQEP peripheral contains the following major functional units (see Figure 5-45):
•
•
•
•
•
•
•
Programmable input qualification for each pin (part of the GPIO MUX)
Quadrature decoder unit (QDU)
Position counter and control unit for position measurement (PCCU)
Quadrature edge-capture unit for low-speed measurement (QCAP)
Unit time base for speed/frequency measurement (UTIME)
Watchdog timer for detecting stalls (QWDOG)
Quadrature Mode Adapter (QMA)
System
control registers
To CPU
EQEPxENCLK
SYSCLK
QCPRD
Enhanced QEP (eQEP) peripheral
QCAPCTL
16
QCTMR
16
16
Quadrature
capture unit
(QCAP)
QCTMRLAT
QCPRDLAT
QUTMR
QUPRD
QWDTMR
QWDPRD
Registers
used by
multiple units
32
16
QDECCTL
16
QEPCTL
QEPSTS
QFLG
UTOUT
UTIME
QWDOG
EQEPx_A
EQEPx_B
EQEPxAIN
WDTOUT
QMA
EQEPxBIN
EQEPxINT
QCLK
PIE
QDIR
EQEPxIIN
Quadrature
32
QI
GPIO
MUX
EQEPx_INDEX
EQEPxIOUT
Position counter/
control unit
(PCCU)
decoder
(QDU)
QS
EQEPxIOE
QPOSLAT
PHE
QPOSSLAT
QPOSILAT
PCSOUT
EQEPxSIN
EQEPx_STROBE
EQEPxSOUT
EQEPxSOE
32
32
16
QEINT
QPOSCNT
QPOSINIT
QPOSMAX
QPOSCMP
QFRC
QCLR
QPOSCTL
Copyright © 2017, Texas Instruments Incorporated
Figure 5-45. eQEP Block Diagram
Copyright © 2020, Texas Instruments Incorporated
Specifications
107
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.10.4.1 eQEP Electrical Data and Timing
Table 5-54 lists the eQEP timing requirements and Table 5-55 lists the eQEP switching characteristics.
Table 5-54. eQEP Timing Requirements(1)
MIN
MAX
UNIT
Synchronous(2)
2tc(SYSCLK)
tw(QEPP)
QEP input period
cycles
Synchronous with input qualifier
Synchronous(2)
2[1tc(SYSCLK) + tw(IQSW)]
2tc(SYSCLK)
2tc(SYSCLK) + tw(IQSW)
2tc(SYSCLK)
tw(INDEXH)
tw(INDEXL)
tw(STROBH)
tw(STROBL)
QEP Index Input High time
QEP Index Input Low time
QEP Strobe High time
QEP Strobe Input Low time
cycles
cycles
cycles
cycles
Synchronous with input qualifier
Synchronous(2)
Synchronous with input qualifier
Synchronous(2)
2tc(SYSCLK) + tw(IQSW)
2tc(SYSCLK)
2tc(SYSCLK) + tw(IQSW)
2tc(SYSCLK)
Synchronous with input qualifier
Synchronous(2)
Synchronous with input qualifier
2tc(SYSCLK) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Table 5-24.
(2) The GPIO GPxQSELn Asynchronous mode should not be used for eQEP module input pins.
Table 5-55. eQEP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
5tc(SYSCLK)
7tc(SYSCLK)
UNIT
cycles
cycles
td(CNTR)xin
Delay time, external clock to counter increment
td(PCS-OUT)QEP
Delay time, QEP input edge to position compare sync output
108
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.11 Communications Peripherals
5.11.1 Controller Area Network (CAN)
NOTE
The CAN module uses the IP known as DCAN. This document uses the names CAN and
DCAN interchangeably to reference this peripheral.
The CAN module implements the following features:
•
•
•
•
Complies with ISO11898-1 ( Bosch® CAN protocol specification 2.0 A and B)
Bit rates up to 1 Mbps
Multiple clock sources
32 message objects (mailboxes), each with the following properties:
–
–
–
–
–
–
Configurable as receive or transmit
Configurable with standard (11-bit) or extended (29-bit) identifier
Supports programmable identifier receive mask
Supports data and remote frames
Holds 0 to 8 bytes of data
Parity-checked configuration and data RAM
•
•
•
•
•
•
•
•
Individual identifier mask for each message object
Programmable FIFO mode for message objects
Programmable loopback modes for self-test operation
Suspend mode for debug support
Software module reset
Automatic bus on after bus-off state by a programmable 32-bit timer
Two interrupt lines
DMA support
NOTE
For a CAN bit clock of 100 MHz, the smallest bit rate possible is 3.90625 kbps.
NOTE
The accuracy of the on-chip zero-pin oscillator is in Table 5-16. Depending on parameters
such as the CAN bit timing settings, bit rate, bus length, and propagation delay, the accuracy
of this oscillator may not meet the requirements of the CAN protocol. In this situation, an
external clock source must be used.
Figure 5-46 shows the CAN block diagram.
Copyright © 2020, Texas Instruments Incorporated
Specifications
109
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
CAN_H
CAN_L
CAN Bus
3.3V CAN Transceiver
External connections
Device
CANx RX pin
CANx TX pin
CAN
CAN Core
Message RAM
Message Handler
Message
RAM
Interface
Register and Message
Object Access (IFx)
32
Message
Objects
(Mailboxes)
Test Modes
Only
Module Interface
CANINT0 CANINT1
DMA
CPU Bus
Figure 5-46. CAN Block Diagram
110
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.11.2 Inter-Integrated Circuit (I2C)
The I2C module has the following features:
•
Compliance with the NXP Semiconductors I2C-bus specification (version 2.1):
–
–
–
–
–
–
–
–
Support for 8-bit format transfers
7-bit and 10-bit addressing modes
General call
START byte mode
Support for multiple master-transmitters and slave-receivers
Support for multiple slave-transmitters and master-receivers
Combined master transmit/receive and receive/transmit mode
Data transfer rate from 10 kbps up to 400 kbps (Fast-mode)
•
•
One 16-byte receive FIFO and one 16-byte transmit FIFO
Supports two ePIE interrupts
–
I2Cx interrupt – Any of the below conditions can be configured to generate an I2Cx interrupt:
•
•
•
•
•
•
•
Transmit Ready
Receive Ready
Register-Access Ready
No-Acknowledgment
Arbitration-Lost
Stop Condition Detected
Addressed-as-Slave
–
I2Cx_FIFO interrupts:
•
•
Transmit FIFO interrupt
Receive FIFO interrupt
•
•
Module enable and disable capability
Free data format mode
Figure 5-47 shows how the I2C peripheral module interfaces within the device.
Copyright © 2020, Texas Instruments Incorporated
Specifications
111
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
I2C module
I2CXSR
I2CDXR
TX FIFO
RX FIFO
FIFO Interrupt
to CPU/PIE
SDA
Peripheral bus
I2CRSR
I2CDRR
Control/status
registers
CPU
Clock
synchronizer
SCL
Prescaler
Noise filters
Arbitrator
Interrupt to
CPU/PIE
I2C INT
Figure 5-47. I2C Peripheral Module Interfaces
112
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.11.2.1 I2C Electrical Data and Timing
Table 5-56 lists the I2C timing requirements. Table 5-57 lists the I2C switching characteristics.
Table 5-56. I2C Timing Requirements
MIN
MAX
UNIT
th(SDA-SCL)START
tsu(SCL-SDA)START
Hold time, START condition, SCL fall delay after SDA fall
0.6
µs
Setup time, Repeated START, SCL rise before SDA fall
delay
0.6
µs
th(SCL-DAT)
tsu(DAT-SCL)
tr(SDA)
Hold time, data after SCL fall
Setup time, data before SCL rise
Rise time, SDA
0
100
20
µs
ns
ns
ns
ns
ns
300
300
300
300
tr(SCL)
Rise time, SCL
20
tf(SDA)
Fall time, SDA
11.4
11.4
tf(SCL)
Fall time, SCL
Setup time, STOP condition, SCL rise before SDA rise
delay
tsu(SCL-SDA)STOP
0.6
µs
Table 5-57. I2C Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
0
MAX UNIT
fSCL
SCL clock frequency
400
kHz
µs
tw(SCLL)
tw(SCLH)
Pulse duration, SCL clock low
Pulse duration, SCL clock high
1.3
0.6
µs
Pulse duration of spikes that will be
suppressed by the input filter
tw(SP)
tBUF
0
50
ns
µs
Bus free time between STOP and START
conditions
1.3
tv(SCL-DAT)
Valid time, data after SCL fall
Valid time, Acknowledge after SCL fall
Valid low-level input voltage
Valid high-level input voltage
Low-level output voltage
0.9
0.9
µs
µs
V
tv(SCL-ACK)
VIL
VIH
VOL
II
–0.3
0.3 * VDDIO
VDDIO + 0.3
0.4
0.7 * VDDIO
V
Sinking 3 mA
0
V
Input current on pins
0.1 Vbus < Vi < 0.9 Vbus
–10
10
µA
NOTE
To meet all of the I2C protocol timing specifications, the I2C module clock must be
configured in the range from 7 MHz to 12 MHz.
Copyright © 2020, Texas Instruments Incorporated
Specifications
113
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.11.3 Power Management Bus (PMBus) Interface
The PMBus module has the following features:
•
•
•
•
Compliance with the SMI Forum PMBus Specification (Part I v1.0 and Part II v1.1)
Support for master and slave modes
Support for I2C mode
Support for two speeds:
–
–
Standard Mode: Up to 100 kHz
Fast Mode: 400 kHz
•
•
•
•
•
Packet error checking
CONTROL and ALERT signals
Clock high and low time-outs
Four-byte transmit and receive buffers
One maskable interrupt, which can be generated by several conditions:
–
–
–
–
–
–
–
–
Receive data ready
Transmit buffer empty
Slave address received
End of message
ALERT input asserted
Clock low time-out
Clock high time-out
Bus free
Figure 5-48 shows the PMBus block diagram.
PCLKCR20
SYSCLK
PMBCTRL
Div
ALERT
CTL
DMA
CPU
PIE
Bit clock
Other registers
GPIO Mux
PMBTXBUF
SCL
Shift register
PMBRXBUF
SDA
PMBUSA_INT
PMBus Module
Figure 5-48. PMBus Block Diagram
114
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.11.3.1 PMBus Electrical Data and Timing
Table 5-58 lists the PMBus electrical characteristics. Table 5-59 lists the PMBUS fast mode switching
characteristics. Table 5-60 lists the PMBUS standard mode switching characteristics.
Table 5-58. PMBus Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.8
UNIT
V
VIL
VIH
VOL
IOL
Valid low-level input voltage
Valid high-level input voltage
Low-level output voltage
Low-level output current
2.1
VDDIO
0.4
V
At Ipullup = 4 mA
V
VOL ≤ 0.4 V
4
0
mA
Pulse width of spikes that must be
suppressed by the input filter
tSP
50
ns
Ii
Input leakage current on each pin
Capacitance on each pin
0.1 Vbus < Vi < 0.9 Vbus
–10
10
10
µA
pF
Ci
Table 5-59. PMBus Fast Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fSCL
tBUF
SCL clock frequency
10
400
kHz
Bus free time between STOP and
START conditions
1.3
0.6
0.6
0.6
µs
µs
µs
µs
START condition hold time -- SDA fall
to SCL fall delay
tHD;STA
tSU;STA
tSU;STO
Repeated START setup time -- SCL
rise to SDA fall delay
STOP condition setup time -- SCL rise
to SDA rise delay
tHD;DAT
tSU;DAT
tTimeout
tLOW
Data hold time after SCL fall
Data setup time before SCL rise
Clock low time-out
300
100
25
ns
ns
ms
µs
µs
35
Low period of the SCL clock
High period of the SCL clock
1.3
0.6
tHIGH
50
25
Cumulative clock low extend time
(slave device)
tLOW;SEXT
tLOW;MEXT
From START to STOP
Within each byte
ms
ms
Cumulative clock low extend time
(master device)
10
tr
tf
Rise time of SDA and SCL
Fall time of SDA and SCL
5% to 95%
95% to 5%
20
20
300
300
ns
ns
Copyright © 2020, Texas Instruments Incorporated
Specifications
115
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Table 5-60. PMBus Standard Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fSCL
tBUF
SCL clock frequency
10
100
kHz
Bus free time between STOP and
START conditions
4.7
4
µs
µs
µs
µs
START condition hold time -- SDA fall
to SCL fall delay
tHD;STA
tSU;STA
tSU;STO
Repeated START setup time -- SCL
rise to SDA fall delay
4.7
4
STOP condition setup time -- SCL rise
to SDA rise delay
tHD;DAT
tSU;DAT
tTimeout
tLOW
Data hold time after SCL fall
Data setup time before SCL rise
Clock low time-out
300
250
25
ns
ns
ms
µs
µs
35
Low period of the SCL clock
High period of the SCL clock
4.7
4
tHIGH
50
25
Cumulative clock low extend time
(slave device)
tLOW;SEXT
tLOW;MEXT
From START to STOP
ms
ms
Cumulative clock low extend time
(master device)
Within each byte
10
tr
tf
Rise time of SDA and SCL
Fall time of SDA and SCL
1000
300
ns
ns
116
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.11.4 Serial Communications Interface (SCI)
The SCI is a 2-wire asynchronous serial port, commonly known as a UART. The SCI module supports
digital communications between the CPU and other asynchronous peripherals that use the standard non-
return-to-zero (NRZ) format
The SCI receiver and transmitter each have a 16-level-deep FIFO for reducing servicing overhead, and
each has its own separate enable and interrupt bits. Both can be operated independently for half-duplex
communication, or simultaneously for full-duplex communication. To specify data integrity, the SCI checks
received data for break detection, parity, overrun, and framing errors. The bit rate is programmable to
different speeds through a 16-bit baud-select register.
Features of the SCI module include:
•
Two external pins:
–
–
–
SCITXD: SCI transmit-output pin
SCIRXD: SCI receive-input pin
Baud rate programmable to 64K different rates
•
Data-word format
–
–
–
–
1 start bit
Data-word length programmable from 1 to 8 bits
Optional even/odd/no parity bit
1 or 2 stop bits
•
•
•
•
•
Four error-detection flags: parity, overrun, framing, and break detection
Two wake-up multiprocessor modes: idle-line and address bit
Half- or full-duplex operation
Double-buffered receive and transmit functions
Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms
with status flags.
–
Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX
EMPTY flag (transmitter-shift register is empty)
–
Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag
(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
•
•
•
•
Separate enable bits for transmitter and receiver interrupts (except BRKDT)
NRZ format
Auto baud-detect hardware logic
16-level transmit and receive FIFO
NOTE
All registers in this module are 8-bit registers. When a register is accessed, the register data
is in the lower byte (bits 7–0), and the upper byte (bits 15–8) is read as zeros. Writing to the
upper byte has no effect.
Figure 5-49 shows the SCI block diagram.
Copyright © 2020, Texas Instruments Incorporated
Specifications
117
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
SCICTL1.1
Frame Format and Mode
Parity
SCITXD
SCITXD
TXSHF
Register
TXENA
TX EMPTY
SCICTL2.6
Even/Odd
Enable
8
SCICCR.6 SCICCR.5
TXRDY
TX INT ENA
SCICTL2.0
Transmitter-Data
Buffer Register
SCICTL2.7
TXWAKE
8
SCICTL1.3
1
TX FIFO _0
TX FIFO _1
−−−−−
TXINT
To CPU
TX Interrupt
Logic
TX FIFO Interrupt
TX FIFO _15
SCI TX Interrupt select logic
Auto baud detect logic
WUT
SCITXBUF.7−0
TX FIFO registers
SCIFFENA
SCIFFTX.14
SCIHBAUD. 15 − 8
SCIRXD
RXSHF
Register
Baud Rate
MSbyte
SCIRXD
Register
RXWAKE
LSPCLK
SCIRXST.1
SCILBAUD. 7 − 0
RXENA
SCICTL1.0
Baud Rate
LSbyte
8
SCICTL2.1
Register
RXRDY
RX/BK INT ENA
Receive Data
Buffer register
SCIRXST.6
SCIRXBUF.7−0
8
BRKDT
SCIRXST.5
RX FIFO _15
−−−−−
RX FIFO_1
RX Interrupt
Logic
RXINT
RX FIFO _0
RX FIFO Interrupt
To CPU
SCIRXBUF.7−0
RX FIFO registers
RXFFOVF
SCIRXST.7
RX Error
SCIRXST.5 – 2
FE OE PE
SCIFFRX.15
RX Error
RX ERR INT ENA
SCICTL1.6
SCI RX Interrupt select logic
Figure 5-49. SCI Block Diagram
118
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.11.5 Serial Peripheral Interface (SPI)
The serial peripheral interface (SPI) is a high-speed synchronous serial input and output (I/O) port that
allows a serial bit stream of programmed length (1 to 16 bits) to be shifted into and out of the device at a
programmed bit-transfer rate. The SPI is normally used for communications between the MCU controller
and external peripherals or another controller. Typical applications include external I/O or peripheral
expansion through devices such as shift registers, display drivers, and analog-to-digital converters
(ADCs). Multidevice communications are supported by the master or slave operation of the SPI. The port
supports a 16-level, receive and transmit FIFO for reducing CPU servicing overhead.
The SPI module features include:
•
•
•
•
•
•
SPISOMI: SPI slave-output/master-input pin
SPISIMO: SPI slave-input/master-output pin
SPISTE: SPI slave transmit-enable pin
SPICLK: SPI serial-clock pin
Two operational modes: Master and Slave
Baud rate: 125 different programmable rates. The maximum baud rate that can be employed is limited
by the maximum speed of the I/O buffers used on the SPI pins.
•
•
Data word length: 1 to 16 data bits
Four clocking schemes (controlled by clock polarity and clock phase bits) include:
–
–
–
–
Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the
rising edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
•
•
Simultaneous receive and transmit operation (transmit function can be disabled in software)
Transmitter and receiver operations are accomplished through either interrupt-driven or polled
algorithm
•
•
•
•
•
•
16-level transmit/receive FIFO
DMA support
High-speed mode
Delayed transmit control
3-wire SPI mode
SPISTE inversion for digital audio interface receive mode on devices with two SPI modules
Figure 5-50 shows the SPI CPU interfaces.
Copyright © 2020, Texas Instruments Incorporated
Specifications
119
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
PCLKCR8
Low-Speed
LSPCLK
CPU
SYSCLK
Prescaler
Bit Clock
SYSRS
SPISIMO
SPISOMI
SPICLK
SPISTE
SPI
GPIO MUX
SPIINT
PIE
SPITXINT
SPIRXDMA
SPITXDMA
DMA
Figure 5-50. SPI CPU Interface
120
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.11.5.1 SPI Master Mode Timings
The following section contains the SPI Master Mode Timings. For more information about the SPI in High-
Speed mode, see the Serial Peripheral Interface (SPI) chapter of the TMS320F28002x Microcontrollers
Technical Reference Manual.
Table 5-61 lists the SPI master mode timing requirements.
Table 5-62 lists the SPI master mode switching characteristics where the clock phase = 0. Figure 5-51
shows the SPI master mode external timing where the clock phase = 0.
Table 5-63 lists the SPI master mode switching characteristics where the clock phase = 1. Figure 5-52
shows the SPI master mode external timing where the clock phase = 1.
NOTE
All timing parameters for SPI High-Speed Mode assume a load capacitance of 5 pF on
SPICLK, SPISIMO, and SPISOMI.
Table 5-61. SPI Master Mode Timing Requirements
(1)
NO.
(BRR + 1)
MIN
MAX UNIT
High-Speed Mode
8
9
tsu(SOMI)M
th(SOMI)M
Setup time, SPISOMI valid before SPICLK
Hold time, SPISOMI valid after SPICLK
Even, Odd
Even, Odd
1
5
ns
ns
Normal Mode
8
9
tsu(SOMI)M
th(SOMI)M
Setup time, SPISOMI valid before SPICLK
Hold time, SPISOMI valid after SPICLK
Even, Odd
Even, Odd
15
0
ns
ns
(1) The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR is
greater than 3.
Copyright © 2020, Texas Instruments Incorporated
Specifications
121
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Table 5-62. SPI Master Mode Switching Characteristics (Clock Phase = 0)
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER
(BRR + 1)(1)
MIN
MAX UNIT
General
Even
Odd
4tc(LSPCLK)
5tc(LSPCLK)
0.5tc(SPC)M – 1 0.5tc(SPC)M + 1
128tc(LSPCLK)
1
2
tc(SPC)M
Cycle time, SPICLK
ns
ns
127tc(LSPCLK)
Even
0.5tc(SPC)M
+
+
1
tw(SPC1)M Pulse duration, SPICLK, first pulse
tw(SPC2)M Pulse duration, SPICLK, second pulse
Odd
Even
Odd
0.5tc(SPC)M + 0.5tc(LSPCLK) – 1 0.5tc(LSPCLK)
0.5tc(SPC)M – 1 0.5tc(SPC)M + 1
0.5tc(SPC)M
–
+
1
3
ns
ns
ns
0.5tc(SPC)M – 0.5tc(LSPCLK) – 1 0.5tc(LSPCLK)
1.5tc(SPC)M
–
Even
1.5tc(SPC)M – 3tc(SYSCLK) – 3
3tc(SYSCLK) + 3
1.5tc(SPC)M
4tc(SYSCLK) + 3
0.5tc(SPC)M – 3 0.5tc(SPC)M + 3
23
24
td(SPC)M
Delay time, SPISTE active to SPICLK
Valid time, SPICLK to SPISTE inactive
–
Odd
1.5tc(SPC)M – 4tc(SYSCLK) – 3
Even
0.5tc(SPC)M
–
+
3
tv(STE)M
Odd
0.5tc(SPC)M – 0.5tc(LSPCLK) – 3 0.5tc(LSPCLK)
High-Speed Mode
4
td(SIMO)M Delay time, SPICLK to SPISIMO valid
Even, Odd
Even
1
ns
ns
0.5tc(SPC)M – 3
5
tv(SIMO)M Valid time, SPISIMO valid after SPICLK
Odd
0.5tc(SPC)M – 0.5tc(LSPCLK) – 3
Normal Mode
4
td(SIMO)M Delay time, SPICLK to SPISIMO valid
Even, Odd
Even
1
ns
ns
0.5tc(SPC)M – 3
5
tv(SIMO)M Valid time, SPISIMO valid after SPICLK
Odd
0.5tc(SPC)M – 0.5tc(LSPCLK) – 3
(1) The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR is
greater than 3.
122
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Table 5-63. SPI Master Mode Switching Characteristics (Clock Phase = 1)
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER
(BRR + 1)
MIN
MAX UNIT
General
Even
Odd
4tc(LSPCLK)
5tc(LSPCLK)
0.5tc(SPC)M – 1 0.5tc(SPC)M + 1
128tc(LSPCLK)
1
2
tc(SPC)M
Cycle time, SPICLK
ns
ns
127tc(LSPCLK)
Even
0.5tc(SPC)M
–
+
1
tw(SPCH)M Pulse duration, SPICLK, first pulse
tw(SPC2)M Pulse duration, SPICLK, second pulse
Odd
Even
Odd
0.5tc(SPC)M – 0.5tc(LSPCLK) – 1 0.5tc(LSPCLK)
0.5tc(SPC)M – 1 0.5tc(SPC)M + 1
0.5tc(SPC)M
+
+
1
3
ns
0.5tc(SPC)M + 0.5tc(LSPCLK) – 1 0.5tc(LSPCLK)
2tc(SPC)M
3tc(SYSCLK) + 2
–
23
24
td(SPC)M
td(STE)M
Delay time, SPISTE valid to SPICLK
Delay time, SPICLK to SPISTE invalid
Even, Odd
2tc(SPC)M – 3tc(SYSCLK) – 3
ns
ns
Even
Odd
–3
–3
2
2
High-Speed Mode
Even
Odd
0.5tc(SPC)M – 2
0.5tc(SPC)M + 0.5tc(LSPCLK) – 2
0.5tc(SPC)M – 3
4
5
td(SIMO)M Delay time, SPISIMO valid to SPICLK
tv(SIMO)M Valid time, SPISIMO valid after SPICLK
ns
ns
Even
Odd
0.5tc(SPC)M – 0.5tc(LSPCLK) – 3
Normal Mode
Even
Odd
0.5tc(SPC)M – 2
0.5tc(SPC)M + 0.5tc(LSPCLK) – 2
0.5tc(SPC)M – 3
4
5
td(SIMO)M Delay time, SPISIMO valid to SPICLK
ns
ns
Even
Odd
tv(SIMO)M Valid time, SPISIMO valid after SPICLK
0.5tc(SPC)M – 0.5tc(LSPCLK) – 3
Copyright © 2020, Texas Instruments Incorporated
Specifications
123
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISIMO
Master Out Data Is Valid
8
9
Master In Data
Must Be Valid
SPISOMI
SPISTE(A)
24
23
A. On the trailing end of the word, SPISTE will go inactive except between back-to-back transmit words in both FIFO and
non-FIFO modes.
Figure 5-51. SPI Master Mode External Timing (Clock Phase = 0)
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISIMO
Master Out Data Is Valid
8
9
Master In Data Must
Be Valid
SPISOMI
SPISTE(A)
24
23
A. On the trailing end of the word, SPISTE will go inactive except between back-to-back transmit words in both FIFO and
non-FIFO modes.
Figure 5-52. SPI Master Mode External Timing (Clock Phase = 1)
124
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.11.5.2 SPI Slave Mode Timings
The following section contains the SPI Slave Mode Timings. For more information about the SPI in High-
Speed mode, see the Serial Peripheral Interface (SPI) chapter of the TMS320F28002x Microcontrollers
Technical Reference Manual.
Table 5-65 lists the SPI slave mode switching characteristics. Table 5-64 lists the SPI slave mode timing
requirements.
Figure 5-53 shows the SPI slave mode external timing where the clock phase = 0. Figure 5-54 shows the
SPI slave mode external timing where the clock phase = 1.
Table 5-64. SPI Slave Mode Timing Requirements
NO.
12
MIN
4tc(SYSCLK)
MAX UNIT
tc(SPC)S
Cycle time, SPICLK
ns
ns
ns
ns
ns
ns
ns
13
14
19
20
25
26
tw(SPC1)S
tw(SPC2)S
tsu(SIMO)S
th(SIMO)S
tsu(STE)S
th(STE)S
Pulse duration, SPICLK, first pulse
Pulse duration, SPICLK, second pulse
Setup time, SPISIMO valid before SPICLK
Hold time, SPISIMO valid after SPICLK
Setup time, SPISTE valid before SPICLK
Hold time, SPISTE invalid after SPICLK
2tc(SYSCLK) – 1
2tc(SYSCLK) – 1
1.5tc(SYSCLK)
1.5tc(SYSCLK)
1.5tc(SYSCLK) + 25
1.5tc(SYSCLK)
Table 5-65. SPI Slave Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
NO.
15
16
PARAMETER
MIN
MAX UNIT
td(SOMI)S
tv(SOMI)S
Delay time, SPICLK to SPISOMI valid
Valid time, SPISOMI valid after SPICLK
12
ns
ns
0
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
15
16
SPISOMI
SPISOMI Data Is Valid
19
20
SPISIMO Data
Must Be Valid
SPISIMO
SPISTE
25
26
Figure 5-53. SPI Slave Mode External Timing (Clock Phase = 0)
Copyright © 2020, Texas Instruments Incorporated
Specifications
125
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
15
SPISOMI
SPISOMI Data Is Valid
Data Valid
Data Valid
16
19
20
SPISIMO Data
Must Be Valid
SPISIMO
SPISTE
26
25
Figure 5-54. SPI Slave Mode External Timing (Clock Phase = 1)
126
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.11.6 Local Interconnect Network (LIN)
This device contains one Local Interconnect Network (LIN) module. The LIN module adheres to the LIN
2.1 standard as defined by the LIN Specification Package Revision 2.1. The LIN is a low-cost serial
interface designed for applications where the CAN protocol may be too expensive to implement, such as
small subnetworks for cabin comfort functions like interior lighting or window control in an automotive
application.
The LIN standard is based on the SCI (UART) serial data link format. The communication concept is
single-master and multiple-slave with a message identification for multicast transmission between any
network nodes.
The LIN module can be programmed to work either as an SCI or as a LIN as the core of the module is an
SCI. The hardware features of the SCI are augmented to achieve LIN compatibility. The SCI module is a
universal asynchronous receiver-transmitter (UART) that implements the standard non-return-to-zero
format.
Though the registers are common for LIN and SCI, the register descriptions have notes to identify the
register/bit usage in different modes. Because of this, code written for this module cannot be directly
ported to the stand-alone SCI module and vice versa.
The LIN module has the following features:
•
•
•
•
•
•
Compatibility with LIN 1.3, 2.0 and 2.1 protocols
Configurable baud rate up to 20 kbps (as per LIN 2.1 protocol)
Two external pins: LINRX and LINTX
Multibuffered receive and transmit units
Identification masks for message filtering
Automatic master header generation
–
–
–
Programmable synchronization break field
Synchronization field
Identifier field
•
Slave automatic synchronization
–
–
–
Synchronization break detection
Optional baud rate update
Synchronization validation
•
•
•
231 programmable transmission rates with 7 fractional bits
Wakeup on LINRX dominant level from transceiver
Automatic wakeup support
–
–
Wakeup signal generation
Expiration times on wakeup signals
•
•
Automatic bus idle detection
Error detection
–
–
–
–
–
–
Bit error
Bus error
No-response error
Checksum error
Synchronization field error
Parity error
•
Capability to use direct memory access (DMA) for transmit and receive data
Copyright © 2020, Texas Instruments Incorporated
Specifications
127
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
•
Two interrupt lines with priority encoding for:
–
–
–
Receive
Transmit
ID, error, and status
•
•
•
•
•
Support for LIN 2.0 checksum
Enhanced synchronizer finite state machine (FSM) support for frame processing
Enhanced handling of extended frames
Enhanced baud rate generator
Update wakeup/go to sleep
Figure 5-55 shows the LIN block diagram.
READ DATA BUS
WRITE DATA BUS
ADDRESS BUS
CHECKSUM
CALCULATOR
INTERFACE
ID PARTY
CHECKER
BIT
MONITOR
TXRX ERROR
DETECTOR (TED)
TIME-OUT
CONTROL
COUNTER
LINRX/
SCIRX
COMPARE
LINTX/
SCITX
DMA
CONTROL
MASK
FILTER
8 RECEIVE
BUFFERS
FSM
8 TRANSMIT
BUFFERS
SYNCHRONIZER
Figure 5-55. LIN Block Diagram
128
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.11.7 Fast Serial Interface (FSI)
The Fast Serial Interface (FSI) module is a serial communication peripheral capable of reliable and robust
high-speed communications. The FSI is designed to ensure data robustness across many system
conditions such as chip-to-chip as well as board-to-board across an isolation barrier. Payload integrity
checks such as CRC, start- and end-of-frame patterns, and user-defined tags, are encoded before
transmit and then verified after receipt without additional CPU interaction. Line breaks can be detected
using periodic transmissions, all managed and monitored by hardware. The FSI is also tightly integrated
with other control peripherals on the device. To ensure that the latest sensor data or control parameters
are available, frames can be transmitted on every control loop period. An integrated skew-compensation
block has been added on the receiver to handle skew that may occur between the clock and data signals
due to a variety of factors, including trace-length mismatch and skews induced by an isolation chip. With
embedded data robustness checks, data-link integrity checks, skew compensation, and integration with
control peripherals, the FSI can enable high-speed, robust communication in any system. These and
many other features of the FSI follow.
The FSI module includes the following features:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Independent transmitter and receiver cores
Source-synchronous transmission
Dual data rate (DDR)
One or two data lines
Programmable data length
Skew adjustment block to compensate for board and system delay mismatches
Frame error detection
Programmable frame tagging for message filtering
Hardware ping to detect line breaks during communication (ping watchdog)
Two interrupts per FSI core
Externally triggered frame generation
Hardware- or software-calculated CRC
Embedded ECC computation module
Register write protection
DMA support
SPI compatibility mode (limited features available)
Operating the FSI at maximum speed (50 MHz) at dual data rate (100 Mbps) may require the integrated
skew compensation block to be configured according to the specific operating conditions on a case-by-
case basis. The Fast Serial Interface (FSI) Skew Compensation Application Report provides example
software on how to configure and set up the integrated skew compensation block on the Fast Serial
Interface.
The FSI consists of independent transmitter (FSITX) and receiver (FSIRX) cores. The FSITX and FSIRX
cores are configured and operated independently. The features available on the FSITX and FSIRX are
described in Section 5.11.7.1 and Section 5.11.7.2, respectively.
Copyright © 2020, Texas Instruments Incorporated
Specifications
129
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.11.7.1 FSI Transmitter
The FSI transmitter module handles the framing of data, CRC generation, signal generation of TXCLK,
TXD0, and TXD1, as well as interrupt generation. The operation of the transmitter core is controlled and
configured through programmable control registers. The transmitter control registers let the CPU program,
control, and monitor the operation of the FSI transmitter. The transmit data buffer is accessible by the
CPU and the DMA.
The transmitter has the following features:
•
•
•
•
•
•
•
•
•
Automated ping frame generation
Externally triggered ping frames
Externally triggered data frames
Software-configurable frame lengths
16-word data buffer
Data buffer underrun and overrun detection
Hardware-generated CRC on data bits
Software ECC calculation on select data
DMA support
Figure 5-56 shows the FSITX CPU interface. Figure 5-57 shows the high-level block diagram of the
FSITX. Not all data paths and internal connections are shown. This diagram provides a high-level
overview of the internal modules present in the FSITX.
PLLRAWCLK
PCLKCR18
SYSCLK
SYSRSN
C28x
ePIE
FSITXyINT1
FSITXyINT2
FSITXyCLK
FSITXyD0
FSITXyD1
FSITX
DMA
FSITXyDMA
32
A. The signals connected to the trigger muxes are described in the External Frame Trigger Mux section of the Fast
Serial Interface (FSI) chapter in the TMS320F28002x Microcontrollers Technical Reference Manual.
Figure 5-56. FSITX CPU Interface
130
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
FSITX
PLLRAWCLK
SYSRSN
SYSCLK
FSI Mode:
TXCLKIN
Transmit Clock
Generator
TXCLK = TXCLKIN/2
SPI Signaling Mode:
TXCLK = TXCLKIN
Register Interface
Core Reset
FSITXINT1
FSITXINT2
Control Registers,
Interrupt Management
TXCLK
TXD0
TXD1
Ping Time-out Counter
FSITX_DMA_EVT
Transmitter Core
External Frame Triggers
Transmit Data
Buffer
ECC Logic
Figure 5-57. FSITX Block Diagram
5.11.7.1.1 FSITX Electrical Data and Timing
Table 5-66 lists the FSITX switching characteristics. Figure 5-58 shows the FSITX timings.
Table 5-66. FSITX Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
NO.
PARAMETER
MIN
20
MAX
UNIT
ns
1
2
tc(TXCLK)
tw(TXCLK)
Cycle time, TXCLK
Pulse width, TXCLK low or TXCLK high
(0.5tc(TXCLK)) – 1
(0.5tc(TXCLK)) + 1
(0.25tc(TXCLK)) + 2
ns
Delay time, TXCLK rising or falling toTXD
valid
3
td(TXCLK–TXD)
(0.25tc(TXCLK)) – 2
-2
ns
ns
Delay skew introduced between TXCLK-
TDM_CLK delay and TXDx-TDM_Dx delays
TDM1
tskew(TDM_CLK-TDM_Dx)
2
1
2
FSITXCLK
FSITXD0
FSITXD1
3
Figure 5-58. FSITX Timings
Copyright © 2020, Texas Instruments Incorporated
Specifications
131
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.11.7.2 FSI Receiver
The receiver module interfaces to the FSI clock (RXCLK), and data lines (RXD0 and RXD1) after they
pass through an optional programmable delay line. The receiver core handles the data framing, CRC
computation, and frame-related error checking. The receiver bit clock and state machine are run by the
RXCLK input, which is asynchronous to the device system clock.
The receiver control registers let the CPU program, control, and monitor the operation of the FSIRX. The
receive data buffer is accessible by the CPU, HIC, and the DMA.
The receiver core has the following features:
•
•
•
•
•
•
•
•
•
16-word data buffer
Multiple supported frame types
Ping frame watchdog
Frame watchdog
CRC calculation and comparison in hardware
ECC detection
Programmable delay line control on incoming signals
DMA support
SPI compatibility mode
Figure 5-59 shows the FSIRX CPU interface. Figure 5-60 provides a high-level overview of the internal
modules present in the FSIRX. Not all data paths and internal connections are shown.
PCLKCR18
SYSCLK
SYSRSN
C28x
ePIE
FSIRXyINT1
FSIRXyINT2
FSIRXyCLK
FSIRXyD0
FSIRXyD1
FSIRX
DMA
FSIRXyDMA
Figure 5-59. FSIRX CPU Interface
132
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
FSIRX
SYSRSn
SYSCLK
Frame Watchdog
Core Reset
Register Interface
FSIRXINT1
Control Registers,
Interrupt Management
FSIRXINT2
RXCLK
RXD0
Ping Watchdog
FSIRX_DMA_EVT
Receiver Core
Skew
Control
RXD1
Receive Data
Buffer
ECC Check
Logic
Figure 5-60. FSIRX Block Diagram
5.11.7.2.1 FSIRX Electrical Data and Timing
Table 5-68 lists the FSIRX timing requirements. Table 5-68 shows the FSIRX timings.
Table 5-67. FSIRX Switching Characteristics
NO.
MIN
MAX
UNIT
RXCLK delay compensation at
RX_DLYLINE_CTRL[RXCLK_DLY]=31
1
2
3
4
td(RXCLK)
10
10
30
30
30
1
ns
RXD0 delay compensation at
RX_DLYLINE_CTRL[RXD0_DLY]=31
td(RXD0)
ns
ns
ns
RXD1 delay compensation
at RX_DLYLINE_CTRL[RXD1_DLY]=31
td(RXD1)
10
Incremental delay of each delay line element
for RXCLK, RXD0, and RXD1
td(DELAY_ELEMENT)
0.3
Table 5-68. FSIRX Timing Requirements
NO.
MIN
MAX
UNIT
ns
1
2
tc(RXCLK)
tw(RXCLK)
Cycle time, RXCLK
20
Pulse width, RXCLK low or RXCLK high.
0.35tc(RXCLK)
0.65tc(RXCLK)
ns
Setup time with respect to RXCLK, applies
to both edges of the clock
3
4
tsu(RXCLK–RXD)
th(RXCLK–RXD)
1.7
ns
ns
Hold time with respect to RXCLK, applies to
both edges of the clock
2
Copyright © 2020, Texas Instruments Incorporated
Specifications
133
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
1
2
FSIRXCLK
FSIRXD0
FSIRXD1
3
4
Figure 5-61. FSIRX Timings
134
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.11.7.3 FSI SPI Compatibility Mode
The FSI supports a SPI compatibility mode to enable communication with programmable SPI devices. In
this mode, the FSI transmits its data in the same manner as a SPI in a single clock configuration mode.
While the FSI is able to physically interface with a SPI in this mode, the external device must be able to
encode and decode an FSI frame to communicate successfully. This is because the FSI transmits all SPI
frame phases with the exception of the preamble and postamble. The FSI provides the same data
validation and frame checking as if it was in standard FSI mode, allowing for more robust communication
without consuming CPU cycles. The external SPI is required to send all relevant information and can
access standard FSI features such as the ping frame watchdog on the FSIRX, frame tagging, or custom
CRC values. The list of features of SPI compatibility mode follows:
•
•
•
Data will transmit on rising edge and receive on falling edge of the clock.
Only 16-bit word size is supported.
TXD1 will be driven like an active-low chip-select signal. The signal will be low for the duration of the
full frame transmission.
•
•
•
No receiver chip-select input is required. RXD1 is not used. Data is shifted into the receiver on every
active clock edge.
No preamble or postamble clocks will be transmitted. All signals return to the idle state after the frame
phase is finished.
It is not possible to transmit in the SPI slave configuration because the FSI TXCLK cannot take an
external clock source.
5.11.7.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
Table 5-69 lists the FSITX SPI signaling mode switching characteristics. Figure 5-62 shows the FSITX SPI
signaling mode timings. Special timings are not required for the FSIRX in SPI signaling mode. FSIRX
timings listed in Table 5-68 are applicable in SPI compatibility mode. Setup and Hold times are only valid
on the falling edge of FSIRXCLK because this is the active edge in SPI signaling mode.
Table 5-69. FSITX SPI Signaling Mode Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
NO.
1
PARAMETER
MIN
20
MAX
UNIT
ns
tc(TXCLK)
Cycle time, TXCLK
2
tw(TXCLK)
Pulse width, TXCLK low or TXCLK high
Delay time, TXD0 valid after TXCLK high
Delay time, TXCLK high after TXD1 low
Delay time, TXD1 high after TXCLK low
(0.5tc(TXCLK)) – 1
(0.5tc(TXCLK)) + 1
3
ns
3
td(TXCLKH–TXD0)
td(TXD1-TXCLK)
td(TXCLK-TXD1)
ns
4
tw(TXCLK) – 3
tw(TXCLK)
ns
5
ns
1
2
FSITXCLK
3
FSITXD0
FSITXD1
5
4
Figure 5-62. FSITX SPI Signaling Mode Timings
Copyright © 2020, Texas Instruments Incorporated
Specifications
135
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.11.8 Host Interface Controller (HIC)
The HIC module allows an external host controller (master) to directly access resources of the device
(slave) by emulating the ASRAM protocol. It has two modes of operation: direct access and mailbox
access. In direct access mode, device resources is written to and read from directly by the external host.
In mailbox access mode, external host and device write to and read from a buffer and notify each other
when the buffer write/read is complete. For security reasons, the HIC has to be enabled by the device
before the external host can access it. Figure 5-63 shows the block diagram of the HIC.
Features of the HIC include:
•
•
•
•
•
•
•
•
Configurable I/O data lines of 8, 16 and 32-bit
Direct and mailbox access modes
8 address lines and 8 configurable base addresses for a total of 2048 possible addressable regions
Two 64 byte buffers for external host and device when using mailbox access mode
Interrupt generation on buffer full/empty
High throughput
Trigger HIC activity from other peripherals
Error indicators to the system or interface
Legend
HIC Pins
HIC Registers
HIC
I/O Interface
A[7:0]
Bus Master Interface
A[31:0]
D[31:0]
nBE[3:0]
nCS
H2DINT to PIE
D2HINT to Pin
WDATA[31:0]
RDATA[31:0]
Memory Mapped HIC
Configuration Interface
Host
To
Device
Device
To
Host
CTRL Regs
STATUS Regs
nWE
BASE_ADDR0
BASE_ADDR1
nOE
.
Mailbox
Buffer
Mailbox
Buffer
.
BASE_ADDRn
BASESEL[2:0]
nRDY
EVT_TRIGGER[15:0]
Figure 5-63. HIC Block Diagram
136
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
5.11.8.1 HIC Electrical Data and Timing
Table 5-70 lists the HIC timing requirements. Table 5-71 lists the HIC switching characteristics.
Table 5-70. HIC Timing Requirements
over operating free-air temperature range (unless otherwise noted)
MIN
MAX UNIT
Read/Write Parameters with nOE and nWE pins - Dual Read/Write pins
tsu(ABBV-OEV)
tsu(ABBV-WEV)
tsu(CSV-OEV)
tsu(CSV-WEV)
th(ABBV-OEIV)
th(ABBV-WEIV)
tw(OEV)
Setup time, A/BASESEL/nBE before nOE active
Setup time, A/BASESEL/nBE before nWE active
Setup time, nCS active before nOE active
Setup time, nCS active before nWE active
Hold time, A/BASESEL/nBE/nCS after nOE inactive
Hold time, A/BASESEL/nBE/nCS after nWE inactive
Active pulse width of nOE (Read)(1)
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
0.5tc(SYSCLK)
0.5tc(SYSCLK)
0
0
4tc(SYSCLK)
4tc(SYSCLK)
3tc(SYSCLK)
3tc(SYSCLK)
3tc(SYSCLK)
0
tw(WEV)
Active pulse width of nWE (Write)
Inactive pulse width of nCS(2)
Inactive Read pulse width of nOE(2)
Inactive Write pulse width of nWE(2)
tw(CSIV)
tw(OEIV)
tw(WEIV)
tsu(DV-WEV)
th(DV-WEIV)
Setup time, D before nWE active
Hold time, D after nWE inactive
0
Read/Write Parameters with RnW pin - Single Read/Write pin
tsu(ABBV-CSV)
tsu(RNWV-CSV)
th(ABBV-CSIV)
tw(CSV_RD)
tw(CSV_WR)
tw(CSIV)
Setup time, A/BASESEL/nBE before nCS active
Setup time, RnW before nCS active
Hold time, A/BASESEL/nBE/RnW after nCS inactive
Active pulse width of nCS for read operation(1)
Active pulse width of nCS for write operation
Inactive pulse width of nCS(2)
0
0.5tc(SYSCLK)
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
4tc(SYSCLK)
4tc(SYSCLK)
3tc(SYSCLK)
3tc(SYSCLK)
0
tw(RNWIV)
Inactive pulse width of RnW(2)
tsu(DV-CSV)
th(DV-CSIV)
Setup time, D before nCS active
Hold time, D after nCS inactive
0
(1) For accesses to the device region, additional 2 SYSCLK cycles are required.
(2) For accesses to the device region with nRDY pin, additional SYSCLK cycle is required.
Copyright © 2020, Texas Instruments Incorporated
Specifications
137
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
MAX UNIT
Table 5-71. HIC Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
Read/Write Parameters with nOE and nWE pins
(1)
td(OEV-DV)
Output data delay time : nOE to D output valid
3tc(SYSCLK)
4tc(SYSCLK) + 14 ns
2tc(SYSCLK) + 14 ns
11 ns
td(OEIV-DIV)
td(OEV-RDYV)
td(WEV-RDYV)
td(RDYV-DV)
tw(RDYACT)
Output data hold time : nOE invalid to D output invalid (tri-state)
Read Ready delay time : nOE to nRDY output valid
Write Ready delay time : nWE to nRDY output valid
Ready to Data delay time : nRDY output valid to D output valid
Active pulse width of nRDY output
1tc(SYSCLK)
0
0
-3
11 ns
3
ns
ns
2tc(SYSCLK)
Read/Write Parameters with RnW pin
(1)
td(CSV-DV)
Output delay time : nCS active to D output valid
3tc(SYSCLK)
1tc(SYSCLK)
0
4tc(SYSCLK) + 14 ns
2tc(SYSCLK) + 14 ns
11 ns
td(CSIV-DIV)
td(CSV-RDYV)
td(RDYV-DV)
tw(RDYACT)
Output hold time : nCS inactive to D output invalid (tri-state)
Output delay time : nCS to nRDY output valid
Ready to Data delay time : nRDY output valid to D output valid
Active pulse width of nRDY output
-3
3
ns
ns
2tc(SYSCLK)
(1) Applicable to mailbox accesses only. Direct memory map (Device) accesses are qualified with nRDY pin.
138
Specifications
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
6 Detailed Description
6.1 Overview
C2000™ 32-bit microcontrollers are optimized for processing, sensing, and actuation to improve closed-
loop performance in real-time control applications such as industrial motor drives; solar inverters and
digital power; electrical vehicles and transportation; motor control; and sensing and signal processing.
The TMS320F28002x (F28002x) is a powerful 32-bit floating-point microcontroller unit (MCU) that lets
designers incorporate crucial control peripherals, differentiated analog, and nonvolatile memory on a
single device.
The real-time control subsystem is based on TI’s 32-bit C28x CPU, which provides 100 MHz of signal
processing performance. The C28x CPU is further boosted by the new TMU extended instruction set,
which enables fast execution of algorithms with trigonometric operations commonly found in transforms
and torque loop calculations; and the VCRC extended instruction set, which reduces the latency for
complex math operations commonly found in encoded applications.
The F28002x supports up to 128KB (64KW) of flash memory in one bank. Up to 24KB (12KW) of on-chip
SRAM is also available in blocks of 4KB (2KW) for efficient system partitioning. Flash ECC, SRAM
ECC/parity, and dual-zone security are also supported.
High-performance analog blocks are integrated on the F28002x MCU to further enable system
consolidation. Two separate 12-bit ADCs provide precise and efficient management of multiple analog
signals, which ultimately boosts system throughput. Four analog comparator modules provide continuous
monitoring of input voltage levels for trip conditions.
The TMS320C2000™ devices contain industry-leading control peripherals with frequency-independent
ePWM/HRPWM and eCAP allow for a best-in-class level of control to the system.
Connectivity is supported through various industry-standard communication ports (such as SPI, SCI, I2C,
PMBus, LIN, and CAN) and offers multiple muxing options for optimal signal placement in a variety of
applications. New to the C2000™ platform is Host Interface Controller (HIC), a high throughput interface
that allows an external host to access resources of the TMS320F28002x. Additionally, in an industry first,
the FSI enables high-speed, robust communication to complement the rich set of peripherals that are
embedded in the device.
A specially enabled device variant, TMS320F28002xC, allows access to the Configurable Logic Block
(CLB) for additional interfacing features and allows access to the secure ROM, which includes a library to
enable InstaSPIN-FOC™. See Device Comparison for more information.
The Embedded Real-Time Analysis and Diagnostic (ERAD) module enhances the debug and system
analysis capabilities of the device by providing additional hardware breakpoints and counters for profiling.
To learn more about the C2000 MCUs, visit the C2000 Overview at www.ti.com/c2000.
Copyright © 2020, Texas Instruments Incorporated
Detailed Description
139
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
6.2 Functional Block Diagram
Figure 6-1 shows the CPU system and associated peripherals.
Boot ROM
Secure ROM
C28x CPU
FPU32
Flash Bank0
16 Sectors
64 KW (128 KB)
FINTDIV
TMU
VCRC
CPU Timers
DCC
DCSM
ePIE
ERAD
M0-M1 RAM
2 KW (4 KB)
BGCRC
HIC
LS4-LS7 RAM
8 KW (16 KB)
Crystal Oscillator
INTOSC1, INTOSC2
PLL
GS0 RAM
2 KW (4 KB)
DMA
6 Channles
PF1
PF3
PF4
PF2
PF7
PF8
PF9
Result
2x 12-Bit ADC
Data
14x ePWM Chan.
(8 Hi-Res Capable)
1x PMBUS
2x SPI
1x CAN
2x LIN
1x SCI
2x I2C
4x CMPSS
39x GPIO
Input XBAR
Output XBAR
ePWM XBAR
3x eCAP
(1 HRCAP Capable)
1x FSI RX
1x FSI TX
NMI
Watchdog
2x eQEP
(CW/CCW Support)
Windowed
Watchdog
Figure 6-1. Functional Block Diagram
140
Detailed Description
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
6.3 Memory
6.3.1 Memory Map
Table 6-1 describes the memory map. See the Memory Controller Module section of the System Control
chapter in the TMS320F28002x Microcontrollers Technical Reference Manual.
Table 6-1. Memory Map
START
ADDRESS
END
ADDRESS
HIC
ACCESS
DMA
ACCESS
ECC/
PARITY
ACCESS
PROTECTION
MEMORY
SIZE
SECURITY
M0 RAM
M1 RAM
1K x 16
1K x 16
512 x 16
2K x 16
2K x 16
2K x 16
2K x 16
2K x 16
2K x 16
1K x 16
1K x 16
64K x 16
32K x 16
64K x 16
0x0000 0000
0x0000 0400
0x0000 0D00
0x0000 A000
0x0000 A800
0x0000 B000
0x0000 B800
0x0000 C000
0x0004 9000
0x0007 0000
0x0007 8000
0x0008 0000
0x003E 8000
0x003F 0000
0x0000 03FF
0x0000 07FF
0x0000 0EFF
0x0000 A7FF
0x0000 AFFF
0x0000 B7FF
0x0000 BFFF
0x0000 C7FF
0x0004 97FF
0x0007 03FF
0x0007 83FF
0x0008 FFFF
0x003E FFFF
0x003F FFFF
-
-
ECC
ECC
-
Yes
-
-
-
-
Yes
PieVectTable
LS4 RAM
-
-
-
-
-
-
ECC
ECC
ECC
ECC
Parity
Parity
ECC
ECC
ECC
Parity
Parity
Yes
Yes
Yes
Yes
Yes
-
LS5 RAM
-
-
Yes
LS6 RAM
-
-
Yes
LS7 RAM
-
-
Yes
GS0 RAM
CAN A Message RAM
TI OTP(1)
Yes
Yes
Yes
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
User OTP
Yes
Yes
Yes
-
Flash
Secure ROM
Boot ROM
Pie Vector Fetch Error
(part of Boot ROM)
1 x 16
0x003F FFBE
0x003F FFC0
0x003F FFBF
0x003F FFFF
-
-
-
-
Parity
Parity
-
-
-
-
Default Vectors
(part of Boot ROM)
64 x 16
(1) TI OTP is for TI internal use only.
6.3.1.1 Dedicated RAM (Mx RAM)
The CPU subsystem has two dedicated ECC-capable RAM blocks: M0 and M1. These memories are
small nonsecure blocks that are tightly coupled with the CPU (that is, only the CPU has access to them).
6.3.1.2 Local Shared RAM (LSx RAM)
Local shared RAMs (LSx RAMs) are accessible to the CPU, HIC, and BGCRC. All LSx RAM blocks have
ECC. These memories are secure and have CPU access protection (CPU write/CPU fetch).
6.3.1.3 Global Shared RAM (GSx RAM)
Global shared RAMs (GSx RAMs) are accessible from the CPU, HIC, and DMA. The CPU, HIC, and DMA
have full read and write access to these memories. All GSx RAM blocks have parity. The GSx RAMs have
access protection (CPU write/CPU fetch/DMA write/HIC write).
Copyright © 2020, Texas Instruments Incorporated
Detailed Description
141
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
6.3.2 Flash Memory Map
On the F28002x devices one flash bank (128KB [64KW]) is available. Code to program the flash should
be executed out of RAM, there should not be any kind of access to the flash bank when an erase or
program operation is in progress. Table 6-2 lists the addresses of flash sectors available for each part
number.
Table 6-2. Addresses of Flash Sectors
ADDRESS
START
ECC ADDRESS
START
PART NUMBER
SECTOR
SIZE
END
SIZE
END
OTP Sectors
TI OTP
1K x 16
1K x 16
0x0007 0000
0x0007 8000
0x0007 03FF
0x0007 83FF
128 x 16
128 x 16
0x0107 0000
0x0107 1000
0x0107 007F
0x0107 107F
All F28002x
DCSM OTP
Bank 0 Sectors
Sector 0
Sector 1
Sector 2
Sector 3
Sector 4
Sector 5
Sector 6
Sector 7
Sector 8
Sector 9
Sector 10
Sector 11
Sector 12
Sector 13
Sector 14
Sector 15
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
0x0008 0000
0x0008 1000
0x0008 2000
0x0008 3000
0x0008 4000
0x0008 5000
0x0008 6000
0x0008 7000
0x0008 8000
0x0008 9000
0x0008 A000
0x0008 B000
0x0008 C000
0x0008 D000
0x0008 E000
0x0008 F000
0x0008 0FFF
0x0008 1FFF
0x0008 2FFF
0x0008 3FFF
0x0008 4FFF
0x0008 5FFF
0x0008 6FFF
0x0008 7FFF
0x0008 8FFF
0x0008 9FFF
0x0008 AFFF
0x0008 BFFF
0x0008 CFFF
0x0008 DFFF
0x0008 EFFF
0x0008 FFFF
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
0x0108 0000
0x0108 0200
0x0108 0400
0x0108 0600
0x0108 0800
0x0108 0A00
0x0108 0C00
0x0108 0E00
0x0108 1000
0x0108 1200
0x0108 1400
0x0108 1600
0x0108 1800
0x0108 1A00
0x0108 1C00
0x0108 1E00
0x0108 01FF
0x0108 03FF
0x0108 05FF
0x0108 07FF
0x0108 09FF
0x0108 0BFF
0x0108 0DFF
0x0108 0FFF
0x0108 11FF
0x0108 13FF
0x0108 15FF
0x0108 17FF
0x0108 19FF
0x0108 1BFF
0x0108 1DFF
0x0108 1FFF
All F28002x
F280025,
F280024,
F280023,
F280022
F280025,
F280024
142
Detailed Description
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
6.3.3 Peripheral Registers Memory Map
Table 6-3 lists the peripheral registers.
Table 6-3. Peripheral Registers Memory Map (C28x)
Bit Field Name
Pipeline
Protected
DMA
Access
HIC
Access
DriverLib Name
Base Address
Instance
Structure
Peripheral Frame 0 (PF0)
ADCARESULT_BASE
ADCCRESULT_BASE
CPUTIMER0_BASE
CPUTIMER1_BASE
CPUTIMER2_BASE
PIECTRL_BASE
AdcaResultRegs
AdccResultRegs
CpuTimer0Regs
CpuTimer1Regs
CpuTimer2Regs
PieCtrlRegs
ADC_RESULT_REGS
ADC_RESULT_REGS
CPUTIMER_REGS
CPUTIMER_REGS
CPUTIMER_REGS
PIE_CTRL_REGS
DMA_REGS
0x0000_0B00
0x0000_0B40
0x0000_0C00
0x0000_0C08
0x0000_0C10
0x0000_0CE0
0x0000_1000
0x0000_1020
0x0000_1040
0x0000_1060
0x0000_1080
0x0000_10A0
0x0000_10C0
-
-
-
-
-
-
-
-
-
-
-
-
-
YES
YES
YES
YES
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DmaRegs
DMA_BASE
Dmach1Regs
Dmach2Regs
Dmach3Regs
Dmach4Regs
Dmach5Regs
Dmach6Regs
DMA_CH_REGS
DMA_CH_REGS
DMA_CH_REGS
DMA_CH_REGS
DMA_CH_REGS
DMA_CH_REGS
DMA_CH1_BASE
DMA_CH2_BASE
DMA_CH3_BASE
DMA_CH4_BASE
DMA_CH5_BASE
DMA_CH6_BASE
Peripheral Frame 1 (PF1)
CLB1_LOGICCFG_BASE
CLB1_LOGICCTRL_BASE
CLB1_DATAEXCH_BASE
CLB2_LOGICCFG_BASE
CLB1_DATAEXCH_BASE
CLB2_LOGICCFG_BASE
EPWM1_BASE
Clb1LogicCfgRegs
Clb1LogicCtrlRegs
Clb1DataExchRegs
Clb2LogicCfgRegs
Clb1DataExchRegs
Clb2LogicCfgRegs
EPwm1Regs
CLB_LOGIC_CONFIG_REGS
CLB_LOGIC_CONTROL_REGS
CLB_DATA_EXCHANGE_REGS
CLB_LOGIC_CONFIG_REGS
CLB_DATA_EXCHANGE_REGS
CLB_LOGIC_CONFIG_REGS
EPWM_REGS
0x0000_3000
0x0000_3100
0x0000_3180
0x0000_3200
0x0000_3300
0x0000_3380
0x0000_4000
0x0000_4100
0x0000_4200
0x0000_4300
0x0000_4400
0x0000_4500
0x0000_4600
0x0000_5100
0x0000_5140
0x0000_5200
0x0000_5240
0x0000_5280
0x0000_52A0
0x0000_5C80
0x0000_5CA0
0x0000_5CC0
0x0000_5CE0
-
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
-
-
-
-
-
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
EPwm2Regs
EPWM_REGS
EPWM2_BASE
EPwm3Regs
EPWM_REGS
EPWM3_BASE
EPwm4Regs
EPWM_REGS
EPWM4_BASE
EPwm5Regs
EPWM_REGS
EPWM5_BASE
EPwm6Regs
EPWM_REGS
EPWM6_BASE
EPwm7Regs
EPWM_REGS
EPWM7_BASE
EQep1Regs
EQEP_REGS
EQEP1_BASE
EQep2Regs
EQEP_REGS
EQEP2_BASE
ECap1Regs
ECAP_REGS
ECAP1_BASE
ECap2Regs
ECAP_REGS
ECAP2_BASE
ECap3Regs
ECAP_REGS
ECAP3_BASE
Hrcap3Regs
HRCAP_REGS
HRCAP3_BASE
Cmpss1Regs
Cmpss2Regs
Cmpss3Regs
Cmpss4Regs
CMPSS_REGS
CMPSS1_BASE
CMPSS_REGS
CMPSS2_BASE
CMPSS_REGS
CMPSS3_BASE
CMPSS_REGS
CMPSS4_BASE
Peripheral Frame 2 (PF2)
SPIA_BASE
SpiaRegs
SPI_REGS
SPI_REGS
0x0000_6100
0x0000_6110
0x0000_6340
0x0000_6400
0x0000_6500
0x0000_6600
0x0000_6680
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
SpibRegs
SPIB_BASE
BgcrcCpuRegs
PmbusaRegs
HicRegs
BGCRC_REGS
PMBUS_REGS
HIC_CFG_REGS
FSI_TX_REGS
FSI_RX_REGS
BGCRC_CPU_BASE
PMBUSA_BASE
HIC_BASE
FsiTxaRegs
FsiRxaRegs
FSITXA_BASE
FSIRXA_BASE
Copyright © 2020, Texas Instruments Incorporated
Detailed Description
143
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Table 6-3. Peripheral Registers Memory Map (C28x) (continued)
Bit Field Name
Pipeline
Protected
DMA
Access
HIC
Access
DriverLib Name
Base Address
Instance
Structure
Peripheral Frame 3 (PF3)
ADCA_BASE
AdcaRegs
ADC_REGS
ADC_REGS
0x0000_7400
0x0000_7500
YES
YES
-
-
-
-
AdccRegs
ADCC_BASE
Peripheral Frame 4 (PF4)
INPUTXBAR_BASE
XBAR_BASE
InputXbarRegs
XbarRegs
INPUT_XBAR_REGS
XBAR_REGS
0x0000_7900
0x0000_7920
0x0000_7940
0x0000_7960
0x0000_7980
0x0000_7A00
0x0000_7A40
0x0000_7A80
0x0000_7BC0
0x0000_7C00
0x0000_7F00
0x0000_7F80
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SyncSocRegs
SYNC_SOC_REGS
SYNCSOC_BASE
-
InputXbar2Regs
DmaClaSrcSelRegs
EPwmXbarRegs
ClbXbarRegs
INPUT_XBAR_REGS
DMA_CLA_SRC_SEL_REGS
EPWM_XBAR_REGS
CLB_XBAR_REGS
INPUTXBAR2_BASE
DMACLASRCSEL_BASE
EPWMXBAR_BASE
CLBXBAR_BASE
-
-
-
-
OutputXbarRegs
OutputXbar2Regs
GpioCtrlRegs
OUTPUT_XBAR_REGS
OUTPUT_XBAR_REGS
GPIO_CTRL_REGS
OUTPUTXBAR_BASE
OUTPUTXBAR2_BASE
GPIOCTRL_BASE
-
-
-
-
GpioDataRegs
GpioDataReadRegs
GPIO_DATA_REGS
GPIO_DATA_READ_REGS
GPIODATA_BASE
GPIODATAREAD_BASE
Peripheral Frame 5 (PF5)
DEVCFG_BASE
YES
DevCfgRegs
DEV_CFG_REGS
CLK_CFG_REGS
0x0005_D000
0x0005_D200
0x0005_D300
0x0005_D500
0x0005_D700
0x0005_F000
0x0005_F040
0x0005_F070
0x0005_F080
YES
YES
YES
YES
YES
YES
YES
YES
YES
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ClkCfgRegs
CLKCFG_BASE
CpuSysRegs
CPU_SYS_REGS
CPUSYS_BASE
PeriphAcRegs
PERIPH_AC_REGS
PERIPHAC_BASE
AnalogSubsysRegs
DcsmBank0Z1Regs
DcsmBank0Z2Regs
DcsmCommonRegs
DcsmCommon2Regs
ANALOG_SUBSYS_REGS
DCSM_BANK0_Z1_REGS
DCSM_BANK0_Z2_REGS
DCSM_COMMON_REGS
DCSM_COMMON2_REGS
ANALOGSUBSYS_BASE
DCSM_BANK0_Z1_BASE
DCSM_BANK0_Z2_BASE
DCSMCOMMON_BASE
DCSMCOMMON2_BASE
Peripheral Frame 6 (PF6)
MEMCFG_BASE
MemCfgRegs
MEM_CFG_REGS
ACCESSPROTECTION_REGS
MEMORY_ERROR_REGS
ROM_WAIT_STATE_REGS
ROM_PREFETCH_REGS
FLASH_CTRL_REGS
0x0005_F400
0x0005_F500
0x0005_F540
0x0005_F580
0x0005_F588
0x0005_F800
0x0005_FB00
YES
YES
YES
YES
YES
YES
YES
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AccessProtectionRegs
MemoryErrorRegs
RomWaitStateRegs
RomPrefetchRegs
Flash0CtrlRegs
ACCESSPROTECTION_BASE
MEMORYERROR_BASE
ROMWAITSTATE_BASE
ROMPREFETCH_BASE
FLASH0CTRL_BASE
FLASH0ECCREGS_BASE
Peripheral Frame 7 (PF7)
CANA_BASE
Flash0EccRegs
FLASH_ECC_REGS
CanaRegs
CAN_REGS
CAN_MBOX
0x0004_8000
0x0004_9000
0x0005_E000
0x0005_E200
0x0005_E700
0x0005_E740
0x0005_E800
0x0005_E900
0x0005_E908
0x0005_E910
0x0005_E918
0x0005_E920
0x0005_E928
0x0005_E930
0x0005_E938
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
CanaMboxRegs
HwbistRegs
CANAMBOX_BASE
HWBIST_BASE
YES
YES
HWBIST_REGS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MpostRegs
MPOST_REGS
MPOST_BASE
Dcc0Regs
DCC_REGS
DCC0_BASE
Dcc1Regs
DCC_REGS
DCC1_BASE
EradGlobalRegs
EradHWBP1Regs
EradHWBP2Regs
EradHWBP3Regs
EradHWBP4Regs
EradHWBP5Regs
EradHWBP6Regs
EradHWBP7Regs
EradHWBP8Regs
ERAD_GLOBAL_REGS
ERAD_HWBP_REGS
ERAD_HWBP_REGS
ERAD_HWBP_REGS
ERAD_HWBP_REGS
ERAD_HWBP_REGS
ERAD_HWBP_REGS
ERAD_HWBP_REGS
ERAD_HWBP_REGS
ERADGLOBAL_BASE
ERADHWBP1_BASE
ERADHWBP2_BASE
ERADHWBP3_BASE
ERADHWBP4_BASE
ERADHWBP5_BASE
ERADHWBP6_BASE
ERADHWBP7_BASE
ERADHWBP8_BASE
144
Detailed Description
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Table 6-3. Peripheral Registers Memory Map (C28x) (continued)
Bit Field Name
Pipeline
Protected
DMA
Access
HIC
Access
DriverLib Name
Base Address
Instance
Structure
EradCounter1Regs
EradCounter2Regs
EradCounter3Regs
EradCounter4Regs
EradCRCGlobalRegs
EradCRC1Regs
EradCRC2Regs
EradCRC3Regs
EradCRC4Regs
EradCRC5Regs
EradCRC6Regs
EradCRC7Regs
EradCRC8Regs
ERAD_COUNTER_REGS
ERAD_COUNTER_REGS
ERAD_COUNTER_REGS
ERAD_COUNTER_REGS
ERAD_CRC_GLOBAL_REGS
ERAD_CRC_REGS
ERADCOUNTER1_BASE
ERADCOUNTER2_BASE
ERADCOUNTER3_BASE
ERADCOUNTER4_BASE
ERADCRCGLOBAL_BASE
ERADCRC1_BASE
ERADCRC2_BASE
ERADCRC3_BASE
ERADCRC4_BASE
ERADCRC5_BASE
ERADCRC6_BASE
ERADCRC7_BASE
ERADCRC8_BASE
Peripheral Frame 8 (PF8)
LINA_BASE
0x0005_E980
0x0005_E990
0x0005_E9A0
0x0005_E9B0
0x0005_EA00
0x0005_EA10
0x0005_EA20
0x0005_EA30
0x0005_EA40
0x0005_EA50
0x0005_EA60
0x0005_EA70
0x0005_EA80
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ERAD_CRC_REGS
ERAD_CRC_REGS
ERAD_CRC_REGS
ERAD_CRC_REGS
ERAD_CRC_REGS
ERAD_CRC_REGS
ERAD_CRC_REGS
LinaRegs
LinbRegs
LIN_REGS
LIN_REGS
0x0000_6A00
0x0000_6B00
YES
YES
YES
YES
YES
YES
LINB_BASE
Peripheral Frame 9 (PF9)
WD_BASE
WdRegs
WD_REGS
NMI_INTRUPT_REGS
XINT_REGS
0x0000_7000
0x0000_7060
0x0000_7070
0x0000_7200
0x0000_7300
0x0000_7340
YES
YES
YES
YES
YES
YES
-
-
-
-
-
-
YES
YES
YES
YES
YES
YES
NmiIntruptRegs
XintRegs
NMI_BASE
XINT_BASE
SciaRegs
I2caRegs
I2cbRegs
SCI_REGS
SCIA_BASE
I2C_REGS
I2CA_BASE
I2C_REGS
I2CB_BASE
Copyright © 2020, Texas Instruments Incorporated
Detailed Description
145
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
6.4 Identification
Table 6-4 lists the Device Identification Registers. Additional information on these device identification
registers can be found in the TMS320F28002x Microcontrollers Technical Reference Manual.
Table 6-4. Device Identification Registers
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
Device part identification number
TMS320F280025
TMS320F280025C
TMS320F280024
TMS320F280024C
TMS320F280023
TMS320F280023C
TMS320F280022
TMS320F280021
Silicon revision number
Revision 0
0x04FF 0500
0x04FF 0500
0x04FE 0500
0x04FE 0500
0x04FD 0500
0x04FD 0500
0x04FC 0500
0x04FB 0500
PARTIDH
0x0005 D00A
2
REVID
0x0005 D00C
0x0007 01E8
2
2
0x0000 0000
Unique identification number. This number is different on each
individual device with the same PARTIDH. This unique number
can be used as a serial number in the application. This number
is present only on TMS devices.
UID_UNIQUE
146
Detailed Description
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
6.5 Bus Architecture – Peripheral Connectivity
Table 6-5 lists a broad view of the peripheral and configuration register accessibility from each bus
master.
Table 6-5. Peripheral Connectivity
PERIPHERAL
C28
DMA
HIC
BGCRC
SYSTEM PERIPHERALS
CPU Timers
ERAD
Y
Y
GPIO Data
Y
Y
GPIO Pin Mapping and Configuration
XBAR Configuration
System Configuration
DCC
Y
Y
Y
Y
MEMORY
M0/M1
LSx
Y
Y
Y
Y
Y
Y
GS0
Y
Y
Y
ROM
FLASH
Y
Y
CONTROL PERIPHERALS
ePWM/HRPWM
eCAP
eQEP(1)
Y
Y
Y
Y
Y
Y
Y
Y
Y
ANALOG PERIPHERALS
CMPSS(1)
Y
Y
Y
Y
Y
ADC Configuration
ADC Results(1)
Y
Y
COMMUNICATION PERIPHERALS
CAN
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
FSITX/FSIRX
I2C
LIN
Y
Y
PMBus
SCI
SPI
Y
(1) These modules are accessible from DMA but cannot trigger a DMA transfer.
Copyright © 2020, Texas Instruments Incorporated
Detailed Description
147
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
6.6 C28x Processor
The CPU is a 32-bit fixed-point processor. This device draws from the best features of digital signal
processing; reduced instruction set computing (RISC); and microcontroller architectures, firmware, and
tool sets.
The CPU features include a modified Harvard architecture and circular addressing. The RISC features are
single-cycle instruction execution, register-to-register operations, and modified Harvard architecture. The
microcontroller features include ease of use through an intuitive instruction set, byte packing and
unpacking, and bit manipulation. The modified Harvard architecture of the CPU enables instruction and
data fetches to be performed in parallel. The CPU can read instructions and data while it writes data
simultaneously to maintain the single-cycle instruction operation across the pipeline. The CPU does this
over six separate address/data buses.
For more information on CPU architecture and instruction set, see the TMS320C28x CPU and Instruction
Set Reference Guide. For more information on the C28x Floating Point Unit (FPU), Trigonometric Math
Unit, and Cyclic Redundancy Check (VCRC) instruction sets, see the TMS320C28x Extended Instruction
Sets Technical Reference Manual. A brief overview of the FPU, TMU, and VCRC are provided here.
6.6.1 Floating-Point Unit (FPU)
The C28x plus floating-point (C28x+FPU) processor extends the capabilities of the C28x fixed-point CPU
by adding registers and instructions to support IEEE single-precision floating-point operations.
Devices with the C28x+FPU include the standard C28x register set plus an additional set of floating-point
unit registers. The additional floating-point unit registers are the following:
•
•
•
Eight floating-point result registers, RnH (where n = 0–7)
Floating-point Status Register (STF)
Repeat Block Register (RB)
All of the floating-point registers, except the RB, are shadowed. This shadowing can be used in high-
priority interrupts for fast context save and restore of the floating-point registers.
6.6.2 Fast Integer Division Unit
The Fast Integer Division (FINTDIV) unit of the C28x CPU uniquely supports three types of integer division
(Truncated, Modulus, Euclidean) of varying data type sizes (16/16, 32/16, 32/32, 64/32, 64/64) in unsigned
or signed formats.
•
•
Truncated integer division is naturally supported by C language (/, % operators).
Modulus and Euclidean divisions are variants that are more efficient for control algorithms and are
supported by C intrinsics.
All three types of integer division produce both a quotient and remainder component, are interruptible, and
execute in a minimum number of deterministic cycles (10 cycles for a 32/32 division). In addition, the Fast
Division capabilities of the C28x CPU uniquely support fast execution of floating-point 32-bit (in 5 cycles)
and 64-bit (in 20 cycles) division.
For more information about fast integer division, see the Fast Integer Division – A Differentiated Offering
From C2000™ Product Family Application Report.
148
Detailed Description
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
6.6.3 Trigonometric Math Unit (TMU)
The TMU extends the capabilities of a C28x+FPU by adding instructions and leveraging existing FPU
instructions to speed up the execution of common trigonometric and arithmetic operations listed in
Table 6-6.
Table 6-6. TMU Supported Instructions
INSTRUCTIONS
MPY2PIF32 RaH,RbH
C EQUIVALENT OPERATION
PIPELINE CYCLES
a = b * 2pi
a = b / 2pi
a = b/c
2/3
2/3
5
DIV2PIF32 RaH,RbH
DIVF32 RaH,RbH,RcH
SQRTF32 RaH,RbH
a = sqrt(b)
5
SINPUF32 RaH,RbH
COSPUF32 RaH,RbH
ATANPUF32 RaH,RbH
QUADF32 RaH,RbH,RcH,RdH
a = sin(b*2pi)
4
a = cos(b*2pi)
4
a = atan(b)/2pi
4
Operation to assist in calculating ATANPU2
5
No changes have been made to existing instructions, pipeline or memory bus architecture. All TMU
instructions use the existing FPU register set (R0H to R7H) to carry out their operations.
Exponent instruction IEXP2F32 and logarithmic instruction LOG2F32 have been added to support
computation of floating-point power function for the non-linear proportional integral derivative control
(NLPID) component of the C2000 Digital Control Library. These two added instructions reduce the power
function calculations from a typical of 300 cycles using library emulation to less than 10 cycles.
6.6.4 VCRC Unit
Cyclic redundancy check (CRC) algorithms provide a straightforward method for verifying data integrity
over large data blocks, communication packets, or code sections. The C28x+VCRC can perform 8-bit, 16-
bit, 24-bit, and 32-bit CRCs. For example, the VCRC can compute the CRC for a block length of 10 bytes
in 10 cycles. A CRC result register contains the current CRC, which is updated whenever a CRC
instruction is executed.
The following are the CRC polynomials used by the CRC calculation logic of the VCRC:
•
•
•
•
•
•
CRC8 polynomial = 0x07
CRC16 polynomial 1 = 0x8005
CRC16 polynomial 2 = 0x1021
CRC24 polynomial = 0x5d6dcb
CRC32 polynomial 1 = 0x04c11db7
CRC32 polynomial 2 = 0x1edc6f41
This module can calculate CRCs for a byte of data in a single cycle. The CRC calculation for CRC8,
CRC16, CRC24, and CRC32 is done byte-wise (instead of computing on a complete 16-bit or 32-bit data
read by the C28x core) to match the byte-wise computation requirement mandated by various standards.
The VCRC Unit also allows the user to provide the size (1b-32b) and value of any polynomial to fit custom
CRC requirements. The CRC execution time increases to three cycles when using a custom polynomial.
Copyright © 2020, Texas Instruments Incorporated
Detailed Description
149
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
6.7 Embedded Real-Time Analysis and Diagnostic (ERAD)
The ERAD module enhances the debug and system-analysis capabilities of the device. The debug and
system-analysis enhancements provided by the ERAD module is done outside of the CPU. The ERAD
module consists of the Enhanced Bus Comparator units and the System Event Counter units. The
Enhanced Bus Comparator units are used to generate hardware breakpoints, hardware watch points, and
other output events. The System Event Counter units are used to analyze and profile the system. The
ERAD module is accessible by the debugger and by the application software, which significantly increases
the debug capabilities of many real-time systems, especially in situations where debuggers are not
connected. In the TMS320F28002x devices, the ERAD module contains eight Enhanced Bus Comparator
units (which increases the number of Hardware breakpoints from two to ten) and four Benchmark System
Event Counter units.
6.8 Background CRC-32 (BGCRC)
The Background CRC (BGCRC) module computes a CRC-32 on a configurable block of memory. It
accomplishes this by fetching the specified block of memory during idle cycles (when the CPU, HIC, or
DMA is not accessing the memory block). The calculated CRC-32 value is compared against a golden
CRC-32 value to indicate a pass or fail. In essence, the BGCRC helps identify memory faults and
corruption.
The BGCRC module has the following features:
•
•
•
•
•
•
One cycle CRC-32 computation on 32 bits of data
No CPU bandwidth impact for zero wait state memory
Minimal CPU bandwidth impact for non-zero wait state memory
Dual operation modes (CRC-32 mode and scrub mode)
Watchdog timer to time CRC-32 completion
Ability to pause and resume CRC-32 computation
150
Detailed Description
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
6.9 Direct Memory Access (DMA)
The DMA module provides a hardware method of transferring data between peripherals and/or memory
without intervention from the CPU, thereby freeing up bandwidth for other system functions. Additionally,
the DMA has the capability to orthogonally rearrange the data as it is transferred as well as “ping-pong”
data between buffers. These features are useful for structuring data into blocks for optimal CPU
processing. Figure 6-2 shows a device-level block diagram of the DMA.
DMA features include:
•
•
Six channels with independent PIE interrupts
Peripheral interrupt trigger sources
–
–
–
–
–
–
–
–
ADC interrupts and EVT signals
External Interrupts
ePWM SOC signals
CPU timers
eCAP
SPI transmit and receive
CAN transmit and receive
LIN transmit and receive
•
Data sources and destinations:
–
–
–
–
GSx RAM
ADC result registers
Control peripheral registers (ePWM, eQEP, eCAP)
SPI, LIN, CAN, and PMBus registers
•
•
Word Size: 16-bit or 32-bit (SPI limited to 16-bit)
Throughput: Four cycles per word without arbitration
Copyright © 2020, Texas Instruments Incorporated
Detailed Description
151
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Global Shared
(GS0) RAM
ADC
WRAPPER
ADC
RESULTS
XINT
TIMER
CAN
LIN
C28x bus
DMA bus
DMA Trigger
TINT(0-2)
XINT(1-5)
Source Selection
ADCx.INT(1-5), ADCx.EVT
CANxIF(1-3)
C28x
PIE
DMACHSRCSEL1.CHx
DMACHSRCSEL2.CHx
CHx.MODE.PERINTSEL
(x = 1 to 6)
DMA
ECAP(1-3)DMA
EPWM(1-7).SOCA, EPWM(1-7.SOCB
SPITXDMA(A-B), SPIRXDMA(A-B)
FSITXADMA, FSIRXADMA
eCAP EPWM
SPI
PMBUS
FSI
Figure 6-2. DMA Block Diagram
152
Detailed Description
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
6.10 Device Boot Modes
This section explains the default boot modes, as well as all the available boot modes supported on this
device. The boot ROM uses the boot mode select, general purpose input/output (GPIO) pins to determine
the boot mode configuration.
Table 6-7 shows the boot mode options available for selection by the default boot mode select pins. Users
have the option to program the device to customize the boot modes selectable in the boot-up table as well
as the boot mode select pin GPIOs used.
All the peripheral boot modes that are supported use the first instance of the peripheral module (SCIA,
SPIA, I2CA, CANA, and so forth). Whenever these boot modes are referred to in this chapter, such as SCI
boot, it is actually referring to the first module instance, which means the SCI boot on the SCIA port. The
same applies to the other peripheral boots.
Table 6-7. Device Default Boot Modes
GPIO24
GPIO32
BOOT MODE
(DEFAULT BOOT MODE SELECT PIN 1)
(DEFAULT BOOT MODE SELECT PIN 0)
Parallel IO
SCI / Wait Boot(1)
CAN
0
0
1
1
0
1
0
1
Flash
(1) SCI boot mode can be used as a wait boot mode as long as SCI continues to wait for an 'A' or 'a' during the SCI autobaud lock process.
6.10.1 Device Boot Configurations
This section details what boot configurations are available and how to configure them. This device
supports from 0 boot mode select pins up to 3 boot mode select pins as well as from 1 configured boot
mode up to 8 configured boot modes.
To change and configure the device from the default settings to custom settings for your application, use
the following process:
1. Determine all the various ways you want application to be able to boot. (For example: Primary boot
option of Flash boot for your main application, secondary boot option of CAN boot for firmware
updates, tertiary boot option of SCI boot for debugging, etc)
2. Based on the number of boot modes needed, determine how many boot mode select pins (BMSPs)
are required to select between your selected boot modes. (For example: 2 BMSPs are required to
select between 3 boot mode options)
3. Assign the required BMSPs to a physical GPIO pin. (For example, BMSP0 to GPIO10, BMSP1 to
GPIO51, and BMSP2 left as default which is disabled). Refer to Section 6.10.1.1 for all the details on
performing these configurations.
4. Assign the determined boot mode definitions to indexes in your custom boot table that correlate to the
decoded value of the BMSPs. For example, BOOTDEF0=Boot to Flash, BOOTDEF1=CAN Boot,
BOOTDEF2=SCI Boot; all other BOOTDEFx are left as default/nothing). Refer to Section 6.10.1.2 for
all the details on setting up and configuring the custom boot mode table.
Additionally, provides some example use cases on how to configure the BMSPs and custom boot tables.
Copyright © 2020, Texas Instruments Incorporated
Detailed Description
153
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
6.10.1.1 Configuring Boot Mode Pins
This section explains how the boot mode select pins can be customized by the user, by programming the
BOOTPIN-CONFIG location (refer to Table 6-8) in the user-configurable dual-zone security module
(DCSM) OTP. The location in the DCSM OTP is Z1-OTP-BOOTPIN-CONFIG or Z2-OTP-BOOTPIN-
CONFIG. When debugging, EMU-BOOTPIN-CONFIG is the emulation equivalent of Z1-OTP-BOOTPIN-
CONFIG/Z2-OTP-BOOTPIN-CONFIG, and can be programmed to experiment with different boot modes
without writing to OTP. The device can be programmed to use 0, 1, 2, or 3 boot mode select pins as
needed.
NOTE
When using Z2-OTP-BOOTPIN-CONFIG, the configurations programmed in this location will
take priority over the configurations in Z1-OTP-BOOTPIN-CONFIG. It is recommended to
use Z1-OTP-BOOTPIN-CONFIG first and then if OTP configurations need to be altered,
switch to using Z2-OTP-BOOTPIN-CONFIG.
Table 6-8. BOOTPIN-CONFIG Bit Fields
BIT
31:24
23:16
15:8
NAME
DESCRIPTION
Key
Write 0x5A to these 8-bits to indicate the bits in this register are valid
Refer to BMSP0 description except for BMSP2
Refer to BMSP0 description except for BMSP1
Boot Mode Select Pin 2 (BMSP2)
Boot Mode Select Pin 1 (BMSP1)
Set to the GPIO pin to be used during boot (up to 255):
- 0x0 = GPIO0
- 0x01 = GPIO1
- and so on
7:0
Boot Mode Select Pin 0 (BMSP0)
Writing 0xFF disables BMSP0 and this pin is no longer used to select
the boot mode.
The following GPIOs cannot be used as a BMSP. If selected for a particular BMSP, the boot ROM
automatically selects the factory default GPIO (the factory default for BMSP2 is 0xFF, which disables the
BMSP).
•
•
•
•
GPIO 20 and GPIO 21
GPIO 36 and GPIO 38
GPIO 47 to GPIO 60
GPIO 63 to GPIO 223
154
Detailed Description
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Table 6-9. Standalone Boot Mode Select Pin Decoding
BOOTPIN_CONFIG
BMSP0
BMSP1
BMSP2
REALIZED BOOT MODE
KEY
!= 0x5A
Don’t Care
Don’t Care
Don’t Care
Boot as defined by the factory default BMSPs
Boot as defined in the boot table for boot mode
0xFF
0xFF
0xFF
0
(All BMSPs disabled)
Boot as defined by the value of BMSP0
(BMSP1 and BMSP2 disabled)
Valid GPIO
0xFF
0xFF
Valid GPIO
0xFF
0xFF
0xFF
Boot as defined by the value of BMSP1
(BMSP0 and BMSP2 disabled)
Boot as defined by the value of BMSP2
(BMSP0 and BMSP1 disabled)
0xFF
Valid GPIO
Boot as defined by the values of BMSP0 and
Valid GPIO
Valid GPIO
Valid GPIO
0xFF
0xFF
BMSP1
(BMSP2 disabled)
Boot as defined by the values of BMSP0 and
BMSP2
Valid GPIO
(BMSP1 disabled)
Boot as defined by the values of BMSP1 and
= 0x5A
0xFF
Valid GPIO
Valid GPIO
Valid GPIO
Valid GPIO
BMSP2
(BMSP0 disabled)
Boot as defined by the values of BMSP0,
BMSP1, and BMSP2
Valid GPIO
BMSP0 is reset to the factory default BMSP0
GPIO
Boot as defined by the values of BMSP0,
BMSP1, and BMSP2
Invalid GPIO
Valid GPIO
Valid GPIO
Valid GPIO
Invalid GPIO
Valid GPIO
Valid GPIO
Valid GPIO
Invalid GPIO
BMSP1 is reset to the factory default BMSP1
GPIO
Boot as defined by the values of BMSP0,
BMSP1, and BMSP2
BMSP2 is reset to the factory default state,
which is disabled
Boot as defined by the values of BMSP0 and
BMSP1
NOTE
When decoding the boot mode, BMSP0 is the least-significant-bit and BMSP2 is the most-
significant-bit of the boot table index value. It is recommended when disabling BMSPs to
start with disabling BMSP2. For example, in an instance when only using BMSP2 (BMSP1
and BMSP0 are disabled), then only the boot table indexes of 0 and 4 will be selectable. In
the instance when using only BMSP0, then the selectable boot table indexes are 0 and 1.
Copyright © 2020, Texas Instruments Incorporated
Detailed Description
155
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
6.10.1.2 Configuring Boot Mode Table Options
This section explains how to configure the boot definition table, BOOTDEF, for the device and the
associated boot options. The 64-bit location is located in user-configurable DCSM OTP in the Z1-OTP-
BOOTDEF-LOW and Z1-OTP-BOOTDEF-HIGH locations. When debugging, EMU-BOOTDEF-LOW and
EMU-BOOTDEF-HIGH are the emulation equivalents of Z1-OTP-BOOTDEF-LOW and Z1-OTP-
BOOTDEF-HIGH, and can be programmed to experiment with different boot mode options without writing
to OTP. The range of customization to the boot definition table depends on how many boot mode select
pins (BMSP) are being used. For example, 0 BMSPs equals to 1 table entry, 1 BMSP equals to 2 table
entries, 2 BMSPs equals to 4 table entries, and 3 BMSPs equals to 8 table entries. Refer to the
TMS320F28002x Microcontrollers Technical Reference Manual for examples on how to set up the
BOOTPIN_CONFIG and BOOTDEF values.
NOTE
The locations Z2-OTP-BOOTDEF-LOW and Z2-OTP-BOOTDEF-HIGH will be used instead
of Z1-OTP-BOOTDEF-LOW and Z1-OTP-BOOTDEF-HIGH locations when Z2-OTP-
BOOTPIN-CONFIG is configured. Refer to Configuring Boot Mode Pins for more details on
BOOTPIN_CONFIG usage.
Table 6-10. BOOTDEF Bit Fields
BYTE
POSITION
BOOTDEF NAME
NAME
DESCRIPTION
Set the boot mode for index 0 of the boot table.
Different boot modes and their options can
include, for example, a boot mode that uses
different GPIOs for a specific bootloader or a
different flash entry point address. Any
unsupported boot mode will cause the device to
either go to wait boot or boot to flash.
BOOT_DEF0
7:0
BOOT_DEF0 Mode/Options
Refer to GPIO Assignments for valid BOOTDEF
values to set in the table.
BOOT_DEF1
BOOT_DEF2
BOOT_DEF3
BOOT_DEF4
BOOT_DEF5
BOOT_DEF6
BOOT_DEF7
15:8
BOOT_DEF1 Mode/Options
BOOT_DEF2 Mode/Options
BOOT_DEF3 Mode/Options
BOOT_DEF4 Mode/Options
BOOT_DEF5 Mode/Options
BOOT_DEF6 Mode/Options
BOOT_DEF7 Mode/Options
23:16
31:24
39:32
47:40
55:48
63:56
Refer to BOOT_DEF0 description
156
Detailed Description
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
6.10.2 GPIO Assignments
This section details the GPIOs and boot option values used for boot mode set in the BOOT_DEF memory
location located at Z1-OTP-BOOTDEF-LOW/ Z2-OTP-BOOTDEF-LOW and Z1-OTP-BOOTDEF-HIGH/
Z2-OTP-BOOTDEF-HIGH. Refer to Configuring Boot Mode Table Options on how to configure
BOOT_DEF. When selecting a boot mode option, make sure to verify that the necessary pins are
available in the pin mux options for the specific device package being used.
Table 6-11. SCI Boot Options
OPTION
BOOTDEF VALUE
SCITXDA GPIO
GPIO29
SCIRXDA GPIO
GPIO28
GPIO17
GPIO9
0 (default)
0x01
0x21
0x41
0x61
0x81
1
2
3
4
GPIO16
GPIO8
GPIO2
GPIO3
GPIO16
GPIO3
Table 6-12. CAN Boot Options
OPTION
BOOTDEF VALUE
CANTXA GPIO
GPIO4
CANRXA GPIO
GPIO5
0 (default)
0x02
0x22
0x42
1
2
GPIO32
GPIO33
GPIO2
GPIO3
Table 6-13. I2C Boot Options
OPTION
BOOTDEF VALUE
SDAA GPIO
GPIO32
SCLA GPIO
GPIO33
GPIO1
0
1
2
0x07
0x27
0x47
GPIO0
GPIO10
GPIO8
Table 6-14. RAM Boot Options
RAM ENTRY POINT
(ADDRESS)
OPTION
BOOTDEF VALUE
0
0x05
0x0000 0000
Table 6-15. Flash Boot Options
FLASH ENTRY POINT
OPTION
BOOTDEF VALUE
FLASH SECTOR
(ADDRESS)
0x0008 0000
0x0008 4000
0x0008 8000
0x0008 EFF0
0 (default)
0x03
0x23
0x43
0x63
Bank0 Sector 0
Bank 0 Sector 4
1
2
3
Bank 0 Sector 8
Bank 0, End of Sector 14
Table 6-16. Wait Boot Options
OPTION
BOOTDEF VALUE
WATCHDOG
Enabled
0
1
0x04
0x24
Disabled
Copyright © 2020, Texas Instruments Incorporated
Detailed Description
157
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Table 6-17. SPI Boot Options
OPTION
BOOTDEF VALUE
SPISIMOA
GPIO2
SPISOMIA
GPIO1
SPICLKA
GPIO3
GPIO3
GPIO9
GPIO9
SPISTEA
0
1
2
3
0x06
0x26
0x46
0x66
GPIO5
GPIO0
GPIO16
GPIO8
GPIO1
GPIO10
GPIO17
GPIO11
GPIO11
GPIO8
Table 6-18. Parallel Boot Options
28x(DSP) CONTROL
GPIO
OPTION
0 (default)
BOOTDEF VALUE
0x00
D0-D7 GPIO
HOST CONTROL GPIO
D0 - GPIO28
D1 - GPIO1
D2 - GPIO2
D3 - GPIO3
D4 - GPIO4
D5 - GPIO5
D6 - GPIO6
D7 - GPIO7
D0 - GPIO0
D1 - GPIO1
D2 - GPIO2
D3 - GPIO3
D4 - GPIO4
D5 - GPIO5
D6 - GPIO6
D7 - GPIO7
GPIO16
GPIO29
1
0x20
GPIO16
GPIO11
158
Detailed Description
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
6.11 Dual Code Security Module
The dual code security module (DCSM) prevents access to on-chip secure memories. The term “secure”
means access to secure memories and resources is blocked. The term “unsecure” means access is
allowed; for example, through a debugging tool such as Code Composer Studio™ (CCS).
The code security mechanism offers protection for two zones, Zone 1 (Z1) and Zone 2 (Z2). The security
implementation for both the zones is identical. Each zone has its own dedicated secure resource (OTP
memory and secure ROM) and allocated secure resource (LSx RAM and flash sectors).
The security of each zone is ensured by its own 128-bit password (CSM password). The password for
each zone is stored in an OTP memory location based on a zone-specific link pointer. The link pointer
value can be changed to program a different set of security settings (including passwords) in OTP.
Code Security Module Disclaimer
THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED
TO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY AND IS
WARRANTED BY TEXAS INSTRUMENTS (TI), IN ACCORDANCE WITH ITS STANDARD
TERMS AND CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS FOR
THE WARRANTY PERIOD APPLICABLE FOR THIS DEVICE.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED
MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT
AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS
CONCERNING THE CSM OR OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,
INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY
OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE,
BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR
INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS.
Copyright © 2020, Texas Instruments Incorporated
Detailed Description
159
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
6.12 Watchdog
The watchdog module is the same as the one on previous TMS320C2000 devices, but with an optional
lower limit on the time between software resets of the counter. This windowed countdown is disabled by
default, so the watchdog is fully backward-compatible.
The watchdog generates either a reset or an interrupt. It is clocked from the internal oscillator with a
selectable frequency divider.
Figure 6-3 shows the various functional blocks within the watchdog module.
WDCR.WDPRECLKDIV
WDCR.WDPS
WDCR.WDDIS
WDCNTR
WDCLK
(INTOSC1)
Overflow
1-count
delay
8-bit
Watchdog
Counter
WDCLK
Divider
Watchdog
Prescaler
SCSR.WDOVERRIDE
SYSRSn
Clear
Count
WDWCR.MIN
WDKEY (7:0)
Watchdog
Window
Detector
Out of Window
Good Key
Watchdog
Key Detector
55 + AA
WDCR(WDCHK(2:0))
Bad Key
WDRSTn
WDINTn
Generate
512-WDCLK
Output Pulse
1
0
1
Watchdog Time-out
SCSR.WDENINT
Figure 6-3. Windowed Watchdog
160
Detailed Description
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
6.13 C28x Timers
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock
prescaling. The timers have a 32-bit count-down register that generates an interrupt when the counter
reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting.
When the counter reaches zero, it is automatically reloaded with a 32-bit period value.
CPU-Timer 0 is for general use and is connected to the PIE block. CPU-Timer 1 is also for general use
and is connected to INT13 of the CPU. CPU-Timer 2 is reserved for TI-RTOS. It is connected to INT14 of
the CPU. If TI-RTOS is not being used, CPU-Timer 2 is available for general use.
CPU-Timer 2 can be clocked by any one of the following:
•
•
•
•
SYSCLK (default)
Internal zero-pin oscillator 1 (INTOSC1)
Internal zero-pin oscillator 2 (INTOSC2)
X1 (XTAL)
6.14 Dual-Clock Comparator (DCC)
There are three Dual-Clock Comparators (DCC0 and DCC1) on the device. All three DCCs are only
accessible through CPU1. The DCC module is used for evaluating and monitoring the clock input based
on a second clock, which can be a more accurate and reliable version. This instrumentation is used to
detect faults in clock source or clock structures, thereby enhancing the system's safety metrics.
6.14.1 Features
The DCC has the following features:
•
Allows the application to ensure that a fixed ratio is maintained between frequencies of two clock
signals.
•
Supports the definition of a programmable tolerance window in terms of the number of reference clock
cycles.
•
•
•
Supports continuous monitoring without requiring application intervention.
Supports a single-sequence mode for spot measurements.
Allows the selection of a clock source for each of the counters, resulting in several specific use cases.
6.14.2 Mapping of DCCx (DCC0 and DCC1) Clock Source Inputs
Table 6-19 is the DCCx Clock Source0 table. Table 6-20 is the DCCx Clock Source1 table.
Table 6-19. DCCx Clock Source0 Table
DCCxCLKSRC0[3:0]
CLOCK NAME
XTAL/X1
0x0
0x1
INTOSC1
0x2
INTOSC2
0x5
CPU1.SYSCLK
INPUT XBAR (Output16 of input-xbar)
Reserved
0xC
others
Copyright © 2020, Texas Instruments Incorporated
Detailed Description
161
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Table 6-20. DCCx Clock Source1 Table
DCCxCLKSRC1[4:0]
CLOCK NAME
PLLRAWCLK
INTOSC1
0x0
0x2
0x3
0x6
INTOSC2
CPU1.SYSCLK
0x9
0xB
Input XBAR (Output15 of the input-xbar)
EPWMCLK
LSPCLK
0xC
0xD
0xE
ADCCLK
WDCLK
0xF
CAN0BITCLK
Reserved
others
162
Detailed Description
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
6.15 Configurable Logic Block (CLB)
The C2000 configurable logic block (CLB) is a collection of blocks that can be interconnected using
software to implement custom digital logic functions or enhance existing on-chip peripherals. The CLB is
able to enhance existing peripherals through a set of crossbar interconnections, which provide a high level
of connectivity to existing control peripherals such as enhanced pulse width modulators (ePWM),
enhanced capture modules (eCAP), and enhanced quadrature encoder pulse modules (eQEP). The
crossbars also allow the CLB to be connected to external GPIO pins. In this way, the CLB can be
configured to interact with device peripherals to perform small logical functions such as comparators, or to
implement custom serial data exchange protocols. Through the CLB, functions that would otherwise be
accomplished using external logic devices can now be implemented inside the MCU.
The CLB peripheral is configured through the CLB tool. For more information on the CLB tool, available
examples, application reports and users guide, please refer to the following location in your C2000Ware
package (C2000Ware_2_00_00_03 and higher):
C2000WARE_INSTALL_LOCATION\utilities\clb_tool\clb_syscfg\doc
CLB Tool User Guide
How to Design with the C2000™ CLB Application Report
How to Migrate Custom Logic From an FPGA/CPLD to C2000™ CLB Application Report
The CLB module and its interconnections are shown in Figure 6-4.
Copyright © 2020, Texas Instruments Incorporated
Detailed Description
163
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Figure 6-4. CLB Overview
Absolute encoder protocol interfaces are now provided as Position Manager solutions in the C2000Ware
MotorControl SDK. Configuration files, application programmer interface (API), and use examples for such
solutions are provided with C2000Ware MotorControl SDK. In some solutions, the TI-configured CLB is
used with other on-chip resources, such as the SPI port or the C28x CPU, to perform more complex
functionality.
164
Detailed Description
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
7 Applications, Implementation, and Layout
NOTE
Information in the following Applications section is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI's customers are responsible for
determining suitability of components for their purposes. Customers should validate and test
their design implementation to confirm system functionality.
7.1 TI Reference Design
The TI Reference Design Library is a robust reference design library spanning analog, embedded
processor, and connectivity. Created by TI experts to help you jump start your system design, all
reference designs include schematic or block diagrams, BOMs, and design files to speed your time to
market. Search and download designs at Select TI reference designs.
Copyright © 2020, Texas Instruments Incorporated
Applications, Implementation, and Layout
165
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
8 Device and Documentation Support
8.1 Device and Development Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320 MCU devices and support tools. Each TMS320™ MCU commercial family member has one of
two prefixes: TMX or TMS (for example, TMS320F280025C). Texas Instruments recommends two of three
possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary
stages of product development from engineering prototypes (with TMX for devices and TMDX for tools)
through fully qualified production devices and tools (with TMS for devices and TMDS for tools).
TMX
TMS
Experimental device that is not necessarily representative of the final device's electrical
specifications
Fully qualified production device
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal
qualification testing
TMDS Fully qualified development-support product
TMX devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be
used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, PN) and temperature range (for example, S).
For device part numbers and further ordering information, see the TI website (www.ti.com) or contact your
TI sales representative.
166
Device and Documentation Support
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Generic Part Number: TMS 320
Orderable Part Number: (blank)
PREFIX(A)
F
280025C
R
X
F
280025C PN
S
SHIPPING OPTIONS
experimental device
TMX (X)
TMS (blank)
=
=
Tray
Tape and Reel
(blank)
R
=
=
qualified device
TEMPERATURE RANGE
−40°C to 125°C (TJ)
S
=
=
DEVICE FAMILY
Q
−40°C to 125°C (TA)
(Q refers to AEC Q100 qualification for automotive applications.)
320 = TMS320 MCU Family
TECHNOLOGY
PACKAGE TYPE
F = Flash
80-Pin PN Low-Profile Quad Flatpack (LQFP)
64-Pin PM LQFP
48-Pin PT LQFP
DEVICE
280025
280024
280023
280022
280021
280025C
280024C
280023C
A. Prefix X is used in orderable part numbers.
Figure 8-1. Device Nomenclature
8.2 Markings
Figure 8-2 and Figure 8-3 show the package symbolization. Table 8-1 lists the silicon revision codes.
X
X
F280025CPMS
$$#−YMLLLLS
G4
F280025CPNS
$$#−YMLLLLS
G4
Package
Pin 1
Package
Pin 1
YMLLLLS
Lot Trace Code
=
YM
LLLL
S
2-Digit Year/Month Code
Assembly Lot
Assembly Site Code
Wafer Fab Code (one or two characters) as applicable
Silicon Revision Code
=
=
=
=
=
$$
#
G4
Green (Low Halogen and RoHS-compliant)
=
Figure 8-2. Package Symbolization for PM and PN Packages
Copyright © 2020, Texas Instruments Incorporated
Device and Documentation Support
167
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
YMLLLLS
Lot Trace Code
=
YM
LLLL
S
980
$$
2-Digit Year/Month Code
Assembly Lot
Assembly Site Code
TI E.I.A. Code
Wafer Fab Code (one or two characters) as applicable
Silicon Revision Code
=
=
=
=
=
=
980
PTS
X
F280025C
YMLLLLS #
#
$$
G4
G4
Green (Low Halogen and RoHS-compliant)
=
Package
Pin 1
Figure 8-3. Package Symbolization for PT Package
Table 8-1. Revision Identification
REVID(1)
SILICON REVISION
SILICON REVISION CODE
COMMENTS
This silicon revision is available as TMX.
ADDRESS: 0x5D00C
Blank
0
0x0000 0000
(1) Silicon Revision ID
8.3 Tools and Software
TI offers an extensive line of development tools. Some of the tools and software to evaluate the
performance of the device, generate code, and develop solutions follow. To view all available tools and
software for C2000™ real-time control MCUs, visit the C2000 real-time control MCUs – Design &
development page.
Development Tools
F280025 controlCARD
The F280025 controlCARD is an HSEC180 controlCARD based evaluation and development tool for the
C2000™ F28002x series of microcontroller products. controlCARDs are ideal to use for initial evaluation
and system prototyping. controlCARDs are complete board-level modules that utilize one of two standard
form factors (100-pin DIMM or 180-pin HSEC ) to provide a low-profile single-board controller solution. For
first evaluation controlCARDs are typically purchased bundled with a baseboard or bundled in an
application kit.
Software Tools
C2000Ware for C2000 MCUs
C2000Ware for C2000™ microcontrollers is a cohesive set of development software and documentation
designed to minimize software development time. From device-specific drivers and libraries to device
peripheral examples, C2000Ware provides a solid foundation to begin development and evaluation of your
product.
Code Composer Studio™ (CCS) Integrated Development Environment (IDE) for C2000 microcontrollers
Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller
and Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop
and debug embedded applications. It includes an optimizing C/C++ compiler, source code editor, project
build environment, debugger, profiler, and many other features. The intuitive IDE provides a single user
interface taking the user through each step of the application development flow. Familiar tools and
interfaces allow users to get started faster than ever before. Code Composer Studio combines the
advantages of the Eclipse software framework with advanced embedded debug capabilities from TI
resulting in a compelling feature-rich development environment for embedded developers.
168
Device and Documentation Support
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
SysConfig Pin Mux Tool
The SysConfig Pin Mux Utility is a software tool which provides a Graphical User Interface for configuring
pin multiplexing settings, resolving conflicts and specifying I/O cell characteristics for TI MPUs. The
SysConfig Pin Mux tool is integrated inside Code Composer Studio (version 9.3 or higher) and
C2000Ware. Device and package specific examples are available in:
•
[C2000Ware 3_01_00_00 or Higher]\driverlib\f28002x\examples\pinmux
Models
Various models are available for download from the product Tools & Software pages. These models
include I/O Buffer Information Specification (IBIS) Models and Boundary-Scan Description Language
(BSDL) Models. To view all available models, visit the Models section of the Tools & Software page for
each device, which can be found in Table 8-2.
Training
To help assist design engineers in taking full advantage of the C2000 microcontroller features and
performance, TI has developed a variety of training resources. Utilizing the online training materials and
downloadable hands-on workshops provides an easy means for gaining a complete working knowledge of
the C2000 microcontroller family. These training resources have been designed to decrease the learning
curve, while reducing development time, and accelerating product time to market. For more information on
the various training resources, visit the C2000™ real-time control MCUs – Support & training site.
Specific TMS320F28004x hands-on training resources can be found at C2000™ MCU Device Workshops.
Technical Introduction to the New C2000 TMS320F28004x Device Family
Many of the peripherals and architecture of the F28002x are similar to the F28004x. This presentation will
cover the technical details of the TMS320F28004x architecture and highlight the new improvements to
various key peripherals which will be helpful to users of the F28002x device.
8.4 Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the
upper right corner, click on Alert me to register and receive a weekly digest of any product information that
has changed. For change details, review the revision history included in any revised document.
The current documentation that describes the processor, related peripherals, and other technical collateral
follows.
Errata
TMS320F28002x MCUs Silicon Errata describes known advisories on silicon and provides workarounds.
Technical Reference Manual
TMS320F28002x Microcontrollers Technical Reference Manual details the integration, the environment,
the functional description, and the programming models for each peripheral and subsystem in the
F28002x microcontrollers.
CPU User's Guides
TMS320C28x CPU and Instruction Set Reference Guide describes the central processing unit (CPU) and
the assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). This
Reference Guide also describes emulation features available on these DSPs.
TMS320C28x Extended Instruction Sets Technical Reference Manual describes the architecture, pipeline,
and instruction set of the TMU, VCU-II, and FPU accelerators.
Peripheral Guides
C2000 Real-Time Control Peripherals Reference Guide describes the peripheral reference guides of the
28x DSPs.
Copyright © 2020, Texas Instruments Incorporated
Device and Documentation Support
169
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
Tools Guides
TMS320C28x Assembly Language Tools v19.6.0.STS User's Guide describes the assembly language
tools (assembler and other tools used to develop assembly language code), assembler directives, macros,
common object file format, and symbolic debugging directives for the TMS320C28x device.
TMS320C28x Optimizing C/C++ Compiler v19.6.0.STS User's Guide describes the TMS320C28x C/C++
compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly
language source code for the TMS320C28x device.
Application Reports
The SMT & packaging application notes website lists documentation on TI’s surface mount technology
(SMT) and application notes on a variety of packaging-related topics.
Semiconductor Packing Methodology describes the packing methodologies employed to prepare
semiconductor devices for shipment to end users.
Calculating Useful Lifetimes of Embedded Processors provides a methodology for calculating the useful
lifetime of TI embedded processors (EPs) under power when used in electronic systems. It is aimed at
general engineers who wish to determine if the reliability of the TI EP meets the end system reliability
requirement.
An Introduction to IBIS (I/O Buffer Information Specification) Modeling discusses various aspects of IBIS
including its history, advantages, compatibility, model generation flow, data requirements in modeling the
input/output structures, and future trends.
Serial Flash Programming of C2000™ Microcontrollers discusses using a flash kernel and ROM loaders
for serial programming a device.
Fast Integer Division – A Differentiated Offering From C2000™ Product Family provides an overview of
the different division and modulo (remainder) functions and its associated properties.
8.5 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 8-2. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
ORDER NOW
TMS320F280025
TMS320F280025C
TMS320F280024
TMS320F280024C
TMS320F280023
TMS320F280023C
TMS320F280022
TMS320F280021
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
8.6 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help —
straight from the experts. Search existing answers or ask your own question to get the quick design help
you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications
and do not necessarily reflect TI's views; see TI's Terms of Use.
170
Device and Documentation Support
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
8.7 Trademarks
TMS320C2000, C2000, InstaSPIN-FOC, Code Composer Studio, TMS320, E2E are trademarks of Texas
Instruments.
Bosch is a registered trademark of Robert Bosch GmbH Corporation.
8.8 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.9 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
Copyright © 2020, Texas Instruments Incorporated
Device and Documentation Support
171
Submit Documentation Feedback
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
TMS320F280025, TMS320F280025C, TMS320F280024, TMS320F280024C
TMS320F280023, TMS320F280023C, TMS320F280022, TMS320F280021
SPRSP45 –MARCH 2020
www.ti.com
9 Mechanical, Packaging, and Orderable Information
9.1 Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the
most current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
To learn more about TI packaging, visit the Packaging information website.
172
Mechanical, Packaging, and Orderable Information
Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
Product Folder Links: TMS320F280025 TMS320F280025C TMS320F280024 TMS320F280024C TMS320F280023
TMS320F280023C TMS320F280022 TMS320F280021
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
F280021PTQR
F280021PTSR
F280023CPMSR
F280023CPNSR
F280023CPTSR
F280023PMQR
F280023PMSR
F280023PNQR
F280023PNSR
F280023PTQR
F280023PTSR
F280025CPMQR
F280025CPMS
F280025CPMSR
F280025CPNQR
F280025CPNSR
F280025CPTQR
F280025CPTSR
F280025PMQR
F280025PMS
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
ACTIVE
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
PT
PT
PM
PN
PT
PM
PM
PN
PN
PT
PT
PM
PM
PM
PN
PN
PT
PT
PM
PM
PM
PN
PN
PN
PT
PT
PT
PM
48
48
64
80
48
64
64
80
80
48
48
64
64
64
80
80
48
48
64
64
64
80
80
80
48
48
48
64
1000
1000
1000
1000
1000
900
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
1000
1000
1000
1000
1000
1000
900
1000
1000
1000
1000
1000
900
1600
1000
1000
1190
1000
1000
2500
1000
160
F280025PMSR
F280025PNQR
F280025PNS
F280025PNSR
F280025PTQR
F280025PTS
F280025PTSR
XF280025CPMS
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
XF280025CPNS
XF280025CPTS
ACTIVE
ACTIVE
LQFP
LQFP
PN
PT
80
48
119
250
TBD
TBD
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
PM0064A
LQFP - 1.6 mm max height
SCALE 1.400
PLASTIC QUAD FLATPACK
10.2
9.8
B
NOTE 3
64
49
PIN 1 ID
1
48
10.2
9.8
12.2
TYP
11.8
NOTE 3
33
16
32
17
A
0.27
0.17
64X
60X 0.5
4X 7.5
0.08
C A B
C
(0.13) TYP
SEATING PLANE
0.08
SEE DETAIL A
0.25
GAGE PLANE
(1.4)
1.6 MAX
0.05 MIN
0.75
0.45
0 -7
DETAIL
SCALE: 14
A
DETAIL A
TYPICAL
4215162/A 03/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MS-026.
www.ti.com
EXAMPLE BOARD LAYOUT
PM0064A
LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK
SYMM
49
64
64X (1.5)
1
48
64X (0.3)
SYMM
(11.4)
60X (0.5)
(R0.05) TYP
33
16
17
32
(11.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
0.05 MAX
ALL AROUND
EXPOSED METAL
METAL
0.05 MIN
ALL AROUND
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4215162/A 03/2017
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. For more information, see Texas Instruments literature number SLMA004 (www.ti.com/lit/slma004).
www.ti.com
EXAMPLE STENCIL DESIGN
PM0064A
LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK
SYMM
64
49
64X (1.5)
1
48
64X (0.3)
SYMM
(11.4)
60X (0.5)
(R0.05) TYP
16
33
17
32
(11.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:8X
4215162/A 03/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MTQF003A – OCTOBER 1994 – REVISED DECEMBER 1996
PT (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
M
0,08
0,50
36
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
6,80
Gage Plane
9,20
SQ
8,80
0,25
0,05 MIN
0°–7°
1,45
1,35
0,75
0,45
Seating Plane
0,10
1,60 MAX
4040052/C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
D. This may also be a thermally enhanced plastic package with leads conected to the die pads.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996
PN (S-PQFP-G80)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
60
M
0,08
41
61
40
0,13 NOM
80
21
1
20
Gage Plane
9,50 TYP
0,25
12,20
SQ
11,80
0,05 MIN
0°–7°
14,20
SQ
13,80
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040135 /B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明