F280049PZQR [TI]
具有 100MHz 频率、FPU、TMU、256KB 闪存、CLA、PGA、SDFM 的汽车类 C2000™ 32 位 MCU | PZ | 100 | -40 to 125;
| 型号： | F280049PZQR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 100MHz 频率、FPU、TMU、256KB 闪存、CLA、PGA、SDFM 的汽车类 C2000™ 32 位 MCU | PZ | 100 | -40 to 125 闪存 |
| 文件： | 总230页 (文件大小：6260K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
TMS320F28004x Microcontrollers
– Embedded Real-time Analysis and Diagnostic
(ERAD)
Communications peripherals
– One Power-Management Bus (PMBus)
interface
1 Features
•
TMS320C28x 32-bit CPU
•
– 100 MHz
– IEEE 754 single-precision Floating-Point Unit
(FPU)
– One Inter-integrated Circuit (I2C) interface
(pin-bootable)
– Trigonometric Math Unit (TMU)
•
3×-cycle to 4×-cycle improvement for
common trigonometric functions versus
software libraries
– Two Controller Area Network (CAN) bus ports
(pin-bootable)
– Two Serial Peripheral Interface (SPI) ports
(pin-bootable)
•
13-cycle Park transform
– Viterbi/Complex Math Unit (VCU-I)
– Ten hardware breakpoints (with ERAD)
Programmable Control Law Accelerator (CLA)
– 100 MHz
– IEEE 754 single-precision floating-point
instructions
– Two Serial Communication Interfaces (SCIs)
(pin-bootable)
– One Local Interconnect Network (LIN)
– One Fast Serial Interface (FSI) with a
transmitter and receiver
Analog system
– Three 3.45-MSPS, 12-bit Analog-to-Digital
Converters (ADCs)
•
•
•
– Executes code independently of main CPU
On-chip memory
•
•
Up to 21 external channels
Four integrated post-processing blocks
(PPBs) per ADC
– 256KB (128KW) of flash (ECC-protected)
across two independent banks
– 100KB (50KW) of RAM (ECC-protected or
parity-protected)
– Dual-zone security supporting third-party
development
– Seven windowed comparators (CMPSS) with
12-bit reference Digital-to-Analog Converters
(DACs)
•
Digital glitch filters
– Unique Identification (UID) number
Clock and system control
– Two 12-bit buffered DAC outputs
•
– Seven Programmable Gain Amplifiers (PGAs)
– Two internal zero-pin 10-MHz oscillators
– On-chip crystal oscillator and external clock
input
•
•
Programmable gain settings: 3, 6, 12, 24
Programmable output filtering
– Windowed watchdog timer module
– Missing clock detection circuitry
1.2-V core, 3.3-V I/O design
– Internal VREG or DC-DC for 1.2-V generation
allows for single-supply designs
– Brownout reset (BOR) circuit
System peripherals
•
Enhanced control peripherals
– 16 ePWM channels with high-resolution
capability (150-ps resolution)
•
•
•
Integrated dead-band support with high
resolution
•
Integrated hardware trip zones (TZs)
– Seven Enhanced Capture (eCAP) modules
•
High-resolution Capture (HRCAP) available
on two modules
– 6-channel Direct Memory Access (DMA)
controller
– Two Enhanced Quadrature Encoder Pulse
(eQEP) modules with support for CW/CCW
operation modes
– Four Sigma-Delta Filter Module (SDFM) input
channels (two parallel filters per channel)
– 40 individually programmable multiplexed
General-Purpose Input/Output (GPIO) pins
– 21 digital inputs on analog pins
– Enhanced Peripheral Interrupt Expansion
(ePIE) module
•
•
Standard SDFM data filtering
Comparator filter for fast action for
overvalue or undervalue condition
– Multiple low-power mode (LPM) support with
external wakeup
•
Configurable Logic Block (CLB)
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
– Augments existing peripheral capability
– Supports position manager solutions
•
•
InstaSPIN-FOC™
– Sensorless field-oriented control (FOC) with
FAST™ software encoder
– Library in on-chip ROM memory
Package options:
– 100-pin Low-profile Quad Flatpack (LQFP)
[PZ suffix]
– 64-pin LQFP [PM suffix]
– 56-pin Very Thin Quad Flatpack No-lead
(VQFN) [RSH suffix]
•
Temperature options:
– S: –40°C to 125°C junction
– Q: –40°C to 125°C free-air
(AEC Q100 qualification for automotive
applications)
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Medium/short range radar
Air conditioner outdoor unit
Door operator drive control
Automated sorting equipment
CNC control
Textile machine
Welding machine
AC charging (pile) station
DC charging (pile) station
EV charging station power module
Wireless vehicle charging module
Energy storage power conversion system (PCS)
Central inverter
Solar power optimizer
String inverter
DC/DC converter
Inverter & motor control
On-board (OBC) & wireless charger
AC drive control module
AC drive power stage module
Linear motor power stage
Servo drive control module
AC-input BLDC motor drive
DC-input BLDC motor drive
Industrial AC-DC
Three phase UPS
Merchant network & server PSU
Merchant telecom rectifiers
Copyright © 2021 Texas Instruments Incorporated
2
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
3 Description
C2000™ 32-bit microcontrollers are optimized for processing, sensing, and actuation to improve closed-loop
performance in real-time control applications such as industrial motor drives; solar inverters and digital power;
electrical vehicles and transportation; motor control; and sensing and signal processing.
The TMS320F28004x (F28004x) is a powerful 32-bit floating-point microcontroller unit (MCU) that lets designers
incorporate crucial control peripherals, differentiated analog, and nonvolatile memory on a single device.
The real-time control subsystem is based on TI’s 32-bit C28x CPU, which provides 100 MHz of signal processing
performance. The C28x CPU is further boosted by the new TMU extended instruction set, which enables fast
execution of algorithms with trigonometric operations commonly found in transforms and torque loop
calculations; and the VCU-I extended instruction set, which reduces the latency for complex math operations
commonly found in encoded applications.
The CLA allows significant offloading of common tasks from the main C28x CPU. The CLA is an independent
32-bit floating-point math accelerator that executes in parallel with the CPU. Additionally, the CLA has its own
dedicated memory resources and it can directly access the key peripherals that are required in a typical control
system. Support of a subset of ANSI C is standard, as are key features like hardware breakpoints and hardware
task-switching.
The F28004x supports up to 256KB (128KW) of flash memory divided into two 128KB (64KW) banks, which
enables programming and execution in parallel. Up to 100KB (50KW) of on-chip SRAM is also available in
blocks of 4KB (2KW) and 16KB (8KW) for efficient system partitioning. Flash ECC, SRAM ECC/parity, and dual-
zone security are also supported.
High-performance analog blocks are integrated on the F28004x MCU to further enable system consolidation.
Three separate 12-bit ADCs provide precise and efficient management of multiple analog signals, which
ultimately boosts system throughput. Seven PGAs on the analog front end enable on-chip voltage scaling before
conversion. Seven analog comparator modules provide continuous monitoring of input voltage levels for trip
conditions.
The TMS320C2000™ microcontrollers contain industry-leading control peripherals with frequency-independent
ePWM/HRPWM and eCAP allow for a best-in-class level of control to the system. The built-in 4-channel SDFM
allows for seamless integration of an oversampling sigma-delta modulator across an isolation barrier.
Connectivity is supported through various industry-standard communication ports (such as SPI, SCI, I2C, LIN,
and CAN) and offers multiple muxing options for optimal signal placement in a variety of applications. New to the
C2000 platform is the fully compliant PMBus. Additionally, in an industry first, the FSI enables high-speed, robust
communication to complement the rich set of peripherals that are embedded in the device.
A specially enabled device variant, TMS320F28004xC, allows access to the Configurable Logic Block (CLB) for
additional interfacing features and allows access to the secure ROM, which includes a library to enable
InstaSPIN-FOC™. See Device Comparison for more information.
The Embedded Real-Time Analysis and Diagnostic (ERAD) module enhances the debug and system analysis
capabilities of the device by providing additional hardware breakpoints and counters for profiling.
To learn more about the C2000 MCUs, visit the C2000 Overview at www.ti.com/c2000.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
Device Information (1)
PART NUMBER
TMS320F280049PZ
PACKAGE
LQFP (100)
LQFP (100)
LQFP (100)
LQFP (100)
LQFP (100)
LQFP (64)
LQFP (64)
LQFP (64)
LQFP (64)
LQFP (64)
LQFP (64)
LQFP (64)
LQFP (64)
LQFP (64)
VQFN (56)
VQFN (56)
VQFN (56)
VQFN (56)
VQFN (56)
BODY SIZE
14.0 mm × 14.0 mm
14.0 mm × 14.0 mm
14.0 mm × 14.0 mm
14.0 mm × 14.0 mm
14.0 mm × 14.0 mm
10.0 mm × 10.0 mm
10.0 mm × 10.0 mm
10.0 mm × 10.0 mm
10.0 mm × 10.0 mm
10.0 mm × 10.0 mm
10.0 mm × 10.0 mm
10.0 mm × 10.0 mm
10.0 mm × 10.0 mm
10.0 mm × 10.0 mm
7.0 mm × 7.0 mm
7.0 mm × 7.0 mm
7.0 mm × 7.0 mm
7.0 mm × 7.0 mm
7.0 mm × 7.0 mm
TMS320F280049CPZ
TMS320F280045PZ
TMS320F280041PZ
TMS320F280041CPZ
TMS320F280049PM
TMS320F280049CPM
TMS320F280048PM
TMS320F280048CPM
TMS320F280045PM
TMS320F280041PM
TMS320F280041CPM
TMS320F280040PM
TMS320F280040CPM
TMS320F280049RSH
TMS320F280049CRSH
TMS320F280045RSH
TMS320F280041RSH
TMS320F280041CRSH
(1) For more information on these devices, see Mechanical, Packaging, and Orderable Information.
Copyright © 2021 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
3.1 Functional Block Diagram
Functional Block Diagram shows the CPU system and associated peripherals.
Boot ROM
C28x CPU
CLA
(Type 2)
Secure ROM
FPU32
TMU
VCU-I
Flash Bank0
16 Sectors
64KW (128KB)
CLA to CPU MSG RAM
CPU to CLA MSG RAM
Flash Bank1
CPU Timers
16 Sectors
64KW (128KB)
DCSM
CLA Data ROM
ePIE
ERAD
CLA Program ROM
M0–M1 RAM
2KW (4KB)
LS0–LS7 RAM
16KW (32KB)
Crystal Oscillator
INTOSC1, INTOSC2
PLL
GS0–GS3 RAM
32KW (64KB)
DMA
6 Channels
PF1
PF3
PF4
PF2
PF7
PF8
PF9
Result
Data
40x GPIO
16x ePWM Chan.
(16 Hi-Res Capable)
1x LIN
2x CAN
2x SCI
1x I2C
1x PMBUS
2x SPI
7x CMPSS
3x 12-Bit ADC
7x eCAP
(2 HRCAP Capable)
2x Buffered DAC
7x PGA
Input XBAR
Output XBAR
ePWM XBAR
NMI
Watchdog
1x FSI RX
1x FSI TX
2x eQEP
(CW/CCW Support)
Windowed
Watchdog
4x SD Filters
Figure 3-1. Functional Block Diagram
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................2
3 Description.......................................................................3
3.1 Functional Block Diagram...........................................5
4 Revision History.............................................................. 6
5 Device Comparison.........................................................7
5.1 Related Products........................................................ 9
6 Terminal Configuration and Functions........................10
6.1 Pin Diagrams............................................................ 10
6.2 Pin Attributes.............................................................14
6.3 Signal Descriptions................................................... 27
6.4 Pin Multiplexing.........................................................39
6.5 Pins With Internal Pullup and Pulldown.................... 49
6.6 Connections for Unused Pins................................... 50
7 Specifications................................................................ 51
7.1 Absolute Maximum Ratings (1) (2) .............................51
7.2 ESD Ratings – Commercial...................................... 51
7.3 ESD Ratings – Automotive....................................... 51
7.4 Recommended Operating Conditions.......................52
7.5 Power Consumption Summary................................. 54
7.6 Electrical Characteristics...........................................60
7.7 Thermal Resistance Characteristics......................... 61
7.8 Thermal Design Considerations................................63
7.9 System......................................................................64
7.10 Analog Peripherals..................................................92
7.11 Control Peripherals............................................... 125
7.12 Communications Peripherals................................147
8 Detailed Description....................................................181
8.1 Overview.................................................................181
8.2 Functional Block Diagram.......................................182
8.3 Memory...................................................................183
8.4 Identification............................................................190
8.5 Bus Architecture – Peripheral Connectivity.............191
8.6 C28x Processor...................................................... 192
8.7 Control Law Accelerator (CLA)............................... 195
8.8 Direct Memory Access (DMA).................................197
8.9 Boot ROM and Peripheral Booting..........................198
8.10 Dual Code Security Module.................................. 203
8.11 Watchdog.............................................................. 204
8.12 Configurable Logic Block (CLB)............................205
9 Applications, Implementation, and Layout............... 207
9.1 TI Reference Design...............................................207
10 Device and Documentation Support........................208
10.1 Device and Development Support Tool
Nomenclature............................................................208
10.2 Markings............................................................... 209
10.3 Tools and Software............................................... 210
10.4 Documentation Support........................................ 212
10.5 Support Resources............................................... 213
10.6 Trademarks...........................................................213
10.7 Electrostatic Discharge Caution............................213
10.8 Glossary................................................................213
11 Mechanical, Packaging, and Orderable
Information.................................................................. 214
11.1 Packaging Information.......................................... 214
4 Revision History
Changes from April 29, 2020 to February 1, 2021 (from Revision E (April 2020) to Revision F
(February 2021))
Page
•
•
•
Added Q1 Part Numbers................................................................................................................................ 0
Table 5-1: Added Q1 Part Numbers....................................................................................................................7
Section 7.9.2.2.2 (Reset (XRSn) Switching Characteristics): Added tboot-flash..................................................68
Copyright © 2021 Texas Instruments Incorporated
6
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
5 Device Comparison
Table 5-1 lists the features of the TMS320F28004x devices.
Table 5-1. Device Comparison
F280049
F280049-Q1
F280049C
F280048
F280048-Q1
F280048C
F280041
F280041-Q1
F280041C
F280040
F280040-Q1
F280040C
FEATURE(1)
F280045
F280049C-Q1 F280048C-Q1
F280041C-Q1 F280040C-Q1
PROCESSOR AND ACCELERATORS
Frequency (MHz)
FPU
100
Yes
Yes
Yes
C28x
VCU-I
TMU – Type 0
Available
Yes
100
No
–
CLA – Type 2
Frequency (MHz)
6-Channel DMA – Type 0
Yes
MEMORY
Flash
RAM
256KB (128KW)
128KB (64KW)
Dedicated and Local Shared RAM
Global Shared RAM
36KB (18KW)
64KB (32KW)
100KB (50KW)
Yes
TOTAL RAM
Code security for on-chip flash, RAM, and OTP blocks
Boot ROM
Yes
User-configurable DCSM OTP
4KB (2KW)
SYSTEM (2)
4 tiles
(F280049C)
4 tiles
(F280048C)
4 tiles
(F280041C)
4 tiles
(F280040C)
Configurable Logic Block (CLB)
–
InstaSPIN-FOC™
F280049C
F280048C
–
3
F280041C
F280040C
32-bit CPU timers
Watchdog timers
1
Nonmaskable Interrupt Watchdog (NMIWD) timers
Crystal oscillator/External clock input
0-pin internal oscillator
100-pin PZ
1
1
2
40
26
25
–
24
–
40
26
25
21
14
12
5
40
26
25
–
24
–
GPIO pins
64-pin PM
56-pin RSH
100-pin PZ
64-pin PM
56-pin RSH
AIO inputs
External interrupts
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
Table 5-1. Device Comparison (continued)
F280049
F280049-Q1
F280049C
F280048
F280048-Q1
F280048C
F280041
F280041-Q1
F280041C
F280040
F280040-Q1
F280040C
FEATURE(1)
F280045
F280049C-Q1 F280048C-Q1
F280041C-Q1 F280040C-Q1
ANALOG PERIPHERALS
Number of ADCs
MSPS
Conversion Time (ns)(3)
3
3.45
290
21
14
12
1
ADC 12-bit
100-pin PZ
ADC channels
(single-ended)
64-pin PM
56-pin RSH
Temperature sensor
Buffered DAC
2
CMPSS
100-pin PZ
64-pin PM
56-pin RSH
100-pin PZ
64-pin PM
56-pin RSH
7
(each CMPSS has two
comparators and two internal
DACs)
6
5
7
PGAs
5
(Gain Settings: 3, 6, 12, 24)
4
CONTROL PERIPHERALS (4)
eCAP/HRCAP modules – Type 1
7 (2 with HRCAP capability)
ePWM/HRPWM channels – Type 4
100-pin PZ
16
2
eQEP modules – Type 1
SDFM channels – Type 1
64-pin PM
56-pin RSH
100-pin PZ
64-pin PM
56-pin RSH
1
1
4
3
3
COMMUNICATION PERIPHERALS (4)
CAN – Type 0
I2C – Type 1
SCI – Type 0
SPI – Type 2
LIN – Type 1
PMBus – Type 0
FSI – Type 0
2
1
2
2
1
1
1
PACKAGE OPTIONS, TEMPERATURE, AND QUALIFICATION
100-pin PZ
64-pin PM
56-pin RSH
100-pin PZ
–
100-pin PZ
64-pin PM
56-pin RSH
–
100-pin PZ
64-pin PM
56-pin RSH
100-pin PZ
–
Junction Temperature (TJ)
Free-Air Temperature (TA)
S: –40°C to 125°C
Q: –40°C to 125°C(5)
–
–
–
–
64-pin PM
64-pin PM
(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor
differences between devices that do not affect the basic functionality of the module. For more information, see the C2000 Real-Time
Control Peripherals Reference Guide.
(2) For more information about InstaSPIN-FOC™ devices, see Section 10.4 for a list of InstaSPIN Technical Reference Manuals.
(3) Time between start of sample-and-hold window to start of sample-and-hold window of the next conversion.
(4) For devices that are available in more than one package, the peripheral count listed in the smaller package is reduced because the
smaller package has less device pins available. The number of peripherals internally present on the device is not reduced compared to
the largest package offered within a part number. See Section 6 to identify which peripheral instances are accessible on pins in the
smaller package.
(5) The letter Q refers to AEC Q100 qualification for automotive applications.
Copyright © 2021 Texas Instruments Incorporated
8
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
5.1 Related Products
Original devices:
TMS320F2802x Microcontrollers
The F2802x series offers the lowest pin-count and Flash memory size options. InstaSPIN-FOC™ versions are
available.
TMS320F2803x Microcontrollers
The F2803x series increases the pin-count and memory size options. The F2803x series also introduces the
parallel control law accelerator (CLA) option.
TMS320F2805x Microcontrollers
The F2805x series is similar to the F2803x series but adds on-chip programmable gain amplifiers (PGAs).
InstaSPIN-FOC and InstaSPIN-MOTION™ versions are available.
TMS320F2806x Microcontrollers
The F2806x series is the first to include a floating-point unit (FPU). The F2806x series also increases the pin-
count, memory size options, and the quantity of peripherals. InstaSPIN-FOC™ and InstaSPIN-MOTION™
versions are available.
Newest devices:
TMS320F2807x Microcontrollers
The F2807x series offers the most performance, largest pin counts, flash memory sizes, and peripheral options.
The F2807x series includes the latest generation of accelerators, ePWM peripherals, and analog technology.
TMS320F28004x Microcontrollers
The F28004x series is a reduced version of the F2807x series with the latest generational enhancements. The
F28004x series is the best roadmap option for those using the F2806x series. InstaSPIN-FOC and configurable
logic block (CLB) versions are available.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
6 Terminal Configuration and Functions
6.1 Pin Diagrams
Figure 6-1 shows the pin assignments on the 100-pin PZ Low-Profile Quad Flatpack. Figure 6-2 shows the pin
assignments on the 64-Pin PM Low-Profile Quad Flatpack. Figure 6-3 shows the pin assignments on the 64-Pin
PM Low-Profile Quad Flatpack for the Q-temperature device. Figure 6-4 shows the pin assignments on the 56-
Pin RSH Very Thin Quad Flatpack No-Lead.
GPIO3
GPIO2
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
GPIO13
FLT1
GPIO1
FLT2
GPIO0
VDDIO
VDDIO_SW
GPIO23_VSW
VSS_SW
GPIO22_VFBSW
GPIO7
VDD
VSS
C14
PGA7_IN
PGA7_GND
GPIO40
VSS
B0
A10,B1,C10,PGA7_OF
VDD
B4,C8,PGA4_OF
VDDIO
A9
GPIO5
A8,PGA6_OF
GPIO9
A4,B8,PGA2_OF
GPIO39
GPIO59
GPIO10
GPIO34
GPIO15
GPIO14
GPIO6
A5
VDDA
VSSA
PGA2_GND,PGA4_GND,PGA6_GND
C3,PGA4_IN
PGA2_IN
C1
GPIO30
GPIO31
GPIO29
C5,PGA6_IN
VREFLOA
VREFLOB,VREFLOC
Not to scale
A. Only the GPIO function is shown on GPIO terminals. See Section 6.3 for the complete, muxed signal name.
Figure 6-1. 100-Pin PZ Low-Profile Quad Flatpack (Top View)
Copyright © 2021 Texas Instruments Incorporated
10
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
GPIO3
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
GPIO33
GPIO2
GPIO1
GPIO11
GPIO12
GPIO0
GPIO13
VDDIO_SW
GPIO23_VSW
VSS_SW
GPIO22_VFBSW
GPIO7
VDDIO
VDD
VSS
A10,B1,C10,PGA7_OF
B4,C8,PGA4_OF
A4,B8,PGA2_OF
VDDA
VSS
VDD
VDDIO
VSSA
GPIO5
PGA2_GND,PGA4_GND,PGA6_GND
C3,PGA4_IN
GPIO9
GPIO10
C1,PGA2_IN
GPIO6
VREFLOA,VREFLOB,VREFLOC
Not to scale
A. Only the GPIO function is shown on GPIO terminals. See Section 6.3 for the complete, muxed signal name.
Figure 6-2. F280049/C/M, F280045, F280041/C 64-Pin PM Low-Profile Quad Flatpack (Top View)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
GPIO3
GPIO2
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
GPIO33
GPIO11
FLT1
GPIO1
GPIO0
FLT2
VDDIO_SW
GPIO23_VSW
VSS_SW
GPIO22_VFBSW
GPIO7
VDDIO
VDD
VSS
A10,B1,C10,PGA7_OF
B4,C8,PGA4_OF
A4,B8,PGA2_OF
VDDA
VSS
VDD
VDDIO
VSSA
GPIO5
PGA2_GND,PGA4_GND,PGA6_GND
C3,PGA4_IN
GPIO9
GPIO10
C1,PGA2_IN
GPIO6
VREFLOA,VREFLOB,VREFLOC
Not to scale
A. Only the GPIO function is shown on GPIO terminals. See Section 6.3 for the complete, muxed signal name.
Figure 6-3. F280048/C, F280040/C 64-Pin PM Low-Profile Quad Flatpack — Q-Temperature (Top View)
Copyright © 2021 Texas Instruments Incorporated
12
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
GPIO4
43
44
45
46
47
48
49
50
51
52
53
54
55
56
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GPIO11
GPIO3
GPIO2
GPIO12
GPIO13
GPIO1
VDDIO
GPIO0
VDD
VDDIO_SW
GPIO23_VSW
VSS_SW
GPIO22_VFBSW
GPIO7
A10,B1,C10,PGA7_OF
B4,C8,PGA4_OF
A4,B8,PGA2_OF
VDDA
VSS
VSSA
VDD
PGA2_GND,PGA4_GND,PGA6_GND
C3,PGA4_IN
VDDIO
GPIO5
C1,PGA2_IN
GPIO9
VREFLOA,VREFLOB,VREFLOC
Not to scale
A. Only the GPIO function is shown on GPIO terminals. See Section 6.3 for the complete, muxed signal name.
B. This figure shows the top view of the 56-pin RSH package. The terminals are actually on the bottom side of the package. See Section 11
for the 56-pin RSH mechanical drawing.
Figure 6-4. 56-Pin RSH Very Thin Quad Flatpack No-Lead (Top View)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
6.2 Pin Attributes
Table 6-1. Pin Attributes
MUX
POSITION
64
PMQ
56
RSH
PIN
TYPE
SIGNAL NAME
100 PZ
64 PM
DESCRIPTION
ANALOG
A0
I
I
ADC-A Input 0
ADC-B Input 15
ADC-C Input 15
B15
C15
23
22
15
14
15
14
13
12
I
DACA_OUT
AIO231
A1
O
I
Buffered DAC-A Output
Digital Input-231 on ADC Pin
ADC-A Input 1
I
DACB_OUT
AIO232
A10
O
I
Buffered DAC-B Output
Digital Input-232 on ADC Pin
ADC-A Input 10
I
B1
I
ADC-B Input 1
C10
I
ADC-C Input 10
PGA7_OF
CMP7_HP0
CMP7_LP0
AIO230
A2
40
25
25
23
O
I
PGA-7 Output Filter (Optional)
CMPSS-7 High Comparator Positive Input 0
CMPSS-7 Low Comparator Positive Input 0
Digital Input-230 on ADC Pin
ADC-A Input 2
I
I
I
B6
I
ADC-B Input 6
PGA1_OF
CMP1_HP0
CMP1_LP0
AIO224
A3
O
I
PGA-1 Output Filter (Optional)
CMPSS-1 High Comparator Positive Input 0
CMPSS-1 Low Comparator Positive Input 0
Digital Input-224 on ADC Pin
ADC-A Input 3
9
9
9
8
I
I
I
CMP1_HP3
CMP1_HN0
CMP1_LP3
CMP1_LN0
AIO233
A4
I
CMPSS-1 High Comparator Positive Input 3
CMPSS-1 High Comparator Negative Input 0
CMPSS-1 Low Comparator Positive Input 3
CMPSS-1 Low Comparator Negative Input 0
Digital Input-233 on ADC Pin
ADC-A Input 4
I
10
36
35
I
I
I
I
B8
I
ADC-B Input 8
PGA2_OF
CMP2_HP0
CMP2_LP0
AIO225
A5
O
I
PGA-2 Output Filter (Optional)
CMPSS-2 High Comparator Positive Input 0
CMPSS-2 Low Comparator Positive Input 0
Digital Input-225 on ADC Pin
ADC-A Input 5
23
23
21
I
I
I
CMP2_HP3
CMP2_HN0
CMP2_LP3
CMP2_LN0
AIO234
I
CMPSS-2 High Comparator Positive Input 3
CMPSS-2 High Comparator Negative Input 0
CMPSS-2 Low Comparator Positive Input 3
CMPSS-2 Low Comparator Negative Input 0
Digital Input-234 on ADC Pin
I
I
I
I
Copyright © 2021 Texas Instruments Incorporated
14
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
Table 6-1. Pin Attributes (continued)
MUX
POSITION
64
PMQ
56
RSH
PIN
TYPE
SIGNAL NAME
100 PZ
64 PM
DESCRIPTION
A6
I
O
I
ADC-A Input 6
PGA5_OF
CMP5_HP0
CMP5_LP0
AIO228
PGA-5 Output Filter (Optional)
6
6
6
CMPSS-5 High Comparator Positive Input 0
CMPSS-5 Low Comparator Positive Input 0
Digital Input-228 on ADC Pin
I
I
A8
I
ADC-A Input 8
PGA6_OF
CMP6_HP0
CMP6_LP0
AIO229
O
I
PGA-6 Output Filter (Optional)
37
38
CMPSS-6 High Comparator Positive Input 0
CMPSS-6 Low Comparator Positive Input 0
Digital Input-229 on ADC Pin
I
I
A9
I
ADC-A Input 9
CMP6_HP3
CMP6_HN0
CMP6_LP3
CMP6_LN0
AIO236
I
CMPSS-6 High Comparator Positive Input 3
CMPSS-6 High Comparator Negative Input 0
CMPSS-6 Low Comparator Positive Input 3
CMPSS-6 Low Comparator Negative Input 0
Digital Input-236 on ADC Pin
I
I
I
I
B0
I
ADC-B Input 0
CMP7_HP3
CMP7_HN0
CMP7_LP3
CMP7_LN0
AIO241
I
CMPSS-7 High Comparator Positive Input 3
CMPSS-7 High Comparator Negative Input 0
CMPSS-7 Low Comparator Positive Input 3
CMPSS-7 Low Comparator Negative Input 0
Digital Input-241 on ADC Pin
I
41
I
I
I
B2
I
ADC-B Input 2
C6
I
ADC-C Input 6
PGA3_OF
CMP3_HP0
CMP3_LP0
AIO226
O
I
PGA-3 Output Filter (Optional)
7
7
7
6
CMPSS-3 High Comparator Positive Input 0
CMPSS-3 Low Comparator Positive Input 0
Digital Input-226 on ADC Pin
I
I
B3
I
ADC-B Input 3
Optional external reference voltage for on-chip DACs. There
is a 100-pF capacitor to VSSA on this pin whether used for
ADC input or DAC reference which cannot be disabled. If
this pin is being used as a reference for the on-chip DACs,
place at least a 1-µF capacitor on this pin.
VDAC
I
8
8
8
7
CMP3_HP3
CMP3_HN0
CMP3_LP3
CMP3_LN0
AIO242
I
I
CMPSS-3 High Comparator Positive Input 3
CMPSS-3 High Comparator Negative Input 0
CMPSS-3 Low Comparator Positive Input 3
CMPSS-3 Low Comparator Negative Input 0
Digital Input-242 on ADC Pin
I
I
I
B4
I
ADC-B Input 4
C8
I
ADC-C Input 8
PGA4_OF
CMP4_HP0
CMP4_LP0
AIO227
O
I
PGA-4 Output Filter (Optional)
39
24
24
22
CMPSS-4 High Comparator Positive Input 0
CMPSS-4 Low Comparator Positive Input 0
Digital Input-227 on ADC Pin
I
I
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
Table 6-1. Pin Attributes (continued)
MUX
POSITION
64
PMQ
56
RSH
PIN
TYPE
SIGNAL NAME
C0
100 PZ
64 PM
DESCRIPTION
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
ADC-C Input 0
CMP1_HP1
CMP1_HN1
CMP1_LP1
CMP1_LN1
AIO237
CMPSS-1 High Comparator Positive Input 1
CMPSS-1 High Comparator Negative Input 1
CMPSS-1 Low Comparator Positive Input 1
CMPSS-1 Low Comparator Negative Input 1
Digital Input-237 on ADC Pin
19
12
12
10
C1
ADC-C Input 1
CMP2_HP1
CMP2_HN1
CMP2_LP1
CMP2_LN1
AIO238
CMPSS-2 High Comparator Positive Input 1
CMPSS-2 High Comparator Negative Input 1
CMPSS-2 Low Comparator Positive Input 1
CMPSS-2 Low Comparator Negative Input 1
Digital Input-238 on ADC Pin
29
44
21
31
17
28
18
18
16
C14
ADC-C Input 14
CMP7_HP1
CMP7_HN1
CMP7_LP1
CMP7_LN1
AIO246
CMPSS-7 High Comparator Positive Input 1
CMPSS-7 High Comparator Negative Input 1
CMPSS-7 Low Comparator Positive Input 1
CMPSS-7 Low Comparator Negative Input 1
Digital Input-246 on ADC Pin
C2
ADC-C Input 2
CMP3_HP1
CMP3_HN1
CMP3_LP1
CMP3_LN1
AIO244
CMPSS-3 High Comparator Positive Input 1
CMPSS-3 High Comparator Negative Input 1
CMPSS-3 Low Comparator Positive Input 1
CMPSS-3 Low Comparator Negative Input 1
Digital Input-244 on ADC Pin
13
19
11
13
19
11
11
C3
ADC-C Input 3
CMP4_HP1
CMP4_HN1
CMP4_LP1
CMP4_LN1
AIO245
CMPSS-4 High Comparator Positive Input 1
CMPSS-4 High Comparator Negative Input 1
CMPSS-4 Low Comparator Positive Input 1
CMPSS-4 Low Comparator Negative Input 1
Digital Input-245 on ADC Pin
17
C4
ADC-C Input 4
CMP5_HP1
CMP5_HN1
CMP5_LP1
CMP5_LN1
AIO239
CMPSS-5 High Comparator Positive Input 1
CMPSS-5 High Comparator Negative Input 1
CMPSS-5 Low Comparator Positive Input 1
CMPSS-5 Low Comparator Negative Input 1
Digital Input-239 on ADC Pin
C5
ADC-C Input 5
CMP6_HP1
CMP6_HN1
CMP6_LP1
CMP6_LN1
AIO240
CMPSS-6 High Comparator Positive Input 1
CMPSS-6 High Comparator Negative Input 1
CMPSS-6 Low Comparator Positive Input 1
CMPSS-6 Low Comparator Negative Input 1
Digital Input-240 on ADC Pin
PGA1_GND
PGA1_IN
CMP1_HP2
CMP1_LP2
14
18
10
12
10
12
9
PGA-1 Ground
PGA-1 Input
10
CMPSS-1 High Comparator Positive Input 2
CMPSS-1 Low Comparator Positive Input 2
Copyright © 2021 Texas Instruments Incorporated
16
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
Table 6-1. Pin Attributes (continued)
MUX
POSITION
64
PMQ
56
RSH
PIN
TYPE
SIGNAL NAME
100 PZ
64 PM
DESCRIPTION
PGA2_GND
PGA2_IN
32
20
18
10
13
20
19
10
11
20
20
18
16
9
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
PGA-2 Ground
PGA-2 Input
CMP2_HP2
CMP2_LP2
PGA3_GND
PGA3_IN
30
15
20
32
31
13
16
32
28
42
43
18
10
13
20
19
10
11
20
CMPSS-2 High Comparator Positive Input 2
CMPSS-2 Low Comparator Positive Input 2
PGA-3 Ground
PGA-3 Input
CMP3_HP2
CMP3_LP2
PGA4_GND
PGA4_IN
11
18
17
9
CMPSS-3 High Comparator Positive Input 2
CMPSS-3 Low Comparator Positive Input 2
PGA-4 Ground
PGA-4 Input
CMP4_HP2
CMP4_LP2
PGA5_GND
PGA5_IN
CMPSS-4 High Comparator Positive Input 2
CMPSS-4 Low Comparator Positive Input 2
PGA-5 Ground
PGA-5 Input
CMP5_HP2
CMP5_LP2
PGA6_GND
PGA6_IN
CMPSS-5 High Comparator Positive Input 2
CMPSS-5 Low Comparator Positive Input 2
PGA-6 Ground
18
PGA-6 Input
CMP6_HP2
CMP6_LP2
PGA7_GND
PGA7_IN
CMPSS-6 High Comparator Positive Input 2
CMPSS-6 Low Comparator Positive Input 2
PGA-7 Ground
PGA-7 Input
CMP7_HP2
CMP7_LP2
CMPSS-7 High Comparator Positive Input 2
CMPSS-7 Low Comparator Positive Input 2
ADC-A High Reference. In external reference mode,
externally drive the high reference voltage onto this pin. In
internal reference mode, a voltage is driven onto this pin by
the device. In either mode, place at least a 2.2-µF capacitor
on this pin. This capacitor should be placed as close to the
device as possible between the VREFHIA and VREFLOA
pins. Do not load this pin externally in either internal or
external reference mode.
VREFHIA
VREFHIB
VREFHIC
25
24
24
16
16
16
16
16
16
14
14
14
I/O
I/O
I/O
ADC-B High Reference. In external reference mode,
externally drive the high reference voltage onto this pin. In
internal reference mode, a voltage is driven onto this pin by
the device. In either mode, place at least a 2.2-µF capacitor
on this pin. This capacitor should be placed as close to the
device as possible between the VREFHIB and VREFLOB
pins. Do not load this pin externally in either internal or
external reference mode.
ADC-C High Reference. In external reference mode,
externally drive the high reference voltage onto this pin. In
internal reference mode, a voltage is driven onto this pin by
the device. In either mode, place at least a 2.2-µF capacitor
on this pin. This capacitor should be placed as close to the
device as possible between the VREFHIC and VREFLOC
pins. Do not load this pin externally in either internal or
external reference mode.
VREFLOA
VREFLOB
VREFLOC
27
26
26
17
17
17
17
17
17
15
15
15
I
I
I
ADC-A Low Reference
ADC-B Low Reference
ADC-C Low Reference
GPIO
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
Table 6-1. Pin Attributes (continued)
MUX
POSITION
64
PMQ
56
RSH
PIN
TYPE
SIGNAL NAME
GPIO0
100 PZ
64 PM
DESCRIPTION
0, 4, 8, 12
I/O
O
General-Purpose Input Output 0
ePWM-1 Output A
EPWM1_A
I2CA_SDA
GPIO1
1
79
52
51
52
47
46
6
I/OD I2C-A Open-Drain Bidirectional Data
0, 4, 8, 12
I/O
O
General-Purpose Input Output 1
ePWM-1 Output B
EPWM1_B
I2CA_SCL
GPIO2
1
78
77
51
50
6
I/OD I2C-A Open-Drain Bidirectional Clock
0, 4, 8, 12
I/O
O
General-Purpose Input Output 2
ePWM-2 Output A
EPWM2_A
OUTPUTXBAR1
PMBUSA_SDA
SCIA_TX
1
5
O
Output X-BAR Output 1
50
45
6
I/OD PMBus-A Open-Drain Bidirectional Data
9
O
I
SCI-A Transmit Data
FSIRXA_D1
GPIO3
10
FSIRX-A Optional Additional Data Input
General-Purpose Input Output 3
ePWM-2 Output B
0, 4, 8, 12
I/O
O
O
EPWM2_B
OUTPUTXBAR2
PMBUSA_SCL
SPIA_CLK
SCIA_RX
1
2, 5
Output X-BAR Output 2
6
76
49
49
44
I/OD PMBus-A Open-Drain Bidirectional Clock
7
I/O
I
SPI-A Clock
9
SCI-A Receive Data
FSIRXA_D0
GPIO4
10
I
FSIRX-A Primary Data Input
General-Purpose Input Output 4
ePWM-3 Output A
0, 4, 8, 12
I/O
O
O
O
I
EPWM3_A
OUTPUTXBAR3
CANA_TX
FSIRXA_CLK
GPIO5
1
5
75
89
48
61
48
61
43
55
Output X-BAR Output 3
CAN-A Transmit
6
10
FSIRX-A Input Clock
0, 4, 8, 12
I/O
O
O
I
General-Purpose Input Output 5
ePWM-3 Output B
EPWM3_B
OUTPUTXBAR3
CANA_RX
SPIA_STE
FSITXA_D1
GPIO6
1
3
Output X-BAR Output 3
CAN-A Receive
6
7
I/O
O
I/O
O
O
O
I
SPI-A Slave Transmit Enable (STE)
FSITX-A Optional Additional Data Output
General-Purpose Input Output 6
ePWM-4 Output A
9
0, 4, 8, 12
EPWM4_A
OUTPUTXBAR4
SYNCOUT
EQEP1_A
1
2
Output X-BAR Output 4
External ePWM Synchronization Pulse
eQEP-1 Input A
3
97
64
64
1
5
CANB_TX
SPIB_SOMI
FSITXA_D0
GPIO7
6
O
I/O
O
I/O
O
O
I
CAN-B Transmit
7
SPI-B Slave Out, Master In (SOMI)
FSITX-A Primary Data Output
General-Purpose Input Output 7
ePWM-4 Output B
9
0, 4, 8, 12
EPWM4_B
OUTPUTXBAR5
EQEP1_B
1
3
5
6
7
9
Output X-BAR Output 5
eQEP-1 Input B
84
57
57
52
CANB_RX
SPIB_SIMO
FSITXA_CLK
I
CAN-B Receive
I/O
O
SPI-B Slave In, Master Out (SIMO)
FSITX-A Output Clock
Copyright © 2021 Texas Instruments Incorporated
18
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
Table 6-1. Pin Attributes (continued)
MUX
POSITION
64
PMQ
56
RSH
PIN
TYPE
SIGNAL NAME
100 PZ
64 PM
DESCRIPTION
GPIO8
0, 4, 8, 12
I/O
O
General-Purpose Input Output 8
EPWM5_A
CANB_TX
1
2
ePWM-5 Output A
CAN-B Transmit
O
ADC Start of Conversion A Output for External ADC (from
ePWM modules)
ADCSOCAO
3
O
74
47
47
42
EQEP1_STROBE
SCIA_TX
5
I/O
O
eQEP-1 Strobe
6
SCI-A Transmit Data
SPIA_SIMO
I2CA_SCL
FSITXA_D1
GPIO9
7
I/O
SPI-A Slave In, Master Out (SIMO)
9
I/OD I2C-A Open-Drain Bidirectional Clock
10
O
I/O
O
FSITX-A Optional Additional Data Output
General-Purpose Input Output 9
ePWM-5 Output B
0, 4, 8, 12
EPWM5_B
SCIB_TX
1
2
O
SCI-B Transmit Data
OUTPUTXBAR6
EQEP1_INDEX
SCIA_RX
3
O
Output X-BAR Output 6
eQEP-1 Index
90
62
62
56
5
I/O
I
6
SCI-A Receive Data
SPIA_CLK
FSITXA_D0
GPIO10
7
I/O
O
SPI-A Clock
10
FSITX-A Primary Data Output
General-Purpose Input Output 10
ePWM-6 Output A
0, 4, 8, 12
I/O
O
EPWM6_A
CANB_RX
1
2
I
CAN-B Receive
ADC Start of Conversion B Output for External ADC (from
ePWM modules)
ADCSOCBO
3
O
93
63
63
EQEP1_A
5
I
eQEP-1 Input A
SCIB_TX
6
O
SCI-B Transmit Data
SPIA_SOMI
I2CA_SDA
FSITXA_CLK
GPIO11
7
I/O
SPI-A Slave Out, Master In (SOMI)
9
I/OD I2C-A Open-Drain Bidirectional Data
10
O
I/O
O
I
FSITX-A Output Clock
General-Purpose Input Output 11
ePWM-6 Output B
0, 4, 8, 12
EPWM6_B
SCIB_RX
1
2, 6
SCI-B Receive Data
OUTPUTXBAR7
EQEP1_B
3
52
31
31
28
O
I
Output X-BAR Output 7
eQEP-1 Input B
5
SPIA_STE
FSIRXA_D1
GPIO12
7
I/O
I
SPI-A Slave Transmit Enable (STE)
FSIRX-A Optional Additional Data Input
General-Purpose Input Output 12
ePWM-7 Output A
9
0, 4, 8, 12
I/O
O
O
I/O
O
I
EPWM7_A
CANB_TX
1
2
5
6
7
9
CAN-B Transmit
EQEP1_STROBE
SCIB_TX
51
30
27
eQEP-1 Strobe
SCI-B Transmit Data
PMBUSA_CTL
FSIRXA_D0
PMBus-A Control Signal
FSIRX-A Primary Data Input
I
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
19
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
Table 6-1. Pin Attributes (continued)
MUX
POSITION
64
PMQ
56
RSH
PIN
TYPE
SIGNAL NAME
GPIO13
100 PZ
64 PM
DESCRIPTION
0, 4, 8, 12
I/O
O
I
General-Purpose Input Output 13
EPWM7_B
CANB_RX
1
ePWM-7 Output B
CAN-B Receive
eQEP-1 Index
2
EQEP1_INDEX
SCIB_RX
5
50
29
26
I/O
I
6
SCI-B Receive Data
PMBUSA_ALERT
FSIRXA_CLK
GPIO14
7
I/OD PMBus-A Open-Drain Bidirectional Alert Signal
9
I
FSIRX-A Input Clock
0, 4, 8, 12
I/O
O
General-Purpose Input Output 14
ePWM-8 Output A
EPWM8_A
SCIB_TX
1
2
O
SCI-B Transmit Data
OUTPUTXBAR3
PMBUSA_SDA
SPIB_CLK
6
96
O
Output X-BAR Output 3
7
I/OD PMBus-A Open-Drain Bidirectional Data
9
I/O
I
SPI-B Clock
EQEP2_A
10
eQEP-2 Input A
GPIO15
0, 4, 8, 12
I/O
O
I
General-Purpose Input Output 15
ePWM-8 Output B
EPWM8_B
SCIB_RX
1
2
SCI-B Receive Data
Output X-BAR Output 4
OUTPUTXBAR4
PMBUSA_SCL
SPIB_STE
6
95
O
7
I/OD PMBus-A Open-Drain Bidirectional Clock
9
I/O
I
SPI-B Slave Transmit Enable (STE)
eQEP-2 Input B
EQEP2_B
10
GPIO16
0, 4, 8, 12
I/O
I/O
O
General-Purpose Input Output 16
SPI-A Slave In, Master Out (SIMO)
CAN-B Transmit
SPIA_SIMO
CANB_TX
1
2
OUTPUTXBAR7
EPWM5_A
SCIA_TX
3
O
Output X-BAR Output 7
ePWM-5 Output A
5
O
54
33
33
30
6
O
SCI-A Transmit Data
SD1_D1
7
I
SDFM-1 Channel 1 Data Input
eQEP-1 Strobe
EQEP1_STROBE
PMBUSA_SCL
9
I/O
10
I/OD PMBus-A Open-Drain Bidirectional Clock
External Clock Output. This pin outputs a divided-down
version of a chosen clock signal from within the device.
XCLKOUT
11
O
GPIO17
0, 4, 8, 12
I/O
I/O
I
General-Purpose Input Output 17
SPI-A Slave Out, Master In (SOMI)
CAN-B Receive
SPIA_SOMI
CANB_RX
1
2
OUTPUTXBAR8
EPWM5_B
SCIA_RX
3
O
O
I
Output X-BAR Output 8
ePWM-5 Output B
5
55
34
34
31
6
SCI-A Receive Data
SD1_C1
7
I
SDFM-1 Channel 1 Clock Input
eQEP-1 Index
EQEP1_INDEX
PMBUSA_SDA
9
I/O
10
I/OD PMBus-A Open-Drain Bidirectional Data
Copyright © 2021 Texas Instruments Incorporated
20
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
Table 6-1. Pin Attributes (continued)
MUX
POSITION
64
PMQ
56
RSH
PIN
TYPE
SIGNAL NAME
100 PZ
64 PM
DESCRIPTION
General-Purpose Input Output 18. This pin and its digital
mux options can only be used when the system is clocked
by INTOSC and X1 has an external pulldown resistor
(recommended 1 kΩ).
GPIO18_X2
0, 4, 8, 12
I/O
SPIA_CLK
SCIB_TX
1
2
I/O
O
I
SPI-A Clock
SCI-B Transmit Data
CAN-A Receive
ePWM-6 Output A
CANA_RX
EPWM6_A
I2CA_SCL
SD1_D2
3
5
O
68
41
41
38
6
I/OD I2C-A Open-Drain Bidirectional Clock
7
I
I
I
SDFM-1 Channel 2 Data Input
eQEP-2 Input A
EQEP2_A
PMBUSA_CTL
9
10
PMBus-A Control Signal
External Clock Output. This pin outputs a divided-down
version of a chosen clock signal from within the device.
XCLKOUT
11
O
X2
ALT
0
I/O
I/O
I/O
Crystal oscillator output
GPIO20
GPIO21
General-Purpose Input Output 20
General-Purpose Input Output 21
0
General-Purpose Input Output 22. This pin is configured for
DC-DC mode by default. If the internal DC-DC regulator is
not used, this can be configured as General-Purpose Input
Output 22 by disabling DC-DC and clearing their bits in
GPAAMSEL register.
GPIO22_VFBSW
0, 4, 8, 12
I/O
EQEP1_STROBE
SCIB_TX
1
3
6
7
9
I/O
O
eQEP-1 Strobe
SCI-B Transmit Data
SPI-B Clock
83
56
56
51
SPIB_CLK
SD1_D4
I/O
I
SDFM-1 Channel 4 Data Input
LIN-A Transmit
LINA_TX
O
Internal DC-DC regulator feedback signal. If the internal DC-
DC regulator is used, tie this pin to the node where L(VSW)
connects to the VDD rail (as close as possible to the
device).
VFBSW
ALT
-
General-Purpose Input Output 23. This pin is configured for
DC-DC mode by default. If the internal DC-DC regulator is
not used, this can be configured as General-Purpose Input
Output 23 by disabling DC-DC and clearing their bits in
GPAAMSEL register. This pin has an internal capacitance of
approximately 100 pF. TI Recommends using an alternate
GPIO, or using this pin only for applications which do not
require a fast switching response.
GPIO23_VSW
0
I/O
81
54
54
49
VSW
ALT
-
I/O
O
I
Switching output of the internal DC-DC regulator
General-Purpose Input Output 24
Output X-BAR Output 1
GPIO24
0, 4, 8, 12
OUTPUTXBAR1
EQEP2_A
EPWM8_A
SPIB_SIMO
SD1_D1
1
2
eQEP-2 Input A
5
O
I/O
I
ePWM-8 Output A
6
56
35
35
32
SPI-B Slave In, Master Out (SIMO)
SDFM-1 Channel 1 Data Input
7
PMBUSA_SCL
SCIA_TX
10
11
13
I/OD PMBus-A Open-Drain Bidirectional Clock
O
O
SCI-A Transmit Data
ERRORSTS
Error Status Output. This signal requires an external pullup.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
Table 6-1. Pin Attributes (continued)
MUX
POSITION
64
PMQ
56
RSH
PIN
TYPE
SIGNAL NAME
GPIO25
100 PZ
64 PM
DESCRIPTION
0, 4, 8, 12
I/O
O
I
General-Purpose Input Output 25
OUTPUTXBAR2
EQEP2_B
1
Output X-BAR Output 2
2
eQEP-2 Input B
SPIB_SOMI
SD1_C1
6
I/O
I
SPI-B Slave Out, Master In (SOMI)
SDFM-1 Channel 1 Clock Input
FSITX-A Optional Additional Data Output
57
7
FSITXA_D1
PMBUSA_SDA
SCIA_RX
9
O
10
I/OD PMBus-A Open-Drain Bidirectional Data
11
I
I/O
O
SCI-A Receive Data
GPIO26
0, 4, 8, 12
General-Purpose Input Output 26
Output X-BAR Output 3
eQEP-2 Index
OUTPUTXBAR3
EQEP2_INDEX
SPIB_CLK
1, 5
2
I/O
I/O
I
6
SPI-B Clock
58
SD1_D2
7
SDFM-1 Channel 2 Data Input
FSITX-A Primary Data Output
PMBus-A Control Signal
FSITXA_D0
PMBUSA_CTL
I2CA_SDA
GPIO27
9
O
10
I
11
I/OD I2C-A Open-Drain Bidirectional Data
0, 4, 8, 12
I/O
O
General-Purpose Input Output 27
Output X-BAR Output 4
OUTPUTXBAR4
EQEP2_STROBE
SPIB_STE
1, 5
2
I/O
I/O
I
eQEP-2 Strobe
6
SPI-B Slave Transmit Enable (STE)
SDFM-1 Channel 2 Clock Input
FSITX-A Output Clock
59
SD1_C2
7
FSITXA_CLK
PMBUSA_ALERT
I2CA_SCL
9
O
10
I/OD PMBus-A Open-Drain Bidirectional Alert Signal
I/OD I2C-A Open-Drain Bidirectional Clock
11
GPIO28
0, 4, 8, 12
I/O
I
General-Purpose Input Output 28
SCI-A Receive Data
ePWM-7 Output A
SCIA_RX
1
EPWM7_A
OUTPUTXBAR5
EQEP1_A
3
O
O
I
5
Output X-BAR Output 5
eQEP-1 Input A
6
1
2
2
3
SD1_D3
7
I
SDFM-1 Channel 3 Data Input
eQEP-2 Strobe
EQEP2_STROBE
LINA_TX
9
I/O
O
I/O
O
I/O
O
O
O
I
10
LIN-A Transmit
SPIB_CLK
11
SPI-B Clock
ERRORSTS
GPIO29
13
Error Status Output. This signal requires an external pullup.
General-Purpose Input Output 29
SCI-A Transmit Data
0, 4, 8, 12
SCIA_TX
1
3
EPWM7_B
OUTPUTXBAR6
EQEP1_B
ePWM-7 Output B
5
Output X-BAR Output 6
6
eQEP-1 Input B
100
1
1
2
SD1_C3
7
I
SDFM-1 Channel 3 Clock Input
eQEP-2 Index
EQEP2_INDEX
LINA_RX
9
I/O
I
10
11
13
LIN-A Receive
SPIB_STE
I/O
O
SPI-B Slave Transmit Enable (STE)
Error Status Output. This signal requires an external pullup.
ERRORSTS
Copyright © 2021 Texas Instruments Incorporated
22
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
Table 6-1. Pin Attributes (continued)
MUX
POSITION
64
PMQ
56
RSH
PIN
TYPE
SIGNAL NAME
100 PZ
64 PM
DESCRIPTION
GPIO30
0, 4, 8, 12
I/O
I
General-Purpose Input Output 30
CANA_RX
SPIB_SIMO
OUTPUTXBAR7
EQEP1_STROBE
SD1_D4
1
CAN-A Receive
3
I/O
O
SPI-B Slave In, Master Out (SIMO)
Output X-BAR Output 7
98
5
6
I/O
I
eQEP-1 Strobe
7
SDFM-1 Channel 4 Data Input
General-Purpose Input Output 31
CAN-A Transmit
GPIO31
0, 4, 8, 12
I/O
O
CANA_TX
SPIB_SOMI
OUTPUTXBAR8
EQEP1_INDEX
SD1_C4
1
3
I/O
O
SPI-B Slave Out, Master In (SOMI)
Output X-BAR Output 8
5
99
6
I/O
I
eQEP-1 Index
7
SDFM-1 Channel 4 Clock Input
FSIRX-A Optional Additional Data Input
General-Purpose Input Output 32
FSIRXA_D1
GPIO32
9
I
0, 4, 8, 12
I/O
I2CA_SDA
SPIB_CLK
EPWM8_B
LINA_TX
1
I/OD I2C-A Open-Drain Bidirectional Data
3
I/O
O
O
I
SPI-B Clock
5
ePWM-8 Output B
64
40
40
37
6
LIN-A Transmit
SD1_D3
7
SDFM-1 Channel 3 Data Input
FSIRX-A Primary Data Input
CAN-A Transmit
FSIRXA_D0
CANA_TX
GPIO33
9
I
10
O
I/O
0, 4, 8, 12
General-Purpose Input Output 33
I2CA_SCL
SPIB_STE
OUTPUTXBAR4
LINA_RX
1
I/OD I2C-A Open-Drain Bidirectional Clock
3
I/O
SPI-B Slave Transmit Enable (STE)
Output X-BAR Output 4
LIN-A Receive
5
O
53
94
32
32
29
6
I
I
SD1_C3
7
SDFM-1 Channel 3 Clock Input
FSIRX-A Input Clock
FSIRXA_CLK
CANA_RX
GPIO34
9
I
10
I
CAN-A Receive
0, 4, 8, 12
I/O
O
General-Purpose Input Output 34
Output X-BAR Output 1
OUTPUTXBAR1
PMBUSA_SDA
GPIO35
1
6
I/OD PMBus-A Open-Drain Bidirectional Data
0, 4, 8, 12
I/O
I
General-Purpose Input Output 35
SCI-A Receive Data
SCIA_RX
1
3
I2CA_SDA
CANA_RX
PMBUSA_SCL
LINA_RX
I/OD I2C-A Open-Drain Bidirectional Data
CAN-A Receive
I/OD PMBus-A Open-Drain Bidirectional Clock
5
I
6
7
I
I
I
LIN-A Receive
63
39
39
36
EQEP1_A
9
eQEP-1 Input A
PMBUSA_CTL
10
PMBus-A Control Signal
JTAG Test Data Input (TDI) - TDI is the default mux
selection for the pin. The internal pullup is disabled by
default. The internal pullup should be enabled or an external
pullup added on the board if this pin is used as JTAG TDI to
avoid a floating input.
TDI
15
I
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
23
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
Table 6-1. Pin Attributes (continued)
MUX
POSITION
64
PMQ
56
RSH
PIN
TYPE
SIGNAL NAME
GPIO37
100 PZ
64 PM
DESCRIPTION
0, 4, 8, 12
I/O
O
General-Purpose Input Output 37
Output X-BAR Output 2
OUTPUTXBAR2
I2CA_SCL
1
3
I/OD I2C-A Open-Drain Bidirectional Clock
SCIA_TX
5
O
O
O
I
SCI-A Transmit Data
CAN-A Transmit
LIN-A Transmit
CANA_TX
6
LINA_TX
7
61
37
37
34
EQEP1_B
9
eQEP-1 Input B
PMBUSA_ALERT
10
I/OD PMBus-A Open-Drain Bidirectional Alert Signal
JTAG Test Data Output (TDO) - TDO is the default mux
selection for the pin. The internal pullup is disabled by
default. The TDO function will be in a tri-state condition
when there is no JTAG activity, leaving this pin floating; the
internal pullup should be enabled or an external pullup
added on the board to avoid a floating GPIO input.
TDO
15
O
GPIO39
0, 4, 8, 12
I/O
General-Purpose Input Output 39
CAN-B Receive
CANB_RX
FSIRXA_CLK
GPIO40
6
91
85
I
I
7
FSIRX-A Input Clock
0, 4, 8, 12
I/O
General-Purpose Input Output 40
PMBUSA_SDA
FSIRXA_D0
SCIB_TX
EQEP1_A
GPIO41
6
I/OD PMBus-A Open-Drain Bidirectional Data
7
I
FSIRX-A Primary Data Input
SCI-B Transmit Data
9
O
10
I
eQEP-1 Input A
0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
General-Purpose Input Output 41
General-Purpose Input Output 42
General-Purpose Input Output 43
General-Purpose Input Output 44
General-Purpose Input Output 45
General-Purpose Input Output 46
General-Purpose Input Output 47
General-Purpose Input Output 48
General-Purpose Input Output 49
General-Purpose Input Output 50
General-Purpose Input Output 51
General-Purpose Input Output 52
General-Purpose Input Output 53
General-Purpose Input Output 54
General-Purpose Input Output 55
General-Purpose Input Output 56
SPI-A Clock
GPIO42
0
GPIO43
0
GPIO44
0
GPIO45
0
GPIO46
0
GPIO47
0
GPIO48
0
GPIO49
0
GPIO50
0
GPIO51
0
GPIO52
0
GPIO53
0
GPIO54
0
GPIO55
0
GPIO56
0, 4, 8, 12
SPIA_CLK
EQEP2_STROBE
SCIB_TX
SD1_D3
1
5
eQEP-2 Strobe
6
65
SCI-B Transmit Data
7
I
SDFM-1 Channel 3 Data Input
SPI-B Slave In, Master Out (SIMO)
eQEP-1 Input A
SPIB_SIMO
EQEP1_A
9
I/O
I
11
Copyright © 2021 Texas Instruments Incorporated
24
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
Table 6-1. Pin Attributes (continued)
MUX
POSITION
64
PMQ
56
RSH
PIN
TYPE
SIGNAL NAME
100 PZ
64 PM
DESCRIPTION
GPIO57
0, 4, 8, 12
I/O
I/O
I/O
I
General-Purpose Input Output 57
SPIA_STE
EQEP2_INDEX
SCIB_RX
1
SPI-A Slave Transmit Enable (STE)
eQEP-2 Index
5
6
66
SCI-B Receive Data
SD1_C3
7
I
SDFM-1 Channel 3 Clock Input
SPI-B Slave Out, Master In (SOMI)
eQEP-1 Input B
SPIB_SOMI
EQEP1_B
GPIO58
9
I/O
I
11
0, 4, 8, 12
I/O
O
General-Purpose Input Output 58
Output X-BAR Output 1
SPI-B Clock
OUTPUTXBAR1
SPIB_CLK
SD1_D4
5
6
I/O
I
7
67
SDFM-1 Channel 4 Data Input
LIN-A Transmit
LINA_TX
9
O
CANB_TX
EQEP1_STROBE
GPIO59
10
O
CAN-B Transmit
11
I/O
I/O
O
eQEP-1 Strobe
0, 4, 8, 12
General-Purpose Input Output 59
Output X-BAR Output 2
SPI-B Slave Transmit Enable (STE)
SDFM-1 Channel 4 Clock Input
LIN-A Receive
OUTPUTXBAR2
SPIB_STE
SD1_C4
5
6
I/O
I
7
92
LINA_RX
9
I
CANB_RX
EQEP1_INDEX
10
11
I
CAN-B Receive
I/O
eQEP-1 Index
TEST, JTAG, AND RESET
FLT1
FLT2
TCK
49
48
60
30
29
36
I/O
I/O
I
Flash test pin 1. Reserved for TI. Must be left unconnected.
Flash test pin 2. Reserved for TI. Must be left unconnected.
JTAG test clock with internal pullup.
36
38
33
35
JTAG test-mode select (TMS) with internal pullup. This
serial control input is clocked into the TAP controller on the
rising edge of TCK. This device does not have a TRSTn pin.
An external pullup resistor (recommended 2.2 kΩ) on the
TMS pin to VDDIO should be placed on the board to keep
JTAG in reset during normal operation.
TMS
62
73
38
46
I/O
Internal voltage regulator enable with internal pulldown. Tie
directly to VSS (low) to enable the internal VREG. Tie
directly to VDDIO (high) to use an external supply.
VREGENZ
46
42
I
Crystal oscillator input or single-ended clock input. The
device initialization software must configure this pin before
the crystal oscillator is enabled. To use this oscillator, a
quartz crystal circuit must be connected to X1 and X2. This
pin can also be used to feed a single-ended 3.3-V level
clock. GPIO19 is not supported. Internally GPIO19 is
connected to the X1 function, therefore the GPIO19 should
be kept in Input Mode with the Pullup disabled to avoid
interference with the X1 clock function.
X1
69
42
39
I/O
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
25
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
Table 6-1. Pin Attributes (continued)
MUX
POSITION
64
PMQ
56
RSH
PIN
TYPE
SIGNAL NAME
100 PZ
64 PM
DESCRIPTION
Device Reset (in) and Watchdog Reset (out). During a
power-on condition, this pin is driven low by the device. An
external circuit may also drive this pin to assert a device
reset. This pin is also driven low by the MCU when a
watchdog reset occurs. During watchdog reset, the XRSn
pin is driven low for the watchdog reset duration of 512
OSCCLK cycles. A resistor with a value from 2.2 kΩ to 10
kΩ should be placed between XRSn and VDDIO. If a
XRSn
2
3
3
4
I/OD capacitor is placed between XRSn and VSS for noise
filtering, it should be 100 nF or smaller. These values allow
the watchdog to properly drive the XRSn pin to VOL within
512 OSCCLK cycles when the watchdog reset is asserted.
The output buffer of this pin is an open-drain with an internal
pullup. If this pin is driven by an external device, It should be
done using an open-drain device. If this pin is driven by an
external device, it should be done using an open-drain
device.
POWER AND GROUND
1.2-V Digital Logic Power Pins. TI recommends placing a
decoupling capacitor near each VDD pin with a minimum
total capacitance of approximately 20 µF. When not using
the internal voltage regulator, the exact value of the
decoupling capacitance should be determined by your
system voltage regulation solution.
4, 46, 4, 27, 4, 27, 5, 24,
71, 87 44, 59 44, 59 41, 53
VDD
3.3-V Analog Power Pins. Place a minimum 2.2-µF
decoupling capacitor to VSSA on each pin.
VDDA
11, 34
22
22
20
3, 47, 28, 43, 28, 43, 25, 40,
3.3-V Digital I/O Power Pins. Place a minimum 0.1-µF
decoupling capacitor on each pin.
VDDIO
70, 88
80
60
53
60
53
54
48
3.3-V Supply pin for the internal DC-DC regulator. If the
internal DC-DC regulator is used, a bulk input capacitance
of 20-µF should be placed on this pin. Always tie this pin to
the VDDIO pin. A ferrite bead may be used for isolation if
desired but VDDIO_SW and VDDIO must be supplied from
the same source.
VDDIO_SW
5, 45, 5, 26, 5, 26,
72, 86 45, 58 45, 58
VSS
PAD
19
Digital Ground
Analog Ground
VSSA
12, 33
82
21
55
21
55
Internal DC-DC regulator ground. Always tie this pin to the
VSS pin.
VSS_SW
50
Copyright © 2021 Texas Instruments Incorporated
26
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
6.3 Signal Descriptions
6.3.1 Analog Signals
Table 6-2. Analog Signals
PIN
TYPE
SIGNAL NAME
DESCRIPTION
GPIO 100 PZ 64 PMQ 64 PM 56 RSH
A0
ADC-A Input 0
ADC-A Input 1
ADC-A Input 2
ADC-A Input 3
ADC-A Input 4
ADC-A Input 5
ADC-A Input 6
ADC-A Input 8
ADC-A Input 9
ADC-A Input 10
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
23
22
9
15
14
9
15
14
9
13
12
8
A1
A2
A3
10
36
35
6
A4
23
6
23
6
21
A5
A6
A8
37
38
40
9
A9
A10
25
9
25
9
23
8
AIO224
AIO225
AIO226
AIO227
AIO228
AIO229
AIO230
AIO231
AIO232
AIO233
AIO234
AIO236
AIO237
AIO238
AIO239
AIO240
AIO241
AIO242
AIO244
AIO245
AIO246
B0
Digital Input-224 on ADC Pin
Digital Input-225 on ADC Pin
Digital Input-226 on ADC Pin
Digital Input-227 on ADC Pin
Digital Input-228 on ADC Pin
Digital Input-229 on ADC Pin
Digital Input-230 on ADC Pin
Digital Input-231 on ADC Pin
Digital Input-232 on ADC Pin
Digital Input-233 on ADC Pin
Digital Input-234 on ADC Pin
Digital Input-236 on ADC Pin
Digital Input-237 on ADC Pin
Digital Input-238 on ADC Pin
Digital Input-239 on ADC Pin
Digital Input-240 on ADC Pin
Digital Input-241 on ADC Pin
Digital Input-242 on ADC Pin
Digital Input-244 on ADC Pin
Digital Input-245 on ADC Pin
Digital Input-246 on ADC Pin
ADC-B Input 0
36
7
23
7
23
7
21
6
39
6
24
6
24
6
22
37
40
23
22
10
35
38
19
29
17
28
41
8
25
15
14
25
15
14
23
13
12
12
18
11
12
18
11
10
16
8
8
7
21
31
44
41
40
7
13
19
13
19
11
17
B1
ADC-B Input 1
25
7
25
7
23
6
B2
ADC-B Input 2
B3
ADC-B Input 3
8
8
8
7
B4
ADC-B Input 4
39
9
24
9
24
9
22
8
B6
ADC-B Input 6
B8
ADC-B Input 8
36
23
19
29
21
23
15
12
18
13
23
15
12
18
13
21
13
10
16
11
B15
ADC-B Input 15
C0
ADC-C Input 0
C1
ADC-C Input 1
C2
ADC-C Input 2
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
27
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
Table 6-2. Analog Signals (continued)
PIN
TYPE
SIGNAL NAME
DESCRIPTION
GPIO 100 PZ 64 PMQ 64 PM 56 RSH
C3
ADC-C Input 3
ADC-C Input 4
ADC-C Input 5
ADC-C Input 6
ADC-C Input 8
ADC-C Input 10
ADC-C Input 14
ADC-C Input 15
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
31
17
28
7
19
11
19
11
17
C4
C5
C6
7
7
6
C8
39
40
44
23
10
19
9
24
25
24
25
22
23
C10
C14
C15
15
15
13
CMP1_HN0
CMP1_HN1
CMP1_HP0
CMP1_HP1
CMP1_HP2
CMP1_HP3
CMP1_LN0
CMP1_LN1
CMP1_LP0
CMP1_LP1
CMP1_LP2
CMP1_LP3
CMP2_HN0
CMP2_HN1
CMP2_HP0
CMP2_HP1
CMP2_HP2
CMP2_HP3
CMP2_LN0
CMP2_LN1
CMP2_LP0
CMP2_LP1
CMP2_LP2
CMP2_LP3
CMP3_HN0
CMP3_HN1
CMP3_HP0
CMP3_HP1
CMP3_HP2
CMP3_HP3
CMP3_LN0
CMP3_LN1
CMP3_LP0
CMP3_LP1
CMP3_LP2
CMP3_LP3
CMP4_HN1
CMPSS-1 High Comparator Negative Input 0
CMPSS-1 High Comparator Negative Input 1
CMPSS-1 High Comparator Positive Input 0
CMPSS-1 High Comparator Positive Input 1
CMPSS-1 High Comparator Positive Input 2
CMPSS-1 High Comparator Positive Input 3
CMPSS-1 Low Comparator Negative Input 0
CMPSS-1 Low Comparator Negative Input 1
CMPSS-1 Low Comparator Positive Input 0
CMPSS-1 Low Comparator Positive Input 1
CMPSS-1 Low Comparator Positive Input 2
CMPSS-1 Low Comparator Positive Input 3
CMPSS-2 High Comparator Negative Input 0
CMPSS-2 High Comparator Negative Input 1
CMPSS-2 High Comparator Positive Input 0
CMPSS-2 High Comparator Positive Input 1
CMPSS-2 High Comparator Positive Input 2
CMPSS-2 High Comparator Positive Input 3
CMPSS-2 Low Comparator Negative Input 0
CMPSS-2 Low Comparator Negative Input 1
CMPSS-2 Low Comparator Positive Input 0
CMPSS-2 Low Comparator Positive Input 1
CMPSS-2 Low Comparator Positive Input 2
CMPSS-2 Low Comparator Positive Input 3
CMPSS-3 High Comparator Negative Input 0
CMPSS-3 High Comparator Negative Input 1
CMPSS-3 High Comparator Positive Input 0
CMPSS-3 High Comparator Positive Input 1
CMPSS-3 High Comparator Positive Input 2
CMPSS-3 High Comparator Positive Input 3
CMPSS-3 Low Comparator Negative Input 0
CMPSS-3 Low Comparator Negative Input 1
CMPSS-3 Low Comparator Positive Input 0
CMPSS-3 Low Comparator Positive Input 1
CMPSS-3 Low Comparator Positive Input 2
CMPSS-3 Low Comparator Positive Input 3
CMPSS-4 High Comparator Negative Input 1
12
9
12
9
10
8
19
18
10
10
19
9
12
12
12
12
10
10
12
9
12
9
10
8
19
18
10
35
29
36
29
30
35
35
29
36
29
30
35
8
12
12
12
12
10
10
18
23
18
18
18
23
18
18
16
21
16
16
18
23
18
18
18
23
18
18
16
21
16
16
8
13
7
8
13
7
7
11
6
21
7
21
20
8
13
13
8
13
13
8
11
11
7
8
8
8
7
21
7
13
7
13
7
11
6
21
20
8
13
13
8
13
13
8
11
11
7
31
19
19
17
Copyright © 2021 Texas Instruments Incorporated
28
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
Table 6-2. Analog Signals (continued)
PIN
TYPE
SIGNAL NAME
DESCRIPTION
GPIO 100 PZ 64 PMQ 64 PM 56 RSH
CMP4_HP0
CMP4_HP1
CMP4_HP2
CMP4_LN1
CMP4_LP0
CMP4_LP1
CMP4_LP2
CMP5_HN1
CMP5_HP0
CMP5_HP1
CMP5_HP2
CMP5_LN1
CMP5_LP0
CMP5_LP1
CMP5_LP2
CMP6_HN0
CMP6_HN1
CMP6_HP0
CMP6_HP1
CMP6_HP2
CMP6_HP3
CMP6_LN0
CMP6_LN1
CMP6_LP0
CMP6_LP1
CMP6_LP2
CMP6_LP3
CMP7_HN0
CMP7_HN1
CMP7_HP0
CMP7_HP1
CMP7_HP2
CMP7_HP3
CMP7_LN0
CMP7_LN1
CMP7_LP0
CMP7_LP1
CMP7_LP2
CMP7_LP3
DACA_OUT
DACB_OUT
PGA1_GND
PGA1_IN
CMPSS-4 High Comparator Positive Input 0
CMPSS-4 High Comparator Positive Input 1
CMPSS-4 High Comparator Positive Input 2
CMPSS-4 Low Comparator Negative Input 1
CMPSS-4 Low Comparator Positive Input 0
CMPSS-4 Low Comparator Positive Input 1
CMPSS-4 Low Comparator Positive Input 2
CMPSS-5 High Comparator Negative Input 1
CMPSS-5 High Comparator Positive Input 0
CMPSS-5 High Comparator Positive Input 1
CMPSS-5 High Comparator Positive Input 2
CMPSS-5 Low Comparator Negative Input 1
CMPSS-5 Low Comparator Positive Input 0
CMPSS-5 Low Comparator Positive Input 1
CMPSS-5 Low Comparator Positive Input 2
CMPSS-6 High Comparator Negative Input 0
CMPSS-6 High Comparator Negative Input 1
CMPSS-6 High Comparator Positive Input 0
CMPSS-6 High Comparator Positive Input 1
CMPSS-6 High Comparator Positive Input 2
CMPSS-6 High Comparator Positive Input 3
CMPSS-6 Low Comparator Negative Input 0
CMPSS-6 Low Comparator Negative Input 1
CMPSS-6 Low Comparator Positive Input 0
CMPSS-6 Low Comparator Positive Input 1
CMPSS-6 Low Comparator Positive Input 2
CMPSS-6 Low Comparator Positive Input 3
CMPSS-7 High Comparator Negative Input 0
CMPSS-7 High Comparator Negative Input 1
CMPSS-7 High Comparator Positive Input 0
CMPSS-7 High Comparator Positive Input 1
CMPSS-7 High Comparator Positive Input 2
CMPSS-7 High Comparator Positive Input 3
CMPSS-7 Low Comparator Negative Input 0
CMPSS-7 Low Comparator Negative Input 1
CMPSS-7 Low Comparator Positive Input 0
CMPSS-7 Low Comparator Positive Input 1
CMPSS-7 Low Comparator Positive Input 2
CMPSS-7 Low Comparator Positive Input 3
Buffered DAC-A Output
I
I
39
31
31
31
39
31
31
17
6
24
19
19
19
24
19
19
11
6
24
19
19
19
24
19
19
11
6
22
17
17
17
22
17
17
I
I
I
I
I
I
I
I
17
16
17
6
11
11
11
6
11
11
11
6
I
I
I
I
17
16
38
28
37
28
28
38
38
28
37
28
28
38
41
44
40
44
43
41
41
44
40
44
43
41
23
22
14
18
9
11
11
11
11
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
25
25
23
I
I
I
I
I
I
25
25
23
I
I
I
O
O
I
15
14
10
12
9
15
14
10
12
9
13
12
9
Buffered DAC-B Output
PGA-1 Ground
PGA-1 Input
I
10
8
PGA1_OF
PGA-1 Output Filter (Optional)
O
I
PGA2_GND
PGA-2 Ground
32
20
20
18
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
29
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
Table 6-2. Analog Signals (continued)
PIN
TYPE
SIGNAL NAME
PGA2_IN
DESCRIPTION
GPIO 100 PZ 64 PMQ 64 PM 56 RSH
PGA-2 Input
I
O
I
30
36
15
20
7
18
23
10
13
7
18
23
10
13
7
16
21
9
PGA2_OF
PGA3_GND
PGA3_IN
PGA-2 Output Filter (Optional)
PGA-3 Ground
PGA-3 Input
I
11
6
PGA3_OF
PGA4_GND
PGA4_IN
PGA-3 Output Filter (Optional)
PGA-4 Ground
O
I
32
31
39
13
16
6
20
19
24
10
11
6
20
19
24
10
11
6
18
17
22
9
PGA-4 Input
I
PGA4_OF
PGA5_GND
PGA5_IN
PGA-4 Output Filter (Optional)
PGA-5 Ground
O
I
PGA-5 Input
I
PGA5_OF
PGA6_GND
PGA6_IN
PGA-5 Output Filter (Optional)
PGA-6 Ground
O
I
32
28
37
42
43
40
20
20
18
PGA-6 Input
I
PGA6_OF
PGA7_GND
PGA7_IN
PGA-6 Output Filter (Optional)
PGA-7 Ground
O
I
PGA-7 Input
I
PGA7_OF
PGA-7 Output Filter (Optional)
O
25
8
25
8
23
7
Optional external reference voltage for on-chip
DACs. There is a 100-pF capacitor to VSSA on
this pin whether used for ADC input or DAC
reference which cannot be disabled. If this pin
is being used as a reference for the on-chip
DACs, place at least a 1-µF capacitor on this
pin.
VDAC
I
8
ADC-A High Reference. In external reference
mode, externally drive the high reference
voltage onto this pin. In internal reference
mode, a voltage is driven onto this pin by the
device. In either mode, place at least a 2.2-µF
capacitor on this pin. This capacitor should be
placed as close to the device as possible
between the VREFHIA and VREFLOA pins. Do
not load this pin externally in either internal or
external reference mode.
VREFHIA
I/O
25
16
16
14
ADC-B High Reference. In external reference
mode, externally drive the high reference
voltage onto this pin. In internal reference
mode, a voltage is driven onto this pin by the
device. In either mode, place at least a 2.2-µF
capacitor on this pin. This capacitor should be
placed as close to the device as possible
between the VREFHIB and VREFLOB pins. Do
not load this pin externally in either internal or
external reference mode.
VREFHIB
I/O
24
16
16
14
ADC-C High Reference. In external reference
mode, externally drive the high reference
voltage onto this pin. In internal reference
mode, a voltage is driven onto this pin by the
device. In either mode, place at least a 2.2-µF
capacitor on this pin. This capacitor should be
placed as close to the device as possible
between the VREFHIC and VREFLOC pins.
Do not load this pin externally in either internal
or external reference mode.
VREFHIC
VREFLOA
I/O
24
27
16
17
16
17
14
15
ADC-A Low Reference
I
Copyright © 2021 Texas Instruments Incorporated
30
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
Table 6-2. Analog Signals (continued)
PIN
TYPE
SIGNAL NAME
DESCRIPTION
GPIO 100 PZ 64 PMQ 64 PM 56 RSH
VREFLOB
VREFLOC
ADC-B Low Reference
ADC-C Low Reference
I
I
26
26
17
17
17
17
15
15
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
31
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
6.3.2 Digital Signals
Table 6-3. Digital Signals
PIN
TYPE
SIGNAL NAME
ADCSOCAO
DESCRIPTION
GPIO 100 PZ 64 PMQ 64 PM 56 RSH
ADC Start of Conversion A Output for External
ADC (from ePWM modules)
O
8
74
93
47
63
47
63
42
ADC Start of Conversion B Output for External
ADC (from ePWM modules)
ADCSOCBO
CANA_RX
CANA_TX
CANB_RX
O
I
10
18, 30, 53, 63,
33, 35, 68, 89,
32, 39, 32, 39, 29, 36,
41, 61 41, 61 38, 55
CAN-A Receive
CAN-A Transmit
CAN-B Receive
5
98
31, 32, 61, 64, 37, 40, 37, 40, 34, 37,
37, 4 75, 99 48 48 43
O
I
10, 13, 50, 55,
17, 39, 84, 91,
34, 57, 29, 34, 26, 31,
63
57, 63
52
59, 7
92, 93
51, 54,
67, 74,
97
12, 16,
58, 6, 8
33, 47, 30, 33,
1, 27,
30, 42
CANB_TX
CAN-B Transmit
O
64
47, 64
EPWM1_A
EPWM1_B
EPWM2_A
EPWM2_B
EPWM3_A
EPWM3_B
EPWM4_A
EPWM4_B
EPWM5_A
EPWM5_B
EPWM6_A
EPWM6_B
EPWM7_A
EPWM7_B
EPWM8_A
EPWM8_B
ePWM-1 Output A
ePWM-1 Output B
ePWM-2 Output A
ePWM-2 Output B
ePWM-3 Output A
ePWM-3 Output B
ePWM-4 Output A
ePWM-4 Output B
ePWM-5 Output A
ePWM-5 Output B
ePWM-6 Output A
ePWM-6 Output B
ePWM-7 Output A
ePWM-7 Output B
ePWM-8 Output A
ePWM-8 Output B
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
0
79
78
52
51
52
51
47
46
1
2
3
77
50
50
45
76
49
49
44
4
75
48
48
43
5
89
61
61
55
6
97
64
64
1
7
84
57
57
52
16, 8
17, 9
10, 18
11
54, 74
55, 90
68, 93
52
33, 47
34, 62
41, 63
31
33, 47
34, 62
41, 63
31
30, 42
31, 56
38
28
12, 28
1, 51
2
2, 30
1, 29
35
27, 3
2, 26
32
13, 29 100, 50
1
14, 24
15, 32
10, 28,
35, 40, 65, 85,
56, 6 93, 97
56, 96
64, 95
1, 63,
35
40
40
37
2, 39,
63, 64
2, 39,
63, 64
EQEP1_A
eQEP-1 Input A
eQEP-1 Input B
eQEP-1 Index
eQEP-1 Strobe
I
1, 3, 36
11, 29, 100, 52,
37, 57, 61, 66,
1, 31,
37, 57
1, 31,
37, 57
2, 28,
34, 52
EQEP1_B
I
7
84
13, 17, 50, 55,
31, 59, 90, 92, 34, 62
99
29, 34, 26, 31,
62 56
EQEP1_INDEX
EQEP1_STROBE
I/O
I/O
9
12, 16, 51, 54,
22, 30, 67, 74,
58, 8
33, 47, 30, 33, 27, 30,
56
47, 56
42, 51
83, 98
14, 18, 56, 68,
EQEP2_A
eQEP-2 Input A
eQEP-2 Input B
eQEP-2 Index
I
I
35, 41
35, 41
32, 38
24
96
EQEP2_B
15, 25
57, 95
26, 29, 100, 58,
57 66
EQEP2_INDEX
I/O
1
1
2
Copyright © 2021 Texas Instruments Incorporated
32
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
Table 6-3. Digital Signals (continued)
PIN
TYPE
SIGNAL NAME
DESCRIPTION
GPIO 100 PZ 64 PMQ 64 PM 56 RSH
27, 28,
56
1, 59,
65
EQEP2_STROBE
ERRORSTS
FSIRXA_CLK
FSIRXA_D0
FSIRXA_D1
FSITXA_CLK
FSITXA_D0
eQEP-2 Strobe
I/O
2
2
3
Error Status Output. This signal requires an
external pullup.
24, 28, 1, 100,
29 56
O
I
1, 2, 35 1, 2, 35 2, 3, 32
13, 33, 50, 53,
39, 4
29, 32, 26, 29,
32, 48
FSIRX-A Input Clock
75, 91
48
43
12, 3,
32, 40
51, 64,
76, 85
30, 40, 27, 37,
49
FSIRX-A Primary Data Input
FSIRX-A Optional Additional Data Input
FSITX-A Output Clock
I
40, 49
31, 50
57, 63
62, 64
47, 61
44
11, 2,
31
52, 77,
99
I
31, 50
28, 45
10, 27, 59, 84,
O
O
O
57, 63
62, 64
47, 61
52
7
93
58, 90,
97
FSITX-A Primary Data Output
FSITX-A Optional Additional Data Output
26, 6, 9
1, 56
42, 55
57, 74,
89
FSITXA_D1
25, 5, 8
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
General-Purpose Input Output 0
General-Purpose Input Output 1
General-Purpose Input Output 2
General-Purpose Input Output 3
General-Purpose Input Output 4
General-Purpose Input Output 5
General-Purpose Input Output 6
General-Purpose Input Output 7
General-Purpose Input Output 8
General-Purpose Input Output 9
General-Purpose Input Output 10
General-Purpose Input Output 11
General-Purpose Input Output 12
General-Purpose Input Output 13
General-Purpose Input Output 14
General-Purpose Input Output 15
General-Purpose Input Output 16
General-Purpose Input Output 17
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
79
78
77
76
75
89
97
84
74
90
93
52
51
50
96
95
54
55
52
51
50
49
48
61
64
57
47
62
63
31
52
51
50
49
48
61
64
57
47
62
63
31
30
29
47
46
45
44
43
55
1
2
3
4
5
6
7
52
42
56
8
9
10
11
12
13
14
15
16
17
28
27
26
33
34
33
34
30
31
General-Purpose Input Output 18. This pin and
its digital mux options can only be used when
the system is clocked by INTOSC and X1 has
an external pulldown resistor (recommended 1
kΩ).
GPIO18_X2
I/O
18
68
41
41
38
GPIO20
GPIO21
General-Purpose Input Output 20
General-Purpose Input Output 21
I/O
I/O
20
21
General-Purpose Input Output 22. This pin is
configured for DC-DC mode by default. If the
internal DC-DC regulator is not used, this can
be configured as General-Purpose Input
Output 22 by disabling DC-DC and clearing
their bits in GPAAMSEL register.
GPIO22_VFBSW
I/O
22
83
56
56
51
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
33
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
Table 6-3. Digital Signals (continued)
PIN
TYPE
SIGNAL NAME
DESCRIPTION
GPIO 100 PZ 64 PMQ 64 PM 56 RSH
General-Purpose Input Output 23. This pin is
configured for DC-DC mode by default. If the
internal DC-DC regulator is not used, this can
be configured as General-Purpose Input
Output 23 by disabling DC-DC and clearing
their bits in GPAAMSEL register. This pin has
an internal capacitance of approximately 100
pF. TI Recommends using an alternate GPIO,
or using this pin only for applications which do
not require a fast switching response.
GPIO23_VSW
I/O
23
81
54
35
54
35
49
32
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
GPIO35
GPIO37
GPIO39
GPIO40
GPIO41
GPIO42
GPIO43
GPIO44
GPIO45
GPIO46
GPIO47
GPIO48
GPIO49
GPIO50
GPIO51
GPIO52
GPIO53
GPIO54
GPIO55
GPIO56
GPIO57
GPIO58
GPIO59
General-Purpose Input Output 24
General-Purpose Input Output 25
General-Purpose Input Output 26
General-Purpose Input Output 27
General-Purpose Input Output 28
General-Purpose Input Output 29
General-Purpose Input Output 30
General-Purpose Input Output 31
General-Purpose Input Output 32
General-Purpose Input Output 33
General-Purpose Input Output 34
General-Purpose Input Output 35
General-Purpose Input Output 37
General-Purpose Input Output 39
General-Purpose Input Output 40
General-Purpose Input Output 41
General-Purpose Input Output 42
General-Purpose Input Output 43
General-Purpose Input Output 44
General-Purpose Input Output 45
General-Purpose Input Output 46
General-Purpose Input Output 47
General-Purpose Input Output 48
General-Purpose Input Output 49
General-Purpose Input Output 50
General-Purpose Input Output 51
General-Purpose Input Output 52
General-Purpose Input Output 53
General-Purpose Input Output 54
General-Purpose Input Output 55
General-Purpose Input Output 56
General-Purpose Input Output 57
General-Purpose Input Output 58
General-Purpose Input Output 59
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
24
25
26
27
28
29
30
31
32
33
34
35
37
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
1, 18,
56
57
58
59
1
2
1
2
1
3
2
100
98
99
64
53
94
63
61
91
85
40
32
40
32
37
29
39
37
39
37
36
34
65
66
67
92
53, 59, 32, 37, 32, 37, 29, 34,
27, 33, 61, 68, 41, 47, 41, 47, 38, 42,
37, 8 74, 78 51 51 46
I2CA_SCL
I2C-A Open-Drain Bidirectional Clock
I/OD
Copyright © 2021 Texas Instruments Incorporated
34
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
Table 6-3. Digital Signals (continued)
PIN
TYPE
SIGNAL NAME
DESCRIPTION
I2C-A Open-Drain Bidirectional Data
LIN-A Receive
GPIO 100 PZ 64 PMQ 64 PM 56 RSH
0, 10,
26, 32, 64, 79,
35 93
58, 63,
39, 40, 39, 40, 36, 37,
I2CA_SDA
LINA_RX
LINA_TX
I/OD
52, 63
52, 63
47
29, 33, 100, 53, 1, 32,
1, 32,
39
2, 29,
36
I
35, 59
63, 92
39
22, 28,
32, 37, 64, 67,
58
1, 61,
2, 37,
40, 56
2, 37,
40, 56
3, 34,
37, 51
LIN-A Transmit
O
83
2, 24,
34, 58
56, 67,
77, 94
OUTPUTXBAR1
OUTPUTXBAR2
OUTPUTXBAR3
OUTPUTXBAR4
Output X-BAR Output 1
Output X-BAR Output 2
Output X-BAR Output 3
Output X-BAR Output 4
O
O
O
O
35, 50
37, 49
48, 61
32, 64
35, 50
37, 49
48, 61
32, 64
32, 45
34, 44
43, 55
1, 29
25, 3,
37, 59
57, 61,
76, 92
14, 26, 58, 75,
4, 5 89, 96
15, 27, 53, 59,
33, 6
28, 7
29, 9
95, 97
OUTPUTXBAR5
OUTPUTXBAR6
Output X-BAR Output 5
Output X-BAR Output 6
O
O
1, 84
2, 57
1, 62
2, 57
1, 62
3, 52
2, 56
100, 90
11, 16, 52, 54,
OUTPUTXBAR7
OUTPUTXBAR8
PMBUSA_ALERT
Output X-BAR Output 7
O
O
31, 33
34
31, 33
34
28, 30
31
30
98
Output X-BAR Output 8
17, 31
55, 99
13, 27, 50, 59,
37 61
PMBus-A Open-Drain Bidirectional Alert Signal
I/OD
37
29, 37
26, 34
12, 18, 51, 58,
26, 35 63, 68
30, 39, 27, 36,
41 38
PMBUSA_CTL
PMBUSA_SCL
PMBus-A Control Signal
I
39, 41
15, 16, 54, 56,
33, 35, 33, 35, 30, 32,
PMBus-A Open-Drain Bidirectional Clock
I/OD
24, 3,
35
63, 76,
95
39, 49
39, 49
36, 44
14, 17, 55, 57,
PMBUSA_SDA
SCIA_RX
PMBus-A Open-Drain Bidirectional Data
SCI-A Receive Data
I/OD
I
2, 25,
34, 40
77, 85, 34, 50
94, 96
34, 50
2, 34,
31, 45
3, 31,
17, 25,
28, 3,
35, 9
1, 55,
2, 34,
57, 63, 39, 49, 39, 49, 36, 44,
76, 90
62
62
56
16, 2, 100, 54, 1, 33,
1, 33,
2, 30,
SCIA_TX
SCIB_RX
SCI-A Transmit Data
SCI-B Receive Data
O
I
24, 29, 56, 61, 35, 37, 35, 37, 32, 34,
37, 8
11, 13, 50, 52,
15, 57 66, 95
10, 12, 51, 65,
74, 77
47, 50
47, 50
42, 45
31
29, 31
26, 28
30, 41,
56, 62,
63
14, 18, 68, 83, 41, 56,
22, 40, 85, 90, 62, 63
27, 38,
51, 56
SCIB_TX
SCI-B Transmit Data
O
56, 9
17, 25
27
93, 96
55, 57
59
SD1_C1
SD1_C2
SDFM-1 Channel 1 Clock Input
SDFM-1 Channel 2 Clock Input
I
I
34
34
31
29, 33, 100, 53,
SD1_C3
SDFM-1 Channel 3 Clock Input
I
1, 32
1, 32
2, 29
57
66
SD1_C4
SD1_D1
SD1_D2
SDFM-1 Channel 4 Clock Input
SDFM-1 Channel 1 Data Input
SDFM-1 Channel 2 Data Input
I
I
I
31, 59
16, 24
18, 26
92, 99
54, 56
58, 68
33, 35
41
33, 35
41
30, 32
38
28, 32,
56
1, 64,
65
SD1_D3
SDFM-1 Channel 3 Data Input
I
2, 40
2, 40
3, 37
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
35
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
Table 6-3. Digital Signals (continued)
PIN
TYPE
SIGNAL NAME
SD1_D4
DESCRIPTION
SDFM-1 Channel 4 Data Input
SPI-A Clock
GPIO 100 PZ 64 PMQ 64 PM 56 RSH
22, 30, 67, 83,
I
56
56
51
58
98
18, 3,
56, 9
65, 68, 41, 49, 41, 49, 38, 44,
SPIA_CLK
I/O
76, 90
54, 74
55, 93
62
62
56
30, 42
31
SPIA_SIMO
SPIA_SOMI
SPI-A Slave In, Master Out (SIMO)
SPI-A Slave Out, Master In (SOMI)
I/O
I/O
16, 8
33, 47
34, 63
33, 47
34, 63
10, 17
11, 5,
57
52, 66,
89
SPIA_STE
SPIB_CLK
SPI-A Slave Transmit Enable (STE)
SPI-B Clock
I/O
I/O
31, 61
31, 61
28, 55
14, 22,
26, 28, 64, 67,
32, 58 83, 96
1, 58,
2, 40,
56
2, 40,
56
3, 37,
51
24, 30, 56, 65,
56, 7 84, 98
SPIB_SIMO
SPIB_SOMI
SPI-B Slave In, Master Out (SIMO)
SPI-B Slave Out, Master In (SOMI)
I/O
I/O
35, 57
64
35, 57
64
32, 52
1
25, 31, 57, 66,
57, 6 97, 99
15, 27, 100, 53,
29, 33, 59, 92,
SPIB_STE
SYNCOUT
SPI-B Slave Transmit Enable (STE)
External ePWM Synchronization Pulse
I/O
O
1, 32
64
1, 32
64
2, 29
1
59
95
6
97
JTAG Test Data Input (TDI) - TDI is the default
mux selection for the pin. The internal pullup is
disabled by default. The internal pullup should
be enabled or an external pullup added on the
board if this pin is used as JTAG TDI to avoid a
floating input.
TDI
I
35
63
39
39
36
JTAG Test Data Output (TDO) - TDO is the
default mux selection for the pin. The internal
pullup is disabled by default. The TDO function
will be in a tri-state condition when there is no
JTAG activity, leaving this pin floating; the
internal pullup should be enabled or an
external pullup added on the board to avoid a
floating GPIO input.
TDO
O
37
22
61
83
37
56
37
56
34
51
Internal DC-DC regulator feedback signal. If
the internal DC-DC regulator is used, tie this
pin to the node where L(VSW) connects to the
VDD rail (as close as possible to the device).
VFBSW
-
Switching output of the internal DC-DC
regulator
VSW
X2
-
23
18
81
68
54
41
54
41
49
38
Crystal oscillator output
I/O
External Clock Output. This pin outputs a
divided-down version of a chosen clock signal
from within the device.
XCLKOUT
O
16, 18
54, 68
33, 41
33, 41
30, 38
Copyright © 2021 Texas Instruments Incorporated
36
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
6.3.3 Power and Ground
Table 6-4. Power and Ground
PIN
TYPE
SIGNAL NAME
DESCRIPTION
GPIO 100 PZ 64 PMQ 64 PM 56 RSH
1.2-V Digital Logic Power Pins. TI
recommends placing a decoupling capacitor
near each VDD pin with a minimum total
capacitance of approximately 20 µF. When not
using the internal voltage regulator, the exact
value of the decoupling capacitance should be
determined by your system voltage regulation
solution.
4, 46,
71, 87
27, 4,
44, 59
27, 4,
44, 59
24, 41,
5, 53
VDD
3.3-V Analog Power Pins. Place a minimum
2.2-µF decoupling capacitor to VSSA on each
pin.
VDDA
11, 34
22
22
20
3.3-V Digital I/O Power Pins. Place a minimum
0.1-µF decoupling capacitor on each pin.
3, 47,
70, 88
28, 43, 28, 43, 25, 40,
VDDIO
60
60
54
3.3-V Supply pin for the internal DC-DC
regulator. If the internal DC-DC regulator is
used, a bulk input capacitance of 20-µF should
be placed on this pin. Always tie this pin to the
VDDIO pin. A ferrite bead may be used for
isolation if desired but VDDIO_SW and VDDIO
must be supplied from the same source.
VDDIO_SW
80
53
53
48
45, 5,
72, 86
26, 45, 26, 45,
VSS
Digital Ground
Analog Ground
PAD
19
5, 58
5, 58
VSSA
12, 33
82
21
21
Internal DC-DC regulator ground. Always tie
this pin to the VSS pin.
VSS_SW
55
55
50
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
37
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
6.3.4 Test, JTAG, and Reset
Table 6-5. Test, JTAG, and Reset
PIN
TYPE
SIGNAL NAME
DESCRIPTION
GPIO 100 PZ 64 PMQ 64 PM 56 RSH
Flash test pin 1. Reserved for TI. Must be left
unconnected.
FLT1
I/O
49
30
Flash test pin 2. Reserved for TI. Must be left
unconnected.
FLT2
TCK
I/O
I
48
60
29
36
JTAG test clock with internal pullup.
36
38
33
35
JTAG test-mode select (TMS) with internal
pullup. This serial control input is clocked into
the TAP controller on the rising edge of TCK.
This device does not have a TRSTn pin. An
external pullup resistor (recommended 2.2 kΩ)
on the TMS pin to VDDIO should be placed on
the board to keep JTAG in reset during normal
operation.
TMS
I/O
62
73
38
46
Internal voltage regulator enable with internal
pulldown. Tie directly to VSS (low) to enable
the internal VREG. Tie directly to VDDIO (high)
to use an external supply.
VREGENZ
I
46
42
Crystal oscillator input or single-ended clock
input. The device initialization software must
configure this pin before the crystal oscillator is
enabled. To use this oscillator, a quartz crystal
circuit must be connected to X1 and X2. This
pin can also be used to feed a single-ended
3.3-V level clock. GPIO19 is not supported.
Internally GPIO19 is connected to the X1
function, therefore the GPIO19 should be kept
in Input Mode with the Pullup disabled to avoid
interference with the X1 clock function.
X1
I/O
69
42
39
Device Reset (in) and Watchdog Reset (out).
During a power-on condition, this pin is driven
low by the device. An external circuit may also
drive this pin to assert a device reset. This pin
is also driven low by the MCU when a
watchdog reset occurs. During watchdog reset,
the XRSn pin is driven low for the watchdog
reset duration of 512 OSCCLK cycles. A
resistor with a value from 2.2 kΩ to 10 kΩ
should be placed between XRSn and VDDIO.
If a capacitor is placed between XRSn and
VSS for noise filtering, it should be 100 nF or
smaller. These values allow the watchdog to
properly drive the XRSn pin to VOL within 512
OSCCLK cycles when the watchdog reset is
asserted. The output buffer of this pin is an
open-drain with an internal pullup. If this pin is
driven by an external device, It should be done
using an open-drain device. If this pin is driven
by an external device, it should be done using
an open-drain device.
XRSn
I/OD
2
3
3
4
Copyright © 2021 Texas Instruments Incorporated
38
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
6.4 Pin Multiplexing
6.4.1 GPIO Muxed Pins
Table 1-1 lists the GPIO muxed pins. The default mode for each GPIO pin is the GPIO function, except GPIO35
and GPIO37, which default to TDI and TDO, respectively. Secondary functions can be selected by setting both
the GPyGMUXn.GPIOz and GPyMUXn.GPIOz register bits. The GPyGMUXn register should be configured
before the GPyMUXn to avoid transient pulses on GPIOs from alternate mux selections. Columns that are not
shown and blank cells are reserved GPIO Mux settings.
Note
GPIO20, GPIO21, and GPIO41 to GPIO55 are not available on any packages. Boot ROM enables
pullups on these pins. For more details, see Section 6.5.
Table 6-6. GPIO Muxed Pins
0, 4, 8, 12
GPIO0
1
2
3
5
6
7
9
10
11
13
14
15
EPWM1_A
EPWM1_B
I2CA_SDA
I2CA_SCL
GPIO1
OUTPUTXB PMBUSA_S
AR1 DA
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
EPWM2_A
EPWM2_B
EPWM3_A
EPWM3_B
EPWM4_A
EPWM4_B
EPWM5_A
EPWM5_B
EPWM6_A
EPWM6_B
EPWM7_A
EPWM7_B
EPWM8_A
EPWM8_B
SCIA_TX
SCIA_RX
FSIRXA_D1
FSIRXA_D0
OUTPUTXB
AR2
OUTPUTXB PMBUSA_S
SPIA_CLK
AR2
CL
OUTPUTXB
AR3
FSIRXA_CL
K
CANA_TX
OUTPUTXB
AR3
CANA_RX
SPIA_STE FSITXA_D1
OUTPUTXB
AR4
SYNCOUT
EQEP1_A
EQEP1_B
CANB_TX SPIB_SOMI FSITXA_D0
OUTPUTXB
AR5
FSITXA_CL
CANB_RX SPIB_SIMO
K
ADCSOCA EQEP1_ST
ROBE
CANB_TX
SCIB_TX
CANB_RX
SCIB_RX
CANB_TX
CANB_RX
SCIB_TX
SCIB_RX
SCIA_TX
SCIA_RX
SCIB_TX
SCIB_RX
SCIB_TX
SCIB_RX
SPIA_SIMO I2CA_SCL FSITXA_D1
O
OUTPUTXB EQEP1_IND
SPIA_CLK
FSITXA_D0
AR6
EX
ADCSOCB
O
FSITXA_CL
K
EQEP1_A
SPIA_SOMI I2CA_SDA
SPIA_STE FSIRXA_D1
OUTPUTXB
AR7
EQEP1_B
EQEP1_ST
ROBE
PMBUSA_C
FSIRXA_D0
TL
EQEP1_IND
EX
PMBUSA_A FSIRXA_CL
LERT
K
OUTPUTXB PMBUSA_S
SPIB_CLK
EQEP2_A
EQEP2_B
AR3 DA
OUTPUTXB PMBUSA_S
SPIB_STE
AR4
CL
OUTPUTXB
AR7
EQEP1_ST PMBUSA_S
ROBE CL
SPIA_SIMO CANB_TX
SPIA_SOMI CANB_RX
EPWM5_A
EPWM5_B
EPWM6_A
SCIA_TX
SD1_D1
XCLKOUT
XCLKOUT
OUTPUTXB
AR8
EQEP1_IND PMBUSA_S
SCIA_RX
SD1_C1
SD1_D2
EX
DA
PMBUSA_C
TL
GPIO18_X2 SPIA_CLK
SCIB_TX
CANA_RX
SCIB_TX
I2CA_SCL
EQEP2_A
GPIO20
GPIO21
GPIO22_VF EQEP1_ST
BSW
SPIB_CLK
SD1_D4
LINA_TX
ROBE
GPIO23_VS
W
OUTPUTXB
AR1
PMBUSA_S
CL
GPIO24
GPIO25
GPIO26
GPIO27
EQEP2_A
EQEP2_B
EPWM8_A SPIB_SIMO
SPIB_SOMI
SD1_D1
SD1_C1
SD1_D2
SD1_C2
SCIA_TX
SCIA_RX
I2CA_SDA
I2CA_SCL
ERRORSTS
OUTPUTXB
AR2
PMBUSA_S
DA
FSITXA_D1
FSITXA_D0
OUTPUTXB EQEP2_IND
AR3 EX
OUTPUTXB
SPIB_CLK
AR3
PMBUSA_C
TL
OUTPUTXB EQEP2_ST
AR4 ROBE
OUTPUTXB
SPIB_STE
AR4
FSITXA_CL PMBUSA_A
LERT
K
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
39
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
Table 6-6. GPIO Muxed Pins (continued)
0, 4, 8, 12
1
2
3
5
6
7
9
10
11
13
14
15
OUTPUTXB
AR5
EQEP2_ST
ROBE
GPIO28
SCIA_RX
EPWM7_A
EQEP1_A
SD1_D3
LINA_TX
SPIB_CLK ERRORSTS
SPIB_STE ERRORSTS
OUTPUTXB
AR6
EQEP2_IND
EX
GPIO29
GPIO30
SCIA_TX
EPWM7_B
EQEP1_B
SD1_C3
SD1_D4
LINA_RX
OUTPUTXB EQEP1_ST
CANA_RX
SPIB_SIMO
AR7
ROBE
OUTPUTXB EQEP1_IND
GPIO31
GPIO32
GPIO33
CANA_TX
I2CA_SDA
I2CA_SCL
SPIB_SOMI
SPIB_CLK
SPIB_STE
SD1_C4
SD1_D3
SD1_C3
FSIRXA_D1
AR8
EX
EPWM8_B
LINA_TX
FSIRXA_D0 CANA_TX
OUTPUTXB
AR4
FSIRXA_CL
CANA_RX
K
LINA_RX
OUTPUTXB
AR1
PMBUSA_S
DA
GPIO34
GPIO35
GPIO37
GPIO39
GPIO40
PMBUSA_S
CL
PMBUSA_C
SCIA_RX
I2CA_SDA
I2CA_SCL
CANA_RX
SCIA_TX
LINA_RX
LINA_TX
EQEP1_A
TL
TDI
OUTPUTXB
AR2
PMBUSA_A
EQEP1_B
CANA_TX
CANB_RX
TDO
LERT
FSIRXA_CL
K
PMBUSA_S
DA
FSIRXA_D0
SCIB_TX
EQEP1_A
GPIO41
GPIO42
GPIO43
GPIO44
GPIO45
GPIO46
GPIO47
GPIO48
GPIO49
GPIO50
GPIO51
GPIO52
GPIO53
GPIO54
GPIO55
EQEP2_ST
ROBE
GPIO56
GPIO57
GPIO58
GPIO59
SPIA_CLK
SPIA_STE
SCIB_TX
SCIB_RX
SPIB_CLK
SPIB_STE
SD1_D3
SD1_C3
SD1_D4
SD1_C4
SPIB_SIMO
SPIB_SOMI
LINA_TX
EQEP1_A
EQEP1_B
EQEP2_IND
EX
OUTPUTXB
AR1
EQEP1_ST
ROBE
CANB_TX
CANB_RX
OUTPUTXB
AR2
EQEP1_IND
EX
LINA_RX
Table 1-1 lists all muxed signals available and the respective GPIO within each package.
Table 6-7. Digital Signals by GPIO
SIGNAL NAME
ADCSOCAO
PIN TYPE
DESCRIPTION
100 PZ
64 PMQ
64 PM
56 RSH
ADC Start of Conversion A Output for External
ADC (from ePWM modules)
O
GPIO8
GPIO8
GPIO8
GPIO8
ADC Start of Conversion B Output for External
ADC (from ePWM modules)
ADCSOCBO
O
I
GPIO10
GPIO10
GPIO5
GPIO10
GPIO5
GPIO18_X
2
GPIO30
GPIO33
GPIO35/T
DI
GPIO5
GPIO5
GPIO18_X GPIO18_X GPIO18_X
2
2
2
CANA_RX
CAN-A Receive
GPIO33
GPIO33
GPIO33
GPIO35/T GPIO35/T GPIO35/T
DI DI DI
Copyright © 2021 Texas Instruments Incorporated
40
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
Table 6-7. Digital Signals by GPIO (continued)
SIGNAL NAME
PIN TYPE
DESCRIPTION
100 PZ
64 PMQ
64 PM
56 RSH
GPIO4
GPIO31
GPIO32
GPIO37/T
DO
GPIO4
GPIO32
GPIO4
GPIO32
GPIO4
GPIO32
CANA_TX
CANB_RX
CANB_TX
O
CAN-A Transmit
CAN-B Receive
CAN-B Transmit
GPIO37/T GPIO37/T GPIO37/T
DO
DO
DO
GPIO7
GPIO10
GPIO13
GPIO17
GPIO39
GPIO59
GPIO7
GPIO10
GPIO13
GPIO17
GPIO7
GPIO10
GPIO17
GPIO7
GPIO13
GPIO17
I
GPIO6
GPIO8
GPIO12
GPIO16
GPIO58
GPIO6
GPIO8
GPIO12
GPIO16
GPIO6
GPIO8
GPIO12
GPIO16
GPIO6
GPIO8
GPIO16
O
EPWM1_A
EPWM1_B
EPWM2_A
EPWM2_B
EPWM3_A
EPWM3_B
EPWM4_A
EPWM4_B
O
O
O
O
O
O
O
O
ePWM-1 Output A
ePWM-1 Output B
ePWM-2 Output A
ePWM-2 Output B
ePWM-3 Output A
ePWM-3 Output B
ePWM-4 Output A
ePWM-4 Output B
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO16
GPIO8
GPIO16
GPIO8
GPIO16
GPIO8
GPIO16
EPWM5_A
EPWM5_B
O
O
ePWM-5 Output A
ePWM-5 Output B
GPIO9
GPIO17
GPIO9
GPIO17
GPIO9
GPIO17
GPIO9
GPIO17
GPIO10
GPIO10
GPIO10
GPIO18_X
2
EPWM6_A
O
ePWM-6 Output A
GPIO18_X GPIO18_X GPIO18_X
2
2
2
EPWM6_B
EPWM7_A
O
O
ePWM-6 Output B
ePWM-7 Output A
GPIO11
GPIO11
GPIO11
GPIO11
GPIO12
GPIO28
GPIO12
GPIO28
GPIO12
GPIO28
GPIO28
GPIO29
GPIO24
GPIO32
GPIO13
GPIO29
GPIO13
GPIO29
GPIO13
GPIO29
EPWM7_B
EPWM8_A
EPWM8_B
O
O
O
ePWM-7 Output B
ePWM-8 Output A
ePWM-8 Output B
GPIO14
GPIO24
GPIO24
GPIO32
GPIO24
GPIO32
GPIO15
GPIO32
GPIO6
GPIO10
GPIO28
GPIO6
GPIO10
GPIO6
GPIO10
GPIO28
GPIO6
GPIO28
GPIO35/T
DI
EQEP1_A
EQEP1_B
I
I
eQEP-1 Input A
eQEP-1 Input B
GPIO35/T GPIO28
DI
GPIO40
GPIO56
GPIO35/T GPIO35/T
DI
DI
GPIO7
GPIO11
GPIO29
GPIO37/T
DO
GPIO7
GPIO11
GPIO29
GPIO7
GPIO11
GPIO29
GPIO7
GPIO11
GPIO29
GPIO37/T GPIO37/T GPIO37/T
DO DO DO
GPIO57
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
41
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
56 RSH
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
Table 6-7. Digital Signals by GPIO (continued)
SIGNAL NAME
PIN TYPE
DESCRIPTION
100 PZ
64 PMQ
64 PM
GPIO9
GPIO13
GPIO17
GPIO31
GPIO59
GPIO9
GPIO13
GPIO17
GPIO9
GPIO13
GPIO17
GPIO9
GPIO17
EQEP1_INDEX
I/O
eQEP-1 Index
GPIO8
GPIO12
GPIO16
GPIO22_V
FBSW
GPIO8
GPIO12
GPIO16
GPIO22_V GPIO22_V
FBSW FBSW
GPIO8
GPIO12
GPIO16
GPIO8
GPIO16
GPIO22_V
FBSW
EQEP1_STROBE
EQEP2_A
I/O
eQEP-1 Strobe
eQEP-2 Input A
GPIO30
GPIO58
GPIO14
GPIO18_X
2
GPIO18_X GPIO18_X GPIO18_X
I
2
2
2
GPIO24
GPIO24
GPIO24
GPIO24
GPIO15
GPIO25
EQEP2_B
I
eQEP-2 Input B
eQEP-2 Index
GPIO26
GPIO29
GPIO57
EQEP2_INDEX
I/O
GPIO29
GPIO28
GPIO29
GPIO28
GPIO29
GPIO28
GPIO27
GPIO28
GPIO56
EQEP2_STROBE
ERRORSTS
I/O
O
eQEP-2 Strobe
GPIO24
GPIO28
GPIO29
GPIO24
GPIO28
GPIO29
GPIO24
GPIO28
GPIO29
GPIO24
GPIO28
GPIO29
Error Status Output. This signal requires an
external pullup.
GPIO4
GPIO13
GPIO33
GPIO39
GPIO4
GPIO13
GPIO33
GPIO4
GPIO13
GPIO33
GPIO4
GPIO33
FSIRXA_CLK
FSIRXA_D0
I
I
FSIRX-A Input Clock
GPIO3
GPIO12
GPIO32
GPIO40
GPIO3
GPIO12
GPIO32
GPIO3
GPIO12
GPIO32
GPIO3
GPIO32
FSIRX-A Primary Data Input
GPIO2
GPIO11
GPIO31
GPIO2
GPIO11
GPIO2
GPIO11
GPIO2
GPIO11
FSIRXA_D1
FSITXA_CLK
FSITXA_D0
FSITXA_D1
I
FSIRX-A Optional Additional Data Input
FSITX-A Output Clock
GPIO7
GPIO10
GPIO27
GPIO7
GPIO10
GPIO7
GPIO10
O
O
O
GPIO7
GPIO6
GPIO9
GPIO26
GPIO6
GPIO9
GPIO6
GPIO9
GPIO6
GPIO9
FSITX-A Primary Data Output
GPIO5
GPIO8
GPIO25
GPIO5
GPIO8
GPIO5
GPIO8
GPIO5
GPIO8
FSITX-A Optional Additional Data Output
GPIO1
GPIO8
GPIO18_X
2
GPIO27
GPIO33
GPIO37/T
DO
GPIO1
GPIO8
GPIO1
GPIO8
GPIO1
GPIO8
GPIO18_X GPIO18_X GPIO18_X
I2CA_SCL
I/OD
I2C-A Open-Drain Bidirectional Clock
2
2
2
GPIO33
GPIO33
GPIO33
GPIO37/T GPIO37/T GPIO37/T
DO DO DO
Copyright © 2021 Texas Instruments Incorporated
42
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
Table 6-7. Digital Signals by GPIO (continued)
SIGNAL NAME
PIN TYPE
DESCRIPTION
100 PZ
64 PMQ
64 PM
56 RSH
GPIO0
GPIO10
GPIO26
GPIO32
GPIO35/T
DI
GPIO0
GPIO10
GPIO32
GPIO0
GPIO10
GPIO32
GPIO0
GPIO32
GPIO35/T
DI
I2CA_SDA
LINA_RX
I/OD
I2C-A Open-Drain Bidirectional Data
GPIO35/T GPIO35/T
DI
DI
GPIO29
GPIO33
GPIO35/T
DI
GPIO29
GPIO33
GPIO29
GPIO33
GPIO29
GPIO33
I
LIN-A Receive
LIN-A Transmit
GPIO35/T GPIO35/T GPIO35/T
DI DI DI
GPIO59
GPIO22_V
FBSW
GPIO28
GPIO32
GPIO37/T
DO
GPIO22_V GPIO22_V GPIO22_V
FBSW
GPIO28
GPIO32
FBSW
GPIO28
GPIO32
FBSW
GPIO28
GPIO32
LINA_TX
O
GPIO37/T GPIO37/T GPIO37/T
DO
DO
DO
GPIO58
GPIO2
GPIO24
GPIO34
GPIO58
GPIO2
GPIO24
GPIO2
GPIO24
GPIO2
GPIO24
OUTPUTXBAR1
OUTPUTXBAR2
O
O
Output X-BAR Output 1
Output X-BAR Output 2
GPIO3
GPIO25
GPIO3
GPIO3
GPIO3
GPIO37/T GPIO37/T GPIO37/T GPIO37/T
DO
DO
DO
DO
GPIO59
GPIO4
GPIO5
GPIO14
GPIO26
GPIO4
GPIO5
GPIO4
GPIO5
GPIO4
GPIO5
OUTPUTXBAR3
OUTPUTXBAR4
O
O
Output X-BAR Output 3
Output X-BAR Output 4
GPIO6
GPIO15
GPIO27
GPIO33
GPIO6
GPIO33
GPIO6
GPIO33
GPIO6
GPIO33
GPIO7
GPIO28
GPIO7
GPIO28
GPIO7
GPIO28
GPIO7
GPIO28
OUTPUTXBAR5
OUTPUTXBAR6
O
O
Output X-BAR Output 5
Output X-BAR Output 6
GPIO9
GPIO29
GPIO9
GPIO29
GPIO9
GPIO29
GPIO9
GPIO29
GPIO11
GPIO16
GPIO30
GPIO11
GPIO16
GPIO11
GPIO16
GPIO11
GPIO16
OUTPUTXBAR7
OUTPUTXBAR8
O
O
Output X-BAR Output 7
Output X-BAR Output 8
GPIO17
GPIO31
GPIO17
GPIO17
GPIO13
GPIO17
GPIO13
GPIO13
GPIO27 GPIO37/T
GPIO37/T
DO
PMBUSA_ALERT
PMBUSA_CTL
I/OD
PMBus-A Open-Drain Bidirectional Alert Signal
PMBus-A Control Signal
GPIO37/T GPIO37/T
DO
DO
DO
GPIO12
GPIO18_X GPIO18_X
GPIO12
GPIO18_X GPIO18_X
GPIO12
2
2
I
2
2
GPIO26 GPIO35/T
GPIO35/T
DI
GPIO35/T GPIO35/T
DI
DI
DI
GPIO3
GPIO15
GPIO16
GPIO24
GPIO35/T
DI
GPIO3
GPIO16
GPIO24
GPIO3
GPIO16
GPIO24
GPIO3
GPIO16
GPIO24
PMBUSA_SCL
I/OD
PMBus-A Open-Drain Bidirectional Clock
GPIO35/T GPIO35/T GPIO35/T
DI DI DI
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
43
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
56 RSH
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
Table 6-7. Digital Signals by GPIO (continued)
SIGNAL NAME
PIN TYPE
DESCRIPTION
100 PZ
64 PMQ
64 PM
GPIO2
GPIO14
GPIO17
GPIO25
GPIO34
GPIO40
GPIO2
GPIO17
GPIO2
GPIO17
GPIO2
GPIO17
PMBUSA_SDA
I/OD
PMBus-A Open-Drain Bidirectional Data
GPIO3
GPIO9
GPIO17
GPIO25
GPIO28
GPIO35/T
DI
GPIO3
GPIO9
GPIO17
GPIO28
GPIO3
GPIO9
GPIO17
GPIO28
GPIO3
GPIO9
GPIO17
GPIO28
SCIA_RX
I
SCI-A Receive Data
GPIO35/T GPIO35/T GPIO35/T
DI
DI
DI
GPIO2
GPIO8
GPIO2
GPIO8
GPIO2
GPIO8
GPIO2
GPIO8
GPIO16
GPIO24
GPIO29
GPIO16
GPIO24
GPIO29
GPIO16
GPIO24
GPIO29
GPIO16
GPIO24
GPIO29
SCIA_TX
SCIB_RX
O
SCI-A Transmit Data
SCI-B Receive Data
GPIO37/T GPIO37/T GPIO37/T GPIO37/T
DO
DO
DO
DO
GPIO11
GPIO13
GPIO15
GPIO57
GPIO11
GPIO13
GPIO11
GPIO13
I
GPIO11
GPIO9
GPIO10
GPIO12
GPIO14
GPIO9
GPIO10
GPIO12
GPIO18_X
2
GPIO9
GPIO10
GPIO9
GPIO12
GPIO18_X
2
GPIO22_V
FBSW
GPIO18_X GPIO18_X
SCIB_TX
O
SCI-B Transmit Data
2
2
GPIO22_V GPIO22_V
GPIO22_V
FBSW
FBSW
GPIO40
GPIO56
FBSW
GPIO17
GPIO25
SD1_C1
SD1_C2
I
I
SDFM-1 Channel 1 Clock Input
SDFM-1 Channel 2 Clock Input
GPIO17
GPIO17
GPIO17
GPIO27
GPIO29
GPIO33
GPIO57
GPIO29
GPIO33
GPIO29
GPIO33
GPIO29
GPIO33
SD1_C3
I
SDFM-1 Channel 3 Clock Input
GPIO31
GPIO59
SD1_C4
SD1_D1
I
I
SDFM-1 Channel 4 Clock Input
SDFM-1 Channel 1 Data Input
GPIO16
GPIO24
GPIO16
GPIO24
GPIO16
GPIO24
GPIO16
GPIO24
GPIO18_X
2
GPIO26
GPIO18_X GPIO18_X GPIO18_X
SD1_D2
SD1_D3
I
I
SDFM-1 Channel 2 Data Input
SDFM-1 Channel 3 Data Input
2
2
2
GPIO28
GPIO32
GPIO56
GPIO28
GPIO32
GPIO28
GPIO32
GPIO28
GPIO32
GPIO22_V
FBSW
GPIO30
GPIO58
GPIO22_V GPIO22_V GPIO22_V
SD1_D4
I
SDFM-1 Channel 4 Data Input
SPI-A Clock
FBSW
FBSW
FBSW
GPIO3
GPIO9
GPIO18_X
2
GPIO3
GPIO9
GPIO3
GPIO9
GPIO3
GPIO9
SPIA_CLK
I/O
GPIO18_X GPIO18_X GPIO18_X
2
2
2
GPIO56
Copyright © 2021 Texas Instruments Incorporated
44
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
Table 6-7. Digital Signals by GPIO (continued)
SIGNAL NAME
PIN TYPE
DESCRIPTION
100 PZ
64 PMQ
64 PM
56 RSH
GPIO8
GPIO16
GPIO8
GPIO16
GPIO8
GPIO16
GPIO8
GPIO16
SPIA_SIMO
SPIA_SOMI
I/O
SPI-A Slave In, Master Out (SIMO)
GPIO10
GPIO17
GPIO10
GPIO17
GPIO10
GPIO17
I/O
I/O
SPI-A Slave Out, Master In (SOMI)
SPI-A Slave Transmit Enable (STE)
GPIO17
GPIO5
GPIO11
GPIO57
GPIO5
GPIO11
GPIO5
GPIO11
GPIO5
GPIO11
SPIA_STE
GPIO14
GPIO22_V
FBSW
GPIO26
GPIO28
GPIO32
GPIO58
GPIO22_V GPIO22_V GPIO22_V
FBSW
GPIO28
GPIO32
FBSW
GPIO28
GPIO32
FBSW
GPIO28
GPIO32
SPIB_CLK
I/O
SPI-B Clock
GPIO7
GPIO24
GPIO30
GPIO56
GPIO7
GPIO24
GPIO7
GPIO24
GPIO7
GPIO24
SPIB_SIMO
SPIB_SOMI
I/O
I/O
SPI-B Slave In, Master Out (SIMO)
SPI-B Slave Out, Master In (SOMI)
GPIO6
GPIO25
GPIO31
GPIO57
GPIO6
GPIO6
GPIO6
GPIO15
GPIO27
GPIO29
GPIO33
GPIO59
GPIO29
GPIO33
GPIO29
GPIO33
GPIO29
GPIO33
SPIB_STE
SYNCOUT
I/O
O
SPI-B Slave Transmit Enable (STE)
External ePWM Synchronization Pulse
GPIO6
GPIO6
GPIO6
GPIO6
JTAG Test Data Input (TDI) - TDI is the default
mux selection for the pin. The internal pullup is
disabled by default. The internal pullup should
be enabled or an external pullup added on the
board if this pin is used as JTAG TDI to avoid a
floating input.
GPIO35/T GPIO35/T GPIO35/T GPIO35/T
DI DI DI DI
TDI
I
JTAG Test Data Output (TDO) - TDO is the
default mux selection for the pin. The internal
pullup is disabled by default. The TDO function
will be in a tri-state condition when there is no
JTAG activity, leaving this pin floating; the
internal pullup should be enabled or an external
pullup added on the board to avoid a floating
GPIO input.
GPIO37/T GPIO37/T GPIO37/T GPIO37/T
DO DO DO DO
TDO
O
Internal DC-DC regulator feedback signal. If the
internal DC-DC regulator is used, tie this pin to GPIO22_V GPIO22_V GPIO22_V GPIO22_V
VFBSW
-
the node where L(VSW) connects to the VDD
rail (as close as possible to the device).
FBSW
FBSW
FBSW
FBSW
Switching output of the internal DC-DC
regulator
GPIO23_V GPIO23_V GPIO23_V GPIO23_V
SW SW SW SW
VSW
X2
-
GPIO18_X GPIO18_X GPIO18_X GPIO18_X
I/O
Crystal oscillator output
2
2
2
2
External Clock Output. This pin outputs a
GPIO16
GPIO16
GPIO16
GPIO16
XCLKOUT
O
divided-down version of a chosen clock signal GPIO18_X GPIO18_X GPIO18_X GPIO18_X
from within the device.
2
2
2
2
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
45
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
6.4.2 Digital Inputs on ADC Pins (AIOs)
GPIOs on port H (GPIO224–GPIO255) are multiplexed with analog pins. These are also referred to as AIOs.
These pins can only function in input mode. By default, these pins will function as analog pins and the GPIOs
are in a high-Z state. The GPHAMSEL register is used to configure these pins for digital or analog operation.
Note
If digital signals with sharp edges (high dv/dt) are connected to the AIOs, cross-talk can occur with
adjacent analog signals. The user should therefore limit the edge rate of signals connected to AIOs if
adjacent channels are being used for analog functions.
6.4.3 GPIO Input X-BAR
The Input X-BAR is used to route signals from a GPIO to many different IP blocks such as the ADCs, eCAPs,
ePWMs, and external interrupts (see Figure 6-5). Table 6-8 lists the input X-BAR destinations. For details on
configuring the Input X-BAR, see the Crossbar (X-BAR) chapter of the TMS320F28004x Microcontrollers
Technical Reference Manual.
GPIO0
Asynchronous
Synchronous
Sync. + Qual.
eCAP1
eCAP2
eCAP3
eCAP4
eCAP5
eCAP6
eCAP7
Input X-BAR
GPIOx
Other Sources
INPUT[16:1]
127:16
15:0
TZ1,TRIP1
TZ2,TRIP2
TZ3,TRIP3
TRIP6
XINT1
TRIP4
TRIP5
XINT2
XINT3
XINT4
XINT5
ePWM
Modules
CPU PIE
CLA
TRIP7
TRIP8
TRIP9
TRIP10
TRIP11
TRIP12
ePWM
X-BAR
Other
Sources
ADCEXTSOC
ADC
EXTSYNCIN1
EXTSYNCIN2
ePWM and eCAP
Sync Chain
Other Sources
Output X-BAR
Figure 6-5. Input X-BAR
Copyright © 2021 Texas Instruments Incorporated
46
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
Table 6-8. Input X-BAR Destinations
INPUT
INPUT1
INPUT2
INPUT3
INPUT4
DESTINATIONS
eCAPx, ePWM X-BAR, ePWM[TZ1,TRIP1], Output X-BAR
eCAPx, ePWM X-BAR, ePWM[TZ2,TRIP2], Output X-BAR
eCAPx, ePWM X-BAR, ePWM[TZ3,TRIP3], Output X-BAR
eCAPx, ePWM X-BAR, XINT1, Output X-BAR
eCAPx, ePWM X-BAR, XINT2, ADCEXTSOC, EXTSYNCIN1, Output
X-BAR
INPUT5
INPUT6
eCAPx, ePWM X-BAR, XINT3, ePWM[TRIP6], EXTSYNCIN2,
Output X-BAR
INPUT7
INPUT8
eCAPx, ePWM X-BAR
eCAPx, ePWM X-BAR
eCAPx, ePWM X-BAR
eCAPx, ePWM X-BAR
eCAPx, ePWM X-BAR
eCAPx, ePWM X-BAR
eCAPx, ePWM X-BAR, XINT4
eCAPx, ePWM X-BAR, XINT5
eCAPx
INPUT9
INPUT10
INPUT11
INPUT12
INPUT13
INPUT14
INPUT15
INPUT16
eCAPx
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
47
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
6.4.4 GPIO Output X-BAR and ePWM X-BAR
The Output X-BAR has eight outputs which are routed to the GPIO module. The ePWM X-BAR has eight outputs
which are routed to each ePWM module. Figure 6-6 shows the sources for both the Output X-BAR and ePWM
X-BAR. For details on the Output X-BAR and ePWM X-BAR, see the Crossbar (X-BAR) chapter of the
TMS320F28004x Microcontrollers Technical Reference Manual.
CTRIPOUTH
CTRIPOUTL
(Output X-BAR only)
CMPSSx
CTRIPH
CTRIPL
(ePWM X-BAR only)
ePWM and eCAP
EXTSYNCOUT
Sync Chain
OUTPUT1
OUTPUT2
OUTPUT3
ADCSOCAO
Select Ckt
ADCSOCAO
GPIO
Mux
OUTPUT4
OUTPUT5
OUTPUT6
OUTPUT7
OUTPUT8
Output
X-BAR
ADCSOCBO
Select Ckt
ADCSOCBO
ECAPxOUT
eCAPx
ADCx
EVT1
EVT2
EVT3
EVT4
TRIP4
TRIP5
TRIP7
TRIP8
TRIP9
TRIP10
TRIP11
TRIP12
All
ePWM
Modules
ePWM
X-BAR
INPUT1-6
Input X-BAR
CLAHALT
INPUT7-14
(ePWM X-BAR only)
CLAHALT
FLT1.COMPH
FLT1.COMPL
X-BAR Flags
(shared)
SDFMx
FLT4.COMPH
FLT4.COMPL
Figure 6-6. Output X-BAR and ePWM X-BAR Sources
Copyright © 2021 Texas Instruments Incorporated
48
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
6.5 Pins With Internal Pullup and Pulldown
Some pins on the device have internal pullups or pulldowns. Table 6-9 lists the pull direction and when it is
active. The pullups on GPIO pins are disabled by default and can be enabled through software. To avoid any
floating unbonded inputs, the Boot ROM will enable internal pullups on GPIO pins that are not bonded out in a
particular package. Other pins noted in Table 6-9 with pullups and pulldowns are always on and cannot be
disabled.
Table 6-9. Pins With Internal Pullup and Pulldown
RESET
(XRSn = 0)
PIN
DEVICE BOOT
APPLICATION
GPIOx (including AIOs)
GPIO35/TDI
GPIO37/TDO
TCK
Pullup disabled
Pullup disabled(1)
Application defined
Application defined
Application defined
Pullup disabled
Pullup disabled
Pullup active
Pullup active
Pulldown active
Pullup active
TMS
VREGENZ
XRSn
Other pins
No pullup or pulldown present
(1) Pins not bonded out in a given package will have the internal pullups enabled by the Boot ROM.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
49
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
6.6 Connections for Unused Pins
For applications that do not need to use all functions of the device, Table 6-10 lists acceptable conditioning for
any unused pins. When multiple options are listed in Table 6-10, any option is acceptable. Pins not listed in Table
6-10 must be connected according to Section 6.
Table 6-10. Connections for Unused Pins
SIGNAL NAME
ACCEPTABLE PRACTICE
ANALOG
•
•
No Connect
Analog input pins with
DACx_OUT
Tie to VSSA through 4.7-kΩ or larger resistor
•
•
No Connect
Analog input pins with
PGAx_OUTF
Tie to VSSA through 4.7-kΩ or larger resistor
•
•
•
No Connect
Analog input pins (except for
DACx_OUT and PGAx_OUTF)
Tie to VSSA
Tie to VSSA through resistor
PGAx_GND
VREFHIx
Tie to VSSA
Tie to VDDA (applies only if ADC or DAC are not used in the application)
VREFLOx
Tie to VSSA
DIGITAL
•
•
No Connect
FLT1 (Flash Test pin 1)
FLT2 (Flash Test pin 2)
Tie to VSS through 4.7-kΩ or larger resistor
•
•
No Connect
Tie to VSS through 4.7-kΩ or larger resistor
•
•
•
No connection (input mode with internal pullup enabled)
No connection (output mode with internal pullup disabled)
GPIOx
Pullup or pulldown resistor (any value resistor, input mode, and with internal pullup disabled)
When TDI mux option is selected (default), the GPIO is in Input mode.
•
•
Internal pullup enabled
External pullup resistor
GPIO35/TDI
When TDO mux option is selected (default), the GPIO is in Output mode only during JTAG activity;
otherwise, it is in a tri-state condition. The pin must be biased to avoid extra current on the input buffer.
GPIO37/TDO
TCK
•
•
Internal pullup enabled
External pullup resistor
•
•
No Connect
Pullup resistor
TMS
Pullup resistor
VREGENZ
X1
Tie to VDDIO if internal regulator is not used
Tie to VSS
X2
No Connect
POWER AND GROUND
VDD
All VDD pins must be connected per Section 6.3.
If a dedicated analog supply is not used, tie to VDDIO.
All VDDIO pins must be connected per Section 6.3.
Always tie to VDDIO.
VDDA
VDDIO
VDDIO_SW
VSS
All VSS pins must be connected to board ground.
Always tie to VSS.
VSS_SW
VSSA
If an analog ground is not used, tie to VSS.
Copyright © 2021 Texas Instruments Incorporated
50
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
7 Specifications
7.1 Absolute Maximum Ratings (1) (2)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.3
–0.3
–0.3
MAX
4.6
UNIT
VDDIO with respect to VSS
Supply voltage
VDDA with respect to VSSA
VDD with respect to VSS
4.6
V
1.5
Voltage difference between VDDIO and
VDDIO_SW pins
±0.3
V
Input voltage
VIN (3.3 V)
–0.3
–0.3
–20
4.6
4.6
20
V
V
Output voltage
VO
Digital/analog input (per pin), IIK (VIN < VSS or VIN > VDDIO)
Analog input (per pin), IIKANALOG
(VIN < VSSA or VIN > VDDA)
–20
–20
20
20
Input clamp current(4)
mA
Total for all inputs, IIKTOTAL
(VIN < VSS/VSSA or VIN > VDDIO/VDDA)
Output current
Digital output (per pin), IOUT
–20
–40
–40
–65
20
125
150
150
mA
°C
°C
°C
Free-Air temperature
Operating junction temperature
Storage temperature(3)
TA
TJ
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 7.4 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
(3) Long-term high-temperature storage or extended use at maximum temperature conditions may result in a reduction of overall device
life. For additional information, see the Semiconductor and IC Package Thermal Metrics Application Report.
(4) Continuous clamp current per pin is ±2 mA. Do not operate in this condition continuously as VDDIO/VDDA voltage may internally rise and
impact other electrical specifications.
7.2 ESD Ratings – Commercial
VALUE
UNIT
F28004x in 100-pin PZ package (S temperature range)
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
±2000
±500
Electrostatic discharge
(ESD)
V(ESD)
V
Charged-device model (CDM), per JEDEC specification
JESD22-C101 or ANSI/ESDA/JEDEC JS-002(2)
F28004x in 64-pin PM package (S temperature range)
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
±2000
±500
Electrostatic discharge
(ESD)
V(ESD)
V
V
Charged-device model (CDM), per JEDEC specification
JESD22-C101 or ANSI/ESDA/JEDEC JS-002(2)
F28004x in 56-pin RSH package (S temperature range)
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
±2000
±500
Electrostatic discharge
(ESD)
V(ESD)
Charged-device model (CDM), per JEDEC specification
JESD22-C101 or ANSI/ESDA/JEDEC JS-002(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 ESD Ratings – Automotive
VALUE
UNIT
F28004x in 100-pin PZ package (Q temperature range)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
51
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
UNIT
VALUE
Human body model (HBM), per
AEC Q100-002(1)
All pins
All pins
±2000
V(ESD)
Electrostatic discharge
Charged device model (CDM),
per AEC Q100-011
±500
±750
V
Corner pins on 100-pin PZ:
1, 25, 26, 50, 51, 75, 76, 100
F28004x in 64-pin PM package (Q temperature range)
Human body model (HBM), per
All pins
All pins
±2000
AEC Q100-002(1)
V(ESD)
Electrostatic discharge
Charged device model (CDM),
per AEC Q100-011
±500
±750
V
Corner pins on 64-pin PM:
1, 16, 17, 32, 33, 48, 49, 64
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.4 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
VBOR-VDDIO(MAX) + VBOR-
Internal BOR enabled(3)
Internal BOR disabled
3.3
3.63
(2)
GB
Device supply voltage, VDDIO and VDDA
V
2.8
3.3
1.2
0
3.63
1.32
Device supply voltage, VDD
Device ground, VSS
1.14
V
V
V
Analog ground, VSSA
0
Supply ramp rate of VDDIO, VDD,
VDDA with respect to VSS.(4)
SRSUPPLY
105
10
V/s
ms
VDDIO supply ramp time from
1 V to VBOR-VDDIO(MAX)
tVDDIO-RAMP
VBOR-GB
VDDIO BOR guard band(5)
S version(1)
0.1
V
Junction temperature, TJ
–40
–40
125
125
°C
Q version(1)
(AEC Q100 qualification)
Free-Air temperature, TA
°C
(1) Operation above TJ = 105°C for extended duration will reduce the lifetime of the device.
See CalculatingUsefulLifetimesofEmbeddedProcessors for more information.
(2) The VDDIO BOR voltage (VBOR-VDDIO[MAX]) in Electrical Characteristics determines the lower voltage bound for device operation. TI
recommends that system designers budget an additional guard band (VBOR-GB) as shown in Figure 7-1.
(3) Internal BOR is enabled by default.
(4) Supply ramp rate faster than this can trigger the on-chip ESD protection.
(5) TI recommends VBOR-GB to avoid BOR resets due to normal supply noise or load-transient events on the 3.3-V VDDIO system
regulator. Good system regulator design and decoupling capacitance (following the system regulator specifications) are important to
prevent activation of the BOR during normal device operation. The value of VBOR-GB is a system-level design consideration; the voltage
listed here is typical for many applications.
Copyright © 2021 Texas Instruments Incorporated
52
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
3.63 V
+10%
Recommended
System Voltage
Regulator Range
3.3 V
0%
F28004x
VDDIO
Operating
Range
3.1 V
3.0 V
–6.1%
–9.1%
VBOR-GB
BOR Guard Band
VBOR-VDDIO
Internal BOR Threshold
–14.8%
–15.1%
2.81 V
2.80 V
Copyright © 2017, Texas Instruments Incorporated
Figure 7-1. Supply Voltages
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
53
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
7.5 Power Consumption Summary
Current values listed in this section are representative for the test conditions given and not the absolute
maximum possible. The actual device currents in an application will vary with application code and pin
configurations. Section 7.5.1 lists the system current consumption values for an external supply. Section 7.5.2
lists the system current consumption values for the internal VREG. Section 7.5.3 lists the system current
consumption values for the DCDC. See Section 7.5.4 for a detailed description of the test case run while
measuring the current consumption in operating mode.
7.5.1 System Current Consumption (External Supply)
over operating free-air temperature range (unless otherwise noted).
TYP : Vnom, 30℃
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPERATING MODE
VDD current consumption during
operational usage(1)
IDD
61
26
12
90
45
30
mA
mA
mA
VDDIO current consumption during
operational usage
IDDIO
See Section 7.5.4.
VDDA current consumption during
operational usage
IDDA
IDLE MODE
IDD
VDD current consumption while device
is in Idle mode(1)
18
1.2
0.9
40
4
mA
mA
mA
•
•
•
CPU is in IDLE mode
Flash is powered down
XCLKOUT is turned off
VDDIO current consumption while
device is in Idle mode
IDDIO
VDDA current consumption while
device is in Idle mode
IDDA
1.2
HALT MODE
VDD current consumption while device
is in Halt mode(1)
IDD
0.9
0.8
0.2
20
4
mA
mA
mA
•
•
•
CPU is in HALT mode
Flash is powered down
XCLKOUT is turned off
VDDIO current consumption while
device is in Halt mode
IDDIO
IDDA
VDDA current consumption while
device is in Halt mode
0.5
FLASH ERASE/PROGRAM
VDD Current consumption during
•
CPU is running from Flash,
performing Erase and
Program on the unused
sector.
IDD
40
70
mA
Erase/Program cycle(1) (2)
VDDIO Current consumption during
Erase/Program cycle(2)
IDDIO
IDDA
33
75
mA
mA
•
•
VREG is disabled.
VDDA Current consumption during
Erase/Program cycle
0.1
2.5
SYSCLK is running at 100
MHz.
•
•
I/Os are inputs with pullups
enabled.
Peripheral clocks are turned
OFF.
(1) IDD MAX is reported with VDD at MAX Recommended Operating Conditions. For the Internal VREG and DCDC tables this VDD
supply will be at the regulated VDD TYP voltage. For this reason, current values reported in this External Supply Table will appear
elevated compared to the Internal VREG and DCDC tables.
(2) Brownout events during flash programming can corrupt flash data and permanently lock the device. Programming environments using
alternate power sources (such as a USB programmer) must be capable of supplying the rated current for the device and other system
components with sufficient margin to avoid supply brownout conditions.
Copyright © 2021 Texas Instruments Incorporated
54
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
7.5.2 System Current Consumption (Internal VREG)
over operating free-air temperature range (unless otherwise noted).
TYP : Vnom, 30℃
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPERATING MODE
VDDIO current consumption during
operational usage
IDDIO
86
12
113
30
mA
mA
See Section 7.5.4.
VDDA current consumption during
operational usage
IDDA
IDLE MODE
IDDIO
VDDIO current consumption while
device is in Idle mode
•
•
•
CPU is in IDLE mode
Flash is powered down
XCLKOUT is turned off
19.2
0.9
36
mA
mA
VDDA current consumption while
device is in Idle mode
IDDA
1.2
HALT MODE
IDDIO
VDDIO current consumption while
device is in Halt mode
•
•
•
CPU is in HALT mode
Flash is powered down
XCLKOUT is turned off
1.7
0.2
18
mA
mA
VDDA current consumption while
device is in Halt mode
IDDA
0.5
FLASH ERASE/PROGRAM
IDDIO
VDDIO current consumption during
•
CPU is running from Flash,
performing Erase and
Program on the unused
sector.
72
106
2.5
mA
mA
Erase/Program cycle(1)
IDDA
VDDA current consumption during
Erase/Program cycle
0.1
•
•
Internal VREG is enabled.
SYSCLK is running at 100
MHz.
•
•
I/Os are inputs with pullups
enabled.
Peripheral clocks are turned
OFF.
(1) Brownout events during flash programming can corrupt flash data and permanently lock the device. Programming environments using
alternate power sources (such as a USB programmer) must be capable of supplying the rated current for the device and other system
components with sufficient margin to avoid supply brownout conditions.
7.5.3 System Current Consumption (DCDC)
over operating free-air temperature range (unless otherwise noted).
TYP : Vnom, 30℃
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPERATING MODE
VDDIO current consumption during
operational usage
IDDIO
52
12
70
30
mA
mA
See Section 7.5.4.
VDDA current consumption during
operational usage
IDDA
IDLE MODE
IDDIO
VDDIO current consumption while
device is in Idle mode
•
•
•
CPU is in IDLE mode
Flash is powered down
XCLKOUT is turned off
9.2
0.9
28
mA
mA
VDDA current consumption while
device is in Idle mode
IDDA
1.5
HALT MODE
IDDIO
VDDIO current consumption while
device is in Halt mode
•
•
•
CPU is in HALT mode
Flash is powered down
XCLKOUT is turned off
1.7
0.2
17
mA
mA
VDDA current consumption while
device is in Halt mode
IDDA
1.5
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
55
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
UNIT
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
over operating free-air temperature range (unless otherwise noted).
TYP : Vnom, 30℃
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
FLASH ERASE/PROGRAM
VDDIO current consumption during
Erase/Program cycle(1)
•
CPU is running from Flash,
performing Erase and
Program on the unused
sector.
IDDIO
IDDA
60
85
mA
mA
VDDA current consumption during
Erase/Program cycle
0.25
2.5
•
•
DCDC is enabled.
SYSCLK is running at 100
MHz.
•
•
I/Os are inputs with pullups
enabled.
Peripheral clocks are turned
OFF.
(1) Brownout events during flash programming can corrupt flash data and permanently lock the device. Programming environments using
alternate power sources (such as a USB programmer) must be capable of supplying the rated current for the device and other system
components with sufficient margin to avoid supply brownout conditions.
Copyright © 2021 Texas Instruments Incorporated
56
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
7.5.4 Operating Mode Test Description
Section 7.5.1, Section 7.5.2, and Section 7.5.3 list the current consumption values for the operational mode of
the device. The operational mode provides an estimation of what an application might encounter. The test case
run to achieve the values shown does the following in a loop. Peripherals that are not on the following list have
had their clocks disabled.
•
•
•
•
Code is executing from RAM.
FLASH is read and kept in active state.
No external components are driven by I/O pins.
All of the communication peripherals are exercised: SPI-A to SPI-C; SCI-A to SCI-C; I2C-A; CAN-A to CAN-
C; LIN-A; PMBUS-A; and FSI-A.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
ePWM-1 to ePWM-3 generate a 5-MHz output on 6 pins.
ePWM-4 to ePWM-7 are in HRPWM mode and generating 25 MHz on 6 pins.
CPU timers are active.
CPU does FIR16 calculations.
DMA does continuous 32-bit transfers.
CLA-1 is executing a 1024-point DFT in a background task.
All ADCs perform continuous conversions.
All DACs vary voltage at the loop frequency ~11 kHz.
All PGAs are enabled.
All CMPSSs generate a square wave with a 100-kHz frequency.
SDFM peripheral clock is enabled.
eCAP-1 to eCAP-7 are in APWM mode, toggling at 250 kHz.
All eQEP watchdogs are enabled and counting.
System watchdog is enabled and counting.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
57
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
7.5.5 Current Consumption Graphs
Figure 7-2, Figure 7-3, and Figure 7-4 show a typical representation of the relationship between frequency and
current consumption on the device. The operational test from Section 7.5.1 was run across frequency at VNOM
and room temperature. Actual results will vary based on the system implementation and conditions.
Leakage current on the VDD core supply will increase with operating temperature in an exponential manner as
seen in Figure 7-5. The current consumption in HALT mode is primarily leakage current as there is no active
switching if the internal oscillator has been powered down.
Figure 7-5 shows the typical leakage current across temperature. The device was placed into HALT mode under
nominal voltage conditions.
65
60
55
50
45
40
35
30
25
20
15
10
5
100
80
60
40
20
0
IDDIO
IDDA
IDD
IDDIO
IDDA
0
0
10
20
30
40
50
60
70
80
90
100
0
10
20
30
40
50
60
70
80
90
100
Frequency (MHz)
Frequency (MHz)
D002
D001
Figure 7-3. Current Versus Frequency — Internal
VREG
Figure 7-2. Current Versus Frequency — External
Supply
55
22
20
18
16
14
12
10
8
50
IDDIO
IDDA
45
40
35
30
25
20
15
10
5
6
4
2
0
0
10
20
30
40
50
60
70
80
90
100
-60
-40
-20
0
20
40
60
80
100
120
140
160
Frequency (MHz)
Temperature (èC)
D003
D004
Figure 7-4. Current Versus Frequency — DCDC
Figure 7-5. Halt Current Versus Temperature (°C)
Copyright © 2021 Texas Instruments Incorporated
58
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
7.5.6 Reducing Current Consumption
All C2000™ microcontrollers provide some methods to reduce the device current consumption:
•
Either of the two low-power modes—IDLE and HALT—could be entered to reduce the current consumption
even further during idle periods in the application.
•
•
•
The flash module may be powered down if the code is run from RAM.
Disable the pullups on pins that assume an output function.
Each peripheral has an individual clock-enable bit (PCLKCRx). Reduced current consumption may be
achieved by turning off the clock to any peripheral that is not used in a given application. Section 7.5.6.1 lists
the typical current consumption value per peripheral at 100-MHz SYSCLK.
To realize the lowest VDDA current consumption in an LPM, see the respective analog chapter of the
TMS320F28004x Microcontrollers Technical Reference Manual to ensure each module is powered down as
well.
•
7.5.6.1 Typical IDD Current Reduction per Disabled Peripheral (at 100-MHz SYSCLK) (1)
IDD CURRENT REDUCTION
PERIPHERAL
(mA)
ADC(2)
0.8
1.1
0.4
1.1
0.4
0.1
0.2
0.5
0.1
0.4
0.7
0.1
0.7
0.8
0.3
0.4
0.2
0.3
0.2
0.9
0.2
0.1
22.9
CAN
CLA
CLB
CMPSS(2)
CPU TIMER
DAC(2)
DMA
eCAP1 to eCAP5
eCAP6 to eCAP7(3)
ePWM
eQEP
FSI
HRPWM
I2C
LIN
PGA(2)
PMBUS
SCI
SDFM
SPI
DCC
PLL at 100 MHz
(1) All peripherals are disabled upon reset. Use the PCLKCRx
register to individually enable peripherals. For peripherals with
multiple instances, the current quoted is for a single module.
(2) This current represents the current drawn by the digital portion
of the each module.
(3) eCAP6 and eCAP7 can also be configured as HRCAP.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
59
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
7.6 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
MIN
TYP
MAX UNIT
Digital and Analog IO
IOH = IOH MIN
IOH = –100 μA
IOL = IOL MAX
IOL = 100 µA
VDDIO * 0.8
VDDIO – 0.2
VOH
High-level output voltage
Low-level output voltage
V
0.4
V
VOL
0.2
IOH
High-level output source current for all output pins
Low-level output sink current for all output pins
High-level output impedance for all output pins
Low-level output impedance for all output pins
High-level input voltage (3.3 V)
–4
mA
IOL
4
mA
Ω
ROH
70
70
ROL
Ω
VIH
2.0
VDDIO + 0.3
0.8
V
VIL
Low-level input voltage (3.3 V)
VSS – 0.3
V
VHYSTERESIS
Input hysteresis
150
100
mV
VDDIO = 3.3 V
VIN = VDDIO
IPULLDOWN
Input current
Input current
Inputs with pulldown(1)
µA
µA
Digital inputs with pullup VDDIO = 3.3 V
160
160
enabled(1)
VIN = 0 V
IPULLUP
Analog inputs with
pullup enabled(1)
VDDA = 3.3 V
VIN = 0 V
All GPIOs except
GPIO23_VSW
Pullups and outputs
disabled
2
0 V ≤ VIN ≤ VDDIO
GPIO23_VSW
45
Analog pins (except
ADCINB3/VDAC and
PGAx_OF)
ILEAK
Pin leakage
µA
pF
0.1
Analog drivers
disabled
0 V ≤ VIN ≤ VDDA
ADCINB3/VDAC
PGAx_OF
2
11
0.25
All digital GPIOs except
GPIO23_VSW
2
CI
Input capacitance
GPIO23_VSW
Analog pins(2)
100
VREG, DC-DC, and BOR
VPOR-VDDIO
VBOR-VDDIO
VVREG
VDDIO power on reset voltage
VDDIO brown out reset voltage
2.3
V
V
V
V
2.81
80%
3.0
Internal voltage regulator output
Internal switching regulator output
Internal VREG On
Internal DC-DC On
1.2
1.2
VDC-DC
Power efficiency of internal DC-DC switching
regulator
Efficiency
(1) See Table 6-9 for a list of pins with a pullup or pulldown.
(2) The analog pins are specified separately; see Table 7-15.
Copyright © 2021 Texas Instruments Incorporated
60
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
7.7 Thermal Resistance Characteristics
7.7.1 PZ Package
°C/W(1)
7.6
AIR FLOW (lfm)(2)
RΘJC
Junction-to-case thermal resistance
Junction-to-board thermal resistance
Junction-to-free air thermal resistance
N/A
N/A
0
RΘJB
24.2
46.1
37.3
34.8
32.6
0.2
RΘJA (High k PCB)
150
250
500
0
RΘJMA
Junction-to-moving air thermal resistance
0.4
150
250
500
0
PsiJT
Junction-to-package top
0.4
0.6
23.8
22.8
22.4
21.9
150
250
500
PsiJB
Junction-to-board
(1) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(2) lfm = linear feet per minute
7.7.2 PM Package
°C/W(1)
12.4
25.6
51.8
42.2
39.4
36.5
0.5
AIR FLOW (lfm)(2)
RΘJC
Junction-to-case thermal resistance
N/A
N/A
0
RΘJB
Junction-to-board thermal resistance
Junction-to-free air thermal resistance
RΘJA (High k PCB)
150
250
500
0
RΘJMA
Junction-to-moving air thermal resistance
0.9
150
250
500
0
PsiJT
Junction-to-package top
1.1
1.4
25.1
23.8
23.4
22.7
150
250
500
PsiJB
Junction-to-board
(1) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
61
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
(2) lfm = linear feet per minute
Copyright © 2021 Texas Instruments Incorporated
62
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
7.7.3 RSH Package
°C/W(1)
11.9
3.3
AIR FLOW (lfm)(2)
RΘJC
Junction-to-case thermal resistance
Junction-to-board thermal resistance
Junction-to-free air thermal resistance
N/A
N/A
0
RΘJB
RΘJA (High k PCB)
25.8
17.4
15.1
13.4
0.2
150
250
500
0
RΘJMA
Junction-to-moving air thermal resistance
0.3
150
250
500
0
PsiJT
Junction-to-package top
0.4
0.4
3.3
3.2
150
250
500
0
PsiJB
Junction-to-board
3.2
3.2
RΘJC, bottom
Junction-to-bottom case thermal resistance
0.7
(1) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(2) lfm = linear feet per minute
7.8 Thermal Design Considerations
Based on the end application design and operational profile, the IDD and IDDIO currents could vary. Systems that
exceed the recommended maximum power dissipation in the end product may require additional thermal
enhancements. Ambient temperature (TA) varies with the end application and product design. The critical factor
that affects reliability and functionality is TJ, the junction temperature, not the ambient temperature. Hence, care
should be taken to keep TJ within the specified limits. Tcase should be measured to estimate the operating
junction temperature TJ. Tcase is normally measured at the center of the package top-side surface. The thermal
application report Semiconductor and IC Package Thermal Metrics helps to understand the thermal metrics and
definitions.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
63
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
7.9 System
7.9.1 Power Management
TMS320F28004x MCUs can be configured to operate with one of three options to supply the required 1.2 V to
the core (VDD):
•
•
•
An external supply (not available for 56-pin RSH package configurations)
Internal 1.2-V LDO Voltage Regulator (VREG)
Internal 1.2-V Switching Regulator (DC-DC)
The system requirements will dictate which supply option best suits the application.
Note
The same system voltage regulator must be used to drive both VDDIO and VDDIO_SW.
7.9.1.1 Internal 1.2-V LDO Voltage Regulator (VREG)
The internal VREG is supplied by VDDIO and generates the 1.2 V required to power the VDD pins. Enable this
functionality by pulling the VREGENZ pin low to VSS. The smaller pin-count packages may not include the
VREGENZ pin; therefore, the internal VREG is always enabled and, as such, is the required supply source for
the VDD pins. Review the description of VREGENZ in Table 6-5 to determine package configuration. Although
the internal VREG eliminates the need to use an external power supply for VDD, decoupling capacitors are
required on each VDD pin for VREG stability. There are two recommended capacitor configurations (described in
the list that follows) for the VDD rail when using the internal VREG. The signal description for VDD can be found
in Table 6-4.
•
Configuration 1: Place a small decoupling capacitor to VSS on each pin as close to the device as possible. In
addition, a bulk capacitance must be placed on the VDD node to VSS (one 20-µF capacitor or two parallel
10-µF capacitors).
•
Configuration 2: Distribute the total capacitance to VSS evenly across all VDD pins (total capacitance divided
by four VDD pins).
7.9.1.2 Internal 1.2-V Switching Regulator (DC-DC)
The internal DC-DC regulator offers increased efficiency over the LDO for converting 3.3 V to 1.2 V. The internal
DC-DC regulator is supplied by the VDDIO_SW pin and generates the 1.2 V required to power the VDD pins. To
use the internal switching regulator, the core domain must power up initially using the internal LDO VREG supply
(tie the VREGENZ pin low to VSS) and then transition to the DC-DC regulator through application software by
setting the DCDCEN bit in the DCDCCTL register. VREGENZ must still be kept low after transition since it
controls both the DC-DC and LDO. Tying VREGENZ high disables both the DC-DC and LDO. The DC-DC
regulator also requires external components (inductor, input capacitance, and output capacitance). The output of
internal DC-DC regulator is not internally fed to the VDD rail and requires an external connection. Figure 7-6
shows the schematic implementation.
L
F28004x
VSW
VDD
V
IN
VDDIO_SW
VSW
VFBSW
VDD
C
VDDIO_SW
VSS_SW
(A)
C
VDD
C
VDD_DECAP
VSS_SW
VSS
VSS
VSS_SW
VSS
Copyright © 2017, Texas Instruments Incorporated
A. One decoupling capacitor per each of the four VDD pins
Figure 7-6. DC-DC Circuit Schematic
Copyright © 2021 Texas Instruments Incorporated
64
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
The VDDIO_SW supply pin (VIN) requires a 3.3-V level voltage. A total input capacitance (CVDDIO_SW) of 20 µF is
required on VDDIO_SW. Due to the capacitor specification requirements detailed in Table 7-2, two parallel 10-µF
capacitors in parallel is the recommended configuration. Decoupling capacitors of 100 nF should also be placed
on each VDD pin as close to the device as possible.
Table 7-1. DC-DC Inductor (LVSW) Specifications Requirements
VALUE AND
VARIATION
VALUE AT
SATURATION
SATURATION
CURRENT
DCR
RATED CURRENT
TEMPERATURE
2.2 µH ± 20%
1.54 µH ± 20%
80 mΩ ± 25%
>1000 mA
>600 mA
–40°C to 125°C
Table 7-2. DC-DC Capacitor (CVDDIO_SW and CVDD) Specifications Requirements
VALUE AND
VARIATION AT 0 V
VALUE AT 1.2 V
VALUE AT 125°C
ESR
RATED VOLTAGE
TEMPERATURE
10 µF ± 20%
10 µF ± 20%
8 µF ± 20%
<10 mΩ
4 V or 6.3 V
–40°C to 125°C
Table 7-3. DC-DC Circuit Component Values
COMPONENT
MIN
1.76
8
NOM
2.2
10
MAX
2.64
12
UNIT
NOTES
Inductor
µH
20% variance
Input capacitor
Output capacitor
µF
20% varaince, two such capacitors in parallel
20% varaince, two such capacitors in parallel
8
10
12
µF
7.9.1.2.1 PCB Layout and Component Guidelines
For optimal performance the application board layout and component selection is important. The list that follows
is a high-level guideline for laying out the DC-DC circuit.
•
•
•
TI recommends star-connecting VDDIO_SW and VDDIO to the same 3.3-V supply.
All external components should be placed as close to the pins as possible.
The loop formed by the VDDIO_SW, input capacitor (CVDDIO_SW), and VSS_SW must be as short as
possible.
•
•
•
The feedback trace must be as short as possible and kept away from any noise source such as the switching
output (VSW).
It is necessary to have a separate island or surgical cut in the ground plane for the input cap (CVDDIO_SW) and
VSS_SW.
A VDD plane is recommended for connecting the VDD node to the LVSW-CVDD point to minimize parasitic
resistance and inductance.
7.9.1.2.1.1 Recommended External Components
MIN
TYP
MAX
UNIT
Based on External Supply IC
Requirements(1)
CVDDIO
Bulk capacitance on VDDIO
0.1
µF
Decoupling capacitor on each VDDIO
pin
CVDDIO_DECAP
CVDDA
CVDDIO_SW
0.1
µF
µF
Capacitor on VDDA pins
2.2
20
For DC-DC operation(2)
For LDO-only operation
For DC-DC operation(2)
For LDO-only operation(3)
For DC-DC operation(2)
For LDO-only operation(3)
Capacitor on VDDIO_SW pin
µF
µF
µF
0.1
20
CVDD
Bulk capacitance on VDD
12
20
27
0.1
CVDD_DECAP
Decoupling capacitor on each VDD pin
0.1
6.75
Inductor between VSW pin and VDD
node for DC-DC
LVSW
2.2
80
µH
RLVSW-DCR
Allowed DCR for LVSW
mΩ
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
65
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
MIN
TYP
MAX
UNIT
ISAT-LVSW
LVSW saturation current
600
mA
(1) Bulk capacitance on this supply should be based on supply IC requirements.
(2) See Section 7.9.1.2 for details.
(3) See Section 7.9.1.1 for details.
7.9.1.3 Deciding Between the LDO and the DC-DC
The DC-DC is significantly more efficient than the LDO. The DC-DC and LDO have typical efficiencies of 80%
and 30%, respectively. However, using the DC-DC comes with the trade-offs outlined below:
•
Potential analog performance degradation: This is heavily board layout-dependent and mostly affects the
ADC. See Section 7.10.1.2.2for details.
•
•
Increased component cost: The DC-DC requires an external inductor and capacitors to function.
Loss of I/Os: Using the DC-DC will make GPIO22 and GPIO23 unavailable for GPIO usage since their
functionality will change to VFBSW and VSW, respectively.
Note
An external DC-DC has the potential to be more efficient and less impactful in terms of noise since its
switching is external to the MCU but comes at the expense of much increased component cost.
7.9.1.4 Power Sequencing
Signal Pin Requirements: Before powering the device, no voltage larger than 0.3 V above VDDIO can be
applied to any digital pin, and no voltage larger than 0.3 V above VDDA can be applied to any analog pin
(including VREFHI).
VDDIO, VDDIO_SW, and VDDA Requirements: The 3.3-V supplies VDDIO, VDDIO_SW, and VDDA should be
powered up together and kept within 0.3 V of each other during functional operation.
VDD Requirements: When VREGENZ is tied to VSS, the VDD sequencing requirements are handled by the
device.
When using an external source for VDD (VREGENZ tied to VDDIO), VDDIO and VDD must be powered on and
off at the same time. VDDIO should not be powered on when VDD is off. During the ramp, VDD should be kept
no more than 0.3 V above VDDIO.
For applications not tying VREGENZ to VSS and not powering VDDIO and VDD at the same time, see the
"INTOSC: VDDIO Powered Without VDD Can Cause INTOSC Frequency Drift" advisory in the TMS320F28004x
MCUs Silicon Errata.
7.9.1.5 Power-On Reset (POR)
An internal power-on reset (POR) circuit holds the device in reset and keeps the I/Os in a high-impedance state
during power up. The POR is in control and forces XRSn low internally until the voltage on VDDIO crosses the
POR threshold. When the voltage crosses the POR threshold, the internal brownout-reset (BOR) circuit takes
control and holds the device in reset until the voltage crosses the BOR threshold (for internal BOR details, see
Section 7.9.1.6).
7.9.1.6 Brownout Reset (BOR)
An internal BOR circuit monitors the VDDIO rail for dips in voltage which result in the supply voltage dropping out
of operational range. When the VDDIO voltage drops below the BOR threshold, the device is forced into reset,
and XRSn is pulled low. XRSn will remain in reset until the voltage returns to the operational range. The BOR is
enabled by default. To disable the BOR, set the BORLVMONDIS bit in the VMONCTL register. The internal BOR
circuit monitors only the VDDIO rail. See Section 7.6 for BOR characteristics. External supply voltage supervisor
(SVS) devices can be used to monitor the voltage on the 3.3-V and 1.2-V rails and to drive XRSn low if supplies
fall outside operational specifications.
Copyright © 2021 Texas Instruments Incorporated
66
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
7.9.2 Reset Timing
XRSn is the device reset pin. It functions as an input and open-drain output. The device has a built-in power-on
reset (POR). During power up, the POR circuit drives the XRSn pin low. A watchdog or NMI watchdog reset will
also drive the pin low. An external circuit may drive the pin to assert a device reset.
A resistor with a value from 2.2 kΩ to 10 kΩ should be placed between XRSn and VDDIO. A capacitor should be
placed between XRSn and VSS for noise filtering, it should be 100 nF or smaller. These values will allow the
watchdog to properly drive the XRSn pin to VOL within 512 OSCCLK cycles when the watchdog reset is
asserted. Figure 7-7 shows the recommended reset circuit.
VDDIO
2.2 kW to 10 kW
Optional open-drain
Reset source
XRSn
£100 nF
Figure 7-7. Reset Circuit
7.9.2.1 Reset Sources
Table 7-4 summarizes the various reset signals and their effect on the device.
Table 7-4. Reset Signals
CPU CORE
RESET
(C28x, FPU, VCU)
JTAG/
DEBUG LOGIC
RESET
PERIPHERALS
RESET
RESET SOURCE
I/Os
XRSn OUTPUT
POR
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Yes
–
XRSn Pin
WDRS
Yes
Yes
No
No
NMIWDRS
SYSRS (Debugger Reset)
SCCRESET
The parameter th(boot-mode) must account for a reset initiated from any of these sources.
See the Resets section of the System Control chapter in the TMS320F28004x Microcontrollers Technical
Reference Manual.
CAUTION
Some reset sources are internally driven by the device. Some of these sources will drive XRSn low,
use this to disable any other devices driving the boot pins. The SCCRESET and debugger reset
sources do not drive XRSn; therefore, the pins used for boot mode should not be actively driven by
other devices in the system. The boot configuration has a provision for changing the boot pins in
OTP; for more details, see the TMS320F28004x Microcontrollers Technical Reference Manual.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
67
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
7.9.2.2 Reset Electrical Data and Timing
Section 7.9.2.2.1 lists the reset (XRSn) timing requirements. Section 7.9.2.2.2 lists the reset (XRSn) switching
characteristics. Figure 7-8 shows the power-on reset. Figure 7-9 shows the warm reset.
7.9.2.2.1 Reset (XRSn) Timing Requirements
MIN
1.5
MAX
UNIT
th(boot-mode)
Hold time for boot-mode pins
ms
All cases
3.2
Pulse duration, XRSn low on
warm reset
tw(RSL2)
µs
Low-power modes used in
application and SYSCLKDIV > 16
3.2 * (SYSCLKDIV/16)
7.9.2.2.2 Reset (XRSn) Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
100
MAX
UNIT
Pulse duration, XRSn driven low by device after supplies are
tw(RSL1)
µs
stable
tw(WDRS)
tboot-flash
Pulse duration, reset pulse generated by watchdog
512tc(OSCCLK)
cycles
µs
Boot-ROM execution time to first instruction fetch in flash
900
7.9.2.2.3 Reset Timing Diagram
VDDIO, VDDA
(3.3 V)
VDD (1.2 V)
t
w(RSL1)
XRSn(A)
Boot ROM
CPU
Execution
Phase
User-code
User-code dependent
(B)
h(boot-mode)
t
Boot-Mode
Pins
GPIO pins as input
Boot-ROM execution starts
Peripheral/GPIO function
Based on boot code
GPIO pins as input (pullups are disabled)
User-code dependent
I/O Pins
Figure 7-8. Power-on Reset
A. The XRSn pin can be driven externally by a supervisor or an external pullup resistor, see Table 6-1. On-chip POR logic will hold this pin
low until the supplies are in a valid range.
B. After reset from any source (see Section 7.11.2.1), the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode
pin, the boot code branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in
debugger environment), the boot code execution time is based on the current SYSCLK speed. The SYSCLK will be based on user
environment and could be with or without PLL enabled.
Copyright © 2021 Texas Instruments Incorporated
68
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
t
w(RSL2)
XRSn
User Code
CPU
Execution
Phase
User Code
Boot ROM
Boot-ROM execution starts
(initiated by any reset source)
(A)
t
h(boot-mode)
Boot-Mode
Pins
Peripheral/GPIO Function
User-Code Dependent
GPIO Pins as Input
Peripheral/GPIO Function
User-Code Execution Starts
I/O Pins
GPIO Pins as Input (Pullups are Disabled)
User-Code Dependent
Figure 7-9. Warm Reset
A. After reset from any source (see Section 7.11.2.1), the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot
Mode pin, the boot code branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in
debugger environment), the Boot code execution time is based on the current SYSCLK speed. The SYSCLK will be based on user
environment and could be with or without PLL enabled.
7.9.3 Clock Specifications
7.9.3.1 Clock Sources
Table 7-5 lists three possible clock sources. Figure 7-10 shows the clocking system. Figure 7-11 shows the
system PLL.
Table 7-5. Possible Reference Clock Sources
CLOCK SOURCE
MODULES CLOCKED
COMMENTS
INTOSC1
Can be used to provide clock for:
Internal oscillator 1.
Zero-pin overhead 10-MHz internal oscillator.
•
•
•
Watchdog block
Main PLL
CPU-Timer 2
INTOSC2(1)
X1 (XTAL)
Can be used to provide clock for:
Internal oscillator 2.
Zero-pin overhead 10-MHz internal oscillator.
•
•
Main PLL
CPU-Timer 2
Can be used to provide clock for:
External crystal or resonator connected between the X1 and X2 pins
or single-ended clock connected to the X1 pin.
•
•
Main PLL
CPU-Timer 2
(1) On reset, internal oscillator 2 (INTOSC2) is the default clock source for the system PLL (OSCCLK).
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
69
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
To watchdog
timer
INTOSC1
WDCLK
CLKSRCCTL1
SYSPLLCTL1
SYSCLKDIVSEL
INTOSC2
X1 (XTAL)
SYSCLK
Divider
OSCCLK
PLLSYSCLK
CPUCLK
To NMIWD
System PLL
PLLRAWCLK
SYSCLK
CPU
To local memories
To ePIE, RAMs, GPIOs,
and DCSM
SYSCLK
One per SYSCLK peripheral
PCLKCRx
PERx.SYSCLK
To peripherals
One per LSPCLK peripheral
PCLKCRx
LOSPCP
PERx.LSPCLK
To SCIs and SPIs
LSP
Divider
LSPCLK
One per CAN module
CLKSRCCTL2
CAN Bit Clock
To CANs
Figure 7-10. Clocking System
OSCCLK
VCO
PLLRAWCLK
/ODIV
/1 to /8
PLL
NF
fPLLRAWCLK = (fOSCCLK )ì
ODIV
/NF
/1 to /127.75
NF = IMULT + FMULT/4
Figure 7-11. System PLL
Copyright © 2021 Texas Instruments Incorporated
70
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
7.9.3.2 Clock Frequencies, Requirements, and Characteristics
This section provides the frequencies and timing requirements of the input clocks, PLL lock times, frequencies of
the internal clocks, and the frequency and switching characteristics of the output clock.
7.9.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
Section 7.9.3.2.1.1 lists the frequency requirements for the input clocks. Section 7.9.3.2.1.2 lists the XTAL
oscillator characteristics. Section 7.9.3.2.1.3 lists the X1 timing requirements. Section 7.9.3.2.1.4 lists the PLL
lock times for the Main PLL .
7.9.3.2.1.1 Input Clock Frequency
MIN
10
2
MAX UNIT
20 MHz
20 MHz
f(XTAL)
f(X1)
Frequency, X1/X2, from external crystal or resonator
Frequency, X1, from external oscillator
7.9.3.2.1.2 XTAL Oscillator Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
–0.3
TYP
MAX
UNIT
V
X1 VIL
X1 VIH
Valid low-level input voltage
Valid high-level input voltage
0.3 * VDDIO
VDDIO + 0.3
0.7 * VDDIO
V
7.9.3.2.1.3 X1 Timing Requirements
MIN
MAX UNIT
tf(X1)
Fall time, X1
6
6
ns
ns
tr(X1)
Rise time, X1
tw(X1L)
tw(X1H)
Pulse duration, X1 low as a percentage of tc(X1)
Pulse duration, X1 high as a percentage of tc(X1)
45%
45%
55%
55%
7.9.3.2.1.4 PLL Lock Times
MIN
NOM
25.5 µs + 1024 * tc(OSCCLK)
MAX UNIT
t(PLL)
Lock time, Main PLL
µs
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
71
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
7.9.3.2.2 Internal Clock Frequencies
Section 7.9.3.2.2.1 provides the clock frequencies for the internal clocks.
7.9.3.2.2.1 Internal Clock Frequencies
MIN
NOM
MAX
100
500
400
UNIT
MHz
ns
f(SYSCLK)
tc(SYSCLK)
f(VCO)
Frequency, device (system) clock
Period, device (system) clock
2
10
Frequency, PLL VCO (before output divider)
120
MHz
Frequency, system PLL output (before SYSCLK
divider)
f(PLLRAWCLK)
15
200
MHz
f(PLL)
Frequency, PLLSYSCLK
Frequency, LSPCLK
Period, LSPCLK
2
2
100
100
500
MHz
MHz
ns
f(LSP)
tc(LSPCLK)
10
Frequency, OSCCLK (INTOSC1 or INTOSC2 or
XTAL or X1)
f(OSCCLK)
f(HRPWM)
See respective clock
MHz
MHz
Frequency, HRPWMCLK
60
100
7.9.3.2.3 Output Clock Frequency and Switching Characteristics
Section 7.9.3.2.3.1 lists the switching characteristics of the output clock, XCLKOUT.
7.9.3.2.3.1 XCLKOUT Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER(1)
MIN
MAX
5
UNIT
ns
tf(XCO)
Fall time, XCLKOUT
tr(XCO)
tw(XCOL)
tw(XCOH)
f(XCO)
Rise time, XCLKOUT
5
ns
Pulse duration, XCLKOUT low
Pulse duration, XCLKOUT high
Frequency, XCLKOUT
H – 2(2)
H – 2(2)
H + 2(2)
H + 2(2)
50
ns
ns
MHz
(1) A load of 40 pF is assumed for these parameters.
(2) H = 0.5tc(XCO)
Copyright © 2021 Texas Instruments Incorporated
72
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
7.9.3.3 Input Clocks and PLLs
Note
GPIO18* and its mux options can be used only when the system is clocked by INTOSC and X1 has
an external pulldown resistor.
In addition to the internal 0-pin oscillators, three types of external clock sources are supported:
•
•
•
A single-ended 3.3-V external clock. The clock signal should be connected to X1, as shown in Figure 7-12,
with the XTALCR.SE bit set to 1.
Microcontroller
GPIO18*
VSS
X1
X2
Not available as a
GPIO when X1 is
used as a clock
+3.3 V
VDD
Out
3.3-V Oscillator
Gnd
Figure 7-12. Single-ended 3.3-V External Clock
An external crystal. The crystal should be connected across X1 and X2 with its load capacitors connected to
VSS as shown in Figure 7-13.
Microcontroller
GPIO18*
VSS
X1
X2
Figure 7-13. External Crystal
An external resonator. The resonator should be connected across X1 and X2 with its ground connected to
VSS as shown in Figure 7-14.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
73
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
Microcontroller
GPIO18*
X2
VSS
X1
Figure 7-14. External Resonator
Copyright © 2021 Texas Instruments Incorporated
74
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
7.9.3.4 Crystal Oscillator
When using a quartz crystal, it may be necessary to include a damping resistor (RD) in the crystal circuit to
prevent overdriving the crystal (drive level can be found in the crystal data sheet). In higher-frequency
applications (10 MHz or greater), RD is generally not required. If a damping resistor is required, RD should be as
small as possible because the size of the resistance affects start-up time (smaller RD = faster start-up time). TI
recommends that the crystal manufacturer characterize the crystal with the application board. Section 7.9.3.4.1
lists the crystal oscillator parameters. Table 7-6 lists the crystal equivalent series resistance (ESR) requirements.
Section 7.9.3.4.2 lists the crystal oscillator electrical characteristics.
7.9.3.4.1 Crystal Oscillator Parameters
MIN
MAX UNIT
CL1, CL2
C0
Load capacitance
12
24
7
pF
pF
Crystal shunt capacitance
Table 7-6. Crystal Equivalent Series Resistance (ESR) Requirements (1) (2)
MAXIMUM ESR (Ω)
(CL1 = CL2 = 12 pF)
MAXIMUM ESR (Ω)
(CL1 = CL2 = 24 pF)
CRYSTAL FREQUENCY (MHz)
10
12
14
16
18
20
55
50
50
45
45
45
110
95
90
75
65
50
(1) Crystal shunt capacitance (C0) should be less than or equal to 7 pF.
(2) ESR = Negative Resistance/3
7.9.3.4.2 Crystal Oscillator Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ms
f = 20 MHz
ESR MAX = 50 Ω
CL1 = CL2 = 24 pF
C0 = 7 pF
Start-up time(1)
2
Crystal drive level (DL)
1
mW
(1) Start-up time is dependent on the crystal and tank circuit components. TI recommends that the crystal vendor characterize the
application with the chosen crystal.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
75
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
7.9.3.5 Internal Oscillators
To reduce production board costs and application development time, all F28004x devices contain two
independent internal oscillators, referred to as INTOSC1 and INTOSC2. By default, both oscillators are enabled
at power up. INTOSC2 is set as the source for the system reference clock (OSCCLK) and INTOSC1 is set as the
backup clock source. INTOSC1 can also be manually configured as the system reference clock (OSCCLK).
Section 7.9.3.5.1 provides the electrical characteristics of the internal oscillators to determine if this module
meets the clocking requirements of the application.
7.9.3.5.1 INTOSC Characteristics
over recommended operating conditions (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
MIN
TYP
MAX
UNIT
Frequency, INTOSC1 and
INTOSC2
fINTOSC
9.7
10
10.3
MHz
Frequency stability at room
temperature
30°C, Nominal
VDD
±0.1%
±0.2%
fINTOSC-STABILITY
Frequency stability over VDD
Frequency stability
30°C
–3%
3%
20
tINT0SC-ST
Start-up and settling time
µs
Copyright © 2021 Texas Instruments Incorporated
76
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
7.9.4 Flash Parameters
Table 7-7 lists the minimum required Flash wait states with different clock sources and frequencies.
Table 7-7. Minimum Required Flash Wait States with Different Clock Sources and Frequencies
EXTERNAL OSCILLATOR OR CRYSTAL
INTOSC1 OR INTOSC2
CPUCLK (MHz) (1)
PROGRAM, ERASE,
PROGRAM, ERASE,
FLASH READ OR
BANK SLEEP, OR PUMP
EXECUTE
FLASH READ OR
EXECUTE
BANK SLEEP, OR PUMP
SLEEP
SLEEP (2)
97 < CPUCLK ≤ 100
80 < CPUCLK ≤ 97
77 < CPUCLK ≤ 80
60 < CPUCLK ≤ 77
58 < CPUCLK ≤ 60
40 < CPUCLK ≤ 58
38 < CPUCLK ≤ 40
20 < CPUCLK ≤ 38
19 < CPUCLK ≤ 20
CPUCLK ≤ 19
5
4
4
3
3
2
2
1
1
0
4
3
2
1
0
4
3
2
1
0
The F28004x devices have an improved 128-bit prefetch buffer that provides high flash code execution efficiency
across wait states. Figure 7-15 and Figure 7-16 illustrate typical efficiency across wait-state settings compared to
previous-generation devices with a 64-bit prefetch buffer. Wait-state execution efficiency with a prefetch buffer
will depend on how many branches are present in application software. Two examples of linear code and if-then-
else code are provided.
100%
90%
80%
70%
60%
50%
40%
30%
100%
95%
90%
85%
80%
75%
70%
65%
60%
55%
Flash with 64-Bit Prefetch
Flash with 128-Bit Prefetch
Flash with 64-Bit Prefetch
Flash with 128-Bit Prefetch
0
1
2
3
4
5
0
1
2
3
4
5
Wait State
Wait State
D005
D006
Figure 7-15. Application Code With Heavy 32-Bit
Floating-Point Math Instructions
Figure 7-16. Application Code With 16-Bit If-Else
Instructions
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
77
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
Table 7-8 lists the Flash parameters.
Table 7-8. Flash Parameters
PARAMETER
MIN
TYP
150
50
MAX
300
UNIT
µs
128 data bits + 16 ECC bits
8KB sector
Program Time (1)
100
ms
EraseTime (2) at < 25 W/E cycles
EraseTime (2) at 1000 W/E cycles
EraseTime (2) at 2000 W/E cycles
EraseTime (2) at 20K W/E cycles
Nwec Write/Erase Cycles
8KB sector
15
100
ms
8KB sector
25
350
ms
8KB sector
30
600
ms
8KB sector
120
4000
20000
ms
cycles
years
tretention Data retention duration at TJ = 85oC
20
(1) Program time is at the maximum device frequency. Program time includes overhead of the flash state machine but does not include
the time to transfer the following into RAM:
• Code that uses flash API to program the flash
• Flash API itself
• Flash data to be programmed
In other words, the time indicated in this table is applicable after all the required code/data is available in the device RAM, ready for
programming. The transfer time will significantly vary depending on the speed of the JTAG debug probe used.
Program time calculation is based on programming 144 bits at a time at the specified operating frequency. Program time includes
Program verify by the CPU. The program time does not degrade with write/erase (W/E) cycling, but the erase time does and hence
Erase time is provided for 25 W/E cycles, 1K W/E cycles, 2K W/E cycles and 20K W/E cycles.
Erase time includes Erase verify by the CPU and does not involve any data transfer.
(2) Erase time includes Erase verify by the CPU.
Note
The Main Array flash programming must be aligned to 64-bit address boundaries and each 64-bit
word may only be programmed once per write/erase cycle.
The DCSM OTP programming must be aligned to 128-bit address boundaries and each 128-bit word
may only be programmed once. The exceptions are:
1. The DCSM Zx-LINKPOINTER1 and Zx-LINKPOINTER2 values in the DCSM OTP should be
programmed together, and may be programmed 1 bit at a time as required by the DCSM operation.
2. The DCSM Zx-LINKPOINTER3 values in the DCSM OTP may be programmed 1 bit at a time on a
64-bit boundary to separate it from Zx-PSWDLOCK, which must only be programmed once.
Copyright © 2021 Texas Instruments Incorporated
78
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
7.9.5 Emulation/JTAG
The JTAG (IEEE Standard 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture) port has
four dedicated pins: TMS, TDI, TDO, and TCK. The cJTAG (IEEE Standard 1149.7-2009 for Reduced-Pin and
Enhanced-Functionality Test Access Port and Boundary-Scan Architecture) port is a compact JTAG interface
requiring only two pins (TMS and TCK), which allows other device functionality to be muxed to the traditional
GPIO35 (TDI) and GPIO37 (TDO) pins.
Typically, no buffers are needed on the JTAG signals when the distance between the MCU target and the JTAG
header is smaller than 6 inches (15.24 cm), and no other devices are present on the JTAG chain. Otherwise,
each signal should be buffered. Additionally, for most JTAG debug probe operations at 10 MHz, no series
resistors are needed on the JTAG signals. However, if high emulation speeds are expected (35 MHz or so), 22-Ω
resistors should be placed in series on each JTAG signal.
The PD (Power Detect) terminal of the JTAG debug probe header should be connected to the board's 3.3-V
supply. Header GND terminals should be connected to board ground. TDIS (Cable Disconnect Sense) should
also be connected to board ground. The JTAG clock should be looped from the header TCK output terminal back
to the RTCK input terminal of the header (to sense clock continuity by the JTAG debug probe). This MCU does
not support the EMU0 and EMU1 signals that are present on 14-pin and 20-pin emulation headers. These
signals should always be pulled up at the emulation header through a pair of board pullup resistors ranging from
2.2 kΩ to 4.7 kΩ (depending on the drive strength of the debugger ports). Typically, a 2.2-kΩ value is used.
Header terminal RESET is an open-drain output from the JTAG debug probe header that enables board
components to be reset through JTAG debug probe commands (available only through the 20-pin header).
Figure 7-17 shows how the 14-pin JTAG header connects to the MCU’s JTAG port signals. Figure 7-18 shows
how to connect to the 20-pin JTAG header. The 20-pin JTAG header terminals EMU2, EMU3, and EMU4 are not
used and should be grounded.
For more information about hardware breakpoints and watchpoints, see Hardware Breakpoints and Watchpoints
for C28x in CCS.
For more information about JTAG emulation, see the XDS Target Connection Guide.
Note
JTAG Test Data Input (TDI) is the default mux selection for the pin. The internal pullup is disabled by
default. If this pin is used as JTAG TDI, the internal pullup should be enabled or an external pullup
added on the board to avoid a floating input. In the cJTAG option, this pin can be used as GPIO.
JTAG Test Data Output (TDO) is the default mux selection for the pin. The internal pullup is disabled
by default. The TDO function will be in a tri-state condition when there is no JTAG activity, leaving this
pin floating. The internal pullup should be enabled or an external pullup added on the board to avoid a
floating GPIO input. In the cJTAG option, this pin can be used as GPIO.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
79
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
Distance between the header and the target
should be less than 6 inches (15.24 cm).
3.3 V
4.7 kΩ
3.3 V
10 kΩ
3.3 V
10 kΩ
2
1
TMS
TMS
TRST
TDI(A)
TDI
TDIS
KEY
3
5
4
GND
MCU
100 Ω
6
3.3 V
PD
TDO(A)
TCK
TDO
RTCK
TCK
EMU0
GND
GND
GND
EMU1
7
8
9
10
12
14
11
13
4.7 kΩ
4.7 kΩ
3.3 V
3.3 V
A. TDI and TDO connections are not required for cJTAG option and these pins can be used as GPIOs instead.
Figure 7-17. Connecting to the 14-Pin JTAG Header
Distance between the header and the target
should be less than 6 inches (15.24 cm).
3.3 V
4.7 kΩ
3.3 V
10 kΩ
3.3 V
10 kΩ
2
1
TMS
TMS
TRST
TDI(A)
TDI
TDIS
KEY
GND
3
5
4
MCU
100 Ω
6
3.3V
PD
TDO(A)
TDO
GND
GND
GND
EMU1
GND
EMU3
GND
7
8
9
10
12
14
16
18
20
RTCK
TCK
11
13
15
17
19
TCK
Ω
4.7 kΩ
4.7 k
3.3 V
EMU0
RESET
EMU2
EMU4
3.3 V
Open
Drain
A low pulse from the JTAG debug probe
can be tied with other reset sources
to reset the board.
GND
GND
A. TDI and TDO connections are not required for cJTAG option and these pins can be used as GPIOs instead.
Figure 7-18. Connecting to the 20-Pin JTAG Header
Copyright © 2021 Texas Instruments Incorporated
80
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
7.9.5.1 JTAG Electrical Data and Timing
Section 7.9.5.1.1 lists the JTAG timing requirements. Section 7.9.5.1.2 lists the JTAG switching characteristics.
Figure 7-19 shows the JTAG timing.
7.9.5.1.1 JTAG Timing Requirements
NO.
1
MIN
66.66
26.66
26.66
13
MAX
UNIT
ns
tc(TCK)
Cycle time, TCK
1a
1b
tw(TCKH)
Pulse duration, TCK high (40% of tc)
Pulse duration, TCK low (40% of tc)
Input setup time, TDI valid to TCK high
Input setup time, TMS valid to TCK high
Input hold time, TDI valid from TCK high
Input hold time, TMS valid from TCK high
ns
tw(TCKL)
ns
tsu(TDI-TCKH)
tsu(TMS-TCKH)
th(TCKH-TDI)
th(TCKH-TMS)
3
4
ns
ns
13
7
7
7.9.5.1.2 JTAG Switching Characteristics
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER
MIN
MAX
UNIT
2
td(TCKL-TDO)
Delay time, TCK low to TDO valid
6
25
ns
7.9.5.1.3 JTAG Timing Diagram
1
1a
1b
TCK
2
TDO
3
4
TDI/TMS
Figure 7-19. JTAG Timing
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
81
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
7.9.5.2 cJTAG Electrical Data and Timing
Section 7.9.5.2.1 lists the cJTAG timing requirements. Section 7.9.5.2.2 lists the cJTAG switching characteristics.
Figure 7-20 shows the cJTAG timing.
7.9.5.2.1 cJTAG Timing Requirements
NO.
1
MIN
100
40
40
15
15
2
MAX
UNIT
ns
tc(TCK)
Cycle time, TCK
1a
1b
tw(TCKH)
Pulse duration, TCK high (40% of tc)
Pulse duration, TCK low (40% of tc)
Input setup time, TMS valid to TCK high
Input setup time, TMS valid to TCK low
Input hold time, TMS valid from TCK high
Input hold time, TMS valid from TCK low
ns
tw(TCKL)
ns
tsu(TMS-TCKH)
tsu(TMS-TCKL)
th(TCKH-TMS)
th(TCKL-TMS)
ns
3
4
ns
ns
2
ns
7.9.5.2.2 cJTAG Switching Characteristics
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER
MIN
MAX
20
UNIT
ns
2
td(TCKL-TMS)
Delay time, TCK low to TMS valid
Delay time, TCK high to TMS disable
6
5
tdis(TCKH-TMS)
20
ns
7.9.5.2.3 cJTAG Timing Diagram
1
1a
1b
2
3
3
4
4
5
TCK
TMS
TMS Input
TMS Output
TMS Input
Figure 7-20. cJTAG Timing
Copyright © 2021 Texas Instruments Incorporated
82
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
7.9.6 GPIO Electrical Data and Timing
The peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. On reset, GPIO pins
are configured as inputs. For specific inputs, the user can also select the number of input qualification cycles to
filter unwanted noise glitches.
The GPIO module contains an Output X-BAR which allows an assortment of internal signals to be routed to a
GPIO in the GPIO mux positions denoted as OUTPUTXBARx. The GPIO module also contains an Input X-BAR
which is used to route signals from any GPIO input to different IP blocks such as the ADCs, eCAPs, ePWMs,
and external interrupts. For more details, see the X-BAR chapter in the TMS320F28004x Microcontrollers
Technical Reference Manual.
7.9.6.1 GPIO – Output Timing
Section 7.9.6.1.1 lists the general-purpose output switching characteristics. Figure 7-21 shows the general-
purpose output timing.
7.9.6.1.1 General-Purpose Output Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
All GPIOs except
GPIO23_VSW
tr(GPIO)
Rise time, GPIO switching low to high
8(1)
ns
All GPIOs except
GPIO23_VSW
tf(GPIO)
fGPIO
Fall time, GPIO switching high to low
8(1)
25
ns
Toggling frequency, all GPIOs except GPIO23_VSW
MHz
(1) Rise time and fall time vary with load. These values assume a 40-pF load.
GPIO
tr(GPIO)
tf(GPIO)
Figure 7-21. General-Purpose Output Timing
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
83
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
7.9.6.2 GPIO – Input Timing
Section 7.9.6.2.1 lists the general-purpose input timing requirements. Figure 7-22 shows the sampling mode.
7.9.6.2.1 General-Purpose Input Timing Requirements
Table 7-9. General-Purpose Input Timing Requirements
MIN
MAX
UNIT
cycles
cycles
cycles
QUALPRD = 0
QUALPRD ≠ 0
1tc(SYSCLK)
tw(SP)
Sampling period
2tc(SYSCLK) * QUALPRD
tw(SP) * (n(1) – 1)
tw(IQSW)
Input qualifier sampling window
Pulse duration, GPIO low/high
Synchronous mode
With input qualifier
2tc(SYSCLK)
(2)
tw(GPI)
tw(IQSW) + tw(SP) + 1tc(SYSCLK)
(1) "n" represents the number of qualification samples as defined by GPxQSELn register.
(2) For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.
(A)
GPIO Signal
GPxQSELn = 1,0 (6 samples)
1
1
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
tw(SP)
Sampling Period determined
by GPxCTRL[QUALPRD](B)
tw(IQSW)
(SYSCLK cycle * 2 * QUALPRD) * 5(C)
Sampling Window
SYSCLK
QUALPRD = 1
(SYSCLK/2)
(D)
Output From
Qualifier
A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can vary from 00 to
0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLK cycle. For any other value "n", the qualification sampling period in 2n
SYSCLK cycles (that is, at every 2n SYSCLK cycles, the GPIO pin will be sampled).
B. The qualification period selected through the GPxCTRL register applies to groups of eight GPIO pins.
C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is used.
D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLK cycles or greater. In other words,
the inputs should be stable for (5 × QUALPRD × 2) SYSCLK cycles. This would ensure 5 sampling periods for detection to occur.
Because external signals are driven asynchronously, an 13-SYSCLK-wide pulse ensures reliable recognition.
Figure 7-22. Sampling Mode
Copyright © 2021 Texas Instruments Incorporated
84
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
7.9.6.3 Sampling Window Width for Input Signals
The following section summarizes the sampling window width for input signals for various input qualifier
configurations.
Sampling frequency denotes how often a signal is sampled with respect to SYSCLK.
Sampling frequency = SYSCLK/(2 × QUALPRD), if QUALPRD ≠ 0
Sampling frequency = SYSCLK, if QUALPRD = 0
Sampling period = SYSCLK cycle × 2 × QUALPRD, if QUALPRD ≠ 0
In the previous equations, SYSCLK cycle indicates the time period of SYSCLK.
Sampling period = SYSCLK cycle, if QUALPRD = 0
In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of the
signal. This is determined by the value written to GPxQSELn register.
Case 1:
Qualification using 3 samples
Sampling window width = (SYSCLK cycle × 2 × QUALPRD) × 2, if QUALPRD ≠ 0
Sampling window width = (SYSCLK cycle) × 2, if QUALPRD = 0
Case 2:
Qualification using 6 samples
Sampling window width = (SYSCLK cycle × 2 × QUALPRD) × 5, if QUALPRD ≠ 0
Sampling window width = (SYSCLK cycle) × 5, if QUALPRD = 0
Figure 7-23 shows the general-purpose input timing.
SYSCLK
GPIOxn
tw(GPI)
Figure 7-23. General-Purpose Input Timing
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
85
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
7.9.7 Interrupts
The C28x CPU has fourteen peripheral interrupt lines. Two of them (INT13 and INT14) are connected directly to
CPU timers 1 and 2, respectively. The remaining twelve are connected to peripheral interrupt signals through the
enhanced Peripheral Interrupt Expansion (ePIE) module. The ePIE multiplexes up to sixteen peripheral
interrupts into each CPU interrupt line. It also expands the vector table to allow each interrupt to have its own
ISR. This allows the CPU to support a large number of peripherals.
An interrupt path is divided into three stages—the peripheral, the ePIE, and the CPU. Each stage has its own
enable and flag registers. This system allows the CPU to handle one interrupt while others are pending,
implement and prioritize nested interrupts in software, and disable interrupts during certain critical tasks.
Figure 7-24 shows the interrupt architecture for this device.
TINT0
TIMER0
LPMINT
LPM Logic
WAKEINT
NMI
NMI module
WD
WDINT
CPU
INPUTXBAR4
XINT1 Control
XINT2 Control
XINT3 Control
XINT4 Control
XINT5 Control
GPIO0
GPIO1
...
...
GPIOx
INT1
to
INT12
INPUTXBAR5
INPUTXBAR6
INPUTXBAR13
INPUTXBAR14
ePIE
Input
X-BAR
TINT1
TINT2
TIMER1
TIMER2
ERAD
INT13
INT14
Peripherals
See ePIE Table.
RTOSINT
Figure 7-24. Device Interrupt Architecture
Copyright © 2021 Texas Instruments Incorporated
86
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
7.9.7.1 External Interrupt (XINT) Electrical Data and Timing
Section 7.9.7.1.1 lists the external interrupt timing requirements. Section 7.9.7.1.2 lists the external interrupt
switching characteristics. Section 7.9.7.1.3 shows the external interrupt timing.
7.9.7.1.1 External Interrupt Timing Requirements
(1)
MIN
2tc(SYSCLK)
MAX
UNIT
Synchronous
With qualifier
tw(INT)
Pulse duration, INT input low/high
cycles
tw(IQSW) + tw(SP) + 1tc(SYSCLK)
(1) For an explanation of the input qualifier parameters, see Section 7.9.6.2.1.
7.9.7.1.2 External Interrupt Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER (1)
MIN
MAX
UNIT
td(INT) Delay time, INT low/high to interrupt-vector fetch (2)
tw(IQSW) + 14tc(SYSCLK)
tw(IQSW) + tw(SP) + 14tc(SYSCLK) cycles
(1) For an explanation of the input qualifier parameters, see Section 7.9.6.2.1.
(2) This assumes that the ISR is in a single-cycle memory.
7.9.7.1.3 Interrupt Timing Diagram
tw(INT)
XINT1, XINT2, XINT3,
XINT4, XINT5
td(INT)
Address bus
(internal)
Interrupt Vector
Figure 7-25. External Interrupt Timing
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
87
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
7.9.8 Low-Power Modes
This device has HALT and IDLE as two clock-gating low-power modes. STANDBY mode is not supported on this
device. See the TMS320F28004x MCUs Silicon Errata for more details.
Further details, as well as the entry and exit procedure, for all of the low-power modes can be found in the Low
Power Modes section of the TMS320F28004x Microcontrollers Technical Reference Manual.
7.9.8.1 Clock-Gating Low-Power Modes
IDLE and HALT modes on this device are similar to those on other C28x devices. Table 7-10 describes the effect
on the system when any of the clock-gating low-power modes are entered.
Table 7-10. Effect of Clock-Gating Low-Power Modes on the Device
MODULES/
CLOCK DOMAIN
IDLE
HALT
SYSCLK
CPUCLK
Active
Gated
Active
Gated
Gated
Gated
Clock to modules connected to
PERx.SYSCLK
WDCLK
PLL
Active
Gated if CLKSRCCTL1.WDHALTI = 0
Software must power down PLL before entering HALT.
Powered down if CLKSRCCTL1.WDHALTI = 0
Powered down if CLKSRCCTL1.WDHALTI = 0
Powered
Powered
Powered
Powered
Powered
Powered
INTOSC1
INTOSC2
Flash(1)
XTAL(2)
Powered
(1) The Flash module is not powered down by hardware in any LPM. It may be powered down using software if required by the
application. For more information, see the Flash and OTP Memory section of the System Control chapter in the TMS320F28004x
Microcontrollers Technical Reference Manual.
(2) The XTAL is not powered down by hardware in any LPM. It may be powered down by software setting the XTALCR.OSCOFF bit to 1.
This can be done at any time during the application if the XTAL is not required.
Copyright © 2021 Texas Instruments Incorporated
88
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
7.9.8.2 Low-Power Mode Wake-up Timing
Section 7.9.8.2.1 lists the IDLE mode timing requirements, Section 7.9.8.2.2 lists the switching characteristics,
and Figure 7-26 shows the timing diagram for IDLE mode.
7.9.8.2.1 IDLE Mode Timing Requirements (1)
MIN
2tc(SYSCLK)
MAX
UNIT
Without input qualifier
With input qualifier
tw(WAKE)
Pulse duration, external wake-up signal
cycles
2tc(SYSCLK) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 7.9.6.2.1.
7.9.8.2.2 IDLE Mode Switching Characteristics (1)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Delay time, external wake signal to program execution resume (2)
•
Wake up from flash
Flash module in active state
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
40tc(SYSCLK)
–
40tc(SYSCLK) + tw(WAKE)
(3)
td(WAKE-IDLE)
•
Wake up from flash
Flash module in sleep state
6700tc(SYSCLK)
cycles
–
6700tc(SYSCLK) (3) + tw(WAKE)
25tc(SYSCLK)
•
Wake up from RAM
25tc(SYSCLK) + tw(WAKE)
(1) For an explanation of the input qualifier parameters, see Section 7.9.6.2.1.
(2) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered
by the wake-up signal) involves additional latency.
(3) This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and
FPAC1[PSLEEP]. For more information, see the Flash/OTP and Pump Power Modes and Wakeup section of the TMS320F28004x
Microcontrollers Technical Reference Manual.
7.9.8.2.3 IDLE Mode Timing Diagram
td(WAKE-IDLE)
Address/Data
(internal)
XCLKOUT
tw(WAKE)
WAKE(A)
A. WAKE can be any enabled interrupt, WDINT or XRSn. After the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum)
is needed before the wake-up signal could be asserted.
Figure 7-26. IDLE Entry and Exit Timing Diagram
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
89
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
Section 7.9.8.2.4 lists the HALT mode timing requirements, Section 7.9.8.2.5 lists the switching characteristics,
and Figure 7-27 shows the timing diagram for HALT mode.
7.9.8.2.4 HALT Mode Timing Requirements
MIN
toscst + 2tc(OSCCLK)
toscst + 8tc(OSCCLK)
MAX
UNIT
cycles
cycles
tw(WAKE-GPIO)
tw(WAKE-XRS)
Pulse duration, GPIO wake-up signal(1)
Pulse duration, XRSn wake-up signal(1)
(1) For applications using X1/X2 for OSCCLK, the user must characterize their specific oscillator start-up time as it is dependent on circuit/
layout external to the device. See Section 7.9.3.4.2 for more information. For applications using INTOSC1 or INTOSC2 for OSCCLK,
see Section 7.9.3.5 for toscst. Oscillator start-up time does not apply to applications using a single-ended crystal on the X1 pin, as it is
powered externally to the device.
7.9.8.2.5 HALT Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
td(IDLE-XCOS)
Delay time, IDLE instruction executed to XCLKOUT stop
16tc(INTOSC1)
cycles
Delay time, external wake signal end to CPU program
execution resume
•
•
•
Wake up from flash
Flash module in active state
75tc(OSCCLK)
–
td(WAKE-HALT)
cycles
Wake up from flash
Flash module in sleep state
(1)
17500tc(OSCCLK)
–
Wake up from RAM
75tc(OSCCLK)
(1) This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and
FPAC1[PSLEEP]. For more information, see the Flash/OTP and Pump Power Modes and Wakeup section of the TMS320F28004x
Microcontrollers Technical Reference Manual.
7.9.8.2.6 HALT Mode Timing Diagram
(C)
(F)
(A)
(B)
(D)(E)
HALT
(G)
Device
Status
HALT
Flushing Pipeline
Normal
Execution
GPIOn
td(WAKE-HALT)
tw(WAKE-GPIO)
OSCCLK
Oscillator Start-up Time
XCLKOUT
td(IDLE-XCOS)
A. IDLE instruction is executed to put the device into HALT mode.
B. The LPM block responds to the HALT signal, SYSCLK is held for a maximum 16 INTOSC1 clock cycles before being turned off. This
delay enables the CPU pipeline and any other pending operations to flush properly.
C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as the clock source,
the internal oscillator is shut down as well. The device is now in HALT mode and consumes very little power. It is possible to keep the
zero-pin internal oscillators (INTOSC1 and INTOSC2) and the watchdog alive in HALT MODE. This is done by writing 1 to
Copyright © 2021 Texas Instruments Incorporated
90
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
CLKSRCCTL1.WDHALTI. After the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum) is needed before the wake-
up signal could be asserted.
D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator wake-up sequence
is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This enables the provision of a clean clock signal
during the PLL lock sequence. Because the falling edge of the GPIO pin asynchronously begins the wake-up procedure, care should be
taken to maintain a low noise environment before entering and during HALT mode.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal
must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the device will not be deterministic and the device
may not exit low-power mode for subsequent wake-up pulses.
F. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after some latency. The HALT mode is now
exited.
G. Normal operation resumes.
H. The user must relock the PLL upon HALT wakeup to ensure a stable PLL lock.
Figure 7-27. HALT Entry and Exit Timing Diagram
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
91
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
7.10 Analog Peripherals
The analog subsystem module is described in this section.
The analog modules on this device include the ADC, PGA, temperature sensor, buffered DAC, and CMPSS.
The analog subsystem has the following features:
•
Flexible voltage references
– The ADCs are referenced to VREFHIx and VREFLOx pins.
•
VREFHIx pin voltage can be driven in externally or can be generated by an internal bandgap voltage
reference.
•
The internal voltage reference range can be selected to be 0 V to 3.3 V or 0 V to 2.5 V.
•
•
•
The buffered DACs are referenced to VREFHIx and VREFLOx.
– Alternately, these DACs can be referenced to the VDAC pin and VSSA.
The comparator DACs are referenced to VDDA and VSSA.
– Alternately, these DACs can be referenced to the VDAC pin and VSSA.
Flexible pin usage
– Buffered DAC outputs, comparator subsystem inputs, PGA functions, and digital inputs are multiplexed
with ADC inputs
– Internal connection to VREFLO on all ADCs for offset self-calibration
Figure 7-28 shows the Analog Subsystem Block Diagram for the 100-pin PZ LQFP.
Figure 7-29 shows the Analog Subsystem Block Diagram for the 64-pin PM LQFP.
Figure 7-30 shows the Analog Subsystem Block Diagram for the 56-pin RSH VQFN.
Copyright © 2021 Texas Instruments Incorporated
92
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
VREFHIA
VREFHIB, VREFHIC
VREFLOA
VREFLOB, VREFLOC
Comparator Subsystem 1
CMP1_HP
CTRIP1H
Digital
Filter
CMP1_HN
VDDA or VDAC
CTRIPOUT1H
VREFHI VDAC
DACREFSEL
DAC12
DAC12
Misc. Analog
CTRIP1L
Digital
Filter
A0/B15/C15/DACA_OUT
A1/DACB_OUT
CMP1_LN
CMP1_LP
CTRIPOUT1L
Temp
Sensor
AIO
I
12-bit
Buffered
DAC-A
DACA_OUT
Comparator Subsystem 2
CMP2_HP
CMP2_HN
CTRIP2H
Digital
Filter
VDDA or VDAC
CTRIPOUT2H
Analog Group 1
Reference Circuit A
ANAREFASEL
DAC12
DAC12
A3
A2/B6/PGA1_OF
C0
AIO
CTRIP2L
Digital
Filter
CMP2_LN
CMP2_LP
PGA1
PGA3
PGA5
Vref
CTRIPOUT2L
PGA1_IN
PGA1_GND
CMPSS1
Input MUX
REFLO
Comparator Subsystem 3
CMP3_HP
CMP3_HN
CTRIP3H
Analog Group 3
Digital
Filter
VDDA or VDAC
CTRIPOUT3H
B3/VDAC
B2/C6/PGA3_OF
C2
AIO
REFHI
DAC12
DAC12
ADC Inputs
A0 to A15
PGA3_IN
PGA3_GND
ADC-A
12-bits
CTRIP3L
Digital
Filter
CMPSS3
Input MUX
CMP3_LN
CMP3_LP
CTRIPOUT3L
REFLO
Analog Group 5
Comparator Subsystem 4
CMP4_HP
CMP4_HN
CTRIP4H
Digital
Filter
AIO
A6/PGA5_OF
C4
PGA5_IN
PGA5_GND
VDDA or VDAC
CTRIPOUT4H
VREFHI VDAC
DACREFSEL
DAC12
DAC12
CMPSS5
Input MUX
CTRIP4L
Digital
Filter
CMP4_LN
CMP4_LP
CTRIPOUT4L
12-bit
Buffered
DAC-B
DACB_OUT
Comparator Subsystem 5
Analog Group 2
CMP5_HP
CMP5_HN
CTRIP5H
Digital
Filter
A5
A4/B8/PGA2_OF
C1
AIO
VDDA or VDAC
CTRIPOUT5H
Reference Circuit B
ANAREFBSEL
PGA2
PGA4
PGA6
DAC12
DAC12
PGA2_IN
CMPSS2
Input MUX
PGA2_GND/
PGA4_GND/
PGA6_GND/
CTRIP5L
Digital
Filter
Vref
CMP5_LN
CMP5_LP
CTRIPOUT5L
REFLO
Analog Group 4
Comparator Subsystem 6
CMP6_HP
CMP6_HN
AIO
B4/C8/PGA4_OF
C3/PGA4_IN
CTRIP6H
Digital
Filter
VDDA or VDAC
CTRIPOUT6H
REFHI
CMPSS4
Input MUX
ADC Inputs
B0 to B15
DAC12
DAC12
ADC-B
12-bits
CTRIP6L
Digital
Filter
CMP6_LN
CMP6_LP
Analog Group 6
CTRIPOUT6L
A9
A8/PGA6_OF
REFLO
AIO
Comparator Subsystem 7
CMP7_HP
CMP7_HN
C5/PGA6_IN
CTRIP7H
Digital
Filter
CMPSS6
Input MUX
VDDA or VDAC
CTRIPOUT7H
DAC12
DAC12
CTRIP7L
Digital
Filter
CMP7_LN
CMP7_LP
CTRIPOUT7L
Analog Group 7
B0
A10/B1/C10/PGA7_OF
C14
AIO
PGA7
PGA7_IN
PGA7_GND
REFHI
CMPSS7
Input MUX
ADC Inputs
C0 to C15
ADC-C
12-bits
REFLO
CMPSS
Inputs
Copyright © 2017, Texas Instruments Incorporated
Figure 7-28. Analog Subsystem Block Diagram (100-Pin PZ LQFP)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
93
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
VREFHIA
VREFLOA
Comparator Subsystem 1
Digital
Filter
CMP1_HP
CMP1_HN
CTRIP1H
VDDA or VDAC
CTRIPOUT1H
VREFHI VDAC
DACREFSEL
DAC12
DAC12
Misc. Analog
CTRIP1L
Digital
Filter
A0/B15/C15/DACA_OUT
A1/DACB_OUT
CMP1_LN
CMP1_LP
CTRIPOUT1L
Temp
Sensor
AIO
12-bit
Buffered
DAC-A
DACA_OUT
Comparator Subsystem 2
Digital
Filter
CMP2_HP
CMP2_HN
CTRIP2H
VDDA or VDAC
CTRIPOUT2H
Analog Group 1
Reference Circuit A
ANAREFASEL
DAC12
DAC12
AIO
A2/B6/PGA1_OF
CTRIP2L
Digital
Filter
CMP2_LN
CMP2_LP
PGA1
PGA3
PGA5
Vref
CTRIPOUT2L
C0/PGA1_IN
PGA1_GND/
PGA3_GND/
PGA5_GND/
CMPSS1
Input MUX
REFLO
Comparator Subsystem 3
CMP3_HP
CMP3_HN
CTRIP3H
Analog Group 3
Digital
Filter
VDDA or VDAC
CTRIPOUT3H
B3/VDAC
B2/C6/PGA3_OF
AIO
REFHI
DAC12
DAC12
ADC Inputs
A0 to A15
C2/PGA3_IN
ADC-A
12-bits
CTRIP3L
Digital
Filter
CMPSS3
Input MUX
CMP3_LN
CMP3_LP
CTRIPOUT3L
REFLO
Analog Group 5
Comparator Subsystem 4
CMP4_HP
CMP4_HN
CTRIP4H
Digital
Filter
AIO
A6/PGA5_OF
C4/PGA5_IN
VDDA or VDAC
CTRIPOUT4H
VREFHI VDAC
DACREFSEL
DAC12
DAC12
CMPSS5
Input MUX
CTRIP4L
Digital
Filter
CMP4_LN
CMP4_LP
CTRIPOUT4L
12-bit
Buffered
DAC-B
DACB_OUT
Comparator Subsystem 5
Analog Group 2
CMP5_HP
CMP5_HN
CTRIP5H
Digital
Filter
AIO
A4/B8/PGA2_OF
VDDA or VDAC
CTRIPOUT5H
PGA2
DAC12
DAC12
C1/PGA2_IN
PGA2_GND/
PGA4_GND/
PGA6_GND/
CMPSS2
Input MUX
CTRIP5L
Digital
Filter
CMP5_LN
CMP5_LP
CTRIPOUT5L
Analog Group 4
AIO
B4/C8/PGA4_OF
C3/PGA4_IN
PGA4
REFHI
CMPSS4
Input MUX
ADC Inputs
B0 to B15
ADC-B
12-bits
REFLO
Comparator Subsystem 7
CMP7_HP
CMP7_LP
PGA6(A)
CTRIP7H
Digital
Filter
VDDA or VDAC
CTRIPOUT7H
DAC12
DAC12
CTRIP7L
Digital
Filter
CTRIPOUT7L
Analog Group 7
AIO
A10/B1/C10
REFHI
CMPSS7
Input MUX
ADC Inputs
C0 to C15
ADC-C
12-bits
REFLO
CMPSS
Inputs
Copyright © 2017, Texas Instruments Incorporated
A. This PGA has no input/output connections on this package, but should be enabled and disabled at the same time as other PGAs with a
shared PGA ground.
Figure 7-29. Analog Subsystem Block Diagram (64-Pin PM LQFP)
Copyright © 2021 Texas Instruments Incorporated
94
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
VREFHIA
VREFLOA
Comparator Subsystem 1
CMP1_HP
CTRIP1H
Digital
Filter
CMP1_HN
VDDA or VDAC
CTRIPOUT1H
VREFHI VDAC
DACREFSEL
DAC12
DAC12
Misc. Analog
CTRIP1L
Digital
Filter
A0/B15/C15/DACA_OUT
A1/DACB_OUT
CMP1_LN
CMP1_LP
CTRIPOUT1L
Temp
Sensor
AIO
12-bit
Buffered
DAC-A
DACA_OUT
Comparator Subsystem 2
CMP2_HP
CMP2_HN
CTRIP2H
Digital
Filter
VDDA or VDAC
CTRIPOUT2H
Analog Group 1
Reference Circuit A
ANAREFASEL
DAC12
DAC12
AIO
A2/B6/PGA1_OF
CTRIP2L
Digital
Filter
CMP2_LN
CMP2_LP
PGA1
Vref
CTRIPOUT2L
C0/PGA1_IN
PGA1_GND/
PGA3_GND/
PGA5_GND/
CMPSS1
Input MUX
REFLO
Comparator Subsystem 3
CMP3_HP
CMP3_HN
CTRIP3H
Analog Group 3
Digital
Filter
VDDA or VDAC
CTRIPOUT3H
B3/VDAC
B2/C6/PGA3_OF
AIO
REFHI
DAC12
DAC12
ADC Inputs
A0 to A15
PGA3
C2/PGA3_IN
ADC-A
12-bits
CTRIP3L
Digital
Filter
CMPSS3
Input MUX
CMP3_LN
CMP3_LP
CTRIPOUT3L
REFLO
Comparator Subsystem 4
CMP4_HP
CMP4_HN
CTRIP4H
Digital
Filter
VDDA or VDAC
CTRIPOUT4H
VREFHI VDAC
DACREFSEL
PGA5(A)
DAC12
DAC12
CTRIP4L
Digital
Filter
CMP4_LN
CMP4_LP
CTRIPOUT4L
12-bit
Buffered
DAC-B
DACB_OUT
Analog Group 2
AIO
A4/B8/PGA2_OF
PGA2
C1/PGA2_IN
PGA2_GND/
PGA4_GND/
PGA6_GND/
CMPSS2
Input MUX
Analog Group 4
AIO
B4/C8/PGA4_OF
C3/PGA4_IN
PGA4
REFHI
CMPSS4
Input MUX
ADC Inputs
B0 to B15
ADC-B
12-bits
REFLO
Comparator Subsystem 7
CMP7_HP
CMP7_LP
PGA6(A)
CTRIP7H
Digital
Filter
VDDA or VDAC
CTRIPOUT7H
DAC12
DAC12
CTRIP7L
Digital
Filter
CTRIPOUT7L
Analog Group 7
AIO
A10/B1/C10
REFHI
CMPSS7
Input MUX
ADC Inputs
C0 to C15
ADC-C
12-bits
REFLO
CMPSS
Inputs
Copyright © 2017, Texas Instruments Incorporated
A. This PGA has no input/output connections on this package, but should be enabled and disabled at the same time as other PGAs with a
shared PGA ground.
Figure 7-30. Analog Subsystem Block Diagram (56-Pin RSH VQFN)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
95
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
Figure 7-31 shows the analog group connections. See Table 1-1 for the specific connections for each group for
each package. Table 1-1 provides descriptions of the analog signals.
CMPSSx Input MUX
CMPxHPMX
PGAx_OF
Gx_ADCC
PGAx_IN
CMPx_HP0
CMPx_HP1
CMPx_HP2
CMPx_HP3
CMPx_HP4
0
1
2
3
4
CMPx_HP
Gx_ADCAB
CMPxHNMX
CMPxLNMX
Gx_ADCAB
Gx_ADCC
CMPx_HN0
CMPx_HN1
0
1
CMPx_HN
CMPx_LN
Gx_ADCAB
Gx_ADCC
CMPx_LN0
CMPx_LN1
0
1
CMPxLPMX
PGAx_OF
Gx_ADCC
PGAx_IN
CMPx_LP0
CMPx_LP1
CMPx_LP2
CMPx_LP3
CMPx_LP4
0
1
2
3
4
CMPx_LP
Gx_ADCAB
Gx_ADCAB
PGAx_OF
Gx_ADCC
Gx_ADCAB
PGAx_OF
Gx_ADCC
AIO(B)
AIO(B)
AIO(B)
PGACTL[FILTRESSEL]
RFILTER
(A)
(C)
VDDA
PGAx_IN
+
PGACTL[PGAEN]
PGAx
PGAx_OUT
œ
VSSA
RGND
ROUT
PGAx_GND
PGACTL[GAIN]
A. On lower pin-count packages, the input to Gx_ADCC will share a pin with the PGA input. If the PGA input is unused, then the ADCC
input can allow the pin to be used as an ADC input, a negative comparator input, or a digital input.
B. AIOs support digital input mode only.
C. The PGA RFILTER path is not available on some device revisions. See the TMS320F28004x MCUs Silicon Errata for more information.
Figure 7-31. Analog Group Connections
Copyright © 2021 Texas Instruments Incorporated
96
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
Table 7-11. Analog Pins and Internal Connections
PACKAGE
ALWAYS CONNECTED (NO MUX)
COMPARATOR SUBSYSTEM (MUX)
GROUP
NAME
PIN NAME
AIO INPUT
100 64 56
HIGH HIGH LOW LOW
POSITIVE NEGATIVE POSITIVE NEGATIVE
ADCA
ADCB
ADCC
PGA
DAC
PZ
PM RSH
VREFHIA
VREFHIB
VREFHIC
VREFLOA
VREFLOB
VREFLOC
-
-
-
-
-
-
25
16
17
14
15
24
27
26
A13
B13
C13
Analog Group 1
A3
CMP1
HPMXSEL HNMXSEL LPMXSEL LNMXSEL
A3
G1_ADCAB
PGA1_OF
10
9
AIO233
AIO224
AIO237
= 3
= 0
= 3
= 0
HPMXSEL
= 0
LPMXSEL
= 0
A2/B6/PGA1_OF
9
8
10
9
A2
B6
PGA1_OF
PGA1_IN
HPMXSEL HNMXSEL LPMXSEL LNMXSEL
C0
G1_ADCC
PGA1_IN
19
18
14
C0
= 1
= 1
= 1
= 1
12
10
HPMXSEL
= 2
LPMXSEL
= 2
PGA1_IN
PGA1_GN
D
PGA1_GND
-
PGA1_GND
PGA1_OUT(1)
PGA1_OU
T
HPMXSEL
= 4
LPMXSEL
= 4
A11
B7
B8
Analog Group 2
A5
CMP2
HPMXSEL HNMXSEL LPMXSEL LNMXSEL
A5
G2_ADCAB
PGA2_OF
35
36
29
30
32
AIO234
AIO225
AIO238
= 3
= 0
= 3
= 0
HPMXSEL
= 0
LPMXSEL
= 0
A4/B8/PGA2_OF
23
18
20
21
16
18
A4
PGA2_OF
PGA2_IN
HPMXSEL HNMXSEL LPMXSEL LNMXSEL
C1
G2_ADCC
PGA2_IN
C1
= 1
= 1
= 1
= 1
HPMXSEL
= 2
LPMXSEL
= 2
PGA2_IN
PGA2_GN
D
PGA2_GND
-
PGA2_GND
PGA2_OUT(1)
PGA2_OU
T
HPMXSEL
= 4
LPMXSEL
= 4
A12
B9
Analog Group 3
CMP3
HPMXSEL HNMXSEL LPMXSEL LNMXSEL
B3/VDAC
B2/C6/PGA3_OF
C2
G3_ADCAB
PGA3_OF
8
8
7
7
6
B3
B2
VDAC
AIO242
AIO226
AIO244
= 3
= 0
= 3
= 0
HPMXSEL
= 0
LPMXSEL
= 0
7
C6
C2
PGA3_OF
PGA3_IN
HPMXSEL HNMXSEL LPMXSEL LNMXSEL
G3_ADCC
PGA3_IN
21
20
15
= 1
= 1
= 1
= 1
13
10
11
9
HPMXSEL
= 2
LPMXSEL
= 2
PGA3_IN
PGA3_GND
-
PGA3_GN
D
PGA3_GND
PGA3_OUT(1)
PGA3_OU
T
HPMXSEL
= 4
LPMXSEL
= 4
B10
C7
Analog Group 4
CMP4
HPMXSEL HNMXSEL LPMXSEL LNMXSEL
B5
G4_ADCAB
PGA4_OF
B5
B4
AIO243
AIO227
AIO245
= 3
= 0
= 3
= 0
HPMXSEL
= 0
LPMXSEL
= 0
B4/C8/PGA4_OF
39
31
32
24
19
20
22
17
18
C8
C3
PGA4_OF
PGA4_IN
HPMXSEL HNMXSEL LPMXSEL LNMXSEL
C3
G4_ADCC
PGA4_IN
= 1
= 1
= 1
= 1
HPMXSEL
= 2
LPMXSEL
= 2
PGA4_IN
PGA4_GN
D
PGA4_GND
-
PGA4_GND
PGA4_OUT(1)
PGA4_OU
T
HPMXSEL
= 4
LPMXSEL
= 4
B11
C9
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
97
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
Table 7-11. Analog Pins and Internal Connections (continued)
PACKAGE
ALWAYS CONNECTED (NO MUX)
COMPARATOR SUBSYSTEM (MUX)
GROUP
NAME
PIN NAME
AIO INPUT
100 64 56
HIGH HIGH LOW LOW
ADCA
ADCB
ADCC
PGA
DAC
PZ
PM RSH
Analog Group 5
POSITIVE NEGATIVE POSITIVE NEGATIVE
CMP5
HPMXSEL HNMXSEL LPMXSEL LNMXSEL
A7
G5_ADCAB
PGA5_OF
A7
AIO235
AIO228
AIO239
= 3
= 0
= 3
= 0
HPMXSEL
= 0
LPMXSEL
= 0
A6/PGA5_OF
6
6
A6
PGA5_OF
PGA5_IN
HPMXSEL HNMXSEL LPMXSEL LNMXSEL
C4
G5_ADCC
PGA5_IN
17
16
13
C4
= 1
= 1
= 1
= 1
11
10
HPMXSEL
= 2
LPMXSEL
= 2
PGA5_IN
PGA5_GN
D
PGA5_GND
-
PGA5_GND
PGA5_OUT(1)
9
PGA5_OU
T
HPMXSEL
= 4
LPMXSEL
= 4
A14
Analog Group 6
A9
CMP6
HPMXSEL HNMXSEL LPMXSEL LNMXSEL
A9
G6_ADCAB
PGA6_OF
38
37
AIO236
AIO229
AIO240
= 3
= 0
= 3
= 0
HPMXSEL
= 0
LPMXSEL
= 0
A8/PGA6_OF
A8
PGA6_OF
PGA6_IN
HPMXSEL HNMXSEL LPMXSEL LNMXSEL
C5
G6_ADCC
PGA6_IN
C5
= 1
= 1
= 1
= 1
28
32
HPMXSEL
= 2
LPMXSEL
= 2
PGA6_IN
PGA6_GN
D
PGA6_GND
-
PGA6_GND
PGA6_OUT(1)
20
18
PGA6_OU
T
HPMXSEL
= 4
LPMXSEL
= 4
A15
Analog Group 7
CMP7
HPMXSEL HNMXSEL LPMXSEL LNMXSEL
B0
G7_ADCAB
PGA7_OF(2)
G7_ADCC
41
40
44
43
42
B0
B1
AIO241
AIO230
AIO246
= 3
= 0
= 3
= 0
HPMXSEL
= 0
LPMXSEL
= 0
A10/B1/C10/PGA7_OF
25
23
A10
C10
C14
PGA7_OF
PGA7_IN
HPMXSEL HNMXSEL LPMXSEL LNMXSEL
C14
= 1
= 1
= 1
= 1
HPMXSEL
= 2
LPMXSEL
= 2
PGA7_IN
PGA7_IN
PGA7_GN
D
PGA7_GND
-
PGA7_GND
PGA7_OUT(1)
PGA7_OU
T
HPMXSEL
= 4
LPMXSEL
= 4
B12
B15
C11
Other Analog
DACA_OU
T
A0/B15/C15/DACA_OUT
A1/DACB_OUT
23
22
15
14
13
12
A0
A1
C15
AIO231
DACB_OU
T
AIO232
AIO247
C12
-
C12
TempSensor(1)
B14
(1) Internal connection only; does not come to a device pin.
(2) PGA functionality not available on 64-pin and 56-pin packages.
Table 7-12. Analog Signal Descriptions
SIGNAL NAME
DESCRIPTION
AIOx
Ax
Digital input on ADC pin
ADC A Input
Bx
ADC B Input
Cx
ADC C Input
CMPx_DACH
CMPx_DACL
CMPx_HNy
CMPx_HPy
Comparator subsystem high DAC output
Comparator subsystem low DAC output
Comparator subsystem high comparator negative input
Comparator subsystem high comparator positive input
Copyright © 2021 Texas Instruments Incorporated
98
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
Table 7-12. Analog Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
CMPx_LNy
CMPx_LPy
DACx_OUT
PGAx_GND
PGAx_IN
Comparator subsystem low comparator negative input
Comparator subsystem low comparator positive input
Buffered DAC Output
PGA Ground
PGA Input
PGAx_OF
PGA Output for filter
PGAx_OUT
TempSensor
PGA Output to internal ADC
Internal temperature sensor
Optional external reference voltage for on-chip DACs. There is a 100-pF capacitor to VSSA on this pin whether
used for ADC input or DAC reference which cannot be disabled. If this pin is used as a reference for the on-
chip DACs, place at least a 1-µF capacitor on this pin.
VDAC
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
99
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
7.10.1 Analog-to-Digital Converter (ADC)
The ADC module described here is a successive approximation (SAR) style ADC with resolution of 12 bits. This
section refers to the analog circuits of the converter as the “core,” and includes the channel-select MUX, the
sample-and-hold (S/H) circuit, the successive approximation circuits, voltage reference circuits, and other analog
support circuits. The digital circuits of the converter are referred to as the “wrapper” and include logic for
programmable conversions, result registers, interfaces to analog circuits, interfaces to the peripheral buses,
post-processing circuits, and interfaces to other on-chip modules.
Each ADC module consists of a single sample-and-hold (S/H) circuit. The ADC module is designed to be
duplicated multiple times on the same chip, allowing simultaneous sampling or independent operation of multiple
ADCs. The ADC wrapper is start-of-conversion (SOC)-based (see the SOC Principle of Operation section of the
Analog-to-Digital Converter (ADC) chapter in the TMS320F28004x Microcontrollers Technical Reference
Manual).
Each ADC has the following features:
•
•
•
•
•
•
•
•
Resolution of 12 bits
Ratiometric external reference set by VREFHI/VREFLO
Selectable internal reference of 2.5 V or 3.3 V
Single-ended signaling
Input multiplexer with up to 16 channels
16 configurable SOCs
16 individually addressable result registers
Multiple trigger sources
– S/W: software immediate start
– All ePWMs: ADCSOC A or B
– GPIO XINT2
– CPU Timers 0/1/2
– ADCINT1/2
•
•
•
Four flexible PIE interrupts
Burst-mode triggering option
Four post-processing blocks, each with:
– Saturating offset calibration
– Error from setpoint calculation
– High, low, and zero-crossing compare, with interrupt and ePWM trip capability
– Trigger-to-sample delay capture
Note
Not every channel may be pinned out from all ADCs. See Section 6 to determine which channels are
available.
Copyright © 2021 Texas Instruments Incorporated
100 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
The block diagram for the ADC core and ADC wrapper are shown in Figure 7-32.
Analog-to-Digital Core
Analog-to-Digital Wrapper Logic
Input Circuit
SOCx (0-15)
CHSEL
[15:0]
[15:0]
[15:0]
SOC Arbitration
& Control
ACQPS
CHSEL
ADCIN0
ADCIN1
ADCIN2
ADCIN3
ADCIN4
ADCIN5
ADCIN6
ADCIN7
ADCIN8
ADCIN9
ADCIN10
ADCIN11
ADCIN12
ADCIN13
ADCIN14
ADCIN15
0
1
ADCSOC
2
3
.
.
.
.
.
.
4
5
ADCCOUNTER
TRIGGER[15:0]
6
VIN
+
DOUT
7
8
VIN-
9
10
11
12
13
14
15
SOC Delay
Timestamp
Trigger
Timestamp
Converter
S/H Circuit
RESULT
-
+
ADCPPBxOFFCAL
ꢀ
saturate
+
ADCPPBxOFFREF
-
ADCPPBxRESULT
ADCEVT
ꢀ
VREFHI
Event
Logic
CONFIG
ADCEVTINT
Bandgap
Reference Circuit
1.65-V Output
(3.3-V Range)
or
1
Post Processing Block (1-4)
Interrupt Block (1-4)
0
2.5-V Output
(2.5-V Range)
ADCINT1-4
VREFLO
Analog System Control
ANAREFSEL
ANAREFx2PSSEL
Reference Voltage Levels
Figure 7-32. ADC Module Block Diagram
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 101
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
7.10.1.1 ADC Configurability
Some ADC configurations are individually controlled by the SOCs, while others are globally controlled per ADC
module. Table 7-13 summarizes the basic ADC options and their level of configurability.
Table 7-13. ADC Options and Configuration Levels
OPTIONS
CONFIGURABILITY
Clock
Per module(1)
Resolution
Signal mode
Not configurable (12-bit resolution only)
Not configurable (single-ended signal mode only)
Reference voltage source
Trigger source
Per module
Per SOC(1)
Per SOC
Converted channel
Acquisition window duration
EOC location
Per SOC(1)
Per module
Per module(1)
Burst mode
(1) Writing these values differently to different ADC modules could cause the ADCs to operate
asynchronously. For guidance on when the ADCs are operating synchronously or asynchronously,
see the Ensuring Synchronous Operation section of the Analog-to-Digital Converter (ADC) chapter
in the TMS320F28004x Microcontrollers Technical Reference Manual.
7.10.1.1.1 Signal Mode
The ADC supports single-ended signaling. In single-ended mode, the input voltage to the converter is sampled
through a single pin (ADCINx), referenced to VREFLO. Figure 7-33 shows the single-ended signaling mode.
Pin Voltage
VREFHI
VREFHI
ADCINx
ADCINx
ADC
VREFHI/2
VREFLO
VREFLO
(VSSA)
Digital Output
2n - 1
ADC Vin
0
Figure 7-33. Single-ended Signaling Mode
Copyright © 2021 Texas Instruments Incorporated
102 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
7.10.1.2 ADC Electrical Data and Timing
Table 5-41 lists the ADC operating conditions. Table 5-42 lists the ADC electrical characteristics.
7.10.1.2.1 ADC Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
ADCCLK (derived from PERx.SYSCLK)
Sample rate
TEST CONDITIONS
MIN
TYP
MAX
50
UNIT
MHz
5
100-MHz SYSCLK
3.45
MSPS
Sample window duration (set by ACQPS and
PERx.SYSCLK)(1)
With 50 Ω or less Rs
75
ns
VREFHI
External Reference
2.4
2.5 or 3.0
1.65
VDDA
V
V
V
V
V
V
V
V
Internal Reference = 3.3V Range
Internal Reference = 2.5V Range
VREFHI(2)
2.5
VREFLO
VSSA
VSSA
VSSA
VDDA
3.3
VREFHI - VREFLO
External Reference
2.4
Internal Reference = 3.3 V Range
Internal Reference = 2.5 V Range
External Reference
0
0
Conversion range
2.5
VREFLO
VREFHI
(1) The sample window must also be at least as long as 1 ADCCLK cycle for correct ADC operation.
(2) In internal reference mode, the reference voltage is driven out of the VREFHI pin by the device. The user should not drive a voltage
into the pin in this mode.
Note
The ADC inputs should be kept below VDDA + 0.3 V during operation. If an ADC input exceeds this
level, the VREF internal to the device may be disturbed, which can impact results for other ADC or
DAC inputs using the same VREF
.
Note
The VREFHI pin must be kept below VDDA + 0.3 V to ensure proper functional operation. If the
VREFHI pin exceeds this level, a blocking circuit may activate, and the internal value of VREFHI may
float to 0 V internally, giving improper ADC conversion or DAC output.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 103
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
UNIT
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
7.10.1.2.2 ADC Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
General
ADCCLK Conversion Cycles
Power Up Time
100-MHz SYSCLK
10.1
11 ADCCLKs
External Reference mode
Internal Reference mode
500
µs
µs
5000
5000
Internal Reference mode, when switching between
2.5-V range and 3.3-V range.
µs
µA
µF
VREFHI input current(1)
130
Internal Reference Capacitor
Value(2)
2.2
2.2
External Reference Capacitor
Value(2)
µF
DC Characteristics
Internal reference
External reference
–45
–5
45
5
Gain Error
LSB
±3
±2
Offset Error
–5
5
LSB
LSB
LSB
LSB
LSB
LSB
LSB
Channel-to-Channel Gain Error
Channel-to-Channel Offset Error
ADC-to-ADC Gain Error
ADC-to-ADC Offset Error
DNL Error
±2
±2
Identical VREFHI and VREFLO for all ADCs
Identical VREFHI and VREFLO for all ADCs
±4
±2
>–1
–2
±0.5
±1.0
1
2
1
INL Error
VREFHI = 2.5 V, synchronous ADCs
VREFHI = 2.5 V, asynchronous ADCs
–1
ADC-to-ADC Isolation
LSBs
Not Supported
AC Characteristics
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from X1
68.8
60.1
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from
INTOSC
SNR(3)
dB
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from X1,
VDD supplied from internal DC-DC regulator(4)
67.5
THD(3)
VREFHI = 2.5 V, fin = 100 kHz
–80.6
79.2
68.5
dB
dB
SFDR(3)
VREFHI = 2.5 V, fin = 100 kHz
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from X1
SINAD(3)
dB
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from
INTOSC
60.0
11.0
11.0
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from
X1, Single ADC
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from
X1, synchronous ADCs
ENOB(3)
bits
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from
X1, asynchronous ADCs
Not
Supported
Copyright © 2021 Texas Instruments Incorporated
104 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD = 1.2-V DC + 100mV
60
DC up to Sine at 1 kHz
VDD = 1.2-V DC + 100 mV
DC up to Sine at 300 kHz
57
PSRR
dB
VDDA = 3.3-V DC + 200 mV
DC up to Sine at 1 kHz
60
57
VDDA = 3.3-V DC + 200 mV
Sine at 900 kHz
(1) Load current on VREFHI increases when ADC input is greater than VDDA. This causes inaccurate conversions.
(2) A ceramic capacitor with package size of 0805 or smaller is preferred. Up to ±20% tolerance is acceptable.
(3) IO activity is minimized on pins adjacent to ADC input and VREFHI pins as part of best practices to reduce capacitive coupling and
crosstalk.
(4) Noise impact from the DCDC regulator to the ADC will be strongly dependent on PCB layout.
7.10.1.2.3 ADC Input Model
The ADC input characteristics are given by Table 7-14 and Figure 7-34.
Table 7-14. Input Model Parameters
DESCRIPTION
REFERENCE MODE
VALUE
Cp
Parasitic input capacitance
All
See Table 7-15
External Reference, 2.5-V Internal
Reference
500 Ω
860 Ω
Ron
Sampling switch resistance
3.3-V Internal Reference
External Reference, 2.5-V Internal
Reference
12.5 pF
Ch
Rs
Sampling capacitor
3.3-V Internal Reference
All
7.5 pF
50 Ω
Nominal source impedance
ADC
ADCINx
Rs
Switch
Ron
AC
Cp
Ch
VREFLO
Figure 7-34. Input Model
This input model should be used with actual signal source impedance to determine the acquisition window
duration. For more information, see the Choosing an Acquisition Window Duration section of the Analog-to-
Digital Converter (ADC) chapter in the TMS320F28004x Microcontrollers Technical Reference Manual.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 105
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
Table 7-15 lists the parasitic capacitance on each channel.
Table 7-15. Per-Channel Parasitic Capacitance
Cp (pF)
ADC CHANNEL
COMPARATOR DISABLED
COMPARATOR ENABLED
ADCINA0
ADCINA1
ADCINA2
ADCINA3
ADCINA4
ADCINA5
ADCINA6
ADCINA7
ADCINA8
ADCINA9
ADCINA10
ADCINB0
ADCINB1
ADCINB2
ADCINB3(1)
ADCINB4
ADCINB5
ADCINB6
ADCINB8
ADCINB15
ADCINC0
ADCINC1
ADCINC2
ADCINC3
ADCINC4
ADCINC5
ADCINC6
ADCINC8
ADCINC10
ADCINC12
ADCINC14
ADCINC15
12.7
13.7
9.2
15.2
16.2
11.7
9.4
6.9
9.2
11.7
10
7.5
8.0
10.5
9.5
7.0
10.0
8.1
12.5
10.6
11.8
9.6
9.3
7.1
9.3
11.8
12.1
128.1
11.3
9.6
9.6
125.6
8.8
7.1
9.2
11.7
11.7
15.2
8.9
9.2
12.7
6.4
6.1
8.6
5.24
5.5
7.74
8
6.2
8.7
5.6
8.1
9.6
12.1
11.3
11.8
6.6
8.8
9.3
4.1
4.5
7
12.7
15.2
(1) This pin is also used to supply reference voltage for COMPDAC and GPDAC, and includes an
internal decoupling capacitor.
Copyright © 2021 Texas Instruments Incorporated
106 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
7.10.1.2.4 ADC Timing Diagrams
Figure 7-35 shows the ADC conversion timings for two SOCs given the following assumptions:
•
•
•
•
SOC0 and SOC1 are configured to use the same trigger.
No other SOCs are converting or pending when the trigger occurs.
The round-robin pointer is in a state that causes SOC0 to convert first.
ADCINTSEL is configured to set an ADCINT flag upon end of conversion for SOC0 (whether this flag
propagates through to the CPU to cause an interrupt is determined by the configurations in the PIE module).
Table 7-16 lists the descriptions of the ADC timing parameters. Table 7-17 lists the ADC timings.
Sample n
Input on SOC0.CHSEL
Input on SOC1.CHSEL
Sample n+1
ADC S+H
SOC0
SOC1
SYSCLK
ADCCLK
ADCTRIG
ADCSOCFLG.SOC0
ADCSOCFLG.SOC1
ADCRESULT0
Sample n
(old data)
(old data)
ADCRESULT1
Sample n+1
ADCINTFLG.ADCINTx
tSH
tLAT
tEOC
tINT
Figure 7-35. ADC Timings
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 107
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
Table 7-16. ADC Timing Parameters
PARAMETER
DESCRIPTION
The duration of the S+H window.
At the end of this window, the value on the S+H capacitor becomes the voltage to be converted into a digital
value. The duration is given by (ACQPS + 1) SYSCLK cycles. ACQPS can be configured individually for each
SOC, so tSH will not necessarily be the same for different SOCs.
tSH
Note: The value on the S+H capacitor will be captured approximately 5 ns before the end of the S+H window
regardless of device clock settings.
The time from the end of the S+H window until the ADC results latch in the ADCRESULTx register.
tLAT
If the ADCRESULTx register is read before this time, the previous conversion results will be returned.
The time from the end of the S+H window until the S+H window for the next ADC conversion can begin. The
subsequent sample can start before the conversion results are latched.
tEOC
The time from the end of the S+H window until an ADCINT flag is set (if configured).
If the INTPULSEPOS bit in the ADCCTL1 register is set, tINT will coincide with the conversion results being
latched into the result register.
If the INTPULSEPOS bit is 0, tINT will coincide with the end of the S+H window. If tINT triggers a read of the
ADC result register (directly through DMA or indirectly by triggering an ISR that reads the result), care must be
taken to ensure the read occurs after the results latch (otherwise, the previous results will be read).
tINT
If the INTPULSEPOS bit is 0, and the OFFSET field in the ADCINTCYCLE register is not 0, then there will be a
delay of OFFSET SYSCLK cycles before the ADCINT flag is set. This delay can be used to enter the ISR or
trigger the DMA at exactly the time the sample is ready.
Table 7-17. ADC Timings
ADCCLK PRESCALE
SYSCLK CYCLES
ADCCLK CYCLES
RATIO
ADCCLK:SYSCLK
(1)
(2)
ADCCTL2 [PRESCALE]
tEOC
tLAT
tINT(EARLY)
tINT(LATE)
tEOC
0
2
1
2
3
4
5
6
7
8
11
21
31
41
51
61
71
81
13
1
1
1
1
1
1
1
1
11
21
31
41
51
61
71
81
11
23
34
44
55
65
76
86
10.5
10.3
10.3
10.2
10.2
10.1
10.1
4
6
8
10
12
14
(1) Refer to the "ADC: DMA Read of Stale Result" advisory in the TMS320F28004x MCUs Silicon Errata.
(2) By default, tINT occurs one SYSCLK cycle after the S+H window if INTPULSEPOS is 0. This can be changed by writing to the OFFSET
field in the ADCINTCYCLE register.
Copyright © 2021 Texas Instruments Incorporated
108 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
7.10.2 Programmable Gain Amplifier (PGA)
The Programmable Gain Amplifier (PGA) is used to amplify an input voltage for the purpose of increasing the
effective resolution of the downstream ADC and CMPSS modules.
The integrated PGA helps to reduce cost and design effort for many control applications that traditionally require
external, stand-alone amplifiers. On-chip integration ensures that the PGA is compatible with the downstream
ADC and CMPSS modules. Software-selectable gain and filter settings make the PGA adaptable to various
performance needs.
The PGA has the following features:
•
•
•
•
Four programmable gain modes: 3x, 6x, 12x, 24x
Internally powered by VDDA and VSSA
Support for Kelvin ground connections using PGA_GND pin
Embedded series resistors for RC filtering
The active component in the PGA is an embedded operational amplifier (op amp) that is configured as a
noninverting amplifier with internal feedback resistors. These internal feedback resistor values are paired to
produce software selectable voltage gains.
Three PGA signals are available at the device pins:
•
•
PGA_IN is the positive input to the PGA op amp. The signal applied to this pin will be amplified by the PGA.
PGA_GND is the Kelvin ground reference for the PGA_IN signal. Ideally, the PGA_GND reference is equal to
VSSA; however, the PGA can tolerate small voltage offsets from VSSA.
•
PGA_OF supports op amp output filtering with RC components. The filtered signal is available for sampling
and monitoring by internal ADC and CMPSS modules. The PGA RFILTER path is not available on some
device revisions. See the TMS320F28004x MCUs Silicon Errata for more information.
PGA_OUT is an internal signal at the op amp output. It is available for sampling and monitoring by the internal
ADC and CMPSS modules. Figure 7-36 shows the PGA block diagram.
VDDA
PGA_IN
+
PGACTL[PGAEN]
PGA_OUT
Op Amp
VSSA
To ADC and CMPSS
To ADC and CMPSS
RFILTER
œ
PGACTL[FILTRESSEL]
RGND
ROUT
PGA_GND
PGACTL[GAIN]
PGA_OF
Figure 7-36. PGA Block Diagram
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 109
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
7.10.2.1 PGA Electrical Data and Timing
Section 7.10.2.1.1 lists the PGA operating conditions. Section 7.10.2.1.2 lists the PGA characteristics.
7.10.2.1.1 PGA Operating Conditions
over recommended operating conditions (unless otherwise noted)
PARAMETER
PGA Output Range(1)
PGA GND Range
TEST CONDITIONS
MIN
VSSA + 0.35
–50
TYP
MAX
VDDA – 0.35
200
UNIT
V
mV
Min ADC S+H
(No Filter; Gain = 3, 6, 12)
Settling within ±1 ADC LSB
Accuracy
160
200
ns
ns
Min ADC S+H
(No Filter; Gain = 24)
Settling within ±2 ADC LSB
Accuracy
(1) This is the linear output range of the PGA. The PGA can output voltages outside this range, but the voltages will not be linear.
7.10.2.1.2 PGA Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
General
Gain Settings
3, 6, 12, 24
Input Bias Current
Short Circuit Current
2
nA
35
mA
Full Scale Step Response
(No Filter)
Settling within ±2 ADC LSB
Accuracy
450
10
ns
Settling Time
Slew Rate
RGND
Gain Switching
Gain = 3
µs
V/µs
V/µs
V/µs
V/µs
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
Ω
15
31
61
78
20
37
Gain = 6
Gain = 12
Gain = 24
Gain = 3
73
98
9
Gain = 6
4.5
Gain = 12
Gain = 24
Gain = 3
2.25
1.125
18
ROUT
Gain = 6
22.5
24.75
25.875
190
153
125
96
Gain = 12
Gain = 24
RFILT = 200 Ω
RFILT = 160 Ω
RFILT = 130 Ω
RFILT = 100 Ω
RFILT = 80 Ω
RFILT = 50 Ω
Filter Resistor Targets
145
117
95
234
188
154
120
98
Ω
Ω
71
Ω
55
77
Ω
31
49
66
Ω
Power Up Time
500
µs
DC Characteristics
Gain = 3, 6, 12
Gain = 24
–0.5
–0.8
0.5
0.8
%
%
Gain Error(1)
Gain Temp Coefficient
Offset Error(2)
±0.004
±5.5
%/C
mV
µV/C
Input Referred
Input Referred
–1.5
1.5
Offset Temp Coefficient
Copyright © 2021 Texas Instruments Incorporated
110
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC Code Spread
2.5
12b LSB
AC Characteristics
Bandwidth(3)
All Gain Modes
7
–78
–70
–60
–50
–75
–50
200
MHz
DC
dB
THD(4)
Up to 100 kHz
DC
dB
dB
dB
CMRR
Up to 100 kHz
DC
dB
PSRR(4)
Up to 100 kHz
1 kHz
dB
Noise PSD(4)
nV/sqrt(Hz)
Integrated Noise
(Input Referred)(4)
3 Hz to 30 MHz
100
µV
(1) Includes ADC gain error in external reference mode.
(2) Includes ADC offset error in external reference mode.
(3) 3dB bandwidth.
(4) Performance of PGA alone.
7.10.2.1.3 PGA Typical Characteristics Graphs
Figure 7-37 shows the input bias current versus temperature.
Note
For Figure 7-37, the following conditions apply (unless otherwise noted):
•
•
•
TA = 30°C
VDDA = 3.3 V
VDD = 1.2 V
INPUT BIAS CURRENT vs TEMPERATURE
300
250
200
150
100
50
0V INPUT
1.65V INPUT
3.3V INPUT
0
-50
-100
-40 -20
0
20
40
TEMPERATURE (C)
60
80 100 120 140 160
DPLO
Figure 7-37. Input Bias Current Versus Temperature
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
111
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
7.10.3 Temperature Sensor
7.10.3.1 Temperature Sensor Electrical Data and Timing
The temperature sensor can be used to measure the device junction temperature. The temperature sensor is
sampled through an internal connection to the ADC and translated into a temperature through TI-provided
software. When sampling the temperature sensor, the ADC must meet the acquisition time in Section 7.10.3.1.1.
7.10.3.1.1 Temperature Sensor Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Tacc
tstartup
tSH
Temperature Accuracy
External reference
±15
°C
Start-up time
(TSNSCTL[ENABLE] to
sampling temperature sensor)
500
µs
ns
ADC sample-and-hold time
450
Copyright © 2021 Texas Instruments Incorporated
112
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
7.10.4 Buffered Digital-to-Analog Converter (DAC)
The buffered DAC module consists of an internal 12-bit DAC and an analog output buffer that can drive an
external load. For driving even higher loads than typical, a trade-off can be made between load size and output
voltage swing. For the load conditions of the buffered DAC, see Section 7.10.4.1. The buffered DAC is a
general-purpose DAC that can be used to generate a DC voltage or AC waveforms such as sine waves, square
waves, triangle waves and so forth. Software writes to the DAC value register can take effect immediately or can
be synchronized with EPWMSYNCO events.
Each buffered DAC has the following features:
•
•
•
•
12-bit resolution
Selectable reference voltage source
x1 and x2 gain modes when using internal VREFHI
Ability to synchronize with EPWMSYNCO
The block diagram for the buffered DAC is shown in Figure 7-38.
DACCTL[DACREFSEL]
ANAREFx2P5
VDAC
0
1
DACREF
1.65v
2.5v
0
1
Internal
Reference
Circuit
1
0
VREFHI
ANAREFxSEL
VDDA
DACCTL[LOADMODE]
0
SYSCLK
DACVALS
>
Q
Q
D
12-bit
DAC
DACOUT
Amp
(x1 or x2)
DACVALA
1
D
EPWM1SYNCPER
EPWM2SYNCPER
EPWM3SYNCPER
0
1
2
EN
VSSA
VSSA
...
EPWMnSYNCPER
Y
n-1
DACCTL[MODE]
(Select x1 or x2 Gain)
DACCTL[SYNCSEL]
Figure 7-38. DAC Module Block Diagram
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
113
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
7.10.4.1 Buffered DAC Electrical Data and Timing
Section 7.10.4.1.1 lists the buffered DAC operating conditions. Section 7.10.4.1.2 lists the buffered DAC
electrical characteristics.
7.10.4.1.1 Buffered DAC Operating Conditions
over recommended operating conditions (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
kΩ
pF
V
RL
CL
Resistive Load(2)
5
Capacitive Load
100
VDDA – 0.3
VDDA – 0.6
VDDA
RL = 5 kΩ
0.3
0.6
2.4
VOUT
Valid Output Voltage Range(3)
RL = 1 kΩ
V
Reference Voltage(4)
VDAC or VREFHI
2.5 or 3.0
V
(1) Typical values are measured with VREFHI = 3.3 V and VREFLO = 0 V, unless otherwise noted. Minimum and maximum values are
tested or characterized with VREFHI = 2.5 V and VREFLO = 0 V.
(2) DAC can drive a minimum resistive load of 1 kΩ, but the output range will be limited.
(3) This is the linear output range of the DAC. The DAC can generate voltages outside this range, but the output voltage will not be linear
due to the buffer.
(4) For best PSRR performance, VDAC or VREFHI should be less than VDDA.
7.10.4.1.2 Buffered DAC Electrical Characteristics
over recommended operating conditions (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
12
MAX
UNIT
General
Resolution
bits
mV/V
V-ns
Load Regulation
Glitch Energy
–1
1
1.5
Settling to 2 LSBs after 0.3V-
to-3V transition
Voltage Output Settling Time Full-Scale
2
µs
µs
Voltage Output Settling Time 1/4th Full-Scale Settling to 2 LSBs after 0.3V-
to-0.75V transition
1.6
Slew rate from 0.3V-to-3V
Voltage Output Slew Rate
transition
2.8
4.5
V/µs
5-kΩ Load
Load Transient Settling Time(6)
1-kΩ Load
328
557
ns
ns
kΩ
µs
µs
Reference Input Resistance(2)
TPU Power Up Time
DC Characteristics
VDAC or VREFHI
160
200
240
External Reference mode
Internal Reference mode
500
5000
Offset
Gain
DNL
INL
Offset Error
Midpoint
–10
–2.5
–1
10
2.5
1
mV
% of FSR
LSB
Gain Error(3)
Differential Non Linearity(4)
Endpoint corrected
Endpoint corrected
±0.4
±2
Integral Non Linearity
–5
5
LSB
AC Characteristics
Integrated noise from 100 Hz
to 100 kHz
600
µVrms
Output Noise
Noise density at 10 kHz
1 kHz, 200 KSPS
800
64
nVrms/√Hz
SNR
THD
Signal to Noise Ratio
dB
dB
Total Harmonic Distortion
1 kHz, 200 KSPS
–64.2
Spurious Free Dynamic
Range
SFDR
1 kHz, 200 KSPS
66
dB
Copyright © 2021 Texas Instruments Incorporated
114
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
over recommended operating conditions (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Signal to Noise and Distortion
Ratio
SINAD
PSRR
1 kHz, 200 KSPS
61.7
dB
DC
70
30
dB
dB
Power Supply Rejection
Ratio(5)
100 kHz
(1) Typical values are measured with VREFHI = 3.3 V and VREFLO = 0 V, unless otherwise noted. Minimum and maximum values are
tested or characterized with VREFHI = 2.5 V and VREFLO = 0 V.
(2) Per active Buffered DAC module.
(3) Gain error is calculated for linear output range.
(4) The DAC output is monotonic.
(5) VREFHI = 3.2 V, VDDA = 3.3 V DC + 100 mV Sine.
(6) Settling to within 3LSBs.
Note
The VDAC pin must be kept below VDDA + 0.3 V to ensure proper functional operation. If the VDAC
pin exceeds this level, a blocking circuit may activate, and the internal value of VDAC may float to 0 V
internally, giving improper DAC output.
Note
The VREFHI pin must be kept below VDDA + 0.3 V to ensure proper functional operation. If the
VREFHI pin exceeds this level, a blocking circuit may activate, and the internal value of VREFHI may
float to 0 V internally, giving improper ADC conversion or DAC output.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
115
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
7.10.4.1.3 Buffered DAC Illustrative Graphs
Figure 7-39 shows the buffered DAC offset. Figure 7-40 shows the buffered DAC gain. Figure 7-41 shows the
buffered DAC linearity.
Offset Error
Code 2048
Figure 7-39. Buffered DAC Offset
Actual Gain
Ideal Gain
Code 3722
Code 373
Linear Range
(3.3-V Reference)
Figure 7-40. Buffered DAC Gain
Copyright © 2021 Texas Instruments Incorporated
116
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
Linearity Error
Code 3722
Code 373
Linear Range
(3.3-V Reference)
Figure 7-41. Buffered DAC Linearity
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
117
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
7.10.4.1.4 Buffered DAC Typical Characteristics Graphs
Figure 7-42 to Figure 7-47 show the typical performance for some buffered DAC parameters. Figure 7-42 shows
the DNL. Figure 7-43 shows the INL. Figure 7-44 shows the glitch response (511 to 512 DACVAL) and Figure
7-45 shows the glitch response (512 to 511 DACVAL). Note that the glitch only happens at MSB transitions, with
511-to-512 and 512-to-511 transitions being the worst case. Figure 7-46 shows the 1-kΩ load transient. Figure
7-47 shows the 5-kΩ load transient.
Note
For Figure 7-42 to Figure 7-47, the following conditions apply (unless otherwise noted):
•
•
•
TA = 30°C
VDDA = 3.3 V
VDD = 1.2 V
DNL at VREFHI = 2.5V
INL at VREFHI = 2.5V
0.6
0.4
0.2
0
1.8
1.6
1.4
1.2
1
DACA
DACB
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.2
-0.4
-0.6
-0.8
-1
DACA
DACB
0
500 1000 1500 2000 2500 3000 3500 4000
DACVAL
0
500 1000 1500 2000 2500 3000 3500 4000
DACVAL
DPLO
DPLO
Figure 7-42. DNL
Figure 7-43. INL
GLITCH RESPONSE at VDAC = 2.5V
511 to 512 DACVAL
GLITCH RESPONSE at VDAC = 2.5V
512 to 511 DACVAL
0.33
0.329
0.328
0.327
0.326
0.325
0.324
0.323
0.322
0.321
0.32
0.325
0.323
0.321
0.319
0.317
0.315
0.313
0.311
0.309
0.307
0.305
0.319
0.318
0.317
0.316
0.315
0
100
200
300
TIME (ns)
400
500
600
0
100
200
300
TIME (ns)
400
500
600
DPLO
DPLO
Figure 7-44. Glitch Response – 511 to 512 DACVAL Figure 7-45. Glitch Response – 512 to 511 DACVAL
Copyright © 2021 Texas Instruments Incorporated
118
Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
1K LOAD TRANSIENT at VDAC = 2.5V
5K LOAD TRANSIENT at VDAC = 2.5V
2.4
2.38
2.36
2.34
2.32
2.3
2.4
2.38
2.36
2.34
2.32
2.3
LOAD CONNECTED
LOAD CONNECTED
2.28
2.26
2.24
2.22
2.2
2.28
2.26
2.24
2.22
2.2
0
100
200
300
400
TIME (ns)
500
600
700
800
0
100
200
300
400
TIME (ns)
500
600
700
800
DPLO
DPLO
Figure 7-46. 1-kΩ Load Transient
Figure 7-47. 5-kΩ Load Transient
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
119
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
7.10.5 Comparator Subsystem (CMPSS)
Each CMPSS contains two comparators, two reference 12-bit DACs, two digital filters, and one ramp generator.
Comparators are denoted "H" or "L" within each module, where “H” and “L” represent high and low, respectively.
Each comparator generates a digital output that indicates whether the voltage on the positive input is greater
than the voltage on the negative input. The positive input of the comparator can be driven from an external pin or
by the PGA . The negative input can be driven by an external pin or by the programmable reference 12-bit DAC.
Each comparator output passes through a programmable digital filter that can remove spurious trip signals. An
unfiltered output is also available if filtering is not required. A ramp generator circuit is optionally available to
control the reference 12-bit DAC value for the high comparator in the subsystem. There are two outputs from
each CMPSS module. These two outputs pass through the digital filters and crossbar before connecting to the
ePWM modules or GPIO pin. Figure 7-48 shows the CMPSS connectivity.
Comparator Subsystem 1
CTRIP1H
CTRIP1L
CTRIP2H
CTRIP2L
CMP1_HP
CMP1_HN
CTRIP1H
Digital
Filter
VDDA or VDAC
CTRIPOUT1H
DAC12
DAC12
CTRIP1L
Digital
Filter
CMP1_LN
CMP1_LP
CTRIPOUT1L
ePWM X-BAR
ePWMs
Comparator Subsystem 2
CMP2_HP
CMP2_HN
CTRIP2H
Digital
Filter
VDDA or VDAC
CTRIPOUT2H
DAC12
DAC12
CTRIP7H
CTRIP7L
CTRIP2L
Digital
Filter
CMP2_LN
CMP2_LP
CTRIPOUT2L
CTRIPOUT1H
CTRIPOUT1L
CTRIPOUT2H
CTRIPOUT2L
Comparator Subsystem 7
CMP7_HP
CMP7_HN
CTRIP7H
Digital
Filter
VDDA or VDAC
CTRIPOUT7H
Output X-BAR
GPIO Mux
DAC12
DAC12
CTRIP7L
Digital
Filter
CMP7_LN
CMP7_LP
CTRIPOUT7L
CTRIPOUT7H
CTRIPOUT7L
Figure 7-48. CMPSS Connectivity
Note
Not all packages have all CMPSS pins. See Table 1-1.
Copyright © 2021 Texas Instruments Incorporated
120 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
7.10.5.1 CMPSS Electrical Data and Timing
Section 7.10.5.1.1 lists the comparator electrical characteristics. Figure 7-49 shows the CMPSS comparator
input referred offset. Figure 7-50 shows the CMPSS comparator hysteresis.
7.10.5.1.1 Comparator Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
500
UNIT
µs
TPU
Power-up time
Comparator input (CMPINxx) range
Input referred offset error
0
VDDA
V
Low common mode, inverting
input set to 50 mV
–20
20
mV
1x
12
24
36
48
21
26
30
46
2x
Hysteresis(1)
LSB
3x
4x
Step response
60
ns
Response time (delay from CMPINx input change to
output on ePWM X-BAR or Output X-BAR)
Ramp response (1.65 V/µs)
Ramp response (8.25 mV/µs)
Up to 250 kHz
ns
dB
dB
PSRR
CMRR
Power Supply Rejection Ratio
Common Mode Rejection Ratio
40
(1) The CMPSS DAC is used as the reference to determine how much hysteresis to apply. Therefore, hysteresis will scale with the
CMPSS DAC reference voltage. Hysteresis is available for all comparator input source configurations.
Note
The CMPSS inputs must be kept below VDDA + 0.3 V to ensure proper functional operation. If a
CMPSS input exceeds this level, an internal blocking circuit isolates the internal comparator from the
external pin until the external pin voltage returns below VDDA + 0.3 V. During this time, the internal
comparator input is floating and can decay below VDDA within approximately 0.5 µs. After this time,
the comparator could begin to output an incorrect result depending on the value of the other
comparator input.
Input Referred Offset
CTRIPx
Logic Level
CTRIPx = 1
CTRIPx = 0
COMPINxP
Voltage
0
CMPINxN or
DACxVAL
Figure 7-49. CMPSS Comparator Input Referred Offset
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 121
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
Hysteresis
CTRIPx
Logic Level
CTRIPx = 1
CTRIPx = 0
COMPINxP
Voltage
0
CMPINxN or
DACxVAL
Figure 7-50. CMPSS Comparator Hysteresis
Section 7.10.5.1.2 lists the CMPSS DAC static electrical characteristics.
7.10.5.1.2 CMPSS DAC Static Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
0
TYP
MAX
UNIT
Internal reference
VDDA
CMPSS DAC output range
V
External reference
0
VDAC(4)
Static offset error(1)
Static gain error(1)
Static DNL
–25
–2
25
2
mV
% of FSR
LSB
Endpoint corrected
Endpoint corrected
>–1
–16
4
Static INL
16
LSB
Settling to 1LSB after full-scale output
change
Settling time
Resolution
1
µs
12
bits
Error induced by comparator trip or
CMPSS DAC code change within the
same CMPSS module
CMPSS DAC output disturbance(2)
–100
100
LSB
CMPSS DAC disturbance time(2)
VDAC reference voltage
VDAC load(3)
200
VDDA
10
ns
V
When VDAC is reference
When VDAC is reference
2.4
6
2.5 or 3.0
8
kΩ
(1) Includes comparator input referred errors.
(2) Disturbance error may be present on the CMPSS DAC output for a certain amount of time after a comparator trip.
(3) Per active CMPSS module.
(4) The maximum output voltage is VDDA when VDAC > VDDA.
Copyright © 2021 Texas Instruments Incorporated
122 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
7.10.5.1.3 CMPSS Illustrative Graphs
Figure 7-51 shows the CMPSS DAC static offset. Figure 7-52 shows the CMPSS DAC static gain. Figure 7-53
shows the CMPSS DAC static linearity.
Offset Error
Figure 7-51. CMPSS DAC Static Offset
Ideal Gain
Actual Gain
Figure 7-52. CMPSS DAC Static Gain
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 123
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
Linearity Error
Figure 7-53. CMPSS DAC Static Linearity
Copyright © 2021 Texas Instruments Incorporated
124 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
7.11 Control Peripherals
7.11.1 Enhanced Capture (eCAP)
The Type 1 enhanced capture (eCAP) module is used in systems where accurate timing of external events is
important.
Applications for the eCAP module include:
•
•
•
•
Speed measurements of rotating machinery (for example, toothed sprockets sensed through Hall sensors)
Elapsed time measurements between position sensor pulses
Period and duty cycle measurements of pulse train signals
Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors
The eCAP module includes the following features:
•
•
•
•
•
•
•
•
•
•
•
4-event time-stamp registers (each 32 bits)
Edge polarity selection for up to four sequenced time-stamp capture events
CPU interrupt on any one of the four events
Independent DMA trigger
Single-shot capture of up to four event timestamps
Continuous mode capture of timestamps in a 4-deep circular buffer
Absolute time-stamp capture
Difference (Delta) mode time-stamp capture
128:1 input multiplexer
Event Prescaler
When not used in capture mode, the eCAP module can be configured as a single channel PWM output.
The capture functionality of the Type-1 eCAP is enhanced from the Type-0 eCAP with the following added
features:
•
Event filter reset bit
– Writing a 1 to ECCTL2[CTRFILTRESET] will clear the event filter, the modulo counter, and any pending
interrupts flags. This is useful for initialization and debug.
Modulo counter status bits
•
– The modulo counter (ECCTL2[MODCTRSTS]) indicates which capture register will be loaded next. In the
Type-0 eCAP, it was not possible to know the current state of modulo counter.
DMA trigger source
– eCAPxDMA was added as a DMA trigger. CEVT[1–4] can be configured as the source for eCAPxDMA.
Input multiplexer
•
•
•
– ECCTL0[INPUTSEL] selects one of 128 input signals.
EALLOW protection
– EALLOW protection was added to critical registers.
The Input X-BAR must be used to connect the device input pins to the module. The Output X-BAR must be used
to connect output signals to the OUTPUTXBARx output locations. See Section 6.4.3 and Section 6.4.4.
Figure 7-54 shows the eCAP block diagram.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 125
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
ECCTL2 [ SYNCI_EN, SYNCOSEL, SWSYNC]
ECCTL2[CAP/APWM]
CTRPHS
APWM Mode
(phase register−32 bit)
ECAPxSYNCIN
OVF
RST
CTR_OVF
CTR [0−31]
PRD [0−31]
CMP [0−31]
TSCTR
ECAPxSYNCOUT
PWM
Compare
Logic
Output
X-Bar
(counter−32 bit)
Delta−Mode
32
CTR=PRD
CTR=CMP
CTR [0−31]
PRD [0−31]
32
ECCTL1 [ CAPLDEN, CTRRSTx]
HRCTRL[HRE]
32
32
LD1
CAP1
Polarity
Select
LD
(APRD Active)
APRD
32
shadow
CMP [0−31]
32
HRCTRL[HRE]
32
HRCTRL[HRE]
32
CAP2
Polarity
Select
LD2
LD
Other
Sources
(ACMP Active)
[127:16]
[15:0]
Event
Prescale
Event
32
ACMP
16
qualifier
Input
shadow
LD
ECCTL1[PRESCALE]
HRCTRL[HRE]
32
X-Bar
32
Polarity
Select
LD3
LD4
CAP3
(APRD Shadow)
HRCTRL[HRE]
32
32
CAP4
Polarity
Select
LD
(ACMP Shadow)
Edge Polarity Select
ECCTL1[CAPxPOL]
4
Capture Events
4
CEVT[1:4]
ECAPxDMA_INT
ECCTL2[CTRFILTRESET]
Interrupt
Continuous /
Oneshot
Trigger
and
MODCNTRSTS
CTR_OVF
CTR=PRD
CTR=CMP
Capture Control
ECCTL2[DMAEVTSEL]
Flag
Control
ECAPx
(to ePIE)
ECCTL2 [ REARM, CONT_ONESHT, STOP_WRAP]
Registers: ECEINT, ECFLG, ECCLR, ECFRC
Capture Pulse
HR Input
SYSCLK
HRCLK
(A)
HR Submodule
ECAPx_HRCAL
(to ePIE)
Copyright © 2018, Texas Instruments Incorporated
A. The HRCAP submodule is not available on all eCAP modules; in this case, the high-resolution muxes and hardware are not
implemented.
Figure 7-54. eCAP Block Diagram
Copyright © 2021 Texas Instruments Incorporated
126 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
7.11.1.1 eCAP Electrical Data and Timing
Section 7.11.1.1.1 lists the eCAP timing requirements. Section 7.11.1.1.2 lists the eCAP switching
characteristics.
7.11.1.1.1 eCAP Timing Requirements
MIN
2tc(SCO)
NOM
MAX
UNIT
Asynchronous
Synchronous
tw(CAP)
Capture input pulse width
2tc(SCO)
ns
With input qualifier
1tc(SCO) + tw_(QSW)
7.11.1.1.2 eCAP Switching Charcteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
ns
tw(APWM)
Pulse duration, APWMx output high/low
20
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 127
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
7.11.2 High-Resolution Capture Submodule (HRCAP6–HRCAP7)
The device contains up to two high-resolution capture (HRCAP) submodules. The HRCAP submodule measures
the difference, in time, between pulses asynchronously to the system clock. This submodule is new to the eCAP
Type 1 module, and features many enhancements over the Type 0 HRCAP module.
Applications for the HRCAP include:
•
•
•
•
•
•
•
Capacitive touch applications
High-resolution period and duty-cycle measurements of pulse train cycles
Instantaneous speed measurements
Instantaneous frequency measurements
Voltage measurements across an isolation boundary
Distance/sonar measurement and scanning
Flow measurements
The HRCAP submodule includes the following features:
•
•
•
•
•
•
•
Pulse-width capture in either non-high-resolution or high-resolution modes
Absolute mode pulse-width capture
Continuous or "one-shot" capture
Capture on either falling or rising edge
Continuous mode capture of pulse widths in 4-deep buffer
Hardware calibration logic for precision high-resolution capture
All of the resources in this list are available on any pin using the Input X-BAR.
The HRCAP submodule includes one high-resolution capture channel in addition to a calibration block. The
calibration block allows the HRCAP submodule to be continually recalibrated, at a set interval, with no “down
time”. Because the HRCAP submodule now uses the same hardware as its respective eCAP, if the HRCAP is
used, the corresponding eCAP will be unavailable.
Each high-resolution-capable channel has the following independent key resources.
•
•
•
All hardware of the respective eCAP
High-resolution calibration logic
Dedicated calibration interrupt
Figure 7-55 shows the HRCAP block diagram.
Copyright © 2021 Texas Instruments Incorporated
128 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
ECCTL2 [ SYNCI_EN, SYNCOSEL, SWSYNC]
ECCTL2[CAP/APWM]
CTRPHS
APWM Mode
(phase register−32 bit)
ECAPxSYNCIN
OVF
RST
CTR_OVF
CTR [0−31]
PRD [0−31]
CMP [0−31]
TSCTR
ECAPxSYNCOUT
PWM
Compare
Logic
Output
X-Bar
(counter−32 bit)
Delta−Mode
32
CTR=PRD
CTR=CMP
CTR [0−31]
PRD [0−31]
32
ECCTL1 [ CAPLDEN, CTRRSTx]
HRCTRL[HRE]
32
32
LD1
CAP1
Polarity
Select
LD
(APRD Active)
APRD
32
shadow
CMP [0−31]
32
HRCTRL[HRE]
32
HRCTRL[HRE]
32
CAP2
Polarity
Select
LD2
LD
Other
Sources
(ACMP Active)
[127:16]
[15:0]
Event
Prescale
Event
32
ACMP
16
qualifier
Input
shadow
LD
ECCTL1[PRESCALE]
HRCTRL[HRE]
32
X-Bar
32
Polarity
Select
LD3
LD4
CAP3
(APRD Shadow)
HRCTRL[HRE]
32
32
CAP4
Polarity
Select
LD
(ACMP Shadow)
Edge Polarity Select
ECCTL1[CAPxPOL]
4
Capture Events
4
CEVT[1:4]
ECAPxDMA_INT
ECCTL2[CTRFILTRESET]
Interrupt
Continuous /
Oneshot
Trigger
and
MODCNTRSTS
CTR_OVF
CTR=PRD
CTR=CMP
Capture Control
ECCTL2[DMAEVTSEL]
Flag
Control
ECAPx
(to ePIE)
ECCTL2 [ REARM, CONT_ONESHT, STOP_WRAP]
Registers: ECEINT, ECFLG, ECCLR, ECFRC
Capture Pulse
HR Input
SYSCLK
HRCLK
(A)
HR Submodule
ECAPx_HRCAL
(to ePIE)
Copyright © 2018, Texas Instruments Incorporated
A. The HRCAP submodule is not available on all eCAP modules; in this case, the high-resolution muxes and hardware are not
implemented.
Figure 7-55. HRCAP Block Diagram
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 129
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
7.11.2.1 HRCAP Electrical Data and Timing
Section 7.11.2.1.1 lists the HRCAP switching characteristics. Figure 7-56 shows the HRCAP accuracy precision
and resolution. Figure 7-57 shows the HRCAP standard deviation characteristics.
7.11.2.1.1 HRCAP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ns
Input pulse width
110
Measurement length ≤ 5 µs
Measurement length > 5 µs
±390
±450
540
ps
Accuracy(1) (2) (3) (4)
1450
ps
Standard deviation
Resolution
See Figure 7-57
300
ps
(1) Value obtained using an oscillator of 100 PPM, oscillator accuracy directly affects the HRCAP accuracy.
(2) Measurement is completed using rising-rising or falling-falling edges
(3) Opposite polarity edges will have an additional inaccuracy due to the difference between VIH and VIL. This effect is dependent on the
signal’s slew rate.
(4) Accuracy only applies to time-converted measurements.
HRCAP’s Mean
Accuracy
Resolution
(Step Size)
Precision
(Standard Deviation)
Actual
Input Signal
A. The HRCAP has some variation in performance, this results in a probability distribution which is described using the following terms:
•
•
•
Accuracy: The time difference between the input signal and the mean of the HRCAP’s distribution.
Precision: The width of the HRCAP’s distribution, this is given as a standard deviation.
Resolution: The minimum measurable increment.
Figure 7-56. HRCAP Accuracy Precision and Resolution
Copyright © 2021 Texas Instruments Incorporated
130 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
2
1.8
1.6
1.4
1.2
1
7.4
Typical Core Conditions
Noisy Core Supply
6.66
5.92
5.18
4.44
3.7
0.8
0.6
0.4
0.2
2.96
2.22
1.48
0.74
0
1000
2000
3000
4000
5000
Time Between Edges(nS)
6000
7000
8000
9000
10000
A. Typical core conditions: All peripheral clocks are enabled.
B. Noisy core supply: All core clocks are enabled and disabled with a regular period during the measurement. This resulted in the 1.2-V rail
experiencing a 18.5-mA swing during the measurement.
C. Fluctuations in current and voltage on the 1.2-V rail cause the standard deviation of the HRCAP to rise. Care should be taken to ensure
that the 1.2-V supply is clean, and that noisy internal events, such as enabling and disabling clock trees, have been minimized while
using the HRCAP.
Figure 7-57. HRCAP Standard Deviation Characteristics
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 131
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
7.11.3 Enhanced Pulse Width Modulator (ePWM)
The ePWM peripheral is a key element in controlling many of the power electronic systems found in both
commercial and industrial equipment. The ePWM type-4 module generates complex pulse width waveforms with
minimal CPU overhead. Some of the highlights of the ePWM type-4 module include complex waveform
generation, dead-band generation, a flexible synchronization scheme, advanced trip-zone functionality, and
global register reload capabilities.
Figure 7-58 shows the signal interconnections with the ePWM. Figure 7-59 shows the ePWM trip input
connectivity.
Copyright © 2021 Texas Instruments Incorporated
132 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
TBCTL2[SYNCOSELX]
Time-Base (TB)
Disable
00
01
10
11
CTR=CPMC
CTR=CPMD
Rsvd
TBPRD Shadow (24)
TBPRD Active (24)
CTR=ZERO
CTR=CMPB
TBPRDHR (8)
Sync
Out
Select
EPWMxSYNCO
TBCTL[SWFSYNC]
EPWMxSYNCI
8
CTR=PRD
TBCTL[PHSEN]
TBCTL[SYNCOSEL]
DCAEVT1.sync(A)
DCBEVT1.sync(A)
Counter
Up/Down
(16 Bit)
CTR=ZERO
CTR_Dir
TBCTR
Active (16)
CTR=PRD
CTR=ZERO
EPWMx_INT
TBPHSHR (8)
16
8
CTR=PRD or ZERO
CTR=CMPA
EPWMxSOCA
EPWMxSOCB
Phase
Control
On-chip
ADC
TBPHS Active (24)
Event
Trigger
and
CTR=CMPB
CTR=CMPC
Interrupt
(ET)
ADCSOCOUTSELECT
CTR=CMPD
Counter Compare (CC)
CTR_Dir
Action
Qualifier
(AQ)
DCAEVT1.soc(A)
DCBEVT1.soc(A)
Select and pulse stretch
for external ADC
CTR=CMPA
CMPAHR (8)
ADCSOCAO
ADCSOCBO
16
HiRes PWM (HRPWM)
CMPAHR (8)
EPWMA
CMPA Active (24)
CMPA Shadow (24)
ePWMxA
PWM
Chopper
(PC)
Trip
Zone
(TZ)
Dead
Band
(DB)
CTR=CMPB
CMPBHR (8)
16
EPWMB
ePWMxB
CMPB Active (24)
CMPB Shadow (24)
CMPBHR (8)
CTR=CMPC
EPWMx_TZ_INT
TZ1 to TZ3
TBCNT(16)
EMUSTOP
CTR=ZERO
DCAEVT1.inter
DCBEVT1.inter
DCAEVT2.inter
CLOCKFAIL
CMPC[15-0] 16
EQEPxERR
CMPC Active (16)
CMPC Shadow (16)
DCAEVT1.force(A)
DCAEVT2.force(A)
DCBEVT1.force(A)
DCBEVT2.force(A)
DCBEVT2.inter
TBCNT(16)
CTR=CMPD
CMPD[15-0] 16
CMPD Active (16)
CMPD Shadow (16)
A. These events are generated by the ePWM digital compare (DC) submodule based on the levels of the TRIPIN inputs.
Figure 7-58. ePWM Submodules and Critical Internal Signal Interconnects
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 133
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
Figure 7-59. ePWM Trip Input Connectivity
Copyright © 2021 Texas Instruments Incorporated
134 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
7.11.3.1 Control Peripherals Synchronization
The ePWM and eCAP Synchronization Chain allows synchronization between multiple modules for the system.
Figure 7-60 shows the Synchronization Chain Architecture.
EXTSYNCIN2
EXTSYNCIN1
EPWM1
EPWM1SYNCOUT
EPWM2
EPWM4
EPWM3
EPWM4SYNCOUT
EPWM5
SYNCSEL.EPWM4SYNCIN
EPWM6
EPWM7
EPWM7SYNCOUT
EPWM8
EXTSYNCOUT
SYNCSEL.EPWM7SYNCIN
Pulse-Stretched
(8 PLLSYSCLK
Cycles)
ECAP1
ECAP1SYNCOUT
ECAP2
SYNCSEL.ECAP1SYNCIN
ECAP3
ECAP4
ECAP4SYNCOUT
SYNCSEL.ECAP4SYNCIN
ECAP5
ECAP6
SYNCSEL.ECAP6SYNCIN
SYNCSEL.SYNCOUT
ECAP7
Figure 7-60. Synchronization Chain Architecture
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 135
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
7.11.3.2 ePWM Electrical Data and Timing
Section 7.11.3.2.1 lists the ePWM timing requirements and Section 7.11.3.2.2 lists the ePWM switching
characteristics.
7.11.3.2.1 ePWM Timing Requirements (1)
MIN
2tc(EPWMCLK)
MAX
UNIT
Asynchronous
Synchronous
tw(SYNCIN)
Sync input pulse width
2tc(EPWMCLK)
cycles
With input qualifier
1tc(EPWMCLK) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 7.9.6.2.1.
7.11.3.2.2 ePWM Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
20
MAX
UNIT
ns
tw(PWM)
Pulse duration, PWMx output high/low
Sync output pulse width
tw(SYNCOUT)
8tc(SYSCLK)
cycles
Delay time, trip input active to PWM forced high
Delay time, trip input active to PWM forced low
Delay time, trip input active to PWM Hi-Z
td(TZ-PWM)
25
ns
7.11.3.2.3 Trip-Zone Input Timing
Section 7.11.3.2.3.1 lists the trip-zone input timing requirements. Figure 7-61 shows the PWM Hi-Z
characteristics.
7.11.3.2.3.1 Trip-Zone Input Timing Requirements (1)
MIN
1tc(EPWMCLK)
MAX UNIT
Asynchronous
Synchronous
tw(TZ)
Pulse duration, TZx input low
2tc(EPWMCLK)
cycles
With input qualifier
1tc(EPWMCLK) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see .
EPWMCLK
tw(TZ)
TZ(A)
td(TZ-PWM)
PWM(B)
A. TZ: TZ1, TZ2, TZ3, TRIP1–TRIP12
B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM recovery software.
Figure 7-61. PWM Hi-Z Characteristics
Copyright © 2021 Texas Instruments Incorporated
136 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
7.11.3.3 External ADC Start-of-Conversion Electrical Data and Timing
Section 7.11.3.3.1 lists the external ADC start-of-conversion switching characteristics. Figure 7-62 shows the
ADCSOCAO or ADCSOCBO timing.
7.11.3.3.1 External ADC Start-of-Conversion Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
tw(ADCSOCL)
Pulse duration, ADCSOCxO low
32tc(SYSCLK)
cycles
tw(ADCSOCL)
ADCSOCAO
or
ADCSOCBO
Figure 7-62. ADCSOCAO or ADCSOCBO Timing
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 137
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
7.11.4 High-Resolution Pulse Width Modulator (HRPWM)
The HRPWM combines multiple delay lines in a single module and a simplified calibration system by using a
dedicated calibration delay line. For each ePWM module, there are two HR outputs:
•
•
HR Duty and Deadband control on Channel A
HR Duty and Deadband control on Channel B
The HRPWM module offers PWM resolution (time granularity) that is significantly better than what can be
achieved using conventionally derived digital PWM methods. The key points for the HRPWM module are:
•
•
Significantly extends the time resolution capabilities of conventionally derived digital PWM
This capability can be used in both single edge (duty cycle and phase-shift control) as well as dual-edge
control for frequency/period modulation.
•
Finer time granularity control or edge positioning is controlled through extensions to the Compare A, B,
phase, period, and deadband registers of the ePWM module.
Note
The minimum HRPWMCLK frequency allowed for HRPWM is 60 MHz.
7.11.4.1 HRPWM Electrical Data and Timing
Section 7.11.4.1.1 lists the high-resolution PWM switching characteristics.
7.11.4.1.1 High-Resolution PWM Characteristics
PARAMETER
MIN
TYP
MAX UNIT
310 ps
Micro Edge Positioning (MEP) step size(1)
150
(1) The MEP step size will be largest at high temperature and minimum voltage on VDD. MEP step size will increase with higher
temperature and lower voltage and decrease with lower temperature and higher voltage.
Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI
software libraries for details of using SFO function in end applications. SFO functions help to estimate the number of MEP steps per
SYSCLK period dynamically while the HRPWM is in operation.
Copyright © 2021 Texas Instruments Incorporated
138 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
7.11.5 Enhanced Quadrature Encoder Pulse (eQEP)
The Type-1 eQEP peripheral contains the following major functional units (see Figure 7-63):
•
•
•
•
•
•
•
Programmable input qualification for each pin (part of the GPIO MUX)
Quadrature decoder unit (QDU)
Position counter and control unit for position measurement (PCCU)
Quadrature edge-capture unit for low-speed measurement (QCAP)
Unit time base for speed/frequency measurement (UTIME)
Watchdog timer for detecting stalls (QWDOG)
Quadrature Mode Adapter (QMA)
System
control registers
To CPU
EQEPxENCLK
SYSCLK
QCPRD
Enhanced QEP (eQEP) peripheral
QCAPCTL
16
QCTMR
16
16
Quadrature
capture unit
(QCAP)
QCTMRLAT
QCPRDLAT
QUTMR
QUPRD
QWDTMR
QWDPRD
Registers
used by
multiple units
32
16
QDECCTL
16
QEPCTL
QEPSTS
QFLG
UTOUT
UTIME
QWDOG
EQEPx_A
EQEPx_B
EQEPxAIN
WDTOUT
QMA
EQEPxBIN
EQEPxINT
QCLK
PIE
QDIR
EQEPxIIN
Quadrature
32
QI
GPIO
MUX
EQEPx_INDEX
EQEPxIOUT
Position counter/
control unit
(PCCU)
decoder
(QDU)
QS
EQEPxIOE
QPOSLAT
PHE
QPOSSLAT
QPOSILAT
PCSOUT
EQEPxSIN
EQEPx_STROBE
EQEPxSOUT
EQEPxSOE
32
32
16
QEINT
QPOSCNT
QPOSINIT
QPOSMAX
QPOSCMP
QFRC
QCLR
QPOSCTL
Copyright © 2017, Texas Instruments Incorporated
Figure 7-63. eQEP Block Diagram
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 139
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
7.11.5.1 eQEP Electrical Data and Timing
Section 7.11.5.1.1 lists the eQEP timing requirements and \Section 7.11.5.1.2 lists the eQEP switching
characteristics.
7.11.5.1.1 eQEP Timing Requirements (1)
MIN
MAX
UNIT
Asynchronous(2)/Synchronous
With input qualifier
2tc(SYSCLK)
tw(QEPP)
QEP input period
cycles
2[1tc(SYSCLK) + tw(IQSW)
]
Asynchronous(2)/Synchronous
2tc(SYSCLK)
2tc(SYSCLK) + tw(IQSW)
2tc(SYSCLK)
tw(INDEXH)
tw(INDEXL)
tw(STROBH)
tw(STROBL)
QEP Index Input High time
QEP Index Input Low time
QEP Strobe High time
QEP Strobe Input Low time
cycles
cycles
cycles
cycles
With input qualifier
Asynchronous(2)/Synchronous
With input qualifier
2tc(SYSCLK) + tw(IQSW)
2tc(SYSCLK)
2tc(SYSCLK) + tw(IQSW)
2tc(SYSCLK)
Asynchronous(2)/Synchronous
With input qualifier
Asynchronous(2)/Synchronous
With input qualifier
2tc(SYSCLK) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 7.9.6.2.1.
(2) See the TMS320F28004xMCUsSiliconErrata for limitations in the asynchronous mode.
7.11.5.1.2 eQEP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
5tc(SYSCLK)
7tc(SYSCLK)
UNIT
cycles
cycles
td(CNTR)xin
Delay time, external clock to counter increment
td(PCS-OUT)QEP
Delay time, QEP input edge to position compare sync output
Copyright © 2021 Texas Instruments Incorporated
140 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
7.11.6 Sigma-Delta Filter Module (SDFM)
The SDFM is a 4-channel digital filter designed specifically for current measurement and resolver position
decoding in motor control applications. Each channel can receive an independent sigma-delta (ΣΔ) modulated
bit stream. The bit streams are processed by four individually programmable digital decimation filters. The filter
set includes a fast comparator for immediate digital threshold comparisons for overcurrent and undercurrent
monitoring.
The SDFM features include:
•
8 external pins per SDFM module
– 4 sigma-delta data input pins per SDFM module (SDx_D1-4)
– 4 sigma-delta clock input pins per SDFM module (SDx_C1-4)
•
4 different configurable modulator clock modes:
– Mode 0: Modulator clock rate equals modulator data rate
– Mode 1: Modulator clock rate running at half the modulator data rate
– Mode 2: Modulator data is Manchester encoded. Modulator clock not required.
– Mode 3: Modulator clock rate is double that of modulator data rate
4 independent configurable secondary filter (comparator) units per SDFM module:
– 4 different filter type selection (Sinc1/Sinc2/Sincfast/Sinc3) options available
– Ability to detect over-value, under-value, and zero-crossing conditions
– OSR value for comparator filter unit (COSR) programmable from 1 to 32
4 independent configurable primary filter (data filter) units per SDFM module:
– 4 different filter type selection (Sinc1/Sinc2/Sincfast/Sinc3) options available
– OSR value for data filter unit (DOSR) programmable from 1 to 256
– Ability to enable individual filter modules
•
•
– Ability to synchronize all the 4 independent filters of an SDFM module using Master Filter Enable (MFE)
bit or using PWM signals
•
Data filter unit has programmable FIFO to reduce interrupt overhead. FIFO has the following features:
– Primary filter (data filter) has 16 deep × 32-bit FIFO
– FIFO can interrupt CPU after programmable number of data ready events
– FIFO Wait-for-Sync feature: Ability to ignore data ready events until PWM synchronization signal
(SDSYNC) is received. Once SDSYNC event is received, FIFO is populated on every data ready event
– Data filter output can be represented in either 16 bits or 32 bits
PWMx.SOCA/SOCB can be configured to serve as SDSYNC source on per data filter channel basis
PWMs can be used to generate a modulator clock for sigma delta modulators
•
•
Note
Care should be taken to avoid noise on the SDx_Cy input. If the minimum pulse width requirements
are not met (for example, through a noise glitch), then the SDFM results could become undefined.
Figure 7-64 shows the SDFM block diagram.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 141
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
SDFM- Sigma Delta Filter Module
SDyFLTx.DRINT
DMA
G4
Streams
Filter Module 1
Secondary
(Comparator)
Filter
Interrupt
Unit
SDx_D1
SDx_C1
Input
Ctrl
Primary (Data)
Filter
SDy_ERR
SDyFLTx.DRINT
CLA
SDSYNC
SDSYNC
FIFO
PWMx.SOCA / SOCB
PWMx.SOCA / SOCB
PWMx.SOCA / SOCB
PWMx.SOCA / SOCB
SDx_D2
SDx_C2
Filter Module 2
SDy_ERR
SDyFLTx.DRINT
ePIE
GPIO
MUX
SDx_D3
SDx_C3
Filter Module 3
Filter Module 4
Output / PWM
XBAR
SDyFLTx.COMPL
SDSYNC
SDSYNC
Register
Map
SDyFLTx.COMPHA
SDx_D4
SDx_C4
SDyFLTx.COMPL
SDyFLTx.COMPHA
SDyFLTx.COMPHB
ECAP
LEGEND
Interrupt / trigger sources from Primary Filter
Internal secondary filter signals
Figure 7-64. SDFM Block Diagram
Copyright © 2021 Texas Instruments Incorporated
142 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
7.11.6.1 SDFM Electrical Data and Timing
SDFM operation with asynchronous GPIO is defined by setting GPyQSELn = 0b11. Section 7.11.6.1.1 lists the
SDFM timing requirements when using the asynchronous GPIO (ASYNC) option. Figure 7-65, Figure 7-66,
Figure 7-67, and Figure 7-68 show the SDFM timing diagrams.
7.11.6.1.1 SDFM Timing Requirements When Using Asynchronous GPIO (ASYNC) Option
MIN
MAX
UNIT
Mode 0
tc(SDC)M0
Cycle time, SDx_Cy
40
10
5
256 * SYSCLK period
tc(SDC)M0 – 10
ns
ns
ns
ns
tw(SDCH)M0
Pulse duration, SDx_Cy high
tsu(SDDV-SDCH)M0
th(SDCH-SDD)M0
Setup time, SDx_Dy valid before SDx_Cy goes high
Hold time, SDx_Dy wait after SDx_Cy goes high
Mode 1
5
tc(SDC)M1
Cycle time, SDx_Cy
80
10
5
256 * SYSCLK period
tc(SDC)M1 – 10
ns
ns
ns
ns
ns
ns
tw(SDCH)M1
Pulse duration, SDx_Cy high
tsu(SDDV-SDCL)M1
tsu(SDDV-SDCH)M1
th(SDCL-SDD)M1
th(SDCH-SDD)M1
Setup time, SDx_Dy valid before SDx_Cy goes low
Setup time, SDx_Dy valid before SDx_Cy goes high
Hold time, SDx_Dy wait after SDx_Cy goes low
Hold time, SDx_Dy wait after SDx_Cy goes high
Mode 2
5
5
5
tc(SDD)M2
Cycle time, SDx_Dy
8 * tc(SYSCLK)
10
20 * tc(SYSCLK)
ns
ns
tw(SDDH)M2
Pulse duration, SDx_Dy high
SDx_Dy long pulse duration keepout, where the long
pulse must not fall within the MIN or MAX values listed.
Long pulse is defined as the high or low pulse which is the
full width of the Manchester bit-clock period.
This requirement must be satisfied for any integer
between 8 and 20.
tw(SDD_LONG_KEEPOUT)M2
(N * tc(SYSCLK)) – 0.5
(N * tc(SYSCLK)) + 0.5
ns
ns
SDx_Dy Short pulse duration for a high or low pulse
(SDD_SHORT_H or SDD_SHORT_L).
Short pulse is defined as the high or low pulse which is
half the width of the Manchester bit-clock period.
tw(SDD_SHORT)M2
tw(SDD_LONG) / 2 – tc(SYSCLK) tw(SDD_LONG) / 2 + tc(SYSCLK)
SDx_Dy Long pulse variation (SDD_LONG_H –
SDD_LONG_L)
tw(SDD_LONG_DUTY)M2
tw(SDD_SHORT_DUTY)M2
– tc(SYSCLK)
– tc(SYSCLK)
tc(SYSCLK)
tc(SYSCLK)
ns
ns
SDx_Dy Short pulse variation (SDD_SHORT_H –
SDD_SHORT_L)
Mode 3
tc(SDC)M3
Cycle time, SDx_Cy
40
10
5
256 * SYSCLK period
tc(SDC)M3 – 5
ns
ns
ns
ns
tw(SDCH)M3
Pulse duration, SDx_Cy high
tsu(SDDV-SDCH)M3
th(SDCH-SDD)M3
Setup time, SDx_Dy valid before SDx_Cy goes high
Hold time, SDx_Dy wait after SDx_Cy goes high
5
7.11.6.1.2 SDFM Timing Diagram
WARNING
The SDFM clock inputs (SDx_Cy pins) directly clock the SDFM module when there is no GPIO input
synchronization. Any glitches or ringing noise on these inputs can corrupt the SDFM module
operation. Special precautions should be taken on these signals to ensure a clean and noise-free
signal that meets SDFM timing requirements. Precautions such as series termination for ringing due
to any impedance mismatch of the clock driver and spacing of traces from other noisy signals are
recommended.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 143
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
WARNING
Mode 2 (Manchester Mode) is not recommended for new applications. See the "SDFM: Manchester
Mode (Mode 2) Does Not Produce Correct Filter Results Under Several Conditions" advisory in the
TMS320F28004x MCUs Silicon Errata.
Mode 0
tw(SDCH)M0
tc(SDC)M0
SDx_Cy
SDx_Dy
tsu(SDDV-SDCH)M0
th(SDCH-SDD)M0
Figure 7-65. SDFM Timing Diagram – Mode 0
Mode 1
SDx_Cy
tw(SDCH)M1
tc(SDC)M1
tsu(SDDV-SDCL)M1
tsu(SDDV-SDCH)M1
SDx_Dy
th(SDCL-SDD)M1
th(SDCH-SDD)M1
Figure 7-66. SDFM Timing Diagram – Mode 1
Mode 2
(Manchester-encoded-bit stream)
tc(SDD)M2
Modulator
Internal clock
tw(SDDH)M2
Modulator
Internal data
1
1
0
1
1
0
0
1
1
tw(SDD_LONG_KEEPOUT)
SDx-Dy
tw(SDD_LONG_L)
tw(SDD_LONG_H)
tw(SDD_SHORT_L)
tw(SDD_SHORT_H)
N x tc(SYSCLK) + 0.5
N x SYSCLK
SYSCLK
N x tc(SYSCLK) œ0.5
œ
Figure 7-67. SDFM Timing Diagram – Mode 2
Copyright © 2021 Texas Instruments Incorporated
144 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
(CLKx is driven externally)
Mode 3
SDx_Cy
tc(SDC)M3
tw(SDCH)M3
tsu(SDDV-SDCH)M3
th(SDCH-SDD)M3
SDx_Dy
Figure 7-68. SDFM Timing Diagram – Mode 3
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 145
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
7.11.6.2 SDFM Electrical Data and Timing (Synchronized GPIO)
SDFM operation with synchronous GPIO is defined by setting GPyQSELn = 0b00. When using this synchronized
GPIO mode, the timing requirement for tw(GPI) pulse duration of 2tc(SYSCLK) must be met. It is important for both
SD-Cx and SD-Dx pairs be configured with SYNC option. Section 7.11.6.2 lists the SDFM timing requirements
when using the synchronized GPIO (SYNC) option. Figure 7-65, Figure 7-66, Figure 7-67, and Figure 7-68 show
the SDFM timing diagrams.
7.11.6.2.1 SDFM Timing Requirements When Using Synchronized GPIO (SYNC) Option
MIN
MAX UNIT
Mode 0
tc(SDC)M0
Cycle time, SDx_Cy
5 * SYSCLK period
2 * SYSCLK period
256 * SYSCLK period
ns
ns
tw(SDCHL)M0
Pulse duration, SDx_Cy high/low
3 * SYSCLK period
Setup time, SDx_Dy valid before SDx_Cy goes
high
tsu(SDDV-SDCH)M0
th(SDCH-SDD)M0
2 * SYSCLK period
2 * SYSCLK period
ns
ns
Hold time, SDx_Dy wait after SDx_Cy goes high
Mode 1
tc(SDC)M1
Cycle time, SDx_Cy
10 * SYSCLK period
2 * SYSCLK period
256 * SYSCLK period
8 * SYSCLK period
ns
ns
tw(SDCHL)M1
Pulse duration, SDx_Cy high/low
Setup time, SDx_Dy valid before SDx_Cy goes
low
tsu(SDDV-SDCL)M1
tsu(SDDV-SDCH)M1
2 * SYSCLK period
2 * SYSCLK period
ns
ns
Setup time, SDx_Dy valid before SDx_Cy goes
high
th(SDCL-SDD)M1
th(SDCH-SDD)M1
Hold time, SDx_Dy wait after SDx_Cy goes low
Hold time, SDx_Dy wait after SDx_Cy goes high
Mode 2
2 * SYSCLK period
2 * SYSCLK period
ns
ns
tc(SDD)M2
Cycle time, SDx_Dy
Option unavailable
tw(SDDH)M2
Pulse duration, SDx_Dy high
Mode 3
tc(SDC)M3
Cycle time, SDx_Cy
5 * SYSCLK period
2 * SYSCLK period
256 * SYSCLK period
3 * SYSCLK period
ns
ns
tw(SDCHL)M3
Pulse duration, SDx_Cy high/low
Setup time, SDx_Dy valid before SDx_Cy goes
high
tsu(SDDV-SDCH)M3
th(SDCH-SDD)M3
2 * SYSCLK period
2 * SYSCLK period
ns
ns
Hold time, SDx_Dy wait after SDx_Cy goes high
Note
The SDFM Synchronized GPIO (SYNC) option provides protection against SDFM module corruption
due to occasional random noise glitches on the SDx_Cy pin that may result in a false comparator trip
and filter output.
The SDFM Synchronized GPIO (SYNC) mode does not provide protection against persistent
violations of the above timing requirements. Timing violations will result in data corruption proportional
to the number of bits which violate the requirements.
Copyright © 2021 Texas Instruments Incorporated
146 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
7.12 Communications Peripherals
7.12.1 Controller Area Network (CAN)
Note
The CAN module uses the IP known as DCAN. This document uses the names CAN and DCAN
interchangeably to reference this peripheral.
The CAN module implements the following features:
•
•
•
•
Complies with ISO11898-1 ( Bosch® CAN protocol specification 2.0 A and B)
Bit rates up to 1 Mbps
Multiple clock sources
32 message objects (mailboxes), each with the following properties:
– Configurable as receive or transmit
– Configurable with standard (11-bit) or extended (29-bit) identifier
– Supports programmable identifier receive mask
– Supports data and remote frames
– Holds 0 to 8 bytes of data
– Parity-checked configuration and data RAM
Individual identifier mask for each message object
Programmable FIFO mode for message objects
Programmable loopback modes for self-test operation
Suspend mode for debug support
Software module reset
Automatic bus on after bus-off state by a programmable 32-bit timer
Two interrupt lines
•
•
•
•
•
•
•
•
DMA support
Note
For a CAN bit clock of 100 MHz, the smallest bit rate possible is 3.90625 kbps.
Note
The accuracy of the on-chip zero-pin oscillator is in Section 7.9.3.5.1. Depending on parameters such
as the CAN bit timing settings, bit rate, bus length, and propagation delay, the accuracy of this
oscillator may not meet the requirements of the CAN protocol. In this situation, an external clock
source must be used.
Figure 7-69 shows the CAN block diagram.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 147
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
CAN_RX
CAN_TX
CAN
CAN Core
Message RAM
Message Handler
Message
RAM
Interface
Registers and Message
Object Access (IFx)
32
Message
Objects
(Mailboxes)
Test Modes
Only
Module Interface
CPU Bus
to ePIE
DMA
Figure 7-69. CAN Block Diagram
Copyright © 2021 Texas Instruments Incorporated
148 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
7.12.2 Inter-Integrated Circuit (I2C)
The I2C module has the following features:
•
Compliance with the NXP Semiconductors I2C-bus specification (version 2.1):
– Support for 8-bit format transfers
– 7-bit and 10-bit addressing modes
– General call
– START byte mode
– Support for multiple master-transmitters and slave-receivers
– Support for multiple slave-transmitters and master-receivers
– Combined master transmit/receive and receive/transmit mode
– Data transfer rate from 10 kbps up to 400 kbps (Fast-mode)
One 16-byte receive FIFO and one 16-byte transmit FIFO
Supports two ePIE interrupts
•
•
– I2Cx interrupt – Any of the below conditions can be configured to generate an I2Cx interrupt:
•
•
•
•
•
•
•
Transmit Ready
Receive Ready
Register-Access Ready
No-Acknowledgment
Arbitration-Lost
Stop Condition Detected
Addressed-as-Slave
– I2Cx_FIFO interrupts:
•
•
Transmit FIFO interrupt
Receive FIFO interrupt
•
•
Module enable and disable capability
Free data format mode
Figure 7-70 shows how the I2C peripheral module interfaces within the device.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 149
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
I2C module
I2CXSR
I2CDXR
TX FIFO
RX FIFO
FIFO Interrupt
to CPU/PIE
SDA
Peripheral bus
I2CRSR
I2CDRR
Control/status
registers
CPU
Clock
synchronizer
SCL
Prescaler
Noise filters
Arbitrator
Interrupt to
CPU/PIE
I2C INT
Figure 7-70. I2C Peripheral Module Interfaces
Copyright © 2021 Texas Instruments Incorporated
150 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
7.12.2.1 I2C Electrical Data and Timing
Section 7.12.2.1.1 lists the I2C timing requirements. Section 7.12.2.1.2 lists the I2C switching characteristics.
Figure 7-71 shows the I2C timing diagram.
7.12.2.1.1 I2C Timing Requirements
NO.
MIN
MAX
UNIT
Standard mode
T0
T1
fmod
I2C module frequency
7
12
MHz
µs
Hold time, START condition, SCL fall delay after
SDA fall
th(SDA-SCL)START
4.0
Setup time, Repeated START, SCL rise before SDA
fall delay
T2
tsu(SCL-SDA)START
4.0
µs
T3
T4
T5
T6
T7
T8
th(SCL-DAT)
tsu(DAT-SCL)
tr(SDA)
Hold time, data after SCL fall
Setup time, data before SCL rise
Rise time, SDA
0
µs
ns
ns
ns
ns
ns
250
1000
1000
300
tr(SCL)
Rise time, SCL
tf(SDA)
Fall time, SDA
tf(SCL)
Fall time, SCL
300
Setup time, STOP condition, SCL rise before SDA
rise delay
T9
tsu(SCL-SDA)STOP
4.0
µs
Pulse duration of spikes that will be suppressed by
filter
T10
tw(SP)
Cb
tc(CMCLK)
31 * tc(CMCLK)
400
µs
pF
T11
capacitance load on each bus line
Fast mode
T0
fmod
I2C module frequency
7
12
MHz
µs
Hold time, START condition, SCL fall delay after
SDA fall
T1
T2
th(SDA-SCL)START
0.6
Setup time, Repeated START, SCL rise before SDA
fall delay
tsu(SCL-SDA)START
0.6
µs
T3
T4
T5
T6
T7
T8
th(SCL-DAT)
tsu(DAT-SCL)
tr(SDA)
Hold time, data after SCL fall
Setup time, data before SCL rise
Rise time, SDA
0
100
20
µs
ns
ns
ns
ns
ns
300
300
300
300
tr(SCL)
Rise time, SCL
20
tf(SDA)
Fall time, SDA
11.4
11.4
tf(SCL)
Fall time, SCL
Setup time, STOP condition, SCL rise before SDA
rise delay
T9
tsu(SCL-SDA)STOP
0.6
µs
Pulse duration of spikes that will be suppressed by
filter
T10
T11
tw(SP)
Cb
tc(CMCLK)
31 * tc(CMCLK)
400
µs
pF
capacitance load on each bus line
7.12.2.1.2 I2C Switching Characteristics
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
Standard mode
S1
S2
S3
S4
fSCL
SCL clock frequency
0
10
100
kHz
µs
TSCL
SCL clock period
tw(SCLL)
tw(SCLH)
Pulse duration, SCL clock low
Pulse duration, SCL clock high
4.7
4.0
µs
µs
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 151
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
Bus free time between STOP and START
conditions
S5
tBUF
4.7
µs
S6
S7
S8
tv(SCL-DAT)
tv(SCL-ACK)
II
Valid time, data after SCL fall
Valid time, Acknowledge after SCL fall
Input current on pins
3.45
3.45
10
µs
µs
µA
0.1 Vbus < Vi < 0.9 Vbus
–10
Fast mode
S1
S2
S3
S4
fSCL
SCL clock frequency
0
2.5
1.3
0.6
400
kHz
µs
TSCL
SCL clock period
tw(SCLL)
tw(SCLH)
Pulse duration, SCL clock low
Pulse duration, SCL clock high
µs
µs
Bus free time between STOP and START
conditions
S5
tBUF
1.3
µs
S6
S7
S8
tv(SCL-DAT)
tv(SCL-ACK)
II
Valid time, data after SCL fall
Valid time, Acknowledge after SCL fall
Input current on pins
0.9
0.9
10
µs
µs
µA
0.1 Vbus < Vi < 0.9 Vbus
–10
7.12.2.1.3 I2C Timing Diagram
Note
To meet all of the I2C protocol timing specifications, the I2C module clock (Fmod) must be configured
in the range from 7 MHz to 12 MHz.
STOP
START
SDA
SCL
ACK
Contd...
Contd...
S7
S6
T10
T5
T7
S3
S4
9th
clock
T6
T8
S2
Repeated
START
STOP
S5
SDA
ACK
T2
T9
T1
SCL
9th
clock
Figure 7-71. I2C Timing Diagram
Copyright © 2021 Texas Instruments Incorporated
152 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
7.12.3 Power Management Bus (PMBus) Interface
The PMBus module has the following features:
•
•
•
•
Compliance with the SMI Forum PMBus Specification (Part I v1.0 and Part II v1.1)
Support for master and slave modes
Support for I2C mode
Support for two speeds:
– Standard Mode: Up to 100 kHz
– Fast Mode: Up to 400 kHz
Packet error checking
CONTROL and ALERT signals
Clock high and low time-outs
Four-byte transmit and receive buffers
One maskable interrupt, which can be generated by several conditions:
– Receive data ready
•
•
•
•
•
– Transmit buffer empty
– Slave address received
– End of message
– ALERT input asserted
– Clock low time-out
– Clock high time-out
– Bus free
Figure 7-72 shows the PMBus block diagram.
PCLKCR20
SYSCLK
PMBCTRL
Div
ALERT
CTL
DMA
CPU
PIE
Bit clock
Other registers
GPIO Mux
PMBTXBUF
SCL
Shift register
PMBRXBUF
SDA
PMBUSA_INT
PMBus Module
Figure 7-72. PMBus Block Diagram
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 153
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
7.12.3.1 PMBus Electrical Data and Timing
Section 7.12.3.1.1 lists the PMBus electrical characteristics. Section 7.12.3.1.2 lists the PMBUS fast mode
switching characteristics. Section 7.12.3.1.3 lists the PMBUS standard mode switching characteristics.
7.12.3.1.1 PMBus Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.8
UNIT
V
VIL
VIH
VOL
IOL
Valid low-level input voltage
Valid high-level input voltage
Low-level output voltage
Low-level output current
2.1
VDDIO
0.4
V
At Ipullup = 4 mA
V
VOL ≤ 0.4 V
4
0
mA
Pulse width of spikes that must be
suppressed by the input filter
tSP
50
ns
Ii
Input leakage current on each pin
Capacitance on each pin
0.1 Vbus < Vi < 0.9 Vbus
–10
10
10
µA
pF
Ci
7.12.3.1.2 PMBus Fast Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fSCL
tBUF
SCL clock frequency
10
400
kHz
Bus free time between STOP and
START conditions
1.3
0.6
0.6
0.6
µs
µs
µs
µs
START condition hold time -- SDA fall
to SCL fall delay
tHD;STA
tSU;STA
tSU;STO
Repeated START setup time -- SCL
rise to SDA fall delay
STOP condition setup time -- SCL rise
to SDA rise delay
tHD;DAT
tSU;DAT
tTimeout
tLOW
Data hold time after SCL fall
Data setup time before SCL rise
Clock low time-out
300
100
25
ns
ns
ms
µs
µs
35
Low period of the SCL clock
High period of the SCL clock
1.3
0.6
tHIGH
50
25
Cumulative clock low extend time
(slave device)
tLOW;SEXT
tLOW;MEXT
From START to STOP
Within each byte
ms
ms
Cumulative clock low extend time
(master device)
10
tr
tf
Rise time of SDA and SCL
Fall time of SDA and SCL
5% to 95%
95% to 5%
20
20
300
300
ns
ns
Copyright © 2021 Texas Instruments Incorporated
154 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
7.12.3.1.3 PMBus Standard Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fSCL
tBUF
SCL clock frequency
10
100
kHz
Bus free time between STOP and
START conditions
4.7
4
µs
µs
µs
µs
START condition hold time -- SDA fall
to SCL fall delay
tHD;STA
tSU;STA
tSU;STO
Repeated START setup time -- SCL
rise to SDA fall delay
4.7
4
STOP condition setup time -- SCL rise
to SDA rise delay
tHD;DAT
tSU;DAT
tTimeout
tLOW
Data hold time after SCL fall
Data setup time before SCL rise
Clock low time-out
300
250
25
ns
ns
ms
µs
µs
35
Low period of the SCL clock
High period of the SCL clock
4.7
4
tHIGH
50
25
Cumulative clock low extend time
(slave device)
tLOW;SEXT
tLOW;MEXT
From START to STOP
Within each byte
ms
ms
Cumulative clock low extend time
(master device)
10
tr
tf
Rise time of SDA and SCL
Fall time of SDA and SCL
1000
300
ns
ns
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 155
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
7.12.4 Serial Communications Interface (SCI)
The SCI is a 2-wire asynchronous serial port, commonly known as a UART. The SCI module supports digital
communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero
(NRZ) format
The SCI receiver and transmitter each have a 16-level-deep FIFO for reducing servicing overhead, and each has
its own separate enable and interrupt bits. Both can be operated independently for half-duplex communication,
or simultaneously for full-duplex communication. To specify data integrity, the SCI checks received data for break
detection, parity, overrun, and framing errors. The bit rate is programmable to different speeds through a 16-bit
baud-select register.
Features of the SCI module include:
•
Two external pins:
– SCITXD: SCI transmit-output pin
– SCIRXD: SCI receive-input pin
Note
Both pins can be used as GPIO if not used for SCI.
– Baud rate programmable to 64K different rates
Data-word format
•
– 1 start bit
– Data-word length programmable from 1 to 8 bits
– Optional even/odd/no parity bit
– 1 or 2 stop bits
•
•
•
•
•
Four error-detection flags: parity, overrun, framing, and break detection
Two wake-up multiprocessor modes: idle-line and address bit
Half- or full-duplex operation
Double-buffered receive and transmit functions
Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with
status flags.
– Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY
flag (transmitter-shift register is empty)
– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (break
condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
Separate enable bits for transmitter and receiver interrupts (except BRKDT)
NRZ format
Auto baud-detect hardware logic
16-level transmit and receive FIFO
•
•
•
•
Note
All registers in this module are 8-bit registers. When a register is accessed, the register data is in the
lower byte (bits 7–0), and the upper byte (bits 15–8) is read as zeros. Writing to the upper byte has no
effect.
Figure 7-73 shows the SCI block diagram.
Copyright © 2021 Texas Instruments Incorporated
156 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
TXENA
SCICTL1.1
Frame Format and Mode
Parity
Even/Odd
SCITXD
SCITXD
TXSHF
Register
TXEMPTY
SCICTL2.6
Enable
TXINTENA
SCICTL2.0
8
SCICCR.6 SCICCR.5
TXRDY
Transmitter Data
Buffer register
SCICTL2.7
SCITXBUF.7−0
8
TXWAKE
SCICTL1.3
TX FIFO_0
TX FIFO_1
−−−−−
TXINT
TX Interrupt
Logic
1
TX FIFO Interrupt
To CPU
TX FIFO_15
SCI TX Interrupt select logic
Auto baud detect logic
WUT
SCITXBUF.7−0
TX FIFO
SCIFFENA
SCIFFTX.14
RXENA
SCICTL1.0
SCIHBAUD. 15 − 8
SCIRXD
RXSHF
Register
Baud Rate
MSbyte
SCIRXD
Register
RXWAKE
LSPCLK
SCIRXST.1
SCILBAUD. 7 − 0
RXENA
SCICTL1.0
8
Baud Rate
LSbyte
RXBKINTENA
SCICTL2.1
Register
RXRDY
Receive Data
Buffer register
SCIRXST.6
SCIRXBUF.7−0
8
BRKDT
SCIRXST.5
RX FIFO_0
−−−−−
RX FIFO_14
RX FIFO_15
SCIRXBUF.7−0
RX Interrupt
Logic
RXINT
RX FIFO Interrupt
To CPU
RX FIFO
RXFFOVF
SCIFFRX.15
SCIRXST.7
RX Error
SCIRXST.5 – 2
BRKDT FE OE PE
RX Error
RXERRINTENA
SCICTL1.6
SCI RX Interrupt select logic
Figure 7-73. SCI Block Diagram
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 157
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
7.12.5 Serial Peripheral Interface (SPI)
The serial peripheral interface (SPI) is a high-speed synchronous serial input and output (I/O) port that allows a
serial bit stream of programmed length (1 to 16 bits) to be shifted into and out of the device at a programmed bit-
transfer rate. The SPI is normally used for communications between the MCU controller and external peripherals
or another controller. Typical applications include external I/O or peripheral expansion through devices such as
shift registers, display drivers, and analog-to-digital converters (ADCs). Multidevice communications are
supported by the master or slave operation of the SPI. The port supports a 16-level, receive and transmit FIFO
for reducing CPU servicing overhead.
The SPI module features include:
•
•
•
•
SPISOMI: SPI slave-output/master-input pin
SPISIMO: SPI slave-input/master-output pin
SPISTE: SPI slave transmit-enable pin
SPICLK: SPI serial-clock pin
Note
All four pins can be used as GPIO, if the SPI module is not used.
•
•
Two operational modes: Master and Slave
Baud rate: 125 different programmable rates. The maximum baud rate that can be employed is limited by the
maximum speed of the I/O buffers used on the SPI pins.
•
•
Data word length: 1 to 16 data bits
Four clocking schemes (controlled by clock polarity and clock phase bits) include:
– Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling
edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the rising
edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
Simultaneous receive and transmit operation (transmit function can be disabled in software)
Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithm
16-level transmit/receive FIFO
•
•
•
•
•
•
•
•
DMA support
High-speed mode
Delayed transmit control
3-wire SPI mode
SPISTE inversion for digital audio interface receive mode on devices with two SPI modules
Figure 7-74 shows the SPI CPU interfaces.
Copyright © 2021 Texas Instruments Incorporated
158 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
PCLKCR8
Low-Speed
Prescaler
CPU
LSPCLK
SYSCLK
Bit Clock
SYSRS
SPISIMO
SPISOMI
SPICLK
SPISTE
SPI
GPIO MUX
SPIINT
PIE
SPITXINT
SPIRXDMA
SPITXDMA
DMA
Figure 7-74. SPI CPU Interface
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 159
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
7.12.5.1 SPI Electrical Data and Timing
The following sections contain the SPI External Timings in Non-High-Speed Mode:
Section 7.12.5.1.1
Section 7.12.5.1.2
Non-High-Speed Master Mode Timings
Non-High-Speed Slave Mode Timings
The following sections contain the SPI External Timings in High-Speed Mode:
Section 7.12.5.1.3
Section 7.12.5.1.4
High-Speed Master Mode Timings
High-Speed Slave Mode Timings
Note
All timing parameters for SPI High-Speed Mode assume a load capacitance of 5 pF on SPICLK,
SPISIMO, and SPISOMI.
For more information about the SPI in High-Speed mode, see the Serial Peripheral Interface (SPI) chapter of the
TMS320F28004x Microcontrollers Technical Reference Manual.
Copyright © 2021 Texas Instruments Incorporated
160 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
7.12.5.1.1 Non-High-Speed Master Mode Timings
Section 7.12.5.1.1.1 lists the SPI master mode switching characteristics where the clock phase = 0. Figure 7-75
shows the SPI master mode external timing where the clock phase = 0.
Section 7.12.5.1.1.2 lists the SPI master mode switching characteristics where the clock phase = 1. Figure 7-76
shows the SPI master mode external timing where the clock phase = 1.
Section 7.12.5.1.1.3 lists the SPI master mode timing requirements.
7.12.5.1.1.1 SPI Master Mode Switching Characteristics (Clock Phase = 0)
over recommended operating conditions (unless otherwise noted)
(BRR + 1)
NO.
PARAMETER
MIN
MAX UNIT
128tc(LSPCLK)
CONDITION(1)
Even
4tc(LSPCLK)
5tc(LSPCLK)
1
tc(SPC)M
Cycle time, SPICLK
ns
Odd
127tc(LSPCLK)
Even
0.5tc(SPC)M – 3
0.5tc(SPC)M + 3
2
tw(SPC1)M
Pulse duration, SPICLK, first pulse
ns
0.5tc(SPC)M
0.5tc(LSPCLK) – 3
+
0.5tc(SPC)M +
0.5tc(LSPCLK) + 3
Odd
Even
Odd
0.5tc(SPC)M – 3
0.5tc(SPC)M + 3
Pulse duration, SPICLK, second
pulse
3
4
5
tw(SPC2)M
td(SIMO)M
tv(SIMO)M
ns
ns
ns
0.5tc(SPC)M
0.5tc(LSPCLK) – 3
–
0.5tc(SPC)M
–
0.5tc(LSPCLK) + 3
Delay time, SPICLK to SPISIMO valid Even, Odd
5
Even
0.5tc(SPC)M – 6
0.5tc(SPC)M
0.5tc(LSPCLK) – 3
1.5tc(SPC)M
3tc(SYSCLK) – 3
1.5tc(SPC)M
Valid time, SPISIMO valid after
SPICLK
–
Odd
–
Even
23 td(SPC)M
Delay time, SPISTE valid to SPICLK
ns
ns
–
Odd
Even
Odd
3tc(SYSCLK) – 3
0.5tc(SPC)M – 6
Delay time, SPICLK to SPISTE
invalid
24 td(STE)M
0.5tc(SPC)M
0.5tc(LSPCLK) – 3
–
(1) The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR is
greater than 3.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 161
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
MAX UNIT
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
7.12.5.1.1.2 SPI Master Mode Switching Characteristics (Clock Phase = 1)
over recommended operating conditions (unless otherwise noted)
(BRR + 1)
NO.
PARAMETER
MIN
CONDITION(1)
Even
4tc(LSPCLK)
5tc(LSPCLK)
128tc(LSPCLK)
1
tc(SPC)M
Cycle time, SPICLK
ns
ns
Odd
127tc(LSPCLK)
Even
0.5tc(SPC)M – 3
0.5tc(SPC)M + 3
2
3
4
5
tw(SPC1)M
Pulse duration, SPICLK, first pulse
0.5tc(SPC)M
–
0.5tc(SPC)M –
0.5tc(LSPCLK) + 3
Odd
Even
Odd
Even
Odd
Even
Odd
0.5tc(LSPCLK) – 3
0.5tc(SPC)M – 3
0.5tc(SPC)M + 3
Pulse duration, SPICLK, second
pulse
tw(SPC2)M
td(SIMO)M
tv(SIMO)M
ns
ns
0.5tc(SPC)M
+
0.5tc(SPC)M
+
0.5tc(LSPCLK) – 3
0.5tc(LSPCLK) + 3
0.5tc(SPC)M – 4
Delay time, SPISIMO valid to SPICLK
0.5tc(SPC)M
+
0.5tc(LSPCLK) – 1
0.5tc(SPC)M – 6
Valid time, SPISIMO valid after
SPICLK
ns
ns
ns
0.5tc(SPC)M
–
0.5tc(LSPCLK) – 1
2tc(SPC)M – 3tc(SYSCLK) – 3
0.5tc(SPC)M – 6
23 td(SPC)M
Delay time, SPISTE valid to SPICLK Even, Odd
Even
Delay time, SPICLK to
SPISTE invalid
24 td(STE)M
0.5tc(SPC)M
–
Odd
0.5tc(LSPCLK) – 1
(1) The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR is
greater than 3.
7.12.5.1.1.3 SPI Master Mode Timing Requirements
(BRR + 1)
NO.
8
MIN
20
0
MAX UNIT
CONDITION(1)
Setup time, SPISOMI valid before
SPICLK
tsu(SOMI)M
th(SOMI)M
Even, Odd
ns
ns
Hold time, SPISOMI valid after
SPICLK
9
Even, Odd
(1) The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR is
greater than 3.
Copyright © 2021 Texas Instruments Incorporated
162 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISIMO
Master Out Data Is Valid
8
9
Master In Data
Must Be Valid
SPISOMI
SPISTE(A)
24
23
A. On the trailing end of the word, SPISTE will go inactive except between back-to-back transmit words in both FIFO and non-FIFO modes.
Figure 7-75. SPI Master Mode External Timing (Clock Phase = 0)
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISIMO
Master Out Data Is Valid
8
9
Master In Data Must
Be Valid
SPISOMI
SPISTE(A)
24
23
A. On the trailing end of the word, SPISTE will go inactive except between back-to-back transmit words in both FIFO and non-FIFO modes.
Figure 7-76. SPI Master Mode External Timing (Clock Phase = 1)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 163
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
7.12.5.1.2 Non-High-Speed Slave Mode Timings
Section 7.12.5.1.2.1 lists the SPI slave mode switching characteristics. Section 7.12.5.1.2.2 lists the SPI slave
mode timing requirements.
Figure 7-77 shows the SPI slave mode external timing where the clock phase = 0. Figure 7-78 shows the SPI
slave mode external timing where the clock phase = 1.
7.12.5.1.2.1 SPI Slave Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER
MIN
MAX UNIT
15 td(SOMI)S
16 tv(SOMI)S
Delay time, SPICLK to SPISOMI valid
Valid time, SPISOMI valid after SPICLK
16
ns
ns
0
7.12.5.1.2.2 SPI Slave Mode Timing Requirements
NO.
MIN
4tc(SYSCLK)
MAX UNIT
12 tc(SPC)S
13 tw(SPC1)S
14 tw(SPC2)S
19 tsu(SIMO)S
20 th(SIMO)S
Cycle time, SPICLK
ns
ns
ns
ns
ns
Pulse duration, SPICLK, first pulse
Pulse duration, SPICLK, second pulse
Setup time, SPISIMO valid before SPICLK
Hold time, SPISIMO valid after SPICLK
2tc(SYSCLK) – 1
2tc(SYSCLK) – 1
1.5tc(SYSCLK)
1.5tc(SYSCLK)
Setup time, SPISTE valid before
SPICLK (Clock Phase = 0)
2tc(SYSCLK) + 2
ns
25 tsu(STE)S
Setup time, SPISTE valid before
SPICLK (Clock Phase = 1)
2tc(SYSCLK) + 22
1.5tc(SYSCLK)
ns
ns
26 th(STE)S
Hold time, SPISTE invalid after SPICLK
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
15
16
SPISOMI
SPISOMI Data Is Valid
19
20
SPISIMO Data
Must Be Valid
SPISIMO
SPISTE
25
26
Figure 7-77. SPI Slave Mode External Timing (Clock Phase = 0)
Copyright © 2021 Texas Instruments Incorporated
164 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
15
SPISOMI
SPISOMI Data Is Valid
Data Valid
Data Valid
16
19
20
SPISIMO Data
Must Be Valid
SPISIMO
SPISTE
26
25
Figure 7-78. SPI Slave Mode External Timing (Clock Phase = 1)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 165
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
7.12.5.1.3 High-Speed Master Mode Timings
Section 7.12.5.1.3.1 lists the SPI high-speed master mode switching characteristics where the clock phase = 0.
Figure 7-79 shows the high-speed SPI master mode external timing where the clock phase = 0.
Section 7.12.5.1.3.2 lists the SPI high-speed master mode switching characteristics where the clock phase = 1.
Figure 7-80 shows the high-speed SPI master mode external timing where the clock phase = 1.
Section 7.12.5.1.3.3 lists the SPI high-speed master mode timing requirements.
7.12.5.1.3.1 SPI High-Speed Master Mode Switching Characteristics (Clock Phase = 0)
over recommended operating conditions (unless otherwise noted)
(BRR + 1)
NO.
PARAMETER
MIN
MAX UNIT
128tc(LSPCLK)
CONDITION(1)
Even
4tc(LSPCLK)
5tc(LSPCLK)
1
tc(SPC)M
Cycle time, SPICLK
ns
Odd
127tc(LSPCLK)
Even
0.5tc(SPC)M – 1
0.5tc(SPC)M + 1
2
tw(SPC1)M
Pulse duration, SPICLK, first pulse
ns
0.5tc(SPC)M
0.5tc(LSPCLK) – 1
+
0.5tc(SPC)M +
0.5tc(LSPCLK) + 1
Odd
Even
Odd
0.5tc(SPC)M – 1
0.5tc(SPC)M + 1
Pulse duration, SPICLK, second
pulse
3
4
5
tw(SPC2)M
td(SIMO)M
tv(SIMO)M
ns
ns
ns
0.5tc(SPC)M
0.5tc(LSPCLK) – 1
–
0.5tc(SPC)M
–
0.5tc(LSPCLK) + 1
Delay time, SPICLK to SPISIMO valid Even, Odd
3
Even
0.5tc(SPC)M – 4
0.5tc(SPC)M
0.5tc(LSPCLK) – 1
1.5tc(SPC)M
3tc(SYSCLK) – 1
1.5tc(SPC)M
Valid time, SPISIMO valid after
SPICLK
–
Odd
–
Even
23 td(SPC)M
Delay time, SPISTE valid to SPICLK
ns
ns
–
Odd
Even
Odd
3tc(SYSCLK) – 1
0.5tc(SPC)M – 4
Delay time, SPICLK to SPISTE
invalid
24 td(STE)M
0.5tc(SPC)M
0.5tc(LSPCLK) – 1
–
(1) The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR is
greater than 3.
7.12.5.1.3.2 SPI High-Speed Master Mode Switching Characteristics (Clock Phase = 1)
over recommended operating conditions (unless otherwise noted)
(BRR + 1)
NO.
PARAMETER
MIN
MAX UNIT
128tc(LSPCLK)
CONDITION(1)
Even
4tc(LSPCLK)
5tc(LSPCLK)
1
tc(SPC)M
Cycle time, SPICLK
ns
Odd
127tc(LSPCLK)
Even
0.5tc(SPC)M – 3
0.5tc(SPC)M + 3
2
3
4
5
tw(SPCH)M
Pulse duration, SPICLK, first pulse
ns
0.5tc(SPC)M
0.5tc(LSPCLK) – 3
–
0.5tc(SPC)M –
0.5tc(LSPCLK) + 3
Odd
Even
Odd
Even
Odd
Even
Odd
0.5tc(SPC)M – 3
0.5tc(SPC)M + 3
Pulse duration, SPICLK, second
pulse
tw(SPC2)M
td(SIMO)M
tv(SIMO)M
ns
ns
ns
0.5tc(SPC)M
0.5tc(LSPCLK) – 3
+
0.5tc(SPC)M
+
0.5tc(LSPCLK) + 3
0.5tc(SPC)M – 4
Delay time, SPISIMO valid to SPICLK
0.5tc(SPC)M
0.5tc(LSPCLK) – 1
+
0.5tc(SPC)M – 6
Valid time, SPISIMO valid after
SPICLK
0.5tc(SPC)M
0.5tc(LSPCLK) – 1
–
Copyright © 2021 Texas Instruments Incorporated
166 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
over recommended operating conditions (unless otherwise noted)
(BRR + 1)
NO.
PARAMETER
MIN
MAX UNIT
CONDITION(1)
2tc(SPC)M
3tc(SYSCLK) – 1
–
23 td(SPC)M
Delay time, SPISTE valid to SPICLK Even, Odd
ns
Even
0.5tc(SPC)M – 6
Delay time, SPICLK to SPISTE
invalid
24 td(STE)M
ns
0.5tc(SPC)M
–
Odd
0.5tc(LSPCLK) – 1
(1) The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR is
greater than 3.
7.12.5.1.3.3 SPI High-Speed Master Mode Timing Requirements
(BRR + 1)
NO.
8
MIN
2
MAX UNIT
CONDITION(1)
Setup time, SPISOMI valid before
SPICLK
tsu(SOMI)M
th(SOMI)M
Even, Odd
ns
ns
Hold time, SPISOMI valid after
SPICLK
9
Even, Odd
11
(1) The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR is
greater than 3.
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISIMO
Master Out Data Is Valid
8
9
Master In Data
Must Be Valid
SPISOMI
SPISTE(A)
24
23
A. On the trailing end of the word, SPISTE will go inactive except between back-to-back transmit words in both FIFO and non-FIFO modes.
Figure 7-79. High-Speed SPI Master Mode External Timing (Clock Phase = 0)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 167
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISIMO
Master Out Data Is Valid
8
9
Master In Data Must
Be Valid
SPISOMI
SPISTE(A)
24
23
A. On the trailing end of the word, SPISTE will go inactive except between back-to-back transmit words in both FIFO and non-FIFO modes.
Figure 7-80. High-Speed SPI Master Mode External Timing (Clock Phase = 1)
Copyright © 2021 Texas Instruments Incorporated
168 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
7.12.5.1.4 High-Speed Slave Mode Timings
Section 7.12.5.1.4.1 lists the SPI high-speed slave mode switching characteristics. Section 7.12.5.1.4.2 lists the
SPI high-speed slave mode timing requirements.
Figure 7-81 shows the high-speed SPI slave mode external timing where the clock phase = 0. Figure 7-82
shows the high-speed SPI slave mode external timing where the clock phase = 1.
7.12.5.1.4.1 SPI High-Speed Slave Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER
MIN
MAX UNIT
15 td(SOMI)S
16 tv(SOMI)S
Delay time, SPICLK to SPISOMI valid
Valid time, SPISOMI valid after SPICLK
14
ns
ns
0
7.12.5.1.4.2 SPI High-Speed Slave Mode Timing Requirements
NO.
MIN
4tc(SYSCLK)
MAX UNIT
12 tc(SPC)S
13 tw(SPC1)S
14 tw(SPC2)S
19 tsu(SIMO)S
20 th(SIMO)S
25 tsu(STE)S
26 th(STE)S
Cycle time, SPICLK
ns
ns
ns
ns
ns
ns
ns
Pulse duration, SPICLK, first pulse
Pulse duration, SPICLK, second pulse
Setup time, SPISIMO valid before SPICLK
Hold time, SPISIMO valid after SPICLK
Setup time, SPISTE valid before SPICLK
Hold time, SPISTE invalid after SPICLK
2tc(SYSCLK) – 1
2tc(SYSCLK) – 1
1.5tc(SYSCLK)
1.5tc(SYSCLK)
1.5tc(SYSCLK)
1.5tc(SYSCLK)
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
15
16
SPISOMI
SPISOMI Data Is Valid
19
20
SPISIMO Data
Must Be Valid
SPISIMO
SPISTE
25
26
Figure 7-81. High-Speed SPI Slave Mode External Timing (Clock Phase = 0)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 169
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
15
SPISOMI
SPISOMI Data Is Valid
Data Valid
Data Valid
16
19
20
SPISIMO Data
Must Be Valid
SPISIMO
SPISTE
26
25
Figure 7-82. High-Speed SPI Slave Mode External Timing (Clock Phase = 1)
Copyright © 2021 Texas Instruments Incorporated
170 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
7.12.6 Local Interconnect Network (LIN)
This device contains one Local Interconnect Network (LIN) module. The LIN module adheres to the LIN 2.1
standard as defined by the LIN Specification Package Revision 2.1. The LIN is a low-cost serial interface
designed for applications where the CAN protocol may be too expensive to implement, such as small
subnetworks for cabin comfort functions like interior lighting or window control in an automotive application.
The LIN standard is based on the SCI (UART) serial data link format. The communication concept is single-
master and multiple-slave with a message identification for multicast transmission between any network nodes.
The LIN module can be programmed to work either as an SCI or as a LIN as the core of the module is an SCI.
The hardware features of the SCI are augmented to achieve LIN compatibility. The SCI module is a universal
asynchronous receiver-transmitter (UART) that implements the standard non-return-to-zero format.
Though the registers are common for LIN and SCI, the register descriptions have notes to identify the register/bit
usage in different modes. Because of this, code written for this module cannot be directly ported to the stand-
alone SCI module and vice versa.
The LIN module has the following features:
•
•
•
•
•
•
Compatibility with LIN 1.3, 2.0 and 2.1 protocols
Configurable baud rate up to 20 kbps (as per LIN 2.1 protocol)
Two external pins: LINRX and LINTX
Multibuffered receive and transmit units
Identification masks for message filtering
Automatic master header generation
– Programmable synchronization break field
– Synchronization field
– Identifier field
•
Slave automatic synchronization
– Synchronization break detection
– Optional baud rate update
– Synchronization validation
•
•
•
231 programmable transmission rates with 7 fractional bits
Wakeup on LINRX dominant level from transceiver
Automatic wakeup support
– Wakeup signal generation
– Expiration times on wakeup signals
Automatic bus idle detection
Error detection
•
•
– Bit error
– Bus error
– No-response error
– Checksum error
– Synchronization field error
– Parity error
•
•
Capability to use direct memory access (DMA) for transmit and receive data
Two interrupt lines with priority encoding for:
– Receive
– Transmit
– ID, error, and status
•
•
•
Support for LIN 2.0 checksum
Enhanced synchronizer finite state machine (FSM) support for frame processing
Enhanced handling of extended frames
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 171
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
•
•
Enhanced baud rate generator
Update wakeup/go to sleep
Figure 7-83 shows the LIN block diagram.
READ DATA BUS
WRITE DATA BUS
ADDRESS BUS
CHECKSUM
CALCULATOR
INTERFACE
ID PARTY
CHECKER
BIT
MONITOR
TXRX ERROR
DETECTOR (TED)
TIME-OUT
CONTROL
COUNTER
LINRX/
SCIRX
COMPARE
LINTX/
SCITX
DMA
CONTROL
MASK
FILTER
8 RECEIVE
BUFFERS
FSM
8 TRANSMIT
BUFFERS
SYNCHRONIZER
Figure 7-83. LIN Block Diagram
Copyright © 2021 Texas Instruments Incorporated
172 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
7.12.7 Fast Serial Interface (FSI)
The Fast Serial Interface (FSI) module is a serial communication peripheral capable of reliable and robust high-
speed communications. The FSI is designed to ensure data robustness across many system conditions such as
chip-to-chip as well as board-to-board across an isolation barrier. Payload integrity checks such as CRC, start-
and end-of-frame patterns, and user-defined tags, are encoded before transmit and then verified after receipt
without additional CPU interaction. Line breaks can be detected using periodic transmissions, all managed and
monitored by hardware. The FSI is also tightly integrated with other control peripherals on the device. To ensure
that the latest sensor data or control parameters are available, frames can be transmitted on every control loop
period. An integrated skew-compensation block has been added on the receiver to handle skew that may occur
between the clock and data signals due to a variety of factors, including trace-length mismatch and skews
induced by an isolation chip. With embedded data robustness checks, data-link integrity checks, skew
compensation, and integration with control peripherals, the FSI can enable high-speed, robust communication in
any system. These and many other features of the FSI follow.
The FSI module includes the following features:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Independent transmitter and receiver cores
Source-synchronous transmission
Dual data rate (DDR)
One or two data lines
Programmable data length
Skew adjustment block to compensate for board and system delay mismatches
Frame error detection
Programmable frame tagging for message filtering
Hardware ping to detect line breaks during communication (ping watchdog)
Two interrupts per FSI core
Externally triggered frame generation
Hardware- or software-calculated CRC
Embedded ECC computation module
Register write protection
DMA support
CLA task triggering
SPI compatibility mode (limited features available)
Operating the FSI at maximum speed (50 MHz) at dual data rate (100 Mbps) may require the integrated skew
compensation block to be configured according to the specific operating conditions on a case-by-case basis.
The Fast Serial Interface (FSI) Skew Compensation Application Report provides example software on how to
configure and set up the integrated skew compensation block on the Fast Serial Interface.
The FSI consists of independent transmitter (FSITX) and receiver (FSIRX) cores. The FSITX and FSIRX cores
are configured and operated independently. The features available on the FSITX and FSIRX are described in
Section 7.12.7.1 and Section 7.12.7.2, respectively.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 173
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
7.12.7.1 FSI Transmitter
The FSI transmitter module handles the framing of data, CRC generation, signal generation of TXCLK, TXD0,
and TXD1, as well as interrupt generation. The operation of the transmitter core is controlled and configured
through programmable control registers. The transmitter control registers let the CPU (or the CLA) program,
control, and monitor the operation of the FSI transmitter. The transmit data buffer is accessible by the CPU, CLA,
and the DMA.
The transmitter has the following features:
•
•
•
•
•
•
•
•
•
•
Automated ping frame generation
Externally triggered ping frames
Externally triggered data frames
Software-configurable frame lengths
16-word data buffer
Data buffer underrun and overrun detection
Hardware-generated CRC on data bits
Software ECC calculation on select data
DMA support
CLA task triggering
Figure 7-84 shows the FSITX CPU interface. Figure 7-85 shows the high-level block diagram of the FSITX. Not
all data paths and internal connections are shown. This diagram provides a high-level overview of the internal
modules present in the FSITX.
PLLRAWCLK
PCLKCR18
SYSCLK
SYSRSN
C28x
ePIE
FSITXyINT1
FSITXyINT2
CLA
FSITXyCLK
FSITXyD0
FSITXyD1
FSITX
DMA
FSITXyDMA
32
A. The signals connected to the trigger muxes are described in the External Frame Trigger Mux section of the Fast Serial Interface (FSI)
chapter in the TMS320F28004x Microcontrollers Technical Reference Manual.
Figure 7-84. FSITX CPU Interface
Copyright © 2021 Texas Instruments Incorporated
174 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
FSITX
PLLRAWCLK
SYSRSN
SYSCLK
FSI Mode:
TXCLKIN
Transmit Clock
Generator
TXCLK = TXCLKIN/2
SPI Signaling Mode:
TXCLK = TXCLKIN
Register Interface
Core Reset
FSITXINT1
FSITXINT2
Control Registers,
Interrupt Management
TXCLK
TXD0
TXD1
Ping Time-out Counter
FSITX_DMA_EVT
Transmitter Core
External Frame Triggers
Transmit Data
Buffer
ECC Logic
Figure 7-85. FSITX Block Diagram
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 175
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
7.12.7.1.1 FSITX Electrical Data and Timing
Section 7.12.7.1.1.1 lists the FSITX switching characteristics. Figure 7-86 shows the FSITX timings.
7.12.7.1.1.1 FSITX Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
NO.
PARAMETER
MIN
20
MAX
UNIT
ns
1
tc(TXCLK)
tw(TXCLK)
Cycle time, TXCLK
2
Pulse width, TXCLK low or TXCLK high
(0.5tc(TXCLK)) – 1
(0.5tc(TXCLK)) + 1
ns
Delay time, Data valid after TXCLK rising or
falling
3
td(TXCLKL–TXD)
(0.25tc(TXCLK)) – 3.2
(0.25tc(TXCLK)) + 4.7
ns
1
2
FSITXCLK
FSITXD0
FSITXD1
3
Figure 7-86. FSITX Timings
Copyright © 2021 Texas Instruments Incorporated
176 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
7.12.7.2 FSI Receiver
The receiver module interfaces to the FSI clock (RXCLK), and data lines (RXD0 and RXD1) after they pass
through an optional programmable delay line. The receiver core handles the data framing, CRC computation,
and frame-related error checking. The receiver bit clock and state machine are run by the RXCLK input, which is
asynchronous to the device system clock.
The receiver control registers let the CPU (or the CLA) program, control, and monitor the operation of the FSIRX.
The receive data buffer is accessible by the CPU, CLA, and the DMA.
The receiver core has the following features:
•
•
•
•
•
•
•
•
•
•
16-word data buffer
Multiple supported frame types
Ping frame watchdog
Frame watchdog
CRC calculation and comparison in hardware
ECC detection
Programmable delay line control on incoming signals
DMA support
CLA task triggering
SPI compatibility mode
Figure 7-87 shows the FSIRX CPU interface. Figure 7-88 provides a high-level overview of the internal modules
present in the FSIRX. Not all data paths and internal connections are shown.
PCLKCR18
SYSCLK
SYSRSN
C28x
ePIE
FSIRXyINT1
FSIRXyINT2
CLA
FSIRXyCLK
FSIRXyD0
FSIRXyD1
FSIRX
DMA
FSIRXyDMA
Figure 7-87. FSIRX CPU Interface
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 177
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
FSIRX
SYSRSn
SYSCLK
Frame Watchdog
Register Interface
Core Reset
FSIRXINT1
Control Registers,
Interrupt Management
FSIRXINT2
RXCLK
RXD0
Ping Watchdog
FSIRX_DMA_EVT
Receiver Core
Skew
Control
RXD1
Receive Data
Buffer
ECC Check
Logic
Figure 7-88. FSIRX Block Diagram
Copyright © 2021 Texas Instruments Incorporated
178 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
7.12.7.2.1 FSIRX Electrical Data and Timing
Section 7.12.7.2.1.1 lists the FSIRX switching characteristics. Section 7.12.7.2.1.2 lists the FSIRX timing
requirements. Figure 7-89 shows the FSIRX timings.
7.12.7.2.1.1 FSIRX Switching Characteristics
NO.
PARAMETER
MIN
MAX
UNIT
RXCLK delay compensation at
RX_DLYLINE_CTRL[RXCLK_DLY]=31
1
td(RXCLK)
6
21
ns
RXD0 delay compensation at
RX_DLYLINE_CTRL[RXD0_DLY]=31
2
3
4
td(RXD0)
6
6
21
21
ns
ns
ns
RXD1 delay compensation at
RX_DLYLINE_CTRL[RXD1_DLY]=31
td(RXD1)
Incremental delay of each delay line element
for RXCLK, RXD0, and RXD1
td(DELAY_ELEMENT)
0.17
0.7
7.12.7.2.1.2 FSIRX Timing Requirements
NO.
MIN
20
MAX
UNIT
ns
1
2
tc(RXCLK)
tw(RXCLK)
Cycle time, RXCLK
Pulse width, RXCLK low or RXCLK high
(0.5tc(RXCLK)) – 1
(0.5tc(RXCLK)) + 1
ns
Setup time with respect to RXCLK, applies to
both edges of the clock
3
4
tsu(RXCLK–RXD)
th(RXCLK–RXD)
1.7
3.8
ns
ns
Hold time with respect to RXCLK, applies to
both edges of the clock
1
2
FSIRXCLK
FSIRXD0
FSIRXD1
3
4
Figure 7-89. FSIRX Timings
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 179
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
7.12.7.3 FSI SPI Compatibility Mode
The FSI supports a SPI compatibility mode to enable communication with programmable SPI devices. In this
mode, the FSI transmits its data in the same manner as a SPI in a single clock configuration mode. While the
FSI is able to physically interface with a SPI in this mode, the external device must be able to encode and
decode an FSI frame to communicate successfully. This is because the FSI transmits all SPI frame phases with
the exception of the preamble and postamble. The FSI provides the same data validation and frame checking as
if it was in standard FSI mode, allowing for more robust communication without consuming CPU cycles. The
external SPI is required to send all relevant information and can access standard FSI features such as the ping
frame watchdog on the FSIRX, frame tagging, or custom CRC values. The list of features of SPI compatibility
mode follows:
•
•
•
Data will transmit on rising edge and receive on falling edge of the clock.
Only 16-bit word size is supported.
TXD1 will be driven like an active-low chip-select signal. The signal will be low for the duration of the full
frame transmission.
•
•
•
No receiver chip-select input is required. RXD1 is not used. Data is shifted into the receiver on every active
clock edge.
No preamble or postamble clocks will be transmitted. All signals return to the idle state after the frame phase
is finished.
It is not possible to transmit in the SPI slave configuration because the FSI TXCLK cannot take an external
clock source.
7.12.7.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
Section 7.12.7.3.1.1 lists the FSITX SPI signaling mode switching characteristics. Figure 7-90 shows the FSITX
SPI signaling mode timings. Special timings are not required for the FSIRX in SPI signaling mode. FSIRX
timings listed in Section 7.12.7.2.1.2 are applicable in SPI compatibility mode. Setup and Hold times are only
valid on the falling edge of FSIRXCLK because this is the active edge in SPI signaling mode.
7.12.7.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
NO.
PARAMETER
MIN
20
MAX
UNIT
ns
1
tc(TXCLK)
Cycle time, TXCLK
2
tw(TXCLK)
Pulse width, TXCLK low or TXCLK high
Delay time, Data valid after TXCLK high
Delay time, TXCLK high after TXD1 low
Delay time, TXD1 high after TXCLK low
(0.5tc(TXCLK)) – 1
(0.5tc(TXCLK)) + 1
3
ns
3
td(TXCLKH–TXD0)
td(TXD1-TXCLK)
td(TXCLK-TXD1)
ns
4
tw(TXCLK) – 1
tw(TXCLK) – 1
ns
5
ns
1
2
FSITXCLK
3
FSITXD0
FSITXD1
5
4
Figure 7-90. FSITX SPI Signaling Mode Timings
Copyright © 2021 Texas Instruments Incorporated
180 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
8 Detailed Description
8.1 Overview
The TMS320F28004x (F28004x) is a powerful 32-bit floating-point microcontroller unit (MCU) that lets designers
incorporate crucial control peripherals, differentiated analog, and nonvolatile memory on a single device.
The real-time control subsystem is based on TI’s 32-bit C28x CPU, which provides 100 MHz of signal processing
performance. The C28x CPU is further boosted by the new TMU extended instruction set, which enables fast
execution of algorithms with trigonometric operations commonly found in transforms and torque loop
calculations; and the VCU-I extended instruction set, which reduces the latency for complex math operations
commonly found in encoded applications.
The CLA allows significant offloading of common tasks from the main C28x CPU. The CLA is an independent
32-bit floating-point math accelerator that executes in parallel with the CPU. Additionally, the CLA has its own
dedicated memory resources and it can directly access the key peripherals that are required in a typical control
system. Support of a subset of ANSI C is standard, as are key features like hardware breakpoints and hardware
task-switching.
The F28004x supports up to 256KB (128KW) of flash memory divided into two 128KB (64KW) banks, which
enables programming and execution in parallel. Up to 100KB (50KW) of on-chip SRAM is also available in
blocks of 4KB (2KW) and 16KB (8KW) for efficient system partitioning. Flash ECC, SRAM ECC/parity, and dual-
zone security are also supported.
High-performance analog blocks are integrated on the F28004x MCU to further enable system consolidation.
Three separate 12-bit ADCs provide precise and efficient management of multiple analog signals, which
ultimately boosts system throughput. Seven PGAs on the analog front end enable on-chip voltage scaling before
conversion. Seven analog comparator modules provide continuous monitoring of input voltage levels for trip
conditions.
The TMS320C2000™ microcontrollers contain industry-leading control peripherals with frequency-independent
ePWM/HRPWM and eCAP allow for a best-in-class level of control to the system. The built-in 4-channel SDFM
allows for seamless integration of an oversampling sigma-delta modulator across an isolation barrier.
Connectivity is supported through various industry-standard communication ports (such as SPI, SCI, I2C, LIN,
and CAN) and offers multiple muxing options for optimal signal placement in a variety of applications. New to the
C2000 platform is the fully compliant PMBus. Additionally, in an industry first, the FSI enables high-speed, robust
communication to complement the rich set of peripherals that are embedded in the device.
A specially enabled device variant, TMS320F28004xC, allows access to the Configurable Logic Block (CLB) for
additional interfacing features and allows access to the secure ROM, which includes a library to enable
InstaSPIN-FOC™. See Device Comparison for more information.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 181
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
8.2 Functional Block Diagram
Figure 8-1 shows the CPU system and associated peripherals.
Boot ROM
C28x CPU
CLA
(Type 2)
Secure ROM
FPU32
TMU
VCU-I
Flash Bank0
16 Sectors
64KW (128KB)
CLA to CPU MSG RAM
CPU to CLA MSG RAM
Flash Bank1
16 Sectors
64KW (128KB)
CPU Timers
DCSM
ePIE
CLA Data ROM
ERAD
CLA Program ROM
M0–M1 RAM
2KW (4KB)
LS0–LS7 RAM
16KW (32KB)
Crystal Oscillator
INTOSC1, INTOSC2
PLL
GS0–GS3 RAM
32KW (64KB)
DMA
6 Channels
PF1
PF3
PF4
PF2
PF7
PF8
PF9
Result
Data
40x GPIO
16x ePWM Chan.
(16 Hi-Res Capable)
2x CAN
1x LIN
2x SCI
1x I2C
1x PMBUS
2x SPI
7x CMPSS
3x 12-Bit ADC
7x eCAP
(2 HRCAP Capable)
2x Buffered DAC
7x PGA
Input XBAR
Output XBAR
ePWM XBAR
NMI
Watchdog
1x FSI RX
1x FSI TX
2x eQEP
(CW/CCW Support)
Windowed
Watchdog
4x SD Filters
Figure 8-1. Functional Block Diagram
Copyright © 2021 Texas Instruments Incorporated
182 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
8.3 Memory
8.3.1 C28x Memory Map
Table 8-1 describes the C28x memory map. Memories accessible by the CLA or DMA (direct memory access)
are also noted. See the Memory Controller Module section of the System Control chapter in the
TMS320F28004x Microcontrollers Technical Reference Manual.
Table 8-1. C28x Memory Map
MEMORY
ACCESS
PROTECTION
START
ADDRESS
END
DMA
ECC-
CAPABLE
MEMORY
SIZE
CLA ACCESS
PARITY
SECURE
ADDRESS
ACCESS
M0 RAM
1K × 16
1K × 16
512 × 16
128 × 16
128 × 16
2K × 16
2K × 16
2K × 16
2K × 16
2K × 16
2K × 16
2K × 16
2K × 16
8K × 16
8K × 16
8K × 16
8K × 16
2K × 16
2K × 16
64K × 16
64K × 16
32K × 16
64K × 16
64 × 16
4K × 16
0x0000 0000
0x0000 0400
0x0000 0D00
0x0000 1480
0x0000 1500
0x0000 8000
0x0000 8800
0x0000 9000
0x0000 9800
0x0000 A000
0x0000 A800
0x0000 B000
0x0000 B800
0x0000 C000
0x0000 E000
0x0001 0000
0x0001 2000
0x0004 9000
0x0004 B000
0x0008 0000
0x0009 0000
0x003E 8000
0x003F 0000
0x003F FFC0
0x0100 1000
0x0000 03FF
0x0000 07FF
0x0000 0EFF
0x0000 14FF
0x0000 157F
0x0000 87FF
0x0000 8FFF
0x0000 97FF
0x0000 9FFF
0x0000 A7FF
0x0000 AFFF
0x0000 B7FF
0x0000 BFFF
0x0000 DFFF
0x0000 FFFF
0x0001 1FFF
0x0001 3FFF
0x0004 97FF
0x0004 B7FF
0x0008 FFFF
0x0009 FFFF
0x003E FFFF
0x003F FFBF
0x003F FFFF
0x0100 1FFF
Yes
Yes
M1 RAM
PieVectTable
CLA-to-CPU MSGRAM
CPU-to-CLA MSGRAM
LS0 RAM
Read/Write
Read
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Configurable
Configurable
Configurable
Configurable
Configurable
Configurable
Configurable
Configurable
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
LS1 RAM
LS2 RAM
LS3 RAM
LS4 RAM
LS5 RAM
LS6 RAM
LS7 RAM
GS0 RAM
Yes
Yes
Yes
Yes
Yes
Yes
GS1 RAM
GS2 RAM
GS3 RAM
CAN A Message RAM
CAN B Message RAM
Flash Bank 0
Flash Bank 1
Secure ROM
Boot ROM
Yes
Yes
N/A
N/A
Yes
Yes
Yes
Vectors
CLA Data ROM
Read
8.3.2 Control Law Accelerator (CLA) ROM Memory Map
Table 8-2 shows the CLA data ROM memory map. For information about the CLA program ROM, see the CLA
Program ROM (CLAPROMCRC) chapter in the TMS320F28004x Microcontrollers Technical Reference Manual.
Table 8-2. CLA Data ROM Memory Map
MEMORY
FFT Tables (Load)
Data (Load)
START ADDRESS
0x0100 1070
0x0100 1870
0x0100 1FFA
0x0000 F070
0x0000 F870
0x0000 FFFA
END ADDRESS
0x0100 186F
0x0100 1FF9
0x0100 1FFF
0x0000 F86F
0x0000 FFF9
0x0000 FFFF
LENGTH
0x0800
0x078A
0x0006
0x0800
0x078A
0x0006
Version (Load)
FFT Tables (Run)
Data (Run)
Version (Run)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 183
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
8.3.3 Flash Memory Map
On the F28004x devices, up to two flash banks (each 128KB [64KW]) are available. The flash banks are
controlled by a single FMC (flash module controller). On the devices in which there is only one flash bank
(F280041 and F280040), the code to program the flash should be executed out of RAM. On the devices in which
there are two flash banks (F280049, F280048, and F280045), only one bank at a time can be programmed or
erased. In the dual-bank devices, the code to program the flash can be executed from one flash bank to erase or
program the other flash bank, or the code can be executed from RAM. There should not be any kind of access to
the flash bank on which an erase/program operation is in progress. Table 8-3 lists the addresses of flash sectors
for F280049, F280048, and F280045. Table 8-4 lists the addresses of flash sectors for F280041 and F280040.
Table 8-3. Addresses of Flash Sectors for F280049, F280048, and F280045
SECTOR
SIZE
START ADDRESS
END ADDRESS
OTP SECTORS
TI OTP Bank 0
1K × 16
1K × 16
1K × 16
1K × 16
0x0007 0000
0x0007 8000
0x0007 0400
0x0007 8400
0x0007 03FF
0x0007 83FF
0x0007 07FF
0x0007 87FF
User-configurable DCSM OTP Bank 0
TI OTP Bank 1
User-configurable DCSM OTP Bank 1
BANK 0 SECTORS
Sector 0
Sector 1
Sector 2
Sector 3
Sector 4
Sector 5
Sector 6
Sector 7
Sector 8
Sector 9
Sector 10
Sector 11
Sector 12
Sector 13
Sector 14
Sector 15
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
0x0008 0000
0x0008 1000
0x0008 2000
0x0008 3000
0x0008 4000
0x0008 5000
0x0008 6000
0x0008 7000
0x0008 8000
0x0008 9000
0x0008 A000
0x0008 B000
0x0008 C000
0x0008 D000
0x0008 E000
0x0008 F000
0x0008 0FFF
0x0008 1FFF
0x0008 2FFF
0x0008 3FFF
0x0008 4FFF
0x0008 5FFF
0x0008 6FFF
0x0008 7FFF
0x0008 8FFF
0x0008 9FFF
0x0008 AFFF
0x0008 BFFF
0x0008 CFFF
0x0008 DFFF
0x0008 EFFF
0x0008 FFFF
BANK 1 SECTORS
Sector 0
Sector 1
Sector 2
Sector 3
Sector 4
Sector 5
Sector 6
Sector 7
Sector 8
Sector 9
Sector 10
Sector 11
Sector 12
Sector 13
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
0x0009 0000
0x0009 1000
0x0009 2000
0x0009 3000
0x0009 4000
0x0009 5000
0x0009 6000
0x0009 7000
0x0009 8000
0x0009 9000
0x0009 A000
0x0009 B000
0x0009 C000
0x0009 D000
0x0009 0FFF
0x0009 1FFF
0x0009 2FFF
0x0009 3FFF
0x0009 4FFF
0x0009 5FFF
0x0009 6FFF
0x0009 7FFF
0x0009 8FFF
0x0009 9FFF
0x0009 AFFF
0x0009 BFFF
0x0009 CFFF
0x0009 DFFF
Copyright © 2021 Texas Instruments Incorporated
184 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
Table 8-3. Addresses of Flash Sectors for F280049, F280048, and F280045 (continued)
SECTOR
Sector 14
Sector 15
SIZE
START ADDRESS
END ADDRESS
0x0009 EFFF
0x0009 FFFF
4K × 16
4K × 16
0x0009 E000
0x0009 F000
FLASH ECC LOCATIONS
TI OTP ECC Bank 0
TI OTP ECC Bank 1
128 × 16
128 × 16
128 × 16
128 × 16
8K × 16
8K × 16
0x0107 0000
0x0107 007F
0x0107 00FF
0x0107 107F
0x0107 10FF
0x0108 1FFF
0x0108 3FFF
0x0107 0080
0x0107 1000
0x0107 1080
0x0108 0000
0x0108 2000
User-configurable DCSM OTP ECC Bank 0
User-configurable DCSM OTP ECC Bank 1
Flash ECC Bank 0
Flash ECC Bank 1
Table 8-4. Addresses of Flash Sectors for F280041 and F280040
SECTOR
SIZE
START ADDRESS
END ADDRESS
OTP SECTORS
TI OTP Bank 0
1K × 16
1K × 16
0x0007 0000
0x0007 8000
0x0007 03FF
0x0007 83FF
User-configurable DCSM OTP Bank 0
BANK 0 SECTORS
Sector 0
Sector 1
Sector 2
Sector 3
Sector 4
Sector 5
Sector 6
Sector 7
Sector 8
Sector 9
Sector 10
Sector 11
Sector 12
Sector 13
Sector 14
Sector 15
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
0x0008 0000
0x0008 1000
0x0008 2000
0x0008 3000
0x0008 4000
0x0008 5000
0x0008 6000
0x0008 7000
0x0008 8000
0x0008 9000
0x0008 A000
0x0008 B000
0x0008 C000
0x0008 D000
0x0008 E000
0x0008 F000
0x0008 0FFF
0x0008 1FFF
0x0008 2FFF
0x0008 3FFF
0x0008 4FFF
0x0008 5FFF
0x0008 6FFF
0x0008 7FFF
0x0008 8FFF
0x0008 9FFF
0x0008 AFFF
0x0008 BFFF
0x0008 CFFF
0x0008 DFFF
0x0008 EFFF
0x0008 FFFF
FLASH ECC LOCATIONS
TI OTP ECC Bank 0
User-configurable DCSM OTP ECC Bank 0
Flash ECC Bank 0
128 × 16
128 × 16
8K × 16
0x0107 0000
0x0107 007F
0x0107 107F
0x0108 1FFF
0x0107 1000
0x0108 0000
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 185
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
8.3.4 Peripheral Registers Memory Map
Table 8-5 lists the peripheral registers.
Table 8-5. Peripheral Registers Memory Map
PIPELINE
CLA
ACCESS
DMA
ACCESS
REGISTER
STRUCTURE NAME
START ADDRESS
END ADDRESS
PROTECTION(1)
Peripheral Frame 0
0x0000 0B00
AdcaResultRegs(2)
AdcbResultRegs(2)
AdccResultRegs(2)
ADC_RESULT_REGS
ADC_RESULT_REGS
ADC_RESULT_REGS
0x0000 0B1F
0x0000 0B3F
0x0000 0B5F
Yes
Yes
Yes
Yes
Yes
Yes
0x0000 0B20
0x0000 0B40
Yes - CLA
only no CPU
access
Cla1OnlyRegs
CLA_ONLY_REGS
0x0000 0C00
0x0000 0CFF
CpuTimer0Regs
CpuTimer1Regs
CpuTimer2Regs
PieCtrlRegs
CPUTIMER_REGS
CPUTIMER_REGS
CPUTIMER_REGS
PIE_CTRL_REGS
0x0000 0C00
0x0000 0C08
0x0000 0C10
0x0000 0CE0
0x0000 0C07
0x0000 0C0F
0x0000 0C17
0x0000 0CFF
Yes - CLA
only no CPU
access
Cla1SoftIntRegs
CLA_SOFTINT_REGS
0x0000 0CE0
0x0000 0CFF
DmaRegs
Cla1Regs
DMA_REGS
CLA_REGS
0x0000 1000
0x0000 1400
Peripheral Frame 1
0x0000 4000
0x0000 4100
0x0000 4200
0x0000 4300
0x0000 4400
0x0000 4500
0x0000 4600
0x0000 4700
0x0000 5100
0x0000 5140
0x0000 5200
0x0000 5240
0x0000 5280
0x0000 52C0
0x0000 5300
0x0000 5340
0x0000 5360
0x0000 5380
0x0000 53A0
0x0000 5B00
0x0000 5B10
0x0000 5B20
0x0000 5B30
0x0000 5B40
0x0000 5B50
0x0000 5B60
0x0000 5C00
0x0000 5C10
0x0000 5C80
0x0000 5CA0
0x0000 5CC0
0x0000 5CE0
0x0000 5D00
0x0000 5D20
0x0000 5D40
0x0000 5E00
0x0000 11FF
0x0000 147F
Yes
EPwm1Regs
EPwm2Regs
EPwm3Regs
EPwm4Regs
EPwm5Regs
EPwm6Regs
EPwm7Regs
EPwm8Regs
EQep1Regs
EQep2Regs
ECap1Regs
ECap2Regs
ECap3Regs
ECap4Regs
ECap5Regs
ECap6Regs
Hrcap6Regs
ECap7Regs
Hrcap7Regs
Pga1Regs
EPWM_REGS
EPWM_REGS
EPWM_REGS
EPWM_REGS
EPWM_REGS
EPWM_REGS
EPWM_REGS
EPWM_REGS
EQEP_REGS
EQEP_REGS
ECAP_REGS
ECAP_REGS
ECAP_REGS
ECAP_REGS
ECAP_REGS
ECAP_REGS
HRCAP_REGS
ECAP_REGS
HRCAP_REGS
PGA_REGS
0x0000 40FF
0x0000 41FF
0x0000 42FF
0x0000 43FF
0x0000 44FF
0x0000 45FF
0x0000 46FF
0x0000 47FF
0x0000 513F
0x0000 517F
0x0000 521F
0x0000 525F
0x0000 529F
0x0000 52DF
0x0000 531F
0x0000 535F
0x0000 537F
0x0000 539F
0x0000 53BF
0x0000 5B0F
0x0000 5B1F
0x0000 5B2F
0x0000 5B3F
0x0000 5B4F
0x0000 5B5F
0x0000 5B6F
0x0000 5C0F
0x0000 5C1F
0x0000 5C9F
0x0000 5CBF
0x0000 5CDF
0x0000 5CFF
0x0000 5D1F
0x0000 5D3F
0x0000 5D5F
0x0000 5E7F
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Pga2Regs
PGA_REGS
Pga3Regs
PGA_REGS
Pga4Regs
PGA_REGS
Pga5Regs
PGA_REGS
Pga6Regs
PGA_REGS
Pga7Regs
PGA_REGS
DacaRegs
DAC_REGS
DacbRegs
DAC_REGS
Cmpss1Regs
Cmpss2Regs
Cmpss3Regs
Cmpss4Regs
Cmpss5Regs
Cmpss6Regs
Cmpss7Regs
Sdfm1Regs
CMPSS_REGS
CMPSS_REGS
CMPSS_REGS
CMPSS_REGS
CMPSS_REGS
CMPSS_REGS
CMPSS_REGS
SDFM_REGS
Copyright © 2021 Texas Instruments Incorporated
186 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
Table 8-5. Peripheral Registers Memory Map (continued)
PIPELINE
CLA
ACCESS
DMA
ACCESS
REGISTER
STRUCTURE NAME
START ADDRESS
END ADDRESS
PROTECTION(1)
Peripheral Frame 2
0x0000 6100
0x0000 6110
0x0000 6400
0x0000 6600
0x0000 6680
Peripheral Frame 3
0x0000 7400
0x0000 7480
0x0000 7500
Peripheral Frame 4
0x0000 7900
0x0000 7920
0x0000 7940
0x0000 7980
0x0000 7A00
0x0000 7A80
0x0000 7C00
0x0000 7F00
Peripheral Frame 5
0x0005 D000
0x0005 D200
0x0005 D300
0x0005 D500
0x0005 D700
Peripheral Frame 6
0x0005 E800
0x0005 E900
0x0005 E908
0x0005 E910
0x0005 E918
0x0005 E920
0x0005 E928
0x0005 E930
0x0005 E938
0x0005 E980
0x0005 E990
0x0005 E9A0
0x0005 E9B0
0x0005 F000
0x0005 F040
0x0005 F100
0x0005 F140
0x0005 F070
0x0005 F080
0x0005 F400
0x0005 F4C0
0x0005 F500
0x0005 F800
0x0005 FB00
Peripheral Frame 7
0x0004 8000
0x0004 A000
0x0005 E608
SpiaRegs(4)
SpibRegs(4)
PmbusaRegs
FsiTxaRegs
FsiRxaRegs
SPI_REGS
SPI_REGS
0x0000 610F
0x0000 611F
0x0000 641F
0x0000 667F
0x0000 66FF
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
PMBUS_REGS
FSI_TX_REGS
FSI_RX_REGS
AdcaRegs
AdcbRegs
AdccRegs
ADC_REGS
ADC_REGS
ADC_REGS
0x0000 747F
0x0000 74FF
0x0000 757F
Yes
Yes
Yes
Yes
Yes
Yes
InputXbarRegs
XbarRegs
INPUT_XBAR_REGS
XBAR_REGS
0x0000 791F
0x0000 793F
0x0000 794F
0x0000 79BF
0x0000 7A3F
0x0000 7ABF
0x0000 7EFF
0x0000 7FFF
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
SyncSocRegs
SYNC_SOC_REGS
DmaClaSrcSelRegs
EPwmXbarRegs
OutputXbarRegs
GpioCtrlRegs
DMA_CLA_SRC_SEL_REGS
EPWM_XBAR_REGS
OUTPUT_XBAR_REGS
GPIO_CTRL_REGS
GPIO_DATA_REGS
GpioDataRegs(3)
Yes
DevCfgRegs
ClkCfgRegs
DEV_CFG_REGS
CLK_CFG_REGS
0x0005 D17F
0x0005 D2FF
0x0005 D3FF
0x0005 D6FF
0x0005 D7FF
Yes
Yes
Yes
Yes
Yes
CpuSysRegs
CPU_SYS_REGS
PeriphAcRegs
AnalogSubsysRegs
PERIPH_AC_REGS
ANALOG_SUBSYS_REGS
EnhancedDebugGlobalRegs
EnhancedDebugHWBP1Regs
EnhancedDebugHWBP2Regs
EnhancedDebugHWBP3Regs
EnhancedDebugHWBP4Regs
EnhancedDebugHWBP5Regs
EnhancedDebugHWBP6Regs
EnhancedDebugHWBP7Regs
EnhancedDebugHWBP8Regs
EnhancedDebugCounter1Regs
EnhancedDebugCounter2Regs
EnhancedDebugCounter3Regs
EnhancedDebugCounter4Regs
DcsmBank0Z1Regs
ERAD_GLOBAL_REGS
ERAD_HWBP_REGS
0x0005 E80A
0x0005 E907
0x0005 E90F
0x0005 E917
0x0005 E91F
0x0005 E927
0x0005 E92F
0x0005 E937
0x0005 E93F
0x0005 E98F
0x0005 E99F
0x0005 E9AF
0x0005 E9BF
0x0005 F022
0x0005 F062
0x0005 F122
0x0005 F162
0x0005 F07F
0x0005 F087
0x0005 F47F
0x0005 F4FF
0x0005 F53F
0x0005 FAFF
0x0005 FB3F
ERAD_HWBP_REGS
ERAD_HWBP_REGS
ERAD_HWBP_REGS
ERAD_HWBP_REGS
ERAD_HWBP_REGS
ERAD_HWBP_REGS
ERAD_HWBP_REGS
ERAD_COUNTER_REGS
ERAD_COUNTER_REGS
ERAD_COUNTER_REGS
ERAD_COUNTER_REGS
DCSM_BANK0_Z1_REGS
DCSM_BANK0_Z2_REGS
DCSM_BANK1_Z1_REGS
DCSM_BANK1_Z2_REGS
DCSM_COMMON_REGS
DCSM_COMMON_REGS
MEM_CFG_REGS
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
DcsmBank0Z2Regs
DcsmBank1Z1Regs
DcsmBank1Z2Regs
DcsmCommonRegs
DcsmCommon2Regs
MemCfgRegs
AccessProtectionRegs
ACCESS_PROTECTION_REGS
MEMORY_ERROR_REGS
FLASH_CTRL_REGS
MemoryErrorRegs
Flash0CtrlRegs
Flash0EccRegs
FLASH_ECC_REGS
CanaRegs
CanbRegs
CAN_REGS
CAN_REGS
0x0004 87FF
0x0004 A7FF
0x0005 E609
Yes
Yes
Yes
Yes
Yes
RomPrefetchRegs
ROM_PREFETCH_REGS
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 187
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
Table 8-5. Peripheral Registers Memory Map (continued)
PIPELINE
CLA
ACCESS
DMA
ACCESS
REGISTER
STRUCTURE NAME
START ADDRESS
END ADDRESS
PROTECTION(1)
DccRegs
DCC_REGS
0x0005 E700
Peripheral Frame 8
0x0000 6A00
0x0005 E73F
Yes
Yes
LinaRegs
LIN_REGS
0x0000 6AFF
Yes
Yes
Peripheral Frame 9
0x0000 7000
WdRegs(4)
NmiIntruptRegs(4)
XintRegs(4)
WD_REGS
NMI_INTRUPT_REGS
XINT_REGS
0x0000 703F
0x0000 706F
0x0000 707F
0x0000 720F
0x0000 721F
0x0000 733F
Yes
Yes
Yes
Yes
Yes
Yes
0x0000 7060
0x0000 7070
SciaRegs(4)
SCI_REGS
0x0000 7200
ScibRegs(4)
SCI_REGS
0x0000 7210
I2caRegs(4)
I2C_REGS
0x0000 7300
(1) The CPU (not applicable for CLA or DMA) contains a write-followed-by-read protection mode to ensure that any read operation that
follows a write operation within a protected address range is executed as written by delaying the read operation until the write is
initiated.
(2) ADC result register has no arbitration. Each master can access any ADC result register without any arbitration.
(3) Both CPU and CLA have their own copy of GPIO_DATA_REGS, and hence, no arbitration is required between CPU and CLA. For
more details, see the General-Purpose Input/Output (GPIO) chapter of the TMS320F28004x Microcontrollers Technical Reference
Manual.
(4) Registers with 16-bit access only.
Copyright © 2021 Texas Instruments Incorporated
188 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
8.3.5 Memory Types
8.3.5.1 Dedicated RAM (Mx RAM)
The CPU subsystem has two dedicated ECC-capable RAM blocks: M0 and M1. These memories are small
nonsecure blocks that are tightly coupled with the CPU (that is, only the CPU has access to them).
8.3.5.2 Local Shared RAM (LSx RAM)
RAM blocks which are dedicated to each subsystem and are accessible only to its CPU and CLA, are called
local shared RAMs (LSx RAMs).
All LSx RAM blocks have parity. These memories are secure and have the access protection (CPU write/CPU
fetch) feature.
By default, these memories are dedicated only to the CPU, and the user could choose to share these memories
with the CLA by configuring the MSEL_LSx bit field in the LSxMSEL registers appropriately (see Table 8-6).
Table 8-6. Master Access for LSx RAM
(With Assumption That all Other Access Protections are Disabled)
CLA1 ALLOWED
MSEL_LSx
CLAPGM_LSx
CPU ALLOWED ACCESS
COMMENT
ACCESS
LSx memory is configured
as CPU dedicated RAM.
00
X
All
–
Data Read
Data Write
Emulation Data Read
Emulation Data Write
LSx memory is shared
between CPU and CLA1.
01
01
0
1
All
Fetch Only
Emulation Program Read
Emulation Program Write
Emulation Read
Emulation Write
LSx memory is CLA1
program memory.
8.3.5.3 Global Shared RAM (GSx RAM)
RAM blocks which are accessible from both the CPU and DMA are called global shared RAMs (GSx RAMs).
Both the CPU and DMA have full read and write access to these memories. Table 8-7 shows the features of the
GSx RAM.
Table 8-7. Global Shared RAM
CPU (FETCH)
CPU (READ)
Yes
CPU (WRITE)
CPU.DMA (READ)
CPU.DMA (WRITE)
Yes
Yes
Yes
Yes
All GSx RAM blocks have parity.
The GSx RAMs have access protection (CPU write/CPU fetch/DMA write).
8.3.5.4 CLA Message RAM (CLA MSGRAM)
These RAM blocks can be used to share data between the CPU and CLA. The CLA has read and write access
to the "CLA to CPU MSGRAM." The CPU has read and write access to the "CPU to CLA MSGRAM." The CPU
and CLA both have read access to both MSGRAMs.
This RAM has parity.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 189
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
8.4 Identification
Table 8-8 lists the Device Identification Registers. Additional information on device identification can be found in
the TMS320F28004x Microcontrollers Technical Reference Manual. See the register descriptions of PARTIDH
and PARTIDL for identification of production status (TMX or TMS); availability of InstaSPIN-FOC™; and other
device information.
Table 8-8. Device Identification Registers
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
Device part identification number
TMS320F280049
TMS320F280049C
TMS320F280048
TMS320F280048C
TMS320F280045
TMS320F280041
TMS320F280041C
TMS320F280040
TMS320F280040C
Silicon revision number
Revision 0
0x01FF 0500
0x01FF 0500
0x01FE 0500
0x01FE 0500
0x01FB 0500
0x01F7 0500
0x01F7 0500
0x01F6 0500
0x01F6 0500
PARTIDH
0x0005 D00A
2
0x0000 0000
0x0000 0001
0x0000 0002
REVID
0x0005 D00C
0x0007 03CC
2
2
Revision A
Revision B
Unique identification number. This number is different on each
individual device with the same PARTIDH. This unique number
can be used as a serial number in the application. This number
is present only on TMS Revision B devices.
UID_UNIQUE
Copyright © 2021 Texas Instruments Incorporated
190 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
8.5 Bus Architecture – Peripheral Connectivity
Table 8-9 lists a broad view of the peripheral and configuration register accessibility from each bus master.
Table 8-9. Bus Master Peripheral Access
PERIPHERALS
DMA
CLA
CPU
SYSTEM PERIPHERALS
CPU Timers
Y
Y
Y
Y
Y
Y
Y
Y
Y
System Configuration (WD, NMIWD, LPM, Peripheral Clock Gating)
Device Capability, Peripheral Reset
Clock and PLL Configuration
Flash Configuration
Reset Configuration
GPIO Pin Mapping and Configuration
GPIO Data(2)
Y
DMA and CLA Trigger Source Select
CONTROL PERIPHERALS
ePWM/HRPWM
eCAP/HRCAP
eQEP(1)
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
SDFM
ANALOG PERIPHERALS
Analog System Control
ADC Configuration
ADC Result(3)
CMPSS(1)
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
DAC(1)
PGA(1)
COMMUNICATION PERIPHERALS
CAN
SPI
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
I2C
PMBus
SCI
Y
LIN
Y
Y
Y
Y
FSI
(1) These modules are accessible from DMA but cannot trigger a DMA transfer.
(2) The GPIO Data Registers are unique for the CPU and CLA. When the GPIO Pin Mapping Register is configured to assign a GPIO to a
particular master, the respective GPIO Data Register will control the GPIO. See the General-Purpose Input/Output (GPIO) chapter of
the TMS320F28004x Microcontrollers Technical Reference Manual for more details.
(3) ADC result registers are duplicated for each master. This allows them to be read with 0-wait states with no arbitration from any or all
masters.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 191
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
8.6 C28x Processor
The CPU is a 32-bit fixed-point processor which draws from the best features of digital signal processing;
reduced instruction set computing (RISC); and microcontroller architectures, firmware, and tool sets.
The features include:
•
CPU – modified Harvard architecture and circular addressing. The modified Harvard architecture of the CPU
enables instruction and data fetches to be performed in parallel. The CPU can read instructions and data
while it writes data simultaneously to maintain the single-cycle instruction operation across the pipeline. The
CPU does this over six separate address and data buses.
•
•
RISC – single-cycle instruction execution, register-to-register operations, and modified Harvard architecture.
Microcontroller – ease of use through an intuitive instruction set, byte packing and unpacking, and bit
manipulation.
For more information on CPU architecture and instruction set, see the TMS320C28x CPU and Instruction Set
Reference Guide. For more information on the C28x Floating-Point Unit (FPU), see the TMS320C28x Extended
Instruction Sets Technical Reference Manual. All of the features of the C28x documented in the TMS320C28x
CPU and Instruction Set Reference Guide apply to the C28x+VCU. All features documented in the TMS320C28x
Extended Instruction Sets Technical Reference Manual apply to the C28x+FPU+VCU. A brief overview of the
FPU, TMU, and VCU-Type 0 is provided here.
An overview of the VCU-I instructions can be found in the TMS320C28x Extended Instruction Sets Technical
Reference Manual.
8.6.1 Embedded Real-Time Analysis and Diagnostic (ERAD)
The ERAD module enhances the debug and system-analysis capabilities of the device. The debug and system-
analysis enhancements provided by the ERAD module is done outside of the CPU. The ERAD module consists
of the Enhanced Bus Comparator units and the Benchmark System Event Counter units. The Enhanced Bus
Comparator units are used to generate hardware breakpoints, hardware watch points, and other output events.
The Benchmark System Event Counter units are used to analyze and profile the system. The ERAD module is
accessible by the debugger and by the application software, which significantly increases the debug capabilities
of many real-time systems, especially in situations where debuggers are not connected. In the TMS320F28004x
devices, the ERAD module contains eight Enhanced Bus Comparator units and four Benchmark System Event
Counter units.
8.6.2 Floating-Point Unit (FPU)
The C28x plus floating-point (C28x+FPU) processor extends the capabilities of the C28x fixed-point CPU by
adding registers and instructions to support IEEE single-precision floating-point operations.
Devices with the C28x+FPU include the standard C28x register set plus an additional set of floating-point unit
registers. The additional floating-point unit registers are the following:
•
•
•
Eight floating-point result registers, RnH (where n = 0–7)
Floating-point Status Register (STF)
Repeat Block Register (RB)
All of the floating-point registers, except the RB, are shadowed. This shadowing can be used in high-priority
interrupts for fast context save and restore of the floating-point registers.
Copyright © 2021 Texas Instruments Incorporated
192 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
8.6.3 Trigonometric Math Unit (TMU)
The TMU extends the capabilities of a C28x+FPU by adding instructions and leveraging existing FPU
instructions to speed up the execution of common trigonometric and arithmetic operations listed in Table 8-10.
Table 8-10. TMU Supported Instructions
INSTRUCTIONS
MPY2PIF32 RaH,RbH
C EQUIVALENT OPERATION
PIPELINE CYCLES
a = b * 2pi
a = b / 2pi
a = b/c
2/3
2/3
5
DIV2PIF32 RaH,RbH
DIVF32 RaH,RbH,RcH
SQRTF32 RaH,RbH
a = sqrt(b)
5
SINPUF32 RaH,RbH
COSPUF32 RaH,RbH
ATANPUF32 RaH,RbH
QUADF32 RaH,RbH,RcH,RdH
a = sin(b*2pi)
4
a = cos(b*2pi)
4
a = atan(b)/2pi
4
Operation to assist in calculating ATANPU2
5
No changes have been made to existing instructions, pipeline or memory bus architecture. All TMU instructions
use the existing FPU register set (R0H to R7H) to carry out their operations.
8.6.4 Viterbi, Complex Math and CRC Unit (VCU-I)
The C28x with VCU (C28x+VCU) processor extends the capabilities of the C28x fixed-point or floating-point
CPU by adding registers and instructions to support the following algorithm types:
•
Viterbi decoding
Viterbi decoding is commonly used in baseband communications applications. The viterbi decode algorithm
consists of three main parts: branch metric calculations, compare-select (viterbi butterfly), and a traceback
operation. Table 8-11 lists a summary of the VCU-I performance for each of these operations.
Table 8-11. Viterbi Decode Performance
VITERBI OPERATION
VCU CYCLES
Branch Metric Calculation (code rate = 1/2)
Branch Metric Calculation (code rate = 1/3)
Viterbi Butterfly (add-compare-select)
Traceback per Stage
1
2p
2 (1)
3 (2)
(1) C28x CPU takes 15 cycles per butterfly.
(2) C28x CPU takes 22 cycles per stage.
•
•
Cyclic redundancy check (CRC)
CRC algorithms provide a straightforward method for verifying data integrity over large data blocks,
communication packets, or code sections. The C28x+VCU can perform 8-, 16-, and 32-bit CRCs. For
example, the VCU can compute the CRC for a block length of 10 bytes in 10 cycles. A CRC result register
contains the current CRC which is updated whenever a CRC instruction is executed.
Complex math
– Complex math is used in many applications; a few of which are:
– Fast fourier transform (FFT)
The complex FFT is used in spread spectrum communications, as well as many signal processing
algorithms.
– Complex filters
Complex filters improve data reliability, transmission distance, and power efficiency. The C28x+VCU can
perform a complex I and Q multiply with coefficients (four multiplies) in a single cycle. In addition, the C28x
+VCU can read/write the real and imaginary parts of 16-bit complex data to memory in a single cycle.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 193
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
Table 8-12 lists a summary of a few complex math operations enabled by the VCU.
Table 8-12. Complex Math Performance
COMPLEX MATH OPERATION
Add or Subtract
VCU CYCLES
NOTES
32 ± 32 = 32-bit (Useful for filters)
16 ± 32 = 15-bit (Useful for FFT)
16 × 16 = 32-bit
1
1
Add or Subtract
Multiply
2p
Multiply and Accumulate (MAC)
RPT MAC
2p
32 + 32 = 32-bit, 16 × 16 = 32-bit
2p+N
Repeat MAC. Single cycle after the first operation.
Copyright © 2021 Texas Instruments Incorporated
194 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
8.7 Control Law Accelerator (CLA)
The CLA Type-2 is an independent, fully programmable, 32-bit floating-point math processor that brings
concurrent control-loop execution to the C28x family. The low interrupt-latency of the CLA allows it to read ADC
samples "just-in-time." This significantly reduces the ADC sample to output delay to enable faster system
response and higher MHz control loops. By using the CLA to service time-critical control loops, the main CPU is
free to perform other system tasks such as communications and diagnostics.
The control law accelerator extends the capabilities of the C28x CPU by adding parallel processing. Time-critical
control loops serviced by the CLA can achieve low ADC sample to output delay. Thus, the CLA enables faster
system response and higher frequency control loops. Using the CLA for time-critical tasks frees up the main
CPU to perform other system and communication functions concurrently.
The following is a list of major features of the CLA:
•
•
Clocked at the same rate as the main CPU (SYSCLKOUT).
An independent architecture allowing CLA algorithm execution independent of the main C28x CPU.
– Complete bus architecture:
•
•
Program Address Bus (PAB) and Program Data Bus (PDB)
Data Read Address Bus (DRAB), Data Read Data Bus (DRDB), Data Write Address Bus (DWAB), and
Data Write Data Bus (DWDB)
– Independent 8-stage pipeline.
– 16-bit program counter (MPC)
– Four 32-bit result registers (MR0 to MR3)
– Two 16-bit auxiliary registers (MAR0, MAR1)
– Status register (MSTF)
•
Instruction set includes:
– IEEE single-precision (32-bit) floating-point math operations
– Floating-point math with parallel load or store
– Floating-point multiply with parallel add or subtract
– 1/X and 1/sqrt(X) estimations
– Data type conversions
– Conditional branch and call
– Data load/store operations
•
The CLA program code can consist of up to eight tasks or interrupt service routines, or seven tasks and a
main background task.
– The start address of each task is specified by the MVECT registers.
– No limit on task size as long as the tasks fit within the configurable CLA program memory space.
– One task is serviced at a time until its completion. There is no nesting of tasks.
– Upon task completion a task-specific interrupt is flagged within the PIE.
– When a task finishes the next highest-priority pending task is automatically started.
– The Type-2 CLA can have a main task that runs continuously in the background, while other high-priority
events trigger a foreground task.
•
•
Task trigger mechanisms:
– C28x CPU through the IACK instruction
– Task1 to Task8: up to 256 possible trigger sources from peripherals connected to the shared bus on which
the CLA assumes secondary ownership.
– Task8 can be set to be the background task, while Tasks 1 to 7 take peripheral triggers.
Memory and Shared Peripherals:
– Two dedicated message RAMs for communication between the CLA and the main CPU.
– The C28x CPU can map CLA program and data memory to the main CPU space or CLA space.
Figure 8-2 shows the CLA block diagram.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 195
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
CLA Control
Register Set
MIFR(16)
MPERINT1
to
MPERINT8
CLA_INT1
to
CLA_INT8
MIOVF(16)
MICLR(16)
From Shared
Peripherals
MICLROVF(16)
MIFRC(16)
C28x
CPU
PIE
INT11
INT12
MIER(16)
MIRUN(16)
LVF
LUF
MCTLBGRND(16)
MSTSBGRND(16)
CLA1SOFTINTEN(16)
CLA1INTFRC(16)
SYSCLK
CLA Clock Enable
SYSRS
MVECT1(16)
MVECT2(16)
MVECT3(16)
MVECT4(16)
MVECT5(16)
MVECT6(16)
MVECT7(16)
MVECT8(16)
CPU Read/Write Data Bus
CLA Program
Memory (LSx)
CLA Program Bus
LSxMSEL[MSEL_LSx]
LSxCLAPGM[CLAPGM_LSx]
MVECTBGRND(16)
MVECTBGRNDACTIVE(16)
MPSACTL(16)
MPSA1(32)
CLA Data
Memory (LSx)
MPSA2(32)
MCTL(16)
CLA Message
RAMs
CLA Execution
Register Set
MPC(16)
MSTF(32)
MR0(32)
MR1(32)
MR2(32)
MR3(32)
Shared
Peripherals
MEALLOW
MAR0(16)
MAR1(16)
CPU Read Data Bus
Figure 8-2. CLA Block Diagram
Copyright © 2021 Texas Instruments Incorporated
196 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
8.8 Direct Memory Access (DMA)
The DMA module provides a hardware method of transferring data between peripherals and/or memory without
intervention from the CPU, thereby freeing up bandwidth for other system functions. Additionally, the DMA has
the capability to orthogonally rearrange the data as it is transferred as well as “ping-pong” data between buffers.
These features are useful for structuring data into blocks for optimal CPU processing.
DMA features include:
•
•
Six channels with independent PIE interrupts
Peripheral interrupt trigger sources
– ADC interrupts and EVT signals
– External Interrupts
– ePWM SOC signals
– CPU timers
– eCAP
– Sigma-Delta Filter Module
– SPI transmit and receive
– CAN transmit and receive
– LIN transmit and receive
•
Data sources and destinations:
– GSx RAM
– ADC result registers
– Control peripheral registers (ePWM, eQEP, eCAP, SDFM)
– DAC and PGA registers
– SPI, LIN, CAN, and PMBus registers
Word Size: 16-bit or 32-bit (SPI limited to 16-bit)
Throughput: Four cycles per word without arbitration
•
•
Figure 8-3 shows a device-level block diagram of the DMA.
Global Shared
(GSx) RAMs
ADC
WRAPPER
ADC
RESULTS
XINT
TIMER
CAN
LIN
C28x Bus
DMA Bus
TINT (0-2)
XINT (1-5)
DMA Trigger
Source Selection
ADCx.INT(1-4), ADCx.EVT
LINATXDMA, LINARXDMA
CANxIF(1-3)
DMACHSRCSEL1.CHx
DMACHSRCSEL2.CHx
CHx.MODE.PERINTSEL
(x = 1 to 6)
DMA
C28x
ECAP(1-7)DMA
SD1DRINT (1-4)
EPWM(1-8).SOCA, EPWM(1-8).SOCB
SPITXDMA(A-B), SPIRXDMA(A-B)
PIE
FSITXADMA, FSIRXADMA
DMA Trigger Source
CPU and DMA Data Path
FSI
eCAP
SDFM
EPWM
SPI
PMBUS
Figure 8-3. DMA Block Diagram
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 197
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
8.9 Boot ROM and Peripheral Booting
The device boot ROM contains bootloading software. The device ROM has an internal bootloader (programmed
by TI) that is executed when the device is powered ON, and each time the device is reset. The bootloader is
used as an initial program to load the application on to device RAM through any of the bootable peripherals, or it
is configured to start the application in flash, if any.
Table 8-13 lists the default boot mode options. Users have the option to customize the boot modes supported as
well as the boot mode select pins.
Table 8-13. Device Default Boot Modes
GPIO24
GPIO32
BOOT MODE
(DEFAULT BOOT MODE SELECT PIN 1)
(DEFAULT BOOT MODE SELECT PIN 0)
Parallel IO
SCI/Wait boot
CAN
0
0
1
1
0
1
0
1
Flash
Table 8-14 lists the possible boot modes supported on the device. The default boot mode pins are GPIO24 (boot
mode pin 1) and GPIO32 (boot mode pin 0). Users may choose to have weak pullups for boot mode pins if they
use a peripheral on these pins as well, so the pullups can be overdriven. On this device, customers can change
the factory default boot mode pins by programming user-configurable Dual Code Security Module (DCSM) OTP
locations.
Table 8-14. All Available Boot Modes
BOOT MODE NUMBER
BOOT MODE
Parallel IO
SCI/Wait boot
CAN
0
1
2
3
4
5
6
7
8
Flash
Wait
RAM
SPI Master
I2C Master
PLC
Note
All the peripheral boot modes supported use the first instance of the peripheral module (SCIA, SPIA,
I2CA, CANA, and so forth). Whenever these boot modes are referred to in this section, such as SCI
boot, it is actually referring to the first module instance, meaning SCI boot on the SCIA port. The same
applies to the other peripheral boots.
Copyright © 2021 Texas Instruments Incorporated
198 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
8.9.1 Configuring Alternate Boot Mode Select Pins
This section explains how the boot mode select pins can be customized by the user, by programming the
BOOTPIN_CONFIG location in user-configurable DCSM OTP. The location in user DCSM OTP is Z1-OTP-
BOOTPIN-CONFIG. When debugging, EMU-BOOTPIN-CONFIG is the emulation equivalent of Z1-OTP-
BOOTPIN-CONFIG, and can be programmed to experiment with different boot modes without writing to OTP.
The device can be programmed to use 0, 1, 2, or 3 boot mode select pins as needed.
Table 8-15. BOOTPIN_CONFIG Bit Fields
BIT
NAME
DESCRIPTION
Write 0x5A to these 8 bits to tell the boot ROM code that the bits in this
register are valid
31–24
Key
23–16
15–8
Boot Mode Select Pin 2 (BMSP2)
Boot Mode Select Pin 1 (BMSP1)
See BMPS0 description
See BMSP0 description
Set to the GPIO pin to be used during boot (up to 255).
0x0 = GPIO0; 0x01 = GPIO1 and so on
0xFF is invalid and selects the factory default chosen BMSP0, if all
other BMSPs are also set to 0xFF.
7–0
Boot Mode Select Pin 0 (BMSP0)
If any other BMSPs are not set to 0xFF, then setting a BMSP to 0xFF
will disable that particular BMSP.
Note
The following GPIOs cannot be used as a BMSP. If selected for a particular BMSP, the boot ROM
automatically selects the factory default GPIO (the factory default for BMSP2 is 0xFF, which disables
the BMSP).
•
•
•
•
GPIO 20 to 23
GPIO 36
GPIO 38
GPIO 60 to 223
Table 8-16. Stand-alone Boot Mode Select Pin Decoding
BOOTPIN_CONFIG
KEY
BMSP0
Don’t Care
0xFF
BMSP1
Don’t Care
0xFF
BMSP2
Don’t Care
0xFF
REALIZED BOOT MODE
Boot as defined by the factory default BMSPs (GPIO24,
GPIO32)
!= 0x5A
Boot as defined in the boot table for boot mode 0
(All BMSPs disabled)
Boot as defined by the value of BMSP0
(BMSP1 and BMSP2 disabled)
Valid GPIO
0xFF
0xFF
0xFF
Boot as defined by the value of BMSP1
(BMSP0 and BMSP2 disabled)
Valid GPIO
0xFF
0xFF
Boot as defined by the value of BMSP2
(BMSP0 and BMSP1 disabled)
0xFF
Valid GPIO
0xFF
= 0x5A
Boot as defined by the values of BMSP0 and BMSP1
(BMSP2 disabled)
Valid GPIO
Valid GPIO
Valid GPIO
0xFF
Boot as defined by the values of BMSP0 and BMSP2
(BMSP1 disabled)
Valid GPIO
Boot as defined by the values of BMSP1 and BMSP2
(BMSP0 disabled)
0xFF
Valid GPIO
Valid GPIO
Valid GPIO
Valid GPIO
Valid GPIO
Boot as defined by the values of BMSP0, BMPS1, and BMSP2
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 199
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
8.9.2 Configuring Alternate Boot Mode Options
This section explains how to configure the boot definition table, BOOTDEF, for the device and the associated
boot options. The 64-bit location is in user-configurable DCSM OTP in the Z1-OTP-BOOTDEF-LOW and Z1-
OTP-BOOTDEF-HIGH locations. When debugging, EMU-BOOTDEF-LOW and EMU-BOOTDEF-HIGH are the
emulation equivalents of Z1-OTP-BOOTDEF-LOW and Z1-OTP-BOOTDEF-HIGH, and can be programmed to
experiment with different boot mode options without writing to OTP. The range of customization to the boot
definition table depends on how many boot mode select pins are being used. For examples on how to use the
BOOTPIN_CONFIG and BOOTDEF values, see the Boot Mode Example Use Cases section of the ROM Code
and Peripheral Booting chapter in the TMS320F28004x Microcontrollers Technical Reference Manual.
Table 8-17. BOOTDEF Bit Fields
BOOTDEF NAME
BYTE POSITION
NAME
DESCRIPTION
Set the boot mode and boot mode options. This can
include changing the GPIOs for a particular boot
peripheral or specifying a different flash entry point.
Any unsupported boot mode will cause the device to
reset.
BOOT_DEF0
7–0
BOOT_DEF0 Mode and Options
See GPIO Assignments for valid BOOTDEF values.
BOOT_DEF1
BOOT_DEF2
BOOT_DEF3
BOOT_DEF4
BOOT_DEF5
BOOT_DEF6
BOOT_DEF7
15–8
23–16
31–24
39–32
47–40
55–48
63–56
BOOT_DEF1 Mode and Options
BOOT_DEF2 Mode and Options
BOOT_DEF3 Mode and Options
BOOT_DEF4 Mode and Options
BOOT_DEF5 Mode and Options
BOOT_DEF6 Mode and Options
BOOT_DEF7 Mode and Options
Refer to BOOT_DEF0 descriptions.
8.9.3 GPIO Assignments
This section details the GPIOs and boot options used for each boot mode set in BOOT_DEFx located at Z1-
OTP-BOOTDEF-LOW and Z1-OTP-BOOTDEF-HIGH. See Configuring Alternate Boot Mode Select Pins on how
to manipulate BOOT_DEFx. When selecting a boot mode option, verify that the necessary pins are available in
the pin mux options for the specific device package being used.
Table 8-18. SCI Boot Options
OPTION
BOOTDEFx VALUE
SCIATX GPIO
SCIARX GPIO
GPIO28
0 (default)
0x01
0x21
0x41
0x61
0x81
GPIO29
1
2
3
4
GPIO16
GPIO17
GPIO8
GPIO9
GPIO48
GPIO49
GPIO24
GPIO25
Note
Pullups are enabled on the SCIATX and SCIARX pins.
Copyright © 2021 Texas Instruments Incorporated
200 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
Table 8-19. CAN Boot Options
OPTION
BOOTDEFx VALUE
CANTXA GPIO
CANRXA GPIO
GPIO33
0 (default)
0x02
0x22
0x42
0x62
GPIO32
1
2
3
GPIO4
GPIO5
GPIO31
GPIO30
GPIO37
GPIO35
Note
Pullups are enabled on the CANTXA and SCIARX pins.
Table 8-20. Flash Boot Options
FLASH ENTRY POINT
(ADDRESS)
OPTION
BOOTDEFx VALUE
FLASH BANK, SECTOR
Bank 0, Sector 0
Flash – Default Option 1
(0x00080000)
0 (default)
0x03
0x23
0x43
0x63
Flash – Option 2
(0x0008EFF0)
1
2
3
Bank 0, Sector 14
Bank 1, Sector 0
Flash – Option 3
(0x00090000)
Flash – Option 4
(0x0009EFF0)
Bank 1, Sector 14
Table 8-21. Wait Boot Options
OPTION
BOOTDEFx VALUE
WATCHDOG STATUS
Enabled
0
1
0x04
0x24
Disabled
Table 8-22. SPI Boot Options
OPTION
BOOTDEFx VALUE
SPIA_SIMO
SPIA_SOMI
SPIA_CLK
SPIA_STE
GPIO11
GPIO57
GPIO57
GPIO11
1
2
3
4
0x26
0x46
0x66
0x86
GPIO8
GPIO10
GPIO9
GPIO56
GPIO56
GPIO9
GPIO54
GPIO16
GPIO8
GPIO55
GPIO17
GPIO17
Note
Pullups are enabled on the SPIA_SIMO, SPIA_SOMI, SPIA_CLK, and SPIA_STE pins.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 201
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
Table 8-23. I2C Boot Options
OPTION
BOOTDEFx VALUE
SDAA GPIO
SCLA GPIO
GPIO33
0
1
2
0x07
0x47
0x67
GPIO32
GPIO26
GPIO27
GPIO42
GPIO43
Note
Pullups are enabled on the SDAA and SCLA pins.
Table 8-24. Parallel Boot Options
OPTION
BOOTDEFx VALUE
D0 to D7 GPIO
DSP CONTROL GPIO
HOST CONTROL GPIO
0 (default)
0x00
GPIO0 to GPIO7
GPIO16
GPIO11
Note
Pullups are enabled on GPIO0 to GPIO7.
Table 8-25. RAM Boot Options
RAM ENTRY POINT
OPTION
BOOTDEFx VALUE
ADDRESS
0
0x05
0x00000000
Copyright © 2021 Texas Instruments Incorporated
202 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
8.10 Dual Code Security Module
The dual code security module (DCSM) prevents access to on-chip secure memories. The term “secure” means
access to secure memories and resources is blocked. The term “unsecure” means access is allowed; for
example, through a debugging tool such as Code Composer Studio™ (CSS).
The code security mechanism offers protection for two zones, Zone 1 (Z1) and Zone 2 (Z2). The security
implementation for both the zones is identical. Each zone has its own dedicated secure resource (OTP memory
and secure ROM) and allocated secure resource (CLA, LSx RAM, and flash sectors).
The security of each zone is ensured by its own 128-bit password (CSM password). The password for each zone
is stored in an OTP memory location based on a zone-specific link pointer. The link pointer value can be
changed to program a different set of security settings (including passwords) in OTP.
Note
THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED TO
PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY AND IS
WARRANTED BY TEXAS INSTRUMENTS (TI), IN ACCORDANCE WITH ITS STANDARD TERMS
AND CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS FOR THE WARRANTY
PERIOD APPLICABLE FOR THIS DEVICE.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY
CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH
ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR
OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY
OR FITNESS FOR A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,
INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF
YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED
TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR
OTHER ECONOMIC LOSS.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 203
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
8.11 Watchdog
The watchdog module is the same as the one on previous TMS320C2000 devices, but with an optional lower
limit on the time between software resets of the counter. This windowed countdown is disabled by default, so the
watchdog is fully backward-compatible.
The watchdog generates either a reset or an interrupt. It is clocked from the internal oscillator with a selectable
frequency divider.
Figure 8-4 shows the various functional blocks within the watchdog module.
WDCR.WDPRECLKDIV
WDCR.WDPS
WDCR.WDDIS
WDCNTR
8-bit
Watchdog
Counter
WDCLK
(INTOSC1)
WDCLK
Divider
Watchdog
Prescaler
Overflow
1-count
delay
SYSRSn
Clear
Count
WDWCR.MIN
WDKEY (7:0)
Watchdog
Window
Detector
Out of Window
Good Key
Watchdog
Key Detector
55 + AA
WDCR(WDCHK(2:0))
Bad Key
WDRSTn
WDINTn
Generate
512-WDCLK
Output Pulse
1
0
1
Watchdog Time-out
SCSR.WDENINT
Figure 8-4. Windowed Watchdog
Copyright © 2021 Texas Instruments Incorporated
204 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
8.12 Configurable Logic Block (CLB)
The C2000 configurable logic block (CLB) is a collection of blocks that can be interconnected using software to
implement custom digital logic functions or enhance existing on-chip peripherals. The CLB is able to enhance
existing peripherals through a set of crossbar interconnections, which provide a high level of connectivity to
existing control peripherals such as enhanced pulse width modulators (ePWM), enhanced capture modules
(eCAP), and enhanced quadrature encoder pulse modules (eQEP). The crossbars also allow the CLB to be
connected to external GPIO pins. In this way, the CLB can be configured to interact with device peripherals to
perform small logical functions such as comparators, or to implement custom serial data exchange protocols.
Through the CLB, functions that would otherwise be accomplished using external logic devices can now be
implemented inside the MCU.
The CLB peripheral is configured through the CLB tool. For more information on the CLB tool, available
examples, application reports and users guide, please refer to the following location in your C2000Ware package
(C2000Ware_2_00_00_03 and higher):
C2000WARE_INSTALL_LOCATION\utilities\clb_tool\clb_syscfg\doc
CLB Tool User Guide
How to Design with the C2000™ CLB Application Report
How to Migrate Custom Logic From an FPGA/CPLD to C2000™ CLB Application Report
The CLB module and its interconnects are shown in Figure 8-5.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 205
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
Figure 8-5. CLB Overview
Absolute encoder protocol interfaces are now provided as Position Manager solutions in the C2000Ware
MotorControl SDK. Configuration files, application programmer interface (API), and use examples for such
solutions are provided with C2000Ware MotorControl SDK. In some solutions, the TI-configured CLB is used
with other on-chip resources, such as the SPI port or the C28x CPU, to perform more complex functionality. See
Table 5-1 for the devices that support the CLB feature.
Copyright © 2021 Texas Instruments Incorporated
206 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
9 Applications, Implementation, and Layout
Note
Information in the following Applications section is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI's customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 TI Reference Design
The TI Reference Design Library is a robust reference design library spanning analog, embedded processor,
and connectivity. Created by TI experts to help you jump start your system design, all reference designs include
schematic or block diagrams, BOMs, and design files to speed your time to market. Search and download
designs at Select TI reference designs.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 207
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
10 Device and Documentation Support
10.1 Device and Development Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320
MCU devices and support tools. Each TMS320™ MCU commercial family member has one of two prefixes: TMX
or TMS (for example, TMS320F280049). Texas Instruments recommends two of three possible prefix
designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product
development from engineering prototypes (with TMX for devices and TMDX for tools) through fully qualified
production devices and tools (with TMS for devices and TMDS for tools).
TMX
TMS
Experimental device that is not necessarily representative of the final device's electrical specifications
Fully qualified production device
Support tool development evolutionary flow:
TMDX
TMDS
Development-support product that has not yet completed Texas Instruments internal qualification testing
Fully qualified development-support product
TMX devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability
of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX) have a greater failure rate than the standard production devices.
Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, PZ) and temperature range (for example, S).
For device part numbers and further ordering information, see the TI website (www.ti.com) or contact your TI
sales representative.
For additional description of the device nomenclature markings on the die, see the TMS320F28004x MCUs
Silicon Errata.
Copyright © 2021 Texas Instruments Incorporated
208 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
A. Prefix X is used in orderable part numbers.
Figure 10-1. Device Nomenclature
10.2 Markings
Figure 10-2 and Figure 10-3 provide examples of the F28004x device markings and define each of the markings.
The device revision can be determined by the symbols marked on the top of the package as shown in Figure
10-2. Some prototype devices may have markings different from those illustrated.
980
F280049PZS
980
F280049PMS
$$#−YMLLLLS
G4
$$#−YMLLLLS
G4
Package
Pin 1
Package
Pin 1
YMLLLLS
Lot Trace Code
=
YM
LLLL
S
980
$$
2-Digit Year/Month Code
Assembly Lot
Assembly Site Code
TI E.I.A. Code
Wafer Fab Code (one or two characters) as applicable
Silicon Revision Code
=
=
=
=
=
=
#
G4
Green (Low Halogen and RoHS-compliant)
=
Figure 10-2. Examples of Device Markings for PM and PZ Packages
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 209
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
YMLLLLS
Lot Trace Code
=
F280049
YM
LLLL
S
2-Digit Year/Month Code
Assembly Lot
Assembly Site Code
Wafer Fab Code (one or two characters) as applicable
Silicon Revision Code
=
=
=
=
=
RSHS
$$#−YMLLLLS
$$
#
TI
G4
G4
Green (Low Halogen and RoHS-compliant)
=
Package
Pin 1
Figure 10-3. Example of Device Markings for RSH Package
Table 10-1. Determining Silicon Revision From Lot Trace Code
REVID(1)
Address: 0x5D00C
SILICON REVISION CODE
SILICON REVISION
COMMENTS
Blank
A
0
0x0000 0000
This silicon revision is available as TMX.
This silicon revision is available as TMX.
A
0x0000 0001
This silicon revision is available as TMX and
TMS.
B
B
0x0000 0002
(1) Silicon Revision ID
10.3 Tools and Software
TI offers an extensive line of development tools. Some of the tools and software to evaluate the performance of
the device, generate code, and develop solutions follow. To view all available tools and software for C2000 real-
time control MCUs, visit the C2000 real-time control MCUs – Design & development page.
Development Tools
F280049C controlCARD Evaluation Module
The F280049C controlCARD Evaluation Module is an HSEC180 controlCARD-based evaluation and
development tool for the C2000 F28004x series of microcontroller products. controlCARDs are ideal to use for
initial evaluation and system prototyping. controlCARDs are complete board-level modules that utilize one of two
standard form factors (100-pin DIMM or 180-pin HSEC) to provide a low-profile single-board controller solution.
For first evaluation, controlCARDs are typically purchased bundled with a baseboard or bundled in an
application kit.
Software Tools
C2000Ware for C2000 MCUs
C2000Ware for C2000™ microcontrollers is a cohesive set of development software and documentation
designed to minimize software development time. From device-specific drivers and libraries to device peripheral
examples, C2000Ware provides a solid foundation to begin development and evaluation of your product.
Code Composer Studio (CCS) Integrated Development Environment (IDE) for C2000 Microcontrollers
Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and
Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug
embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build environment,
debugger, profiler, and many other features. The intuitive IDE provides a single user interface taking the user
through each step of the application development flow. Familiar tools and interfaces allow users to get started
faster than ever before. Code Composer Studio combines the advantages of the Eclipse software framework
with advanced embedded debug capabilities from TI resulting in a compelling feature-rich development
environment for embedded developers.
Copyright © 2021 Texas Instruments Incorporated
210 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
Pin Mux Tool
The Pin Mux Utility is a software tool which provides a Graphical User Interface for configuring pin multiplexing
settings, resolving conflicts and specifying I/O cell characteristics for TI MPUs.
F021 Flash Application Programming Interface (API)
The F021 Flash Application Programming Interface (API) provides a software library of functions to program,
erase, and verify F021 on-chip Flash memory.
UniFlash Standalone Flash Tool
UniFlash is a standalone tool used to program on-chip flash memory through a GUI, command line, or scripting
interface.
Models
Various models are available for download from the product Tools & Software pages. These models include I/O
Buffer Information Specification (IBIS) Models and Boundary-Scan Description Language (BSDL) Models. To
view all available models, visit the Models section of the Tools & Software page for each device.
Training
To help assist design engineers in taking full advantage of the C2000 microcontroller features and performance,
TI has developed a variety of training resources. Utilizing the online training materials and downloadable hands-
on workshops provides an easy means for gaining a complete working knowledge of the C2000 microcontroller
family. These training resources have been designed to decrease the learning curve, while reducing
development time, and accelerating product time to market. For more information on the various training
resources, visit the C2000™ real-time control MCUs – Support & training site.
Specific TMS320F28004x hands-on training resources can be found at C2000™ MCU Device Workshops.
Technical Introduction to the New C2000 TMS320F28004x Device Family
Discover the newest member to the C2000 MCU family. This presentation will cover the technical details of the
TMS320F28004x architecture and highlight the new improvements to various key peripherals, such as an
enhanced Type 2 CLA capable of running a background task, and the inclusion of a set of high-speed
programmable gain amplifiers. Also, a completely new boot mode flow enables expanded booting options.
Where applicable, a comparison to the TMS320F2807x MCU device series will be used, and some knowledge
about the previous device architectures will be helpful in understanding the topics presented in this presentation.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
211
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
10.4 Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
The current documentation that describes the processor, related peripherals, and other technical collateral
follows.
Errata
TMS320F28004x MCUs Silicon Errata describes known advisories on silicon and provides workarounds.
Technical Reference Manual
TMS320F28004x Microcontrollers Technical Reference Manual details the integration, the environment, the
functional description, and the programming models for each peripheral and subsystem in the F28004x
microcontrollers.
InstaSPIN Technical Reference Manuals
InstaSPIN-FOC™ and InstaSPIN-MOTION™ User's Guide describes the InstaSPIN-FOC and InstaSPIN-
MOTION™ devices.
CPU User's Guides
TMS320C28x CPU and Instruction Set Reference Guide describes the central processing unit (CPU) and the
assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). This Reference
Guide also describes emulation features available on these DSPs.
TMS320C28x Extended Instruction Sets Technical Reference Manual describes the architecture, pipeline, and
instruction set of the TMU, VCU-II, and FPU accelerators.
Peripheral Guides
C2000 Real-Time Control Peripherals Reference Guide describes the peripheral reference guides of the 28x
DSPs.
Tools Guides
TMS320C28x Assembly Language Tools v20.2.0.LTS User's Guide describes the assembly language tools
(assembler and other tools used to develop assembly language code), assembler directives, macros, common
object file format, and symbolic debugging directives for the TMS320C28x device.
TMS320C28x Optimizing C/C++ Compiler v20.2.0.LTS User's Guide describes the TMS320C28x C/C++
compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly
language source code for the TMS320C28x device.
Application Reports
The SMT & packaging application notes website lists documentation on TI’s surface mount technology (SMT)
and application notes on a variety of packaging-related topics.
Semiconductor Packing Methodology describes the packing methodologies employed to prepare semiconductor
devices for shipment to end users.
Calculating Useful Lifetimes of Embedded Processors provides a methodology for calculating the useful lifetime
of TI embedded processors (EPs) under power when used in electronic systems. It is aimed at general
engineers who wish to determine if the reliability of the TI EP meets the end system reliability requirement.
An Introduction to IBIS (I/O Buffer Information Specification) Modeling discusses various aspects of IBIS
including its history, advantages, compatibility, model generation flow, data requirements in modeling the input/
output structures, and future trends.
Serial Flash Programming of C2000™ Microcontrollers discusses using a flash kernel and ROM loaders for
serial programming a device.
Copyright © 2021 Texas Instruments Incorporated
212 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
www.ti.com
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
10.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.6 Trademarks
InstaSPIN-FOC™, FAST™, TMS320C2000™, C2000™, Code Composer Studio™, InstaSPIN-MOTION™, and TI
E2E™ are trademarks of Texas Instruments.
TMS320™ is a trademark of Texas Instruments.
Bosch® is a registered trademark of Robert Bosch GmbH Corporation.
All trademarks are the property of their respective owners.
10.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.8 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 213
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021
www.ti.com
11 Mechanical, Packaging, and Orderable Information
11.1 Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
For packages with a thermal pad, the MECHANICAL DATA figure shows a generic thermal pad without
dimensions. For the actual thermal pad dimensions that are applicable to this device, see the THERMAL PAD
MECHANICAL DATA figure.
To learn more about TI packaging, visit the Packaging information website.
Copyright © 2021 Texas Instruments Incorporated
214 Submit Document Feedback
Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C
TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C
PACKAGE OPTION ADDENDUM
www.ti.com
14-Feb-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
F280040CPMQR
F280040PMQR
F280041CPMS
F280041CPZQR
F280041CPZS
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LQFP
LQFP
LQFP
LQFP
LQFP
VQFN
PM
PM
PM
PZ
64
64
1000 RoHS & Green
1000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
F280040CPMQ
NIPDAU
NIPDAU
F280040PMQ
F280041CPMS
F280041CPZQ
F280041CPZS
64
160
1000 RoHS & Green
90 RoHS & Green
2500 RoHS & Green
160 RoHS & Green
RoHS & Green
100
100
56
NIPDAU
PZ
NIPDAU
F280041CRSHSR
RSH
Call TI | NIPDAU
F280041C
RSHS
F280041PMS
F280041PMSR
F280041PZQR
F280041PZS
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LQFP
LQFP
LQFP
LQFP
LQFP
VQFN
PM
PM
PZ
64
64
NIPDAU
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
F280041PMS
F280041PMS
F280041PZQ
F280041PZS
F280041PZS
1000 RoHS & Green
1000 RoHS & Green
100
100
100
56
NIPDAU
PZ
90
RoHS & Green
NIPDAU
F280041PZSR
F280041RSHSR
PZ
1000 RoHS & Green
2500 RoHS & Green
NIPDAU
RSH
Call TI | NIPDAU
F280041
RSHS
F280045PMS
F280045PMSR
F280045PZS
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LQFP
LQFP
LQFP
LQFP
VQFN
PM
PM
PZ
64
64
160
1000 RoHS & Green
90 RoHS & Green
RoHS & Green
NIPDAU
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
F280045PMS
F280045PMS
F280045PZS
F280045PZS
100
100
56
NIPDAU
F280045PZSR
F280045RSHSR
PZ
1000 RoHS & Green
2500 RoHS & Green
NIPDAU
RSH
Call TI | NIPDAU
F280045
RSHS
F280048CPMQR
F280048PMQR
ACTIVE
ACTIVE
LQFP
LQFP
PM
PM
64
64
1000 RoHS & Green
1000 RoHS & Green
NIPDAU
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
F280048CPMQ
F280048PMQ
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Feb-2021
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
F280049CPMS
F280049CPMSR
F280049CPZQR
F280049CPZS
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LQFP
LQFP
LQFP
LQFP
VQFN
PM
PM
PZ
64
64
160
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
F280049CPMS
1000 RoHS & Green
1000 RoHS & Green
NIPDAU
NIPDAU
F280049CPMS
F280049CPZQ
F280049CPZS
100
100
56
PZ
90
2500 RoHS & Green
160 RoHS & Green
1000 RoHS & Green
90 RoHS & Green
1000 RoHS & Green
90 RoHS & Green
RoHS & Green
NIPDAU
F280049CRSHSR
RSH
Call TI | NIPDAU
F280049C
RSHS
F280049PMS
F280049PMSR
F280049PZQ
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
VQFN
PM
PM
PZ
64
64
NIPDAU
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
F280049PMS
F280049PMS
F280049PZQ
F280049PZQ
F280049PZS
F280049PZS
100
100
100
100
56
NIPDAU
F280049PZQR
F280049PZS
PZ
NIPDAU
PZ
NIPDAU
F280049PZSR
F280049RSHSR
PZ
1000 RoHS & Green
2500 RoHS & Green
NIPDAU
RSH
Call TI | NIPDAU
F280049
RSHS
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
14-Feb-2021
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TMS320F280041, TMS320F280041-Q1, TMS320F280041C, TMS320F280041C-Q1, TMS320F280049, TMS320F280049-Q1,
TMS320F280049C, TMS320F280049C-Q1 :
Catalog: TMS320F280041, TMS320F280041C, TMS320F280049, TMS320F280049C
•
Automotive: TMS320F280041-Q1, TMS320F280041C-Q1, TMS320F280049-Q1, TMS320F280049C-Q1
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Feb-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
F280040CPMQR
F280040PMQR
F280041CPZQR
F280041CRSHSR
F280041PMSR
F280041PZQR
F280041RSHSR
F280045PMSR
F280045PZSR
F280045RSHSR
F280048CPMQR
F280048PMQR
F280049CPMSR
F280049CPZQR
F280049CRSHSR
F280049PMSR
F280049PZQR
F280049PZSR
LQFP
LQFP
LQFP
VQFN
LQFP
LQFP
VQFN
LQFP
LQFP
VQFN
LQFP
LQFP
LQFP
LQFP
VQFN
LQFP
LQFP
LQFP
PM
PM
PZ
64
64
1000
1000
1000
2500
1000
1000
2500
1000
1000
2500
1000
1000
1000
1000
2500
1000
1000
1000
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
24.4
24.4
32.4
16.4
24.4
32.4
16.4
24.4
32.4
16.4
24.4
24.4
24.4
32.4
16.4
24.4
32.4
32.4
13.0
13.0
16.9
7.3
13.0
13.0
16.9
7.3
2.1
2.1
2.0
1.1
2.1
2.0
1.1
2.1
2.0
1.1
2.1
2.1
2.1
2.0
1.1
2.1
2.0
2.0
16.0
16.0
24.0
12.0
16.0
24.0
12.0
16.0
24.0
12.0
16.0
16.0
16.0
24.0
12.0
16.0
24.0
24.0
24.0
24.0
32.0
16.0
24.0
32.0
16.0
24.0
32.0
16.0
24.0
24.0
24.0
32.0
16.0
24.0
32.0
32.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
100
56
RSH
PM
PZ
64
13.0
16.9
7.3
13.0
16.9
7.3
100
56
RSH
PM
PZ
64
13.0
16.9
7.3
13.0
16.9
7.3
100
56
RSH
PM
PM
PM
PZ
64
13.0
13.0
13.0
16.9
7.3
13.0
13.0
13.0
16.9
7.3
64
64
100
56
RSH
PM
PZ
64
13.0
16.9
16.9
13.0
16.9
16.9
100
100
PZ
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Feb-2021
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
F280049RSHSR
VQFN
RSH
56
2500
330.0
16.4
7.3
7.3
1.1
12.0
16.0
Q2
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
F280040CPMQR
F280040PMQR
F280041CPZQR
F280041CRSHSR
F280041PMSR
F280041PZQR
F280041RSHSR
F280045PMSR
F280045PZSR
LQFP
LQFP
LQFP
VQFN
LQFP
LQFP
VQFN
LQFP
LQFP
VQFN
LQFP
LQFP
LQFP
LQFP
VQFN
LQFP
PM
PM
PZ
64
64
1000
1000
1000
2500
1000
1000
2500
1000
1000
2500
1000
1000
1000
1000
2500
1000
336.6
336.6
367.0
336.6
336.6
367.0
336.6
336.6
367.0
336.6
336.6
336.6
336.6
367.0
336.6
336.6
336.6
336.6
367.0
336.6
336.6
367.0
336.6
336.6
367.0
336.6
336.6
336.6
336.6
367.0
336.6
336.6
41.3
41.3
55.0
31.8
41.3
55.0
31.8
41.3
55.0
31.8
41.3
41.3
41.3
55.0
31.8
41.3
100
56
RSH
PM
PZ
64
100
56
RSH
PM
PZ
64
100
56
F280045RSHSR
F280048CPMQR
F280048PMQR
F280049CPMSR
F280049CPZQR
F280049CRSHSR
F280049PMSR
RSH
PM
PM
PM
PZ
64
64
64
100
56
RSH
PM
64
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Feb-2021
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
F280049PZQR
F280049PZSR
F280049RSHSR
LQFP
LQFP
VQFN
PZ
PZ
100
100
56
1000
1000
2500
367.0
367.0
336.6
367.0
367.0
336.6
55.0
55.0
31.8
RSH
Pack Materials-Page 3
PACKAGE OUTLINE
PM0064A
LQFP - 1.6 mm max height
SCALE 1.400
PLASTIC QUAD FLATPACK
10.2
9.8
B
NOTE 3
64
49
PIN 1 ID
1
48
10.2
9.8
12.2
TYP
11.8
NOTE 3
33
16
32
17
A
0.27
0.17
64X
60X 0.5
4X 7.5
0.08
C A B
C
(0.13) TYP
SEATING PLANE
0.08
SEE DETAIL A
0.25
GAGE PLANE
(1.4)
1.6 MAX
0.05 MIN
0.75
0.45
0 -7
DETAIL
SCALE: 14
A
DETAIL A
TYPICAL
4215162/A 03/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MS-026.
www.ti.com
EXAMPLE BOARD LAYOUT
PM0064A
LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK
SYMM
49
64
64X (1.5)
1
48
64X (0.3)
SYMM
(11.4)
60X (0.5)
(R0.05) TYP
33
16
17
32
(11.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
0.05 MAX
ALL AROUND
EXPOSED METAL
METAL
0.05 MIN
ALL AROUND
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4215162/A 03/2017
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. For more information, see Texas Instruments literature number SLMA004 (www.ti.com/lit/slma004).
www.ti.com
EXAMPLE STENCIL DESIGN
PM0064A
LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK
SYMM
64
49
64X (1.5)
1
48
64X (0.3)
SYMM
(11.4)
60X (0.5)
(R0.05) TYP
16
33
17
32
(11.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:8X
4215162/A 03/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996
PZ (S-PQFP-G100)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
75
M
0,08
51
50
76
26
100
0,13 NOM
1
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
0,25
16,20
SQ
0,05 MIN
0°–7°
15,80
1,45
1,35
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040149/B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OUTLINE
RSH0056D
VQFN - 1 mm max height
S
C
A
L
E
2
.
0
0
0
VQFN
7.15
6.85
A
B
PIN 1 INDEX AREA
7.15
6.85
C
1 MAX
SEATING PLANE
0.05
0.00
5.3 0.1
(0.2)
15
28
14
29
52X 0.4
4X
5.2
1
42
0.25
56X
PIN 1 ID
0.15
43
56
(OPTIONAL)
0.1
C A
C
B
0.6
0.4
56X
0.05
4218794/A 07/2013
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RSH0056D
VQFN - 1 mm max height
VQFN
(5.3)
43
SYMM
56
SEE DETAILS
56X (0.7)
56X (0.2)
1
42
52X (0.4)
6X
(1.12)
(1.28)
TYP
SYMM
(6.7)
14
29
(
0.2) TYP
VIA
15
28
(1.28) TYP
6X (1.12)
(6.7)
LAND PATTERN EXAMPLE
SCALE:10X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL
SOLDERMASK
OPENING
SOLDERMASK
OPENING
METAL
NON SOLDERMASK
DEFINED
SOLDERMASK
DEFINED
(PREFERRED)
SOLDERMASK DETAILS
4218794/A 07/2013
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note
in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RSH0056D
VQFN - 1 mm max height
VQFN
SYMM
METAL
TYP
(1.28) TYP
43
56
56X (0.7)
1
42
56X (0.2)
52X (0.4)
(1.28)
TYP
SYMM
(6.7)
14
29
15
28
16X (1.08)
(6.7)
SOLDERPASTE EXAMPLE
BASED ON 0.1mm THICK STENCIL
EXPOSED PAD
67% PRINTED SOLDER COVERAGE BY AREA
SCALE:12X
4218794/A 07/2013
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,
costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either
on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s
applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明