F28384DZWTQR [TI]
TMS320F2838x Real-Time Microcontrollers With Connectivity Manager;
| 型号： | F28384DZWTQR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TMS320F2838x Real-Time Microcontrollers With Connectivity Manager 微控制器 |
| 文件： | 总306页 (文件大小：8283K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1,TMS320F28384S,TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
TMS320F2838x Real-Time Microcontrollers With Connectivity Manager
– Inter-integrated Circuit (CM-I2C)
1 Features
– Synchronous Serial Interface (SSI)
– 10/100 Ethernet 1588 MII/RMII
– MCAN (CAN-FD)
C28x communications peripherals
– Fast Serial Interface (FSI) with two transmitters
and eight receivers
– Four high-speed (up to 50-MHz) SPI ports (pin-
bootable)
– Four Serial Communications Interfaces (SCI/
UART) (pin-bootable)
– Two I2C interfaces (pin-bootable)
– Power-Management Bus (PMBus) interface
– Two Multichannel Buffered Serial Ports
(McBSPs)
CM-C28x shared communications peripherals
– EtherCAT® Slave Controller (ESC)
– USB 2.0 (MAC + PHY)
– Two Controller Area Network (CAN) modules
(pin-bootable)
Analog subsystem
•
Dual-core C28x architecture
– Two TMS320C28x 32-bit CPUs
•
•
200 MHz
•
IEEE 754 double-precision (64-bit) Floating-
Point Unit (FPU)
•
•
•
Trigonometric Math Unit (TMU)
CRC engine and instructions (VCRC)
Fast Integer Division (FINTDIV)
– 512KB (256KW) of flash on each CPU
(ECC-protected)
– 44KB (22KW) of local RAM on each CPU
– 128KB (64KW) of global RAM shared between
the two CPUs (parity-protected)
Two Control Law Accelerators (CLAs)
– 200 MHz
– IEEE 754 single-precision floating-point
– Executes code independently of C28x CPU
System peripherals
•
•
•
•
– Two External Memory Interfaces (EMIFs) with
ASRAM and SDRAM support
– Four Analog-to-Digital Converters (ADCs)
– Two 6-channel Direct Memory Access (DMA)
controllers
•
16-bit mode
– 1.1 MSPS each
– Up to 169 General-Purpose Input/Output
(GPIO) pins with input filtering
– Expanded Peripheral Interrupt controller (ePIE)
– Low-power mode (LPM) support
– Dual-zone security for third-party development
– Unique Identification (UID) number
– Embedded Real-time Analysis and Diagnostic
(ERAD)
– 12 differential or 24 single-ended inputs
12-bit mode
– 3.5 MSPS each
– 24 single-ended inputs
Single sample-and-hold (S/H) on each ADC
Hardware post-processing of conversions
•
•
•
– Eight windowed comparators with 12-bit Digital-
to-Analog Converter (DAC) references
– Three 12-bit buffered DAC outputs
Control peripherals
– Background CRC (BGCRC)
Connectivity Manager (CM)
– Arm® Cortex®-M4 processor
•
•
– 32 Pulse Width Modulator (PWM) channels
– 125 MHz
•
High resolution on both A and B channels of
8 PWM modules (16 channels)
Dead-band support (on both standard and
high resolution)
– 512KB of flash (ECC-protected)
– 96KB of RAM (ECC-protected or parity-
protected)
– Advanced Encryption Standard (AES)
accelerator
– Generic CRC (GCRC)
– 32-channel Micro Direct Memory Access
(µDMA) controller
•
– Seven Enhanced Capture (eCAP) modules
•
High-resolution Capture (HRCAP) available
on two of the seven eCAP modules
– Three Enhanced Quadrature Encoder Pulse
(eQEP) modules
– Eight Sigma-Delta Filter Module (SDFM) input
channels, 2 independent filters per channel
– Universal Asynchronous Receiver/Transmitter
(CM-UART)
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
www.ti.com
•
•
Configurable Logic Block (CLB)
– Augments existing peripheral capability
– Supports position manager solutions
Clock and system control
– Two internal zero-pin 10-MHz oscillators
– On-chip crystal oscillator
– Windowed watchdog timer module
– Missing clock detection circuitry
– Dual-clock Comparator (DCC)
1.2-V core, 3.3-V I/O design
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
Medium/short range radar
HVAC large commercial motor control
Automated sorting equipment
CNC control
Central inverter
String inverter
Inverter & motor control
On-board (OBC) & wireless charger
Linear motor segment controller
Servo drive control module
Industrial AC-DC
•
•
Package options:
– Lead-free, green packaging
– 337-ball New Fine Pitch Ball Grid Array
(nFBGA) [ZWT suffix]
Three phase UPS
– 176-pin PowerPAD™ Thermally Enhanced Low-
profile Quad Flatpack (HLQFP) [PTP suffix]
Temperature options:
•
– S: –40°C to 125°C junction
– Q: –40°C to 125°C ambient
(AEC Q100 qualification for automotive
applications)
3 Description
The TMS320F2838x (F2838x) is a member of the C2000™ real-time microcontroller family of scalable, ultra-low
latency devices designed for efficiency in power electronics, including but not limited to: high power density, high
switching frequencies, and supporting the use of GaN and SiC technologies.
These include such applications as:
•
•
•
•
•
•
Industrial motor drives
Motor control
Solar inverters
Digital power
Electrical vehicles and transportation
Sensing and signal processing
The real-time control subsystem is based on TI’s 32-bit C28x DSP core, which provides 200 MHz of signal-
processing performance in each core for floating- or fixed-point code running from either on-chip flash or SRAM.
The C28x CPU is further boosted by the Trigonometric Math Unit (TMU) and VCRC (Cyclical Redundancy
Check) extended instruction sets, speeding up common algorithms key to real-time control systems. Extended
instruction sets enable IEEE double-precision 64-bit floating-point math. Finally, the Control Law Accelerator
(CLA) enables an additional 200 MHz per core of independent processing ability.
This device also contains an independent Connectivity Manager (CM), based on the ARM Cortex-M4 processor,
that runs at 125 MHz. With its own dedicated flash and SRAM, the CM allows fully independent control of the
interfaces coming in and out of the F2838x, allowing maximum bandwidth for the C28x DSPs to focus on real-
time control.
High-performance analog blocks are tightly integrated with the processing and control units to provide optimal
real-time signal chain performance. Thirty-two frequency-independent PWMs enable control of multiple power
stages, from a 3-phase inverter to advanced multi-level power topologies.
The inclusion of the Configurable Logic Block (CLB) allows the user to add custom logic and potentially integrate
FPGA-like functions into the C2000 real-time MCU.
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Product Folder Links: TMS320F28388D TMS320F28386D TMS320F28386D-Q1 TMS320F28384D
TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
www.ti.com
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
For the first time on a C2000 real-time MCU, there is an EtherCAT Slave Controller, along with other industry-
standard protocols like CAN-FD and USB 2.0. The Fast Serial Interface (FSI) enables up to 200 Mbps of robust
communications across an isolation boundary.
Want to learn more about features that make C2000 MCUs the right choice for your real-time control system?
Check out The Essential Guide for Developing With C2000™ Real-Time Microcontrollers and visit the C2000™
real-time control MCUs page.
Ready to get started? Check out the TMDSCNCD28388D evaluation board and download C2000Ware.
Device Information
PART NUMBER(1)
TMS320F28388DZWT
TMS320F28388SZWT
TMS320F28386DZWT
TMS320F28386SZWT
TMS320F28384DZWT
TMS320F28384SZWT
TMS320F28388DPTP
TMS320F28388SPTP
TMS320F28386DPTP
TMS320F28386SPTP
TMS320F28384DPTP
TMS320F28384SPTP
PACKAGE
nFBGA (337)
nFBGA (337)
nFBGA (337)
nFBGA (337)
nFBGA (337)
nFBGA (337)
HLQFP (176)
HLQFP (176)
HLQFP (176)
HLQFP (176)
HLQFP (176)
HLQFP (176)
BODY SIZE
16.0 mm × 16.0 mm
16.0 mm × 16.0 mm
16.0 mm × 16.0 mm
16.0 mm × 16.0 mm
16.0 mm × 16.0 mm
16.0 mm × 16.0 mm
24.0 mm × 24.0 mm
24.0 mm × 24.0 mm
24.0 mm × 24.0 mm
24.0 mm × 24.0 mm
24.0 mm × 24.0 mm
24.0 mm × 24.0 mm
(1) For more information on these devices, see Mechanical, Packaging, and Orderable Information.
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Product Folder Links: TMS320F28388D TMS320F28386D TMS320F28386D-Q1 TMS320F28384D
TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
www.ti.com
3.1 Functional Block Diagram
The Functional Block Diagram shows the CPU system and associated peripherals.
Connectivity
Manager (CM)
C28 CPU1
C28 CPU2
CPU1 - CM
IPC
CPU1
CPU1.CLA
CPU1.DMA
FPU64
FPU32
TMU
FPU64
FPU32
TMU
MSGRAM0
MSGRAM1
CPU1.CLA1
CPU2.CLA1
Arm Cortex-M4
VCRC
VCRC
CPU2
CPU2.CLA
CPU2.DMA
AES
CPU Timers
GCRC
NVIC
NMI WD
Windowed WD
CPU2 - CM
IPC
BGCRC
BGCRC
CPU Timers
DCC
ePIE
ERAD
BGCRC
BGCRC
CPU Timers
CM M4 CODE
CM M4 SYS
CM µDMA
CM Bus Matrix
Ethernet DMA
MSGRAM0
CPU - CLA
MSGRAM
CPU - CLA
MSGRAM
ePIE
ERAD
NMI WD
MSGRAM1
NMI WD
Windowed WD
Windowed WD
CPU1 - CPU2
IPC
Boot ROM
Secure
Memories
shown in Red
Boot ROM
Secure ROM
Boot ROM
CLA ROM
CLA ROM
MSGRAM0
MSGRAM1
Secure ROM
Secure ROM
Flash (512KB)
Flash (512KB)
Flash (512KB)
C0-C1 RAM (16KB)
E0 RAM (16KB)
M0-M1 RAM (4KB)
D0-D1 RAM (8KB)
M0-M1 RAM (4KB)
D0-D1 RAM (8KB)
LS0-LS7 RAM
(32KB)
LS0-LS7 RAM
(32KB)
GS0-GS15 RAM
(128KB)
S0-S3 RAM (64KB)
DMA - CLA
MSGRAM
DMA - CLA
MSGRAM
CPU1.DMA
CPU2.DMA
CM µDMA
CM Bus
Matrix
PF3
PF1
PF9
PF2
PF5
PF6
PF10
PF4
MUX
MUX
MUX
MUX
Data
169x GPIO
2x CAN
1x USB 1x CAN-FD
8x FSIRX
2x FSITX
2x McBSP
1x PMBUS
4x SPI
EMIF1
EMIF2
8x CLB
8x CMPSS
3x DAC
2x I2C
4x SCI
Result
DMA
1x EtherCAT
(2 Ports)
1x Ethernet
4x ADC
(16-bit / 12-bit)
INPUT XBAR
OUTPUT XBAR
ePWM XBAR
1x CM-I2C
1x CM-UART
1x SSI
7x eCAP
(2 Hi-Res)
32x ePWM
Channels
(16 Hi-Res)
CLB XBAR
CLB INPUT XBAR
3x eQEP
CLB OUTPUT XBAR
8x SD Filters
Figure 3-1. Functional Block Diagram
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
www.ti.com
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................2
3 Description.......................................................................2
3.1 Functional Block Diagram...........................................4
4 Revision History.............................................................. 6
5 Device Comparison.........................................................8
5.1 Related Products...................................................... 10
6 Terminal Configuration and Functions........................11
6.1 Pin Diagrams.............................................................11
6.2 Pin Attributes.............................................................17
6.3 Signal Descriptions................................................... 50
6.4 Pins With Internal Pullup and Pulldown.................... 72
6.5 Pin Multiplexing.........................................................72
6.6 Connections for Unused Pins................................... 86
7 Specifications................................................................ 87
7.1 Absolute Maximum Ratings...................................... 87
7.2 ESD Ratings – Commercial...................................... 88
7.3 ESD Ratings – Automotive....................................... 88
7.4 Recommended Operating Conditions.......................88
7.5 Power Consumption Summary................................. 89
7.6 Electrical Characteristics...........................................94
7.7 Thermal Resistance Characteristics for ZWT
7.12 C28x Control Peripherals......................................162
7.13 C28x Communications Peripherals.......................180
7.14 Connectivity Manager (CM) Peripherals...............223
8 Detailed Description....................................................244
8.1 Overview.................................................................244
8.2 Functional Block Diagram.......................................245
8.3 Memory...................................................................246
8.4 Identification............................................................254
8.5 Bus Architecture – Peripheral Connectivity.............255
8.6 Boot ROM and Peripheral Booting..........................257
8.7 Dual Code Security Module (DCSM)...................... 263
8.8 C28x (CPU1/CPU2) Subsystem............................. 264
8.9 Connectivity Manager (CM) Subsystem................. 280
9 Applications, Implementation, and Layout............... 290
9.1 TI Reference Design...............................................290
10 Device and Documentation Support........................291
10.1 Device and Development Support Tool
Nomenclature............................................................291
10.2 Markings............................................................... 292
10.3 Tools and Software............................................... 293
10.4 Documentation Support........................................ 294
10.5 Support Resources............................................... 295
10.6 Trademarks...........................................................295
10.7 Electrostatic Discharge Caution............................295
10.8 Glossary................................................................295
11 Mechanical, Packaging, and Orderable
Package...................................................................... 96
7.8 Thermal Resistance Characteristics for PTP
Package...................................................................... 96
7.9 Thermal Design Considerations................................97
7.10 System....................................................................98
7.11 C28x Analog Peripherals...................................... 130
Information.................................................................. 296
11.1 Packaging Information.......................................... 296
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
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4 Revision History
Changes from November 8, 2020 to February 2, 2021 (from Revision C (November 2020) to
Revision D (February 2021))
Page
•
Global: Added TMS320F28386D-Q1, TMS320F28384D-Q1, TMS320F28386S-Q1, and TMS320F28384S-
Q1.......................................................................................................................................................................1
Section 5 (Device Comparison): Added 28386D-Q1, 28384D-Q1, 28386S-Q1, and 28384S-Q1 to column
header. Updated "Temperature and Qualification" section of table with device numbers...................................8
Section 7.3 (ESD Ratings – Automotive): Updated device numbers. ..............................................................88
Figure 10-1 (Device Nomenclature): Updated figure to add -Q1 nomenclature............................................. 291
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•
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Product Folder Links: TMS320F28388D TMS320F28386D TMS320F28386D-Q1 TMS320F28384D
TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
www.ti.com
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
Changes from May 18, 2020 to November 7, 2020 (from Revision B (May 2020) to Revision C
(November 2020))
Page
•
•
•
•
•
•
Global: Updated the numbering format for tables, figures, and cross-references throughout the document.... 1
Global: Added 176-pin PowerPAD™ Thermally Enhanced Low-profile Quad Flatpack (HLQFP) [PTP suffix]. 1
Section 1 (Features): Updated Package options. ..............................................................................................1
Section 3 (Description): Updated section and Device Information table. ...........................................................2
Figure 3-1 (Functional Block Diagram): Updated figure..................................................................................... 4
Section 5 (Device Comparison): Updated Device Comparison table. Added 176-pin PTP to Temperature
Options. Updated EMIF2 (16-bit). Updated GPIO I/O pins. Updated Input channels for ADC 16-bit mode.
Updated Input channels for ADC 12-bit mode. Appended "(UART-compatible)" to "Serial Communications
Interface (SCI) - Type 0"..................................................................................................................................... 8
Figure 6-6 (176-Pin PTP PowerPAD Thermally Enhanced Low-Profile Quad Flatpack (Top View)): Added
figure.................................................................................................................................................................11
Section 6.2 (Pin Attributes): Updated Pin Attributes table. Added data for 176-pin package. .........................17
Table 6-2 (Analog Signals): Added data for 176-pin package. ........................................................................ 50
Table 6-3 (Digital Signals): Added data for 176-pin package. ..........................................................................50
Table 6-4 (Power and Ground): Added data for 176-pin package. .................................................................. 50
Table 6-5 (Test, JTAG, and Reset): Added data for 176-pin package. ............................................................ 50
Section 7.2 (ESD Ratings – Commercial): Added data for 176-pin PTP package. ......................................... 88
Section 7.3 (ESD Ratings – Automotive): Added data for 176-pin PTP package. ...........................................88
Section 7.8 (Thermal Resistance Characteristics for PTP Package): Added section. .....................................96
Section 7.10.2.2.2 (Reset (XRSn) Switching Characteristics): Added tboot-flash................................................99
Figure 7-5 (Power-on Reset): Added tboot-flash..................................................................................................99
Section 7.10.4 (Flash Parameters): Updated Erase Times in Flash Parameters table.................................. 109
Section 7.10.5 (Emulation/JTAG): Updated URL of "Hardware Breakpoints and Watchpoints for C28x in
CCS"............................................................................................................................................................... 110
Figure 7-27 (Analog Subsystem Block Diagram (176-Pin PTP)): Added figure............................................. 130
Section 7.11.2.1 (Result Register Mapping): Added section.......................................................................... 134
Section 7.11.2.3.2 (ADC Characteristics (16-bit Differential)): Added footnote about load current on VREFHI...
138
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•
Section 7.11.2.3.6 (ADC Characteristics (12-bit Single-Ended)): Updated table............................................138
Figure 7-33 (ADC Timings for 12-Bit Mode): Updated tINT............................................................................. 147
Section 7.13.1 (Controller Area Network (CAN)): Updated Note about the accuracy of the on-chip zero-pin
oscillator .........................................................................................................................................................180
Figure 7-76 (SCI Block Diagram): Updated figure..........................................................................................207
Section 7.14.2.1.1 (MAC Tx and Rx Features): Updated "Support Ethernet packet timestamping ..." feature....
225
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•
Figure 8-1 (Functional Block Diagram): Updated figure................................................................................. 245
Figure 10-2 (Package Symbolization): Updated figure...................................................................................292
Section 10.3 (Tools and Software): Updated section......................................................................................293
Section 10.4 (Documentation Support): Updated section...............................................................................294
Section 11.1 (Packaging Information): Updated section. ...............................................................................296
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Product Folder Links: TMS320F28388D TMS320F28386D TMS320F28386D-Q1 TMS320F28384D
TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
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5 Device Comparison
The Device Comparison table lists the features of each 2838x device.
Table 5-1. Device Comparison
28386D
28386D-Q1 28384D-Q1
28384D
28386S
28386S-Q1 28384S-Q1
28384S
FEATURE(1)
28388D
28388S
C28x Subsystem
Number
2
1
Frequency (MHz)
200
C28x
32-bit and 64-bit Floating-Point Unit (FPU)
Yes
Yes
Yes
VCRC
TMU – Type 0
Number
2 (1 per CPU)
1
CLA – Type 2
C28x Flash
Frequency (MHz)
200
1MB (512KW)
[512KB (256KW) per CPU]
512KB (256KW)
12KB (6KW)
24KB (12KW)
[12KB (6KW) per CPU]
Dedicated RAM
64KB (32KW)
[32KB (16KW) per CPU]
Local Shared RAM
32KB (16KW)
C28x RAM
128KB (64KW)
(Shared between CPUs)
Global Shared RAM
128KB (64KW)
Total RAM
216KB (108KW)
172KB (86KW)
Background Cyclic Redundancy Check (BGCRC) module
Configurable Logic Block (CLB)
1
8 tiles
6 (3 per CPU)
No
8 tiles
No
32-bit CPU timers
3
1
6-Channel DMA – Type 0
2 (1 per CPU)
Dual-zone Code Security Module (DCSM) for on-chip flash and RAM
Embedded Real-time Analysis and Diagnostic (ERAD)
Yes
Yes
1
337-ball ZWT
EMIF1
(16-bit or 32-bit)
176-pin PTP
1
EMIF
337-ball ZWT
EMIF2 (16-bit)
176-pin PTP
1
–
External interrupts
5
I/O pins (shared
among CPU1,
CPU2, and CM)
337-ball ZWT
176-pin PTP
169
97
GPIO
Input XBAR
Yes
Yes
Output XBAR
24KB
8KB
C28x CPU1, C28x CPU2, and Cortex-M4
C28x CPUs and CLAs
(4KB each direction between
each of the three pairs)
(4KB each direction between
CPU1 and Cortex-M4)
1KB
512 bytes
(256 bytes each direction between CPU
and CLA)
Message RAM
(256 bytes each direction between each
CPU and CLA pair)
1KB
512 bytes
(256 bytes each direction between DMA
and CLA)
DMAs and CLAs
(256 bytes each direction between each
DMA and CLA pair)
Nonmaskable Interrupt Watchdog (NMIWD) timers
Watchdog (WD) timers
2 (1 per CPU)
2 (1 per CPU)
1
1
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
Table 5-1. Device Comparison (continued)
28386D
28386D-Q1 28384D-Q1
28384D
28386S
28386S-Q1 28384S-Q1
28384S
FEATURE(1)
28388D
28388S
Connectivity Manager (CM) Subsystem
Arm Cortex-M4
125 MHz
Flash on Cortex-M4
RAM on Cortex-M4
512KB
96KB
Advanced Encryption Standard (AES) Accelerator
CPU timers
1
3
1
Generic Cyclic Redundancy Check (GCRC) module
Memory Protection Unit (MPU) for Cortex-M4, µDMA, and Ethernet
DMA
3
CM Nonmaskable Interrupt (CMNMI) Module
Trace Port Interface Unit (TPIU)
µDMA
1
1
1
1
Watchdog (WD) timer
C28x Analog Peripherals
Analog-to-Digital Converter (ADC) (configurable to 12-bit or 16-bit)
4
MSPS
1.1
915
24
Conversion Time (ns)(2)
Input channels
(single-ended
mode)
337-ball ZWT
176-pin PTP
ADC 16-bit mode
20
337-ball ZWT
176-pin PTP
12
9
Input channels
(differential mode)
MSPS
3.5
280
24
20
1
Conversion Time (ns)(2)
ADC 12-bit mode
337-ball ZWT
176-pin PTP
Input channels
(single-ended)
Temperature sensor
Comparator subsystem (CMPSS)
(each CMPSS has two comparators and two internal DACs)
8
3
Buffered Digital-to-Analog Converter (DAC)
C28x Control Peripherals
Total inputs
7
eCAP/HRCAP – Type 2
Channels with high-resolution capability
Total channels
2 (eCAP6 and eCAP7)
32
ePWM/HRPWM – Type 4
Channels with high-resolution capability
16 (ePWM1–ePWM8)
ePWM XBAR
Yes
3
eQEP modules – Type 2
SDFM channels – Type 2
8
C28x Communications Peripherals
Fast Serial Interface (FSI) RX - Type 1
Fast Serial Interface (FSI) TX - Type 1
Inter-Integrated Circuit (I2C) – Type 0
8
2
2
2
1
Multichannel Buffered Serial Port (McBSP) – Type 1
Power Management Bus (PMBus) – Type 0
Serial Communications Interface (SCI) – Type 0
(UART-compatible)
4
4
Serial Peripheral Interface (SPI) – Type 2
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
www.ti.com
28384S
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
Table 5-1. Device Comparison (continued)
28386D
28386D-Q1 28384D-Q1
28384D
28386S
FEATURE(1)
28388D
28388S
28386S-Q1 28384S-Q1
Connectivity Manager (CM) Communications Peripherals
2
2
Controller Area Network (CAN) 2.0B – Type 0(3)
CAN with Flexible Data-Rate (CAN-FD)
(can be assigned to
CPU1, CPU2, or CM)
(can be assigned to CPU1 or CM)
1
1
1
(can be
(can be
Ethernet for Control Automation Technology (EtherCAT)
assigned to
CPU1 or
CM)
–
assigned to
CPU1 or
CM)
–
Ethernet Media Access Controller (EMAC)
CM Inter-Integrated Circuit (CM-I2C)
1
1
1
1
1
Synchronous Serial Interface (SSI)
CM Universal Asynchronous Receiver-Transmitter (CM-UART)
Universal Serial Bus (USB) – Type 0
(shared between CPU1 and CM)
Temperature and Qualification
S: –40°C to 125°C
Junction
Temperature (TJ)
337-ball ZWT
28388D, 28386D, 28384D
28388S, 28386S, 28384S
176-pin PTP
337-ball ZWT
176-pin PTP
Temperature Options
Q: –40°C to
–
–
28386D-Q1 28384D-Q1
28386D-Q1 28384D-Q1
–
–
–
–
125°C(4) Ambient
Temperature (TA)
28386S-Q1 28384S-Q1
(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor
differences between devices that do not affect the basic functionality of the module. For more information, see the C2000 Real-Time
Control Peripherals Reference Guide.
(2) Time between start of sample-and-hold window to start of sample-and-hold window of the next conversion.
(3) The CAN module uses the IP known as DCAN. This document uses the names CAN and DCAN interchangeably to reference this
peripheral.
(4) The letter Q refers to AEC Q100 qualification for automotive applications.
5.1 Related Products
TMS320F2837xD Real-Time Dual-Core Microcontrollers
The F2837xD series sets a new standard for performance with dual subsystems. Each subsystem consists of a
C28x CPU and a parallel control law accelerator (CLA), each running at 200 MHz. Enhancing performance are
TMU and VCU accelerators. New capabilities include multiple 16-bit/12-bit mode ADCs, DAC, Sigma-Delta
filters, USB, configurable logic block (CLB), on-chip oscillators, and enhanced versions of all peripherals. The
F2837xD is available with up to 1MB of Flash. It is available in a 176-pin QFP or 337-pin BGA package.
TMS320F2837xS Real-Time Microcontrollers
The F2837xS series is a pin-to-pin compatible version of F2837xD but with only one C28x-CPU-and-CLA
subsystem enabled. It is also available in a 100-pin QFP to enable compatibility with the TMS320F2807x series.
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
6 Terminal Configuration and Functions
6.1 Pin Diagrams
Figure 6-1 shows the terminal assignments on the 337-ball ZWT New Fine Pitch Ball Grid Array (nFBGA). Figure
6-2 to Figure 6-5 show the terminal assignments on the 337-ball ZWT nFBGA in quadrants.
Figure 6-6 shows the pin assignments on the 176-pin PTP PowerPAD Thermally Enhanced Low-Profile Quad
Flatpack.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
ADCINB1
,DACOUTC
ADCINB3
,CMPIN3N
W
V
U
T
VSSA
ADCINB5
VREFHIB
VREFLOD
VSS
VDDIO
GPIO128
GPIO116
GPIO29
FLT1
TDI
TMS
TDO
GPIO121
GPIO39
GPIO132
VSS
ADCINB0
,VDAC
ADCINB2
,CMPIN3P
VREFHIA
ADCINB4
VREFHID
VREFLOB
VSSA
ADCIND5
ADCIND4
VSS
GPIO124
GPIO123
GPIO122
VSS
GPIO127
GPIO126
GPIO125
VDDIO
GPIO131
GPIO130
GPIO129
VDD
GPIO28
GPIO31
GPIO30
VDD3VFL
VSS
GPIO115
GPIO117
GPIO118
VDD3VFL
VSS
FLT2
GPIO32
GPIO33
VDD
TRSTn
GPIO34
GPIO35
VSS
TCK
GPIO120
GPIO119
VSS
GPIO36
GPIO37
GPIO38
GPIO48
GPIO52
GPIO56
GPIO59
GPIO61
GPIO65
GPIO63
VDDOSC
VSS
GPIO40
GPIO41
GPIO136
GPIO49
GPIO53
GPIO58
GPIO60
GPIO64
GPIO66
GPIO62
VDDOSC
VSS
GPIO134
GPIO135
GPIO137
GPIO50
GPIO54
GPIO57
GPIO141
VSS
VDDIO
ERRORSTS
GPIO138
GPIO51
GPIO55
GPIO139
GPIO140
GPIO142
GPIO45
X2
ADCINA0
,DACOUTA
ADCINA2
,CMPIN1P
ADCINA4
,CMPIN2P
ADCIN15
,CMPIN4N
ADCIND1
,CMPIN7N
ADCIND3
,CMPIN8N
ADCINA1
,DACOUTB
ADCINA3
,CMPIN1N
ADCINA5
,CMPIN2N
ADCIN14
,CMPIN4P
ADCIND0
,CMPIN7P
ADCIND2
,CMPIN8P
ADCINC2
,CMPIN6P
ADCINC4
,CMPIN5P
R
P
N
M
L
VREFHIC
VSSA
VREFLOA
VREFLOC
GPIO109
GPIO110
GPIO106
GPIO25
GPIO104
GPIO101
GPIO8
VSSA
VSSA
VSS
VDDA
VDDA
VSS
ADCINC3
,CMPIN6N
ADCINC5
,CMPIN5N
VSS
VSS
VDDIO
VDD
VDD
VSS
VSS
VSS
GPIO114
GPIO112
GPIO107
GPIO24
GPIO105
GPIO102
GPIO9
GPIO113
GPIO111
GPIO108
GPIO23
GPIO22
NC
VDDIO
VSS
VDDIO
VSS
VDDIO
GPIO27
GPIO26
GPIO103
GPIO100
GPIO99
GPIO98
GPIO16
GPIO13
GPIO11
VDDIO
VSS
VDDIO
VSS
VDDIO
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDIO
VSS
VDDIO
VSS
K
J
VDD
VDD
GPIO44
VSS
VSS
VDD
VDD
NC
H
G
F
VDDIO
VDDIO
VSS
VDDIO
VDDIO
VSS
VSS
VSS
VSSOSC
GPIO133
GPIO143
GPIO47
GPIO146
GPIO68
GPIO69
VDDIO
VSSOSC
VDDIO
VDD
VDD
X1
GPIO20
GPIO17
GPIO14
GPIO12
GPIO10
GPIO97
GPIO21
GPIO18
GPIO15
GPIO96
GPIO95
GPIO94
VDDIO
VDDIO
VDDIO
GPIO5
GPIO4
GPIO3
GPIO2
VSS
VSS
VDD
VDDIO
VDDIO
VDD
VSS
VDDIO
VDDIO
VSS
VSS
VDDIO
GPIO144
GPIO145
GPIO147
GPIO74
GPIO71
GPIO70
XRSn
E
D
C
B
A
GPIO19
GPIO168
GPIO167
GPIO93
GPIO92
VSS
VSS
VDD
VDD
VSS
VSS
VSS
VDDIO
GPIO46
GPIO42
GPIO43
GPIO67
GPIO166
GPIO165
GPIO91
GPIO90
GPIO89
GPIO88
GPIO7
GPIO6
GPIO1
GPIO0
GPIO164
GPIO163
GPIO162
GPIO161
GPIO160
VDDIO
GPIO159
GPIO158
GPIO157
VSS
GPIO87
GPIO86
GPIO85
GPIO84
GPIO156
GPIO155
GPIO154
GPIO153
GPIO152
GPIO151
GPIO150
GPIO149
GPIO148
GPIO83
GPIO82
GPIO81
GPIO80
GPIO79
GPIO78
GPIO77
GPIO75
GPIO76
GPIO72
GPIO73
VSS
Not to scale
A. Only the GPIO function is shown on GPIO terminals. See the Pin Attributes table for the complete, muxed signal name.
Figure 6-1. 337-Ball ZWT New Fine Pitch Ball Grid Array (Bottom View)
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
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1
2
3
4
5
6
7
8
9
10
ADCINB1
,DACOUTC
ADCINB3
,CMPIN3N
W
V
U
T
VSSA
ADCINB5
VREFHIB
VREFLOD
VSS
VDDIO
GPIO128
GPIO116
ADCINB0
,VDAC
ADCINB2
,CMPIN3P
VREFHIA
ADCINB4
VREFHID
VREFLOB
VSSA
ADCIND5
ADCIND4
VSS
GPIO124
GPIO123
GPIO122
VSS
GPIO127
GPIO126
GPIO125
VDDIO
GPIO131
GPIO130
GPIO129
VDD
ADCINA0
,DACOUTA
ADCINA2
,CMPIN1P
ADCINA4
,CMPIN2P
ADCIN15
,CMPIN4N
ADCIND1
,CMPIN7N
ADCIND3
,CMPIN8N
ADCINA1
,DACOUTB
ADCINA3
,CMPIN1N
ADCINA5
,CMPIN2N
ADCIN14
,CMPIN4P
ADCIND0
,CMPIN7P
ADCIND2
,CMPIN8P
ADCINC2
,CMPIN6P
ADCINC4
,CMPIN5P
R
P
N
M
L
VREFHIC
VSSA
VREFLOA
VREFLOC
GPIO109
GPIO110
GPIO106
GPIO25
VSSA
VSSA
VSS
VDDA
VDDA
VSS
ADCINC3
,CMPIN6N
ADCINC5
,CMPIN5N
VSS
VSS
VDDIO
VDD
VSS
GPIO114
GPIO112
GPIO107
GPIO24
GPIO113
GPIO111
GPIO108
GPIO23
VDDIO
GPIO27
GPIO26
VDDIO
VSS
VDDIO
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K
VDD
VDD
VSS
Not to scale
1
2
4
3
A. Only the GPIO function is shown on GPIO terminals. See the Pin Attributes table for the complete, muxed signal name.
Figure 6-2. 337-Ball ZWT New Fine Pitch Ball Grid Array (Bottom View) – [Quadrant 1]
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
11
12
13
14
15
16
17
18
19
W
V
U
T
GPIO29
FLT1
TDI
TMS
TDO
GPIO121
GPIO39
GPIO132
VSS
GPIO28
GPIO31
GPIO30
VDD3VFL
VSS
GPIO115
GPIO117
GPIO118
VDD3VFL
VSS
FLT2
GPIO32
GPIO33
VDD
TRSTn
GPIO34
GPIO35
VSS
TCK
GPIO120
GPIO119
VSS
GPIO36
GPIO37
GPIO38
GPIO48
GPIO52
GPIO56
GPIO59
GPIO61
GPIO65
GPIO40
GPIO41
GPIO136
GPIO49
GPIO53
GPIO58
GPIO60
GPIO64
GPIO66
GPIO134
GPIO135
GPIO137
GPIO50
GPIO54
GPIO57
GPIO141
VSS
VDDIO
ERRORSTS
GPIO138
GPIO51
R
P
N
M
L
VDD
VSS
VSS
GPIO55
VDDIO
VSS
VDDIO
VSS
GPIO139
GPIO140
GPIO142
VSS
VSS
VSS
VSS
VSS
VSS
VDDIO
VSS
VDDIO
VSS
K
GPIO44
GPIO45
Not to scale
1
3
2
4
A. Only the GPIO function is shown on GPIO terminals. See the Pin Attributes table for the complete, muxed signal name.
Figure 6-3. 337-Ball ZWT New Fine Pitch Ball Grid Array (Bottom View) – [Quadrant 2]
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Product Folder Links: TMS320F28388D TMS320F28386D TMS320F28386D-Q1 TMS320F28384D
TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
www.ti.com
1
2
3
4
5
6
7
8
9
10
J
GPIO103
GPIO104
GPIO105
GPIO22
VSS
VSS
VSS
VSS
VSS
H
G
F
GPIO100
GPIO99
GPIO98
GPIO16
GPIO13
GPIO11
VDDIO
VSS
GPIO101
GPIO8
GPIO102
GPIO9
NC
VDDIO
VDDIO
VSS
VDDIO
VDDIO
VSS
VSS
VSS
VSS
VDDIO
GPIO20
GPIO17
GPIO14
GPIO12
GPIO10
GPIO97
GPIO21
GPIO18
GPIO15
GPIO96
GPIO95
GPIO94
VDDIO
VDDIO
VDDIO
GPIO5
GPIO4
GPIO3
GPIO2
VSS
VSS
VDD
VDDIO
VDDIO
E
D
C
B
A
GPIO19
GPIO168
GPIO167
GPIO93
GPIO92
VSS
VSS
VDD
GPIO166
GPIO165
GPIO91
GPIO90
GPIO89
GPIO88
GPIO7
GPIO6
GPIO1
GPIO0
GPIO164
GPIO163
GPIO162
GPIO161
GPIO160
VDDIO
GPIO159
GPIO158
GPIO157
VSS
Not to scale
1
3
2
4
A. Only the GPIO function is shown on GPIO terminals. See the Pin Attributes table for the complete, muxed signal name.
Figure 6-4. 337-Ball ZWT New Fine Pitch Ball Grid Array (Bottom View) – [Quadrant 3]
Copyright © 2021 Texas Instruments Incorporated
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
11
12
13
14
15
16
17
18
19
X2
J
VSS
VSS
VDD
VDD
GPIO63
GPIO62
NC
H
G
F
VSS
VSS
VSS
VDD
VSS
VDD
VDDOSC
VDDOSC
VSSOSC
GPIO133
GPIO143
GPIO47
GPIO146
GPIO68
GPIO69
VDDIO
VSSOSC
VSS
VSS
X1
VDD
VSS
VDDIO
VDDIO
VSS
VSS
VDDIO
VDDIO
GPIO75
GPIO76
GPIO72
GPIO73
GPIO144
GPIO145
GPIO147
GPIO74
GPIO71
GPIO70
XRSn
E
D
C
B
A
VDD
VSS
VSS
VSS
GPIO46
GPIO42
GPIO43
GPIO67
GPIO87
GPIO86
GPIO85
GPIO84
GPIO156
GPIO155
GPIO154
GPIO153
GPIO152
GPIO151
GPIO150
GPIO149
GPIO148
GPIO83
GPIO82
GPIO81
GPIO80
GPIO79
GPIO78
GPIO77
VSS
Not to scale
1
3
2
4
A. Only the GPIO function is shown on GPIO terminals. See the Pin Attributes table for the complete, muxed signal name.
Figure 6-5. 337-Ball ZWT New Fine Pitch Ball Grid Array (Bottom View) – [Quadrant 4]
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Product Folder Links: TMS320F28388D TMS320F28386D TMS320F28386D-Q1 TMS320F28384D
TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
www.ti.com
GPIO68
GPIO69
GPIO70
GPIO71
VDD
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
VDDIO
GPIO40
GPIO39
GPIO38
GPIO37
GPIO36
VDDIO
TCK
VDDIO
GPIO72
GPIO73
GPIO74
GPIO75
GPIO76
GPIO77
GPIO78
GPIO79
VDDIO
GPIO80
GPIO81
GPIO82
GPIO83
VDDIO
VDD
GPIO84
GPIO85
GPIO86
GPIO87
VDD
VDDIO
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
VDDIO
VDD
TMS
TRSTn
TDO
TDI
VDD
VDDIO
FLT2
FLT1
VDD3VFL
GPIO35
GPIO34
GPIO33
VDDIO
GPIO32
GPIO31
GPIO29
GPIO28
GPIO30
VDDIO
VDD
ADCIND4
ADCIND3,CMPIN8N
ADCIND2,CMPIN8P
ADCIND1,CMPIN7N
ADCIND0,CMPIN7P
VREFHID
VDDA
VREFHIB
VSSA
VREFLOD
VREFLOB
ADCINB3,CMPIN3N
ADCINB2,CMPIN3P
ADCINB1,DACOUTC
ADCINB0,VDAC
ADCIN15,CMPIN4N
GPIO88
GPIO89
GPIO90
GPIO91
GPIO92
GPIO93
GPIO94
Not to scale
A. Only the GPIO function is shown on GPIO terminals. See the Pin Attributes table for the complete, muxed signal name.
Figure 6-6. 176-Pin PTP PowerPAD Thermally Enhanced Low-Profile Quad Flatpack (Top View)
Copyright © 2021 Texas Instruments Incorporated
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Product Folder Links: TMS320F28388D TMS320F28386D TMS320F28386D-Q1 TMS320F28384D
TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
www.ti.com
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
6.2 Pin Attributes
Table 6-1. Pin Attributes
MUX
POSITION
PIN
TYPE
SIGNAL NAME
337
176
DESCRIPTION
ANALOG
Input 14 to all ADCs. This pin can be used as a general
purpose ADCIN pin or it can be used to calibrate all ADCs
together (either single-ended or differential) from an
external reference
ADCIN14
CMPIN4P
ADCIN15
I
I
I
T4
44
Comparator 4 positive input
Input 15 to all ADCs. This pin can be used as a general
purpose ADCIN pin or it can be used to calibrate all ADCs
together (either single-ended or differential) from an
external reference
U4
45
CMPIN4N
ADCINA0
DACOUTA
ADCINA1
I
I
Comparator 4 negative input
ADC-A Input 0. There is a 50-kΩ internal pulldown on this
pin in both an ADC input or DAC output mode which
cannot be disabled.
U1
T1
43
42
O
I
Buffered DAC-A Output.
ADC-A Input 1. There is a 50-kΩ internal pulldown on this
pin in both an ADC input or DAC output mode which
cannot be disabled.
DACOUTB
ADCINA2
CMPIN1P
ADCINA3
CMPIN1N
ADCINA4
CMPIN2P
ADCINA5
CMPIN2N
O
I
Buffered DAC-B Output.
ADC-A Input 2
U2
T2
U3
T3
41
40
39
38
I
Comparator 1 positive input
ADC-A Input 3
I
I
Comparator 1 negative input
ADC-A Input 4
I
I
Comparator 2 positive input
ADC-A Input 5
I
I
Comparator 2 negative input
ADC-B Input 0. There is a 100-pF capacitor to VSSA on
this pin whether used for ADC input or DAC reference
which cannot be disabled. If this pin is being used as a
reference for the on-chip DACs, place at least a 1-µF
capacitor on this pin.
ADCINB0
I
V2
46
47
VDAC
I
I
Optional external reference voltage for on-chip DACs.
ADC-B Input 1. There is a 50-kΩ internal pulldown on this
pin in both an ADC input or DAC output mode which
cannot be disabled.
ADCINB1
W2
DACOUTC
ADCINB2
CMPIN3P
ADCINB3
CMPIN3N
ADCINB4
ADCINB5
ADCINC2
CMPIN6P
ADCINC3
CMPIN6N
O
I
Buffered DAC-C Output.
ADC-B Input 2
V3
48
49
I
Comparator 3 positive input
ADC-B Input 3
I
W3
I
Comparator 3 negative input
ADC-B Input 4
V4
I
W4
I
ADC-B Input 5
I
ADC-C Input 2
R3
P3
31
30
I
Comparator 6 positive input
ADC-C Input 3
I
I
Comparator 6 negative input
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
www.ti.com
Table 6-1. Pin Attributes (continued)
MUX
POSITION
PIN
TYPE
SIGNAL NAME
ADCINC4
337
176
DESCRIPTION
I
I
I
I
I
I
I
I
I
I
I
I
I
I
ADC-C Input 4
R4
29
CMPIN5P
ADCINC5
CMPIN5N
ADCIND0
CMPIN7P
ADCIND1
CMPIN7N
ADCIND2
CMPIN8P
ADCIND3
CMPIN8N
ADCIND4
ADCIND5
Comparator 5 positive input
ADC-C Input 5
P4
T5
U5
T6
U6
Comparator 5 negative input
ADC-D Input 0
56
57
58
Comparator 7 positive input
ADC-D Input 1
Comparator 7 negative input
ADC-D Input 2
Comparator 8 positive input
ADC-D Input 3
59
60
Comparator 8 negative input
ADC-D Input 4
T7
U7
ADC-D Input 5
ADC-A high reference. This voltage must be driven into
the pin from external circuitry. Place at least a 2.2-µF
capacitor on this pin for the 12-bit mode, or at least a 22-
µF capacitor for the 16-bit mode. This capacitor should be
placed as close to the device as possible between the
VREFHIA and VREFLOA pins. NOTE: Do not load this pin
externally
VREFHIA
VREFHIB
VREFHIC
VREFHID
V1
W5
R1
V5
37
53
35
55
I
I
I
I
ADC-B high reference. This voltage must be driven into
the pin from external circuitry. Place at least a 2.2-µF
capacitor on this pin for the 12-bit mode, or at least a 22-
µF capacitor for the 16-bit mode. This capacitor should be
placed as close to the device as possible between the
VREFHIB and VREFLOB pins. NOTE: Do not load this pin
externally
ADC-C high reference. This voltage must be driven into
the pin from external circuitry. Place at least a 2.2-µF
capacitor on this pin for the 12-bit mode, or at least a 22-
µF capacitor for the 16-bit mode. This capacitor should be
placed as close to the device as possible between the
VREFHIC and VREFLOC pins. NOTE: Do not load this
pin externally
ADC-D high reference. This voltage must be driven into
the pin from external circuitry. Place at least a 2.2-µF
capacitor on this pin for the 12-bit mode, or at least a 22-
µF capacitor for the 16-bit mode. This capacitor should be
placed as close to the device as possible between the
VREFHID and VREFLOD pins. NOTE: Do not load this
pin externally
VREFLOA
VREFLOB
VREFLOC
VREFLOD
R2
V6
P2
W6
33
50
32
51
I
I
I
I
ADC-A Low Reference
ADC-B Low Reference
ADC-C Low Reference
ADC-D Low Reference
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
www.ti.com
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
Table 6-1. Pin Attributes (continued)
MUX
POSITION
PIN
TYPE
SIGNAL NAME
337
176
DESCRIPTION
GPIO
GPIO0
0, 4, 8, 12
I/O
General-Purpose Input Output 0
EPWM1A
1
O
ePWM-1 Output A (High-res available on ePWM1-8)
I2C-A Open-Drain Bidirectional Data
CM-I2C-A Open-Drain Bidirectional Data
EtherCAT General-Purpose Input 0
FSITX-A Data Output 0
I2CA_SDA
CM-I2CA_SDA
ESC_GPI0
FSITXA_D0
GPIO1
6
I/OD
C8
160
9
I/OD
10
I
13
O
0, 4, 8, 12
I/O
General-Purpose Input Output 1
ePWM-1 Output B (High-res available on ePWM1-8)
McBSP-B Receive Frame Sync
I2C-A Open-Drain Bidirectional Clock
CM-I2C-A Open-Drain Bidirectional Clock
EtherCAT General-Purpose Input 1
FSITX-A Data Output 1
EPWM1B
1
O
MFSRB
3
I
I2CA_SCL
CM-I2CA_SCL
ESC_GPI1
FSITXA_D1
GPIO2
6
D8
A7
B7
161
162
163
I/OD
9
I/OD
10
I
O
I/O
O
O
I/OD
I
13
0, 4, 8, 12
General-Purpose Input Output 2
ePWM-2 Output A (High-res available on ePWM1-8)
Output X-BAR Output 1
EPWM2A
1
OUTPUTXBAR1
I2CB_SDA
ESC_GPI2
FSITXA_CLK
GPIO3
5
6
I2C-B Open-Drain Bidirectional Data
EtherCAT General-Purpose Input 2
FSITX-A Output Clock
10
13
O
I/O
O
O
I
0, 4, 8, 12
General-Purpose Input Output 3
ePWM-2 Output B (High-res available on ePWM1-8)
Output X-BAR Output 2
EPWM2B
1
OUTPUTXBAR2
MCLKRB
2, 5
3
McBSP-B Receive Clock
I2CB_SCL
ESC_GPI3
FSIRXA_D0
GPIO4
6
I/OD
I
I2C-B Open-Drain Bidirectional Clock
EtherCAT General-Purpose Input 3
FSIRX-A Data Input 0
10
13
I
0, 4, 8, 12
I/O
O
O
O
O
I
General-Purpose Input Output 4
ePWM-3 Output A (High-res available on ePWM1-8)
Output X-BAR Output 3
EPWM3A
1
OUTPUTXBAR3
CANA_TX
MCAN_TX
ESC_GPI4
FSIRXA_D1
GPIO5
5
6
C7
164
CAN-A Transmit
9
CAN/CAN-FD Transmit
10
EtherCAT General-Purpose Input 4
FSIRX-A Data Input 1
13
I
0, 4, 8, 12
I/O
O
I
General-Purpose Input Output 5
ePWM-3 Output B (High-res available on ePWM1-8)
McBSP-A Receive Frame Sync
Output X-BAR Output 3
EPWM3B
1
2
MFSRA
OUTPUTXBAR3
CANA_RX
MCAN_RX
ESC_GPI5
FSIRXA_CLK
3
O
I
D7
165
6
CAN-A Receive
9
I
CAN/CAN-FD Receive
10
13
I
EtherCAT General-Purpose Input 5
FSIRX-A Input Clock
I
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Product Folder Links: TMS320F28388D TMS320F28386D TMS320F28386D-Q1 TMS320F28384D
TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
www.ti.com
Table 6-1. Pin Attributes (continued)
MUX
POSITION
PIN
TYPE
SIGNAL NAME
337
176
DESCRIPTION
GPIO6
0, 4, 8, 12
I/O
O
O
O
I
General-Purpose Input Output 6
EPWM4A
1
ePWM-4 Output A (High-res available on ePWM1-8)
Output X-BAR Output 4
OUTPUTXBAR4
EXTSYNCOUT
EQEP3_A
CANB_TX
ESC_GPI6
FSITXB_D0
GPIO7
2
3
External ePWM Synchronization Pulse
eQEP-3 Input A
A6
166
5
6
O
I
CAN-B Transmit
10
EtherCAT General-Purpose Input 6
FSITX-B Data Output 0
13
O
I/O
O
I
0, 4, 8, 12
General-Purpose Input Output 7
ePWM-4 Output B (High-res available on ePWM1-8)
McBSP-A Receive Clock
EPWM4B
1
MCLKRA
2
OUTPUTXBAR5
EQEP3_B
CANB_RX
ESC_GPI7
FSITXB_D1
GPIO8
3
O
I
Output X-BAR Output 5
B6
167
5
eQEP-3 Input B
6
I
CAN-B Receive
10
I
EtherCAT General-Purpose Input 7
FSITX-B Data Output 1
13
O
I/O
O
O
0, 4, 8, 12
General-Purpose Input Output 8
ePWM-5 Output A (High-res available on ePWM1-8)
CAN-B Transmit
EPWM5A
1
2
CANB_TX
ADC Start of Conversion A Output for External ADC (from
ePWM modules)
ADCSOCAO
3
O
EQEP3_STROBE
SCIA_TX
5
I/O
O
O
O
O
O
I
eQEP-3 Strobe
G2
18
6
SCI-A Transmit Data
MCAN_TX
9
CAN/CAN-FD Transmit
EtherCAT General-Purpose Output 0
FSITX-B Output Clock
ESC_GPO0
FSITXB_CLK
FSITXA_D1
FSIRXA_D0
GPIO9
10
13
14
FSITX-A Data Output 1
FSIRX-A Data Input 0
15
0, 4, 8, 12
I/O
O
O
O
I/O
I
General-Purpose Input Output 9
ePWM-5 Output B (High-res available on ePWM1-8)
SCI-B Transmit Data
EPWM5B
1
2
SCIB_TX
OUTPUTXBAR6
EQEP3_INDEX
SCIA_RX
3
Output X-BAR Output 6
eQEP-3 Index
5
G3
19
6
SCI-A Receive Data
ESC_GPO1
FSIRXB_D0
FSITXA_D0
FSIRXA_CLK
10
13
14
15
O
I
EtherCAT General-Purpose Output 1
FSIRX-B Data Input 0
O
I
FSITX-A Data Output 0
FSIRX-A Input Clock
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
www.ti.com
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
Table 6-1. Pin Attributes (continued)
MUX
POSITION
PIN
TYPE
SIGNAL NAME
337
176
DESCRIPTION
GPIO10
0, 4, 8, 12
I/O
O
I
General-Purpose Input Output 10
ePWM-6 Output A (High-res available on ePWM1-8)
CAN-B Receive
EPWM6A
CANB_RX
1
2
ADC Start of Conversion B Output for External ADC (from
ePWM modules)
ADCSOCBO
3
O
EQEP1_A
SCIB_TX
5
I
O
I
eQEP-1 Input A
B2
1
6
SCI-B Transmit Data
MCAN_RX
ESC_GPO2
FSIRXB_D1
FSITXA_CLK
FSIRXA_D1
GPIO11
9
CAN/CAN-FD Receive
10
O
I
EtherCAT General-Purpose Output 2
FSIRX-B Data Input 1
13
14
O
I
FSITX-A Output Clock
15
FSIRX-A Data Input 1
0, 4, 8, 12
I/O
O
I
General-Purpose Input Output 11
ePWM-6 Output B (High-res available on ePWM1-8)
SCI-B Receive Data
EPWM6B
1
SCIB_RX
2, 6
OUTPUTXBAR7
EQEP1_B
ESC_GPO3
FSIRXB_CLK
FSIRXA_D1
GPIO12
3
O
I
Output X-BAR Output 7
C1
2
5
eQEP-1 Input B
10
O
I
EtherCAT General-Purpose Output 3
FSIRX-B Input Clock
13
14
I
FSIRX-A Data Input 1
0, 4, 8, 12
I/O
O
O
O
I/O
O
O
I
General-Purpose Input Output 12
ePWM-7 Output A (High-res available on ePWM1-8)
CAN-B Transmit
EPWM7A
1
CANB_TX
MDXB
2
3
McBSP-B Transmit Serial Data
eQEP-1 Strobe
EQEP1_STROBE
SCIC_TX
5
C2
4
6
SCI-C Transmit Data
ESC_GPO4
FSIRXC_D0
FSIRXA_D0
GPIO13
10
EtherCAT General-Purpose Output 4
FSIRX-C Data Input 0
13
14
I
FSIRX-A Data Input 0
0, 4, 8, 12
I/O
O
I
General-Purpose Input Output 13
ePWM-7 Output B (High-res available on ePWM1-8)
CAN-B Receive
EPWM7B
1
CANB_RX
MDRB
2
3
I
McBSP-B Receive Serial Data
eQEP-1 Index
EQEP1_INDEX
SCIC_RX
5
D1
5
I/O
I
6
SCI-C Receive Data
ESC_GPO5
FSIRXC_D1
FSIRXA_CLK
GPIO14
10
O
I
EtherCAT General-Purpose Output 5
FSIRX-C Data Input 1
13
14
I
FSIRX-A Input Clock
0, 4, 8, 12
I/O
O
O
O
O
O
I
General-Purpose Input Output 14
ePWM-8 Output A (High-res available on ePWM1-8)
SCI-B Transmit Data
EPWM8A
1
2
SCIB_TX
MCLKXB
3
D2
6
McBSP-B Transmit Clock
Output X-BAR Output 3
OUTPUTXBAR3
ESC_GPO6
FSIRXC_CLK
6
10
13
EtherCAT General-Purpose Output 6
FSIRX-C Input Clock
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Product Folder Links: TMS320F28388D TMS320F28386D TMS320F28386D-Q1 TMS320F28384D
TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
www.ti.com
Table 6-1. Pin Attributes (continued)
MUX
POSITION
PIN
TYPE
SIGNAL NAME
GPIO15
337
176
DESCRIPTION
0, 4, 8, 12
I/O
O
I
General-Purpose Input Output 15
EPWM8B
1
ePWM-8 Output B (High-res available on ePWM1-8)
SCI-B Receive Data
SCIB_RX
2
MFSXB
3
D3
7
O
O
O
I
McBSP-B Transmit Frame Sync
Output X-BAR Output 4
OUTPUTXBAR4
ESC_GPO7
FSIRXD_D0
GPIO16
6
10
EtherCAT General-Purpose Output 7
FSIRX-D Data Input 0
13
0, 4, 8, 12
I/O
I/O
O
O
O
I
General-Purpose Input Output 16
SPI-A Slave In, Master Out (SIMO)
CAN-B Transmit
SPIA_SIMO
CANB_TX
OUTPUTXBAR7
EPWM9A
1
2
3
Output X-BAR Output 7
E1
8
5
ePWM-9 Output A (High-res available on ePWM1-8)
SDFM-1 Channel 1 Data Input
SSI-A Serial Data Transmit
FSIRX-D Data Input 1
SD1_D1
7
SSIA_TX
11
I/O
I
FSIRXD_D1
GPIO17
13
0, 4, 8, 12
I/O
I/O
I
General-Purpose Input Output 17
SPI-A Slave Out, Master In (SOMI)
CAN-B Receive
SPIA_SOMI
CANB_RX
OUTPUTXBAR8
EPWM9B
1
2
3
O
O
I
Output X-BAR Output 8
E2
9
5
ePWM-9 Output B (High-res available on ePWM1-8)
SDFM-1 Channel 1 Clock Input
SSI-A Serial Data Receive
SD1_C1
7
SSIA_RX
11
I/O
I
FSIRXD_CLK
GPIO18
13
FSIRX-D Input Clock
0, 4, 8, 12
I/O
I/O
O
I
General-Purpose Input Output 18
SPI-A Clock
SPIA_CLK
SCIB_TX
1
2
SCI-B Transmit Data
CANA_RX
EPWM10A
SD1_D2
3
CAN-A Receive
5
O
I
ePWM-10 Output A (High-res available on ePWM1-8)
SDFM-1 Channel 2 Data Input
CAN/CAN-FD Receive
E3
10
7
MCAN_RX
EMIF1_CS2n
SSIA_CLK
FSIRXE_D0
GPIO19
9
I
10
O
I/O
I
External memory interface 1 chip select 2
SSI-A Clock
11
13
FSIRX-E Data Input 0
0, 4, 8, 12
I/O
I/O
I
General-Purpose Input Output 19
SPI-A Slave Transmit Enable (STE)
SCI-B Receive Data
SPIA_STEn
SCIB_RX
1
2
CANA_TX
EPWM10B
SD1_C2
3
O
O
I
CAN-A Transmit
5
ePWM-10 Output B (High-res available on ePWM1-8)
SDFM-1 Channel 2 Clock Input
CAN/CAN-FD Transmit
E4
12
7
MCAN_TX
EMIF1_CS3n
SSIA_FSS
FSIRXE_D1
9
O
O
I/O
I
10
11
13
External memory interface 1 chip select 3
SSI-A Frame Sync
FSIRX-E Data Input 1
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
www.ti.com
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
Table 6-1. Pin Attributes (continued)
MUX
POSITION
PIN
SIGNAL NAME
337
176
DESCRIPTION
TYPE
I/O
I
GPIO20
0, 4, 8, 12
General-Purpose Input Output 20
eQEP-1 Input A
EQEP1_A
MDXA
1
2
O
O
O
I
McBSP-A Transmit Serial Data
CAN-B Transmit
CANB_TX
EPWM11A
SD1_D3
3
5
ePWM-11 Output A (High-res available on ePWM1-8)
SDFM-1 Channel 3 Data Input
External memory interface 1 bank address 0
Trace Data 0
F2
13
7
EMIF1_BA0
TRACE_DATA0
FSIRXE_CLK
SPIC_SIMO
GPIO21
10
O
O
I
11
13
FSIRX-E Input Clock
14
I/O
I/O
I
SPI-C Slave In, Master Out (SIMO)
General-Purpose Input Output 21
eQEP-1 Input B
0, 4, 8, 12
EQEP1_B
MDRA
1
2
I
McBSP-A Receive Serial Data
CAN-B Receive
CANB_RX
EPWM11B
SD1_C3
3
I
5
O
I
ePWM-11 Output B (High-res available on ePWM1-8)
SDFM-1 Channel 3 Clock Input
External memory interface 1 bank address 1
Trace Data 1
F3
14
7
EMIF1_BA1
TRACE_DATA1
FSIRXF_D0
SPIC_SOMI
GPIO22
10
O
O
I
11
13
FSIRX-F Data Input 0
14
I/O
I/O
I/O
O
O
O
I/O
I
SPI-C Slave Out, Master In (SOMI)
General-Purpose Input Output 22
eQEP-1 Strobe
0, 4, 8, 12
EQEP1_STROBE
MCLKXA
1
2
McBSP-A Transmit Clock
SCIB_TX
3
SCI-B Transmit Data
EPWM12A
SPIB_CLK
SD1_D4
5
ePWM-12 Output A (High-res available on ePWM1-8)
SPI-B Clock
6
J4
22
7
SDFM-1 Channel 4 Data Input
CAN/CAN-FD Transmit
MCAN_TX
EMIF1_RAS
TRACE_DATA2
FSIRXF_D1
SPIC_CLK
GPIO23
9
O
O
O
I
10
External memory interface 1 row address strobe
Trace Data 2
11
13
FSIRX-F Data Input 1
14
I/O
I/O
I/O
O
I
SPI-C Clock
0, 4, 8, 12
General-Purpose Input Output 23
eQEP-1 Index
EQEP1_INDEX
MFSXA
1
2
McBSP-A Transmit Frame Sync
SCI-B Receive Data
SCIB_RX
3
EPWM12B
SPIB_STEn
SD1_C4
5
O
I/O
I
ePWM-12 Output B (High-res available on ePWM1-8)
SPI-B Slave Transmit Enable (STE)
SDFM-1 Channel 4 Clock Input
CAN/CAN-FD Receive
6
K4
23
7
MCAN_RX
EMIF1_CAS
TRACE_DATA3
FSIRXF_CLK
SPIC_STEn
9
I
10
11
13
14
O
O
I
External memory interface 1 column address strobe
Trace Data 3
FSIRX-F Input Clock
I/O
SPI-C Slave Transmit Enable (STE)
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Product Folder Links: TMS320F28388D TMS320F28386D TMS320F28386D-Q1 TMS320F28384D
TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
www.ti.com
Table 6-1. Pin Attributes (continued)
MUX
POSITION
PIN
TYPE
SIGNAL NAME
GPIO24
337
176
DESCRIPTION
0, 4, 8, 12
I/O
O
General-Purpose Input Output 24
Output X-BAR Output 1
OUTPUTXBAR1
EQEP2_A
1
2
I
eQEP-2 Input A
MDXB
3
O
McBSP-B Transmit Serial Data
SPI-B Slave In, Master Out (SIMO)
SDFM-2 Channel 1 Data Input
PMBus-A Open-Drain Bidirectional Clock
SPIB_SIMO
SD2_D1
6
I/O
I
7
K3
24
PMBUSA_SCL
EMIF1_DQM0
TRACE_CLK
EPWM13A
9
I/OD
O
10
External memory interface 1 Input/output mask for byte 0
Trace Clock
11
O
13
O
ePWM-13 Output A (High-res available on ePWM1-8)
FSIRX-G Data Input 0
FSIRXG_D0
GPIO25
15
I
0, 4, 8, 12
I/O
O
General-Purpose Input Output 25
Output X-BAR Output 2
OUTPUTXBAR2
EQEP2_B
1
2
I
eQEP-2 Input B
MDRB
3
I
McBSP-B Receive Serial Data
SPI-B Slave Out, Master In (SOMI)
SDFM-2 Channel 1 Clock Input
PMBus-A Open-Drain Bidirectional Data
External memory interface 1 Input/output mask for byte 1
Trace Single Wire Out
SPIB_SOMI
SD2_C1
6
I/O
I
7
K2
25
PMBUSA_SDA
EMIF1_DQM1
TRACE_SWO
EPWM13B
9
I/OD
O
10
11
O
13
O
ePWM-13 Output B (High-res available on ePWM1-8)
FSITX-A Data Output 1
FSITXA_D1
FSIRXG_D1
GPIO26
14
O
15
I
FSIRX-G Data Input 1
0, 4, 8, 12
I/O
O
General-Purpose Input Output 26
Output X-BAR Output 3
OUTPUTXBAR3
EQEP2_INDEX
MCLKXB
1, 5
2
I/O
O
eQEP-2 Index
3
McBSP-B Transmit Clock
SPIB_CLK
6
I/O
I
SPI-B Clock
SD2_D2
7
SDFM-2 Channel 2 Data Input
PMBus-A Open-Drain Bidirectional Alert Signal
External memory interface 1 Input/output mask for byte 2
EtherCAT MDIO Clock
K1
27
PMBUSA_ALERT
EMIF1_DQM2
ESC_MDIO_CLK
EPWM14A
9
I/OD
O
10
11
13
14
15
O
O
ePWM-14 Output A (High-res available on ePWM1-8)
FSITX-A Data Output 0
FSITXA_D0
FSIRXG_CLK
O
I
FSIRX-G Input Clock
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
www.ti.com
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
Table 6-1. Pin Attributes (continued)
MUX
POSITION
PIN
SIGNAL NAME
337
176
DESCRIPTION
TYPE
I/O
O
I/O
O
I/O
I
GPIO27
0, 4, 8, 12
General-Purpose Input Output 27
Output X-BAR Output 4
OUTPUTXBAR4
EQEP2_STROBE
MFSXB
1, 5
2
eQEP-2 Strobe
3
McBSP-B Transmit Frame Sync
SPI-B Slave Transmit Enable (STE)
SDFM-2 Channel 2 Clock Input
PMBus-A Control Signal
SPIB_STEn
SD2_C2
6
7
L1
28
PMBUSA_CTL
EMIF1_DQM3
ESC_MDIO_DATA
EPWM14B
9
I
10
O
I/O
O
O
I
External memory interface 1 Input/output mask for byte 3
EtherCAT MDIO Data
11
13
ePWM-14 Output B (High-res available on ePWM1-8)
FSITX-A Output Clock
FSITXA_CLK
FSIRXH_D0
GPIO28
14
15
FSIRX-H Data Input 0
0, 4, 8, 12
I/O
I
General-Purpose Input Output 28
SCI-A Receive Data
SCIA_RX
1
EMIF1_CS4n
OUTPUTXBAR5
EQEP3_A
2
O
O
I
External memory interface 1 chip select 4
Output X-BAR Output 5
5
6
V11
64
eQEP-3 Input A
SD2_D3
7
I
SDFM-2 Channel 3 Data Input
External memory interface 1 chip select 2
ePWM-15 Output A (High-res available on ePWM1-8)
FSIRX-H Data Input 1
EMIF1_CS2n
EPWM15A
9
O
O
I
13
FSIRXH_D1
GPIO29
15
0, 4, 8, 12
I/O
O
O
O
I
General-Purpose Input Output 29
SCI-A Transmit Data
SCIA_TX
1
EMIF1_SDCKE
OUTPUTXBAR6
EQEP3_B
2
External memory interface 1 SDRAM clock enable
Output X-BAR Output 6
5
6
eQEP-3 Input B
SD2_C3
7
I
SDFM-2 Channel 3 Clock Input
External memory interface 1 chip select 3
EtherCAT LatchSignal Input 0
EtherCAT I2C Data
W11
65
EMIF1_CS3n
ESC_LATCH0
ESC_I2C_SDA
EPWM15B
9
O
I
10
11
I/OC
O
O
I
13
ePWM-15 Output B (High-res available on ePWM1-8)
EtherCAT SyncSignal Output 0
FSIRX-H Input Clock
ESC_SYNC0
FSIRXH_CLK
GPIO30
14
15
0, 4, 8, 12
I/O
I
General-Purpose Input Output 30
CAN-A Receive
CANA_RX
1
2
EMIF1_CLK
MCAN_RX
O
I
External memory interface 1 clock
CAN/CAN-FD Receive
3
OUTPUTXBAR7
EQEP3_STROBE
SD2_D4
5
O
I/O
I
Output X-BAR Output 7
6
eQEP-3 Strobe
7
T11
63
SDFM-2 Channel 4 Data Input
External memory interface 1 chip select 4
EtherCAT LatchSignal Input 1
EtherCAT I2C Clock
EMIF1_CS4n
ESC_LATCH1
ESC_I2C_SCL
EPWM16A
9
O
I
10
11
13
14
15
I/OC
O
O
I/O
ePWM-16 Output A (High-res available on ePWM1-8)
EtherCAT SyncSignal Output 1
SPI-D Slave In, Master Out (SIMO)
ESC_SYNC1
SPID_SIMO
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Product Folder Links: TMS320F28388D TMS320F28386D TMS320F28386D-Q1 TMS320F28384D
TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
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Table 6-1. Pin Attributes (continued)
MUX
POSITION
PIN
TYPE
SIGNAL NAME
GPIO31
337
176
DESCRIPTION
0, 4, 8, 12
I/O
O
General-Purpose Input Output 31
CAN-A Transmit
CANA_TX
1
EMIF1_WEn
MCAN_TX
2
O
External memory interface 1 write enable
CAN/CAN-FD Transmit
3
O
OUTPUTXBAR8
EQEP3_INDEX
SD2_C4
5
O
Output X-BAR Output 8
6
I/O
I
eQEP-3 Index
U11
66
7
SDFM-2 Channel 4 Clock Input
External memory interface 1 read not write
I2C-A Open-Drain Bidirectional Data
CM-I2C-A Open-Drain Bidirectional Data
EMIF1_RNW
I2CA_SDA
9
O
10
I/OD
I/OD
O
CM-I2CA_SDA
EPWM16B
11
13
ePWM-16 Output B (High-res available on ePWM1-8)
SPI-D Slave Out, Master In (SOMI)
General-Purpose Input Output 32
I2C-A Open-Drain Bidirectional Data
External memory interface 1 chip select 0
SPI-A Slave In, Master Out (SIMO)
CLB Output X-BAR Output 1
SPID_SOMI
GPIO32
15
I/O
I/O
I/OD
O
0, 4, 8, 12
I2CA_SDA
1
EMIF1_CS0n
SPIA_SIMO
CLB_OUTPUTXBAR1
EMIF1_OEn
I2CA_SCL
2
3
I/O
O
7
U13
67
9
O
External memory interface 1 output enable
I2C-A Open-Drain Bidirectional Clock
CM-I2C-A Open-Drain Bidirectional Clock
SPI-D Clock
10
I/OD
I/OD
I/O
I/O
I/OD
O
CM-I2CA_SCL
SPID_CLK
11
15
GPIO33
0, 4, 8, 12
General-Purpose Input Output 33
I2C-A Open-Drain Bidirectional Clock
External memory interface 1 read not write
SPI-A Slave Out, Master In (SOMI)
CLB Output X-BAR Output 2
I2CA_SCL
1
EMIF1_RNW
SPIA_SOMI
CLB_OUTPUTXBAR2
EMIF1_BA0
SPID_STEn
GPIO34
2
3
T13
69
I/O
O
7
9
O
External memory interface 1 bank address 0
SPI-D Slave Transmit Enable (STE)
General-Purpose Input Output 34
Output X-BAR Output 1
15
I/O
I/O
O
0, 4, 8, 12
OUTPUTXBAR1
EMIF1_CS2n
SPIA_CLK
1
2
O
External memory interface 1 chip select 2
SPI-A Clock
3
I/O
I/OD
O
I2CB_SDA
6
I2C-B Open-Drain Bidirectional Data
CLB Output X-BAR Output 3
CLB_OUTPUTXBAR3
EMIF1_BA1
ESC_LATCH0
ENET_MII_CRS
SCIA_TX
7
U14
70
9
O
External memory interface 1 bank address 1
EtherCAT LatchSignal Input 0
10
11
13
14
I
I
EMAC MII carrier sense
O
SCI-A Transmit Data
ESC_SYNC0
O
EtherCAT SyncSignal Output 0
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
Table 6-1. Pin Attributes (continued)
MUX
POSITION
PIN
SIGNAL NAME
337
176
DESCRIPTION
TYPE
I/O
I
GPIO35
0, 4, 8, 12
General-Purpose Input Output 35
SCI-A Receive Data
SCIA_RX
1
EMIF1_CS3n
SPIA_STEn
I2CB_SCL
2
O
I/O
I/OD
O
O
I
External memory interface 1 chip select 3
SPI-A Slave Transmit Enable (STE)
I2C-B Open-Drain Bidirectional Clock
CLB Output X-BAR Output 4
External memory interface 1 address line 0
EtherCAT LatchSignal Input 1
EMAC MII collision detect
3
6
T14
71
CLB_OUTPUTXBAR4
EMIF1_A0
7
9
ESC_LATCH1
ENET_MII_COL
ESC_SYNC1
GPIO36
10
11
I
14
O
I/O
O
I
EtherCAT SyncSignal Output 1
General-Purpose Input Output 36
SCI-A Transmit Data
0, 4, 8, 12
SCIA_TX
1
EMIF1_WAIT
CANA_RX
2
External memory interface 1 Asynchronous SRAM WAIT
CAN-A Receive
6
I
V16
83
CLB_OUTPUTXBAR5
EMIF1_A1
7
O
O
I
CLB Output X-BAR Output 5
External memory interface 1 address line 1
CAN/CAN-FD Receive
9
MCAN_RX
10
SD1_D1
13
I
SDFM-1 Channel 1 Data Input
General-Purpose Input Output 37
Output X-BAR Output 2
GPIO37
0, 4, 8, 12
I/O
O
O
O
O
O
O
I
OUTPUTXBAR2
EMIF1_OEn
CANA_TX
1
2
External memory interface 1 output enable
CAN-A Transmit
6
U16
84
CLB_OUTPUTXBAR6
EMIF1_A2
7
CLB Output X-BAR Output 6
External memory interface 1 address line 2
CAN/CAN-FD Transmit
9
MCAN_TX
10
SD1_D2
13
SDFM-1 Channel 2 Data Input
General-Purpose Input Output 38
External memory interface 1 address line 0
SCI-C Transmit Data
GPIO38
0, 4, 8, 12
I/O
O
O
O
O
O
EMIF1_A0
2
5
6
7
9
SCIC_TX
CANB_TX
CAN-B Transmit
CLB_OUTPUTXBAR7
EMIF1_A3
CLB Output X-BAR Output 7
External memory interface 1 address line 3
T16
85
EMAC MII receive data valid (or) RMII carrier sense/
receive data valid
ENET_MII_RX_DV
10
I
ENET_MII_CRS
SD1_D3
11
I
I
EMAC MII carrier sense
13
SDFM-1 Channel 3 Data Input
General-Purpose Input Output 39
External memory interface 1 address line 1
SCI-C Receive Data
GPIO39
0, 4, 8, 12
I/O
O
I
EMIF1_A1
2
5
SCIC_RX
CANB_RX
6
I
CAN-B Receive
CLB_OUTPUTXBAR8
EMIF1_A4
7
W17
86
O
O
I
CLB Output X-BAR Output 8
External memory interface 1 address line 4
EMAC MII / RMII receive error
EMAC MII collision detect
9
ENET_MII_RX_ERR
ENET_MII_COL
SD1_D4
10
11
13
I
I
SDFM-1 Channel 4 Data Input
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
www.ti.com
Table 6-1. Pin Attributes (continued)
MUX
POSITION
PIN
TYPE
SIGNAL NAME
GPIO40
337
176
DESCRIPTION
0, 4, 8, 12
I/O
O
General-Purpose Input Output 40
External memory interface 1 address line 2
I2C-B Open-Drain Bidirectional Data
EMAC MII carrier sense
EMIF1_A2
2
I2CB_SDA
6
V17
87
I/OD
I
ENET_MII_CRS
ESC_I2C_SDA
GPIO41
11
14
I/OC
I/O
O
EtherCAT I2C Data
0, 4, 8, 12
General-Purpose Input Output 41
External memory interface 1 address line 3
I2C-B Open-Drain Bidirectional Clock
EMAC REVMII MDIO reset
EMIF1_A3
2
I2CB_SCL
6
I/OD
I
U17
D19
C19
89
ENET_REVMII_MDIO_RST
ENET_MII_COL
ESC_I2C_SCL
GPIO42
10
11
I
EMAC MII collision detect
14
0, 4, 8, 12
6
I/OC
I/O
I/OD
EtherCAT I2C Clock
General-Purpose Input Output 42
I2C-A Open-Drain Bidirectional Data
I2CA_SDA
EMAC management data clock, Output in MII/RMII
modes, Input in RevMII mode
ENET_MDIO_CLK
10
I/O
130
UARTA_TX
SCIA_TX
11
I/O
O
UART-A Serial Data Transmit
SCI-A Transmit Data
15
USB0DM
ALT
O
USB-0 PHY differential data
General-Purpose Input Output 43
I2C-A Open-Drain Bidirectional Clock
EMAC management data
GPIO43
0, 4, 8, 12
I/O
I/OD
I/O
I/O
I
I2CA_SCL
6
ENET_MDIO_DATA
UARTA_RX
SCIA_RX
10
131
11
UART-A Serial Data Receive
SCI-A Receive Data
15
USB0DP
ALT
O
USB-0 PHY differential data
General-Purpose Input Output 44
External memory interface 1 address line 4
EMAC MII transmit clock
GPIO44
0, 4, 8, 12
I/O
O
EMIF1_A4
2
K18
K19
113
115
ENET_MII_TX_CLK
ESC_TX1_CLK
GPIO45
11
I
14
I
EtherCAT MII Transmit-1 Clock
General-Purpose Input Output 45
External memory interface 1 address line 5
EMAC MII / RMII transmit enable
EtherCAT MII Transmit-1 Enable
General-Purpose Input Output 46
External memory interface 1 address line 6
SCI-D Receive Data
0, 4, 8, 12
I/O
O
EMIF1_A5
2
ENET_MII_TX_EN
ESC_TX1_ENA
GPIO46
11
O
14
I/O
I/O
O
0, 4, 8, 12
EMIF1_A6
2
SCID_RX
6
E19
E18
128
129
I
ENET_MII_TX_ERR
ESC_MDIO_CLK
GPIO47
11
O
EMAC MII transmit error
14
O
EtherCAT MDIO Clock
0, 4, 8, 12
I/O
O
General-Purpose Input Output 47
External memory interface 1 address line 7
SCI-D Transmit Data
EMIF1_A7
2
6
SCID_TX
O
ENET_PPS0
ESC_MDIO_DATA
11
14
O
EMAC Pulse Per Second Output 0
EtherCAT MDIO Data
I/O
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
www.ti.com
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
Table 6-1. Pin Attributes (continued)
MUX
POSITION
PIN
TYPE
SIGNAL NAME
337
176
DESCRIPTION
GPIO48
0, 4, 8, 12
I/O
O
O
O
I
General-Purpose Input Output 48
Output X-BAR Output 3
OUTPUTXBAR3
EMIF1_A8
SCIA_TX
1
2
External memory interface 1 address line 8
SCI-A Transmit Data
6
R16
90
SD1_D1
7
SDFM-1 Channel 1 Data Input
EMAC Pulse Per Second Output 1
EtherCAT PHY Clock
ENET_PPS1
ESC_PHY_CLK
GPIO49
11
O
O
I/O
O
O
I
14
0, 4, 8, 12
General-Purpose Input Output 49
Output X-BAR Output 4
OUTPUTXBAR4
EMIF1_A9
SCIA_RX
1
2
External memory interface 1 address line 9
SCI-A Receive Data
6
SD1_C1
7
R17
93
I
SDFM-1 Channel 1 Clock Input
External memory interface 1 address line 5
EMAC MII receive clock
EMIF1_A5
ENET_MII_RX_CLK
SD2_D1
9
O
I
11
13
I
SDFM-2 Channel 1 Data Input
FSITX-A Data Output 0
FSITXA_D0
GPIO50
14
O
I/O
I
0, 4, 8, 12
General-Purpose Input Output 50
eQEP-1 Input A
EQEP1_A
1
2
6
7
9
EMIF1_A10
SPIC_SIMO
SD1_D2
O
I/O
I
External memory interface 1 address line 10
SPI-C Slave In, Master Out (SIMO)
SDFM-1 Channel 2 Data Input
External memory interface 1 address line 6
R18
94
EMIF1_A6
O
EMAC MII receive data valid (or) RMII carrier sense/
receive data valid
ENET_MII_RX_DV
11
I
SD2_D2
13
I
O
I/O
I
SDFM-2 Channel 2 Data Input
FSITX-A Data Output 1
FSITXA_D1
GPIO51
14
0, 4, 8, 12
General-Purpose Input Output 51
eQEP-1 Input B
EQEP1_B
1
EMIF1_A11
SPIC_SOMI
SD1_C2
2
O
I/O
I
External memory interface 1 address line 11
SPI-C Slave Out, Master In (SOMI)
SDFM-1 Channel 2 Clock Input
External memory interface 1 address line 7
EMAC MII / RMII receive error
SDFM-2 Channel 3 Data Input
FSITX-A Output Clock
6
7
R19
95
EMIF1_A7
9
O
I
ENET_MII_RX_ERR
SD2_D3
11
13
I
FSITXA_CLK
GPIO52
14
O
I/O
I/O
O
I/O
I
0, 4, 8, 12
General-Purpose Input Output 52
eQEP-1 Strobe
EQEP1_STROBE
EMIF1_A12
SPIC_CLK
SD1_D3
1
2
External memory interface 1 address line 12
SPI-C Clock
6
7
P16
96
SDFM-1 Channel 3 Data Input
External memory interface 1 address line 8
EMAC MII / RMII receive data 0
SDFM-2 Channel 4 Data Input
FSIRX-A Data Input 0
EMIF1_A8
9
O
I
ENET_MII_RX_DATA0
SD2_D4
11
13
14
I
FSIRXA_D0
I
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Product Folder Links: TMS320F28388D TMS320F28386D TMS320F28386D-Q1 TMS320F28384D
TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
www.ti.com
Table 6-1. Pin Attributes (continued)
MUX
POSITION
PIN
TYPE
SIGNAL NAME
GPIO53
337
176
DESCRIPTION
0, 4, 8, 12
I/O
I/O
I/O
I/O
I/O
I
General-Purpose Input Output 53
eQEP-1 Index
EQEP1_INDEX
EMIF1_D31
EMIF2_D15
SPIC_STEn
SD1_C3
1
2
External memory interface 1 data line 31
External memory interface 2 data line 15
SPI-C Slave Transmit Enable (STE)
SDFM-1 Channel 3 Clock Input
External memory interface 1 address line 9
EMAC MII / RMII receive data 1
SDFM-1 Channel 1 Clock Input
FSIRX-A Data Input 1
3
6
P17
97
7
EMIF1_A9
9
O
I
ENET_MII_RX_DATA1
SD1_C1
11
13
I
FSIRXA_D1
GPIO54
14
I
0, 4, 8, 12
I/O
I/O
I/O
I/O
I
General-Purpose Input Output 54
SPI-A Slave In, Master Out (SIMO)
External memory interface 1 data line 30
External memory interface 2 data line 14
eQEP-2 Input A
SPIA_SIMO
EMIF1_D30
EMIF2_D14
EQEP2_A
1
2
3
5
SCIB_TX
6
O
I
SCI-B Transmit Data
P18
98
SD1_D4
7
SDFM-1 Channel 4 Data Input
External memory interface 1 address line 10
EMAC MII receive data 2
EMIF1_A10
ENET_MII_RX_DATA2
SD1_C2
9
O
I
11
13
I
SDFM-1 Channel 2 Clock Input
FSIRX-A Input Clock
FSIRXA_CLK
SSIA_TX
14
I
15
I/O
I/O
I/O
I/O
I/O
I
SSI-A Serial Data Transmit
GPIO55
0, 4, 8, 12
General-Purpose Input Output 55
SPI-A Slave Out, Master In (SOMI)
External memory interface 1 data line 29
External memory interface 2 data line 13
eQEP-2 Input B
SPIA_SOMI
EMIF1_D29
EMIF2_D13
EQEP2_B
1
2
3
5
SCIB_RX
6
I
SCI-B Receive Data
P19
100
SD1_C4
7
I
SDFM-1 Channel 4 Clock Input
External memory interface 1 data line 0
EMAC MII receive data 3
EMIF1_D0
ENET_MII_RX_DATA3
SD1_C3
9
I/O
I
11
13
14
15
I
SDFM-1 Channel 3 Clock Input
FSITX-B Data Output 0
FSITXB_D0
SSIA_RX
O
I/O
SSI-A Serial Data Receive
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
www.ti.com
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
Table 6-1. Pin Attributes (continued)
MUX
POSITION
PIN
SIGNAL NAME
337
176
DESCRIPTION
TYPE
I/O
I/O
I/O
I/O
I/O
O
GPIO56
0, 4, 8, 12
General-Purpose Input Output 56
SPI-A Clock
SPIA_CLK
1
EMIF1_D28
EMIF2_D12
EQEP2_STROBE
SCIC_TX
2
External memory interface 1 data line 28
External memory interface 2 data line 12
eQEP-2 Strobe
3
5
6
SCI-C Transmit Data
SD2_D1
7
N16
101
I
SDFM-2 Channel 1 Data Input
External memory interface 1 data line 1
I2C-A Open-Drain Bidirectional Data
EMAC MII / RMII transmit enable
SDFM-1 Channel 4 Clock Input
FSITX-B Output Clock
EMIF1_D1
9
I/O
I/OD
O
I2CA_SDA
10
ENET_MII_TX_EN
SD1_C4
11
13
I
FSITXB_CLK
SSIA_CLK
14
O
15
I/O
I/O
I/O
I/O
I/O
I/O
I
SSI-A Clock
GPIO57
0, 4, 8, 12
General-Purpose Input Output 57
SPI-A Slave Transmit Enable (STE)
External memory interface 1 data line 27
External memory interface 2 data line 11
eQEP-2 Index
SPIA_STEn
EMIF1_D27
EMIF2_D11
EQEP2_INDEX
SCIC_RX
1
2
3
5
6
SCI-C Receive Data
N18
102
SD2_C1
7
I
SDFM-2 Channel 1 Clock Input
External memory interface 1 data line 2
I2C-A Open-Drain Bidirectional Clock
EMAC MII transmit error
EMIF1_D2
9
I/O
I/OD
O
I2CA_SCL
10
ENET_MII_TX_ERR
FSITXB_D1
SSIA_FSS
11
14
O
FSITX-B Data Output 1
15
I/O
I/O
I
SSI-A Frame Sync
GPIO58
0, 4, 8, 12
General-Purpose Input Output 58
McBSP-A Receive Clock
MCLKRA
1
2
EMIF1_D26
EMIF2_D10
OUTPUTXBAR1
SPIB_CLK
I/O
I/O
O
External memory interface 1 data line 26
External memory interface 2 data line 10
Output X-BAR Output 1
3
5
6
I/O
I
SPI-B Clock
SD2_D2
7
N17
103
SDFM-2 Channel 2 Data Input
External memory interface 1 data line 3
EtherCAT Link-0 Active
EMIF1_D3
9
I/O
O
ESC_LED_LINK0_ACTIVE
ENET_MII_TX_CLK
SD2_C2
10
11
13
14
15
I
EMAC MII transmit clock
I
SDFM-2 Channel 2 Clock Input
FSIRX-B Data Input 0
FSIRXB_D0
SPIA_SIMO
I
I/O
SPI-A Slave In, Master Out (SIMO)
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Product Folder Links: TMS320F28388D TMS320F28386D TMS320F28386D-Q1 TMS320F28384D
TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
www.ti.com
Table 6-1. Pin Attributes (continued)
MUX
POSITION
PIN
TYPE
SIGNAL NAME
GPIO59
337
176
DESCRIPTION
0, 4, 8, 12
I/O
I
General-Purpose Input Output 59
McBSP-A Receive Frame Sync
External memory interface 1 data line 25
External memory interface 2 data line 9
Output X-BAR Output 2
MFSRA
1
EMIF1_D25
EMIF2_D9
2
I/O
I/O
O
3
OUTPUTXBAR2
SPIB_STEn
SD2_C2
5
6
I/O
I
SPI-B Slave Transmit Enable (STE)
SDFM-2 Channel 2 Clock Input
External memory interface 1 data line 4
EtherCAT Link-1 Active
7
M16
104
EMIF1_D4
9
I/O
O
ESC_LED_LINK1_ACTIVE
ENET_MII_TX_DATA0
SD2_C3
10
11
O
EMAC MII / RMII transmit data 0
SDFM-2 Channel 3 Clock Input
FSIRX-B Data Input 1
13
I
FSIRXB_D1
SPIA_SOMI
GPIO60
14
I
15
I/O
I/O
I
SPI-A Slave Out, Master In (SOMI)
General-Purpose Input Output 60
McBSP-B Receive Clock
0, 4, 8, 12
MCLKRB
1
EMIF1_D24
EMIF2_D8
2
I/O
I/O
O
External memory interface 1 data line 24
External memory interface 2 data line 8
Output X-BAR Output 3
3
OUTPUTXBAR3
SPIB_SIMO
SD2_D3
5
6
I/O
I
SPI-B Slave In, Master Out (SIMO)
SDFM-2 Channel 3 Data Input
External memory interface 1 data line 5
EtherCAT Error LED
7
M17
105
EMIF1_D5
9
I/O
O
ESC_LED_ERR
ENET_MII_TX_DATA1
SD2_C4
10
11
O
EMAC MII / RMII transmit data 1
SDFM-2 Channel 4 Clock Input
FSIRX-B Input Clock
13
I
FSIRXB_CLK
SPIA_CLK
14
I
15
I/O
I/O
I
SPI-A Clock
GPIO61
0, 4, 8, 12
General-Purpose Input Output 61
McBSP-B Receive Frame Sync
External memory interface 1 data line 23
External memory interface 2 data line 7
Output X-BAR Output 4
MFSRB
1
2
EMIF1_D23
EMIF2_D7
I/O
I/O
O
3
OUTPUTXBAR4
SPIB_SOMI
SD2_C3
5
6
I/O
I
SPI-B Slave Out, Master In (SOMI)
SDFM-2 Channel 3 Clock Input
External memory interface 1 data line 6
EtherCAT Run LED
L16
107
7
EMIF1_D6
9
I/O
O
ESC_LED_RUN
ENET_MII_TX_DATA2
CANA_RX
10
11
14
15
O
EMAC MII transmit data 2
I
CAN-A Receive
SPIA_STEn
I/O
SPI-A Slave Transmit Enable (STE)
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
www.ti.com
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
Table 6-1. Pin Attributes (continued)
MUX
POSITION
PIN
SIGNAL NAME
337
176
DESCRIPTION
TYPE
I/O
I
GPIO62
0, 4, 8, 12
General-Purpose Input Output 62
SCI-C Receive Data
SCIC_RX
1
EMIF1_D22
EMIF2_D6
2
I/O
I/O
I
External memory interface 1 data line 22
External memory interface 2 data line 6
eQEP-3 Input A
3
EQEP3_A
5
CANA_RX
6
J17
108
I
CAN-A Receive
SD2_D4
7
I
SDFM-2 Channel 4 Data Input
External memory interface 1 data line 7
EtherCAT State Run
EMIF1_D7
9
I/O
O
ESC_LED_STATE_RUN
ENET_MII_TX_DATA3
CANA_TX
10
11
O
EMAC MII transmit data 3
14
O
CAN-A Transmit
GPIO63
0, 4, 8, 12
I/O
O
General-Purpose Input Output 63
SCI-C Transmit Data
SCIC_TX
1
EMIF1_D21
EMIF2_D5
2
I/O
I/O
I
External memory interface 1 data line 21
External memory interface 2 data line 5
eQEP-3 Input B
3
EQEP3_B
5
CANA_TX
6
O
CAN-A Transmit
J16
109
SD2_C4
7
I
SDFM-2 Channel 4 Clock Input
SSI-A Serial Data Transmit
EMAC MII / RMII receive data 0
SDFM-1 Channel 1 Data Input
EtherCAT MII Receive-1 Data-0
SPI-B Slave In, Master Out (SIMO)
General-Purpose Input Output 64
External memory interface 1 data line 20
External memory interface 2 data line 4
eQEP-3 Strobe
SSIA_TX
9
I/O
I
ENET_MII_RX_DATA0
SD1_D1
11
13
I
ESC_RX1_DATA0
SPIB_SIMO
GPIO64
14
I
15
I/O
I/O
I/O
I/O
I/O
I
0, 4, 8, 12
EMIF1_D20
EMIF2_D4
2
3
5
6
9
EQEP3_STROBE
SCIA_RX
SCI-A Receive Data
SSIA_RX
I/O
SSI-A Serial Data Receive
L17
110
EMAC MII receive data valid (or) RMII carrier sense/
receive data valid
ENET_MII_RX_DV
10
I
ENET_MII_RX_DATA1
SD1_C1
11
I
I
EMAC MII / RMII receive data 1
SDFM-1 Channel 1 Clock Input
EtherCAT MII Receive-1 Data-1
SPI-B Slave Out, Master In (SOMI)
General-Purpose Input Output 65
External memory interface 1 data line 19
External memory interface 2 data line 3
eQEP-3 Index
13
ESC_RX1_DATA1
SPIB_SOMI
14
I
15
I/O
I/O
I/O
I/O
I/O
O
I/O
I
GPIO65
0, 4, 8, 12
EMIF1_D19
2
3
EMIF2_D3
EQEP3_INDEX
SCIA_TX
5
6
SCI-A Transmit Data
SSIA_CLK
9
K16
111
SSI-A Clock
ENET_MII_RX_ERR
ENET_MII_RX_DATA2
SD1_D2
10
11
13
14
15
EMAC MII / RMII receive error
EMAC MII receive data 2
I
I
SDFM-1 Channel 2 Data Input
EtherCAT MII Receive-1 Data-2
SPI-B Clock
ESC_RX1_DATA2
SPIB_CLK
I
I/O
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Product Folder Links: TMS320F28388D TMS320F28386D TMS320F28386D-Q1 TMS320F28384D
TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
www.ti.com
Table 6-1. Pin Attributes (continued)
MUX
POSITION
PIN
TYPE
SIGNAL NAME
GPIO66
337
176
DESCRIPTION
0, 4, 8, 12
I/O
I/O
I/O
I/OD
I/O
I
General-Purpose Input Output 66
External memory interface 1 data line 18
External memory interface 2 data line 2
I2C-B Open-Drain Bidirectional Data
SSI-A Frame Sync
EMIF1_D18
2
EMIF2_D2
3
I2CB_SDA
6
SSIA_FSS
9
K17
112
ENET_MII_RX_DATA0
ENET_MII_RX_DATA3
SD1_C2
10
EMAC MII / RMII receive data 0
EMAC MII receive data 3
11
I
13
I
SDFM-1 Channel 2 Clock Input
EtherCAT MII Receive-1 Data-3
SPI-B Slave Transmit Enable (STE)
General-Purpose Input Output 67
External memory interface 1 data line 17
External memory interface 2 data line 1
EMAC MII receive clock
ESC_RX1_DATA3
SPIB_STEn
14
I
15
I/O
I/O
I/O
I/O
I
GPIO67
0, 4, 8, 12
EMIF1_D17
2
EMIF2_D1
3
B19
132
ENET_MII_RX_CLK
ENET_REVMII_MDIO_RST
SD1_D3
10
11
I
EMAC REVMII MDIO reset
13
I
SDFM-1 Channel 3 Data Input
General-Purpose Input Output 68
External memory interface 1 data line 16
External memory interface 2 data line 0
GPIO68
0, 4, 8, 12
I/O
I/O
I/O
EMIF1_D16
2
3
EMIF2_D0
C18
133
EMAC PHY interrupt, Input in MII/RMII mode, Output in
RevMII mode
ENET_MII_INTR
11
I/O
SD1_C3
13
I
I
SDFM-1 Channel 3 Clock Input
EtherCAT PHY-1 Link Status
General-Purpose Input Output 69
External memory interface 1 data line 15
I2C-B Open-Drain Bidirectional Clock
EMAC MII / RMII transmit enable
EMAC MII receive clock
ESC_PHY1_LINKSTATUS
GPIO69
14
0, 4, 8, 12
I/O
I/O
I/OD
O
EMIF1_D15
I2CB_SCL
2
6
ENET_MII_TX_EN
ENET_MII_RX_CLK
SD1_D4
10
B18
134
11
I
13
I
SDFM-1 Channel 4 Data Input
EtherCAT MII Receive-1 Clock
SPI-C Slave In, Master Out (SIMO)
General-Purpose Input Output 70
External memory interface 1 data line 14
CAN-A Receive
ESC_RX1_CLK
SPIC_SIMO
GPIO70
14
I
15
I/O
I/O
I/O
I
0, 4, 8, 12
EMIF1_D14
CANA_RX
2
5
6
9
SCIB_TX
O
SCI-B Transmit Data
MCAN_RX
I
CAN/CAN-FD Receive
A17
135
EMAC MII receive data valid (or) RMII carrier sense/
receive data valid
ENET_MII_RX_DV
11
I
SD1_C4
13
14
15
I
I
SDFM-1 Channel 4 Clock Input
EtherCAT MII Receive-1 Data Valid
SPI-C Slave Out, Master In (SOMI)
ESC_RX1_DV
SPIC_SOMI
I/O
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
www.ti.com
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
Table 6-1. Pin Attributes (continued)
MUX
POSITION
PIN
SIGNAL NAME
337
176
DESCRIPTION
TYPE
I/O
I/O
O
GPIO71
0, 4, 8, 12
General-Purpose Input Output 71
External memory interface 1 data line 13
CAN-A Transmit
EMIF1_D13
2
CANA_TX
5
SCIB_RX
6
I
SCI-B Receive Data
MCAN_TX
9
B17
136
O
CAN/CAN-FD Transmit
ENET_MII_RX_DATA0
ENET_MII_RX_ERR
ESC_RX1_ERR
SPIC_CLK
10
I
EMAC MII / RMII receive data 0
EMAC MII / RMII receive error
EtherCAT MII Receive-1 Error
SPI-C Clock
11
I
14
I
15
I/O
I/O
I/O
O
GPIO72
0, 4, 8, 12
General-Purpose Input Output 72
External memory interface 1 data line 12
CAN-B Transmit
EMIF1_D12
2
CANB_TX
5
SCIC_TX
6
O
SCI-C Transmit Data
B16
139
ENET_MII_RX_DATA1
ENET_MII_TX_DATA3
ESC_TX1_DATA3
SPIC_STEn
10
I
EMAC MII / RMII receive data 1
EMAC MII transmit data 3
11
O
14
O
EtherCAT MII Transmit-1 Data-3
SPI-C Slave Transmit Enable (STE)
General-Purpose Input Output 73
External memory interface 1 data line 11
15
0, 4, 8, 12
2
I/O
I/O
I/O
GPIO73
EMIF1_D11
External Clock Output. This pin outputs a divided-down
version of a chosen clock signal from within the device.
XCLKOUT
3
O
CANB_RX
5
I
I
CAN-B Receive
A16
140
SCIC_RX
6
SCI-C Receive Data
ENET_RMII_CLK
ENET_MII_TX_DATA2
SD2_D2
10
I/O
O
I
EMAC RMII clock
11
EMAC MII transmit data 2
13
SDFM-2 Channel 2 Data Input
EtherCAT MII Transmit-1 Data-2
General-Purpose Input Output 74
External memory interface 1 data line 10
CAN/CAN-FD Transmit
ESC_TX1_DATA2
GPIO74
14
O
I/O
I/O
O
O
I
0, 4, 8, 12
EMIF1_D10
2
MCAN_TX
9
C17
D16
C16
141
142
143
ENET_MII_TX_DATA1
SD2_C2
11
EMAC MII / RMII transmit data 1
SDFM-2 Channel 2 Clock Input
EtherCAT MII Transmit-1 Data-1
General-Purpose Input Output 75
External memory interface 1 data line 9
CAN/CAN-FD Receive
13
ESC_TX1_DATA1
GPIO75
14
O
I/O
I/O
I
0, 4, 8, 12
EMIF1_D9
2
MCAN_RX
9
ENET_MII_TX_DATA0
SD2_D3
11
O
I
EMAC MII / RMII transmit data 0
SDFM-2 Channel 3 Data Input
EtherCAT MII Transmit-1 Data-0
General-Purpose Input Output 76
External memory interface 1 data line 8
SCI-D Transmit Data
13
ESC_TX1_DATA0
GPIO76
14
O
I/O
I/O
O
I
0, 4, 8, 12
EMIF1_D8
2
SCID_TX
6
ENET_MII_RX_ERR
SD2_C3
10
13
14
EMAC MII / RMII receive error
SDFM-2 Channel 3 Clock Input
EtherCAT PHY Active Low Reset
I
ESC_PHY_RESETn
O
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
www.ti.com
Table 6-1. Pin Attributes (continued)
MUX
POSITION
PIN
TYPE
SIGNAL NAME
GPIO77
337
176
DESCRIPTION
0, 4, 8, 12
I/O
I/O
I
General-Purpose Input Output 77
External memory interface 1 data line 7
SCI-D Receive Data
EMIF1_D7
SCID_RX
2
6
A15
144
SD2_D4
13
I
SDFM-2 Channel 4 Data Input
EtherCAT MII Receive-0 Clock
General-Purpose Input Output 78
External memory interface 1 data line 6
eQEP-2 Input A
ESC_RX0_CLK
GPIO78
14
I
0, 4, 8, 12
I/O
I/O
I
EMIF1_D6
EQEP2_A
SD2_C4
2
6
B15
C15
145
146
13
I
SDFM-2 Channel 4 Clock Input
EtherCAT MII Receive-0 Data Valid
General-Purpose Input Output 79
External memory interface 1 data line 5
eQEP-2 Input B
ESC_RX0_DV
GPIO79
14
I
0, 4, 8, 12
I/O
I/O
I
EMIF1_D5
EQEP2_B
SD2_D1
2
6
13
I
SDFM-2 Channel 1 Data Input
EtherCAT MII Receive-0 Error
General-Purpose Input Output 80
External memory interface 1 data line 4
eQEP-2 Strobe
ESC_RX0_ERR
GPIO80
14
I
0, 4, 8, 12
I/O
I/O
I/O
I
EMIF1_D4
EQEP2_STROBE
SD2_C1
2
6
D15
A14
148
149
13
SDFM-2 Channel 1 Clock Input
EtherCAT MII Receive-0 Data-0
General-Purpose Input Output 81
External memory interface 1 data line 3
eQEP-2 Index
ESC_RX0_DATA0
GPIO81
14
I
0, 4, 8, 12
I/O
I/O
I/O
I
EMIF1_D3
EQEP2_INDEX
ESC_RX0_DATA1
GPIO82
2
6
14
EtherCAT MII Receive-0 Data-1
General-Purpose Input Output 82
External memory interface 1 data line 2
EtherCAT MII Receive-0 Data-2
General-Purpose Input Output 83
External memory interface 1 data line 1
EtherCAT MII Receive-0 Data-3
General-Purpose Input Output 84
SCI-A Transmit Data
0, 4, 8, 12
I/O
I/O
I
EMIF1_D2
ESC_RX0_DATA2
GPIO83
2
B14
C14
150
151
14
0, 4, 8, 12
I/O
I/O
I
EMIF1_D1
ESC_RX0_DATA3
GPIO84
2
14
0, 4, 8, 12
I/O
O
O
I/O
I/O
O
I/O
I/O
I
SCIA_TX
5
MDXB
6
McBSP-B Transmit Serial Data
UART-A Serial Data Transmit
EtherCAT MII Transmit-0 Enable
McBSP-A Transmit Serial Data
General-Purpose Input Output 85
External memory interface 1 data line 0
SCI-A Receive Data
A11
154
UARTA_TX
ESC_TX0_ENA
MDXA
11
14
15
GPIO85
0, 4, 8, 12
EMIF1_D0
SCIA_RX
2
5
MDRB
6
B11
155
I
McBSP-B Receive Serial Data
UART-A Serial Data Receive
EtherCAT MII Transmit-0 Clock
McBSP-A Receive Serial Data
UARTA_RX
ESC_TX0_CLK
MDRA
11
14
15
I/O
I
I
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
www.ti.com
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
Table 6-1. Pin Attributes (continued)
MUX
POSITION
PIN
SIGNAL NAME
337
176
DESCRIPTION
TYPE
I/O
O
GPIO86
0, 4, 8, 12
General-Purpose Input Output 86
EMIF1_A13
EMIF1_CAS
SCIB_TX
2
External memory interface 1 address line 13
External memory interface 1 column address strobe
SCI-B Transmit Data
3
O
5
C11
156
O
MCLKXB
6
O
McBSP-B Transmit Clock
ESC_PHY0_LINKSTATUS
MCLKXA
14
I
EtherCAT PHY-0 Link Status
15
O
McBSP-A Transmit Clock
GPIO87
0, 4, 8, 12
I/O
O
General-Purpose Input Output 87
EMIF1_A14
EMIF1_RAS
SCIB_RX
2
External memory interface 1 address line 14
External memory interface 1 row address strobe
SCI-B Receive Data
3
O
5
I
D11
157
MFSXB
6
O
McBSP-B Transmit Frame Sync
EMIF1_DQM3
ESC_TX0_DATA0
MFSXA
9
O
External memory interface 1 Input/output mask for byte 3
EtherCAT MII Transmit-0 Data-0
14
O
15
O
McBSP-A Transmit Frame Sync
GPIO88
0, 4, 8, 12
I/O
O
General-Purpose Input Output 88
EMIF1_A15
EMIF1_DQM0
EMIF1_DQM1
ESC_TX0_DATA1
GPIO89
2
External memory interface 1 address line 15
External memory interface 1 Input/output mask for byte 0
External memory interface 1 Input/output mask for byte 1
EtherCAT MII Transmit-0 Data-1
3
C6
D6
170
171
O
9
O
14
O
0, 4, 8, 12
I/O
O
General-Purpose Input Output 89
EMIF1_A16
EMIF1_DQM1
SCIC_TX
2
External memory interface 1 address line 16
External memory interface 1 Input/output mask for byte 1
SCI-C Transmit Data
3
O
6
O
EMIF1_CAS
ESC_TX0_DATA2
GPIO90
9
O
External memory interface 1 column address strobe
EtherCAT MII Transmit-0 Data-2
14
O
0, 4, 8, 12
I/O
O
General-Purpose Input Output 90
EMIF1_A17
EMIF1_DQM2
SCIC_RX
2
External memory interface 1 address line 17
External memory interface 1 Input/output mask for byte 2
SCI-C Receive Data
3
O
A5
172
6
I
EMIF1_RAS
ESC_TX0_DATA3
GPIO91
9
O
External memory interface 1 row address strobe
EtherCAT MII Transmit-0 Data-3
14
O
0, 4, 8, 12
I/O
O
General-Purpose Input Output 91
EMIF1_A18
EMIF1_DQM3
I2CA_SDA
2
3
External memory interface 1 address line 18
External memory interface 1 Input/output mask for byte 3
I2C-A Open-Drain Bidirectional Data
External memory interface 1 Input/output mask for byte 2
PMBus-A Open-Drain Bidirectional Clock
SSI-A Serial Data Transmit
O
6
I/OD
O
EMIF1_DQM2
PMBUSA_SCL
SSIA_TX
9
B5
173
10
11
13
14
15
I/OD
I/O
I
FSIRXF_D0
CLB_OUTPUTXBAR1
SPID_SIMO
FSIRX-F Data Input 0
O
CLB Output X-BAR Output 1
I/O
SPI-D Slave In, Master Out (SIMO)
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
www.ti.com
Table 6-1. Pin Attributes (continued)
MUX
POSITION
PIN
TYPE
SIGNAL NAME
GPIO92
337
176
DESCRIPTION
0, 4, 8, 12
I/O
O
General-Purpose Input Output 92
EMIF1_A19
2
External memory interface 1 address line 19
External memory interface 1 bank address 1
I2C-A Open-Drain Bidirectional Clock
EMIF1_BA1
3
O
I2CA_SCL
6
I/OD
O
EMIF1_DQM0
PMBUSA_SDA
SSIA_RX
9
External memory interface 1 Input/output mask for byte 0
PMBus-A Open-Drain Bidirectional Data
SSI-A Serial Data Receive
A4
174
10
I/OD
I/O
I
11
FSIRXF_D1
13
FSIRX-F Data Input 1
CLB_OUTPUTXBAR2
SPID_SOMI
GPIO93
14
O
CLB Output X-BAR Output 2
SPI-D Slave Out, Master In (SOMI)
General-Purpose Input Output 93
External memory interface 1 bank address 0
SCI-D Transmit Data
15
I/O
I/O
O
0, 4, 8, 12
EMIF1_BA0
3
SCID_TX
6
O
PMBUSA_ALERT
SSIA_CLK
10
I/OD
I/O
I
PMBus-A Open-Drain Bidirectional Alert Signal
SSI-A Clock
B4
175
11
FSIRXF_CLK
CLB_OUTPUTXBAR3
SPID_CLK
13
FSIRX-F Input Clock
14
O
CLB Output X-BAR Output 3
SPI-D Clock
15
I/O
I/O
I
GPIO94
0, 4, 8, 12
General-Purpose Input Output 94
SCI-D Receive Data
SCID_RX
6
EMIF1_BA1
9
O
External memory interface 1 bank address 1
PMBus-A Control Signal
PMBUSA_CTL
SSIA_FSS
10
I
A3
176
11
I/O
I
SSI-A Frame Sync
FSIRXG_D0
CLB_OUTPUTXBAR4
SPID_STEn
13
FSIRX-G Data Input 0
14
O
CLB Output X-BAR Output 4
SPI-D Slave Transmit Enable (STE)
General-Purpose Input Output 95
External memory interface 2 address line 12
FSIRX-G Data Input 1
15
I/O
I/O
O
GPIO95
0, 4, 8, 12
EMIF2_A12
3
B3
C3
FSIRXG_D1
CLB_OUTPUTXBAR5
GPIO96
13
I
14
O
CLB Output X-BAR Output 5
General-Purpose Input Output 96
External memory interface 2 Input/output mask for byte 1
eQEP-1 Input A
0, 4, 8, 12
I/O
O
EMIF2_DQM1
EQEP1_A
3
5
I
FSIRXG_CLK
CLB_OUTPUTXBAR6
GPIO97
13
I
FSIRX-G Input Clock
14
O
CLB Output X-BAR Output 6
General-Purpose Input Output 97
External memory interface 2 Input/output mask for byte 0
eQEP-1 Input B
0, 4, 8, 12
I/O
O
EMIF2_DQM0
EQEP1_B
3
5
A2
F1
I
FSIRXH_D0
CLB_OUTPUTXBAR7
GPIO98
13
I
FSIRX-H Data Input 0
14
O
CLB Output X-BAR Output 7
General-Purpose Input Output 98
External memory interface 2 address line 0
eQEP-1 Strobe
0, 4, 8, 12
I/O
O
EMIF2_A0
3
5
EQEP1_STROBE
FSIRXH_D1
CLB_OUTPUTXBAR8
I/O
I
13
14
FSIRX-H Data Input 1
O
CLB Output X-BAR Output 8
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
www.ti.com
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
Table 6-1. Pin Attributes (continued)
MUX
POSITION
PIN
TYPE
SIGNAL NAME
337
176
DESCRIPTION
GPIO99
0, 4, 8, 12
I/O
O
General-Purpose Input Output 99
External memory interface 2 address line 1
eQEP-1 Index
EMIF2_A1
EQEP1_INDEX
FSIRXH_CLK
GPIO100
3
G1
17
5
I/O
I
13
FSIRX-H Input Clock
0, 4, 8, 12
I/O
O
General-Purpose Input Output 100
External memory interface 2 address line 2
eQEP-2 Input A
EMIF2_A2
EQEP2_A
3
5
I
H1
H2
H3
J1
SPIC_SIMO
ESC_GPI0
FSITXA_D0
GPIO101
6
I/O
I
SPI-C Slave In, Master Out (SIMO)
EtherCAT General-Purpose Input 0
FSITX-A Data Output 0
10
13
O
0, 4, 8, 12
I/O
O
General-Purpose Input Output 101
External memory interface 2 address line 3
eQEP-2 Input B
EMIF2_A3
EQEP2_B
3
5
I
SPIC_SOMI
ESC_GPI1
FSITXA_D1
GPIO102
6
I/O
I
SPI-C Slave Out, Master In (SOMI)
EtherCAT General-Purpose Input 1
FSITX-A Data Output 1
10
13
O
0, 4, 8, 12
I/O
O
General-Purpose Input Output 102
External memory interface 2 address line 4
eQEP-2 Strobe
EMIF2_A4
EQEP2_STROBE
SPIC_CLK
ESC_GPI2
FSITXA_CLK
GPIO103
3
5
I/O
I/O
I
6
SPI-C Clock
10
EtherCAT General-Purpose Input 2
FSITX-A Output Clock
13
O
0, 4, 8, 12
I/O
O
General-Purpose Input Output 103
External memory interface 2 address line 5
eQEP-2 Index
EMIF2_A5
EQEP2_INDEX
SPIC_STEn
ESC_GPI3
FSIRXA_D0
GPIO104
3
5
I/O
I/O
I
6
SPI-C Slave Transmit Enable (STE)
EtherCAT General-Purpose Input 3
FSIRX-A Data Input 0
10
13
I
0, 4, 8, 12
I/O
I/OD
O
General-Purpose Input Output 104
I2C-A Open-Drain Bidirectional Data
External memory interface 2 address line 6
eQEP-3 Input A
I2CA_SDA
EMIF2_A6
EQEP3_A
1
3
5
I
J2
SCID_TX
6
O
SCI-D Transmit Data
ESC_GPI4
CM-I2CA_SDA
FSIRXA_D1
GPIO105
10
I
EtherCAT General-Purpose Input 4
CM-I2C-A Open-Drain Bidirectional Data
FSIRX-A Data Input 1
11
I/OD
I
13
0, 4, 8, 12
I/O
I/OD
O
General-Purpose Input Output 105
I2C-A Open-Drain Bidirectional Clock
External memory interface 2 address line 7
eQEP-3 Input B
I2CA_SCL
EMIF2_A7
EQEP3_B
1
3
5
I
SCID_RX
6
I
SCI-D Receive Data
J3
ESC_GPI5
CM-I2CA_SCL
FSIRXA_CLK
10
11
13
I
EtherCAT General-Purpose Input 5
CM-I2C-A Open-Drain Bidirectional Clock
FSIRX-A Input Clock
I/OD
I
EMAC management data clock, Output in MII/RMII
modes, Input in RevMII mode
ENET_MDIO_CLK
14
I/O
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
www.ti.com
Table 6-1. Pin Attributes (continued)
MUX
POSITION
PIN
TYPE
SIGNAL NAME
GPIO106
337
176
DESCRIPTION
0, 4, 8, 12
I/O
O
I/O
O
I
General-Purpose Input Output 106
External memory interface 2 address line 8
eQEP-3 Strobe
EMIF2_A8
3
EQEP3_STROBE
SCIC_TX
5
6
L2
SCI-C Transmit Data
ESC_GPI6
10
EtherCAT General-Purpose Input 6
FSITX-B Data Output 0
FSITXB_D0
ENET_MDIO_DATA
GPIO107
13
O
I/O
I/O
O
I/O
I
14
EMAC management data
0, 4, 8, 12
General-Purpose Input Output 107
External memory interface 2 address line 9
eQEP-3 Index
EMIF2_A9
3
EQEP3_INDEX
SCIC_RX
5
6
L3
SCI-C Receive Data
ESC_GPI7
10
I
EtherCAT General-Purpose Input 7
FSITX-B Data Output 1
FSITXB_D1
ENET_REVMII_MDIO_RST
GPIO108
13
O
I
14
EMAC REVMII MDIO reset
General-Purpose Input Output 108
External memory interface 2 address line 10
EtherCAT General-Purpose Input 8
FSITX-B Output Clock
0, 4, 8, 12
I/O
O
I
EMIF2_A10
3
ESC_GPI8
10
13
L4
FSITXB_CLK
O
EMAC PHY interrupt, Input in MII/RMII mode, Output in
RevMII mode
ENET_MII_INTR
14
I/O
GPIO109
0, 4, 8, 12
I/O
General-Purpose Input Output 109
External memory interface 2 address line 11
EtherCAT General-Purpose Input 9
EMAC MII carrier sense
EMIF2_A11
ESC_GPI9
3
O
N2
M2
10
I
ENET_MII_CRS
GPIO110
14
I
0, 4, 8, 12
I/O
General-Purpose Input Output 110
External memory interface 2 Asynchronous SRAM WAIT
EtherCAT General-Purpose Input 10
FSIRX-B Data Input 0
EMIF2_WAIT
ESC_GPI10
FSIRXB_D0
ENET_MII_COL
GPIO111
3
I
10
I
13
I
14
I
I/O
O
I
EMAC MII collision detect
0, 4, 8, 12
General-Purpose Input Output 111
External memory interface 2 bank address 0
EtherCAT General-Purpose Input 11
FSIRX-B Data Input 1
EMIF2_BA0
ESC_GPI11
FSIRXB_D1
ENET_MII_RX_CLK
GPIO112
3
10
M4
13
I
14
I
EMAC MII receive clock
0, 4, 8, 12
I/O
O
I
General-Purpose Input Output 112
External memory interface 2 bank address 1
EtherCAT General-Purpose Input 12
FSIRX-B Input Clock
EMIF2_BA1
ESC_GPI12
FSIRXB_CLK
3
10
13
M3
N4
I
EMAC MII receive data valid (or) RMII carrier sense/
receive data valid
ENET_MII_RX_DV
14
I
GPIO113
0, 4, 8, 12
I/O
General-Purpose Input Output 113
EMIF2_CAS
ESC_GPI13
3
O
I
External memory interface 2 column address strobe
EtherCAT General-Purpose Input 13
EMAC MII / RMII receive error
10
14
ENET_MII_RX_ERR
I
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
www.ti.com
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
Table 6-1. Pin Attributes (continued)
MUX
POSITION
PIN
TYPE
SIGNAL NAME
337
176
DESCRIPTION
GPIO114
0, 4, 8, 12
I/O
O
I
General-Purpose Input Output 114
External memory interface 2 row address strobe
EtherCAT General-Purpose Input 14
EMAC MII / RMII receive data 0
General-Purpose Input Output 115
External memory interface 2 chip select 0
Output X-BAR Output 5
EMIF2_RAS
3
N3
ESC_GPI14
10
ENET_MII_RX_DATA0
GPIO115
14
I
0, 4, 8, 12
I/O
O
O
I
EMIF2_CS0n
OUTPUTXBAR5
ESC_GPI15
3
5
V12
10
EtherCAT General-Purpose Input 15
FSIRX-C Data Input 0
FSIRXC_D0
13
I
ENET_MII_RX_DATA1
GPIO116
14
I
EMAC MII / RMII receive data 1
General-Purpose Input Output 116
External memory interface 2 chip select 2
Output X-BAR Output 6
0, 4, 8, 12
I/O
O
O
I
EMIF2_CS2n
OUTPUTXBAR6
ESC_GPI16
3
5
W10
10
EtherCAT General-Purpose Input 16
FSIRX-C Data Input 1
FSIRXC_D1
13
I
ENET_MII_RX_DATA2
GPIO117
14
I
EMAC MII receive data 2
0, 4, 8, 12
I/O
O
I
General-Purpose Input Output 117
External memory interface 2 SDRAM clock enable
EtherCAT General-Purpose Input 17
FSIRX-C Input Clock
EMIF2_SDCKE
ESC_GPI17
3
10
U12
T12
T15
U15
W16
FSIRXC_CLK
ENET_MII_RX_DATA3
GPIO118
13
I
14
I
EMAC MII receive data 3
0, 4, 8, 12
I/O
O
I
General-Purpose Input Output 118
External memory interface 2 clock
EtherCAT General-Purpose Input 18
FSIRX-D Data Input 0
EMIF2_CLK
3
ESC_GPI18
10
FSIRXD_D0
13
I
ENET_MII_TX_EN
GPIO119
14
O
I/O
O
I
EMAC MII / RMII transmit enable
General-Purpose Input Output 119
External memory interface 2 read not write
EtherCAT General-Purpose Input 19
FSIRX-D Data Input 1
0, 4, 8, 12
EMIF2_RNW
ESC_GPI19
3
10
FSIRXD_D1
13
I
ENET_MII_TX_ERR
GPIO120
14
O
I/O
O
I
EMAC MII transmit error
0, 4, 8, 12
General-Purpose Input Output 120
External memory interface 2 write enable
EtherCAT General-Purpose Input 20
FSIRX-D Input Clock
EMIF2_WEn
ESC_GPI20
3
10
FSIRXD_CLK
ENET_MII_TX_CLK
GPIO121
13
I
14
I
EMAC MII transmit clock
0, 4, 8, 12
I/O
O
I
General-Purpose Input Output 121
External memory interface 2 output enable
EtherCAT General-Purpose Input 21
FSIRX-E Data Input 0
EMIF2_OEn
3
ESC_GPI21
10
13
14
FSIRXE_D0
I
ENET_MII_TX_DATA0
O
EMAC MII / RMII transmit data 0
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Product Folder Links: TMS320F28388D TMS320F28386D TMS320F28386D-Q1 TMS320F28384D
TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
www.ti.com
Table 6-1. Pin Attributes (continued)
MUX
POSITION
PIN
TYPE
SIGNAL NAME
GPIO122
337
176
DESCRIPTION
0, 4, 8, 12
I/O
I/O
I/O
I
General-Purpose Input Output 122
External memory interface 2 data line 15
SPI-C Slave In, Master Out (SIMO)
SDFM-1 Channel 1 Data Input
EtherCAT General-Purpose Input 22
EMAC MII / RMII transmit data 1
General-Purpose Input Output 123
External memory interface 2 data line 14
SPI-C Slave Out, Master In (SOMI)
SDFM-1 Channel 1 Clock Input
EtherCAT General-Purpose Input 23
EMAC MII transmit data 2
EMIF2_D15
SPIC_SIMO
SD1_D1
3
6
T8
7
ESC_GPI22
ENET_MII_TX_DATA1
GPIO123
10
I
14
O
I/O
I/O
I/O
I
0, 4, 8, 12
EMIF2_D14
SPIC_SOMI
SD1_C1
3
6
U8
7
ESC_GPI23
ENET_MII_TX_DATA2
GPIO124
10
I
14
O
I/O
I/O
I/O
I
0, 4, 8, 12
General-Purpose Input Output 124
External memory interface 2 data line 13
SPI-C Clock
EMIF2_D13
SPIC_CLK
SD1_D2
3
6
V8
7
SDFM-1 Channel 2 Data Input
EtherCAT General-Purpose Input 24
EMAC MII transmit data 3
ESC_GPI24
ENET_MII_TX_DATA3
GPIO125
10
I
14
O
I/O
I/O
I/O
I
0, 4, 8, 12
General-Purpose Input Output 125
External memory interface 2 data line 12
SPI-C Slave Transmit Enable (STE)
SDFM-1 Channel 2 Clock Input
EtherCAT General-Purpose Input 25
FSIRX-E Data Input 1
EMIF2_D12
SPIC_STEn
SD1_C2
3
6
7
T9
ESC_GPI25
FSIRXE_D1
ESC_LATCH0
GPIO126
10
I
13
I
14
I
EtherCAT LatchSignal Input 0
0, 4, 8, 12
I/O
I/O
I
General-Purpose Input Output 126
External memory interface 2 data line 11
SDFM-1 Channel 3 Data Input
EtherCAT General-Purpose Input 26
FSIRX-E Input Clock
EMIF2_D11
SD1_D3
3
7
U9
ESC_GPI26
FSIRXE_CLK
ESC_LATCH1
GPIO127
10
I
13
I
14
I
EtherCAT LatchSignal Input 1
0, 4, 8, 12
I/O
I/O
I
General-Purpose Input Output 127
External memory interface 2 data line 10
SDFM-1 Channel 3 Clock Input
EtherCAT General-Purpose Input 27
EtherCAT SyncSignal Output 0
General-Purpose Input Output 128
External memory interface 2 data line 9
SDFM-1 Channel 4 Data Input
EtherCAT General-Purpose Input 28
EtherCAT SyncSignal Output 1
General-Purpose Input Output 129
External memory interface 2 data line 8
SDFM-1 Channel 4 Clock Input
EtherCAT General-Purpose Input 29
EtherCAT MII Transmit-1 Enable
EMIF2_D10
SD1_C3
3
7
V9
W9
T10
ESC_GPI27
ESC_SYNC0
GPIO128
10
I
14
O
I/O
I/O
I
0, 4, 8, 12
EMIF2_D9
3
SD1_D4
7
ESC_GPI28
ESC_SYNC1
GPIO129
10
I
14
O
I/O
I/O
I
0, 4, 8, 12
EMIF2_D8
3
7
SD1_C4
ESC_GPI29
ESC_TX1_ENA
10
14
I
I/O
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
www.ti.com
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
Table 6-1. Pin Attributes (continued)
MUX
POSITION
PIN
SIGNAL NAME
337
176
DESCRIPTION
TYPE
I/O
I/O
I
GPIO130
0, 4, 8, 12
General-Purpose Input Output 130
External memory interface 2 data line 7
SDFM-2 Channel 1 Data Input
EMIF2_D7
SD2_D1
3
7
U10
ESC_GPI30
ESC_TX1_CLK
GPIO131
10
I
EtherCAT General-Purpose Input 30
EtherCAT MII Transmit-1 Clock
General-Purpose Input Output 131
External memory interface 2 data line 6
SDFM-2 Channel 1 Clock Input
EtherCAT General-Purpose Input 31
EtherCAT MII Transmit-1 Data-0
General-Purpose Input Output 132
External memory interface 2 data line 5
SDFM-2 Channel 2 Data Input
14
I
0, 4, 8, 12
I/O
I/O
I
EMIF2_D6
SD2_C1
3
7
V10
ESC_GPI31
ESC_TX1_DATA0
GPIO132
10
I
14
O
I/O
I/O
I
0, 4, 8, 12
EMIF2_D5
SD2_D2
3
7
W18
G18
V18
ESC_GPO0
ESC_TX1_DATA1
GPIO133
10
O
O
I/O
I
EtherCAT General-Purpose Output 0
EtherCAT MII Transmit-1 Data-1
General-Purpose Input Output 133
SDFM-2 Channel 2 Clock Input
Auxilary Clock Input
14
0, 4, 8, 12
SD2_C2
7
118
AUXCLKIN
GPIO134
ALT
I
0, 4, 8, 12
I/O
I/O
I
General-Purpose Input Output 134
External memory interface 2 data line 4
SDFM-2 Channel 3 Data Input
EMIF2_D4
SD2_D3
3
7
ESC_GPO1
ESC_TX1_DATA2
GPIO135
10
O
O
I/O
I/O
O
I
EtherCAT General-Purpose Output 1
EtherCAT MII Transmit-1 Data-2
General-Purpose Input Output 135
External memory interface 2 data line 3
SCI-A Transmit Data
14
0, 4, 8, 12
EMIF2_D3
SCIA_TX
3
6
U18
SD2_C3
7
SDFM-2 Channel 3 Clock Input
EtherCAT General-Purpose Output 2
EtherCAT MII Transmit-1 Data-3
General-Purpose Input Output 136
External memory interface 2 data line 2
SCI-A Receive Data
ESC_GPO2
ESC_TX1_DATA3
GPIO136
10
O
O
I/O
I/O
I
14
0, 4, 8, 12
EMIF2_D2
SCIA_RX
3
6
T17
SD2_D4
7
I
SDFM-2 Channel 4 Data Input
ESC_GPO3
ESC_RX1_DV
GPIO137
10
O
I
EtherCAT General-Purpose Output 3
EtherCAT MII Receive-1 Data Valid
General-Purpose Input Output 137
ePWM-13 Output A (High-res available on ePWM1-8)
External memory interface 2 data line 1
SCI-B Transmit Data
14
0, 4, 8, 12
I/O
O
I/O
O
I
EPWM13A
EMIF2_D1
SCIB_TX
1
3
6
T18
SD2_C4
7
SDFM-2 Channel 4 Clock Input
EtherCAT General-Purpose Output 4
EtherCAT MII Receive-1 Clock
ESC_GPO4
ESC_RX1_CLK
10
14
O
I
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Product Folder Links: TMS320F28388D TMS320F28386D TMS320F28386D-Q1 TMS320F28384D
TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
www.ti.com
Table 6-1. Pin Attributes (continued)
MUX
POSITION
PIN
TYPE
SIGNAL NAME
GPIO138
337
176
DESCRIPTION
0, 4, 8, 12
I/O
O
I/O
I
General-Purpose Input Output 138
EPWM13B
1
ePWM-13 Output B (High-res available on ePWM1-8)
External memory interface 2 data line 0
SCI-B Receive Data
EMIF2_D0
3
T19
SCIB_RX
6
ESC_GPO5
ESC_RX1_ERR
GPIO139
10
O
I
EtherCAT General-Purpose Output 5
EtherCAT MII Receive-1 Error
14
0, 4, 8, 12
I/O
O
I
General-Purpose Input Output 139
ePWM-14 Output A (High-res available on ePWM1-8)
SCI-C Receive Data
EPWM14A
1
SCIC_RX
6
N19
M19
M18
L19
ESC_GPO6
ESC_RX1_DATA0
GPIO140
10
O
I
EtherCAT General-Purpose Output 6
EtherCAT MII Receive-1 Data-0
14
0, 4, 8, 12
I/O
O
O
O
I
General-Purpose Input Output 140
ePWM-14 Output B (High-res available on ePWM1-8)
SCI-C Transmit Data
EPWM14B
1
SCIC_TX
6
ESC_GPO7
ESC_RX1_DATA1
GPIO141
10
EtherCAT General-Purpose Output 7
EtherCAT MII Receive-1 Data-1
14
0, 4, 8, 12
I/O
O
I
General-Purpose Input Output 141
ePWM-15 Output A (High-res available on ePWM1-8)
SCI-D Receive Data
EPWM15A
1
SCID_RX
6
ESC_GPO8
ESC_RX1_DATA2
GPIO142
10
O
I
EtherCAT General-Purpose Output 8
EtherCAT MII Receive-1 Data-2
14
0, 4, 8, 12
I/O
O
O
O
I
General-Purpose Input Output 142
ePWM-15 Output B (High-res available on ePWM1-8)
SCI-D Transmit Data
EPWM15B
1
SCID_TX
6
ESC_GPO9
ESC_RX1_DATA3
GPIO143
10
EtherCAT General-Purpose Output 9
EtherCAT MII Receive-1 Data-3
14
0, 4, 8, 12
I/O
O
O
O
I/O
O
O
O
I/O
O
O
O
I/O
O
O
O
I/O
O
O
O
General-Purpose Input Output 143
ePWM-16 Output A (High-res available on ePWM1-8)
EtherCAT General-Purpose Output 10
EtherCAT Link-0 Active
EPWM16A
1
F18
F17
E17
D18
D17
ESC_GPO10
ESC_LED_LINK0_ACTIVE
GPIO144
10
14
0, 4, 8, 12
General-Purpose Input Output 144
ePWM-16 Output B (High-res available on ePWM1-8)
EtherCAT General-Purpose Output 11
EtherCAT Link-1 Active
EPWM16B
1
ESC_GPO11
ESC_LED_LINK1_ACTIVE
GPIO145
10
14
0, 4, 8, 12
General-Purpose Input Output 145
ePWM-1 Output A (High-res available on ePWM1-8)
EtherCAT General-Purpose Output 12
EtherCAT Error LED
EPWM1A
1
ESC_GPO12
ESC_LED_ERR
GPIO146
10
14
0, 4, 8, 12
General-Purpose Input Output 146
ePWM-1 Output B (High-res available on ePWM1-8)
EtherCAT General-Purpose Output 13
EtherCAT Run LED
EPWM1B
1
ESC_GPO13
ESC_LED_RUN
GPIO147
10
14
0, 4, 8, 12
General-Purpose Input Output 147
ePWM-2 Output A (High-res available on ePWM1-8)
EtherCAT General-Purpose Output 14
EtherCAT State Run
EPWM2A
1
ESC_GPO14
ESC_LED_STATE_RUN
10
14
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
www.ti.com
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
Table 6-1. Pin Attributes (continued)
MUX
POSITION
PIN
SIGNAL NAME
337
176
DESCRIPTION
TYPE
I/O
O
GPIO148
0, 4, 8, 12
General-Purpose Input Output 148
ePWM-2 Output B (High-res available on ePWM1-8)
EtherCAT General-Purpose Output 15
EtherCAT PHY-0 Link Status
EPWM2B
1
D14
ESC_GPO15
ESC_PHY0_LINKSTATUS
GPIO149
10
O
14
I
0, 4, 8, 12
I/O
O
General-Purpose Input Output 149
ePWM-3 Output A (High-res available on ePWM1-8)
EtherCAT General-Purpose Output 16
EtherCAT PHY-1 Link Status
EPWM3A
1
A13
B13
C13
D13
A12
B12
C12
D12
B10
C10
ESC_GPO16
ESC_PHY1_LINKSTATUS
GPIO150
10
O
14
I
0, 4, 8, 12
I/O
O
General-Purpose Input Output 150
ePWM-3 Output B (High-res available on ePWM1-8)
EtherCAT General-Purpose Output 17
EtherCAT I2C Data
EPWM3B
1
ESC_GPO17
ESC_I2C_SDA
GPIO151
10
O
14
I/OC
I/O
O
0, 4, 8, 12
General-Purpose Input Output 151
ePWM-4 Output A (High-res available on ePWM1-8)
EtherCAT General-Purpose Output 18
EtherCAT I2C Clock
EPWM4A
1
ESC_GPO18
ESC_I2C_SCL
GPIO152
10
O
14
I/OC
I/O
O
0, 4, 8, 12
General-Purpose Input Output 152
ePWM-4 Output B (High-res available on ePWM1-8)
EtherCAT General-Purpose Output 19
EtherCAT MDIO Clock
EPWM4B
1
ESC_GPO19
ESC_MDIO_CLK
GPIO153
10
O
14
O
0, 4, 8, 12
I/O
O
General-Purpose Input Output 153
ePWM-5 Output A (High-res available on ePWM1-8)
EtherCAT General-Purpose Output 20
EtherCAT MDIO Data
EPWM5A
1
ESC_GPO20
ESC_MDIO_DATA
GPIO154
10
O
14
I/O
I/O
O
0, 4, 8, 12
General-Purpose Input Output 154
ePWM-5 Output B (High-res available on ePWM1-8)
EtherCAT General-Purpose Output 21
EtherCAT PHY Clock
EPWM5B
1
ESC_GPO21
ESC_PHY_CLK
GPIO155
10
O
14
O
0, 4, 8, 12
I/O
O
General-Purpose Input Output 155
ePWM-6 Output A (High-res available on ePWM1-8)
EtherCAT General-Purpose Output 22
EtherCAT PHY Active Low Reset
EPWM6A
1
ESC_GPO22
ESC_PHY_RESETn
GPIO156
10
O
14
O
0, 4, 8, 12
I/O
O
General-Purpose Input Output 156
ePWM-6 Output B (High-res available on ePWM1-8)
EtherCAT General-Purpose Output 23
EtherCAT MII Transmit-0 Enable
EPWM6B
1
ESC_GPO23
ESC_TX0_ENA
GPIO157
10
O
14
I/O
I/O
O
0, 4, 8, 12
General-Purpose Input Output 157
ePWM-7 Output A (High-res available on ePWM1-8)
EtherCAT General-Purpose Output 24
EtherCAT MII Transmit-0 Clock
EPWM7A
1
ESC_GPO24
ESC_TX0_CLK
GPIO158
10
O
14
I
0, 4, 8, 12
I/O
O
General-Purpose Input Output 158
ePWM-7 Output B (High-res available on ePWM1-8)
EtherCAT General-Purpose Output 25
EtherCAT MII Transmit-0 Data-0
EPWM7B
1
ESC_GPO25
ESC_TX0_DATA0
10
14
O
O
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Product Folder Links: TMS320F28388D TMS320F28386D TMS320F28386D-Q1 TMS320F28384D
TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
www.ti.com
Table 6-1. Pin Attributes (continued)
MUX
POSITION
PIN
TYPE
SIGNAL NAME
GPIO159
337
176
DESCRIPTION
0, 4, 8, 12
I/O
O
O
O
I/O
O
O
O
I/O
O
O
O
I/O
O
O
I
General-Purpose Input Output 159
EPWM8A
1
ePWM-8 Output A (High-res available on ePWM1-8)
EtherCAT General-Purpose Output 26
EtherCAT MII Transmit-0 Data-1
D10
ESC_GPO26
ESC_TX0_DATA1
GPIO160
10
14
0, 4, 8, 12
General-Purpose Input Output 160
EPWM8B
1
ePWM-8 Output B (High-res available on ePWM1-8)
EtherCAT General-Purpose Output 27
EtherCAT MII Transmit-0 Data-2
B9
C9
D9
A8
B8
C5
D5
C4
D4
ESC_GPO27
ESC_TX0_DATA2
GPIO161
10
14
0, 4, 8, 12
General-Purpose Input Output 161
EPWM9A
1
ePWM-9 Output A (High-res available on ePWM1-8)
EtherCAT General-Purpose Output 28
EtherCAT MII Transmit-0 Data-3
ESC_GPO28
ESC_TX0_DATA3
GPIO162
10
14
0, 4, 8, 12
General-Purpose Input Output 162
EPWM9B
1
ePWM-9 Output B (High-res available on ePWM1-8)
EtherCAT General-Purpose Output 29
EtherCAT MII Receive-0 Data Valid
General-Purpose Input Output 163
ESC_GPO29
ESC_RX0_DV
GPIO163
10
14
0, 4, 8, 12
I/O
O
O
I
EPWM10A
1
ePWM-10 Output A (High-res available on ePWM1-8)
EtherCAT General-Purpose Output 30
EtherCAT MII Receive-0 Clock
ESC_GPO30
ESC_RX0_CLK
GPIO164
10
14
0, 4, 8, 12
I/O
O
O
I
General-Purpose Input Output 164
EPWM10B
1
ePWM-10 Output B (High-res available on ePWM1-8)
EtherCAT General-Purpose Output 31
EtherCAT MII Receive-0 Error
ESC_GPO31
ESC_RX0_ERR
GPIO165
10
14
0, 4, 8, 12
I/O
O
O
I
General-Purpose Input Output 165
EPWM11A
1
ePWM-11 Output A (High-res available on ePWM1-8)
McBSP-A Transmit Serial Data
MDXA
10
ESC_RX0_DATA0
GPIO166
14
EtherCAT MII Receive-0 Data-0
0, 4, 8, 12
I/O
O
I
General-Purpose Input Output 166
EPWM11B
1
ePWM-11 Output B (High-res available on ePWM1-8)
McBSP-A Receive Serial Data
MDRA
10
ESC_RX0_DATA1
GPIO167
14
I
EtherCAT MII Receive-0 Data-1
0, 4, 8, 12
I/O
O
O
I
General-Purpose Input Output 167
EPWM12A
1
ePWM-12 Output A (High-res available on ePWM1-8)
McBSP-A Transmit Clock
MCLKXA
10
ESC_RX0_DATA2
GPIO168
14
EtherCAT MII Receive-0 Data-2
0, 4, 8, 12
I/O
O
O
I
General-Purpose Input Output 168
EPWM12B
1
ePWM-12 Output B (High-res available on ePWM1-8)
McBSP-A Transmit Frame Sync
MFSXA
10
14
ESC_RX0_DATA3
EtherCAT MII Receive-0 Data-3
TEST, JTAG, AND RESET
Error Status Output. When used, this signal requires an
external pulldown.
ERRORSTS
FLT1
U19
92
73
O
Flash test pin 1. Reserved for TI. Must be left
unconnected.
W12
I/O
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
www.ti.com
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
Table 6-1. Pin Attributes (continued)
MUX
POSITION
PIN
TYPE
SIGNAL NAME
337
176
DESCRIPTION
Flash test pin 2. Reserved for TI. Must be left
unconnected.
FLT2
NC
V13
74
I/O
No Connection. This pin is not internally connected to the
device. This pin may be left open or connected to any
voltage within the maximum operating conditions.
H4
119
81
JTAG test-mode select (TMS) with internal pullup. This
serial control input is clocked into the TAP controller on
the rising edge of TCK.
TCK
TDI
V15
W13
W15
I
I
JTAG test data input (TDI) with internal pullup. TDI is
clocked into the selected register (instruction or data) on a
rising edge of TCK.
77
JTAG scan out, test data output (TDO). The contents of
the selected register (instruction or data) are shifted out of
TDO on the falling edge of TCK.
TDO
78
O
JTAG test-mode select (TMS) with internal pullup. This
serial control input is clocked into the TAP controller on
the rising edge of TCK. An external pullup resistor
(recommended 2.2 kΩ) on the TMS pin to VDDIO should
be placed on the board to keep JTAG in reset during
normal operation.
TMS
W14
80
I
JTAG test reset with internal pulldown. TRSTn, when
driven high, gives the scan system control of the
operations of the device. If this signal is driven low, the
device operates in its functional mode, and the test reset
signals are ignored. NOTE: TRST must be maintained low
at all times during normal device operation. An external
pulldown resistor is required on this pin. The value of this
resistor should be based on drive strength of the
debugger pods applicable to the design. A 2.2-kΩ or
smaller resistor generally offers adequate protection. The
value of the resistor is application-specific. TI
TRSTn
V14
79
I
recommends that each target board be validated for
proper operation of the debugger and the application. This
pin has an internal 50-ns (nominal) glitch filter.
Crystal oscillator input or single-ended clock input. The
device initialization software must configure this pin before
the crystal oscillator is enabled. To use this oscillator, a
quartz crystal circuit must be connected to X1 and X2.
This pin can also be used to feed a single-ended 3.3-V
level clock.
X1
X2
G19
J19
123
121
I
O
Crystal oscillator output.
Device Reset (in) and Watchdog Reset (out). During a
power-on condition, this pin is driven low by the device.
An external circuit may also drive this pin to assert a
device reset. This pin is also driven low by the MCU when
a watchdog reset occurs. During watchdog reset, the
XRSn pin is driven low for the watchdog reset duration of
512 OSCCLK cycles. A resistor between 2.2 kΩ and 10
kΩ should be placed between XRSn and VDDIO. If a
capacitor is placed between XRSn and VSS for noise
filtering, it should be 100 nF or smaller. These values will
allow the watchdog to properly drive the XRSn pin to VOL
within 512 OSCCLK cycles when the watchdog reset is
asserted. The output buffer of this pin is an open-drain
with an internal pullup. If this pin is driven by an external
device, it should be done using an open-drain device. If
this pin is driven by an external device, it should be done
using an open-drain device.
XRSn
F19
124
I/OD
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
www.ti.com
Table 6-1. Pin Attributes (continued)
MUX
POSITION
PIN
TYPE
SIGNAL NAME
337
176
DESCRIPTION
POWER AND GROUND
1.2-V Digital Logic Power Pins. TI recommends placing a
decoupling capacitor near each VDD pin with a minimum
total capacitance of approximately 20 µF. The exact value
of the decoupling capacitance should be determined by
your system voltage regulation solution. A single 56Ω
resistor (10% tolerance) should be placed between
between VDD and VSS. This resistor provides a load to
consume an internal VDD3VFL to VDD current source
and avoid VDD voltage rising during low power device
conditions.
E9, E11,
F9, F11,
G14,
61, 76,
117, 126,
G15,
VDD
J14, J15, 137, 153,
K5, K6, 158, 169,
P10,
P13,
16, 21
R10, R13
3.3-V Flash power pin. Place a minimum 0.1-µF
decoupling capacitor on each pin
VDD3VFL
VDDA
R11, R12
P6, R6
72
3.3-V Analog Power Pins. Place a minimum 2.2-µF
decoupling capacitor to VSSA on each pin.
54, 36
A9, A18,
B1, E7,
E10,
E13, F7, 62, 68,
F10, 75, 82,
F13, G5, 88, 91,
G6, H5, 99, 106,
H6, L14, 114, 116,
L15, M1, 127, 138,
M5, M6, 147, 152,
3.3-V Digital I/O Power Pins. Place a minimum 0.1-µF
decoupling capacitor on each pin.
VDDIO
N14,
159, 168,
N15, P9, 3, 11, 15,
R9, V19, 20, 26
W8, F4,
G4, E16,
F16
Power pins for the 3.3-V on-chip crystal oscillator (X1 and
X2) and the two zero-pin internal oscillators (INTOSC).
Place a 0.1-µF (minimum) decoupling capacitor on each
pin.
VDDOSC
H16, H17 120, 125
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
www.ti.com
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
Table 6-1. Pin Attributes (continued)
MUX
POSITION
PIN
TYPE
SIGNAL NAME
337
176
DESCRIPTION
A1, A10,
A19, E5,
E6, E8,
E12,
E14,
E15, F5,
F6, F8,
F12,
F14,
F15,
G16,
G17, H8,
H9, H10,
H11,
H12,
H14,
H15, J5,
J6, J8,
J9, J10,
J11, J12,
K8, K9,
K10,
178, 179,
180, 177
VSS
Digital Ground
K11,
K12,
K14,
K15, L5,
L6, L8,
L9, L10,
L11, L12,
L18, M8,
M9, M10,
M11,
M12,
M14,
M15, N1,
N5, N6,
P7, P8,
P11,
P12,
P14,
P15, R7,
R8, R14,
R15, W7,
W19
P1, P5,
R5, V7,
W1
VSSA
52, 34
122
Analog Ground
Crystal oscillator (X1 and X2) ground pin. When using an
external crystal, do not connect this pin to the board
ground. Instead, connect it to the ground reference of the
external crystal oscillator circuit. If an external crystal is
not used, this pin may be connected to the board ground.
VSSOSC
H18, H19
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
www.ti.com
6.3 Signal Descriptions
6.3.1 Analog Signals
Table 6-2. Analog Signals
PIN
TYPE
SIGNAL NAME
DESCRIPTION
GPIO
337 BGA 176 Pin
Input 14 to all ADCs. This pin can be used as a
general purpose ADCIN pin or it can be used to
calibrate all ADCs together (either single-ended or
differential) from an external reference
ADCIN14
ADCIN15
I
I
T4
U4
44
45
Input 15 to all ADCs. This pin can be used as a
general purpose ADCIN pin or it can be used to
calibrate all ADCs together (either single-ended or
differential) from an external reference
ADC-A Input 0. There is a 50-kΩ internal pulldown on
this pin in both an ADC input or DAC output mode
which cannot be disabled.
ADCINA0
ADCINA1
I
I
U1
T1
43
42
ADC-A Input 1. There is a 50-kΩ internal pulldown on
this pin in both an ADC input or DAC output mode
which cannot be disabled.
ADCINA2
ADCINA3
ADCINA4
ADCINA5
ADC-A Input 2
ADC-A Input 3
ADC-A Input 4
ADC-A Input 5
I
I
I
I
U2
T2
U3
T3
41
40
39
38
ADC-B Input 0. There is a 100-pF capacitor to VSSA
on this pin whether used for ADC input or DAC
reference which cannot be disabled. If this pin is being
used as a reference for the on-chip DACs, place at
least a 1-µF capacitor on this pin.
ADCINB0
I
V2
46
ADC-B Input 1. There is a 50-kΩ internal pulldown on
this pin in both an ADC input or DAC output mode
which cannot be disabled.
ADCINB1
I
W2
47
ADCINB2
ADCINB3
ADCINB4
ADCINB5
ADCINC2
ADCINC3
ADCINC4
ADCINC5
ADCIND0
ADCIND1
ADCIND2
ADCIND3
ADCIND4
ADCIND5
CMPIN1N
CMPIN1P
CMPIN2N
CMPIN2P
CMPIN3N
CMPIN3P
CMPIN4N
ADC-B Input 2
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
V3
W3
V4
W4
R3
P3
R4
P4
T5
U5
T6
U6
T7
U7
T2
U2
T3
U3
W3
V3
U4
48
49
ADC-B Input 3
ADC-B Input 4
ADC-B Input 5
ADC-C Input 2
31
30
29
ADC-C Input 3
ADC-C Input 4
ADC-C Input 5
ADC-D Input 0
56
57
58
59
60
ADC-D Input 1
ADC-D Input 2
ADC-D Input 3
ADC-D Input 4
ADC-D Input 5
Comparator 1 negative input
Comparator 1 positive input
Comparator 2 negative input
Comparator 2 positive input
Comparator 3 negative input
Comparator 3 positive input
Comparator 4 negative input
40
41
38
39
49
48
45
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
Table 6-2. Analog Signals (continued)
PIN
TYPE
SIGNAL NAME
DESCRIPTION
Comparator 4 positive input
GPIO
337 BGA 176 Pin
CMPIN4P
CMPIN5N
CMPIN5P
CMPIN6N
CMPIN6P
CMPIN7N
CMPIN7P
CMPIN8N
CMPIN8P
DACOUTA
DACOUTB
DACOUTC
VDAC
I
I
T4
P4
R4
P3
R3
U5
T5
U6
T6
U1
T1
W2
V2
44
Comparator 5 negative input
Comparator 5 positive input
Comparator 6 negative input
Comparator 6 positive input
Comparator 7 negative input
Comparator 7 positive input
Comparator 8 negative input
Comparator 8 positive input
Buffered DAC-A Output.
I
29
30
31
57
56
59
58
43
42
47
46
I
I
I
I
I
I
O
O
O
I
Buffered DAC-B Output.
Buffered DAC-C Output.
Optional external reference voltage for on-chip DACs.
ADC-A high reference. This voltage must be driven
into the pin from external circuitry. Place at least a 2.2-
µF capacitor on this pin for the 12-bit mode, or at least
a 22-µF capacitor for the 16-bit mode. This capacitor
should be placed as close to the device as possible
between the VREFHIA and VREFLOA pins. NOTE: Do
not load this pin externally
VREFHIA
VREFHIB
VREFHIC
VREFHID
I
I
I
I
V1
W5
R1
V5
37
53
35
55
ADC-B high reference. This voltage must be driven
into the pin from external circuitry. Place at least a 2.2-
µF capacitor on this pin for the 12-bit mode, or at least
a 22-µF capacitor for the 16-bit mode. This capacitor
should be placed as close to the device as possible
between the VREFHIB and VREFLOB pins. NOTE: Do
not load this pin externally
ADC-C high reference. This voltage must be driven
into the pin from external circuitry. Place at least a 2.2-
µF capacitor on this pin for the 12-bit mode, or at least
a 22-µF capacitor for the 16-bit mode. This capacitor
should be placed as close to the device as possible
between the VREFHIC and VREFLOC pins. NOTE: Do
not load this pin externally
ADC-D high reference. This voltage must be driven
into the pin from external circuitry. Place at least a 2.2-
µF capacitor on this pin for the 12-bit mode, or at least
a 22-µF capacitor for the 16-bit mode. This capacitor
should be placed as close to the device as possible
between the VREFHID and VREFLOD pins. NOTE: Do
not load this pin externally
VREFLOA
VREFLOB
VREFLOC
VREFLOD
ADC-A Low Reference
ADC-B Low Reference
ADC-C Low Reference
ADC-D Low Reference
I
I
I
I
R2
V6
P2
W6
33
50
32
51
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
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6.3.2 Digital Signals
Table 6-3. Digital Signals
PIN
TYPE
SIGNAL NAME
ADCSOCAO
DESCRIPTION
GPIO
337 BGA 176 Pin
ADC Start of Conversion A Output for External ADC
(from ePWM modules)
O
8
G2
18
ADC Start of Conversion B Output for External ADC
(from ePWM modules)
ADCSOCBO
AUXCLKIN
O
I
10
B2
1
Auxilary Clock Input
133
G18
118
A17, D7, 10, 107,
E3, J17, 108, 135,
L16, T11, 165, 63,
18, 30,
36, 5, 61,
62, 70
CANA_RX
CANA_TX
CANB_RX
CANB_TX
CAN-A Receive
I
V16
83
B17, C7, 108, 109,
E4, J16, 12, 136,
J17, U11, 164, 66,
19, 31,
37, 4, 62,
63, 71
CAN-A Transmit
CAN-B Receive
CAN-B Transmit
O
I
U16
84
A16, B2,
B6, D1,
E2, F3,
W17
10, 13,
17, 21,
39, 7, 73
1, 14,
140, 167,
5, 86, 9
A6, B16,
C2, E1,
F2, G2,
T16
12, 16,
20, 38, 6,
72, 8
13, 139,
166, 18,
4, 8, 85
O
CLB_OUTPUTXBAR1
CLB_OUTPUTXBAR2
CLB_OUTPUTXBAR3
CLB_OUTPUTXBAR4
CLB_OUTPUTXBAR5
CLB_OUTPUTXBAR6
CLB_OUTPUTXBAR7
CLB_OUTPUTXBAR8
CLB Output X-BAR Output 1
CLB Output X-BAR Output 2
CLB Output X-BAR Output 3
CLB Output X-BAR Output 4
CLB Output X-BAR Output 5
CLB Output X-BAR Output 6
CLB Output X-BAR Output 7
CLB Output X-BAR Output 8
O
O
O
O
O
O
O
O
32, 91
33, 92
34, 93
35, 94
36, 95
37, 96
38, 97
39, 98
B5, U13
A4, T13
B4, U14
A3, T14
B3, V16
C3, U16
A2, T16
F1, W17
173, 67
174, 69
175, 70
176, 71
83
84
85
86
1, 105,
32
D8, J3,
U13
CM-I2CA_SCL
CM-I2CA_SDA
EMIF1_CAS
CM-I2C-A Open-Drain Bidirectional Clock
CM-I2C-A Open-Drain Bidirectional Data
External memory interface 1 column address strobe
I/OD
I/OD
O
161, 67
160, 66
0, 104,
31
C8, J2,
U11
23, 86,
89
C11, D6, 156, 171,
K4
23
EMIF1_CLK
EMIF1_OEn
External memory interface 1 clock
O
O
30
T11
63
External memory interface 1 output enable
32, 37 U13, U16 67, 84
22, 87,
90
A5, D11, 157, 172,
EMIF1_RAS
External memory interface 1 row address strobe
O
J4
22
66, 69
65
EMIF1_RNW
External memory interface 1 read not write
O
O
31, 33
29
T13, U11
W11
EMIF1_SDCKE
External memory interface 1 SDRAM clock enable
External memory interface 1 Asynchronous SRAM
WAIT
EMIF1_WAIT
I
36
V16
83
66
EMIF1_WEn
EMIF2_CAS
EMIF2_CLK
EMIF2_OEn
EMIF2_RAS
EMIF2_RNW
External memory interface 1 write enable
External memory interface 2 column address strobe
External memory interface 2 clock
O
O
O
O
O
O
31
U11
N4
113
118
121
114
119
T12
W16
N3
External memory interface 2 output enable
External memory interface 2 row address strobe
External memory interface 2 read not write
T15
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
www.ti.com
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
Table 6-3. Digital Signals (continued)
PIN
TYPE
SIGNAL NAME
DESCRIPTION
GPIO
117
337 BGA 176 Pin
EMIF2_SDCKE
EMIF2_WAIT
External memory interface 2 SDRAM clock enable
O
U12
M2
External memory interface 2 Asynchronous SRAM
WAIT
I
110
EMIF2_WEn
EMIF1_A0
EMIF1_A1
EMIF1_A2
EMIF1_A3
EMIF1_A4
EMIF1_A5
EMIF1_A6
EMIF1_A7
EMIF1_A8
EMIF1_A9
EMIF1_A10
EMIF1_A11
EMIF1_A12
EMIF1_A13
EMIF1_A14
EMIF1_A15
EMIF1_A16
EMIF1_A17
EMIF1_A18
EMIF1_A19
External memory interface 2 write enable
External memory interface 1 address line 0
External memory interface 1 address line 1
External memory interface 1 address line 2
External memory interface 1 address line 3
External memory interface 1 address line 4
External memory interface 1 address line 5
External memory interface 1 address line 6
External memory interface 1 address line 7
External memory interface 1 address line 8
External memory interface 1 address line 9
External memory interface 1 address line 10
External memory interface 1 address line 11
External memory interface 1 address line 12
External memory interface 1 address line 13
External memory interface 1 address line 14
External memory interface 1 address line 15
External memory interface 1 address line 16
External memory interface 1 address line 17
External memory interface 1 address line 18
External memory interface 1 address line 19
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
120
U15
35, 38
T14, T16
71, 85
36, 39 V16, W17 83, 86
37, 40
38, 41
U16, V17
T16, U17
84, 87
85, 89
39, 44 K18, W17 113, 86
45, 49
46, 50
47, 51
48, 52
49, 53
50, 54
51
K19, R17 115, 93
E19, R18 128, 94
E18, R19 129, 95
P16, R16
P17, R17
P18, R18
R19
90, 96
93, 97
94, 98
95
52
P16
96
86
C11
156
87
D11
157
88
C6
170
89
D6
171
90
A5
172
91
B5
173
92
A4
174
20, 33,
93
B4, F2,
T13
13, 175,
69
EMIF1_BA0
External memory interface 1 bank address 0
O
21, 34,
92, 94
A3, A4,
F3, U14
14, 174,
176, 70
EMIF1_BA1
EMIF1_CS0n
EMIF1_CS2n
External memory interface 1 bank address 1
External memory interface 1 chip select 0
External memory interface 1 chip select 2
O
O
O
32
U13
67
18, 28,
34
E3, U14,
V11
10, 64,
70
19, 29,
35
E4, T14,
W11
12, 65,
71
EMIF1_CS3n
External memory interface 1 chip select 3
O
EMIF1_CS4n
EMIF1_D0
EMIF1_D1
EMIF1_D2
EMIF1_D3
EMIF1_D4
EMIF1_D5
EMIF1_D6
EMIF1_D7
EMIF1_D8
EMIF1_D9
EMIF1_D10
EMIF1_D11
External memory interface 1 chip select 4
External memory interface 1 data line 0
External memory interface 1 data line 1
External memory interface 1 data line 2
External memory interface 1 data line 3
External memory interface 1 data line 4
External memory interface 1 data line 5
External memory interface 1 data line 6
External memory interface 1 data line 7
External memory interface 1 data line 8
External memory interface 1 data line 9
External memory interface 1 data line 10
External memory interface 1 data line 11
O
28, 30
55, 85
T11, V11
63, 64
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
B11, P19 100, 155
56, 83 C14, N16 101, 151
57, 82
58, 81
B14, N18 102, 150
A14, N17 103, 149
59, 80 D15, M16 104, 148
60, 79 C15, M17 105, 146
61, 78
62, 77
76
B15, L16 107, 145
A15, J17 108, 144
C16
D16
C17
A16
143
142
141
140
75
74
73
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
www.ti.com
Table 6-3. Digital Signals (continued)
PIN
TYPE
SIGNAL NAME
EMIF1_D12
DESCRIPTION
GPIO
337 BGA 176 Pin
External memory interface 1 data line 12
External memory interface 1 data line 13
External memory interface 1 data line 14
External memory interface 1 data line 15
External memory interface 1 data line 16
External memory interface 1 data line 17
External memory interface 1 data line 18
External memory interface 1 data line 19
External memory interface 1 data line 20
External memory interface 1 data line 21
External memory interface 1 data line 22
External memory interface 1 data line 23
External memory interface 1 data line 24
External memory interface 1 data line 25
External memory interface 1 data line 26
External memory interface 1 data line 27
External memory interface 1 data line 28
External memory interface 1 data line 29
External memory interface 1 data line 30
External memory interface 1 data line 31
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
B16
B17
A17
B18
C18
B19
K17
K16
L17
J16
139
136
135
134
133
132
112
111
110
109
108
107
105
104
103
102
101
100
98
EMIF1_D13
EMIF1_D14
EMIF1_D15
EMIF1_D16
EMIF1_D17
EMIF1_D18
EMIF1_D19
EMIF1_D20
EMIF1_D21
EMIF1_D22
EMIF1_D23
EMIF1_D24
EMIF1_D25
EMIF1_D26
EMIF1_D27
EMIF1_D28
EMIF1_D29
EMIF1_D30
EMIF1_D31
J17
L16
M17
M16
N17
N18
N16
P19
P18
P17
97
External memory interface 1 Input/output mask for byte
0
24, 88,
92
A4, C6, 170, 174,
K3 24
EMIF1_DQM0
EMIF1_DQM1
EMIF1_DQM2
EMIF1_DQM3
O
O
O
O
External memory interface 1 Input/output mask for byte
1
25, 88,
89
C6, D6, 170, 171,
K2 25
External memory interface 1 Input/output mask for byte
2
26, 90,
91
A5, B5, 172, 173,
K1 27
External memory interface 1 Input/output mask for byte
3
27, 87,
91
B5, D11, 157, 173,
L1
28
EMIF2_A0
EMIF2_A1
EMIF2_A2
EMIF2_A3
EMIF2_A4
EMIF2_A5
EMIF2_A6
EMIF2_A7
EMIF2_A8
EMIF2_A9
EMIF2_A10
EMIF2_A11
EMIF2_A12
EMIF2_BA0
EMIF2_BA1
EMIF2_CS0n
EMIF2_CS2n
EMIF2_D0
External memory interface 2 address line 0
External memory interface 2 address line 1
External memory interface 2 address line 2
External memory interface 2 address line 3
External memory interface 2 address line 4
External memory interface 2 address line 5
External memory interface 2 address line 6
External memory interface 2 address line 7
External memory interface 2 address line 8
External memory interface 2 address line 9
External memory interface 2 address line 10
External memory interface 2 address line 11
External memory interface 2 address line 12
External memory interface 2 bank address 0
External memory interface 2 bank address 1
External memory interface 2 chip select 0
External memory interface 2 chip select 2
External memory interface 2 data line 0
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I/O
98
F1
99
G1
H1
H2
H3
J1
17
100
101
102
103
104
105
106
107
108
109
95
J2
J3
L2
L3
L4
N2
B3
M4
M3
V12
W10
111
112
115
116
138, 68 C18, T19
133
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
www.ti.com
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
Table 6-3. Digital Signals (continued)
PIN
SIGNAL NAME
DESCRIPTION
GPIO
337 BGA 176 Pin
TYPE
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
EMIF2_D1
EMIF2_D2
EMIF2_D3
EMIF2_D4
EMIF2_D5
EMIF2_D6
EMIF2_D7
EMIF2_D8
EMIF2_D9
External memory interface 2 data line 1
External memory interface 2 data line 2
External memory interface 2 data line 3
External memory interface 2 data line 4
External memory interface 2 data line 5
External memory interface 2 data line 6
External memory interface 2 data line 7
External memory interface 2 data line 8
External memory interface 2 data line 9
External memory interface 2 data line 10
External memory interface 2 data line 11
External memory interface 2 data line 12
External memory interface 2 data line 13
External memory interface 2 data line 14
External memory interface 2 data line 15
137, 67 B19, T18
136, 66 K17, T17
135, 65 K16, U18
134, 64 L17, V18
132, 63 J16, W18
131, 62 J17, V10
130, 61 L16, U10
129, 60 M17, T10
128, 59 M16, W9
132
112
111
110
109
108
107
105
104
103
102
101
100
98
EMIF2_D10
EMIF2_D11
EMIF2_D12
EMIF2_D13
EMIF2_D14
EMIF2_D15
127, 58
126, 57 N18, U9
N17, V9
125, 56
124, 55
123, 54
122, 53
N16, T9
P19, V8
P18, U8
P17, T8
97
External memory interface 2 Input/output mask for byte
0
EMIF2_DQM0
EMIF2_DQM1
O
O
97
96
A2
C3
External memory interface 2 Input/output mask for byte
1
EMAC management data clock, Output in MII/RMII
modes, Input in RevMII mode
ENET_MDIO_CLK
ENET_MDIO_DATA
I/O
I/O
105, 42
106, 43
D19, J3
C19, L2
130
131
EMAC management data
M2, T14,
U17,
W17
110, 35,
39, 41
71, 86,
89
ENET_MII_COL
EMAC MII collision detect
I
109, 34, N2, T16,
70, 85,
87
ENET_MII_CRS
ENET_MII_INTR
ENET_MII_RX_CLK
EMAC MII carrier sense
I
I/O
I
38, 40
U14, V17
EMAC PHY interrupt, Input in MII/RMII mode, Output
in RevMII mode
108, 68
C18, L4
133
111, 49, B18, B19, 132, 134,
EMAC MII receive clock
67, 69
M4, R17
93
114, 52, B17, J16,
109, 112,
136, 96
ENET_MII_RX_DATA0
EMAC MII / RMII receive data 0
I
63, 66,
71
K17, N3,
P16
115, 53, B16, L17, 110, 139,
ENET_MII_RX_DATA1
ENET_MII_RX_DATA2
ENET_MII_RX_DATA3
EMAC MII / RMII receive data 1
EMAC MII receive data 2
EMAC MII receive data 3
I
I
I
64, 72
116, 54, K16, P18,
65 W10
117, 55, K17, P19,
P17, V12
97
111, 98
100, 112
66
U12
112, 38, A17, L17,
50, 64, M3, R18,
EMAC MII receive data valid (or) RMII carrier sense/
receive data valid
110, 135,
85, 94
ENET_MII_RX_DV
I
70
T16
B17,
C16,
113, 39,
51, 65,
71, 76
111, 136,
ENET_MII_RX_ERR
ENET_MII_TX_CLK
EMAC MII / RMII receive error
EMAC MII transmit clock
I
I
K16, N4, 143, 86,
R19,
W17
95
120, 44,
58
K18,
N17, U15
103, 113
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
www.ti.com
Table 6-3. Digital Signals (continued)
PIN
TYPE
SIGNAL NAME
DESCRIPTION
GPIO
337 BGA 176 Pin
D16,
M16,
W16
121, 59,
75
ENET_MII_TX_DATA0
EMAC MII / RMII transmit data 0
O
104, 142
122, 60,
74
C17,
M17, T8
ENET_MII_TX_DATA1
ENET_MII_TX_DATA2
ENET_MII_TX_DATA3
ENET_MII_TX_EN
EMAC MII / RMII transmit data 1
EMAC MII transmit data 2
EMAC MII transmit data 3
EMAC MII / RMII transmit enable
EMAC MII transmit error
O
O
O
O
O
105, 141
107, 140
108, 139
123, 61, A16, L16,
73 U8
124, 62, B16, J17,
72 V8
118, 45, B18, K19, 101, 115,
56, 69
N16, T12
134
119, 46,
57
E19,
N18, T15
ENET_MII_TX_ERR
102, 128
ENET_PPS0
ENET_PPS1
EMAC Pulse Per Second Output 0
EMAC Pulse Per Second Output 1
O
O
47
48
E18
R16
129
90
107, 41, B19, L3,
ENET_REVMII_MDIO_RST
EMAC REVMII MDIO reset
I
132, 89
67
U17
ENET_RMII_CLK
EPWM10A
EPWM10B
EPWM11A
EPWM11B
EPWM12A
EPWM12B
EPWM13A
EPWM13B
EPWM14A
EPWM14B
EPWM15A
EPWM15B
EPWM16A
EPWM16B
EPWM1A
EPWM1B
EPWM2A
EPWM2B
EPWM3A
EPWM3B
EPWM4A
EPWM4B
EPWM5A
EPWM5B
EPWM6A
EPWM6B
EPWM7A
EPWM7B
EPWM8A
EMAC RMII clock
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
73
A16
140
10
12
13
14
22
23
24
25
27
28
64
65
63
66
160
161
162
163
164
165
166
167
18
19
1
ePWM-10 Output A (High-res available on ePWM1-8)
ePWM-10 Output B (High-res available on ePWM1-8)
ePWM-11 Output A (High-res available on ePWM1-8)
ePWM-11 Output B (High-res available on ePWM1-8)
ePWM-12 Output A (High-res available on ePWM1-8)
ePWM-12 Output B (High-res available on ePWM1-8)
ePWM-13 Output A (High-res available on ePWM1-8)
ePWM-13 Output B (High-res available on ePWM1-8)
ePWM-14 Output A (High-res available on ePWM1-8)
ePWM-14 Output B (High-res available on ePWM1-8)
ePWM-15 Output A (High-res available on ePWM1-8)
ePWM-15 Output B (High-res available on ePWM1-8)
ePWM-16 Output A (High-res available on ePWM1-8)
ePWM-16 Output B (High-res available on ePWM1-8)
ePWM-1 Output A (High-res available on ePWM1-8)
ePWM-1 Output B (High-res available on ePWM1-8)
ePWM-2 Output A (High-res available on ePWM1-8)
ePWM-2 Output B (High-res available on ePWM1-8)
ePWM-3 Output A (High-res available on ePWM1-8)
ePWM-3 Output B (High-res available on ePWM1-8)
ePWM-4 Output A (High-res available on ePWM1-8)
ePWM-4 Output B (High-res available on ePWM1-8)
ePWM-5 Output A (High-res available on ePWM1-8)
ePWM-5 Output B (High-res available on ePWM1-8)
ePWM-6 Output A (High-res available on ePWM1-8)
ePWM-6 Output B (High-res available on ePWM1-8)
ePWM-7 Output A (High-res available on ePWM1-8)
ePWM-7 Output B (High-res available on ePWM1-8)
ePWM-8 Output A (High-res available on ePWM1-8)
163, 18
164, 19
165, 20
166, 21
167, 22
168, 23
137, 24
138, 25
139, 26
140, 27
A8, E3
B8, E4
C5, F2
D5, F3
C4, J4
D4, K4
K3, T18
K2, T19
K1, N19
L1, M19
141, 28 M18, V11
142, 29 L19, W11
143, 30 F18, T11
144, 31 F17, U11
0, 145
1, 146
147, 2
148, 3
149, 4
150, 5
151, 6
152, 7
153, 8
154, 9
10, 155
11, 156
12, 157
C8, E17
D18, D8
A7, D17
B7, D14
A13, C7
B13, D7
A6, C13
B6, D13
A12, G2
B12, G3
B2, C12
C1, D12
B10, C2
2
4
13, 158 C10, D1
14, 159 D10, D2
5
6
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
www.ti.com
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
Table 6-3. Digital Signals (continued)
PIN
TYPE
SIGNAL NAME
DESCRIPTION
GPIO
337 BGA 176 Pin
EPWM8B
EPWM9A
EPWM9B
ePWM-8 Output B (High-res available on ePWM1-8)
ePWM-9 Output A (High-res available on ePWM1-8)
ePWM-9 Output B (High-res available on ePWM1-8)
O
15, 160
16, 161
162, 17
B9, D3
C9, E1
D9, E2
7
8
9
O
O
10, 20,
50, 96
B2, C3,
F2, R18
EQEP1_A
EQEP1_B
eQEP-1 Input A
eQEP-1 Input B
eQEP-1 Index
eQEP-1 Strobe
eQEP-2 Input A
eQEP-2 Input B
eQEP-2 Index
eQEP-2 Strobe
eQEP-3 Input A
eQEP-3 Input B
eQEP-3 Index
eQEP-3 Strobe
I
I
1, 13, 94
14, 2, 95
11, 21,
51, 97
A2, C1,
F3, R19
13, 23,
53, 99
D1, G1, 17, 23, 5,
K4, P17
EQEP1_INDEX
EQEP1_STROBE
EQEP2_A
I/O
I/O
I
97
12, 22,
52, 98
C2, F1,
J4, P16
22, 4, 96
100, 24, B15, H1, 145, 24,
54, 78 K3, P18 98
101, 25, C15, H2, 100, 146,
55, 79 K2, P19 25
EQEP2_B
I
103, 26, A14, J1, 102, 149,
57, 81 K1, N18 27
EQEP2_INDEX
EQEP2_STROBE
EQEP3_A
I/O
I/O
I
102, 27, D15, H3, 101, 148,
56, 80 L1, N16 28
104, 28, A6, J17, 108, 166,
6, 62 J2, V11 64
105, 29, B6, J16, 109, 167,
63, 7 J3, W11 65
EQEP3_B
I
107, 31, G3, K16, 111, 19,
65, 9 L3, U11 66
EQEP3_INDEX
EQEP3_STROBE
I/O
I/O
106, 30, G2, L17, 110, 18,
64, 8
0, 100
1, 101
102, 2
103, 3
104, 4
105, 5
106, 6
107, 7
108
L2, T11
C8, H1
D8, H2
A7, H3
B7, J1
C7, J2
D7, J3
A6, L2
B6, L3
L4
63
ESC_GPI0
ESC_GPI1
ESC_GPI2
ESC_GPI3
ESC_GPI4
ESC_GPI5
ESC_GPI6
ESC_GPI7
ESC_GPI8
ESC_GPI9
ESC_GPI10
ESC_GPI11
ESC_GPI12
ESC_GPI13
ESC_GPI14
ESC_GPI15
ESC_GPI16
ESC_GPI17
ESC_GPI18
ESC_GPI19
ESC_GPI20
EtherCAT General-Purpose Input 0
EtherCAT General-Purpose Input 1
EtherCAT General-Purpose Input 2
EtherCAT General-Purpose Input 3
EtherCAT General-Purpose Input 4
EtherCAT General-Purpose Input 5
EtherCAT General-Purpose Input 6
EtherCAT General-Purpose Input 7
EtherCAT General-Purpose Input 8
EtherCAT General-Purpose Input 9
EtherCAT General-Purpose Input 10
EtherCAT General-Purpose Input 11
EtherCAT General-Purpose Input 12
EtherCAT General-Purpose Input 13
EtherCAT General-Purpose Input 14
EtherCAT General-Purpose Input 15
EtherCAT General-Purpose Input 16
EtherCAT General-Purpose Input 17
EtherCAT General-Purpose Input 18
EtherCAT General-Purpose Input 19
EtherCAT General-Purpose Input 20
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
160
161
162
163
164
165
166
167
109
N2
110
M2
111
M4
112
M3
113
N4
114
N3
115
V12
116
W10
U12
117
118
T12
119
T15
120
U15
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
www.ti.com
Table 6-3. Digital Signals (continued)
PIN
TYPE
SIGNAL NAME
ESC_GPI21
DESCRIPTION
GPIO
337 BGA 176 Pin
EtherCAT General-Purpose Input 21
EtherCAT General-Purpose Input 22
EtherCAT General-Purpose Input 23
EtherCAT General-Purpose Input 24
EtherCAT General-Purpose Input 25
EtherCAT General-Purpose Input 26
EtherCAT General-Purpose Input 27
EtherCAT General-Purpose Input 28
EtherCAT General-Purpose Input 29
EtherCAT General-Purpose Input 30
EtherCAT General-Purpose Input 31
EtherCAT General-Purpose Output 0
EtherCAT General-Purpose Output 1
EtherCAT General-Purpose Output 2
EtherCAT General-Purpose Output 3
EtherCAT General-Purpose Output 4
EtherCAT General-Purpose Output 5
EtherCAT General-Purpose Output 6
EtherCAT General-Purpose Output 7
EtherCAT General-Purpose Output 8
EtherCAT General-Purpose Output 9
EtherCAT General-Purpose Output 10
EtherCAT General-Purpose Output 11
EtherCAT General-Purpose Output 12
EtherCAT General-Purpose Output 13
EtherCAT General-Purpose Output 14
EtherCAT General-Purpose Output 15
EtherCAT General-Purpose Output 16
EtherCAT General-Purpose Output 17
EtherCAT General-Purpose Output 18
EtherCAT General-Purpose Output 19
EtherCAT General-Purpose Output 20
EtherCAT General-Purpose Output 21
EtherCAT General-Purpose Output 22
EtherCAT General-Purpose Output 23
EtherCAT General-Purpose Output 24
EtherCAT General-Purpose Output 25
EtherCAT General-Purpose Output 26
EtherCAT General-Purpose Output 27
EtherCAT General-Purpose Output 28
EtherCAT General-Purpose Output 29
EtherCAT General-Purpose Output 30
EtherCAT General-Purpose Output 31
I
121
122
W16
T8
ESC_GPI22
ESC_GPI23
ESC_GPI24
ESC_GPI25
ESC_GPI26
ESC_GPI27
ESC_GPI28
ESC_GPI29
ESC_GPI30
ESC_GPI31
ESC_GPO0
ESC_GPO1
ESC_GPO2
ESC_GPO3
ESC_GPO4
ESC_GPO5
ESC_GPO6
ESC_GPO7
ESC_GPO8
ESC_GPO9
ESC_GPO10
ESC_GPO11
ESC_GPO12
ESC_GPO13
ESC_GPO14
ESC_GPO15
ESC_GPO16
ESC_GPO17
ESC_GPO18
ESC_GPO19
ESC_GPO20
ESC_GPO21
ESC_GPO22
ESC_GPO23
ESC_GPO24
ESC_GPO25
ESC_GPO26
ESC_GPO27
ESC_GPO28
ESC_GPO29
ESC_GPO30
ESC_GPO31
I
I
123
U8
I
124
V8
I
125
T9
I
126
U9
I
127
V9
I
128
W9
T10
U10
V10
I
129
I
130
I
131
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
132, 8
134, 9
10, 135
11, 136
12, 137
13, 138
G2, W18
G3, V18
B2, U18
C1, T17
C2, T18
D1, T19
18
19
1
2
4
5
139, 14 D2, N19
140, 15 D3, M19
6
7
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
M18
L19
F18
F17
E17
D18
D17
D14
A13
B13
C13
D13
A12
B12
C12
D12
B10
C10
D10
B9
C9
D9
A8
B8
151, 30, C13, T11,
41 U17
ESC_I2C_SCL
EtherCAT I2C Clock
I/OC
63, 89
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
Table 6-3. Digital Signals (continued)
PIN
TYPE
SIGNAL NAME
DESCRIPTION
GPIO
337 BGA 176 Pin
150, 29, B13, V17,
40 W11
ESC_I2C_SDA
ESC_LATCH0
ESC_LATCH1
EtherCAT I2C Data
I/OC
65, 87
65, 70
63, 71
125, 29, T9, U14,
34 W11
EtherCAT LatchSignal Input 0
EtherCAT LatchSignal Input 1
I
I
126, 30, T11, T14,
35 U9
ESC_LED_ERR
EtherCAT Error LED
EtherCAT Link-0 Active
EtherCAT Link-1 Active
EtherCAT Run LED
EtherCAT State Run
O
O
O
O
O
145, 60 E17, M17
143, 58 F18, N17
144, 59 F17, M16
146, 61 D18, L16
147, 62 D17, J17
105
103
104
107
108
ESC_LED_LINK0_ACTIVE
ESC_LED_LINK1_ACTIVE
ESC_LED_RUN
ESC_LED_STATE_RUN
152, 26,
46
D13,
E19, K1
ESC_MDIO_CLK
ESC_MDIO_DATA
EtherCAT MDIO Clock
EtherCAT MDIO Data
O
128, 27
129, 28
153, 27, A12, E18,
47 L1
I/O
ESC_PHY0_LINKSTATUS
ESC_PHY1_LINKSTATUS
ESC_PHY_CLK
EtherCAT PHY-0 Link Status
EtherCAT PHY-1 Link Status
EtherCAT PHY Clock
I
I
148, 86 C11, D14
149, 68 A13, C18
154, 48 B12, R16
155, 76 C12, C16
156
133
90
O
O
I
ESC_PHY_RESETn
ESC_RX0_CLK
EtherCAT PHY Active Low Reset
EtherCAT MII Receive-0 Clock
EtherCAT MII Receive-0 Data Valid
EtherCAT MII Receive-0 Error
EtherCAT MII Receive-1 Clock
EtherCAT MII Receive-1 Data Valid
EtherCAT MII Receive-1 Error
EtherCAT MII Receive-0 Data-0
EtherCAT MII Receive-0 Data-1
EtherCAT MII Receive-0 Data-2
EtherCAT MII Receive-0 Data-3
EtherCAT MII Receive-1 Data-0
EtherCAT MII Receive-1 Data-1
EtherCAT MII Receive-1 Data-2
EtherCAT MII Receive-1 Data-3
143
144
145
146
134
135
136
148
149
150
151
109
110
111
112
163, 77
162, 78
164, 79
A15, A8
B15, D9
B8, C15
ESC_RX0_DV
I
ESC_RX0_ERR
I
ESC_RX1_CLK
I
137, 69 B18, T18
136, 70 A17, T17
138, 71 B17, T19
165, 80 C5, D15
ESC_RX1_DV
I
ESC_RX1_ERR
I
ESC_RX0_DATA0
ESC_RX0_DATA1
ESC_RX0_DATA2
ESC_RX0_DATA3
ESC_RX1_DATA0
ESC_RX1_DATA1
ESC_RX1_DATA2
ESC_RX1_DATA3
I
I
166, 81
167, 82
A14, D5
B14, C4
I
I
168, 83 C14, D4
139, 63 J16, N19
140, 64 L17, M19
141, 65 K16, M18
142, 66 K17, L19
127, 29, U14, V9,
I
I
I
I
ESC_SYNC0
ESC_SYNC1
EtherCAT SyncSignal Output 0
EtherCAT SyncSignal Output 1
O
O
65, 70
63, 71
34
128, 30, T11, T14,
35 W9
W11
ESC_TX0_CLK
ESC_TX0_ENA
ESC_TX1_CLK
ESC_TX1_ENA
ESC_TX0_DATA0
ESC_TX0_DATA1
ESC_TX0_DATA2
ESC_TX0_DATA3
ESC_TX1_DATA0
EtherCAT MII Transmit-0 Clock
EtherCAT MII Transmit-0 Enable
EtherCAT MII Transmit-1 Clock
EtherCAT MII Transmit-1 Enable
EtherCAT MII Transmit-0 Data-0
EtherCAT MII Transmit-0 Data-1
EtherCAT MII Transmit-0 Data-2
EtherCAT MII Transmit-0 Data-3
EtherCAT MII Transmit-1 Data-0
I
I/O
I
157, 85 B10, B11
156, 84 A11, D12
130, 44 K18, U10
129, 45 K19, T10
158, 87 C10, D11
159, 88 C6, D10
155
154
113
115
157
170
171
172
142
I/O
O
O
O
O
O
160, 89
161, 90
B9, D6
A5, C9
131, 75 D16, V10
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
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Table 6-3. Digital Signals (continued)
PIN
TYPE
SIGNAL NAME
ESC_TX1_DATA1
DESCRIPTION
GPIO
337 BGA 176 Pin
C17,
141
EtherCAT MII Transmit-1 Data-1
O
132, 74
W18
ESC_TX1_DATA2
ESC_TX1_DATA3
EXTSYNCOUT
EtherCAT MII Transmit-1 Data-2
EtherCAT MII Transmit-1 Data-3
External ePWM Synchronization Pulse
O
O
O
134, 73 A16, V18
135, 72 B16, U18
140
139
166
6
A6
D1, D7,
G3, J3,
P18
105, 13,
5, 54, 9
165, 19,
5, 98
FSIRXA_CLK
FSIRXA_D0
FSIRXA_D1
FSIRX-A Input Clock
FSIRX-A Data Input 0
FSIRX-A Data Input 1
I
I
I
B7, C2,
G2, J1,
P16
103, 12,
3, 52, 8
163, 18,
4, 96
B2, C1,
C7, J2,
P17
10, 104,
11, 4, 53
1, 164, 2,
97
11, 112, C1, M17,
FSIRXB_CLK
FSIRXB_D0
FSIRXB_D1
FSIRX-B Input Clock
FSIRX-B Data Input 0
FSIRX-B Data Input 1
I
I
I
105, 2
103, 19
1, 104
60
M3
G3, M2,
N17
110, 58, 9
10, 111, B2, M16,
59
M4
FSIRXC_CLK
FSIRXC_D0
FSIRXC_D1
FSIRXD_CLK
FSIRXD_D0
FSIRXD_D1
FSIRXE_CLK
FSIRXE_D0
FSIRXE_D1
FSIRXF_CLK
FSIRXF_D0
FSIRXF_D1
FSIRXG_CLK
FSIRXG_D0
FSIRXG_D1
FSIRXH_CLK
FSIRXH_D0
FSIRXH_D1
FSIRX-C Input Clock
FSIRX-C Data Input 0
FSIRX-C Data Input 1
FSIRX-D Input Clock
FSIRX-D Data Input 0
FSIRX-D Data Input 1
FSIRX-E Input Clock
FSIRX-E Data Input 0
FSIRX-E Data Input 1
FSIRX-F Input Clock
FSIRX-F Data Input 0
FSIRX-F Data Input 1
FSIRX-G Input Clock
FSIRX-G Data Input 0
FSIRX-G Data Input 1
FSIRX-H Input Clock
FSIRX-H Data Input 0
FSIRX-H Data Input 1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
117, 14
115, 12
D2, U12
C2, V12
6
4
5
116, 13 D1, W10
120, 17
118, 15
119, 16
126, 20
E2, U15
D3, T12
E1, T15
F2, U9
9
7
8
13
121, 18 E3, W16
10
125, 19
23, 93
21, 91
22, 92
26, 96
24, 94
25, 95
29, 99
27, 97
28, 98
E4, T9
B4, K4
B5, F3
A4, J4
12
175, 23
14, 173
174, 22
27
C3, K1
A3, K3
B3, K2
G1, W11
A2, L1
F1, V11
176, 24
25
17, 65
28
64
A7, B2,
H3, L1,
R19
10, 102,
2, 27, 51
1, 162,
28, 95
FSITXA_CLK
FSITXA_D0
FSITX-A Output Clock
FSITX-A Data Output 0
O
O
C8, G3,
H1, K1,
R17
0, 100,
26, 49, 9
160, 19,
27, 93
D8, G2,
H2, K2,
R18
1, 101,
25, 50, 8
161, 18,
25, 94
FSITXA_D1
FSITX-A Data Output 1
FSITX-B Output Clock
O
O
108, 56,
8
G2, L4,
N16
FSITXB_CLK
101, 18
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
www.ti.com
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
Table 6-3. Digital Signals (continued)
PIN
TYPE
SIGNAL NAME
DESCRIPTION
GPIO
337 BGA 176 Pin
106, 55,
6
A6, L2,
100, 166
P19
FSITXB_D0
FSITXB_D1
FSITX-B Data Output 0
O
107, 57,
7
B6, L3,
102, 167
N18
FSITX-B Data Output 1
O
GPIO0
General-Purpose Input Output 0
General-Purpose Input Output 1
General-Purpose Input Output 2
General-Purpose Input Output 3
General-Purpose Input Output 4
General-Purpose Input Output 5
General-Purpose Input Output 6
General-Purpose Input Output 7
General-Purpose Input Output 8
General-Purpose Input Output 9
General-Purpose Input Output 10
General-Purpose Input Output 11
General-Purpose Input Output 12
General-Purpose Input Output 13
General-Purpose Input Output 14
General-Purpose Input Output 15
General-Purpose Input Output 16
General-Purpose Input Output 17
General-Purpose Input Output 18
General-Purpose Input Output 19
General-Purpose Input Output 100
General-Purpose Input Output 101
General-Purpose Input Output 102
General-Purpose Input Output 103
General-Purpose Input Output 104
General-Purpose Input Output 105
General-Purpose Input Output 106
General-Purpose Input Output 107
General-Purpose Input Output 108
General-Purpose Input Output 109
General-Purpose Input Output 110
General-Purpose Input Output 111
General-Purpose Input Output 112
General-Purpose Input Output 113
General-Purpose Input Output 114
General-Purpose Input Output 115
General-Purpose Input Output 116
General-Purpose Input Output 117
General-Purpose Input Output 118
General-Purpose Input Output 119
General-Purpose Input Output 120
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
C8
D8
A7
B7
C7
D7
A6
B6
G2
G3
B2
C1
C2
D1
D2
D3
E1
E2
E3
E4
H1
H2
H3
J1
160
161
162
163
164
165
166
167
18
19
1
GPIO1
1
GPIO2
2
GPIO3
3
GPIO4
4
GPIO5
5
GPIO6
6
GPIO7
7
GPIO8
8
GPIO9
9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO100
GPIO101
GPIO102
GPIO103
GPIO104
GPIO105
GPIO106
GPIO107
GPIO108
GPIO109
GPIO110
GPIO111
GPIO112
GPIO113
GPIO114
GPIO115
GPIO116
GPIO117
GPIO118
GPIO119
GPIO120
10
11
2
12
4
13
5
14
6
15
7
16
8
17
9
18
10
12
19
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
J2
J3
L2
L3
L4
N2
M2
M4
M3
N4
N3
V12
W10
U12
T12
T15
U15
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
www.ti.com
Table 6-3. Digital Signals (continued)
PIN
TYPE
SIGNAL NAME
DESCRIPTION
GPIO
337 BGA 176 Pin
GPIO121
GPIO122
GPIO123
GPIO124
GPIO125
GPIO126
GPIO127
GPIO128
GPIO129
GPIO130
GPIO131
GPIO132
GPIO133
GPIO134
GPIO135
GPIO136
GPIO137
GPIO138
GPIO139
GPIO140
GPIO141
GPIO142
GPIO143
GPIO144
GPIO145
GPIO146
GPIO147
GPIO148
GPIO149
GPIO150
GPIO151
GPIO152
GPIO153
GPIO154
GPIO155
GPIO156
GPIO157
GPIO158
GPIO159
GPIO160
GPIO161
GPIO162
GPIO163
GPIO164
GPIO165
General-Purpose Input Output 121
General-Purpose Input Output 122
General-Purpose Input Output 123
General-Purpose Input Output 124
General-Purpose Input Output 125
General-Purpose Input Output 126
General-Purpose Input Output 127
General-Purpose Input Output 128
General-Purpose Input Output 129
General-Purpose Input Output 130
General-Purpose Input Output 131
General-Purpose Input Output 132
General-Purpose Input Output 133
General-Purpose Input Output 134
General-Purpose Input Output 135
General-Purpose Input Output 136
General-Purpose Input Output 137
General-Purpose Input Output 138
General-Purpose Input Output 139
General-Purpose Input Output 140
General-Purpose Input Output 141
General-Purpose Input Output 142
General-Purpose Input Output 143
General-Purpose Input Output 144
General-Purpose Input Output 145
General-Purpose Input Output 146
General-Purpose Input Output 147
General-Purpose Input Output 148
General-Purpose Input Output 149
General-Purpose Input Output 150
General-Purpose Input Output 151
General-Purpose Input Output 152
General-Purpose Input Output 153
General-Purpose Input Output 154
General-Purpose Input Output 155
General-Purpose Input Output 156
General-Purpose Input Output 157
General-Purpose Input Output 158
General-Purpose Input Output 159
General-Purpose Input Output 160
General-Purpose Input Output 161
General-Purpose Input Output 162
General-Purpose Input Output 163
General-Purpose Input Output 164
General-Purpose Input Output 165
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
W16
T8
U8
V8
T9
U9
V9
W9
T10
U10
V10
W18
G18
V18
U18
T17
T18
T19
N19
M19
M18
L19
F18
F17
E17
D18
D17
D14
A13
B13
C13
D13
A12
B12
C12
D12
B10
C10
D10
B9
118
C9
D9
A8
B8
C5
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
Table 6-3. Digital Signals (continued)
PIN
SIGNAL NAME
DESCRIPTION
GPIO
337 BGA 176 Pin
TYPE
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO166
GPIO167
GPIO168
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
GPIO39
GPIO40
GPIO41
GPIO42
GPIO43
GPIO44
GPIO45
GPIO46
GPIO47
GPIO48
GPIO49
GPIO50
GPIO51
GPIO52
GPIO53
GPIO54
GPIO55
GPIO56
GPIO57
GPIO58
GPIO59
GPIO60
GPIO61
General-Purpose Input Output 166
General-Purpose Input Output 167
General-Purpose Input Output 168
General-Purpose Input Output 20
General-Purpose Input Output 21
General-Purpose Input Output 22
General-Purpose Input Output 23
General-Purpose Input Output 24
General-Purpose Input Output 25
General-Purpose Input Output 26
General-Purpose Input Output 27
General-Purpose Input Output 28
General-Purpose Input Output 29
General-Purpose Input Output 30
General-Purpose Input Output 31
General-Purpose Input Output 32
General-Purpose Input Output 33
General-Purpose Input Output 34
General-Purpose Input Output 35
General-Purpose Input Output 36
General-Purpose Input Output 37
General-Purpose Input Output 38
General-Purpose Input Output 39
General-Purpose Input Output 40
General-Purpose Input Output 41
General-Purpose Input Output 42
General-Purpose Input Output 43
General-Purpose Input Output 44
General-Purpose Input Output 45
General-Purpose Input Output 46
General-Purpose Input Output 47
General-Purpose Input Output 48
General-Purpose Input Output 49
General-Purpose Input Output 50
General-Purpose Input Output 51
General-Purpose Input Output 52
General-Purpose Input Output 53
General-Purpose Input Output 54
General-Purpose Input Output 55
General-Purpose Input Output 56
General-Purpose Input Output 57
General-Purpose Input Output 58
General-Purpose Input Output 59
General-Purpose Input Output 60
General-Purpose Input Output 61
166
167
168
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
D5
C4
D4
F2
F3
13
14
J4
22
K4
23
K3
24
K2
25
K1
27
L1
28
V11
W11
T11
U11
U13
T13
U14
T14
V16
U16
T16
W17
V17
U17
D19
C19
K18
K19
E19
E18
R16
R17
R18
R19
P16
P17
P18
P19
N16
N18
N17
M16
M17
L16
64
65
63
66
67
69
70
71
83
84
85
86
87
89
130
131
113
115
128
129
90
93
94
95
96
97
98
100
101
102
103
104
105
107
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
www.ti.com
Table 6-3. Digital Signals (continued)
PIN
TYPE
SIGNAL NAME
DESCRIPTION
GPIO
337 BGA 176 Pin
GPIO62
GPIO63
GPIO64
GPIO65
GPIO66
GPIO67
GPIO68
GPIO69
GPIO70
GPIO71
GPIO72
GPIO73
GPIO74
GPIO75
GPIO76
GPIO77
GPIO78
GPIO79
GPIO80
GPIO81
GPIO82
GPIO83
GPIO84
GPIO85
GPIO86
GPIO87
GPIO88
GPIO89
GPIO90
GPIO91
GPIO92
GPIO93
GPIO94
GPIO95
GPIO96
GPIO97
GPIO98
GPIO99
General-Purpose Input Output 62
General-Purpose Input Output 63
General-Purpose Input Output 64
General-Purpose Input Output 65
General-Purpose Input Output 66
General-Purpose Input Output 67
General-Purpose Input Output 68
General-Purpose Input Output 69
General-Purpose Input Output 70
General-Purpose Input Output 71
General-Purpose Input Output 72
General-Purpose Input Output 73
General-Purpose Input Output 74
General-Purpose Input Output 75
General-Purpose Input Output 76
General-Purpose Input Output 77
General-Purpose Input Output 78
General-Purpose Input Output 79
General-Purpose Input Output 80
General-Purpose Input Output 81
General-Purpose Input Output 82
General-Purpose Input Output 83
General-Purpose Input Output 84
General-Purpose Input Output 85
General-Purpose Input Output 86
General-Purpose Input Output 87
General-Purpose Input Output 88
General-Purpose Input Output 89
General-Purpose Input Output 90
General-Purpose Input Output 91
General-Purpose Input Output 92
General-Purpose Input Output 93
General-Purpose Input Output 94
General-Purpose Input Output 95
General-Purpose Input Output 96
General-Purpose Input Output 97
General-Purpose Input Output 98
General-Purpose Input Output 99
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
J17
J16
L17
K16
K17
B19
C18
B18
A17
B17
B16
A16
C17
D16
C16
A15
B15
C15
D15
A14
B14
C14
A11
B11
C11
D11
C6
108
109
110
111
112
132
133
134
135
136
139
140
141
142
143
144
145
146
148
149
150
151
154
155
156
157
170
171
172
173
174
175
176
D6
A5
B5
A4
B4
A3
B3
C3
A2
F1
G1
17
1, 105,
32, 33,
43, 57, N18, T13,
A4, C19,
D8, J3,
102, 131,
161, 174,
67, 69
I2CA_SCL
I2CA_SDA
I2C-A Open-Drain Bidirectional Clock
I2C-A Open-Drain Bidirectional Data
I/OD
I/OD
92
U13
0, 104,
31, 32,
42, 56, N16, U11,
91 U13
B5, C8,
D19, J2,
101, 130,
160, 173,
66, 67
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
Table 6-3. Digital Signals (continued)
PIN
TYPE
SIGNAL NAME
DESCRIPTION
I2C-B Open-Drain Bidirectional Clock
I2C-B Open-Drain Bidirectional Data
GPIO
337 BGA 176 Pin
3, 35, 41, B18, B7, 134, 163,
69 T14, U17 71, 89
I2CB_SCL
I2CB_SDA
I/OD
2, 34, 40, A7, K17, 112, 162,
I/OD
I
66
U14, V17
70, 87
10, 18,
A17, B2,
1, 10,
23, 30, D16, D7, 135, 142,
36, 5, 70, E3, K4,
MCAN_RX
MCAN_TX
CAN/CAN-FD Receive
CAN/CAN-FD Transmit
165, 23,
63, 83
75
T11, V16
B17,
12, 136,
141, 164,
18, 22,
19, 22, C17, C7,
31, 37, 4, E4, G2,
71, 74, 8 J4, U11,
U16
O
66, 84
MCLKRA
MCLKRB
McBSP-A Receive Clock
McBSP-B Receive Clock
I
I
58, 7
3, 60
B6, N17 103, 167
B7, M17 105, 163
167, 22, C11, C4,
MCLKXA
MCLKXB
MDRA
McBSP-A Transmit Clock
O
O
I
156, 22
86
J4
14, 26,
86
C11, D2, 156, 27,
McBSP-B Transmit Clock
K1
6
166, 21, B11, D5,
McBSP-A Receive Serial Data
McBSP-B Receive Serial Data
McBSP-A Transmit Serial Data
McBSP-B Transmit Serial Data
14, 155
85
F3
13, 25,
85
B11, D1, 155, 25,
MDRB
I
K2
5
165, 20, A11, C5,
MDXA
O
O
13, 154
84
F2
12, 24,
84
A11, C2, 154, 24,
K3
MDXB
4
MFSRA
MFSRB
McBSP-A Receive Frame Sync
McBSP-B Receive Frame Sync
I
I
5, 59
1, 61
D7, M16 104, 165
D8, L16 107, 161
168, 23, D11, D4,
MFSXA
MFSXB
McBSP-A Transmit Frame Sync
McBSP-B Transmit Frame Sync
Output X-BAR Output 1
O
O
O
O
157, 23
87
K4
D11, D3, 157, 28,
L1
15, 27,
87
7
2, 24, 34, A7, K3, 103, 162,
58 N17, U14 24, 70
OUTPUTXBAR1
OUTPUTXBAR2
25, 3, 37, B7, K2, 104, 163,
Output X-BAR Output 2
59
M16, U16 25, 84
C7, D2, 105, 164,
14, 26, 4,
48, 5, 60
OUTPUTXBAR3
OUTPUTXBAR4
Output X-BAR Output 3
Output X-BAR Output 4
O
O
D7, K1,
165, 27,
6, 90
M17, R16
A6, D3,
L1, L16,
R17
15, 27,
49, 6, 61
107, 166,
28, 7, 93
B6, V11,
V12
OUTPUTXBAR5
OUTPUTXBAR6
OUTPUTXBAR7
Output X-BAR Output 5
Output X-BAR Output 6
Output X-BAR Output 7
O
O
O
115, 28, 7
116, 29, 9
11, 16, 30
167, 64
19, 65
G3, W10,
W11
C1, E1,
T11
2, 63, 8
OUTPUTXBAR8
PMBUSA_ALERT
PMBUSA_CTL
PMBUSA_SCL
Output X-BAR Output 8
O
I/OD
I
17, 31
26, 93
27, 94
24, 91
E2, U11
B4, K1
A3, L1
B5, K3
66, 9
PMBus-A Open-Drain Bidirectional Alert Signal
PMBus-A Control Signal
175, 27
176, 28
173, 24
PMBus-A Open-Drain Bidirectional Clock
I/OD
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
www.ti.com
Table 6-3. Digital Signals (continued)
PIN
TYPE
SIGNAL NAME
PMBUSA_SDA
DESCRIPTION
GPIO
337 BGA 176 Pin
PMBus-A Open-Drain Bidirectional Data
I/OD
I
25, 92
A4, K2
174, 25
136, 28, B11, C19, 110, 131,
35, 43, G3, L17, 155, 19,
49, 64, R17, T14, 64, 71,
SCIA_RX
SCI-A Receive Data
SCI-A Transmit Data
85, 9
T17, V11
93
A11, D19,
135, 29, G2, K16, 111, 130,
34, 36,
42, 48,
R16,
U14,
U18,
154, 18,
65, 70,
83, 90
SCIA_TX
O
65, 8, 84
V16, W11
11, 138, B17, C1,
100, 12,
136, 157,
2, 23, 7
15, 19,
23, 55,
71, 87
D11, D3,
E4, K4,
P19, T19
SCIB_RX
SCIB_TX
SCI-B Receive Data
SCI-B Transmit Data
I
A17, B2,
C11, D2,
E3, G3,
J4, P18,
T18
10, 137,
14, 18,
22, 54,
1, 10,
135, 156,
19, 22, 6,
98
O
70, 86, 9
A16, A5,
D1, J17, 102, 108,
L3, N18, 140, 172,
N19,
W17
107, 13,
139, 39,
57, 62,
73, 90
SCIC_RX
SCIC_TX
SCI-C Receive Data
SCI-C Transmit Data
I
5, 86
106, 12, B16, C2,
140, 38, D6, J16,
101, 109,
139, 171,
4, 85
O
56, 63,
72, 89
L2, M19,
N16, T16
105, 141, A15, A3,
128, 144,
176
SCID_RX
SCID_TX
SD1_C1
SD1_C2
SD1_C3
SD1_C4
SD1_D1
SD1_D2
SD1_D3
SCI-D Receive Data
I
O
I
46, 77,
94
E19, J3,
M18
104, 142, B4, C16,
129, 143,
175
SCI-D Transmit Data
47, 76,
93
E18, J2,
L19
123, 17, E2, L17,
110, 9,
93, 97
SDFM-1 Channel 1 Clock Input
SDFM-1 Channel 2 Clock Input
SDFM-1 Channel 3 Clock Input
SDFM-1 Channel 4 Clock Input
SDFM-1 Channel 1 Data Input
SDFM-1 Channel 2 Data Input
SDFM-1 Channel 3 Data Input
49, 53,
64
P17,
R17, U8
125, 19, E4, K17,
112, 12,
95, 98
I
51, 54,
66
P18,
R19, T9
127, 21, C18, F3,
53, 55, P17, P19,
100, 133,
14, 97
I
68
V9
129, 23, A17, K4,
100, 101,
135, 23
I
55, 56,
70
N16,
P19, T10
122, 16, E1, J16,
109, 8,
83, 90
I
36, 48,
63
R16, T8,
V16
124, 18, E3, K16,
10, 111,
84, 94
I
37, 50,
65
R18,
U16, V8
126, 20, B19, F2,
38, 52, P16, T16,
13, 132,
85, 96
I
67
U9
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
www.ti.com
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
Table 6-3. Digital Signals (continued)
PIN
TYPE
SIGNAL NAME
DESCRIPTION
GPIO
337 BGA 176 Pin
128, 22, B18, J4,
134, 22,
86, 98
SD1_D4
SD2_C1
SD2_C2
SDFM-1 Channel 4 Data Input
I
39, 54,
69
P18,
W17, W9
131, 25, D15, K2, 102, 148,
SDFM-2 Channel 1 Clock Input
SDFM-2 Channel 2 Clock Input
I
I
57, 80
N18, V10
25
133, 27,
58, 59,
74
C17,
103, 104,
G18, L1, 118, 141,
M16, N17
28
135, 29, C16, L16,
104, 107,
143, 65
SD2_C3
SD2_C4
SD2_D1
SDFM-2 Channel 3 Clock Input
SDFM-2 Channel 4 Clock Input
SDFM-2 Channel 1 Data Input
I
I
I
59, 61,
76
M16,
U18, W11
137, 31, B15, J16,
105, 109,
145, 66
60, 63,
78
M17,
T18, U11
130, 24, C15, K3,
101, 146,
24, 93
49, 56,
79
N16,
R17, U10
A16, K1,
N17,
R18,
132, 26,
50, 58,
73
103, 140,
27, 94
SD2_D2
SD2_D3
SDFM-2 Channel 2 Data Input
I
W18
D16,
M17,
R19, V11, 64, 95
V18
134, 28,
51, 60,
75
105, 142,
SDFM-2 Channel 3 Data Input
SDFM-2 Channel 4 Data Input
I
I
136, 30, A15, J17,
52, 62, P16, T11,
108, 144,
63, 96
SD2_D4
77
T17
18, 34, E3, M17, 10, 101,
56, 60 N16, U14 105, 70
SPIA_CLK
SPI-A Clock
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
16, 32,
54, 58
E1, N17, 103, 67,
P18, U13 8, 98
SPIA_SIMO
SPIA_SOMI
SPIA_STEn
SPIB_CLK
SPI-A Slave In, Master Out (SIMO)
SPI-A Slave Out, Master In (SOMI)
SPI-A Slave Transmit Enable (STE)
SPI-B Clock
17, 33, E2, M16, 100, 104,
55, 59
P19, T13
E4, L16, 102, 107,
N18, T14 12, 71
J4, K1, 103, 111,
K16, N17 22, 27
J16, K3, 105, 109,
M17 24
K2, L16, 107, 110,
L17 25
K17, K4, 104, 112,
69, 9
19, 35,
57, 61
22, 26,
58, 65
24, 60,
63
SPIB_SIMO
SPIB_SOMI
SPIB_STEn
SPI-B Slave In, Master Out (SIMO)
SPI-B Slave Out, Master In (SOMI)
SPI-B Slave Transmit Enable (STE)
25, 61,
64
23, 27,
59, 66
L1, M16
23, 28
102, 124, B17, H3,
136, 22,
96
SPIC_CLK
SPIC_SIMO
SPIC_SOMI
SPIC_STEn
SPI-C Clock
I/O
I/O
I/O
I/O
22, 52,
71
J4, P16,
V8
100, 122, B18, F2,
20, 50, H1, R18,
13, 134,
94
SPI-C Slave In, Master Out (SIMO)
SPI-C Slave Out, Master In (SOMI)
SPI-C Slave Transmit Enable (STE)
69
T8
101, 123, A17, F3,
21, 51, H2, R19,
135, 14,
95
70
U8
103, 125, B16, J1,
139, 23,
97
23, 53,
72
K4, P17,
T9
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
www.ti.com
Table 6-3. Digital Signals (continued)
PIN
TYPE
SIGNAL NAME
DESCRIPTION
GPIO
337 BGA 176 Pin
SPID_CLK
SPI-D Clock
I/O
I/O
I/O
I/O
32, 93
30, 91
31, 92
33, 94
B4, U13
B5, T11
A4, U11
A3, T13
B4, E3,
175, 67
173, 63
174, 66
176, 69
10, 101,
SPID_SIMO
SPID_SOMI
SPID_STEn
SPI-D Slave In, Master Out (SIMO)
SPI-D Slave Out, Master In (SOMI)
SPI-D Slave Transmit Enable (STE)
18, 56,
65, 93
SSIA_CLK
SSIA_FSS
SSIA_RX
SSIA_TX
SSI-A Clock
I/O
I/O
I/O
I/O
K16, N16 111, 175
19, 57,
66, 94
A3, E4, 102, 112,
K17, N18 12, 176
SSI-A Frame Sync
17, 55,
64, 92
A4, E2, 100, 110,
L17, P19
SSI-A Serial Data Receive
SSI-A Serial Data Transmit
174, 9
16, 54,
63, 91
B5, E1, 109, 173,
J16, P18
K3
8, 98
24
TRACE_CLK
TRACE_DATA0
TRACE_DATA1
TRACE_DATA2
TRACE_DATA3
TRACE_SWO
UARTA_RX
Trace Clock
O
O
24
20
Trace Data 0
F2
13
Trace Data 1
O
21
F3
14
Trace Data 2
O
22
J4
22
Trace Data 3
O
23
K4
23
Trace Single Wire Out
UART-A Serial Data Receive
UART-A Serial Data Transmit
USB-0 PHY differential data
USB-0 PHY differential data
O
25
K2
25
I/O
I/O
O
43, 85
42, 84
42
B11, C19 131, 155
A11, D19 130, 154
UARTA_TX
USB0DM
D19
C19
130
131
USB0DP
O
43
External Clock Output. This pin outputs a divided-down
version of a chosen clock signal from within the device.
XCLKOUT
O
73
A16
140
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
6.3.3 Power and Ground
Table 6-4. Power and Ground
PIN
TYPE
SIGNAL NAME
DESCRIPTION
GPIO
337 BGA 176 Pin
1.2-V Digital Logic Power Pins. TI recommends
placing a decoupling capacitor near each VDD pin with
a minimum total capacitance of approximately 20 µF.
The exact value of the decoupling capacitance should
be determined by your system voltage regulation
solution. A single 56Ω resistor (10% tolerance) should
be placed between between VDD and VSS. This
resistor provides a load to consume an internal
VDD3VFL to VDD current source and avoid VDD
voltage rising during low power device conditions.
E11, E9,
F11, F9,
117, 126,
G14,
137, 153,
G15, J14,
158, 16,
J15, K5,
169, 21,
K6, P10,
61, 76
VDD
P13,
R10, R13
3.3-V Flash power pin. Place a minimum 0.1-µF
decoupling capacitor on each pin
VDD3VFL
VDDA
R11, R12
P6, R6
72
3.3-V Analog Power Pins. Place a minimum 2.2-µF
decoupling capacitor to VSSA on each pin.
36, 54
A18, A9,
B1, E10,
E13, E16,
E7, F10,
F13, F16,
F4, F7,
G4, G5,
G6, H5,
H6, L14,
L15, M1,
M5, M6,
N14,
106, 11,
114, 116,
127, 138,
147, 15,
152, 159,
168, 20,
26, 3, 62,
68, 75,
3.3-V Digital I/O Power Pins. Place a minimum 0.1-µF
decoupling capacitor on each pin.
VDDIO
82, 88,
91, 99
N15, P9,
R9, V19,
W8
Power pins for the 3.3-V on-chip crystal oscillator (X1
and X2) and the two zero-pin internal oscillators
(INTOSC). Place a 0.1-μF (minimum) decoupling
capacitor on each pin.
VDDOSC
H16, H17 120, 125
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
www.ti.com
Table 6-4. Power and Ground (continued)
PIN
TYPE
SIGNAL NAME
DESCRIPTION
GPIO
337 BGA 176 Pin
A1, A10,
A19, E12,
E14, E15,
E5, E6,
E8, F12,
F14, F15,
F5, F6,
F8, G16,
G17,
H10, H11,
H12,
H14,
H15, H8,
H9, J10,
J11, J12,
J5, J6,
J8, J9,
K10, K11,
K12, K14, 177, 178,
K15, K8, 179, 180
K9, L10,
L11, L12,
L18, L5,
L6, L8,
VSS
Digital Ground
L9, M10,
M11,
M12,
M14,
M15, M8,
M9, N1,
N5, N6,
P11, P12,
P14, P15,
P7, P8,
R14,
R15, R7,
R8, W19,
W7
P1, P5,
VSSA
Analog Ground
R5, V7,
W1
34, 52
122
Crystal oscillator (X1 and X2) ground pin. When using
an external crystal, do not connect this pin to the board
ground. Instead, connect it to the ground reference of
the external crystal oscillator circuit. If an external
crystal is not used, this pin may be connected to the
board ground.
VSSOSC
H18, H19
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
6.3.4 Test, JTAG, and Reset
Table 6-5. Test, JTAG, and Reset
PIN
TYPE
SIGNAL NAME
DESCRIPTION
GPIO
337 BGA 176 Pin
Error Status Output. When used, this signal requires
an external pulldown.
ERRORSTS
FLT1
O
U19
W12
V13
92
73
74
Flash test pin 1. Reserved for TI. Must be left
unconnected.
I/O
I/O
Flash test pin 2. Reserved for TI. Must be left
unconnected.
FLT2
No Connection. This pin is not internally connected to
the device. This pin may be left open or connected to
any voltage within the maximum operating conditions.
NC
H4, J18
V15
119
81
JTAG test-mode select (TMS) with internal pullup. This
serial control input is clocked into the TAP controller on
the rising edge of TCK.
TCK
TDI
I
I
JTAG test data input (TDI) with internal pullup. TDI is
clocked into the selected register (instruction or data)
on a rising edge of TCK.
W13
77
JTAG scan out, test data output (TDO). The contents
of the selected register (instruction or data) are shifted
out of TDO on the falling edge of TCK.
TDO
O
W15
78
JTAG test-mode select (TMS) with internal pullup. This
serial control input is clocked into the TAP controller on
the rising edge of TCK. An external pullup resistor
(recommended 2.2 kΩ) on the TMS pin to VDDIO
should be placed on the board to keep JTAG in reset
during normal operation.
TMS
I
W14
80
JTAG test reset with internal pulldown. TRSTn, when
driven high, gives the scan system control of the
operations of the device. If this signal is driven low, the
device operates in its functional mode, and the test
reset signals are ignored. NOTE: TRST must be
maintained low at all times during normal device
operation. An external pulldown resistor is required on
this pin. The value of this resistor should be based on
drive strength of the debugger pods applicable to the
design. A 2.2-kΩ or smaller resistor generally offers
adequate protection. The value of the resistor is
application-specific. TI recommends that each target
board be validated for proper operation of the
debugger and the application. This pin has an internal
50-ns (nominal) glitch filter.
TRSTn
I
V14
79
Crystal oscillator input or single-ended clock input. The
device initialization software must configure this pin
before the crystal oscillator is enabled. To use this
oscillator, a quartz crystal circuit must be connected to
X1 and X2. This pin can also be used to feed a single-
ended 3.3-V level clock.
X1
X2
I
G19
J19
123
121
Crystal oscillator output.
O
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
www.ti.com
Table 6-5. Test, JTAG, and Reset (continued)
PIN
TYPE
SIGNAL NAME
DESCRIPTION
GPIO
337 BGA 176 Pin
Device Reset (in) and Watchdog Reset (out). During a
power-on condition, this pin is driven low by the
device. An external circuit may also drive this pin to
assert a device reset. This pin is also driven low by the
MCU when a watchdog reset occurs. During watchdog
reset, the XRSn pin is driven low for the watchdog
reset duration of 512 OSCCLK cycles. A resistor
between 2.2 kΩ and 10 kΩ should be placed between
XRSn and VDDIO. If a capacitor is placed between
XRSn and VSS for noise filtering, it should be 100 nF
or smaller. These values will allow the watchdog to
properly drive the XRSn pin to VOL within 512
OSCCLK cycles when the watchdog reset is asserted.
The output buffer of this pin is an open-drain with an
internal pullup. If this pin is driven by an external
device, it should be done using an open-drain device.
If this pin is driven by an external device, it should be
done using an open-drain device.
XRSn
I/OD
F19
124
6.4 Pins With Internal Pullup and Pulldown
Some pins on the device have internal pullups or pulldowns. Table 6-6 lists the pull direction and when it is
active. The pullups on GPIO pins are disabled by default and can be enabled through software. In order to avoid
any floating unbonded inputs, the Boot ROM will enable internal pullups on GPIO pins that are not bonded out in
a particular package. Other pins noted in Table 6-6 with pullups and pulldowns are always on and cannot be
disabled.
Table 6-6. Pins With Internal Pullup and Pulldown
RESET
(XRSn = 0)
PIN
DEVICE BOOT
APPLICATION SOFTWARE
Pullup enable is application-
defined
GPIOx
Pullup disabled
Pullup disabled(1)
TRSTn
TCK
Pulldown active
Pullup active
TMS
Pullup active
TDI
Pullup active
XRSn
Pullup active
ERRORSTS
DACOUTx
Other pins
Pulldown active
Pulldown active
No pullup or pulldown present
(1) Pins not bonded out in a given package will have the internal pullups enabled by the Boot ROM.
6.5 Pin Multiplexing
GPIO muxed pins are listed in the GPIO Muxed Pins table in Section 6.5.1.
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
6.5.1 GPIO Muxed Pins Table
Table 6-7. GPIO Muxed Pins
0, 4, 8, 12
GPIO0
1
2
3
5
6
7
9
10
11
13
14
15
ALT
EPWM1A
EPWM1B
EPWM2A
EPWM2B
EPWM3A
EPWM3B
EPWM4A
EPWM4B
I2CA_SDA
I2CA_SCL
I2CB_SDA
I2CB_SCL
CANA_TX
CANA_RX
CANB_TX
CANB_RX
CM-I2CA_SDA
CM-I2CA_SCL
ESC_GPI0
ESC_GPI1
ESC_GPI2
ESC_GPI3
ESC_GPI4
ESC_GPI5
ESC_GPI6
ESC_GPI7
FSITXA_D0
FSITXA_D1
FSITXA_CLK
FSIRXA_D0
FSIRXA_D1
FSIRXA_CLK
FSITXB_D0
FSITXB_D1
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
MFSRB
OUTPUTXBAR1
OUTPUTXBAR2
OUTPUTXBAR3
OUTPUTXBAR2
MFSRA
MCLKRB
MCAN_TX
MCAN_RX
OUTPUTXBAR3
OUTPUTXBAR4 EXTSYNCOUT
EQEP3_A
EQEP3_B
MCLKRA
OUTPUTXBAR5
ADCSOCAO
EQEP3_STROB
E
GPIO8
EPWM5A
CANB_TX
SCIA_TX
MCAN_TX
MCAN_RX
ESC_GPO0
FSITXB_CLK
FSITXA_D1
FSIRXA_D0
GPIO9
EPWM5B
EPWM6A
EPWM6B
SCIB_TX
CANB_RX
SCIB_RX
OUTPUTXBAR6 EQEP3_INDEX
SCIA_RX
SCIB_TX
SCIB_RX
ESC_GPO1
ESC_GPO2
ESC_GPO3
FSIRXB_D0
FSIRXB_D1
FSIRXB_CLK
FSITXA_D0
FSITXA_CLK
FSIRXA_D1
FSIRXA_CLK
FSIRXA_D1
GPIO10
GPIO11
ADCSOCBO
EQEP1_A
EQEP1_B
OUTPUTXBAR7
EQEP1_STROB
E
GPIO12
EPWM7A
CANB_TX
MDXB
SCIC_TX
ESC_GPO4
FSIRXC_D0
FSIRXA_D0
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
EPWM7B
EPWM8A
CANB_RX
SCIB_TX
SCIB_RX
CANB_TX
CANB_RX
SCIB_TX
SCIB_RX
MDXA
MDRB
MCLKXB
EQEP1_INDEX
SCIC_RX
ESC_GPO5
ESC_GPO6
ESC_GPO7
FSIRXC_D1
FSIRXC_CLK
FSIRXD_D0
FSIRXD_D1
FSIRXD_CLK
FSIRXE_D0
FSIRXE_D1
FSIRXE_CLK
FSIRXF_D0
FSIRXA_CLK
OUTPUTXBAR3
OUTPUTXBAR4
EPWM8B
MFSXB
SPIA_SIMO
SPIA_SOMI
SPIA_CLK
SPIA_STEn
EQEP1_A
EQEP1_B
OUTPUTXBAR7
OUTPUTXBAR8
CANA_RX
CANA_TX
EPWM9A
EPWM9B
EPWM10A
EPWM10B
EPWM11A
EPWM11B
SD1_D1
SD1_C1
SD1_D2
SD1_C2
SD1_D3
SD1_C3
SSIA_TX
SSIA_RX
MCAN_RX
MCAN_TX
EMIF1_CS2n
EMIF1_CS3n
EMIF1_BA0
EMIF1_BA1
SSIA_CLK
SSIA_FSS
CANB_TX
TRACE_DATA0
TRACE_DATA1
SPIC_SIMO
SPIC_SOMI
MDRA
CANB_RX
EQEP1_STROB
E
GPIO22
MCLKXA
SCIB_TX
EPWM12A
EPWM12B
SPIB_CLK
SD1_D4
MCAN_TX
EMIF1_RAS
TRACE_DATA2
FSIRXF_D1
SPIC_CLK
GPIO23
GPIO24
GPIO25
EQEP1_INDEX
OUTPUTXBAR1
OUTPUTXBAR2
MFSXA
EQEP2_A
EQEP2_B
SCIB_RX
MDXB
SPIB_STEn
SPIB_SIMO
SPIB_SOMI
SD1_C4
SD2_D1
SD2_C1
MCAN_RX
EMIF1_CAS
EMIF1_DQM0
EMIF1_DQM1
TRACE_DATA3
TRACE_CLK
TRACE_SWO
FSIRXF_CLK
EPWM13A
EPWM13B
SPIC_STEn
PMBUSA_SCL
PMBUSA_SDA
FSIRXG_D0
FSIRXG_D1
MDRB
FSITXA_D1
FSITXA_D0
PMBUSA_ALER
T
ESC_MDIO_CL
K
GPIO26
GPIO27
OUTPUTXBAR3 EQEP2_INDEX
MCLKXB
MFSXB
OUTPUTXBAR3
OUTPUTXBAR4
SPIB_CLK
SD2_D2
SD2_C2
EMIF1_DQM2
EMIF1_DQM3
EPWM14A
EPWM14B
FSIRXG_CLK
FSIRXH_D0
EQEP2_STROB
ESC_MDIO_DA
TA
OUTPUTXBAR4
E
SPIB_STEn
PMBUSA_CTL
FSITXA_CLK
GPIO28
GPIO29
SCIA_RX
SCIA_TX
EMIF1_CS4n
OUTPUTXBAR5
OUTPUTXBAR6
EQEP3_A
EQEP3_B
SD2_D3
SD2_C3
EMIF1_CS2n
EMIF1_CS3n
EPWM15A
EPWM15B
FSIRXH_D1
EMIF1_SDCKE
ESC_LATCH0
ESC_LATCH1
I2CA_SDA
ESC_I2C_SDA
ESC_I2C_SCL
CM-I2CA_SDA
CM-I2CA_SCL
ESC_SYNC0
ESC_SYNC1
FSIRXH_CLK
EQEP3_STROB
E
GPIO30
GPIO31
GPIO32
CANA_RX
CANA_TX
I2CA_SDA
EMIF1_CLK
EMIF1_WEn
EMIF1_CS0n
MCAN_RX
MCAN_TX
SPIA_SIMO
OUTPUTXBAR7
SD2_D4
SD2_C4
EMIF1_CS4n
EMIF1_RNW
EMIF1_OEn
EPWM16A
EPWM16B
SPID_SIMO
SPID_SOMI
SPID_CLK
OUTPUTXBAR8 EQEP3_INDEX
CLB_OUTPUTX
BAR1
I2CA_SCL
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TMS320F28386S-Q1 TMS320F28384S TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
www.ti.com
Table 6-7. GPIO Muxed Pins (continued)
0, 4, 8, 12
1
2
3
5
6
7
9
10
11
13
14
15
ALT
CLB_OUTPUTX
BAR2
GPIO33
I2CA_SCL
EMIF1_RNW
SPIA_SOMI
EMIF1_BA0
SPID_STEn
CLB_OUTPUTX
BAR3
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
OUTPUTXBAR1
SCIA_RX
EMIF1_CS2n
EMIF1_CS3n
EMIF1_WAIT
EMIF1_OEn
EMIF1_A0
SPIA_CLK
I2CB_SDA
I2CB_SCL
CANA_RX
CANA_TX
CANB_TX
EMIF1_BA1
EMIF1_A0
EMIF1_A1
EMIF1_A2
EMIF1_A3
EMIF1_A4
ESC_LATCH0 ENET_MII_CRS
ESC_LATCH1 ENET_MII_COL
MCAN_RX
SCIA_TX
ESC_SYNC0
ESC_SYNC1
CLB_OUTPUTX
BAR4
SPIA_STEn
CLB_OUTPUTX
BAR5
SCIA_TX
SD1_D1
SD1_D2
SD1_D3
SD1_D4
CLB_OUTPUTX
BAR6
OUTPUTXBAR2
MCAN_TX
CLB_OUTPUTX
BAR7
ENET_MII_RX_
ENET_MII_CRS
DV
SCIC_TX
SCIC_RX
CLB_OUTPUTX
BAR8
ENET_MII_RX_
ENET_MII_COL
ERR
GPIO39
GPIO40
GPIO41
EMIF1_A1
EMIF1_A2
EMIF1_A3
CANB_RX
I2CB_SDA
I2CB_SCL
ENET_MII_CRS
ESC_I2C_SDA
ESC_I2C_SCL
ENET_REVMII_
ENET_MII_COL
MDIO_RST
ENET_MDIO_C
UARTA_TX
LK
GPIO42
GPIO43
GPIO44
GPIO45
GPIO46
I2CA_SDA
I2CA_SCL
SCIA_TX
SCIA_RX
USB0DM
USB0DP
ENET_MDIO_D
UARTA_RX
ATA
ENET_MII_TX_
CLK
EMIF1_A4
EMIF1_A5
EMIF1_A6
ESC_TX1_CLK
ESC_TX1_ENA
ENET_MII_TX_
EN
ENET_MII_TX_
ERR
ESC_MDIO_CL
K
SCID_RX
ESC_MDIO_DA
TA
GPIO47
GPIO48
GPIO49
EMIF1_A7
EMIF1_A8
EMIF1_A9
SCID_TX
SCIA_TX
SCIA_RX
ENET_PPS0
ENET_PPS1
OUTPUTXBAR3
OUTPUTXBAR4
SD1_D1
SD1_C1
ESC_PHY_CLK
FSITXA_D0
ENET_MII_RX_
CLK
EMIF1_A5
EMIF1_A6
EMIF1_A7
EMIF1_A8
EMIF1_A9
EMIF1_A10
EMIF1_D0
EMIF1_D1
EMIF1_D2
SD2_D1
SD2_D2
SD2_D3
SD2_D4
SD1_C1
SD1_C2
SD1_C3
SD1_C4
ENET_MII_RX_
DV
GPIO50
GPIO51
GPIO52
GPIO53
GPIO54
GPIO55
GPIO56
GPIO57
EQEP1_A
EQEP1_B
EMIF1_A10
EMIF1_A11
EMIF1_A12
EMIF1_D31
EMIF1_D30
EMIF1_D29
EMIF1_D28
EMIF1_D27
SPIC_SIMO
SPIC_SOMI
SPIC_CLK
SPIC_STEn
SCIB_TX
SD1_D2
SD1_C2
SD1_D3
SD1_C3
SD1_D4
SD1_C4
SD2_D1
SD2_C1
FSITXA_D1
FSITXA_CLK
FSIRXA_D0
FSIRXA_D1
FSIRXA_CLK
FSITXB_D0
FSITXB_CLK
FSITXB_D1
ENET_MII_RX_
ERR
EQEP1_STROB
E
ENET_MII_RX_
DATA0
ENET_MII_RX_
DATA1
EQEP1_INDEX
SPIA_SIMO
SPIA_SOMI
SPIA_CLK
EMIF2_D15
EMIF2_D14
EMIF2_D13
EMIF2_D12
EMIF2_D11
ENET_MII_RX_
DATA2
EQEP2_A
EQEP2_B
SSIA_TX
SSIA_RX
SSIA_CLK
SSIA_FSS
ENET_MII_RX_
DATA3
SCIB_RX
EQEP2_STROB
E
ENET_MII_TX_
SCIC_TX
I2CA_SDA
EN
ENET_MII_TX_
SPIA_STEn
EQEP2_INDEX
SCIC_RX
I2CA_SCL
ERR
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TMS320F28386S-Q1 TMS320F28384S TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
www.ti.com
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
Table 6-7. GPIO Muxed Pins (continued)
0, 4, 8, 12
1
2
3
5
6
7
9
10
11
13
14
15
ALT
ESC_LED_LINK ENET_MII_TX_
0_ACTIVE CLK
GPIO58
MCLKRA
EMIF1_D26
EMIF2_D10
OUTPUTXBAR1
SPIB_CLK
SD2_D2
EMIF1_D3
SD2_C2
FSIRXB_D0
SPIA_SIMO
ESC_LED_LINK ENET_MII_TX_
GPIO59
GPIO60
GPIO61
GPIO62
GPIO63
GPIO64
GPIO65
GPIO66
GPIO67
GPIO68
GPIO69
GPIO70
GPIO71
GPIO72
GPIO73
GPIO74
GPIO75
GPIO76
MFSRA
MCLKRB
MFSRB
EMIF1_D25
EMIF1_D24
EMIF1_D23
EMIF1_D22
EMIF1_D21
EMIF1_D20
EMIF1_D19
EMIF1_D18
EMIF1_D17
EMIF1_D16
EMIF1_D15
EMIF1_D14
EMIF1_D13
EMIF1_D12
EMIF1_D11
EMIF1_D10
EMIF1_D9
EMIF2_D9
EMIF2_D8
EMIF2_D7
EMIF2_D6
EMIF2_D5
EMIF2_D4
EMIF2_D3
EMIF2_D2
EMIF2_D1
EMIF2_D0
OUTPUTXBAR2
OUTPUTXBAR3
OUTPUTXBAR4
EQEP3_A
SPIB_STEn
SPIB_SIMO
SPIB_SOMI
CANA_RX
CANA_TX
SCIA_RX
SD2_C2
SD2_D3
SD2_C3
SD2_D4
SD2_C4
EMIF1_D4
EMIF1_D5
EMIF1_D6
EMIF1_D7
SSIA_TX
SD2_C3
SD2_C4
FSIRXB_D1
FSIRXB_CLK
CANA_RX
SPIA_SOMI
SPIA_CLK
SPIA_STEn
1_ACTIVE
DATA0
ENET_MII_TX_
DATA1
ESC_LED_ERR
ENET_MII_TX_
DATA2
ESC_LED_RUN
ESC_LED_STAT ENET_MII_TX_
SCIC_RX
SCIC_TX
CANA_TX
E_RUN
DATA3
ENET_MII_RX_
DATA0
ESC_RX1_DAT
A0
EQEP3_B
SD1_D1
SD1_C1
SD1_D2
SD1_C2
SD1_D3
SD1_C3
SD1_D4
SD1_C4
SPIB_SIMO
SPIB_SOMI
SPIB_CLK
SPIB_STEn
EQEP3_STROB
E
ENET_MII_RX_ ENET_MII_RX_
DV DATA1
ESC_RX1_DAT
A1
SSIA_RX
SSIA_CLK
SSIA_FSS
ENET_MII_RX_ ENET_MII_RX_
ERR DATA2
ESC_RX1_DAT
A2
EQEP3_INDEX
SCIA_TX
ENET_MII_RX_ ENET_MII_RX_
DATA0 DATA3
ESC_RX1_DAT
A3
I2CB_SDA
ENET_MII_RX_ ENET_REVMII_
CLK
MDIO_RST
ESC_PHY1_LIN
KSTATUS
ENET_MII_INTR
ENET_MII_TX_ ENET_MII_RX_
I2CB_SCL
SCIB_TX
SCIB_RX
SCIC_TX
SCIC_RX
ESC_RX1_CLK
ESC_RX1_DV
ESC_RX1_ERR
SPIC_SIMO
SPIC_SOMI
SPIC_CLK
SPIC_STEn
EN
CLK
ENET_MII_RX_
DV
CANA_RX
CANA_TX
CANB_TX
CANB_RX
MCAN_RX
MCAN_TX
ENET_MII_RX_ ENET_MII_RX_
DATA0 ERR
ENET_MII_RX_ ENET_MII_TX_
DATA1 DATA3
ESC_TX1_DATA
3
ENET_RMII_CL ENET_MII_TX_
ESC_TX1_DATA
2
XCLKOUT
SD2_D2
SD2_C2
SD2_D3
SD2_C3
K
DATA2
ENET_MII_TX_
DATA1
ESC_TX1_DATA
1
MCAN_TX
MCAN_RX
ENET_MII_TX_
DATA0
ESC_TX1_DATA
0
ENET_MII_RX_
ERR
ESC_PHY_RES
ETn
EMIF1_D8
SCID_TX
GPIO77
GPIO78
GPIO79
EMIF1_D7
EMIF1_D6
EMIF1_D5
SCID_RX
EQEP2_A
EQEP2_B
SD2_D4
SD2_C4
SD2_D1
ESC_RX0_CLK
ESC_RX0_DV
ESC_RX0_ERR
EQEP2_STROB
E
ESC_RX0_DAT
A0
GPIO80
GPIO81
GPIO82
EMIF1_D4
EMIF1_D3
EMIF1_D2
SD2_C1
ESC_RX0_DAT
A1
EQEP2_INDEX
ESC_RX0_DAT
A2
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TMS320F28386S-Q1 TMS320F28384S TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
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Table 6-7. GPIO Muxed Pins (continued)
0, 4, 8, 12
1
2
3
5
6
7
9
10
11
13
14
15
ALT
ESC_RX0_DAT
A3
GPIO83
EMIF1_D1
GPIO84
GPIO85
SCIA_TX
SCIA_RX
MDXB
MDRB
UARTA_TX
UARTA_RX
ESC_TX0_ENA
ESC_TX0_CLK
MDXA
MDRA
EMIF1_D0
ESC_PHY0_LIN
KSTATUS
GPIO86
GPIO87
GPIO88
GPIO89
GPIO90
GPIO91
GPIO92
GPIO93
GPIO94
GPIO95
GPIO96
GPIO97
GPIO98
EMIF1_A13
EMIF1_CAS
EMIF1_RAS
EMIF1_DQM0
EMIF1_DQM1
EMIF1_DQM2
EMIF1_DQM3
EMIF1_BA1
SCIB_TX
SCIB_RX
MCLKXB
MFSXB
MCLKXA
MFSXA
ESC_TX0_DATA
0
EMIF1_A14
EMIF1_A15
EMIF1_A16
EMIF1_A17
EMIF1_A18
EMIF1_A19
EMIF1_DQM3
EMIF1_DQM1
EMIF1_CAS
EMIF1_RAS
EMIF1_DQM2
EMIF1_DQM0
ESC_TX0_DATA
1
ESC_TX0_DATA
2
SCIC_TX
SCIC_RX
I2CA_SDA
I2CA_SCL
SCID_TX
SCID_RX
ESC_TX0_DATA
3
CLB_OUTPUTX
BAR1
PMBUSA_SCL
PMBUSA_SDA
SSIA_TX
SSIA_RX
SSIA_CLK
SSIA_FSS
FSIRXF_D0
FSIRXF_D1
FSIRXF_CLK
FSIRXG_D0
FSIRXG_D1
FSIRXG_CLK
FSIRXH_D0
FSIRXH_D1
SPID_SIMO
SPID_SOMI
SPID_CLK
SPID_STEn
CLB_OUTPUTX
BAR2
PMBUSA_ALER
T
CLB_OUTPUTX
BAR3
EMIF1_BA0
CLB_OUTPUTX
BAR4
EMIF1_BA1
PMBUSA_CTL
CLB_OUTPUTX
BAR5
EMIF2_A12
EMIF2_DQM1
EMIF2_DQM0
EMIF2_A0
CLB_OUTPUTX
BAR6
EQEP1_A
EQEP1_B
CLB_OUTPUTX
BAR7
EQEP1_STROB
E
CLB_OUTPUTX
BAR8
GPIO99
EMIF2_A1
EMIF2_A2
EMIF2_A3
EQEP1_INDEX
EQEP2_A
FSIRXH_CLK
FSITXA_D0
FSITXA_D1
GPIO100
GPIO101
SPIC_SIMO
SPIC_SOMI
ESC_GPI0
ESC_GPI1
EQEP2_B
EQEP2_STROB
E
GPIO102
EMIF2_A4
SPIC_CLK
ESC_GPI2
FSITXA_CLK
GPIO103
GPIO104
EMIF2_A5
EMIF2_A6
EQEP2_INDEX
EQEP3_A
SPIC_STEn
SCID_TX
ESC_GPI3
ESC_GPI4
FSIRXA_D0
FSIRXA_D1
I2CA_SDA
I2CA_SCL
CM-I2CA_SDA
CM-I2CA_SCL
ENET_MDIO_C
LK
GPIO105
GPIO106
GPIO107
EMIF2_A7
EMIF2_A8
EMIF2_A9
EQEP3_B
SCID_RX
SCIC_TX
SCIC_RX
ESC_GPI5
ESC_GPI6
ESC_GPI7
FSIRXA_CLK
FSITXB_D0
EQEP3_STROB
E
ENET_MDIO_D
ATA
ENET_REVMII_
MDIO_RST
EQEP3_INDEX
FSITXB_D1
GPIO108
GPIO109
GPIO110
EMIF2_A10
EMIF2_A11
EMIF2_WAIT
ESC_GPI8
ESC_GPI9
ESC_GPI10
FSITXB_CLK
ENET_MII_INTR
ENET_MII_CRS
ENET_MII_COL
FSIRXB_D0
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TMS320F28386S-Q1 TMS320F28384S TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
www.ti.com
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
Table 6-7. GPIO Muxed Pins (continued)
0, 4, 8, 12
1
2
3
5
6
7
9
10
11
13
14
15
ALT
ENET_MII_RX_
CLK
GPIO111
EMIF2_BA0
ESC_GPI11
FSIRXB_D1
ENET_MII_RX_
DV
GPIO112
GPIO113
GPIO114
GPIO115
GPIO116
GPIO117
GPIO118
GPIO119
GPIO120
GPIO121
GPIO122
GPIO123
GPIO124
EMIF2_BA1
EMIF2_CAS
EMIF2_RAS
EMIF2_CS0n
EMIF2_CS2n
EMIF2_SDCKE
EMIF2_CLK
EMIF2_RNW
EMIF2_WEn
EMIF2_OEn
EMIF2_D15
EMIF2_D14
EMIF2_D13
ESC_GPI12
ESC_GPI13
ESC_GPI14
ESC_GPI15
ESC_GPI16
ESC_GPI17
ESC_GPI18
ESC_GPI19
ESC_GPI20
ESC_GPI21
ESC_GPI22
ESC_GPI23
ESC_GPI24
FSIRXB_CLK
ENET_MII_RX_
ERR
ENET_MII_RX_
DATA0
ENET_MII_RX_
DATA1
OUTPUTXBAR5
OUTPUTXBAR6
FSIRXC_D0
FSIRXC_D1
FSIRXC_CLK
FSIRXD_D0
FSIRXD_D1
FSIRXD_CLK
FSIRXE_D0
ENET_MII_RX_
DATA2
ENET_MII_RX_
DATA3
ENET_MII_TX_
EN
ENET_MII_TX_
ERR
ENET_MII_TX_
CLK
ENET_MII_TX_
DATA0
ENET_MII_TX_
DATA1
SPIC_SIMO
SPIC_SOMI
SD1_D1
SD1_C1
SD1_D2
ENET_MII_TX_
DATA2
ENET_MII_TX_
DATA3
SPIC_CLK
GPIO125
GPIO126
GPIO127
GPIO128
GPIO129
GPIO130
EMIF2_D12
EMIF2_D11
EMIF2_D10
EMIF2_D9
EMIF2_D8
EMIF2_D7
SPIC_STEn
SD1_C2
SD1_D3
SD1_C3
SD1_D4
SD1_C4
SD2_D1
ESC_GPI25
ESC_GPI26
ESC_GPI27
ESC_GPI28
ESC_GPI29
ESC_GPI30
FSIRXE_D1
ESC_LATCH0
ESC_LATCH1
ESC_SYNC0
ESC_SYNC1
ESC_TX1_ENA
ESC_TX1_CLK
FSIRXE_CLK
ESC_TX1_DATA
0
GPIO131
EMIF2_D6
EMIF2_D5
SD2_C1
ESC_GPI31
ESC_GPO0
ESC_TX1_DATA
1
GPIO132
GPIO133
GPIO134
SD2_D2
SD2_C2
SD2_D3
AUXCLKIN
ESC_TX1_DATA
2
EMIF2_D4
EMIF2_D3
ESC_GPO1
ESC_GPO2
ESC_TX1_DATA
3
GPIO135
SCIA_TX
SD2_C3
GPIO136
GPIO137
GPIO138
EMIF2_D2
EMIF2_D1
EMIF2_D0
SCIA_RX
SCIB_TX
SCIB_RX
SD2_D4
SD2_C4
ESC_GPO3
ESC_GPO4
ESC_GPO5
ESC_RX1_DV
ESC_RX1_CLK
ESC_RX1_ERR
EPWM13A
EPWM13B
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TMS320F28386S-Q1 TMS320F28384S TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
www.ti.com
Table 6-7. GPIO Muxed Pins (continued)
0, 4, 8, 12
1
2
3
5
6
7
9
10
11
13
14
15
ALT
ESC_RX1_DAT
A0
GPIO139
EPWM14A
SCIC_RX
ESC_GPO6
ESC_RX1_DAT
A1
GPIO140
GPIO141
GPIO142
GPIO143
GPIO144
EPWM14B
EPWM15A
EPWM15B
EPWM16A
EPWM16B
SCIC_TX
SCID_RX
SCID_TX
ESC_GPO7
ESC_GPO8
ESC_GPO9
ESC_GPO10
ESC_GPO11
ESC_RX1_DAT
A2
ESC_RX1_DAT
A3
ESC_LED_LINK
0_ACTIVE
ESC_LED_LINK
1_ACTIVE
GPIO145
GPIO146
EPWM1A
EPWM1B
ESC_GPO12
ESC_GPO13
ESC_LED_ERR
ESC_LED_RUN
ESC_LED_STAT
E_RUN
GPIO147
GPIO148
GPIO149
EPWM2A
EPWM2B
EPWM3A
ESC_GPO14
ESC_GPO15
ESC_GPO16
ESC_PHY0_LIN
KSTATUS
ESC_PHY1_LIN
KSTATUS
GPIO150
GPIO151
EPWM3B
EPWM4A
ESC_GPO17
ESC_GPO18
ESC_I2C_SDA
ESC_I2C_SCL
ESC_MDIO_CL
K
GPIO152
EPWM4B
ESC_GPO19
ESC_MDIO_DA
TA
GPIO153
GPIO154
GPIO155
EPWM5A
EPWM5B
EPWM6A
ESC_GPO20
ESC_GPO21
ESC_GPO22
ESC_PHY_CLK
ESC_PHY_RES
ETn
GPIO156
GPIO157
EPWM6B
EPWM7A
ESC_GPO23
ESC_GPO24
ESC_TX0_ENA
ESC_TX0_CLK
ESC_TX0_DATA
0
GPIO158
GPIO159
GPIO160
GPIO161
EPWM7B
EPWM8A
EPWM8B
EPWM9A
ESC_GPO25
ESC_GPO26
ESC_GPO27
ESC_GPO28
ESC_TX0_DATA
1
ESC_TX0_DATA
2
ESC_TX0_DATA
3
GPIO162
GPIO163
GPIO164
EPWM9B
EPWM10A
EPWM10B
ESC_GPO29
ESC_GPO30
ESC_GPO31
ESC_RX0_DV
ESC_RX0_CLK
ESC_RX0_ERR
ESC_RX0_DAT
A0
GPIO165
GPIO166
EPWM11A
EPWM11B
MDXA
MDRA
ESC_RX0_DAT
A1
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TMS320F28386S-Q1 TMS320F28384S TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
www.ti.com
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
Table 6-7. GPIO Muxed Pins (continued)
0, 4, 8, 12
1
2
3
5
6
7
9
10
11
13
14
15
ALT
ESC_RX0_DAT
A2
GPIO167
EPWM12A
MCLKXA
ESC_RX0_DAT
A3
GPIO168
EPWM12B
MFSXA
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TMS320F28386S-Q1 TMS320F28384S TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
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6.5.2 Input X-BAR
The Input X-BAR is used to route any GPIO input to the ADC, eCAP, and ePWM peripherals as well as to
external interrupts (XINT) (see Figure 6-7). Table 6-8 lists the input X-BAR destinations. For details on
configuring the Input X-BAR, see the Crossbar (X-BAR) chapter of the TMS320F2838x Real-Time
Microcontrollers Technical Reference Manual.
Figure 6-7. Input X-BAR
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
Table 6-8. Input X-BAR Destinations
INPUT
DESTINATION
INPUT1
INPUT2
INPUT3
INPUT4
eCAPx, ePWM X-BAR, ePWM[TZ1,TRIP1], Output X-BAR, EtherCAT, ERAD
eCAPx, ePWM X-BAR, ePWM[TZ2,TRIP2], Output X-BAR, EtherCAT, ERAD
eCAPx, ePWM X-BAR, ePWM[TZ3,TRIP3], Output X-BAR, EtherCAT, ERAD
eCAPx, ePWM X-BAR, XINT1, Output X-BAR, EtherCAT, ERAD
eCAPx, ePWM X-BAR, XINT2, ADCEXTSOC, EXTSYNCIN1, ePWM SYNC, eCAP SYNC, Output X-BAR,
EtherCAT, ERAD
INPUT5
INPUT6
eCAPx, ePWM X-BAR, XINT3, ePWM[TRIP6], EXTSYNCIN2, Output X-BAR, ePWM SYNC, eCAP SYNC,
Output X-BAR, EtherCAT, ERAD
INPUT7
INPUT8
eCAPx, ePWM X-BAR, EtherCAT, ERAD, eCAP1 Capture Input
eCAPx, ePWM X-BAR, EtherCAT, ERAD, eCAP2 Capture Input
eCAPx, ePWM X-BAR, EtherCAT, ERAD, eCAP3 Capture Input
eCAPx, ePWM X-BAR, EtherCAT, ERAD, eCAP4 Capture Input
eCAPx, ePWM X-BAR, EtherCAT, ERAD, eCAP5 Capture Input
eCAPx, ePWM X-BAR, EtherCAT, ERAD, eCAP6 Capture Input
eCAPx, ePWM X-BAR, XINT4, EtherCAT
INPUT9
INPUT10
INPUT11
INPUT12
INPUT13
INPUT14
INPUT15
INPUT16
eCAPx, ePWM X-BAR, XINT5, EtherCAT, ERAD
eCAPx, EtherCAT
eCAPx, EtherCAT, DCCx
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
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6.5.3 Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR
The Output X-BAR has eight outputs that can be selected on the GPIO mux as OUTPUTXBARx. The CLB X-
BAR has eight outputs that are connected to the CLB global mux as AUXSIGx. The CLB Output X-BAR has
eight outputs that can be selected on the GPIO mux as CLB_OUTPUTXBARx. The ePWM X-BAR has eight
outputs that are connected to the TRIPx inputs of the ePWM. The sources for the Output X-BAR, CLB X-BAR,
CLB Output X-BAR, and ePWM X-BAR are shown in Figure 6-8. For details on the Output X-BAR, CLB X-BAR,
CLB Output X-BAR, and ePWM X-BAR, see the Crossbar (X-BAR) chapter of the TMS320F2838x Real-Time
Microcontrollers Technical Reference Manual.
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
CTRIPOUTH
CTRIPOUTL
(Output X-BAR only)
(ePWM X-BAR only)
CMPSSx
CTRIPH
CTRIPL
ePWM and eCAP
Sync Chain
EXTSYNCOUT
ADCSOCA0
AUXSIG1
AUXSIG2
AUXSIG3
AUXSIG4
AUXSIG5
AUXSIG6
AUXSIG7
AUXSIG8
CLB
Global
Mux
ADCSOCA0
Select Circuit
CLB
X-BAR
ADCSOCB0
Select Circuit
ADCSOCB0
ECAPxOUT
TRIP4
TRIP5
eCAPx
ADCx
EVT1
EVT2
EVT3
EVT4
All
ePWM
Modules
TRIP7
TRIP8
TRIP9
TRIP10
TRIP11
TRIP12
EPWM
X-BAR
INPUT1-6
INPUT7-14
(ePWM X-BAR only)
Input X-BAR
CLAHALT
eQEPx
CLAHALT
OUTPUTXBAR1
OUTPUTXBAR2
OUTPUTXBAR3
OUTPUTXBAR4
OUTPUTXBAR5
OUTPUTXBAR6
OUTPUTXBAR7
OUTPUTXBAR8
FLT1.COMPH
FLT1.COMPL
Output
X-BAR
SDFMx
FLT4.COMPH
FLT4.COMPL
GPIO
Mux
X-BAR Flags
(shared)
CLB_OUTPUTXBAR1
CLB_OUTPUTXBAR2
CLB_OUTPUTXBAR3
CLB_OUTPUTXBAR4
CLB_OUTPUTXBAR5
CLB_OUTPUTXBAR6
CLB_OUTPUTXBAR7
CLB_OUTPUTXBAR8
CLB
Output
X-BAR
CLB Input X-BAR
CLB TILEx
Figure 6-8. Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR Sources
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
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6.5.4 USB Pin Muxing
Table 6-9 lists assignment of the alternate USB function mapping. These can be configured with the GPBAMSEL
register.
Table 6-9. Alternate USB Function
GPIO
GPBAMSEL SETTING
GPBAMSEL[10] = 1b
GPBAMSEL[11] = 1b
USB FUNCTION
USB0DM
GPIO42
GPIO43
USB0DP
6.5.5 High-Speed SPI Pin Muxing
The SPI module on this device has a high-speed mode. To achieve the highest possible speed, a special GPIO
configuration is used on a single GPIO mux option for each SPI. These GPIOs may also be used by the SPI
when not in high-speed mode (HS_MODE = 0).
To select the mux options that enable the SPI high-speed mode, configure the GPyGMUX and GPyMUX
registers as shown in Table 6-10.
Table 6-10. GPIO Configuration for High-Speed SPI
GPIO
SPI SIGNAL
MUX CONFIGURATION
SPIA
SPIB
SPIC
SPID
GPIO58
GPIO59
GPIO60
GPIO61
SPISIMOA
SPISOMIA
SPICLKA
SPISTEA
GPBGMUX2[21:20]=11b
GPBMUX2[21:20]=11b
GPBMUX2[23:22]=11b
GPBMUX2[25:24]=11b
GPBMUX2[27:26]=11b
GPBGMUX2[23:22]=11b
GPBGMUX2[25:24]=11b
GPBGMUX2[27:26]=11b
GPIO63
GPIO64
GPIO65
GPIO66
SPISIMOB
SPISOMIB
SPICLKB
SPISTEB
GPBGMUX2[31:30]=11b
GPCGMUX1[1:0]=11b
GPCGMUX1[3:2]=11b
GPCGMUX1[5:4]=11b
GPBMUX2[31:30]=11b
GPCMUX1[1:0]=11b
GPCMUX1[3:2]=11b
GPCMUX1[5:4]=11b
GPIO69
GPIO70
GPIO71
GPIO72
SPISIMOC
SPISOMIC
SPICLKC
SPISTEC
GPCGMUX1[11:10]=11b
GPCGMUX1[13:12]=11b
GPCGMUX1[15:14]=11b
GPCGMUX1[17:16]=11b
GPCMUX1[11:10]=11b
GPCMUX1[13:12]=11b
GPCMUX1[15:14]=11b
GPCMUX1[17:16]=11b
GPIO91
GPIO92
GPIO93
GPIO94
SPISIMOD
SPISOMID
SPICLKD
SPISTED
GPCGMUX2[23:22]=11b
GPCGMUX2[25:24]=11b
GPCGMUX2[27:26]=11b
GPCGMUX2[29:28]=11b
GPCMUX2[23:22]=11b
GPCMUX2[25:24]=11b
GPCMUX2[27:26]=11b
GPCMUX2[29:28]=11b
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
6.5.6 High-Speed SSI Pin Muxing
The SSI module on this device has a high-speed mode. To enable the high-speed mode on the SSI module,
enable the high-speed clock and the high-speed capabilities of the SSI module (SSICR1[HSCLKEN] and
SSIPP[HSCLK]). The GPIO Configuration for High-Speed SSI table lists the SSI high-speed-capable pinmux
options.
Table 6-11. GPIO Configuration for High-Speed SSI
GPIO
SSI SIGNAL
GPIO MUX SELECTION INDEX
GPIO16
GPIO17
GPIO18
GPIO19
SSIA_TX
11
11
11
11
SSIA_RX
SSIA_CLK
SSIA_FSS
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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6.6 Connections for Unused Pins
For applications that do not need to use all functions of the device, Table 6-12 lists acceptable conditioning for
any unused pins. When multiple options are listed in Table 6-12, any are acceptable. Pins not listed in Table 6-12
must be connected according to the Pin Attributes table.
Table 6-12. Connections for Unused Pins
SIGNAL NAME
ACCEPTABLE PRACTICE
Analog
VREFHIx
VREFLOx
Tie to VDDA
Tie to VSSA
•
•
No Connect
ADCINx (except DAC pins)
ADCINx (DAC pins)
Tie to VSSA
•
•
No Connect
Pulldown to VSSA through 5-kΩ resistor
Digital
•
•
•
No connection (input mode with internal pullup enabled)
No connection (output mode with internal pullup disabled)
GPIOx
Pullup or pulldown resistor (any value resistor, input mode, and with internal pullup
disabled)
X1
X2
Tie to VSS
No Connect
•
•
No Connect
TCK
TDI
Pullup resistor
•
•
No Connect
Pullup resistor
TDO
No Connect
TMS
No Connect
TRSTn
ERRORSTS
FLT1
Pulldown resistor (2.2 kΩ or smaller)
No Connect
No Connect
FLT2
No Connect
Power and Ground
VDD
All VDD pins must be connected per the Pin Attributes table.
If a dedicated analog supply is not used, tie to VDDIO.
All VDDIO pins must be connected per the Pin Attributes table.
Must be tied to VDDIO
VDDA
VDDIO
VDD3VFL
VDDOSC
VSS
Must be tied to VDDIO
All VSS pins must be connected to board ground.
If a dedicated analog ground is not used, tie to VSS.
If an external crystal is not used, this pin may be connected to the board ground.
VSSA
VSSOSC
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
7 Specifications
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those indicated under the Recommended Operating Conditions is not implied. Exposure to absolute-maximum-
rated conditions for extended periods may affect device reliability. All voltage values are with respect to VSS,
unless otherwise noted.
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
MAX
4.6
4.6
4.6
4.6
1.5
4.6
4.6
UNIT
VDDIO with respect to VSS
VDDA with respect to VSSA
VDD3VFL with respect to VSS
VDDOSC with respect to VSS
VDD with respect to VSS
VIN (3.3 V)
Supply voltage
V
Input voltage
V
V
Output voltage
VO
Digital/analog input (per pin), IIK (VIN < VSS/VSSA or VIN > VDDIO/
VDDA)(2)
–20
–20
20
20
Input clamp current
mA
Total for all inputs, IIKTOTAL
(VIN < VSS/VSSA or VIN > VDDIO/VDDA)
Output current
Digital output (per pin), IOUT
–20
–40
–40
–65
20
125
150
150
mA
°C
°C
°C
Ambient temperature
Operating junction temperature
Storage temperature(1)
TA
TJ
Tstg
(1) Long-term high-temperature storage or extended use at maximum temperature conditions may result in a reduction of overall device
life. For additional information, see the Semiconductor and IC Package Thermal Metrics Application Report.
(2) Continuous clamp current per pin is ±2 mA. Do not operate in this condition continuously as VDDIO/VDDA voltage may internally rise and
impact other electrical specifications.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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UNIT
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
7.2 ESD Ratings – Commercial
VALUE
TMS320F28388D, TMS320F28386D, TMS320F28384D, TMS320F28388S, TMS320F28386S, and TMS320F28384S in 337-ball ZWT
package
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
±500
V(ESD)
Electrostatic discharge (ESD)
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101 or ANSI/ESDA/JEDEC JS-002(2)
TMS320F28388D, TMS320F28386D, TMS320F28384D, TMS320F28388S, TMS320F28386S, and TMS320F28384S in 176-pin PTP
package
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
±500
V(ESD)
Electrostatic discharge (ESD)
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101 or ANSI/ESDA/JEDEC JS-002(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 ESD Ratings – Automotive
VALUE
UNIT
TMS320F28386D-Q1 and TMS320F28384D-Q1 in 337-ball ZWT package
Human body model (HBM), per
AEC Q100-002(1)
All pins
All pins
±2000
V(ESD)
Electrostatic discharge
Charged device model (CDM),
per AEC Q100-011
±500
±750
V
Corner balls on 337-ball ZWT:
A1, A19, W1, W19
TMS320F28386D-Q1, TMS320F28384D-Q1, TMS320F28386S-Q1, and TMS320F28384S-Q1 in 176-pin PTP package
Human body model (HBM), per
AEC Q100-002(1)
All pins
±2000
V(ESD)
Electrostatic discharge
Charged device model (CDM),
per AEC Q100-011
All pins
±500
±750
V
Corner pins on 176-pin PTP:
1, 44, 45, 88, 89, 132, 133, 176
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.4 Recommended Operating Conditions
MIN
3.14
3.14
1.14
NOM
3.3
3.3
1.2
0
MAX
3.47
3.47
1.26
UNIT
Device supply voltage, VDDIO(1)
Analog supply voltage, VDDA
Device supply voltage, VDD
Device ground, VSS
V
V
V
V
V
Analog ground, VSSA
0
Supply ramp rate of VDDIO, VDD,
VDDA with respect to VSS(2)
SRSUPPLY
105
10
V/s
ms
VDDIO supply ramp time from 1V to
VDDIOMIN
tVDDIO-RAMP
VIN
Digital input voltage
VSS – 0.3
VSSA – 0.3
–40
VDDIO + 0.3
VDDA + 0.3
125
V
V
VIN
Analog input voltage
S version(3)
Junction temperature, TJ
Free-Air temperature, TA
°C
°C
Q version(3) (AEC Q100 qualification)
–40
125
(1) VDDIO, VDD3VFL, and VDDOSC should be maintained within 0.3 V of each other.
(2) Supply ramp rate faster than this can trigger the on-chip ESD protection.
(3) Operation above TJ = 105°C for extended duration will reduce the lifetime of the device. See Calculating Useful Lifetimes of Embedded
Processors for more information.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
7.5 Power Consumption Summary
Current values listed in this section are representative for the test conditions given and not the absolute
maximum possible. The actual device currents in an application will vary with application code and pin
configurations. Section 7.5.1 lists the system current consumption values for an external supply.
7.5.1 System Current Consumption (External Supply)
over operating free-air temperature range (unless otherwise noted).
TYP : Vnom, 30℃
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPERATING MODE
VDD current consumption during
operational usage(3)
IDD
288
45
8
475
mA
mA
mA
VDDIO current consumption during
operational usage(2)
IDDIO
See Section 7.5.2.
VDDA current consumption during
operational usage
IDDA
15
IDLE MODE
IDD
VDD current consumption while device is in
Idle mode(3)
90
4
265
7
mA
mA
mA
CPU is in IDLE mode
VDDIO current consumption while device is
in Idle mode(2)
•
•
Flash is powered down
XCLKOUT is turned off
IDDIO
VDDA current consumption while device is
in Idle mode
IDDA
0.002
0.010
STANDBY MODE
VDD current consumption while device is in
Standby mode(3)
IDD
30
4
200
7
mA
mA
mA
CPU is in STANDBY mode
VDDIO current consumption while device is
in Standby mode(2)
•
•
Flash is powered down
XCLKOUT is turned off
IDDIO
IDDA
VDDA current consumption while device is
in Standby mode
0.002
0.010
FLASH ERASE/PROGRAM
VDD Current consumption during Erase/
IDD
CPU is running from Flash, performing
Erase and Program on the unused sector.
242
56
360
75
mA
mA
mA
Program cycle(1) (3)
VDDIO Current consumption during Erase/
Program cycle(1) (2)
•
•
•
SYSCLK is running at 200 MHz.
I/Os are inputs with pullups enabled.
Peripheral clocks are turned OFF.
IDDIO
VDDA Current consumption during Erase/
Program cycle
IDDA
0.01
0.15
RESET MODE
CPU is held in reset via external low signal
driven onto XRSn
VDD current consumption while held in
reset via XRSn(3)
IDD
55
15
mA
mA
mA
•
XRSn held low through power-up
CPU is held in reset via external low signal
driven onto XRSn
VDDIO current consumption while held in
reset via XRSn(2)
IDDIO
•
XRSn held low through power-up
CPU is held in reset via external low signal
driven onto XRSn
VDDA current consumption while held in
reset via XRSn
IDDA
0.05
•
XRSn held low through power-up
(1) Brown-out events during flash programming can corrupt flash data and permanently lock the device. Programming environments using
alternate power sources (such as a USB programmer) must be capable of supplying the rated current for the device and other system
components with sufficient margin to avoid supply brown-out conditions.
(2) Includes current consumption for VDD3VFL supply (VDDIO + VDD3VFL).
(3) VDD current values in this table do not include the 21-mA current from VDD to VSS through the 56Ω resistor that is mentioned in the
Signal Descriptions section
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.5.2 Operating Mode Test Description
Section 7.5.1 and the Typical Current Reduction per Disabled Peripheral table list the current consumption
values for the operational mode of the device. The operational mode provides an estimation of what an
application might encounter. The test condition for these measurements has the following properties:
•
•
•
•
•
•
•
Code is executing from RAM.
FLASH is read and kept in active state.
No external components are driven by I/O pins.
All peripherals have clocks enabled.
All CPUs are actively executing code.
CPU1 and CPU2 are operating at 200 MHz and CM is operating at 125 MHz.
All analog peripherals are powered up. ADCs and DACs are periodically converting.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.5.3 Current Consumption Graphs
Figure 7-1, Figure 7-2, and Figure 7-3 show a typical representation of the relationship between frequency,
temperature, core supply, and current consumption on the device. Actual results will vary based on the system
implementation and conditions.
Figure 7-1 shows the typical operating current profile across temperature and core supply voltage. Figure 7-2
shows the typical standby current profile across temperature and core supply voltage. Figure 7-3 shows how the
typical operating currents change with changing clock frequency of the C28x CPUs and changing clock
frequency of the CM module.
330
Vdd = 1.14
Vdd = 1.2
Vdd = 1.26
325
320
315
310
305
300
295
290
285
280
275
270
265
-40 -20
0
20
40
Temperature (°C)
60
80 100 120 140 160
D001
Figure 7-1. Typical Operating Current Versus Temperature
57
Vdd = 1.14
Vdd = 1.2
Vdd = 1.26
54
51
48
45
42
39
36
33
30
27
24
21
-40 -20
0
20
40
Temperature (°C)
60
80 100 120 140 160
D002
Figure 7-2. Typical Standby Current Versus Temperature
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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300
CMCLK = 125 MHz
CMCLK = 75 MHz
CMCLK = 25 MHz
275
250
225
200
175
150
125
100
75
50
25
20
40
60
80
100 120 140 160 180 200
SYSCLK (MHz)
D003
Figure 7-3. Typical Operating Current Versus SYSCLK
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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7.5.4 Reducing Current Consumption
The F2838x devices provide some methods to reduce the device current consumption:
•
One of the two low-power modes—IDLE or STANDBY—could be entered during idle periods in the
application.
•
•
•
The flash module may be powered down if the code is run from RAM.
Disable the pullups on pins that assume an output function.
Each peripheral has an individual clock-enable bit (PCLKCRx). Reduced current consumption may be
achieved by turning off the clock to any peripheral that is not used in a given application. The Typical Current
Reduction per Disabled Peripheral table lists the typical current reduction that may be achieved by disabling
the clocks using the PCLKCRx register.
•
To realize the lowest VDDA current consumption in an LPM, see the Analog-to-Digital Converter (ADC)
chapter of the TMS320F2838x Real-Time Microcontrollers Technical Reference Manual to ensure each
module is powered down as well.
Table 7-1. Typical Current Reduction per Disabled Peripheral
PERIPHERAL(1)
IDD CURRENT REDUCTION (mA)
ADC(2)
2.6
1.5
0.3
1.6
0.4
2.4
1.4
0.4
0.4
0.7
0.7
0.5
0.1
0.4
1.6
0.2
1.4
0.3
0.7
1.0
4.0
2.0
1.1
0.5
2.9
3.7
0.7
0.9
0.4
1.5
2.4
0.6
0.3
CLA
CLA BGCRC
CLB
CM - AES
CM - GCRC
CM - I2C
CM - SSI
CM - uDMA
CM - UART
CMPSS(2)
CPU BGCRC
CPU TIMER
DAC(2)
DCAN
DCC
DMA
eCAP1 to eCAP5
eCAP6 to eCAP7(3)
EMIF
ERAD
ePWM1 - ePWM8(4)
ePWM9 - ePWM16
eQEP
EtherCAT
Ethernet
FSI RX
FSI TX
I2C
MCAN (CAN-FD)
McBSP
PMBUS
SCI
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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Table 7-1. Typical Current Reduction per Disabled Peripheral (continued)
PERIPHERAL(1)
IDD CURRENT REDUCTION (mA)
SDFM
SPI
2.7
0.7
5.4
USB
(1) All peripherals are disabled upon reset. Use the PCLKCRx register to individually enable peripherals. For peripherals with multiple
instances, the current quoted is for a single module.
(2) This current represents the current drawn by the digital portion of the each module.
(3) eCAP6 and eCAP7 can also be configured as HRCAP.
(4) ePWM1 to ePWM8 can also be configured as HRPWM.
7.6 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
TEST
PARAMETER
MIN
TYP
MAX UNIT
CONDITIONS
IOH = IOH MIN
IOH = –100 μA
IOL = IOL MAX
IOL = 100 µA
VDDIO * 0.8
VDDIO – 0.2
VOH
High-level output voltage
V
0.4
V
0.2
VOL
Low-level output voltage
IOH
IOL
High-level output source current for all output pins
Low-level output sink current for all output pins
High-level output
–4
mA
4
mA
Group 1(1)
Group 2(2)
Group 3(3)
Group 4(4)
Group 1(1)
Group 2(2)
Group 3(3)
Group 4(4)
impedance for group 1
output pins
70
35
45
60
70
35
45
60
Ω
High-level output
impedance for group 2
output pins
Ω
Ω
Ω
Ω
Ω
Ω
Ω
ROH
High-level output
impedance for group 3
output pins
High-level output
impedance for group 4
output pins
Low-level output
impedance for group 1
output pins
Low-level output
impedance for group 2
output pins
ROL
Low-level output
impedance for group 3
output pins
Low-level output
impedance for group 4
output pins
GPIO42, GPIO43
All other pins
VDDIO * 0.7
2.0
V
V
High-level input voltage
(3.3V)
VIH
VIL
Low-level input voltage (3.3V)
Input hysteresis
0.8
V
VHYSTERESIS
150
mV
Digital Inputs with
pulldown(5)
VDDIO = 3.3 V
VIN = VDDIO
IPULLDOWN
IPULLUP
Input current
Input current
120
150
µA
µA
Digital Inputs with pullup VDDIO = 3.3 V
enabled(5)
VIN = 0 V
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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7.6 Electrical Characteristics (continued)
over recommended operating conditions (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
MIN
TYP
MAX UNIT
Pullups and outputs
disabled
0 V ≤ VIN ≤ VDDIO
Digital
-2
2
µA
µA
Analog (except
ADCINB0 or
DACOUTx)
ILEAK
Pin leakage
-0.3
0.3
11
0 V ≤ VIN ≤ VDDA
ADCINB0(6)
2
66
2
µA
µA
pF
DACOUTx
CI
Input capacitance(7)
VDDIO power on reset
voltage
VDDIO-POR
2.5
V
(1) Group 1: GPIO0-2, 6, 8-10, 16, 18-29, 31-41, 44-70, 72-117, 119-132, 134-138
(2) Group 2: GPIO3-5, 7, 11-15, 17, 133, 139-168
(3) Group 3: GPIO30, 71, 118
(4) Group 4: USB pins (GPIO42, 43)
(5) See Table 6-6 for a list of pins with a pullup or pulldown.
(6) The MAX input leakage shown on ADCINB0 is at high temperature.
(7) The analog pins are specified separately; see Table 7-8.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.7 Thermal Resistance Characteristics for ZWT Package
°C/W(1)
8.3
AIR FLOW (lfm)(2)
RΘJC
Junction-to-case thermal resistance
Junction-to-board thermal resistance
Junction-to-ambient thermal resistance
N/A
N/A
0
RΘJB
11.6
20.6
18.6
17.4
16.5
0.3
RΘJA (High k PCB)
150
250
500
0
RΘJMA
Junction-to-moving air thermal resistance
0.4
150
250
500
0
PsiJT
Junction-to-package top
0.5
0.6
11.4
11.2
11.1
11.1
150
250
500
PsiJB
Junction-to-board
(1) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(2) lfm = linear feet per minute
7.8 Thermal Resistance Characteristics for PTP Package
°C/W(1)
6.97
6.05
17.8
12.8
11.4
10.1
0.11
0.24
0.33
0.42
6.1
AIR FLOW (lfm)(2)
RΘJC
Junction-to-case thermal resistance
Junction-to-board thermal resistance
Junction-to-ambient thermal resistance
N/A
N/A
0
RΘJB
RΘJA (High k PCB)
150
250
500
0
RΘJMA
Junction-to-moving air thermal resistance
150
250
500
0
PsiJT
Junction-to-package top
5.5
150
250
500
PsiJB
Junction-to-board
5.4
5.3
(1) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(2) lfm = linear feet per minute
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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7.9 Thermal Design Considerations
Based on the end application design and operational profile, the IDD and IDDIO currents could vary. Systems that
exceed the recommended maximum power dissipation in the end product may require additional thermal
enhancements. Ambient temperature (TA) varies with the end application and product design. The critical factor
that affects reliability and functionality is TJ, the junction temperature, not the ambient temperature. Hence, care
should be taken to keep TJ within the specified limits. Tcase should be measured to estimate the operating
junction temperature TJ. Tcase is normally measured at the center of the package top-side surface. The thermal
application report Semiconductor and IC Package Thermal Metrics helps to understand the thermal metrics and
definitions.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.10 System
7.10.1 Power Sequencing
Signal Pin Requirements: Before powering the device, no voltage larger than 0.3 V above VDDIO can be
applied to any digital pin, and no voltage larger than 0.3 V above VDDA can be applied to any analog pin
(including VREFHI).
VDDIO and VDDA Requirements: The 3.3-V supplies VDDIO and VDDA should be powered up together and
kept within 0.3 V of each other during functional operation.
VDD Requirements: During the supply ramp, VDD should be kept no more than 0.3 V above VDDIO.
A single 56Ω resistor (10% tolerance) should be placed between VDD and VSS. This resistor provides a load to
consume an internal VDD3VFL-to-VDD current source and avoid VDD voltage rising during low-power device
conditions.
7.10.2 Reset Timing
XRSn is the device reset pin. It functions as an input and open-drain output. The device has a built-in power-on
reset (POR). During power up, the POR circuit drives the XRSn pin low. A watchdog or NMI watchdog reset also
drives the pin low. An external circuit may drive the pin to assert a device reset.
A resistor with a value from 2.2 kΩ to 10 kΩ should be placed between XRSn and VDDIO. A capacitor should be
placed between XRSn and VSS for noise filtering; the capacitance should be 100 nF or smaller. These values will
allow the watchdog to properly drive the XRSn pin to VOL within 512 OSCCLK cycles when the watchdog reset is
asserted. Figure 7-4 shows the recommended reset circuit.
VDDIO
2.2 kW to 10 kW
Optional open-drain
Reset source
XRSn
£100 nF
Figure 7-4. Reset Circuit
7.10.2.1 Reset Sources
The following reset sources exist on this device: XRSn, WDRSn, NMIWDRSn, SYSRSn, SCCRESET,
ECAT_RESET_OUT, SIMRESET_XRSn, and SIMRESET_CPU1RSn. See the Reset Signals table in the
System Control chapter of the TMS320F2838x Real-Time Microcontrollers Technical Reference Manual.
The parameter th(boot-mode) must account for a reset initiated from any of these sources.
CAUTION
Some reset sources are internally driven by the device. Some of these sources will drive XRSn low.
Use this to disable any other devices driving the boot pins. The SCCRESET and debugger reset
sources do not drive XRSn; therefore, the pins used for boot mode should not be actively driven by
other devices in the system. The boot configuration has a provision for changing the boot pins in
OTP; for more details, see the TMS320F2838x Real-Time Microcontrollers Technical Reference
Manual.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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7.10.2.2 Reset Electrical Data and Timing
Section 7.10.2.2.1 lists the reset (XRSn) timing requirements. Section 7.10.2.2.2 lists the reset (XRSn) switching
characteristics. Figure 7-5 shows the power-on reset. Figure 7-6 shows the warm reset.
7.10.2.2.1 Reset (XRSn) Timing Requirements
MIN
1.5
MAX
UNIT
ms
th(boot-mode)
tw(RSL2)
Hold time for boot-mode pins
Pulse duration, XRSn low on warm reset
3.2
µs
7.10.2.2.2 Reset (XRSn) Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
100
MAX
UNIT
tw(RSL1)
tw(WDRS)
tboot-flash
Pulse duration, XRSn driven low by device after supplies are stable
Pulse duration, reset pulse generated by watchdog
µs
cycles
ms
512tc(OSCCLK)
Boot-ROM execution time to first instruction fetch in flash
1.2
7.10.2.2.3 Reset Timing Diagrams
VDDIO, VDDA
(3.3 V)
VDD (1.2 V)
t
w(RSL1)
XRSn(A)
t
boot-flash
Boot ROM
CPU
Execution
Phase
User-code
User-code dependent
(B)
h(boot-mode)
t
GPIO pins as input
Boot-ROM execution starts
Boot-Mode Pins
Peripheral/GPIO function
Based on boot code
I/O Pins
GPIO pins as input (pullups are disabled)
User-code dependent
A. The XRSn pin can be driven externally by a supervisor or an external pullup resistor, see the Pin Attributes table.
B. After reset from any source (see Section 7.10.2.1), the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode
pin, the boot code branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in
debugger environment), the boot code execution time is based on the current SYSCLK speed. The SYSCLK will be based on user
environment and could be with or without PLL enabled.
Figure 7-5. Power-on Reset
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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t
w(RSL2)
XRSn
User Code
CPU
Execution
Phase
User Code
Boot ROM
Boot-ROM execution starts
(initiated by any reset source)
(A)
t
h(boot-mode)
Peripheral/GPIO Function
User-Code Dependent
GPIO Pins as Input
Boot-Mode Pins
I/O Pins
Peripheral/GPIO Function
User-Code Execution Starts
GPIO Pins as Input (Pullups are Disabled)
User-Code Dependent
A. After reset from any source (see Section 7.10.2.1), the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot
Mode pin, the boot code branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in
debugger environment), the Boot code execution time is based on the current SYSCLK speed. The SYSCLK will be based on user
environment and could be with or without PLL enabled.
Figure 7-6. Warm Reset
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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7.10.3 Clock Specifications
7.10.3.1 Clock Sources
Table 7-2 lists four possible clock sources. Figure 7-7 provides an overview of the device's clocking system.
Table 7-2. Possible Reference Clock Sources
CLOCK SOURCE
MODULES CLOCKED
COMMENTS
INTOSC1
Can be used to provide clock for:
Internal oscillator 1.
Zero-pin overhead 10-MHz internal oscillator.
•
•
•
Watchdog block
Main PLL
CPU-Timer 2
INTOSC2(1)
Can be used to provide clock for:
Internal oscillator 2.
Zero-pin overhead 10-MHz internal oscillator.
•
•
•
Main PLL
Auxiliary PLL
CPU-Timer 2
XTAL
Can be used to provide clock for:
External crystal or resonator connected between the X1 and X2 pins
or single-ended clock connected to the X1 pin.
•
•
•
Main PLL
Auxiliary PLL
CPU-Timer 2
AUXCLKIN
Can be used to provide clock for:
Single-ended 3.3-V level clock source. GPIO133/AUXCLKIN pin
should be used to provide the input clock.
•
•
Auxiliary PLL
CPU-Timer 2
(1) On reset, internal oscillator 2 (INTOSC2) is the default clock source for both system PLL (OSCCLK) and auxiliary PLL (AUXOSCCLK).
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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AUXPLLCLKEN
AUXCLKDIV
AUXOSCCLK
AUX PLL
AUXCLK
Divider
SYSCLKDIVSEL
AUXCLKSRCCEL
SYS
Divider
PLLRAWCLK
SYS PLL
AUXPLLRAWCLK
USBBITCLK
PLLSYSCLK
PLLCLKEN
OSCCLKSRCSEL
One per CMCLK peripheral
CMPCLKCRx.PERx
CMDIVSRCSEL
PLLSYSCLK
WDCLK
CMCLK
DIVIDER
CMCLK
DIVSRCSEL
NMIWDs
GSx RAMs
GPIOs
Watch Dog
Timers
CPU1
CPU2
ETHERCATCLK
MSG RAMs
IPC
XBARs
AnalogSubsys
SystemControl
EMIF1
CM.PERx.SYSCLK
ECATDIV
ETHERCATCLK
Divider
CPU2.CPUCLK
CM.PERx.SYSCLK
FPU
TMU
PHYCLKEN
CPU1.CPUCLK
VCRC
Flash
CPU1.SYSCLK
FPU
TMU
VCRC
Flash
DCSM
HWBIST
DCSM
MxRAM
DxRAM
BootROM
HWBIST
/4
CPU2.SYSCLK
CPUTIMERx
DMA
ETHERCAT
PALLOCATE0
.USB
ETHERCATPHYCLK
CPUTIMERx
DMA
CLA1
XINT
PIE
CPU1.PCLKCRx
CLA1
XINT
USB
LSx RAM
MSG RAMs
MxRAM
DxRAM
BootROM
BGCRC
ERAD
PIE
CPU1_CPU2_CM
.PERx.SYSCLK
LSx RAM
MSG RAMs
BGCRC
ERAD
CPU2.PCLKCRx
CPU2.PERx.SYSCLK
CANx
PALLOCATE0.CANx
CPUSELx.CANx
EMIF2
WD
X1 (XTAL)
One per SYSCLK peripheral
AUXCLKIN
CPU2.PCLKCRx
CPUSELx
One per LSPCLK peripheral
CANxBITCLK
CPUSELx
CPU1.PCLKCRx
CANxBIT Clock
CPU1.PCLKCRx
LSP
Divider
LSPCLKDIV
PERx.SYSCLK
CPU2.PCLKCRx
PERx.SYSCLK
EPWMCLKDIV
HRCAL
/1
/2
PERx.LSPCLK
ECAPx
EQEPx
SDFMx
SPIx
SCIx
McBSPx
ADC
One per ePWM peripheral
McBSPx Bit
Clock
CPU1.PCLKCRx
SPIx Bit Clock
SCIx Bit Clock
CPUSELx
EPWMCLK
CMPSSx
DACx
FSIx
I2C
PMBUS
DCCx
CPU2.PCLKCRx
ePWM
HRPWM
HRCAL
CPU1.PCLKCRx
HRCALCLK
Figure 7-7. Clocking System
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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SYSPLL / AUXPLL
OSCCLK/
INTCLK/
VCOCLK/
PLLRAWCLK/
AUXOSCCLK
AUXINTCLK
AUXVCOCLK
AUXPLLRAWCLK
÷
÷
VCO
(REFDIV+1)
(ODIV+1)
÷
IMULT
Figure 7-8. SYSPLL/AUXPLL
In Figure 7-8,
IMULT
fOSCCLK
REVDIV +1
=
ì
fPLLRAWCLK
ODIV +1
fAUXOSCCLK
IMULT
=
ì
fAUXPLLRAWCLK
REVDIV +1
ODIV +1
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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7.10.3.2 Clock Frequencies, Requirements, and Characteristics
This section provides the frequencies and timing requirements of the input clocks, PLL lock times, frequencies of
the internal clocks, and the frequency and switching characteristics of the output clock.
7.10.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
Section 7.10.3.2.1.1 lists the frequency requirements for the input clocks. Section 7.10.3.2.1.2 lists the XTAL
oscillator characteristics. Section 7.10.3.2.1.3 and Section 7.10.3.2.1.4 list the timing requirements for the input
clocks. Section 7.10.3.2.1.5 lists the PLL lock times for SYSPLL and AUXPLL.
7.10.3.2.1.1 Input Clock Frequency
MIN
10
MAX
20
UNIT
MHz
MHz
MHz
f(XTAL)
f(X1)
Frequency, X1/X2, from external crystal or resonator
Frequency, X1, from external oscillator
10
25
f(AUXI)
Frequency, AUXCLKIN, from external oscillator
10
60
7.10.3.2.1.2 XTAL Oscillator Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
–0.3
TYP
MAX
UNIT
X1 VIL
X1 VIH
Valid low-level input voltage
Valid high-level input voltage
0.3 * VDDIO
VDDIO + 0.3
V
V
0.7 * VDDIO
7.10.3.2.1.3 X1 Timing Requirements
MIN
MAX
UNIT
ns
tf(X1)
Fall time, X1
6
6
tr(X1)
Rise time, X1
ns
tw(X1L)
tw(X1H)
Pulse duration, X1 low as a percentage of tc(X1)
Pulse duration, X1 high as a percentage of tc(X1)
45%
45%
55%
55%
7.10.3.2.1.4 AUXCLKIN Timing Requirements
MIN
MAX
6
UNIT
ns
tf(AUXI)
Fall time, AUXCLKIN
tr(AUXI)
tw(AUXL)
tw(AUXH)
Rise time, AUXCLKIN
6
ns
Pulse duration, AUXCLKIN low as a percentage of tc(XCI)
Pulse duration, AUXCLKIN high as a percentage of tc(XCI)
45%
45%
55%
55%
7.10.3.2.1.5 APLL Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
PLL Lock Time
SYSPLL / AUXPLL Lock time(1)
MIN TYP
MAX UNIT
5µs + (1024 * (REFDIV + 1) * tc(OSCCLK)
)
µs
(1) The PLL lock time here defines the typical time that takes for the PLL to lock once PLL is enabled (SYSPLLCTL1[PLLENA]=1 or
AUXPLLCTL1[PLLENA]=1). Additional time to verify the PLL clock using Dual Clock Comparator (DCC) is not accounted here. TI
recommends using the latest example software from C2000Ware for initializing the PLLs. For the system PLL, see InitSysPll() or
SysCtl_setClock(). For the auxiliary PLL, see InitAuxPll() or SysCtl_setAuxClock().
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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7.10.3.2.2 Internal Clock Frequencies
Section 7.10.3.2.2.1 provides the clock frequencies for the internal clocks. Up to 1000 ppm of variation is
accounted for in the frequencies below when using an external clock source such as a crystal or resonator.
7.10.3.2.2.1 Internal Clock Frequencies
MIN
2
TYP
MAX
200
500
125
500
25
UNIT
MHz
ns
f(SYSCLK)
Frequency, device (system) clock
tc(SYSCLK)
f(CMCLK)
Period, device (system) clock
5
Frequency, Connectivity Manager (CM) clock
Period, Connectivity Manager (CM) clock
Frequency, system PLL going into VCO (after REFDIV)(1)
Frequency, system PLL VCO (before ODIV)
Frequency, system PLL output (before SYSCLK divider)
Frequency, auxiliary PLL going into VCO (after REFDIV)
Frequency, auxiliary PLL VCO (before ODIV)
Frequency, auxiliary PLL output (before AUXCLK divider)
Frequency, PLLSYSCLK
2
MHz
ns
tc(CMCLK)
8
f(INTCLK)
10
220
6
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
f(VCOCLK)
f(PLLRAWCLK)
f(AUXINTCLK)
f(AUXVCOCLK)
f(AUXPLLRAWCLK)
f(PLL)
600
400
25
10
220
6
600
400
200
2
f(PLL_LIMP)
f(AUXPLL)
f(AUXPLL_LIMP)
f(LSP)
Frequency, PLL Limp Frequency (2)
45/(ODIV+1)
45/(ODIV+1)
Frequency, AUXPLLCLK
2
150
Frequency, AUXPLL Limp Frequency (3)
Frequency, LSPCLK
2
5
200
500
tc(LSPCLK)
Period, LSPCLK
Frequency, OSCCLK (INTOSC1 or INTOSC2 or XTAL or
X1)
f(OSCCLK)
See respective clock
See respective clock
MHz
MHz
Frequency, auxiliary OSCCLK (INTOSC1 or INTOSC2 or
XTAL or X1 or AUXCLKIN)
f(AUXOSCCLK)
f(EPWM)
Frequency, EPWMCLK
Frequency, HRPWMCLK
200
200
MHz
MHz
f(HRPWM)
60
(1) INTOSC1 and INTOSC2 with +/-3% resolution can be used as a Reference Clock to PLL
(2) PLL output frequency when OSCCLK is dead (Loss of OSCCLK causes PLL to Limp)
(3) PLL output frequency when AUXOSCCLK is dead (Loss of AUXOSCCCLK causes AUXPLL to Limp)
7.10.3.2.3 Output Clock Frequency and Switching Characteristics
Section 7.10.3.2.3.1 lists the frequency and switching characteristics of the output clock, XCLKOUT.
7.10.3.2.3.1 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
over recommended operating conditions (unless otherwise noted)
PARAMETER(1)
MIN
MAX
5
UNIT
ns
tf(XCO)
Fall time, XCLKOUT
Rise time, XCLKOUT
tr(XCO)
tw(XCOL)
tw(XCOH)
f(XCO)
5
ns
Pulse duration, XCLKOUT low
Pulse duration, XCLKOUT high
Frequency, XCLKOUT
H – 2(2)
H – 2(2)
H + 2(2)
H + 2(2)
50
ns
ns
MHz
(1) A load of 40 pF is assumed for these parameters.
(2) H = 0.5tc(XCO)
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.10.3.3 Input Clocks
In addition to the internal 0-pin oscillators, multiple external clock source options are available. Figure 7-9 shows
the recommended methods of connecting crystals, resonators, and oscillators to pins X1/X2 (also referred to as
XTAL) and AUXCLKIN.
X1
X2
X1
X2
v
v
ssosc
ssosc
RESONATOR
CRYSTAL
R
C
C
L1
D
L2
X1
X2
GPIO133/AUXCLKIN
v
ssosc
NC
3.3V
VDD
CLK
3.3V
VDD
CLK
OUT
GND
OUT
GND
3.3V OSCILLATOR
3.3V OSCILLATOR
Figure 7-9. Connecting Input Clocks to a 2838x Device
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.10.3.4 Crystal Oscillator
When using a quartz crystal, it may be necessary to include a damping resistor (RD) in the crystal circuit to
prevent over-driving the crystal (drive level can be found in the crystal data sheet). In higher-frequency
applications (10 MHz or greater), RD is generally not required. If a damping resistor is required, RD should be as
small as possible because the size of the resistance affects start-up time (smaller RD = faster start-up time). TI
recommends that the crystal manufacturer characterize the crystal with the application board. Section 7.10.3.4.1
lists the crystal oscillator parameters. Table 7-3 lists the crystal equivalent series resistance (ESR) requirements.
Section 7.10.3.4.3 lists the crystal oscillator electrical characteristics.
7.10.3.4.1 Crystal Oscillator Parameters
MIN
MAX
24
UNIT
pF
CL1, CL2
C0
Load capacitance
12
Crystal shunt capacitance
7
pF
7.10.3.4.2 Crystal Equivalent Series Resistance (ESR) Requirements Table
For Table 7-3, ESR = Negative Resistance/3.
Table 7-3. Crystal Equivalent Series Resistance (ESR) Requirements
MAXIMUM ESR (Ω)
(CL1 = CL2 = 12 pF)
MAXIMUM ESR (Ω)
(CL1 = CL2 = 24 pF)
CRYSTAL FREQUENCY (MHz)
10
12
14
16
18
20
55
50
50
45
45
45
110
95
90
75
65
50
7.10.3.4.3 Crystal Oscillator Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ESR MAX = 110 Ω
CL1 = CL2 = 24 pF
C0 = 7 pF
f = 10 MHz
4
ms
Start-up
time(1)
ESR MAX = 50 Ω
CL1 = CL2 = 24 pF
C0 = 7 pF
f = 20 MHz
2
ms
Crystal drive level (DL)
1
mW
(1) Start-up time is dependent on the crystal and tank circuit components. TI recommends that the crystal vendor characterize the
application with the chosen crystal.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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7.10.3.5 Internal Oscillators
All F2838x devices contain two independent internal oscillators, referred to as INTOSC1 and INTOSC2. By
default, both oscillators are enabled at power up. INTOSC2 is set as the source for the system reference clock
(OSCCLK) and INTOSC1 is set as the backup clock source. INTOSC1 can also be manually configured as the
system reference clock (OSCCLK).
Section 7.10.3.5.1 provides the electrical characteristics of the internal oscillators to determine if this module
meets the clocking requirements of the application.
Note
This oscillator cannot be used as the PLL source if the PLLSYSCLK is configured to frequencies
above 194 MHz.
7.10.3.5.1 INTOSC Characteristics
over recommended operating conditions (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
MIN
TYP
MAX
UNIT
MHz
%
Frequency, INTOSC1 and
INTOSC2
fINTOSC
9.7
10
10.3
Frequency stability at room
temperature
30°C, Nominal
VDD
±0.1
±0.2
fINTOSC-STABILITY
Frequency stability over VDD
Start-up and settling time
30°C
%
tINT0SC-ST
20
µs
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.10.4 Flash Parameters
The on-chip flash memory is tightly integrated to the CPU, allowing code execution directly from flash through
128-bit-wide prefetch reads and a pipeline buffer. Flash performance for sequential code is equal to execution
from RAM. Factoring in discontinuities, most applications will run with an efficiency of approximately 80% relative
to code executing from RAM.
This device also has an One-Time-Programmable (OTP) sector used for the dual code security module (DCSM),
which cannot be erased after it is programmed.
Table 7-4 lists the minimum required flash wait states at different frequencies. The Flash Parameters table lists
the flash parameters.
Table 7-4. Flash Wait States
CPUCLK (MHz)
MINIMUM WAIT STATES (1)
EXTERNAL OSCILLATOR OR CRYSTAL
150 < CPUCLK ≤ 200
INTOSC1 OR INTOSC2
145 < CPUCLK ≤ 194
97 < CPUCLK ≤ 145
48 < CPUCLK ≤ 97
CPUCLK ≤ 48
3
2
1
0
100 < CPUCLK ≤ 150
50 < CPUCLK ≤ 100
CPUCLK ≤ 50
(1) Minimum required FRDCNTL[RWAIT].
Table 7-5. Flash Parameters
PARAMETER
MIN
TYP
40
MAX
300
UNIT
µs
128 data bits + 16 ECC bits
8KW sector
Program Time(1)
90
180
ms
Program Time(1)
32KW sector
360
30
720
ms
EraseTime(2) at < 25 cycles
EraseTime(2) at 1000 cycles
EraseTime(2) at 2000 cycles
EraseTime(2) at 20K cycles
Nwec Write/Erase Cycles
8KW or 32KW sector
8KW or 32KW sector
8KW or 32KW sector
8KW or 32KW sector
55
ms
40
350
ms
50
600
ms
110
4000
20000
ms
cycles
years
tretention Data retention duration at TJ = 85oC
20
(1) Program time is at the maximum device frequency. Program time includes overhead of the flash state machine but does not include
the time to transfer the following into RAM:
• Code that uses flash API to program the flash
• Flash API itself
• Flash data to be programmed
In other words, the time indicated in this table is applicable after all the required code/data is available in the device RAM, ready for
programming. The transfer time will significantly vary depending on the speed of the emulator used.
Program time calculation is based on programming 144 bits at a time at the specified operating frequency. Program time includes
Program verify by the CPU. The program time does not degrade with write/erase (W/E) cycling, but the erase time does.
Erase time includes Erase verify by the CPU and does not involve any data transfer.
(2) Erase time includes Erase verify by the CPU.
Note
The Main Array flash programming must be aligned to 64-bit address boundaries and each 64-bit
word may only be programmed once per write/erase cycle. For more details, see the "Flash: Minimum
Programming Word Size" advisory in the TMS320F2838x Real-Time MCUs Silicon Errata.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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7.10.5 Emulation/JTAG
The JTAG port has five dedicated pins: TRSTn, TMS, TDI, TDO, and TCK. The TRSTn signal should always be
pulled down through a 2.2-kΩ pulldown resistor on the board. This MCU does not support the EMU0 and EMU1
signals that are present on 14-pin and 20-pin emulation headers. These signals should always be pulled up at
the emulation header through a pair of board pullup resistors ranging from 2.2 kΩ to 4.7 kΩ (depending on the
drive strength of the debugger ports). Typically, a 2.2-kΩ value is used.
See Figure 7-10 to see how the 14-pin JTAG header connects to the MCU’s JTAG port signals. Figure 7-11
shows how to connect to the 20-pin header. The 20-pin JTAG header terminals EMU2, EMU3, and EMU4 are
not used and should be grounded.
The PD (Power Detect) terminal of the JTAG debug probe header should be connected to the board 3.3-V
supply. Header GND terminals should be connected to board ground. TDIS (Cable Disconnect Sense) should
also be connected to board ground. The JTAG clock should be looped from the header TCK output terminal back
to the RTCK input terminal of the header (to sense clock continuity by the JTAG debug probe). Header terminal
RESETn is an open-drain output from the JTAG debug probe header that enables board components to be reset
through JTAG debug probe commands (available only through the 20-pin header).
Typically, no buffers are needed on the JTAG signals when the distance between the MCU target and the JTAG
header is smaller than 6 inches (15.24 cm), and no other devices are present on the JTAG chain. Otherwise,
each signal should be buffered. Additionally, for most JTAG debug probe operations at 10 MHz, no series
resistors are needed on the JTAG signals. However, if high emulation speeds are expected, 22-Ω resistors
should be placed in series on each JTAG signal.
For more information about hardware breakpoints and watchpoints, see Hardware Breakpoints and Watchpoints
for C28x in CCS.
For more information about JTAG emulation, see the XDS Target Connection Guide.
Distance between the header and the target
should be less than 6 inches (15.24 cm).
2.2 kW
GND
TRSTn
TMS
TDI
2
1
3
TMS
TDI
TRSTn
TDIS
4
GND
100 W
MCU
5
6
3.3 V
PD
KEY
7
8
TDO
TCK
TDO
RTCK
TCK
GND
GND
GND
EMU1
9
10
12
14
11
13
4.7 kW
4.7 kW
3.3 V
EMU0
3.3 V
Figure 7-10. Connecting to the 14-Pin JTAG Header
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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Distance between the header and the target
should be less than 6 inches (15.24 cm).
2.2 kW
TRSTn
TMS
TDI
GND
GND
2
1
3
TMS
TRSTn
TDIS
4
TDI
100 W
MCU
5
6
3.3V
PD
KEY
7
8
TDO
TCK
TDO
GND
GND
GND
EMU1
GND
EMU3
GND
9
10
12
14
16
18
20
RTCK
TCK
11
13
15
17
19
4.7 kW
4.7 kW
3.3 V
EMU0
RESETn
EMU2
EMU4
3.3 V
open
drain
A low pulse from the JTAG debug probe
can be tied with other reset sources
to reset the board.
GND
GND
Figure 7-11. Connecting to the 20-Pin JTAG Header
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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7.10.5.1 JTAG Electrical Data and Timing
Section 7.10.5.1.1 lists the JTAG timing requirements. Section 7.10.5.1.2 lists the JTAG switching
characteristics. Figure 7-12 shows the JTAG timing.
7.10.5.1.1 JTAG Timing Requirements
NO.
MIN
66.66
26.66
26.66
13
MAX
UNIT
ns
1
tc(TCK)
Cycle time, TCK
1a
1b
tw(TCKH)
Pulse duration, TCK high (40% of tc)
Pulse duration, TCK low (40% of tc)
Input setup time, TDI valid to TCK high
Input setup time, TMS valid to TCK high
Input hold time, TDI valid from TCK high
Input hold time, TMS valid from TCK high
ns
tw(TCKL)
ns
tsu(TDI-TCKH)
tsu(TMS-TCKH)
th(TCKH-TDI)
th(TCKH-TMS)
3
4
ns
ns
13
11
11
7.10.5.1.2 JTAG Switching Characteristics
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER
MIN
MAX
UNIT
2
td(TCKL-TDO)
Delay time, TCK low to TDO valid
6
30
ns
7.10.5.1.3 JTAG Timing
1
1a
1b
TCK
TDO
2
3
4
TDI/TMS
Figure 7-12. JTAG Timing
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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7.10.6 GPIO Electrical Data and Timing
The peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. On reset, GPIO pins
are configured as inputs. For specific inputs, the user can also select the number of input qualification cycles to
filter unwanted noise glitches.
The GPIO module contains an Output X-BAR which allows an assortment of internal signals to be routed to a
GPIO in the GPIO mux positions denoted as OUTPUTXBARx. The GPIO module also contains an Input X-BAR
which is used to route signals from any GPIO input to different IP blocks such as the ADC(s), eCAP(s),
ePWM(s), and external interrupts. For more details, see the X-BAR chapter in the TMS320F2838x Real-Time
Microcontrollers Technical Reference Manual.
7.10.6.1 GPIO - Output Timing
Section 7.10.6.1.1 lists the general-purpose output switching characteristics. Figure 7-13 shows the general-
purpose output timing.
7.10.6.1.1 General-Purpose Output Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
8(1)
8(1)
50
UNIT
ns
tr(GPO)
tf(GPO)
tfGPO
Rise time, GPIO switching low to high
All GPIOs
All GPIOs
Fall time, GPIO switching high to low
Toggling frequency, GPIO pins
ns
MHz
(1) Rise time and fall time vary with load. These values assume a 40-pF load.
7.10.6.1.2 General-Purpose Output Timing
GPIO
tr(GPO)
tf(GPO)
Figure 7-13. General-Purpose Output Timing
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.10.6.2 GPIO - Input Timing
Section 7.10.6.2.1 lists the general-purpose input timing requirements. Figure 7-14 shows the sampling mode.
7.10.6.2.1 General-Purpose Input Timing Requirements
MIN
1tc(SYSCLK)
MAX
UNIT
cycles
cycles
cycles
cycles
cycles
QUALPRD = 0
QUALPRD ≠ 0
tw(SP)
Sampling period
2tc(SYSCLK) * QUALPRD
tw(SP) * (n(1) – 1)
tw(IQSW)
Input qualifier sampling window
Pulse duration, GPIO low/high
Synchronous mode
With input qualifier
2tc(SYSCLK)
(2)
tw(GPI)
tw(IQSW) + tw(SP) + 1tc(SYSCLK)
(1) "n" represents the number of qualification samples as defined by GPxQSELn register.
(2) For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.
7.10.6.2.2 Sampling Mode
(A)
GPIO Signal
GPxQSELn = 1,0 (6 samples)
1
1
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
tw(SP)
Sampling Period determined
by GPxCTRL[QUALPRD](B)
tw(IQSW)
(SYSCLK cycle * 2 * QUALPRD) * 5(C)
Sampling Window
SYSCLK
QUALPRD = 1
(SYSCLK/2)
(D)
Output From
Qualifier
A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can vary from 00 to
0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLK cycle. For any other value "n", the qualification sampling period in 2n
SYSCLK cycles (that is, at every 2n SYSCLK cycles, the GPIO pin will be sampled).
B. The qualification period selected through the GPxCTRL register applies to groups of 8 GPIO pins.
C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is used.
D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLK cycles or greater. In other words,
the inputs should be stable for (5 x QUALPRD x 2) SYSCLK cycles. This would ensure 5 sampling periods for detection to occur.
Because external signals are driven asynchronously, an 13-SYSCLK-wide pulse ensures reliable recognition.
Figure 7-14. Sampling Mode
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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7.10.6.3 Sampling Window Width for Input Signals
The following section summarizes the sampling window width for input signals for various input qualifier
configurations.
Sampling frequency denotes how often a signal is sampled with respect to SYSCLK.
Sampling frequency = SYSCLK/(2 ´ QUALPRD), if QUALPRD ¹ 0
(1)
Sampling frequency = SYSCLK, if QUALPRD = 0
(2)
Sampling period = SYSCLK cycle ´ 2 ´ QUALPRD, if QUALPRD ¹ 0
(3)
In Equation 1, Equation 2, and Equation 3, SYSCLK cycle indicates the time period of SYSCLK.
Sampling period = SYSCLK cycle, if QUALPRD = 0
In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of the
signal. This is determined by the value written to GPxQSELn register.
Case 1:
Qualification using 3 samples
Sampling window width = (SYSCLK cycle × 2 × QUALPRD) × 2, if QUALPRD ≠ 0
Sampling window width = (SYSCLK cycle) × 2, if QUALPRD = 0
Case 2:
Qualification using 6 samples
Sampling window width = (SYSCLK cycle × 2 × QUALPRD) × 5, if QUALPRD ≠ 0
Sampling window width = (SYSCLK cycle) × 5, if QUALPRD = 0
Figure 7-15 shows the general-purpose input timing.
SYSCLK
GPIOxn
tw(GPI)
Figure 7-15. General-Purpose Input Timing
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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7.10.7 Interrupts
Figure 7-16 provides a high-level view of the interrupt architecture.
As shown in Figure 7-16, the devices support five external interrupts (XINT1 to XINT5) that can be mapped onto
any of the GPIO pins.
In this device, 16 ePIE block interrupts are grouped into 1 CPU interrupt. In total, there are 12 CPU interrupt
groups, with 16 interrupts per group.
CM_STATUS
SYS_ERR
CPU1.CRC
CPU1.CLA1.CRC
CPU1.TINT0
CPU1.TIMER0
CPU1.LPMINT
CPU1.WDINT
CPU1.NMIWD
CMNMIWDRSn
LPM Logic
CPU1.WD
CPU1.WAKEINT
NMI
CPU1
CPU1
ePIE
CPU1.XINT1 Control
INPUTXBAR4
INT1
To
INT12
GPIO0
GPIO1
...
CPU1.XINT2 Control
CPU1.XINT3 Control
CPU1.XINT4 Control
CPU1.XINT5 Control
INPUTXBAR5
INPUTXBAR6
INPUTXBAR13
Input
X-Bar
...
GPIOx
INPUTXBAR14
CPU1.TINT1
CPU1.TINT2
INT13
INT14
CPU1.TIMER1
CPU1.TIMER2
IPC
4 CPU-to-CPU
8 CM-to-CPU
Interrupts
Peripherals
NMI
CPU2.NMIWD
CPU2
CPU2.XINT1 Control
CPU2.XINT2 Control
CPU2.XINT3 Control
CPU2.XINT4 Control
CPU2.XINT5 Control
INT1
To
INT12
CPU2
ePIE
CPU2.TINT1
CPU2.TINT2
CPU2.TIMER1
CPU2.TIMER2
INT13
INT14
CPU2.LPMINT
CPU2.WDINT
LPM Logic
CPU2.WD
CPU2.WAKEINT
CPU2.TINT0
CPU2.TIMER0
CPU2.CRC
CPU2.CLA1.CRC
SYS_ERR
Figure 7-16. External and ePIE Interrupt Sources
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TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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7.10.7.1 External Interrupt (XINT) Electrical Data and Timing
Section 7.10.7.1.1 lists the external interrupt timing requirements. Section 7.10.7.1.2 lists the external interrupt
switching characteristics. Figure 7-17 shows the external interrupt timing. For an explanation of the input qualifier
parameters, see Section 7.10.6.2.1.
7.10.7.1.1 External Interrupt Timing Requirements
MIN
2tc(SYSCLK)
MAX
UNIT
cycles
cycles
Synchronous
With qualifier
tw(INT)
Pulse duration, INT input low/high
tw(IQSW) + tw(SP) + 1tc(SYSCLK)
7.10.7.1.2 External Interrupt Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
td(INT) Delay time, INT low/high to interrupt-vector fetch(1)
(1) This assumes that the ISR is in a single-cycle memory.
7.10.7.1.3 External Interrupt Timing
tw(IQSW) + 14tc(SYSCLK)
tw(IQSW) + tw(SP) + 14tc(SYSCLK) cycles
tw(INT)
XINT1, XINT2, XINT3,
XINT4, XINT5
td(INT)
Address bus
(internal)
Interrupt Vector
Figure 7-17. External Interrupt Timing
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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7.10.8 Low-Power Modes
This device has two clock-gating low-power modes.
Further details, as well as the entry and exit procedure, for all of the low-power modes can be found in the Low
Power Modes section of the TMS320F2838x Real-Time Microcontrollers Technical Reference Manual.
7.10.8.1 Clock-Gating Low-Power Modes
IDLE and STANDBY modes on this device are similar to those on other C28x devices. Table 7-6 describes the
effect on the system when any of the clock-gating low-power modes are entered.
Table 7-6. Effect of Clock-Gating Low-Power Modes on the Device
MODULES/CLOCK DOMAIN
CPU1 IDLE
Active
Active
Gated
N/A
CPU1 STANDBY
CPU2 IDLE
CPU2 STANDBY
CPU1.CLKIN
Gated
Gated
Gated
N/A
N/A
N/A
N/A
CPU1.SYSCLK
CPU1.CPUCLK
CPU2.CLKIN
N/A
N/A
N/A
Active
Active
Gated
Active
Gated
Gated
Gated
CPU2.SYSCLK
CPU2.CPUCLK
N/A
N/A
N/A
N/A
Clock to modules Connected to
PERx.SYSCLK
Active
Gated if CPUSEL.PERx =
CPU1
Gated if CPUSEL.PERx =
CPU2
CPU1.WDCLK
CPU2.WDCLK
AUXPLLCLK
PLL
Active
N/A
Active
N/A
N/A
N/A
Active
Active
Active
Active
Active
Active
Powered
Powered
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Powered
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Powered
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INTOSC1
INTOSC2
Flash(1)
X1/X2 Crystal Oscillator
(1) Entering any of the low-power modes does not automatically power down the flash. The application should always power down the
flash memory before entering a low-power mode.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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7.10.8.2 Low-Power Mode Wakeup Timing
Section 7.10.8.2.1 lists the IDLE mode timing requirements, Section 7.10.8.2.2 lists the switching characteristics,
and Figure 7-18 shows the timing diagram for IDLE mode. For an explanation of the input qualifier parameters,
see Section 7.10.6.2.1.
7.10.8.2.1 IDLE Mode Timing Requirements
MIN
2tc(SYSCLK)
MAX
UNIT
Without input qualifier
With input qualifier
tw(WAKE)
Pulse duration, external wake-up signal
cycles
2tc(SYSCLK) + tw(IQSW)
7.10.8.2.2 IDLE Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
40tc(SYSCLK) cycles
Wakeup from Flash
(Flash module in active state)
40tc(SYSCLK) + tw(WAKE) cycles
Delay time,
external wake
(2)
6700tc(SYSCLK)
cycles
Wakeup from Flash
(Flash module in sleep state)
td(WAKE-IDLE) signal to program
execution
6700tc(SYSCLK) (2) + tw(WAKE) cycles
25tc(SYSCLK) cycles
resume(1)
Wakeup from RAM
25tc(SYSCLK) + tw(WAKE) cycles
(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered
by the wake-up signal) involves additional latency.
(2) This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and
FPAC1[PSLEEP]. This value can be realized when SYSCLK is 200 MHz, RWAIT is 3, and FPAC1[PSLEEP] is 0x860.
7.10.8.2.3 IDLE Entry and Exit Timing Diagram
td(WAKE-IDLE)
Address/Data
(internal)
XCLKOUT
tw(WAKE)
WAKE(A)
A. WAKE can be any enabled interrupt, WDINT or XRSn. After the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum)
is needed before the wake-up signal could be asserted.
Figure 7-18. IDLE Entry and Exit Timing Diagram
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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Section 7.10.8.2.4 lists the STANDBY mode timing requirements, Section 7.10.8.2.5 lists the switching
characteristics, and Figure 7-19 shows the timing diagram for STANDBY mode.
7.10.8.2.4 STANDBY Mode Timing Requirements
MIN
MAX
UNIT
QUALSTDBY = 0 | 2tc(OSCCLK)
QUALSTDBY > 0 |
3tc(OSCCLK)
Pulse duration, external
wake-up signal
tw(WAKE-INT)
cycles
(2 + QUALSTDBY) * tc(OSCCLK)
(1)
(2 + QUALSTDBY)tc(OSCCLK)
(1) QUALSTDBY is a 6-bit field in the LPMCR register.
7.10.8.2.5 STANDBY Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
Delay time, IDLE instruction executed to
XCLKOUT stop
td(IDLE-XCOS)
16tc(INTOSC1) cycles
Wakeup from flash
(Flash module in
active state)
td(WAKE-STBY)
175tc(SYSCLK) + tw(WAKE-INT) cycles
Delay time, external wake signal to program
execution resume(1)
Wakeup from flash
(Flash module in
sleep state)
td(WAKE-STBY)
td(WAKE-STBY)
6700tc(SYSCLK) (2) + tw(WAKE-INT) cycles
Wakeup from RAM
3tc(OSC) + 15tc(SYSCLK) + tw(WAKE-INT) cycles
(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered
by the wake-up signal) involves additional latency.
(2) This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and
FPAC1[PSLEEP]. This value can be realized when SYSCLK is 200 MHz, RWAIT is 3, and FPAC1[PSLEEP] is 0x860.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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7.10.8.2.6 STANDBY Entry and Exit Timing Diagram
(C)
(F)
(A)
(B)
(D)(E)
(G)
Device
Status
STANDBY
STANDBY
Normal Execution
Flushing Pipeline
Wake-up
Signal
tw(WAKE-INT)
td(WAKE-STBY)
OSCCLK
XCLKOUT
td(IDLE-XCOS)
A. IDLE instruction is executed to put the device into STANDBY mode.
B. The LPM block responds to the STANDBY signal, SYSCLK is held for a maximum 16 INTOSC1 clock cycles before being turned off.
This delay enables the CPU pipeline and any other pending operations to flush properly.
C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in STANDBY mode. After
the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum) is needed before the wake-up signal could be asserted.
D. The external wake-up signal is driven active.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal
must be free of glitches. If a noisy signal is fed to a GPIO pin, the wakeup behavior of the device will not be deterministic and the device
may not exit low-power mode for subsequent wakeup pulses.
F. After a latency period, the STANDBY mode is exited.
G. Normal execution resumes. The device will respond to the interrupt (if enabled).
Figure 7-19. STANDBY Entry and Exit Timing Diagram
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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7.10.9 External Memory Interface (EMIF)
The EMIF provides a means of connecting the CPU to various external storage devices like asynchronous
memories (SRAM, NOR flash) or synchronous memory (SDRAM).
7.10.9.1 Asynchronous Memory Support
The EMIF supports asynchronous memories:
•
•
SRAMs
NOR Flash memories
There is an external wait input that allows slower asynchronous memories to extend the memory access. The
EMIF module supports up to three chip selects ( EMIF_CS[4:2]). Each chip select has the following individually
programmable attributes:
•
•
•
•
•
•
Data bus width
Read cycle timings: setup, hold, strobe
Write cycle timings: setup, hold, strobe
Bus turnaround time
Extended wait option with programmable time-out
Select strobe option
7.10.9.2 Synchronous DRAM Support
The EMIF memory controller is compliant with the JESD21-C SDR SDRAMs that use a 32-bit or 16-bit data bus.
The EMIF has a single SDRAM chip select ( EMIF_CS[0]).
The address space of the EMIF, for the synchronous memory (SDRAM), lies beyond the 22-bit range of the
program address bus and can only be accessed through the data bus, which places a restriction on the C
compiler being able to work effectively on data in this space. Therefore, when using SDRAM, the user is advised
to copy data (using the DMA) from external memory to RAM before working on it. See the examples in
C2000Ware for C2000 MCUs and the TMS320F2838x Real-Time Microcontrollers Technical Reference Manual.
SDRAM configurations supported are:
•
•
•
•
•
One-bank, two-bank, and four-bank SDRAM devices
Devices with 8-, 9-, 10-, and 11-column addresses
CAS latency of two or three clock cycles
16-bit/32-bit data bus width
3.3-V LVCMOS interface
Additionally, the EMIF supports placing the SDRAM in self-refresh and power-down modes. Self-refresh mode
allows the SDRAM to be put in a low-power state while still retaining memory contents because the SDRAM will
continue to refresh itself even without clocks from the microcontroller. Power-down mode achieves even lower
power, except the microcontroller must periodically wake up and issue refreshes if data retention is required. The
EMIF module does not support mobile SDRAM devices.
On this device, the EMIF does not support burst access for SDRAM configurations. This means every access to
an external SDRAM device will have CAS latency.
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TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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7.10.9.3 EMIF Electrical Data and Timing
7.10.9.3.1 Asynchronous RAM
Section 7.10.9.3.1.1 lists the EMIF asynchronous memory timing requirements. Section 7.10.9.3.1.2 lists the
EMIF asynchronous memory switching characteristics. Figure 7-20 through Figure 7-23 show the EMIF
asynchronous memory timing diagrams.
7.10.9.3.1.1 EMIF Asynchronous Memory Timing Requirements
NO.
MIN
MAX
UNIT
Reads and Writes
E
EMIF clock period
tc(SYSCLK)
2E(1)
ns
ns
2
Reads
12
tw(EM_WAIT)
Pulse duration, EMxWAIT assertion and deassertion
tsu(EMDV-EMOEH)
th(EMOEH-EMDIV)
Setup time, EMxD[y:0] valid before EMxOE high
Hold time, EMxD[y:0] valid after EMxOE high
15
0
ns
ns
13
Setup Time, EMxWAIT asserted before end of Strobe
Phase(2)
14
Writes
28
tsu(EMOEL-EMWAIT)
4E+20(1)
ns
Setup Time, EMxWAIT asserted before end of Strobe
Phase(2)
tsu(EMWEL-EMWAIT)
4E+20(1)
ns
(1) E = EMxCLK period in ns.
(2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EMxWAIT must be asserted to add extended
wait states. Figure 7-21 and Figure 7-23 describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
7.10.9.3.1.2 EMIF Asynchronous Memory Switching Characteristics
NO.
PARAMETER(1) (2) (3)
MIN
MAX UNIT
1
td(TURNAROUND)
Turn around time
(TA)*E–3
(TA)*E+2
ns
Reads
EMIF read cycle time (EW = 0)
(RS+RST+RH)*E–3
(RS+RST+RH)*E+2
ns
ns
3
4
tc(EMRCYCLE)
(RS+RST+RH+
(EWC*16))*E–3
(RS+RST+RH+
(EWC*16))*E+2
EMIF read cycle time (EW = 1)
Output setup time, EMxCS[y:2] low to
EMxOE low (SS = 0)
(RS)*E–3
–3
(RS)*E+2
2
ns
ns
ns
ns
ns
ns
ns
ns
tsu(EMCEL-EMOEL)
Output setup time, EMxCS[y:2] low to
EMxOE low (SS = 1)
Output hold time, EMxOE high to
EMxCS[y:2] high (SS = 0)
(RH)*E–3
–3
(RH)*E
0
5
th(EMOEH-EMCEH)
Output hold time, EMxOE high to
EMxCS[y:2] high (SS = 1)
Output setup time, EMxBA[y:0] valid to
EMxOE low
6
7
8
9
tsu(EMBAV-EMOEL)
th(EMOEH-EMBAIV)
tsu(EMAV-EMOEL)
th(EMOEH-EMAIV)
(RS)*E–3
(RH)*E–3
(RS)*E–3
(RH)*E–3
(RS)*E+2
(RH)*E
(RS)*E+2
(RH)*E
Output hold time, EMxOE high to
EMxBA[y:0] invalid
Output setup time, EMxA[y:0] valid to
EMxOE low
Output hold time, EMxOE high to
EMxA[y:0] invalid
EMxOE active low width (EW = 0)
EMxOE active low width (EW = 1)
(RST)*E–1
(RST)*E+1
ns
ns
10
tw(EMOEL)
(RST+(EWC*16))*E–1
(RST+(EWC*16))*E+1
Delay time from EMxWAIT deasserted
to EMxOE high
11
29
30
td(EMWAITH-EMOEH)
tsu(EMDQMV-EMOEL)
th(EMOEH-EMDQMIV)
4*E+10
(RS)*E–3
(RH)*E–3
5*E+15
(RS)*E+2
(RH)*E
ns
ns
ns
Output setup time, EMxDQM[y:0] valid
to EMxOE low
Output hold time, EMxOE high to
EMxDQM[y:0] invalid
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TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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7.10.9.3.1.2 EMIF Asynchronous Memory Switching Characteristics (continued)
NO.
PARAMETER(1) (2) (3)
MIN
Writes
EMIF write cycle time (EW = 0)
(WS+WST+WH)*E–3
(WS+WST+WH)*E+2
ns
ns
15
16
tc(EMWCYCLE)
(WS+WST+WH+
(EWC*16))*E–3
(WS+WST+WH+
(EWC*16))*E+2
EMIF write cycle time (EW = 1)
Output setup time, EMxCS[y:2] low to
EMxWE low (SS = 0)
(WS)*E–3
–3
(WS)*E+2
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu(EMCEL-EMWEL)
Output setup time, EMxCS[y:2] low to
EMxWE low (SS = 1)
Output hold time, EMxWE high to
EMxCS[y:2] high (SS = 0)
(WH)*E–3
–3
(WH)*E
17
th(EMWEH-EMCEH)
Output hold time, EMxWE high to
EMxCS[y:2] high (SS = 1)
0
Output setup time, EMxDQM[y:0] valid
to EMxWE low
18
19
20
21
22
23
tsu(EMDQMV-EMWEL)
th(EMWEH-EMDQMIV)
tsu(EMBAV-EMWEL)
th(EMWEH-EMBAIV)
tsu(EMAV-EMWEL)
th(EMWEH-EMAIV)
(WS)*E–3
(WH)*E–3
(WS)*E–3
(WH)*E–3
(WS)*E–3
(WH)*E–3
(WST)*E–1
(WST+(EWC*16))*E–1
4*E+10
(WS)*E+2
(WH)*E
Output hold time, EMxWE high to
EMxDQM[y:0] invalid
Output setup time, EMxBA[y:0] valid to
EMxWE low
(WS)*E+2
(WH)*E
Output hold time, EMxWE high to
EMxBA[y:0] invalid
Output setup time, EMxA[y:0] valid to
EMxWE low
(WS)*E+2
(WH)*E
Output hold time, EMxWE high to
EMxA[y:0] invalid
EMxWE active low width
(EW = 0)
(WST)*E+1
(WST+(EWC*16))*E+1
5*E+15
24
tw(EMWEL)
EMxWE active low width
(EW = 1)
Delay time from EMxWAIT deasserted
to EMxWE high
25
26
27
td(EMWAITH-EMWEH)
tsu(EMDV-EMWEL)
th(EMWEH-EMDIV)
Output setup time, EMxD[y:0] valid to
EMxWE low
(WS)*E–3
(WH)*E–3
(WS)*E+2
(WH)*E
Output hold time, EMxWE high to
EMxD[y:0] invalid
(1) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold,
MEWC = Maximum external wait cycles. These parameters are programmed through the Asynchronous Bank and Asynchronous Wait
Cycle Configuration Registers. These support the following ranges of values: TA[4–1], RS[16–1], RST[64–4], RH[8–1], WS[16–1],
WST[64–1], WH[8–1], and MEWC[1–256]. See the TMS320F2838x Real-Time Microcontrollers Technical Reference Manual for more
information.
(2) E = EMxCLK period in ns.
(3) EWC = external wait cycles determined by EMxWAIT input signal. EWC supports the following range of values. EWC[256–1]. The
maximum wait time before time-out is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. See the
TMS320F2838x Real-Time Microcontrollers Technical Reference Manual for more information.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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7.10.9.3.1.3 EMIF Asynchronous Memory Timing Diagrams
3
1
EMxCS[y:2]
EMxBA[y:0]
EMxA[y:0]
EMxDQM[y:0]
4
8
5
9
6
7
29
30
10
EMxOE
13
12
EMxD[y:0]
EMxWE
Figure 7-20. Asynchronous Memory Read Timing
Extended Due to EMxWAIT
SETUP
STROBE
STROBE HOLD
EMxCS[y:2]
EMxBA[y:0]
EMxA[y:0]
EMxD[y:0]
14
11
EMxOE
2
2
EMxWAIT
Asserted
Deasserted
Figure 7-21. EMxWAIT Read Timing Requirements
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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15
1
EMxCS[y:2]
EMxBA[y:0]
EMxA[y:0]
EMxDQM[y:0]
16
18
17
19
21
23
20
24
22
EMxWE
27
26
EMxD[y:0]
EMxOE
Figure 7-22. Asynchronous Memory Write Timing
Extended Due to EMxWAIT
SETUP
STROBE
STROBE HOLD
EMxCS[y:2]
EMxBA[y:0]
EMxA[y:0]
EMxD[y:0]
28
25
EMxWE
2
2
EMxWAIT
Asserted
Deasserted
Figure 7-23. EMxWAIT Write Timing Requirements
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.10.9.3.2 Synchronous RAM
Section 7.10.9.3.2.1 lists the EMIF synchronous memory timing requirements. Section 7.10.9.3.2.2 lists the
EMIF synchronous memory switching characteristics. Figure 7-24 and Figure 7-25 show the synchronous
memory timing diagrams.
7.10.9.3.2.1 EMIF Synchronous Memory Timing Requirements
NO.
MIN
2
MAX
UNIT
ns
19
tsu(EMIFDV-EM_CLKH)
th(CLKH-DIV)
Input setup time, read data valid on EMxD[y:0] before EMxCLK rising
Input hold time, read data valid on EMxD[y:0] after EMxCLK rising
20
1.5
ns
7.10.9.3.2.2 EMIF Synchronous Memory Switching Characteristics
NO.
PARAMETER
MIN
10
3
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
tc(CLK)
Cycle time, EMIF clock EMxCLK
2
tw(CLK)
Pulse width, EMIF clock EMxCLK high or low
3
td(CLKH-CSV)
toh(CLKH-CSIV)
td(CLKH-DQMV)
toh(CLKH-DQMIV)
td(CLKH-AV)
Delay time, EMxCLK rising to EMxCS[y:2] valid
Output hold time, EMxCLK rising to EMxCS[y:2] invalid
Delay time, EMxCLK rising to EMxDQM[y:0] valid
Output hold time, EMxCLK rising to EMxDQM[y:0] invalid
Delay time, EMxCLK rising to EMxA[y:0] and EMxBA[y:0] valid
Output hold time, EMxCLK rising to EMxA[y:0] and EMxBA[y:0] invalid
Delay time, EMxCLK rising to EMxD[y:0] valid
8
8
8
8
8
8
8
8
4
1
1
1
1
1
1
1
1
5
6
7
8
toh(CLKH-AIV)
td(CLKH-DV)
9
10
11
12
13
14
15
16
17
18
toh(CLKH-DIV)
td(CLKH-RASV)
toh(CLKH-RASIV)
td(CLKH-CASV)
toh(CLKH-CASIV)
td(CLKH-WEV)
toh(CLKH-WEIV)
td(CLKH-DHZ)
toh(CLKH-DLZ)
Output hold time, EMxCLK rising to EMxD[y:0] invalid
Delay time, EMxCLK rising to EMxRAS valid
Output hold time, EMxCLK rising to EMxRAS invalid
Delay time, EMxCLK rising to EMxCAS valid
Output hold time, EMxCLK rising to EMxCAS invalid
Delay time, EMxCLK rising to EMxWE valid
Output hold time, EMxCLK rising to EMxWE invalid
Delay time, EMxCLK rising to EMxD[y:0] tri-stated
Output hold time, EMxCLK rising to EMxD[y:0] driving
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.10.9.3.2.3 EMIF Synchronous Memory Timing Diagrams
BASIC SDRAM
1
READ OPERATION
2
2
EMxCLK
EMxCS[y:2]
EMxDQM[y:0]
EMxBA[y:0]
EMxA[y:0]
4
3
5
7
7
6
8
8
19
20
2 EM_CLK Delay
18
17
EMxD[y:0]
EMxRAS
11
12
13
14
EMxCAS
EMxWE
Figure 7-24. Basic SDRAM Read Operation
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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1
BASIC SDRAM
WRITE OPERATION
2
2
EMxCLK
3
5
7
7
4
EMxCS[y:2]
EMxDQM[y:0]
EMxBA[y:0]
EMxA[y:0]
6
8
8
9
10
EMxD[y:0]
EMxRAS
EMxCAS
EMxWE
11
12
13
15
16
Figure 7-25. Basic SDRAM Write Operation
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.11 C28x Analog Peripherals
7.11.1 Analog Subsystem
The analog modules on this device include the Analog-to-Digital Converter (ADC), Temperature Sensor, Buffered
Digital-to-Analog Converter (DAC), and Comparator Subsystem (CMPSS).
The analog subsystem has the following features:
•
Flexible voltage references
– The ADCs are referenced to VREFHIx and VREFLOx pins
•
VREFHIx pin voltage must be driven in externally
•
•
•
•
The buffered DACs are referenced to VREFHIx and VSSA
– Alternately, these DACs can be referenced to the VDAC pin and VSSA
The comparator DACs are referenced to VDDA and VSSA
– Alternately, these DACs can be referenced to the VDAC pin and VSSA
Flexible pin usage
– Buffered DAC and comparator subsystem functions multiplexed with ADC inputs
Internal connection to VREFLO on all ADCs for offset self-calibration
Figure 7-26 shows the Analog Subsystem Block Diagram for the 337-ball ZWT package.
Figure 7-27 shows the Analog Subsystem Block Diagram for the 176-pin PTP package.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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VREFHIA
VREFHIA
VDAC
Comparator Subsystem 1
Digital
DACOUTA/ADCINA0
DACOUTB/ADCINA1
CMPIN1P/ADCINA2
CMPIN1N/ADCINA3
CMPIN2P/ADCINA4
CMPIN2N/ADCINA5
0
1
2
3
4
5
6
7
8
REFHI
CMPIN1P
CTRIP1H
DACREFSEL
VDDA or VDAC
Filter
CTRIPOUT1H
12-bit
Buffered
DAC
DAC12
DAC12
ADC-A
16-bits
or
12-bits
(selectable)
CTRIP1L
Digital
Filter
CMPIN1N
CMPIN2P
CTRIPOUT1L
VREFLOA
VREFLOA
VSSA
9
10
11
12
13
14
15
Comparator Subsystem 2
Digital
VREFHIA
VDAC
CTRIP2H
VDDA or VDAC
Filter
CTRIPOUT2H
TEMP SENSOR
CMPIN4P/ADCIN14
CMPIN4N/ADCIN15
DACREFSEL
DAC12
DAC12
REFLO
REFHI
12-bit
Buffered
DAC
CTRIP2L
Digital
Filter
VREFLOA
VREFHIB
CMPIN2N
CMPIN3P
CTRIPOUT2L
VSSA
Comparator Subsystem 3
Digital
VDAC/ADCINB0
DACOUTC/ADCINB1
CMPIN3P/ADCINB2
CMPIN3N/ADCINB3
ADCINB4
0
1
2
3
4
5
6
7
8
CTRIP3H
VREFHIB VDAC
DACREFSEL
VDDA or VDAC
Filter
CTRIPOUT3H
DAC12
DAC12
ADCINB5
ADC-B
16-bits
or
12-bits
(selectable)
CTRIP3L
Digital
Filter
12-bit
Buffered
DAC
CMPIN3N
CMPIN4P
CTRIPOUT3L
VREFLOB
VREFLOB
9
10
11
12
13
14
15
Comparator Subsystem 4
Digital
VSSA
CTRIP4H
VDDA or VDAC
Filter
CTRIPOUT4H
DAC12
DAC12
REFLO
REFHI
Digital
Filter
CTRIP4L
VREFLOB
VREFHIC
CMPIN4N
CMPIN5P
CTRIPOUT4L
Comparator Subsystem 5
Digital
0
1
CTRIP5H
CMPIN6P/ADCINC2
CMPIN6N/ADCINC3
CMPIN5P/ADCINC4
CMPIN5N/ADCINC5
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VDDA or VDAC
Filter
CTRIPOUT5H
DAC12
DAC12
ADC-C
16-bits
or
12-bits
(selectable)
CTRIP5L
Digital
Filter
CTRIPOUT5L
CMPIN5N
CMPIN6P
VREFLOC
VREFLOC
Comparator Subsystem 6
Digital
CTRIP6H
VDDA or VDAC
Filter
CTRIPOUT6H
DAC12
DAC12
REFLO
REFHI
Digital
Filter
CTRIP6L
VREFLOC
VREFHID
CTRIPOUT6L
CMPIN6N
CMPIN7P
Comparator Subsystem 7
Digital
CMPIN7P/ADCIND0
CMPIN7N/ADCIND1
CMPIN8P/ADCIND2
CMPIN8N/ADCIND3
ADCIND4
0
1
2
3
4
5
6
7
8
CTRIP7H
VDDA or VDAC
Filter
CTRIPOUT7H
DAC12
DAC12
ADCIND5
ADC-D
16-bits
or
12-bits
(selectable)
CTRIP7L
Digital
Filter
CTRIPOUT7L
CMPIN7N
CMPIN8P
VREFLOD
VREFLOD
9
10
11
12
13
14
15
Comparator Subsystem 8
Digital
CTRIP8H
VDDA or VDAC
Filter
CTRIPOUT8H
DAC12
DAC12
REFLO
Digital
Filter
CTRIP8L
VREFLOD
CTRIPOUT8L
CMPIN8N
Figure 7-26. Analog Subsystem Block Diagram (337-Ball ZWT)
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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VREFHIA
VREFHIA VDAC
Comparator Subsystem 1
Digital
DACOUTA/ADCINA0
DACOUTB/ADCINA1
CMPIN1P/ADCINA2
CMPIN1N/ADCINA3
CMPIN2P/ADCINA4
CMPIN2N/ADCINA5
0
1
2
3
4
5
6
7
8
REFHI
CMPIN1P
CTRIP1H
DACREFSEL
VDDA or VDAC
Filter
CTRIPOUT1H
12-bit
Buffered
DAC
DAC12
DAC12
ADC-A
16-bits
or
12-bits
(selectable)
CTRIP1L
Digital
Filter
CMPIN1N
CMPIN2P
CTRIPOUT1L
VREFLOA
VREFLOA
VSSA
VSSA
VSSA
9
10
11
12
13
14
15
Comparator Subsystem 2
Digital
VREFHIA VDAC
DACREFSEL
CTRIP2H
VDDA or VDAC
Filter
CTRIPOUT2H
TEMP SENSOR
CMPIN4P/ADCIN14
CMPIN4N/ADCIN15
DAC12
DAC12
REFLO
REFHI
12-bit
Buffered
DAC
CTRIP2L
Digital
Filter
VREFLOA
VREFHIB
CMPIN2N
CMPIN3P
CTRIPOUT2L
Comparator Subsystem 3
Digital
VDAC/ADCINB0
DACOUTC/ADCINB1
CMPIN3P/ADCINB2
CMPIN3N/ADCINB3
0
1
2
3
4
5
6
7
8
CTRIP3H
VREFHIB VDAC
DACREFSEL
VDDA or VDAC
Filter
CTRIPOUT3H
DAC12
DAC12
ADC-B
16-bits
or
12-bits
(selectable)
12-bit
Buffered
DAC
CTRIP3L
Digital
Filter
CMPIN3N
CMPIN4P
CTRIPOUT3L
VREFLOB
VREFLOB
9
10
11
12
13
14
15
Comparator Subsystem 4
Digital
CTRIP4H
VDDA or VDAC
Filter
CTRIPOUT4H
DAC12
DAC12
REFLO
REFHI
Digital
Filter
CTRIP4L
VREFLOB
VREFHIC
CMPIN4N
CMPIN5P
CTRIPOUT4L
Comparator Subsystem 5
Digital
0
1
CTRIP5H
CMPIN6P/ADCINC2
CMPIN6N/ADCINC3
CMPIN5P/ADCINC4
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VDDA or VDAC
Filter
CTRIPOUT5H
DAC12
DAC12
ADC-C
16-bits
or
12-bits
(selectable)
CTRIP5L
Digital
Filter
CTRIPOUT5L
VREFLOC
VREFLOC
Comparator Subsystem 6
Digital
CMPIN6P
CTRIP6H
VDDA or VDAC
Filter
CTRIPOUT6H
DAC12
DAC12
REFLO
REFHI
Digital
Filter
CTRIP6L
VREFLOC
VREFHID
CTRIPOUT6L
CMPIN6N
CMPIN7P
Comparator Subsystem 7
Digital
CMPIN7P/ADCIND0
CMPIN7N/ADCIND1
CMPIN8P/ADCIND2
CMPIN8N/ADCIND3
ADCIND4
0
1
2
3
4
5
6
7
8
CTRIP7H
VDDA or VDAC
Filter
CTRIPOUT7H
DAC12
DAC12
ADC-D
16-bits
or
12-bits
(selectable)
CTRIP7L
Digital
Filter
CTRIPOUT7L
CMPIN7N
CMPIN8P
VREFLOD
VREFLOD
9
10
11
12
13
14
15
Comparator Subsystem 8
Digital
CTRIP8H
VDDA or VDAC
Filter
CTRIPOUT8H
DAC12
DAC12
REFLO
Digital
Filter
CTRIP8L
VREFLOD
CTRIPOUT8L
CMPIN8N
Figure 7-27. Analog Subsystem Block Diagram (176-Pin PTP)
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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7.11.2 Analog-to-Digital Converter (ADC)
The ADC module is a successive approximation (SAR) style ADC with a selectable resolution of either 16 bits or
12 bits. The ADC is composed of a core and a wrapper. The core is composed of the analog circuits, which
include the channel select MUX, the sample-and-hold (S/H) circuit, the successive approximation circuits,
voltage reference circuits, and other analog support circuits. The wrapper is composed of the digital circuits that
configure and control the ADC. These circuits include the logic for programmable conversions, result registers,
interfaces to analog circuits, interfaces to the peripheral buses, post-processing circuits, and interfaces to other
on-chip modules.
Each ADC module consists of a single sample-and-hold (S/H) circuit. The ADC module is designed to be
duplicated multiple times on the same chip, allowing simultaneous sampling or independent operation of multiple
ADCs. The ADC wrapper is start-of-conversion (SOC) based (see the SOC Principle of Operation section of the
Analog-to-Digital Converter (ADC) chapter in the TMS320F2838x Real-Time Microcontrollers Technical
Reference Manual).
Each ADC has the following features:
•
•
•
•
•
•
•
•
Selectable resolution of 12 bits or 16 bits
Ratiometric external reference set by VREFHI and VREFLO pins
Differential signal conversions (16-bit mode only)
Single-ended signal conversions
Input multiplexer with up to 16 channels (single-ended) or 8 channels (differential)
16 configurable SOCs
16 individually addressable result registers
Multiple trigger sources
– S/W: software immediate start
– All ePWMs: ADCSOC A or B
– GPIO Input X-BAR INPUT5
– CPU Timer 0, CPU Timer 1, CPU Timer 2 (from each C28x core present)
– ADCINT1, ADCINT2
•
•
•
•
Four flexible PIE interrupts
Configurable interrupt placement
Burst mode
Four post-processing blocks, each with:
– Saturating offset calibration
– Error from setpoint calculation
– High, low, and zero-crossing compare, with interrupt and ePWM trip capability
– Trigger-to-sample delay capture
Note
Not every channel may be pinned out from all ADCs. See Section 6 to determine which channels are
available.
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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Figure 7-28 shows the ADC module block diagram.
Analog to Digital Core
Analog to Digital Wrapper Logic
SIGNALMODE
SIGNALMODE
RESOLUTION
RESOLUTION
ADCSOC
Input Circuit
SOCx (0-15)
CHSEL
[15:0]
[15:0]
[15:0]
SOC
Arbitration
& Control
ACQPS
CHSEL
0
1
ADCIN0
ADCIN1
ADCIN2
ADCIN3
ADCIN4
ADCIN5
ADCIN6
ADCIN7
ADCIN8
ADCIN9
ADCIN10
ADCIN11
ADCIN12
ADCIN13
ADCIN14
ADCIN15
2
3
.
.
.
.
.
.
4
5
ADCCOUNTER
6
TRIGGER[15:0]
VIN+
7
DOUT
8
VIN-
9
10
11
12
13
14
15
SOC Delay
Timestamp
Trigger
Timestamp
S/H Circuit
Converter
RESULT
-
+
ADCPPBxOFFCAL
S
saturate
+
ADCPPBxOFFREF
ADCPPBxRESULT
-
S
ADCEVT
VREFHI
Event
Logic
CONFIG
ADCEVTINT
VREFLO
Reference Voltage Levels
Post Processing Block (1-4)
Interrupt Block (1-4)
ADCINT1-4
Figure 7-28. ADC Module Block Diagram
7.11.2.1 Result Register Mapping
The ADC results and the ADC PPB results are duplicated for each memory bus controller in the system. Bus
controllers include all C28x CPUs, C28x DMAs, and CLAs present on the specific part family and part number.
For each bus controller, no access configuration is needed to allow read access to the result registers and no
contention occurs in cases where multiple bus controllers try to read the ADC results simultaneously.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.11.2.2 ADC Configurability
Some ADC configurations are individually controlled by the SOCs, while others are globally controlled per ADC
module. Table 7-7 summarizes the basic ADC options and their level of configurability.
Table 7-7. ADC Options and Configuration Levels
OPTIONS
CONFIGURABILITY
Clock
Per module(1)
Per module(1)
Per module
Resolution
Signal mode
Reference voltage source
Trigger source
Not configurable (external reference only)
Per SOC(1)
Converted channel
Acquisition window duration
EOC location
Per SOC
Per SOC(1)
Per module
Per module(1)
Burst Mode
(1) Writing these values differently to different ADC modules could cause the ADCs to operate
asynchronously. For guidance on when the ADCs are operating synchronously or asynchronously,
see the Ensuring Synchronous Operation section of the Analog-to-Digital Converter (ADC) chapter
in the TMS320F2838x Real-Time Microcontrollers Technical Reference Manual.
7.11.2.2.1 Signal Mode
The ADC supports two signal modes: single-ended and differential. In single-ended mode, the input voltage to
the converter is sampled through a single pin (ADCINx), referenced to VREFLO. In differential signaling mode,
the input voltage to the converter is sampled through a pair of input pins, one of which is the positive input
(ADCINxP) and the other is the negative input (ADCINxN). The actual input voltage is the difference between the
two (ADCINxP – ADCINxN). Figure 7-29 shows the differential signaling mode. Figure 7-30 shows the single-
ended signaling mode.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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Pin Voltages
VREFHI
VREFHI
ADCINxP
VREFHI/2
ADCINxN
ADCINxP
ADCINxN
ADC
VREFLO
VREFLO
(VSSA)
Input Common Mode
VREFHI
Vin Common Mode
VREFHI/2 50mV
VREFLO
(VSSA)
Effective Input Voltage
+VREFHI
ADC Vin
0
-VREFHI
Digital Output
2n - 1
ADC Vin
0
Figure 7-29. Differential Signaling Mode
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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Pin Voltage
VREFHI
VREFHI
ADCINx
ADCINx
ADC
VREFHI/2
VREFLO
VREFLO
(VSSA)
Digital Output
2n - 1
ADC Vin
0
Figure 7-30. Single-ended Signaling Mode
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.11.2.3 ADC Electrical Data and Timing
Section 7.11.2.3.1 lists the ADC operating conditions for the 16-bit differential mode. Section 7.11.2.3.2 lists the
ADC characteristics for the 16-bit differential mode. Section 7.11.2.3.3 lists the ADC operating conditions for the
16-bit single-ended mode. Section 7.11.2.3.4 lists the ADC characteristics for the 16-bit single-ended mode.
Section 7.11.2.3.5 lists the ADC operating conditions for the 12-bit single-ended mode. Section 7.11.2.3.6 lists
the ADC characteristics for the 12-bit single-ended mode. Section 7.11.2.3.7 lists the ADCEXTSOC timing
requirements.
7.11.2.3.1 ADC Operating Conditions (16-bit Differential)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
ADCCLK (derived from PERx.SYSCLK)
Sample rate
TEST CONDITIONS
MIN
TYP
MAX UNIT
50 MHz
5
200-MHz SYSCLK
With 50 Ω or less Rs
1.1 MSPS
Sample window duration (set by ACQPS and
PERx.SYSCLK)(1)
320
ns
VREFHI
2.4 2.5 or 3.0
VSSA VSSA
VREFLO
VDDA
VSSA
V
V
V
VREFLO
Conversion range
VREFHI
ADC input signal common mode voltage(2) (3)
VREFCM – 50 VREFCM VREFCM + 50 mV
(1) The sample window must also be at least as long as 1 ADCCLK cycle for correct ADC operation.
(2) VREFCM = (VREFHI + VREFLO)/2
(3) The VREFCM requirements will not be met if the negative ADC input pin is connected to VSSA or VREFLO.
7.11.2.3.1.1 ADC Operating Conditions (16-bit Differential) Notes
Note
The ADC inputs should be kept below VDDA + 0.3 V during operation. If an ADC input exceeds this
level, the VREF internal to the device may be disturbed, which can impact results for other ADC or
DAC inputs using the same VREF.
Note
The VREFHI pin must be kept below VDDA for the ADC and DAC to meet specified performance
parameters. The VREFHI pin must be kept below VDDA + 0.3 V for functional operation. If the
VREFHI pin exceeds VDDA + 0.3 V, a blocking circuit may activate, causing the interval value of
VREFHI to float to 0 V internally, giving improper ADC conversion or DAC output.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.11.2.3.2 ADC Characteristics (16-bit Differential)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
General
ADCCLK Conversion Cycles
29.6
31 ADCCLKs
Power Up Time
500
µs
VREFHI input current (1)
190
µA
External Reference Capacitor
Value(2)
22
µF
DC Characteristics
Gain Error
–64
–6
±9
±4
64
6
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
Offset Error
Channel-to-Channel Gain Error
Channel-to-Channel Offset Error
ADC-to-ADC Gain Error
ADC-to-ADC Offset Error
DNL Error
±6
±3
Identical VREFHI and VREFLO for all ADCs
Identical VREFHI and VREFLO for all ADCs
±6
±3
>–1
–3.5
–2
±0.5
±1.0
1
3.5
2
INL Error
VREFHI = 2.5 V, synchronous ADCs
VREFHI = 2.5 V, asynchronous ADCs
ADC-to-ADC Isolation
LSBs
Not Supported
AC Characteristics
VREFHI = 2.5 V, fin = 10 kHz, SYSCLK from X1
90.2
90.2
dB
dB
SNR(3)
VREFHI = 2.5 V, fin = 10 kHz, SYSCLK from
INTOSC
THD(3)
VREFHI = 2.5 V, fin = 10 kHz
–105
106
dB
dB
SFDR(3)
VREFHI = 2.5 V, fin = 10 kHz
VREFHI = 2.5 V, fin = 10 kHz, SYSCLK from X1
90.0
SINAD(3)
dB
VREFHI = 2.5 V, fin = 10 kHz, SYSCLK from
INTOSC
90.0
14.65
14.65
VREFHI = 2.5 V, fin = 10 kHz, SYSCLK from
X1, Single ADC
VREFHI = 2.5 V, fin = 10 kHz, SYSCLK from
X1, synchronous ADCs
ENOB(3)
bits
VREFHI = 2.5 V, fin = 10 kHz, SYSCLK from
X1, asynchronous ADCs
Not
Supported
VDD = 1.2-V DC + 200mV
DC up to Sine at 1 kHz
77
74
77
74
VDD = 1.2-V DC + 200 mV
Sine at 800 kHz
PSRR
dB
VDDA = 3.3-V DC + 200 mV
DC up to Sine at 800 kHz
VDDA = 3.3-V DC + 200 mV
Sine at 800 kHz
(1) Load current on VREFHI increases when ADC input is greater than VDDA. This causes inaccurate conversions.
(2) A ceramic capacitor with package size of 0805 or smaller is preferred. Up to ±20% tolerance is acceptable.
(3) IO activity is minimized on pins adjacent to ADC input and VREFHI pins as part of best practices to reduce capacitive coupling and
crosstalk
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.11.2.3.3 ADC Operating Conditions (16-bit Single-Ended)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
ADCCLK (derived from PERx.SYSCLK)
Sample rate
TEST CONDITIONS
MIN
TYP
MAX UNIT
50 MHz
5
200-MHz SYSCLK
With 50 Ω or less Rs
1.1 MSPS
Sample window duration (set by ACQPS and
PERx.SYSCLK)(1)
320
ns
VREFHI
2.4
VSSA
2.5 or 3.0
VSSA
VDDA
VSSA
V
V
V
VREFLO
Conversion range
External reference
VREFLO
VREFHI
(1) The sample window must also be at least as long as 1 ADCCLK cycle for correct ADC operation.
7.11.2.3.3.1 ADC Operating Conditions (16-bit Single-Ended) Notes
Note
The ADC inputs should be kept below VDDA + 0.3 V during operation. If an ADC input exceeds this
level, the VREF internal to the device may be disturbed, which can impact results for other ADC or
DAC inputs using the same VREF.
Note
The VREFHI pin must be kept below VDDA for the ADC and DAC to meet specified performance
parameters. The VREFHI pin must be kept below VDDA + 0.3 V for functional operation. If the
VREFHI pin exceeds VDDA + 0.3 V, a blocking circuit may activate, causing the interval value of
VREFHI to float to 0 V internally, giving improper ADC conversion or DAC output.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.11.2.3.4 ADC Characteristics (16-bit Single-Ended)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
General
ADCCLK Conversion Cycles
29.6
31 ADCCLKs
Power Up Time
500
µs
VREFHI input current(1)
190
µA
External Reference Capacitor
Value(2)
22
µF
DC Characteristics
Gain Error
–64
–6
±20
±4
64
6
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
Offset Error
Channel-to-Channel Gain Error
Channel-to-Channel Offset Error
ADC-to-ADC Gain Error
ADC-to-ADC Offset Error
DNL Error
±6
±6
Identical VREFHI and VREFLO for all ADCs
Identical VREFHI and VREFLO for all ADCs
±6
±6
>–1
–6
±0.5
±1.5
1
6
2
INL Error
VREFHI = 2.5 V, synchronous ADCs
VREFHI = 2.5 V, asynchronous ADCs
–2
ADC-to-ADC Isolation
LSBs
Not Supported
AC Characteristics
VREFHI = 2.5 V, fin = 10 kHz, SYSCLK from X1 via
PLL
83.5
83.5
-94
dB
dB
dB
dB
SNR(3)
VREFHI = 2.5 V, fin = 10 kHz, SYSCLK from
INTOSC via PLL
VREFHI = 2.5 V, fin = 10 kHz, SYSCLK from X1 via
PLL
THD(3)
VREFHI = 2.5 V, fin = 10 kHz SYSCLK from X1 via
PLL
SFDR(3)
93
VREFHI = 2.5 V, fin = 10 kHz, SYSCLK from X1 via
PLL
83.4
83.4
13.5
13.5
SINAD(3)
dB
VREFHI = 2.5 V, fin = 10 kHz, SYSCLK from
INTOSC via PLL
VREFHI = 2.5 V, fin = 10 kHz, SYSCLK from
X1, Single ADC
VREFHI = 2.5 V, fin = 10 kHz, SYSCLK from
X1, synchronous ADCs
ENOB(3)
bits
VREFHI = 2.5 V, fin = 10 kHz, SYSCLK from
X1, asynchronous ADCs
Not
Supported
VDD = 1.2-V DC + 200mV
DC up to Sine at 1 kHz
77
74
77
74
Sine at 800 kHz
PSRR
dB
VDDA = 3.3-V DC + 200 mV
DC up to Sine at 1 kHz
Sine at 800 kHz
(1) Load current on VREFHI increases when ADC input is greater than VDDA. This causes inaccurate conversions.
(2) A ceramic capacitor with package size of 0805 or smaller is preferred. Up to ±20% tolerance is acceptable.
(3) IO activity is minimized on pins adjacent to ADC input and VREFHI pins as part of best practices to reduce capacitive coupling and
crosstalk
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.11.2.3.5 ADC Operating Conditions (12-bit Single-Ended)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
ADCCLK (derived from PERx.SYSCLK)
Sample rate
TEST CONDITIONS
MIN
TYP
MAX UNIT
50 MHz
5
200-MHz SYSCLK
With 50 Ω or less Rs
3.45 MSPS
Sample window duration (set by ACQPS and
PERx.SYSCLK)(1)
75
ns
VREFHI
2.4
VSSA
2.5 or 3.0
VSSA
VDDA
VSSA
V
V
V
VREFLO
Conversion range
External reference
VREFLO
VREFHI
(1) The sample window must also be at least as long as 1 ADCCLK cycle for correct ADC operation.
7.11.2.3.5.1 ADC Operating Conditions (12-bit Single-Ended) Notes
Note
The ADC inputs should be kept below VDDA + 0.3 V during operation. If an ADC input exceeds this
level, the VREF internal to the device may be disturbed, which can impact results for other ADC or
DAC inputs using the same VREF.
Note
The VREFHI pin must be kept below VDDA for the ADC and DAC to meet specified performance
parameters. The VREFHI pin must be kept below VDDA + 0.3 V for functional operation. If the
VREFHI pin exceeds VDDA + 0.3 V, a blocking circuit may activate, causing the interval value of
VREFHI to float to 0 V internally, giving improper ADC conversion or DAC output.
7.11.2.3.6 ADC Characteristics (12-bit Single-Ended)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
General
ADCCLK Conversion Cycles
10.1
11 ADCCLKs
Power Up Time
500
µs
VREFHI input current(1)
130
µA
External Reference Capacitor
Value(2)
2.2
µF
DC Characteristics
Gain Error
–5
–4
±3
±2
5
4
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSBs
Offset Error
Channel-to-Channel Gain Error
Channel-to-Channel Offset Error
ADC-to-ADC Gain Error
ADC-to-ADC Offset Error
DNL Error
±4
±2
Identical VREFHI and VREFLO for all ADCs
Identical VREFHI and VREFLO for all ADCs
±4
±2
>–1
–2
±0.5
±1.0
1
2
1
INL Error
ADC-to-ADC Isolation
VREFHI = 2.5 V, synchronous ADCs
–1
VREFHI = 2.5 V, asynchronous ADCs, 337-ball
ZWT package
ADC-to-ADC Isolation
ADC-to-ADC Isolation
-2
-9
2
9
LSBs
LSBs
VREFHI = 2.5 V, asynchronous ADCs, 176-pin
PTP package
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.11.2.3.6 ADC Characteristics (12-bit Single-Ended) (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC Characteristics
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from X1
via PLL
69.1
69.1
–88
89
dB
dB
dB
dB
SNR(3)
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from
INTOSC via PLL
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from X1
via PLL
THD(3)
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from X1
via PLL
SFDR(3)
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from X1
via PLL
69.0
69.0
11.2
11.2
10.9
9.7
SINAD(3)
ENOB(3)
dB
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from
INTOSC via PLL
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from
X1, Single ADC
bits
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from
X1, synchronous ADCs
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from
X1, asynchronous ADCs, 337-ball ZWT package
ENOB(3)
ENOB(3)
bits
bits
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from
X1, asynchronous ADCs, 176-pin PTP package
VDD = 1.2-V DC + 100mV
DC up to Sine at 1 kHz
60
VDD = 1.2-V DC + 100 mV
Sine at 800 kHz
57
PSRR
dB
VDDA = 3.3-V DC + 200 mV
DC up to Sine at 1 kHz
60
VDDA = 3.3-V DC + 200 mV
Sine at 800 kHz
57
(1) Load current on VREFHI increases when ADC input is greater than VDDA. This causes inaccurate conversions.
(2) A ceramic capacitor with package size of 0805 or smaller is preferred. Up to ±20% tolerance is acceptable.
(3) IO activity is minimized on pins adjacent to ADC input and VREFHI pins as part of best practices to reduce capacitive coupling and
crosstalk
7.11.2.3.7 ADCEXTSOC Timing Requirements
MIN
2tc(SYSCLK)
MAX
UNIT
cycles
cycles
Synchronous
tw(INT)
Pulse duration, INT input low/high
With qualifier(1)
tw(IQSW) + tw(SP) + 1tc(SYSCLK)
(1) For an explanation of the input qualifier parameters, see Section 7.10.6.2.1.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.11.2.3.8 ADC Input Models
Note
ADC channels ADCINA0, ADCINA1, and ADCINB1 have a 50-kΩ pulldown resistor to VSSA.
For single-ended operation, the ADC input characteristics are given by Section 7.11.2.3.8.1, Section
7.11.2.3.8.2, and Figure 7-31.
7.11.2.3.8.1 Single-Ended Input Model Parameters (12-bit Resolution)
DESCRIPTION
Parasitic input capacitance
VALUE
See Table 7-8
425 Ω
Cp
Ron
Ch
Rs
Sampling switch resistance
Sampling capacitor
14.5 pF
Nominal source impedance
50 Ω
7.11.2.3.8.2 Single-Ended Input Model Parameters (16-bit Resolution)
DESCRIPTION
VALUE
See Table 7-8
425 Ω
Cp
Ron
Ch
Rs
Parasitic input capacitance
Sampling switch resistance
Sampling capacitor
32.5 pF
Nominal source impedance
50 Ω
7.11.2.3.8.3 Single-Ended Input Model
ADC
ADCINx
Rs
Switch
Ron
AC
Cp
Ch
VREFLO
Figure 7-31. Single-Ended Input Model
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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For differential operation, the ADC input characteristics are given by Section 7.11.2.3.8.4 and Figure 7-32.
7.11.2.3.8.4 Differential Input Model Parameters (16-bit Resolution)
DESCRIPTION
Parasitic input capacitance
VALUE
See Table 7-8
700 Ω
Cp
Ron
Ch
Rs
Sampling switch resistance
Sampling capacitor
16.5 pF
Nominal source impedance
50 Ω
7.11.2.3.8.5 Differential Input Model
ADC
ADCINxP
ADCINxN
Rs
Cp
Cp
Ron
Switch
Switch
AC
Ch
VSSA
Ron
Rs
Figure 7-32. Differential Input Model
Table 7-8 lists the parasitic capacitance on each channel. Also, enabling a comparator adds approximately
1.4 pF of capacitance on positive comparator inputs and 2.5 pF of capacitance on negative comparator inputs.
Table 7-8. Per-Channel Parasitic Capacitance
Cp (pF)
ADC CHANNEL
COMPARATOR DISABLED
COMPARATOR ENABLED
ADCINA0
ADCINA1
ADCINA2
ADCINA3
ADCINA4
ADCINA5
ADCINB0(1)
ADCINB1
ADCINB2
ADCINB3
ADCINB4
ADCINB5
ADCINC2
ADCINC3
ADCINC4
ADCINC5
ADCIND0
ADCIND1
ADCIND2
ADCIND3
ADCIND4
ADCIND5
ADCIN14
ADCIN15
12.9
10.3
5.9
6.3
5.9
6.3
117.0
10.6
5.9
6.2
5.2
5.1
5.5
5.8
5.0
5.3
5.3
5.7
5.3
5.6
4.3
4.3
8.6
9.0
N/A
N/A
7.3
8.8
7.3
8.8
N/A
N/A
7.3
8.7
N/A
N/A
6.9
8.3
6.4
7.8
6.7
8.2
6.7
8.1
N/A
N/A
10.0
11.5
(1) The increased capacitance is due to VDAC functionality.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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These input models should be used along with actual signal source impedance to determine the acquisition
window duration. See the Choosing an Acquisition Window Duration section of the TMS320F2838x Real-Time
Microcontrollers Technical Reference Manual for more information.
The user should analyze the ADC input setting assuming worst-case initial conditions on Ch. This will require
assuming that Ch could start the S+H window completely charged to VREFHI or completely discharged to
VREFLO. When the ADC transitions from an odd-numbered channel to an even-numbered channel, or vice-
versa, the actual initial voltage on Ch will be close to being completely discharged to VREFLO. For even-to-even
or odd-to-odd channel transitions, the initial voltage on Ch will be close to the voltage of the previously converted
channel.
7.11.2.3.9 ADC Timing Diagrams
Section 7.11.2.3.9.1 lists the ADC timings in 12-bit mode (SYSCLK cycles). Section 7.11.2.3.9.2 lists the ADC
timings in 16-bit mode. Figure 7-33 and Figure 7-34 show the ADC conversion timings for two SOCs given the
following assumptions:
•
•
•
•
SOC0 and SOC1 are configured to use the same trigger.
No other SOCs are converting or pending when the trigger occurs.
The round robin pointer is in a state that causes SOC0 to convert first.
ADCINTSEL is configured to set an ADCINT flag upon end of conversion for SOC0 (whether this flag
propagates through to the CPU to cause an interrupt is determined by the configurations in the PIE module).
Table 7-9 lists the descriptions of the ADC timing parameters that are in Figure 7-33 and Figure 7-34.
Table 7-9. ADC Timing Parameters
PARAMETER
DESCRIPTION
The duration of the S+H window.
At the end of this window, the value on the S+H capacitor becomes the voltage to be converted into a digital
value. The duration is given by (ACQPS + 1) SYSCLK cycles. ACQPS can be configured individually for each
SOC, so tSH will not necessarily be the same for different SOCs.
tSH
Note: The value on the S+H capacitor will be captured approximately 5 ns before the end of the S+H window
regardless of device clock settings.
The time from the end of the S+H window until the ADC conversion results latch in the ADCRESULTx register.
tLAT
If the ADCRESULTx register is read before this time, the previous conversion results will be returned.
The time from the end of the S+H window until the next ADC conversion S+H window can begin. The
subsequent sample can start before the conversion results are latched.
tEOC
The time from the end of the S+H window until an ADCINT flag is set (if configured).
If the INTPULSEPOS bit in the ADCCTL1 register is set, tINT will coincide with the conversion results being
latched into the result register.
tINT
If the INTPULSEPOS bit is 0, tINT will coincide with the end of the S+H window. If tINT triggers a read of the
ADC result register (directly through DMA or indirectly by triggering an ISR that reads the result), care must be
taken to ensure the read occurs after the results latch (otherwise, the previous results will be read).
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.11.2.3.9.1 ADC Timings in 12-Bit Mode (SYSCLK Cycles)
ADCCLK
CYCLES
ADCCLK PRESCALE
SYSCLK CYCLES
ADCCTL2
[PRESCALE]
RATIO
ADCCLK:SYSCLK
(1)
tEOC
tLAT
tINT(EARLY)
tINT(LATE)
tEOC
0
1
1
1.5
2
11
13
1
11
11.0
Invalid
2
21
26
31
36
41
46
51
56
61
66
71
76
81
86
23
28
34
39
44
49
55
60
65
70
76
81
86
91
1
1
1
1
1
1
1
1
1
1
1
1
1
1
21
26
31
36
41
46
51
56
61
66
71
76
81
86
10.5
10.4
10.3
10.3
10.3
10.2
10.2
10.2
10.2
10.2
10.1
10.1
10.1
10.1
3
2.5
3
4
5
3.5
4
6
7
4.5
5
8
9
5.5
6
10
11
12
13
14
15
6.5
7
7.5
8
8.5
(1) Refer to the "ADC: DMA Read of Stale Result" advisory in the TMS320F2838x Real-Time MCUs Silicon Errata.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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Sample n
Input on SOC0.CHSEL
Input on SOC1.CHSEL
Sample n+1
SOC0
SOC1
ADC S+H
SYSCLK
ADCCLK
ADCTRIG
ADCSOCFLG.SOC0
ADCSOCFLG.SOC1
ADCRESULT0
ADCRESULT1
ADCINTFLG.ADCINTx
Sample n
(old data)
(old data)
Sample n+1
tSH
tLAT
tEOC
tINT
Figure 7-33. ADC Timings for 12-Bit Mode
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.11.2.3.9.2 ADC Timings in 16-Bit Mode
ADCCLK
ADCCLK PRESCALE
SYSCLK CYCLES
CYCLES
ADCCTL2
[PRESCALE]
RATIO
ADCCLK:SYSCLK
(1)
tEOC
tLAT
32
tINT(EARLY)
tINT(LATE)
tEOC
0
1
1
1.5
2
31
1
31
31.0
Invalid
2
60
61
1
1
1
1
1
1
1
1
1
1
1
1
1
1
60
30.0
30.0
30.0
29.7
29.8
29.8
29.8
29.6
29.7
29.7
29.7
29.6
29.6
29.6
3
2.5
3
75
75
75
4
90
91
90
5
3.5
4
104
119
134
149
163
178
193
208
222
237
252
106
120
134
150
165
179
193
209
224
238
252
104
119
134
149
163
178
193
208
222
237
252
6
7
4.5
5
8
9
5.5
6
10
11
12
13
14
15
6.5
7
7.5
8
8.5
(1) Refer to the "ADC: DMA Read of Stale Result" advisory in the TMS320F2838x Real-Time MCUs Silicon Errata.
Sample n
Input on SOC0.CHSEL
Input on SOC1.CHSEL
Sample n+1
SOC0
SOC1
ADC S+H
SYSCLK
ADCCLK
ADCTRIG
ADCSOCFLG.SOC0
ADCSOCFLG.SOC1
ADCRESULT0
ADCRESULT1
ADCINTFLG.ADCINTx
Sample n
(old data)
(old data)
Sample n+1
tSH
tLAT
tEOC
tINT
Figure 7-34. ADC Timings for 16-Bit Mode
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.11.2.4 Temperature Sensor Electrical Data and Timing
The temperature sensor can be used to measure the device junction temperature. The temperature sensor is
sampled through an internal connection to the ADC and translated into a temperature through TI-provided
software. When sampling the temperature sensor, the ADC must meet the acquisition time listed in Section
7.11.2.4.1.
7.11.2.4.1 Temperature Sensor Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Tacc
tstartup
tacq
Temperature Accuracy
External reference
±15
°C
Start-up time
(TSNSCTL[ENABLE] to
sampling temperature sensor)
500
µs
ns
ADC acquisition time
700
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.11.3 Comparator Subsystem (CMPSS)
The comparator subsystem is built around a number of modules. Each subsystem contains two comparators,
two reference 12-bit DACs, two digital filters, and one ramp generator. Comparators are denoted "H" or "L" within
each module, where “H” and “L” represent high and low, respectively. Each comparator generates a digital
output which indicates whether the voltage on the positive input is greater than the voltage on the negative input.
The positive input of the comparator is driven from an external pin. The negative input can be driven by an
external pin or by the programmable reference 12-bit DAC. Each comparator output passes through a
programmable digital filter that can remove spurious trip signals. An unfiltered output is also available if filtering
is not required. A ramp generator circuit is optionally available to control the reference 12-bit DAC value for the
high comparator in the subsystem.
Each CMPSS includes:
•
•
•
•
•
•
•
•
•
•
•
•
Two analog comparators
Two programmable reference 12-bit DACs
One ramp generator
Two digital filters
Ability to synchronize submodules with EPWMSYNCPER
Ability to extend clear signal with EPWMBLANK
Ability to synchronize output with SYSCLK
Ability to latch output
Ability to invert output
Option to use hysteresis on the input
Option for negative input of comparator to be driven by an external signal or by the reference DAC
Option to choose between VDDA or VDAC to be the DAC reference voltage
The block diagram for the CMPSS is shown in Figure 7-35.
•
CTRIPx (x= "H" or "L") signals are connected to the ePWM X-BAR for ePWM trip response. For more details
on the ePWM X-BAR mux configuration, see the Enhanced Pulse Width Modulator (ePWM) chapter of the
TMS320F2838x Real-Time Microcontrollers Technical Reference Manual.
•
CTRIPxOUTx (x= "H" or "L") signals are connected to the Output X-BAR for external signaling. For more
details on the Output X-BAR mux configuration, see the General-Purpose Input/Output (GPIO) chapter of the
TMS320F2838x Real-Time Microcontrollers Technical Reference Manual.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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Figure 7-35. CMPSS Module Block Diagram
Figure 7-36 shows the CMPSS connectivity on the 337-ball ZWT and 176-pin PTP packages.
Comparator Subsystem 1
CMPIN1P Pin
CTRIP1H
Digital
Filter
CTRIPOUT1H
VDDA or VDAC
CTRIP1H
CTRIP1L
CTRIP2H
CTRIP2L
DAC12
DAC12
CTRIP1L
Digital
Filter
CTRIPOUT1L
ePWMs
ePWM X-BAR
CMPIN1N Pin
CMPIN2P Pin
CTRIP8H
CTRIP8L
Comparator Subsystem 2
Digital
CTRIP2H
CTRIPOUT2H
VDDA or VDAC
Filter
DAC12
DAC12
CTRIP2L
Digital
Filter
CTRIPOUT2L
CMPIN2N Pin
CTRIPOUT1H
CTRIPOUT1L
CTRIPOUT2H
CTRIPOUT2L
Comparator Subsystem 8
Digital
CMPIN8P Pin
CTRIP8H
Output X-BAR
GPIO Mux
CTRIPOUT8H
VDDA or VDAC
Filter
CTRIPOUT8H
CTRIPOUT8L
DAC12
DAC12
CTRIP8L
Digital
Filter
CTRIPOUT8L
CMPIN8N Pin
Figure 7-36. CMPSS Connectivity (337-Ball ZWT and 176-Pin PTP)
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.11.3.1 CMPSS Electrical Data and Timing
Section 7.11.3.1.1 lists the comparator electrical characteristics. Figure 7-37 shows the CMPSS comparator
input referred offset. Figure 7-38 shows the CMPSS comparator hysteresis.
7.11.3.1.1 Comparator Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TPU
Power-up time
500
µs
Comparator input (CMPINxx)
range
0
VDDA
20
V
Low common mode, inverting
input set to 50 mV
Input referred offset error
–20
mV
1x
12
24
36
48
21
26
30
46
2x
Hysteresis(1)
LSB
3x
4x
Response time (delay from
CMPINx input change to output
on ePWM X-BAR or Output X-
BAR)
Step response
60
ns
Ramp response (1.65 V/µs)
Ramp response (8.25 mV/µs)
Up to 250 kHz
ns
dB
dB
PSRR
CMRR
Power Supply Rejection Ratio
Common Mode Rejection Ratio
40
(1) The CMPSS DAC is used as the reference to determine how much hysteresis to apply. Therefore, hysteresis will scale with the
CMPSS DAC reference voltage. Hysteresis is available for all comparator input source configurations.
7.11.3.1.2 CMPSS Comparator Input Referred Offset and Hysteresis
Note
The CMPSS inputs must be kept below VDDA + 0.3 V to ensure proper functional operation. If a
CMPSS input exceeds this level, an internal blocking circuit will isolate the internal comparator from
the external pin until the external pin voltage returns below VDDA + 0.3 V. During this time, the
internal comparator input will be floating and can decay below VDDA within approximately 0.5 µs.
After this time, the comparator could begin to output an incorrect result depending on the value of the
other comparator input.
Input Referred Offset
CTRIPx
Logic Level
CTRIPx = 1
CTRIPx = 0
COMPINxP
Voltage
0
CMPINxN or
DACxVAL
Figure 7-37. CMPSS Comparator Input Referred Offset
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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Hysteresis
CTRIPx
Logic Level
CTRIPx = 1
CTRIPx = 0
COMPINxP
Voltage
0
CMPINxN or
DACxVAL
Figure 7-38. CMPSS Comparator Hysteresis
Section 7.11.3.1.3 lists the CMPSS DAC static electrical characteristics.
7.11.3.1.3 CMPSS DAC Static Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
0
TYP
MAX
UNIT
Internal reference
VDDA
CMPSS DAC output range
V
External reference
0
VDAC(4)
Static offset error(1)
Static gain error(1)
Static DNL
–25
–2
25
2
mV
% of FSR
LSB
Endpoint corrected
>–1
–16
4
Static INL
Endpoint corrected
16
1
LSB
Settling time
Resolution
Settling to 1LSB after full-scale output change
µs
12
bits
Error induced by comparator trip or CMPSS
DAC code change within the same CMPSS
module
CMPSS DAC output disturbance(2)
–100
2.4
100
LSB
CMPSS DAC disturbance time(2)
VDAC reference voltage
VDAC load(3)
200
2.5 or 3.0
6
ns
V
When VDAC is reference
When VDAC is reference
VDDA
kΩ
(1) Includes comparator input referred errors.
(2) Disturbance error may be present on the CMPSS DAC output for a certain amount of time after a comparator trip.
(3) Per active CMPSS module.
(4) The maximum output voltage is VDDA when VDAC > VDDA.
7.11.3.1.4 CMPSS Illustrative Graphs
Note
The VDAC pin must be kept below VDDA for the DAC and CMPSS to meet specified performance
parameters. The VDAC pin must be kept below VDDA + 0.3 V for functional operation. If the VDAC
pin exceeds VDDA + 0.3 V, a blocking circuit may activate, causing the interval value of VDAC to float
to 0 V internally, giving improper DAC output or CMPSS trips.
Figure 7-39 shows the CMPSS DAC static offset. Figure 7-40 shows the CMPSS DAC static gain. Figure 7-41
shows the CMPSS DAC static linearity.
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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Offset Error
Figure 7-39. CMPSS DAC Static Offset
Ideal Gain
Actual Gain
Figure 7-40. CMPSS DAC Static Gain
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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Linearity Error
Figure 7-41. CMPSS DAC Static Linearity
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.11.4 Buffered Digital-to-Analog Converter (DAC)
The buffered DAC module consists of an internal 12-bit DAC and an analog output buffer that is capable of
driving an external load. An integrated pulldown resistor on the DAC output helps to provide a known pin voltage
when the output buffer is disabled. This pulldown resistor cannot be disabled and remains as a passive
component on the pin, even for other shared pinmux functions. The buffered DAC is a general-purpose DAC that
can be used to generate a DC voltage in addition to AC waveforms such as sine waves, square waves, triangle
waves, and so forth. Software writes to the DAC value register can take effect immediately or can be
synchronized with EPWMSYNCPER events.
Each buffered DAC has the following features:
•
•
•
•
12-bit programmable internal DAC
Selectable reference voltage source
Pulldown resistor on output
Ability to synchronize with EPWMSYNCPER
The block diagram for the buffered DAC is shown in Figure 7-42.
DACCTL[DACREFSEL]
VDAC
0
1
DACREF
VREFHI
VDDA
DACCTL[LOADMODE]
SYSCLK
>
Q
Q
0
1
DACVALS
D
12-bit
DAC
DACOUT
DACVALA
Buffer
D
RPD
EPWM1SYNCPER
EPWM2SYNCPER
EPWM3SYNCPER
0
1
2
EN
VSSA
VSSA
...
EPWMnSYNCPER
Y
n-1
DACCTL[SYNCSEL]
Figure 7-42. DAC Module Block Diagram
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.11.4.1 Buffered DAC Electrical Data and Timing
Section 7.11.4.1.1 lists the buffered DAC operating conditions. Section 7.11.4.1.2 lists the buffered DAC
electrical characteristics. Figure 7-43 shows the buffered DAC offset. Figure 7-44 shows the buffered DAC gain.
Figure 7-45 shows the buffered DAC linearity.
7.11.4.1.1 Buffered DAC Operating Conditions
over recommended operating conditions (unless otherwise noted)
PARAMETER
Resistive Load
Capacitive Load
TEST CONDITIONS
MIN(1)
TYP(1)
MAX(1)
UNIT
kΩ
pF
V
RL
5
CL
100
VDDA – 0.3
VDDA
VOUT
Valid Output Voltage Range(2) RL = 5 kΩ
Reference Voltage(3)
VDAC or VREFHI
0.3
2.4
2.5 or 3.0
V
(1) Typical values are measured with VREFHI = 3.3 V unless otherwise noted. Minimum and maximum values are tested or characterized
with VREFHI = 2.5 V.
(2) This is the linear output range of the DAC. The DAC can generate voltages outside this range, but the output voltage will not be linear
due to the buffer.
(3) For best PSRR performance, VDAC or VREFHI should be less than VDDA.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.11.4.1.2 Buffered DAC Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN(1)
TYP(1)
MAX(1)
UNIT
General
Resolution
12
50
bits
kΩ
RPD
Pulldown Resistor
Load Regulation
Glitch Energy
–1
1
mV/V
V-ns
1.5
2
Voltage Output Settling Time Settling to 2 LSBs after 0.3V-
Full-Scale to-3V transition
µs
µs
Voltage Output Settling Time Settling to 2 LSBs after 0.3V-
1.6
1/4th Full-Scale
to-0.75V transition
Slew rate from 0.3V-to-3V
transition
Voltage Output Slew Rate
2.8
4.5
V/µs
ns
Load Transient Settling
Time(6)
5-kΩ Load
328
Reference Input Resistance(2) VDAC or VREFHI
170
kΩ
µs
TPU
Power-up Time External Reference mode
500
DC Characteristics
Offset
Gain
DNL
INL
Offset Error
Midpoint
–10
–2.5
> –1
–5
10
2.5
1
mV
% of FSR
LSB
Gain Error(3)
Differential Non Linearity(4)
Endpoint corrected
Endpoint corrected
±0.4
±2
Integral Non Linearity
5
LSB
AC Characteristics
Integrated noise from 100 Hz
to 100 kHz
500
µVrms
Output Noise
Noise density at 10 kHz
1020 Hz, 1 MSPS
711
67
nVrms/√Hz
SNR
THD
Signal to Noise Ratio
dB
dB
Total Harmonic Distortion
1020 Hz, 1 MSPS
–63
1020 Hz, 1 MSPS (including
harmonics and spurs)
66
Spurious Free Dynamic
Range
SFDR
PSRR
dBc
dB
1020 Hz, 1 MSPS (including
only spurs)
104
DC
70
30
Power Supply Rejection
Ratio(5)
100 kHz
(1) Typical values are measured with VREFHI = 3.3 V unless otherwise noted. Minimum and maximum values are tested or characterized
with VREFHI = 2.5 V.
(2) Per active Buffered DAC module.
(3) Gain error is calculated for linear output range.
(4) The DAC output is monotonic.
(5) VREFHI = 3.2 V, VDDA = 3.3 V DC + 100 mV Sine.
(6) Settling to within 3LSBs.
7.11.4.1.3 Buffered DAC Notes and Illustrative Graphs
Note
The VDAC pin must be kept below VDDA for the DAC and CMPSS to meet specified performance
parameters. The VDAC pin must be kept below VDDA + 0.3 V for functional operation. If the VDAC
pin exceeds VDDA + 0.3 V, a blocking circuit may activate, causing the interval value of VDAC to float
to 0 V internally, giving improper DAC output or CMPSS trips.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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Note
The VREFHI pin must be kept below VDDA for the ADC and DAC to meet specified performance
parameters. The VREFHI pin must be kept below VDDA + 0.3 V for functional operation. If the
VREFHI pin exceeds VDDA + 0.3 V, a blocking circuit may activate, causing the interval value of
VREFHI to float to 0 V internally, giving improper ADC conversion or DAC output.
Offset Error
Code 2048
Figure 7-43. Buffered DAC Offset
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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Actual Gain
Ideal Gain
Code 3722
Code 373
Linear Range
(3.3-V Reference)
Figure 7-44. Buffered DAC Gain
Linearity Error
Code 3722
Code 373
Linear Range
(3.3-V Reference)
Figure 7-45. Buffered DAC Linearity
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.12 C28x Control Peripherals
Note
For the actual number of each peripheral on a specific device, see the Device Comparison table.
7.12.1 Enhanced Capture and High-Resolution Capture (eCAP, HRCAP)
The eCAP module can be used in systems where accurate timing of external events is important.
Applications for eCAP include:
•
•
•
•
Speed measurements of rotating machinery (for example, toothed sprockets sensed through Hall sensors)
Elapsed time measurements between position sensor pulses
Period and duty cycle measurements of pulse train signals
Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors
The eCAP module includes the following features:
•
•
•
•
•
•
•
•
•
4-event time-stamp registers (each 32 bits)
Edge-polarity selection for up to four sequenced time-stamp capture events
Interrupt on either of the four events
Single shot capture of up to four event timestamps
Continuous mode capture of timestamps in a four-deep circular buffer
Absolute time-stamp capture
Difference (Delta) mode time-stamp capture
All of the above resources dedicated to a single input pin
When not used in capture mode, the eCAP module can be configured as a single-channel PWM output
(APWM).
The capture functionality of the Type-2 eCAP is enhanced from the Type-0 eCAP with the following added
features:
•
Event filter reset bit
– Writing a 1 to ECCTL2[CTRFILTRESET] will clear the event filter, the modulo counter, and any pending
interrupts flags. Resetting the bit is useful for initialization and debug.
Modulo counter status bits
•
– The modulo counter (ECCTL2 [MODCTRSTS]) indicates which capture register will be loaded next. In the
Type-0 eCAP, it was not possible to know current state of modulo counter.
DMA trigger source
– eCAPxDMA is added as a DMA trigger. CEVT[1–4] can be configured as the source for eCAPxDMA.
Input multiplexer
•
•
•
– ECCTL0 [INPUTSEL] selects one of 128 input signals.
EALLOW protection
– EALLOW protection is added to critical registers. To maintain software compatibility with the Type-0 eCAP,
configure DEV_CFG_REGS.ECAPTYPE to make these registers unprotected.
ECAPxSYNCINSEL register
•
– The ECAPSxYNCINSEL register is added for each eCAP to select an external SYNCIN. Every eCAP can
have a separate SYNCIN signal.
The eCAP inputs connect to any GPIO input through the Input X-BAR. The APWM outputs connect to GPIO pins
through the Output X-BAR to OUTPUTx positions in the GPIO mux. See Section 6.5.2 and Section 6.5.3.
Figure 7-46 shows the eCAP and HRCAP block diagram.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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ECCTL2 [ SYNCI_EN, SYNCOSEL, SWSYNC]
ECCTL2[CAP/APWM]
APWM Mode
CTRPHS
(phase register−32 bit)
ECAPxSYNCIN
OVF
RST
CTR_OVF
CTR [0−31]
PRD [0−31]
CMP [0−31]
TSCTR
ECAPxSYNCOUT
PWM
Compare
Logic
Output
X-Bar
(counter−32 bit)
Delta−Mode
32
CTR=PRD
CTR=CMP
CTR [0−31]
PRD [0−31]
32
ECCTL1 [ CAPLDEN, CTRRSTx]
HRCTRL[HRE]
32
32
LD1
CAP1
Polarity
Select
LD
(APRD Active)
APRD
32
shadow
CMP [0−31]
32
HRCTRL[HRE]
32
HRCTRL[HRE]
32
CAP2
Polarity
Select
LD2
LD
Other
Sources
(ACMP Active)
[127:16]
[15:0]
Event
Prescale
Event
32
ACMP
16
qualifier
Input
shadow
LD
ECCTL1[PRESCALE]
HRCTRL[HRE]
32
X-Bar
32
Polarity
Select
LD3
LD4
CAP3
(APRD Shadow)
HRCTRL[HRE]
32
32
CAP4
Polarity
Select
LD
(ACMP Shadow)
Edge Polarity Select
ECCTL1[CAPxPOL]
4
Capture Events
4
CEVT[1:4]
ECAPxDMA_INT
ECCTL2[CTRFILTRESET]
Interrupt
Continuous /
Oneshot
Trigger
and
MODCNTRSTS
CTR_OVF
CTR=PRD
CTR=CMP
Capture Control
ECCTL2[DMAEVTSEL]
Flag
Control
ECAPx
(to ePIE)
ECCTL2 [ REARM, CONT_ONESHT, STOP_WRAP]
Registers: ECEINT, ECFLG, ECCLR, ECFRC
Capture Pulse
HR Input
SYSCLK
HRCLK
(A)
HR Submodule
ECAPx_HRCAL
(to ePIE)
Copyright © 2018, Texas Instruments Incorporated
A. The HRCAP submodule is not available on all eCAP modules; in this case, the high-resolution muxes and hardware are not
implemented.
Figure 7-46. eCAP and HRCAP Block Diagram
The eCAP module is clocked by PERx.SYSCLK.
The clock enable bits (ECAPx) in the PCLKCR3 register turn off the eCAP module individually (for low-power
operation). Upon reset, ECAP1ENCLK is set to low, indicating that the peripheral clock is off.
The eCAP6 and eCAP7 modules can be configured as high-resolution capture (HRCAP) submodules. The
HRCAP submodule measures the difference, in time, between pulses asynchronously to the system clock. This
submodule is new to the eCAP Type 2 module, and features many enhancements over the Type 0 HRCAP
module.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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Applications for the HRCAP include:
•
•
•
•
•
•
•
Capacitive touch applications
High-resolution period and duty-cycle measurements of pulse train cycles
Instantaneous speed measurements
Instantaneous frequency measurements
Voltage measurements across an isolation boundary
Distance/sonar measurement and scanning
Flow measurements
The HRCAP submodule includes the following features:
•
•
•
•
•
•
•
Pulse-width capture in either non-high-resolution or high-resolution modes
Absolute mode pulse-width capture
Continuous or "one-shot" capture
Capture on either falling or rising edge
Continuous mode capture of pulse widths in 4-deep buffer
Hardware calibration logic for precision high-resolution capture
All of the resources in this list are available on any pin using the Input X-BAR.
The HRCAP submodule includes one high-resolution capture channel in addition to a calibration block. The
calibration block allows the HRCAP submodule to be continually recalibrated, at a set interval, with no “down
time”. Because the HRCAP submodule now uses the same hardware as its respective eCAP, if the HRCAP is
used, the corresponding eCAP will be unavailable.
Each high-resolution-capable channel has the following independent key resources.
•
•
•
All hardware of the respective eCAP
High-resolution calibration logic
Dedicated calibration interrupt
7.12.1.1 eCAP Synchronization
The eCAP modules can be synchronized with each other by selecting a common SYNCIN source. SYNCIN
source for eCAP can be either software sync-in or external sync-in. The external sync-in signal can come from
EPWM or eCAP or X-Bar or EtherCAT. The SYNC signal is defined by the selection in the
ECAPxSYNCINSEL[SEL] bit for ECAPx as shown in Figure 7-47.
ECAPx
Disable
0x0
0x1
ECAPxSYNCIN
ECAPxSYNCOUT
EPWM[1..16]SYNCOUT
ECAP[1..7]SYNCOUT
INPUT5 (Input X-Bar)
EPWMxSYNCOUT
ECCTL2[SWSYNC]
CTR=PRD
EXTSYNCOUT
Disable
INPUT6 (Input X-Bar)
ETHERCATSYNC0
ETHERCATSYNC1
Disable
0x1f
SYNCSELECT[SYNCOUT]
ECCTL2[SYNCOSEL]
ECAPSYNCINSEL[SEL]
Figure 7-47. eCAPSynchronization Scheme
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.12.1.2 eCAP Electrical Data and Timing
Section 7.12.1.2.1 lists the eCAP timing requirements and Section 7.12.1.2.2 lists the eCAP switching
characteristics.
7.12.1.2.1 eCAP Timing Requirements
MIN
2tc(SYSCLK)
NOM
MAX
UNIT
Asynchronous
Synchronous
tw(CAP)
Capture input pulse width
2tc(SYSCLK)
ns
With input qualifier
1tc(SYSCLK) + tw_(IQSW)
7.12.1.2.2 eCAP Switching Charcteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
20
TYP
MAX
UNIT
ns
tw(APWM)
Pulse duration, APWMx output high/low
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.12.1.3 HRCAP Electrical Data and Timing
Section 7.12.1.3.1 lists the HRCAP switching characteristics. Figure 7-48 shows the HRCAP accuracy precision
and resolution. Figure 7-49 shows the HRCAP standard deviation characteristics.
7.12.1.3.1 HRCAP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ns
Input pulse width
110
Measurement length ≤ 5 µs
Measurement length > 5 µs
±390
±450
540
ps
Accuracy(1) (2) (3) (4)
1450
ps
Standard deviation
Resolution
See Figure 7-49
300
ps
(1) Value obtained using an oscillator of 100 PPM, oscillator accuracy directly affects the HRCAP accuracy.
(2) Measurement is completed using rising-rising or falling-falling edges
(3) Opposite polarity edges will have an additional inaccuracy due to the difference between VIH and VIL. This effect is dependent on the
signal’s slew rate.
(4) Accuracy only applies to time-converted measurements.
7.12.1.3.2 HRCAP Graphs
HRCAP’s Mean
Accuracy
Resolution
(Step Size)
Precision
(Standard Deviation)
Actual
Input Signal
A. The HRCAP has some variation in performance, this results in a probability distribution which is described using the following terms:
•
•
•
Accuracy: The time difference between the input signal and the mean of the HRCAP’s distribution.
Precision: The width of the HRCAP’s distribution, this is given as a standard deviation.
Resolution: The minimum measurable increment.
Figure 7-48. HRCAP Accuracy Precision and Resolution
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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2
1.8
1.6
1.4
1.2
1
7.4
Typical Core Conditions
Noisy Core Supply
6.66
5.92
5.18
4.44
3.7
0.8
0.6
0.4
0.2
2.96
2.22
1.48
0.74
0
1000
2000
3000
4000
5000
Time Between Edges(nS)
6000
7000
8000
9000
10000
A. Typical core conditions: All peripheral clocks are enabled.
B. Noisy core supply: All core clocks are enabled and disabled with a regular period during the measurement. This resulted in the 1.2-V rail
experiencing a 18.5-mA swing during the measurement.
C. Fluctuations in current and voltage on the 1.2-V rail cause the standard deviation of the HRCAP to rise. Care should be taken to ensure
that the 1.2-V supply is clean, and that noisy internal events, such as enabling and disabling clock trees, have been minimized while
using the HRCAP.
Figure 7-49. HRCAP Standard Deviation Characteristics
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.12.2 Enhanced Pulse Width Modulator (ePWM)
The ePWM peripheral is a key element in controlling many of the power electronic systems found in both
commercial and industrial equipment. The ePWM type-4 module is able to generate complex pulse width
waveforms with minimal CPU overhead by building the peripheral up from smaller modules with separate
resources that can operate together to form a system. Some of the highlights of the ePWM type-4 module
include complex waveform generation, dead-band generation, a flexible synchronization scheme, advanced trip-
zone functionality, and global register reload capabilities.
Figure 7-50 shows the signal interconnections with the ePWM. Figure 7-51 shows the ePWM trip input
connectivity.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
Time-Base (TB)
TBPRD Shadow (24)
ePWM
SYNC
Scheme
EXTSYNCIN
EXTSYNCOUT
TBPRDHR (8)
TBPRD Active (24)
CTR=PRD
EPWMxSYNCI
TBCTL[PHSEN]
TBCTL[SWFSYNC]
DCAEVT1/sync(A)
DCBEVT1/sync(A)
Counter
Up/Down
(16 bit)
CTR=ZERO
CTR_Dir
TBCTR
Active (16)
CTR=PRD
EPWMx_INT
CTR=ZERO
TBPHSHR (8)
EPWMxSOCA
EPWMxSOCB
CTR=PRD or ZERO
CTR=CMPA
16
8
On-chip
ADC
Event
Trigger
And
Interrupt
(ET)
Phase
Control
TBPHS Active (24)
CTR=CMPB
CTR=CMPC
CTR=CMPD
CTR_Dir
DCAEVT1.soc(A)
DCBEVT1.soc(A)
ADCSOCOUTSELECT
Counter Compare (CC)
Action
Qualifier
(AQ)
CTR=CMPA
CMPAHR (8)
Select and pulse stretch
for external ADC
16
HiRes PWM (HRPWM)
CMPAHR (8)
EPWMA
ADCSOCAO
ADCSOCBO
CMPA Active (24)
CMPA Shadow (24)
ePWMxA
Trip
Zone
(TZ)
Dead
Band
(DB)
PWM
Chopper
(DB)
CTR=CMPB
CMPBHR (8)
16
CMPB Active (16)
EPWMB
ePWMxB
CMPB Shadow (16)
CMPBHR (8)
CTR=CMPC
EPWMx_TZ_INT
TZ1 to TZ3
TBCNT (16)
CMPC[15-0]
CTR=ZERO
DCAEVT1.inter
DCBEVT1.inter
DCAEVT2.inter
EMUSTOP
16
CLOCKFAIL
CMPC Active (16)
EQEPxERR
DCBEVT2.inter
DCAEVT1.force(A)
DCBEVT1.force(A)
DCAEVT2.force(A)
CMPC Shadow (16)
TBCNT (16)
CTR=CMPD
DCBEVT2.force(A)
CMPD[15-0]
16
CMPD Active (16)
CMPD Shadow (16)
A. These events are generated by the ePWM digital compare (DC) submodule based on the levels of the TRIPIN inputs.
Figure 7-50. ePWM Submodules and Critical Internal Signal Interconnects
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
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GPIO0
Async/
Sync/
Input X-Bar
Sync+Filter
GPIOx
Other Sources
INPUT[1:16]
16:127
0:15
eCAPx
XINT1
XINT2
XINT3
XINT4
XINT5
ADC
Wrapper(s)
PIE,
CLA
ePWM
eCAP
Sync Chain
EXTSYNCIN1
EXTSYNCIN2
TZ1
TZ2
TZ3
EPWMINT
TZINT
TRIP1
TRIP2
TRIP3
TRIP6
EPWMx.EPWMCLK
PCLKCR2[EPWMx]
TBCLKSYNC
PCLKCR0[TBCLKSYNC]
TRIP4
TRIP5
TRIP7
TRIP8
TRIP9
TRIP10
TRIP11
TRIP12
INPUT[1:14]
CMPSSx.TRIPH
CMPSSx.TRIPHORL
SDFM
CMPSSx.TRIPL
ADCx.EVT1-4
ECAPx.OUT
All
ePWM
Modules
FLT1
FLT2
FLT3
FLT4
ePWM
X-Bar
SD1.FLTx.COMPx
SD1.FLTx.DRINTx
EXTSYNCOUT
ADCSOCx
ADCSOCAO Select
ADCSOCBO Select
CLAHALT
TRIP14
TRIP15
TZ4
TZ5
TZ6
ECCERR
SOCA
SOCB
CPU1.PIEVECTERROR
CPU2.PIEVECTERROR
ADC
Wrapper(s)
EQEPERR
CLKFAIL
CPU1.EMUSTOP
CPU2.EMUSTOP
EPWMn.EMUSTOP
EPWMSYNCPER
Blanking Window
DAC
CPUSEL0.EPWMx
CMPSS
Figure 7-51. ePWM Trip Input Connectivity
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
7.12.2.1 Control Peripherals Synchronization
The ePWM and eCAP synchronization scheme on the device provides flexibility in partitioning the ePWM and
eCAP modules between CPU1 and CPU2 and allows localized synchronization within the modules belonging to
the same CPU. Like the other peripherals, the partitioning of the ePWM and eCAP modules needs to be done
using the CPUSELx registers. Figure 7-52 shows the synchronization scheme.
TBCTL
SWFSYNC
CTR=ZERO
CTR=CMPB
CTR=CMPC
CTR=CMPD
CLR
DCAEVT1.sync
One Shot
Latch
DCBEVT1.sync
0
Set
Q
EPWMSYNCOUTEN
1
SWEN
ZEROEN
0
0
1
CMPBEN
EPWMxSYNCOUT
1
0
OR
CMPCEN
CMPDEN
DCARVT1EN
DCBEVT1EN
TBCTL2[SELFCLRTRREM]
Clear
Register
Disable
0
EPWM1SYNCOUT
|
|
|
EPWMxSYNCOUT
ECAP1SYNCOUT
HRPCTL[PWMSYNCSELX]
CTR=CMPC UP
EPWMxSYNCIN
|
|
|
CTR=CMPC DOWN
CTR=CMPD UP
ECAPySYNCOUT
Other Sources
EPWMxSYNCPER
CTR=CMPD DOWN
HRPCTL[PWMSYNCSEL]
CTR=PRD
CMPSS
DAC
EPWMSYNCINSEL
Note: SYNCO and SYNCOUT are used interchangeably
CTR=ZERO
Figure 7-52. Synchronization Chain Architecture
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.12.2.2 ePWM Electrical Data and Timing
Section 7.12.2.2.1 lists the PWM timing requirements and Section 7.12.2.2.2 lists the PWM switching
characteristics. For an explanation of the input qualifier parameters, see Section 7.10.6.2.1.
7.12.2.2.1 ePWM Timing Requirements
MIN
MAX
UNIT
f(EPWM)
Frequency, EPWMCLK
Sync input pulse width
200
MHz
Asynchronous
Synchronous
2tc(EPWMCLK)
2tc(EPWMCLK)
tw(SYNCIN)
cycles
With input qualifier
1tc(EPWMCLK) + tw(IQSW)
7.12.2.2.2 ePWM Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
20
MAX
UNIT
tw(PWM)
Pulse duration, PWMx output high/low
Sync output pulse width
ns
tw(SYNCOUT)
8tc(SYSCLK)
cycles
Delay time, trip input active to PWM forced high
Delay time, trip input active to PWM forced low
Delay time, trip input active to PWM Hi-Z
(1)
td(TZ-PWM)
tskew(PWM)
30
ns
ns
Skew between any two PWM outputs
2.5
(1) The delay time is only for GPIO sources, it excludes the CMPSS.
7.12.2.2.3 Trip-Zone Input Timing
Section 7.12.2.2.3.1 lists the trip-zone input timing requirements. Figure 7-53 shows the PWM Hi-Z
characteristics. For an explanation of the input qualifier parameters, see Section 7.10.6.2.1.
7.12.2.2.3.1 Trip-Zone Input Timing Requirements
MIN
1tc(EPWMCLK)
MAX UNIT
cycles
Asynchronous
Synchronous
tw(TZ)
Pulse duration, TZx input low
2tc(EPWMCLK)
cycles
With input qualifier
1tc(EPWMCLK) + tw(IQSW)
cycles
EPWMCLK
tw(TZ)
TZ(A)
td(TZ-PWM)
PWM(B)
A. TZ: TZ1, TZ2, TZ3, TRIP1–TRIP12
B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM recovery software.
Figure 7-53. PWM Hi-Z Characteristics
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
7.12.2.3 External ADC Start-of-Conversion Electrical Data and Timing
Section 7.12.2.3.1 lists the external ADC start-of-conversion switching characteristics. Figure 7-54 shows the
ADCSOCAO or ADCSOCBO timing.
7.12.2.3.1 External ADC Start-of-Conversion Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
tw(ADCSOCL)
Pulse duration, ADCSOCxO low
32tc(SYSCLK)
cycles
tw(ADCSOCL)
ADCSOCAO
or
ADCSOCBO
Figure 7-54. ADCSOCAO or ADCSOCBO Timing
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.12.3 High-Resolution Pulse Width Modulator (HRPWM)
The HRPWM combines multiple delay lines in a single module and a simplified calibration system by using a
dedicated calibration delay line. For each ePWM module, there are two HR outputs:
•
•
HR Duty and Deadband control on Channel A
HR Duty and Deadband control on Channel B
The HRPWM module offers PWM resolution (time granularity) that is significantly better than what can be
achieved using conventionally derived digital PWM methods. The key points for the HRPWM module are:
•
•
Significantly extends the time resolution capabilities of conventionally derived digital PWM
This capability can be used in both single edge (duty cycle and phase-shift control) as well as dual edge
control for frequency/period modulation.
•
Finer time granularity control or edge positioning is controlled through extensions to the Compare A, B,
phase, period and deadband registers of the ePWM module.
Note
The minimum HRPWMCLK frequency allowed for HRPWM is 60 MHz.
7.12.3.1 HRPWM Electrical Data and Timing
Section 7.12.3.1.1 lists the high-resolution PWM switching characteristics.
7.12.3.1.1 High-Resolution PWM Characteristics
PARAMETER
MIN
TYP
MAX UNIT
310 ps
Micro Edge Positioning (MEP) step size(1)
150
(1) The MEP step size will be largest at high temperature and minimum voltage on VDD. MEP step size will increase with higher
temperature and lower voltage and decrease with lower temperature and higher voltage.
Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI
software libraries for details of using SFO functions in end applications. SFO functions help to estimate the number of MEP steps per
SYSCLK period dynamically while the HRPWM is in operation.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.12.4 Enhanced Quadrature Encoder Pulse (eQEP)
The eQEP module on this device is Type-2. The eQEP interfaces directly with linear or rotary incremental
encoders to obtain position, direction, and speed information from rotating machines used in high-performance
motion and position control systems.
The eQEP peripheral contains the following major functional units (see Figure 7-55):
•
•
•
•
•
•
•
Programmable input qualification for each pin (part of the GPIO MUX)
Quadrature decoder unit (QDU)
Position counter and control unit for position measurement (PCCU)
Quadrature edge-capture unit for low-speed measurement (QCAP)
Unit time base for speed/frequency measurement (UTIME)
Watchdog timer for detecting stalls (QWDOG)
Quadrature Mode Adapter (QMA)
System
control registers
To CPU
EQEPxENCLK
SYSCLK
QCPRD
Enhanced QEP (eQEP) peripheral
QCAPCTL
16
QCTMR
16
16
Quadrature
capture unit
(QCAP)
QCTMRLAT
QCPRDLAT
QUTMR
QUPRD
QWDTMR
QWDPRD
Registers
used by
multiple units
32
16
QDECCTL
16
QEPCTL
QEPSTS
QFLG
UTOUT
UTIME
QWDOG
EQEPx_A
EQEPx_B
EQEPxAIN
WDTOUT
QMA
EQEPxBIN
EQEPxINT
QCLK
PIE
QDIR
EQEPxIIN
Quadrature
32
QI
GPIO
MUX
EQEPx_INDEX
EQEPxIOUT
Position counter/
control unit
(PCCU)
decoder
(QDU)
QS
EQEPxIOE
QPOSLAT
PHE
QPOSSLAT
QPOSILAT
PCSOUT
EQEPxSIN
EQEPx_STROBE
EQEPxSOUT
EQEPxSOE
32
32
16
QEINT
QPOSCNT
QPOSINIT
QPOSMAX
QPOSCMP
QFRC
QCLR
QPOSCTL
Copyright © 2017, Texas Instruments Incorporated
Figure 7-55. eQEP Block Diagram
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.12.4.1 eQEP Electrical Data and Timing
Section 7.12.4.1.1 lists the eQEP timing requirement. GPIO asynchronous mode should not be used for eQEP
input pins. For an explanation of the input qualifier parameters, see Section 7.10.6.2.1.
Section 7.12.4.1.2 lists the eQEP switching characteristics.
7.12.4.1.1 eQEP Timing Requirements
MIN
MAX
UNIT
Synchronous(1)
2tc(SYSCLK)
tw(QEPP)
QEP input period
cycles
With input qualifier
Synchronous(1)
2[1tc(SYSCLK) + tw(IQSW)]
2tc(SYSCLK)
2tc(SYSCLK) + tw(IQSW)
2tc(SYSCLK)
tw(INDEXH)
tw(INDEXL)
tw(STROBH)
tw(STROBL)
QEP Index Input High time
QEP Index Input Low time
QEP Strobe High time
QEP Strobe Input Low time
cycles
cycles
cycles
cycles
With input qualifier
Synchronous(1)
With input qualifier
Synchronous(1)
2tc(SYSCLK) + tw(IQSW)
2tc(SYSCLK)
2tc(SYSCLK) + tw(IQSW)
2tc(SYSCLK)
With input qualifier
Synchronous(1)
With input qualifier
2tc(SYSCLK) + tw(IQSW)
(1) The GPIO GPxQSELn Asynchronous mode should not be used for eQEP module input pins.
7.12.4.1.2 eQEP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
4tc(SYSCLK)
6tc(SYSCLK)
UNIT
cycles
cycles
td(CNTR)xin
Delay time, external clock to counter increment
td(PCS-OUT)QEP
Delay time, QEP input edge to position compare sync output
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.12.5 Sigma-Delta Filter Module (SDFM)
The SDFM is a four-channel digital filter designed specifically for current measurement and resolver position
decoding in motor control applications. Each input channel can receive an independent sigma-delta (ΣΔ)
modulated bit stream. The bit streams are processed by four individually programmable digital decimation filters.
The filter set includes a fast comparator (secondary filter) for immediate digital threshold comparisons for over-
current and under-current monitoring, and zeros-crossing detection. Figure 7-56 shows a block diagram of the
SDFMs.
SDFM features include:
•
Eight external pins per SDFM module
– Four sigma-delta data input pins per SDFM module (SD-Dx, where x = 1 to 4)
– Four sigma-delta clock input pins per SDFM module (SD-Cx, where x = 1 to 4)
Configurable modulator clock mode supported:
•
•
– Mode 0: Modulator clock rate equals the modulator data rate.
Four independent, configurable secondary filter (comparator) units per SDFM module:
– Four different filter type selection (Sinc1/Sinc2/Sincfast/Sinc3) options available
– Ability to detect over-value condition, under-value condition, and Threshold-crossing conditions
1. Two independent Higher Threshold comparators (used to detect over-value condition)
2. Two independent Lower Threshold comparators (used to detect under-value condition)
3. One independent Threshold-Crossing comparator (used to measure duty cycle/frequency with eCAP)
– OSR value for comparator filter unit (COSR) programmable from 1 to 32
Four independent configurable primary filter (data filter) units per SDFM module:
– Four different filter type selection (Sinc1/Sinc2/Sincfast/Sinc3) options available
– OSR value for data filter unit (DOSR) programmable from 1 to 256
– Ability to enable or disable (or both) individual filter module
•
– Ability to synchronize all four independent filters of an SDFM module by using the Master Filter Enable
(MFE) bit or by using PWM signals
•
•
Data filter output can be represented in either 16 bits or 32 bits.
Data filter unit has a programmable mode FIFO to reduce interrupt overhead. The FIFO has the following
features:
– The primary filter (data filter) has a 16-deep x 32-bit FIFO.
– The FIFO can interrupt the CPU after programmable number of data-ready events.
– FIFO Wait-for-Sync feature: Ability to ignore data-ready events until the PWM synchronization signal
(SDSYNC) is received. Once the SDSYNC event is received, the FIFO is populated on every data-ready
event.
– Data filter output can be represented in either 16 bits or 32 bits.
•
•
•
•
•
PWMx.SOCA/SOCB can be configured to serve as SDSYNC source on a per-data-filter-channel basis.
PWMs can be used to generate a modulator clock for sigma-delta modulators.
Configurable Input Qualification available for both SD-Cx and SD-Dx
Ability to use one filter channel clock (SD-C1) to provide clock to other filter clock channels.
Configurable digital filter available on comparator filter events to blankout comparator events caused by
spurious noise
Note
Care should be taken to avoid noise on the SDx_Cy input. If the minimum pulse width requirements
are not met (for example, through a noise glitch), then the SDFM results could become undefined.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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Figure 7-56 shows the SDFM block diagram.
Output XBAR
PWM XBAR
SDyFLTx_CEVT1 SDyFLTx_CEVT2
Comparator
Signals
SDyFLTx.DR
SDFM- Sigma Delta Filter Module
G4
Streams
DMA
Filter Module 1
Secondary
(Comparator)
Filter
Interrupt
Unit
SDy_D1
SDy_C1
Input
Ctrl
SDy_ERR
Primary (Data)
Filter
SDyFLTx.DR
CLA
PWMi.SOCA / SOCB
PWMj.CMPC
FIFO
SDy_D2
SDy_C2
Filter Module 2
SDy_ERR
SDyFLTx.DR
C28x
GPIO
MUX
PWMi.SOCA / SOCB
PWMj.CMPC
SDy_D3
SDy_C3
Filter Module 3
Filter Module 4
SDyFLTx_CEVT1
SDyFLTx_CEVT2
ECAP
PWMi.SOCA / SOCB
PWMj.CMPD
Register
Map
SDy_D4
SDy_C4
PWMi.SOCA / SOCB
PWMj.CMPD
LEGEND
Where,
j
i
=
=
y =
x =
11 for SDFM1 & 12 for SDFM2
1 to Max. no of PWMs
1 for SDFM1 & 2 for SDFM2
1 t 4
Interrupt / trigger sources from SDFM
Internal secondary filter signals
Figure 7-56. SDFM Block Diagram
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.12.5.1 SDFM Electrical Data and Timing (Using ASYNC)
Section 7.12.5.1.1 lists the SDFM timing requirements. The following configurations should be made:
•
•
SDFM GPIO pins should be configured in ASYNC mode only (using GPYQSELn = 0b11).
Both SDx-Cy and SDx-Dy signals need to be synchronized to PLLRAWCLK (using SDCTLPARMx registers).
Figure 7-57 shows the SDFM timing diagram.
7.12.5.1.1 SDFM Timing Requirements When Using Asynchronous GPIO (ASYNC) Option
MIN
MAX
UNIT
Mode 0
tc(SDC)M0
Cycle time, SDx_Cy
4 * tc(PLLRAWCLK)
2 * tc(PLLRAWCLK)
256 * SYSCLK period
ns
ns
ns
ns
tw(SDDHL)M0
Pulse duration, SDx_Dy (high / Low)
Setup time, SDx_Dy valid before SDx_Cy goes high
Hold time, SDx_Dy wait after SDx_Cy goes high
tsu(SDDV-SDCH)M0
th(SDCH-SDD)M0
1 * tc(PLLRAWCLK) + 5
1 * tc(PLLRAWCLK) + 5
7.12.5.1.2 SDFM Timing Diagram
WARNING
Special precautions should be taken on both SD-Cx and SD-Dx signals to ensure a clean and noise-
free signal that meets SDFM timing requirements. Precautions such as series termination resistors
for ringing noise due to any impedance mismatch of clock driver and spacing of traces from other
noisy signals are recommended.
Note
The SDFM SD-Cx and SD-Dx signals, when synchronized to PLLRAWCLK, provide protection against
SDFM module corruption due to occasional random noise glitches that may result in a false
comparator trip and filter output. However, the signals do not provide protection against persistent
violations of the above timing requirements. Timing violations will result in data corruption proportional
to the number of bits which violate the requirements.
Mode 0
tw(SDCH)M0
tc(SDC)M0
SDx_Cy
SDx_Dy
tsu(SDDV-SDCH)M0
th(SDCH-SDD)M0
Figure 7-57. SDFM Timing Diagram – Mode 0
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.13 C28x Communications Peripherals
Note
For the actual number of each peripheral on a specific device, see the Device Comparison table.
7.13.1 Controller Area Network (CAN)
This device uses the CAN IP known as DCAN.
The CAN module performs CAN protocol communication according to ISO 11898-1 (identical to Bosch® CAN
protocol specification 2.0 A, B). The bit rate can be programmed to values up to 1 Mbps. A CAN transceiver chip
is required for the connection to the physical layer (CAN bus).
For communication on a CAN network, individual message objects can be configured. The message objects and
identifier masks are stored in the Message RAM.
All functions concerning the handling of messages are implemented in the message handler. These functions
are: acceptance filtering; the transfer of messages between the CAN Core and the Message RAM; and the
handling of transmission requests as well as the generation of interrupts or DMA requests.
The register set of the CAN may be accessed directly by the CPU through the module interface. These registers
are used to control and configure the CAN core and the message handler, and to access the message RAM.
The CAN module implements the following features:
•
•
•
•
Complies with ISO11898-1 ( Bosch® CAN protocol specification 2.0 A and B)
Bit rates up to 1 Mbps
Multiple clock sources
32 message objects (mailboxes), each with the following properties:
– Configurable as receive or transmit
– Configurable with standard (11-bit) or extended (29-bit) identifier
– Supports programmable identifier receive mask
– Supports data and remote frames
– Holds 0 to 8 bytes of data
– Parity-checked configuration and data RAM
Individual identifier mask for each message object
Programmable FIFO mode for message objects
Programmable loop-back modes for self-test operation
Suspend mode for debug support
•
•
•
•
•
•
•
•
•
Software module reset
Automatic bus-on, after bus-off state by a programmable 32-bit timer
Message-RAM parity-check mechanism
Two interrupt lines
DMA support
Note
For a CAN bit clock of 200 MHz, the smallest bit rate possible is 7.8125 kbps.
Note
The accuracy of the on-chip zero-pin oscillator is in Section 7.10.3.5.1. Depending on parameters
such as the CAN bit timing settings, bit rate, bus length, and propagation delay, the accuracy of this
oscillator may not meet the requirements of the CAN protocol. In this situation, an external clock
source must be used.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
Figure 7-58 shows the CAN block diagram.
CAN_H
CAN_L
CAN Bus
3.3V CAN Transceiver
CANx TX pin
External connections
Device
CANx RX pin
CAN
CAN Core
Message RAM
Message Handler
Message
RAM
Interface
Register and Message
Object Access (IFx)
32
Message
Objects
(Mailboxes)
Test Modes
Only
Module Interface
CANINT0 CANINT1
(to ePIE)
CPU Bus
Figure 7-58. CAN Block Diagram
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.13.2 Fast Serial Interface (FSI)
The Fast Serial Interface (FSI) module is a serial communication peripheral capable of reliable and robust high-
speed communications. The FSI is designed to ensure data robustness across many system conditions such as
chip-to-chip as well as board-to-board across an isolation barrier. Payload integrity checks such as CRC, start-
and end-of-frame patterns, and user-defined tags, are encoded before transmit and then verified after receipt
without additional CPU interaction. Line breaks can be detected using periodic transmissions, all managed and
monitored by hardware. The FSI is also tightly integrated with other control peripherals on the device. To ensure
that the latest sensor data or control parameters are available, frames can be transmitted on every control loop
period. An integrated skew-compensation block has been added on the receiver to handle skew that may occur
between the clock and data signals due to a variety of factors, including trace-length mismatch and skews
induced by an isolation chip. With embedded data robustness checks, data-link integrity checks, skew
compensation, and integration with control peripherals, the FSI can enable high-speed, robust communication in
any system. These and many other features of the FSI follow.
The FSI module includes the following features:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Independent transmitter and receiver cores
Source-synchronous transmission
Double data rate (DDR)
One or two data lines
Programmable data length
Skew adjustment block to compensate for board and system delay mismatches
Frame error detection
Programmable frame tagging for message filtering
Hardware ping to detect line breaks during communication (ping watchdog)
Two interrupts per FSI core
Externally triggered frame generation
Hardware- or software-calculated CRC
Embedded ECC computation module
Register write protection
DMA support
CLA task triggering
SPI signaling mode (limited features available)
Operating the FSI at maximum speed (50 MHz) at dual data rate (100 Mbps) may require the integrated skew
compensation block to be configured according to the specific operating conditions on a case-by-case basis.
The Fast Serial Interface (FSI) Skew Compensation Application Report provides example software on how to
configure and set up the integrated skew compensation block on the Fast Serial Interface.
The FSI consists of independent transmitter (FSITX) and receiver (FSIRX) cores. The FSITX and FSIRX cores
are configured and operated independently. The features available on the FSITX and FSIRX are described in
Section 7.13.2.1 and Section 7.13.2.2, respectively.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.13.2.1 FSI Transmitter
The FSI transmitter module handles the framing of data, CRC generation, signal generation of TXCLK, TXD0,
and TXD1, as well as interrupt generation. The operation of the transmitter core is controlled and configured
through programmable control registers. The transmitter control registers let the CPU (or the CLA) program,
control, and monitor the operation of the FSI transmitter. The transmit data buffer is accessible by the CPU, CLA,
and the DMA.
The transmitter has the following features:
•
•
•
•
•
•
•
•
•
•
Automated ping frame generation
Externally triggered ping frames
Externally triggered data frames
Software-configurable frame lengths
16-word data buffer
Data buffer underrun and overrun detection
Hardware-generated CRC on data bits
Software ECC calculation on select data
DMA support
CLA task triggering
Figure 7-59 shows the FSITX CPU interface. Figure 7-60 shows the high-level block diagram of the FSITX. Not
all data paths and internal connections are shown. This diagram provides a high-level overview of the internal
modules present in the FSITX.
PLLRAWCLK
PCLKCR18
SYSCLK
SYSRSN
C28x
ePIE
FSITXyINT1
FSITXyINT2
CLA
FSITXyCLK
FSITXyD0
FSITXyD1
FSITX
DMA
FSITXyDMA
32
A. The signals connected to the trigger muxes are described in the External Frame Trigger Mux section of the Fast Serial Interface (FSI)
chapter in the TMS320F2838x Real-Time Microcontrollers Technical Reference Manual.
Figure 7-59. FSITX CPU Interface
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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FSITX
PLLRAWCLK
SYSRSN
SYSCLK
FSI Mode:
TXCLKIN
Transmit Clock
Generator
TXCLK = TXCLKIN/2
SPI Signaling Mode:
TXCLK = TXCLKIN
Register Interface
Core Reset
FSITXINT1
FSITXINT2
Control Registers,
Interrupt Management
TXCLK
Ping Time-out Counter
FSITX_DMA_EVT
TXD0
TXD1
Transmitter Core
External Frame Triggers
Transmit Data
Buffer
ECC Logic
Figure 7-60. FSITX Block Diagram
7.13.2.1.1 FSITX Electrical Data and Timing
Section 7.13.2.1.1.1 lists the FSITX switching characteristics. Figure 7-61 shows the FSITX timings.
7.13.2.1.1.1 FSITX Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
NO.
PARAMETER
MIN
20
MAX
UNIT
ns
1
tc(TXCLK)
tw(TXCLK)
Cycle time, TXCLK
2
Pulse width, TXCLK low or TXCLK high
(0.5tc(TXCLK)) – 1
(0.5tc(TXCLK)) + 1
ns
Delay time, Data valid after TXCLK high or
low
3
td(TXCLKL–TXD)
(0.25tc(TXCLK)) – 2
(0.25tc(TXCLK)) + 2.5
ns
7.13.2.1.1.2 FSITX Timings
1
2
FSITXCLK
FSITXD0
FSITXD1
3
Figure 7-61. FSITX Timings
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.13.2.2 FSI Receiver
The receiver module interfaces to the FSI clock (RXCLK) and the data lines (RXD0 and RXD1) after they pass
through the programmable delay line. The receiver core handles the data framing, CRC computation, and frame-
related error checking. The receiver bit clock and state machine are run by the RXCLK input, which is
asynchronous to the device system clock.
The receiver control registers let the CPU (or the CLA) program, control, and monitor the operation of the FSIRX.
The receive data buffer is accessible by the CPU, CLA, and the DMA.
The receiver core has the following features:
•
•
•
•
•
•
•
•
•
16-word data buffer
Multiple supported frame types
Ping frame watchdog
Frame watchdog
CRC calculation and comparison in hardware
ECC detection
Programmable delay line control on incoming signals
DMA support
CLA task triggering
Figure 7-62 shows the FSIRX CPU interface. Figure 7-63 provides a high-level overview of the internal modules
present in the FSIRX. Not all data paths and internal connections are shown.
PCLKCR18
SYSCLK
SYSRSN
C28x
ePIE
FSIRXyINT1
FSIRXyINT2
CLA
FSIRXyCLK
FSIRXyD0
FSIRXyD1
FSIRX
DMA
FSIRXyDMA
Figure 7-62. FSIRX CPU Interface
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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FSIRX
SYSRSn
SYSCLK
Frame Watchdog
Register Interface
Core Reset
FSIRXINT1
Control Registers,
Interrupt Management
FSIRXINT2
RXCLK
RXD0
Ping Watchdog
FSIRX_DMA_EVT
Receiver Core
Skew
Control
RXD1
Receive Data
Buffer
ECC Check
Logic
Figure 7-63. FSIRX Block Diagram
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.13.2.2.1 FSIRX Electrical Data and Timing
Section 7.13.2.2.1.1 lists the FSIRX timing requirements. Section 7.13.2.2.1.2 lists the FSIRX electrical
characteristics. Figure 7-64 shows the FSIRX timings.
7.13.2.2.1.1 FSIRX Timing Requirements
NO.
MIN
20
MAX
UNIT
ns
1
tc(RXCLK)
tw(RXCLK)
Cycle time, RXCLK
2
Pulse width, RXCLK low or RXCLK high.
(0.5tc(RXCLK)) – 1
(0.5tc(RXCLK)) + 1
ns
Setup time with respect to RXCLK, applies to
both edges of the clock
3
4
tsu(RXCLK–RXD)
th(RXCLK–RXD)
3
ns
ns
Hold time with respect to RXCLK, applies to
both edges of the clock
2.5
7.13.2.2.1.2 FSIRX Switching Characteristics
NO.
PARAMETER
MIN
MAX
UNIT
RXCLK delay compensation at
RX_DLYLINE_CTRL[RXCLK_DLY]=31
1
td(RXCLK)
10
30
ns
RXD0 delay compensation at
RX_DLYLINE_CTRL[RXD0_DLY]=31
2
3
4
td(RXD0)
10
10
30
30
1
ns
ns
ns
RXD1 delay compensation
at RX_DLYLINE_CTRL[RXD1_DLY]=31
td(RXD1)
Incremental delay of each delay line element
for RXCLK, RXD0, and RXD1
td(DELAY_ELEMENT)
0.3
7.13.2.2.1.3 FSIRX Timing Diagram
1
2
FSIRXCLK
FSIRXD0
FSIRXD1
3
4
Figure 7-64. FSIRX Timings
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.13.2.3 SPI Signaling Mode
The FSI supports a SPI signaling mode to enable communication with programmable SPI devices. In this mode,
the FSI transmits its data in the same manner as a SPI in a single clock configuration mode. While the FSI is
able to physically interface with a SPI in this mode, the external device must be able to encode and decode an
FSI frame to communicate successfully. This is because the FSI transmits all SPI frame phases with the
exception of the preamble and postamble. The FSI provides the same data validation and frame checking as if it
was in standard FSI mode, allowing for more robust communication without consuming CPU cycles. The
external SPI is required to send all relevant information and can access standard FSI features such as the ping
frame watchdog on the FSIRX, frame tagging, or custom CRC values. The list of features of the SPI signaling
mode follows:
•
•
•
Data will transmit on rising edge and receive on falling edge of the clock.
Only 16-bit word size is supported.
TXD1 will be driven like an active-low chip-select signal. The signal will be low for the duration of the full
frame transmission.
•
•
•
No receiver chip-select input is required. RXD1 is not used. Data is shifted into the receiver on every active
clock edge.
No preamble or postamble clocks will be transmitted. All signals return to the idle state after the frame phase
is finished.
It is not possible to transmit in the SPI slave configuration because the FSI TXCLK cannot take an external
clock source.
7.13.2.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
Section 7.13.2.3.1.1 lists the FSITX SPI signaling mode switching characteristics. Figure 7-65 shows the FSITX
SPI signaling mode timings. Special timings are not required for the FSIRX in SPI signaling mode. FSIRX
timings listed in Section 7.13.2.2.1.1 are applicable in the SPI signaling mode. Setup and Hold times are only
valid on the falling edge of FSIRXCLK because this is the active edge in SPI signaling mode.
7.13.2.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
NO.
PARAMETER
MIN
20
MAX
UNIT
ns
1
tc(TXCLK)
Cycle time, TXCLK
2
tw(TXCLK)
Pulse width, TXCLK low or TXCLK high
Delay time, TXD0 valid after TXCLK high
Delay time, TXCLK high after TXD1 low
Delay time, TXD1 high after TXCLK low
(0.5tc(TXCLK)) – 1
(0.5tc(TXCLK)) + 1
3
ns
3
td(TXCLKH–TXD0)
td(TXD1-TXCLK)
td(TXCLK-TXD1)
ns
4
tw(TXCLK) – 3
tw(TXCLK) – 2
ns
5
ns
7.13.2.3.1.2 FSITX SPI Signaling Mode Timings
1
2
FSITXCLK
3
FSITXD0
5
4
FSITXD1
Figure 7-65. FSITX SPI Signaling Mode Timings
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.13.3 Inter-Integrated Circuit (I2C)
The I2C module has the following features:
•
Compliance with the NXP™ Semiconductors I2C bus specification (version 2.1):
– Support for 8-bit format transfers
– 7-bit and 10-bit addressing modes
– General call
– START byte mode
– Support for multiple master-transmitters and slave-receivers
– Support for multiple slave-transmitters and master-receivers
– Combined master transmit/receive and receive/transmit mode
– Data transfer rate from 10 kbps up to 400 kbps (Fast-mode)
Receive FIFO and Transmitter FIFO (16-deep x 8-bit FIFO)
Supports two ePIE interrupts:
•
•
– I2Cx Interrupt – Any of the below events can be configured to generate an I2Cx interrupt:
•
•
•
•
•
•
•
Transmit-data ready
Receive-data ready
Register-access ready
No-acknowledgment received
Arbitration lost
Stop condition detected
Addressed as slave
– I2Cx_FIFO interrupts:
•
•
Transmit FIFO interrupt
Receive FIFO interrupt
•
•
Module enable/disable capability
Free data format mode
Figure 7-66 shows the I2C block diagram.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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I2C module
I2CXSR
I2CDXR
TX FIFO
RX FIFO
FIFO Interrupt
to CPU/PIE
SDA
Peripheral bus
I2CRSR
I2CDRR
Control/status
registers
CPU
Clock
synchronizer
SCL
Prescaler
Noise filters
Arbitrator
Interrupt to
CPU/PIE
I2C INT
Figure 7-66. I2C Module Conceptual Block Diagram
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7.13.3.1 I2C Electrical Data and Timing
Section 7.13.3.1.1 lists the I2C timing requirements. Section 7.13.3.1.2 lists the I2C switching characteristics.
Figure 7-67 shows the I2C timing diagram.
Note
To meet all of the I2C protocol timing specifications, the I2C module clock (Fmod) must be configured
from 7 MHz to 12 MHz.
7.13.3.1.1 I2C Timing Requirements
NO.
MIN
MAX
UNIT
Standard mode
T0
T1
fmod
I2C module frequency
7
12
MHz
µs
Hold time, START condition, SCL fall delay after
SDA fall
th(SDA-SCL)START
4.0
Setup time, Repeated START, SCL rise before SDA
fall delay
T2
tsu(SCL-SDA)START
4.7
µs
T3
T4
T5
T6
T7
T8
th(SCL-DAT)
tsu(DAT-SCL)
tr(SDA)
Hold time, data after SCL fall
Setup time, data before SCL rise
Rise time, SDA
0
µs
ns
ns
ns
ns
ns
250
1000
1000
300
tr(SCL)
Rise time, SCL
tf(SDA)
Fall time, SDA
tf(SCL)
Fall time, SCL
300
Setup time, STOP condition, SCL rise before SDA
rise delay
T9
tsu(SCL-SDA)STOP
4.0
0
µs
Pulse duration of spikes that will be suppressed by
filter
T10
tw(SP)
Cb
50
ns
T11
capacitance load on each bus line
400
pF
Fast mode
T0
fmod
I2C module frequency
7
12
MHz
µs
Hold time, START condition, SCL fall delay after
SDA fall
T1
T2
th(SDA-SCL)START
0.6
Setup time, Repeated START, SCL rise before SDA
fall delay
tsu(SCL-SDA)START
0.6
µs
T3
T4
T5
T6
T7
T8
th(SCL-DAT)
tsu(DAT-SCL)
tr(SDA)
Hold time, data after SCL fall
Setup time, data before SCL rise
Rise time, SDA
0
100
20
µs
ns
ns
ns
ns
ns
300
300
300
300
tr(SCL)
Rise time, SCL
20
tf(SDA)
Fall time, SDA
11.4
11.4
tf(SCL)
Fall time, SCL
Setup time, STOP condition, SCL rise before SDA
rise delay
T9
tsu(SCL-SDA)STOP
0.6
0
µs
Pulse duration of spikes that will be suppressed by
filter
T10
T11
tw(SP)
Cb
50
ns
capacitance load on each bus line
400
pF
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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7.13.3.1.2 I2C Switching Characteristics
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER
TEST CONDITIONS
0.1 Vbus < Vi < 0.9 Vbus
0.1 Vbus < Vi < 0.9 Vbus
MIN
MAX UNIT
Standard mode
S1
S2
S3
S4
fSCL
SCL clock frequency
0
10
100
kHz
µs
TSCL
SCL clock period
tw(SCLL)
tw(SCLH)
Pulse duration, SCL clock low
Pulse duration, SCL clock high
4.7
4.0
µs
µs
Bus free time between STOP and START
conditions
S5
tBUF
4.7
µs
S6
S7
S8
tv(SCL-DAT)
tv(SCL-ACK)
II
Valid time, data after SCL fall
Valid time, Acknowledge after SCL fall
Input current on pins
3.45
3.45
10
µs
µs
µA
–10
Fast mode
S1
S2
S3
S4
fSCL
SCL clock frequency
0
2.5
1.3
0.6
400
kHz
µs
TSCL
SCL clock period
tw(SCLL)
tw(SCLH)
Pulse duration, SCL clock low
Pulse duration, SCL clock high
µs
µs
Bus free time between STOP and START
conditions
S5
tBUF
1.3
µs
S6
S7
S8
tv(SCL-DAT)
tv(SCL-ACK)
II
Valid time, data after SCL fall
Valid time, Acknowledge after SCL fall
Input current on pins
0.9
0.9
10
µs
µs
µA
–10
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.13.3.1.3 I2C Timing Diagram
STOP
START
SDA
SCL
ACK
Contd...
Contd...
S7
S6
T10
T5
T7
S3
S4
9th
clock
T6
T8
S2
Repeated
START
STOP
S5
SDA
ACK
T2
T9
T1
SCL
9th
clock
Figure 7-67. I2C Timing Diagram
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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7.13.4 Multichannel Buffered Serial Port (McBSP)
The McBSPs feature:
•
•
•
•
•
•
•
Full-duplex communication
Double-buffered transmission and triple-buffered reception, allowing a continuous data stream
Independent clocking and framing for reception and transmission
The capability to send interrupts to the CPU and to send DMA events to the DMA controller
128 channels for transmission and reception
Multichannel selection modes that enable or disable block transfers in each of the channels
Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially connected A/D
and D/A devices
•
•
Support for external generation of clock signals and frame-synchronization signals
A programmable sample rate generator for internal generation and control of clock signals and frame-
synchronization signals
•
•
Programmable polarity for frame-synchronization pulses and clock signals
Direct interface to:
– T1/E1 framers
– IOM-2 compliant devices
– AC97-compliant devices (the necessary multiphase frame capability is provided)
– I2S compliant devices
– SPI devices
•
A wide selection of data sizes: 8, 12, 16, 20, 24, and 32 bits
Note
A value of the chosen data size is referred to as a serial word or word throughout the McBSP
documentation. Elsewhere, word is used to describe a 16-bit value.
•
•
•
•
μ-law and A-law companding
The option of transmitting/receiving 8-bit data with the LSB first
Status bits for flagging exception/error conditions
ABIS mode is not supported
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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Figure 7-68 shows the block diagram of the McBSP module.
TX
Interrupt
MXINT
CPU
Peripheral Write Bus
TX Interrupt Logic
To CPU
16
16
McBSP Transmit
Interrupt Select Logic
DXR2 Transmit Buffer
DXR1 Transmit Buffer
16
PERx.LSPCLK
MFSXx
16
MCLKXx
Compand Logic
XSR2
XSR1
MDXx
MDRx
RSR1
16
RSR2
16
CPU
DMA Bus
MCLKRx
Expand Logic
MFSRx
RBR2 Register
16
RBR1 Register
16
DRR2 Receive Buffer
DRR1 Receive Buffer
McBSP Receive
Interrupt Select Logic
16
16
RX
Interrupt
RX Interrupt Logic
MRINT
CPU
Peripheral Read Bus
To CPU
Figure 7-68. McBSP Block Diagram
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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7.13.4.1 McBSP Electrical Data and Timing
7.13.4.1.1 McBSP Transmit and Receive Timing
Section 7.13.4.1.1.1 lists the McBSP timing requirements:
•
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the
timing references of that signal are also inverted.
•
2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux. CLKG = CLKSRG / (1 + CLKGDV).
CLKSRG can be LSPCLK, CLKX, CLKR as source. CLKSRG ≤ (SYSCLK/2).
Section 7.13.4.1.1.2 lists the McBSP switching characteristics:
•
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the
timing references of that signal are also inverted.
•
2P = 1/CLKG in ns.
Figure 7-69 and Figure 7-70 show the McBSP timing diagrams.
7.13.4.1.1.1 McBSP Timing Requirements
NO.
MIN
MAX UNIT
1
kHz
McBSP module clock (CLKG, CLKX, CLKR) range
McBSP module cycle time (CLKG, CLKX, CLKR) range
25
1
MHz
ns
40
ms
ns
M11 tc(CKRX)
M12 tw(CKRX)
M13 tr(CKRX)
M14 tf(CKRX)
Cycle time, CLKR/X
CLKR/X ext
CLKR/X ext
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
2P
Pulse duration, CLKR/X high or CLKR/X low
Rise time, CLKR/X
P – 7
ns
7
7
ns
Fall time, CLKR/X
ns
21
2
M15 tsu(FRH-CKRL)
M16 th(CKRL-FRH)
M17 tsu(DRV-CKRL)
M18 th(CKRL-DRV)
M19 tsu(FXH-CKXL)
M20 th(CKXL-FXH)
Setup time, external FSR high before CLKR low
Hold time, external FSR high after CLKR low
Setup time, DR valid before CLKR low
ns
ns
ns
ns
ns
ns
0
6
21
5
0
Hold time, DR valid after CLKR low
3
21
2
Setup time, external FSX high before CLKX low
Hold time, external FSX high after CLKX low
CLKX ext
CLKX int
0
CLKX ext
6
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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7.13.4.1.1.2 McBSP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
NO.
M1
M2
M3
PARAMETER
MIN
MAX UNIT
tc(CKRX)
Cycle time, CLKR/X
CLKR/X int
CLKR/X int
CLKR/X int
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
2P
ns
tw(CKRXH)
tw(CKRXL)
Pulse duration, CLKR/X high
Pulse duration, CLKR/X low
D – 5 (1)
D + 5 (1)
ns
ns
C – 5 (1)
C + 5 (1)
–3
3
4
27
4
M4
M5
M6
td(CKRH-FRV)
td(CKXH-FXV)
tdis(CKXH-DXHZ)
Delay time, CLKR high to internal FSR valid
Delay time, CLKX high to internal FSX valid
ns
ns
ns
–3
3
27
8
–8
4
Disable time, CLKX high to DX high impedance
following last data bit
25
5
Delay time, CLKX high to DX valid.
–3
This applies to all bits except the first bit
transmitted.
CLKX ext
7
25
CLKX int
CLKX ext
CLKX int
–3
7
5
25
Delay time, CLKX high to DX
DXENA = 0
valid
M7
td(CKXH-DXV)
ns
Only applies to first bit
P – 3
P + 5
transmitted when in Data
Delay 1 or 2 (XDATDLY=01b
DXENA = 1
CLKX ext
P + 7
P + 25
or 10b) modes
CLKX int
CLKX ext
CLKX int
–8
5
Enable time, CLKX high to
DXENA = 0
DX driven
Only applies to first bit
P – 8
M8
M9
ten(CKXH-DX)
ns
ns
ns
transmitted when in Data
Delay 1 or 2 (XDATDLY=01b
DXENA = 1
CLKX ext
P + 5
or 10b) modes
FSX int
FSX ext
FSX int
8
18.5
Delay time, FSX high to DX
DXENA = 0
valid
Only applies to first bit
P + 8
td(FXH-DXV)
transmitted when in Data
Delay 0 (XDATDLY=00b)
DXENA = 1
FSX ext
P + 18.5
mode.
FSX int
FSX ext
FSX int
–2
6
Enable time, FSX high to DX
DXENA = 0
driven
Only applies to first bit
P – 2
M10 ten(FXH-DX)
transmitted when in Data
Delay 0 (XDATDLY=00b)
DXENA = 1
FSX ext
P + 6
mode
(1) C = CLKRX low pulse width = P
D = CLKRX high pulse width = P
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.13.4.1.1.3 McBSP Receive and Transmit Timing Diagrams
M1, M11
M2, M12
M3, M12
M13
CLKR
M4
M4
M14
FSR (int)
M15
M16
FSR (ext)
M18
M17
DR
(RDATDLY=00b)
Bit (n−1)
M17
(n−2)
(n−3)
(n−2)
(n−4)
M18
DR
(RDATDLY=01b)
Bit (n−1)
(n−3)
(n−2)
M17
M18
DR
(RDATDLY=10b)
Bit (n−1)
Figure 7-69. McBSP Receive Timing
M1, M11
M2, M12
M13
M3, M12
CLKX
FSX (int)
FSX (ext)
DX
M5
M5
M19
M20
M9
M7
M7
M10
Bit 0
Bit (n−1)
(n−2)
(n−3)
(n−2)
(XDATDLY=00b)
M8
DX
(XDATDLY=01b)
Bit (n−1)
M8
Bit 0
M6
M7
DX
(XDATDLY=10b)
Bit 0
Bit (n−1)
Figure 7-70. McBSP Transmit Timing
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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7.13.4.1.2 McBSP as SPI Master or Slave Timing
Section 7.13.4.1.2.1 lists the McBSP as SPI master timing requirements. Section 7.13.4.1.2.2 lists the McBSP as
SPI master switching characteristics. Section 7.13.4.1.2.3 lists the McBSP as SPI slave timing requirements.
Section 7.13.4.1.2.4 lists the McBSP as SPI slave switching characteristics.
Figure 7-71 through Figure 7-74 show the McBSP as SPI master or slave timing diagrams.
7.13.4.1.2.1 McBSP as SPI Master Timing Requirements
NO.
MIN
MAX
UNIT
CLOCK
tc(CLKG)
P
Cycle time, CLKG(1)
2 * tc(LSPCLK)
tc(LSPCLK)
ns
ns
Cycle time, LSPCLK(1)
M33,
M42,
M52,
M61
tc(CKX)
Cycle time, CLKX
2P
ns
CLKSTP = 10b, CLKXP = 0
M30
M31
tsu(DRV-CKXL)
th(CKXL-DRV)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
30
1
ns
ns
CLKSTP = 11b, CLKXP = 0
M39
M40
tsu(DRV-CKXH)
th(CKXH-DRV)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
30
1
ns
ns
CLKSTP = 10b, CLKXP = 1
M49
M50
tsu(DRV-CKXH)
th(CKXH-DRV)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
30
1
ns
ns
CLKSTP = 11b, CLKXP = 1
M58
M59
tsu(DRV-CKXL)
th(CKXL-DRV)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
30
1
ns
ns
(1) CLKG should be configured to LSPCLK/2 by setting CLKSM = 1 and CLKGDV = 1
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.13.4.1.2.2 McBSP as SPI Master Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
NO.
CLOCK
M33
PARAMETER
MIN
TYP
MAX
UNIT
tc(CLKG)
Cycle time, CLKG(1) (n * tc(LSPCLK)
Half CLKG cycle; 0.5 * tc(CLKG)
LSPCLK to CLKG divider
)
40
20
2
ns
ns
ns
P
n
CLKSTP = 10b, CLKXP = 0
M24
M25
M26
th(CKXL-FXL)
td(FXL-CKXH)
td(CLKXH-DXV)
Hold time, FSX high after CLKX low
Delay time, FSX low to CLKX high
Delay time, CLKX high to DX valid
2P – 4
P - 4
–3
ns
ns
ns
5
Disable time, DX high impedance following last data bit from
CLKX low
M28
M29
tdis(FXH-DXHZ)
td(FXL-DXV)
P – 8
P – 3
ns
ns
Delay time, FSX low to DX valid
P + 6
CLKSTP = 11b, CLKXP = 0
M34
M35
M36
th(CKXL-FXH)
td(FXL-CKXH)
td(CLKXL-DXV)
Hold time, FSX high after CLKX low
Delay time, FSX low to CLKX high
Delay time, CLKX low to DX valid
P – 4
2P – 4
–3
ns
ns
ns
5
5
Disable time, DX high impedance following last data bit from
CLKX low
M37
M38
tdis(CKXL-DXHZ)
td(FXL-DXV)
P – 8
–3
ns
ns
Delay time, FSX low to DX valid
CLKSTP = 10b, CLKXP = 1
M43
M44
M45
th(CKXH-FXH)
td(FXL-CKXL)
td(CLKXL-DXV)
Hold time, FSX high after CLKX high
Delay time, FSX low to CLKX low
Delay time, CLKX low to DX valid
2P – 4
P – 4
–3
ns
ns
ns
5
5
Disable time, DX high impedance following last data bit from
CLKX high
M47
M48
tdis(CKXH-DXHZ)
td(FXL-DXV)
P – 8
–3
ns
ns
Delay time, FSX low to DX valid
CLKSTP = 11b, CLKXP = 1
M53
M54
M55
th(CKXH-FXH)
td(FXL-CKXL)
td(CLKXH-DXV)
Hold time, FSX high after CLKX high
Delay time, FSX low to CLKX low
Delay time, CLKX high to DX valid
P – 4
2P – 4
–3
ns
ns
ns
5
5
Disable time, DX high impedance following last data bit from
CLKX high
M56
M57
tdis(CKXH-DXHZ)
td(FXL-DXV)
P – 8
–3
ns
ns
Delay time, FSX low to DX valid
(1) CLKG should be configured to LSPCLK/2 by setting CLKSM = 1 and CLKGDV = 1.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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7.13.4.1.2.3 McBSP as SPI Slave Timing Requirements
NO.
MIN
MAX
UNIT
CLOCK
tc(CLKG)
P
Cycle time, CLKG(1)
2 * tc(LSPCLK)
tc(LSPCLK)
ns
ns
Cycle time, LSPCLK(1)
M33,
M42,
M52,
M61
tc(CKX)
Cycle time, CLKX(2)
16P
ns
CLKSTP = 10b, CLKXP = 0
M30
M31
M32
tsu(DRV-CKXL)
th(CKXL-DRV)
tsu(BFXL-CKXH)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
Setup time, FSX low before CLKX high
8P – 10
8P – 10
8P+10
ns
ns
ns
CLKSTP = 11b, CLKXP = 0
M39
M40
M41
tsu(DRV-CKXH)
th(CKXH-DRV)
tsu(FXL-CKXH)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
Setup time, FSX low before CLKX high
8P – 10
8P – 10
16P+10
ns
ns
ns
CLKSTP = 10b, CLKXP = 1
M49
M50
M51
tsu(DRV-CKXH)
th(CKXH-DRV)
tsu(FXL-CKXL)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
Setup time, FSX low before CLKX low
8P – 10
8P – 10
8P+10
ns
ns
ns
CLKSTP = 11b, CLKXP = 1
M58
M59
M60
tsu(DRV-CKXL)
th(CKXL-DRV)
tsu(FXL-CKXL)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
Setup time, FSX low before CLKX low
8P – 10
8P – 10
16P+10
ns
ns
ns
(1) CLKG should be configured to LSPCLK/2 by setting CLKSM = 1 and CLKGDV = 1
(2) For SPI slave modes CLKX must be a minimum of 8 CLKG cycles
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.13.4.1.2.4 McBSP as SPI Slave Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
NO.
PARAMETER
MIN
TYP
MAX
UNIT
CLOCK
2P
CLKSTP = 10b, CLKXP = 0
Cycle time, CLKG
ns
M26
M28
M29
td(CLKXH-DXV)
tdis(CKXL-DXHZ)
td(FXL-DXV)
Delay time, CLKX high to DX valid
3P+6
6P+6
5P+20
5P+20
5P+20
5P + 20
ns
ns
ns
Disable time, DX high impedance following last data bit from
CLKX low
Delay time, FSX low to DX valid
4P + 6
CLKSTP = 11b, CLKXP = 0
M36
M37
M38
td(CLKXL-DXV)
tdis(CKXL-DXHZ)
td(FXL-DXV)
Delay time, CLKX low to DX valid
3P+6
7P+6
ns
ns
ns
Disable time, DX high impedance following last data bit from
CLKX low
Delay time, FSX low to DX valid
4P + 6
CLKSTP = 10b, CLKXP = 1
M45
M47
M48
td(CLKXL-DXV)
tdis(CLKXH-DXHZ)
td(FXL-DXV)
Delay time, CLKX low to DX valid
3P+6
6P+6
ns
ns
ns
Disable time, DX high impedance following last data bit from
CLKX high
Delay time, FSX low to DX valid
4P + 6
CLKSTP = 11b, CLKXP = 1
M55
M56
M57
td(CLKXH-DXV)
tdis(CKXH-DXHZ)
td(FXL-DXV)
Delay time, CLKX high to DX valid
3P+6
7P + 6
4P + 6
ns
ns
ns
Disable time, DX high impedance following last data bit from
CLKX high
Delay time, FSX low to DX valid
7.13.4.1.2.5 McBSP as SPI Master or Slave Timing Diagrams
M33
M32
MSB
LSB
CLKX
M25
M24
FSX
M26
M29
M28
DX
DR
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
M31
(n-2)
(n-3)
(n-4)
M30
Bit 0
(n-3)
(n-4)
Figure 7-71. McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
M42
MSB
M41
LSB
CLKX
FSX
DX
M35
M34
M36
(n-2)
M40
(n-2)
M37
M38
Bit 0
Bit(n-1)
Bit(n-1)
(n-3)
(n-4)
M39
DR
Bit 0
(n-3)
(n-4)
Figure 7-72. McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
M52
M51
MSB
LSB
CLKX
FSX
M43
M44
M48
M47
M45
DX
DR
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
M49
M50
(n-2)
Bit 0
(n-3)
(n-4)
Figure 7-73. McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
M61
M60
MSB
M54
LSB
CLKX
FSX
DX
M53
M56
M55
M57
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
M58
M59
(n-2)
DR
Bit 0
Bit(n-1)
(n-3)
(n-4)
Figure 7-74. McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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7.13.5 Power Management Bus (PMBus)
The PMBus module provides an interface between the microcontroller and devices compliant with the SMI
Forum PMBus Specification Part I version 1.0 and Part II version 1.1. PMBus is based on SMBus, which uses a
similar physical layer to I2C.
The PMBus module has the following features:
•
•
•
Compliance with the SMI Forum PMBus Specification (Part I v1.0 and Part II v1.1)
Support for master and slave modes
Support for two speeds:
– Standard Mode: Up to 100 kHz
– Fast Mode: Up to 400 kHz
Packet error checking
CONTROL and ALERT signals
Clock high and low time-outs
Four-byte transmit and receive buffers
One maskable interrupt, which can be generated by several conditions:
– Receive data ready
•
•
•
•
•
– Transmit buffer empty
– Slave address received
– End of message
– ALERT input asserted
– Clock low time-out
– Clock high time-out
– Bus free
Figure 7-75 shows the PMBus block diagram.
PCLKCR20
SYSCLK
PMBCTRL
Div
ALERT
CTL
DMA
CPU
PIE
Bit clock
Other registers
GPIO Mux
PMBTXBUF
SCL
Shift register
PMBRXBUF
SDA
PMBUSA_INT
PMBus Module
Figure 7-75. PMBus Block Diagram
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
7.13.5.1 PMBus Electrical Data and Timing
Section 7.13.5.1.1 lists the PMBus electrical characteristics. Section 7.13.5.1.2 lists the PMBus fast mode
switching characteristics. Section 7.13.5.1.3 lists the PMBus standard mode switching characteristics.
7.13.5.1.1 PMBus Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.8
UNIT
V
VIL
VIH
VOL
IOL
Valid low-level input voltage
Valid high-level input voltage
Low-level output voltage
Low-level output current
2.1
VDDIO
0.4
V
At Ipullup = 4 mA
V
VOL ≤ 0.4 V
4
0
mA
Pulse width of spikes that must be
suppressed by the input filter
tSP
50
ns
Ii
Input leakage current on each pin
Capacitance on each pin
0.1 Vbus < Vi < 0.9 Vbus
–10
10
10
µA
pF
Ci
7.13.5.1.2 PMBus Fast Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fSCL
tBUF
SCL clock frequency
10
400
kHz
Bus free time between STOP and
START conditions
1.3
0.6
0.6
0.6
µs
µs
µs
µs
START condition hold time -- SDA fall
to SCL fall delay
tHD;STA
tSU;STA
tSU;STO
Repeated START setup time -- SCL
rise to SDA fall delay
STOP condition setup time -- SCL rise
to SDA rise delay
tHD;DAT
tSU;DAT
tTimeout
tLOW
Data hold time after SCL fall
Data setup time before SCL rise
Clock low time-out
300
100
25
ns
ns
ms
µs
µs
35
Low period of the SCL clock
High period of the SCL clock
1.3
0.6
tHIGH
50
25
Cumulative clock low extend time
(slave device)
tLOW;SEXT
tLOW;MEXT
From START to STOP
Within each byte
ms
ms
Cumulative clock low extend time
(master device)
10
tr
tf
Rise time of SDA and SCL
Fall time of SDA and SCL
5% to 95%
95% to 5%
20
20
300
300
ns
ns
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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7.13.5.1.3 PMBus Standard Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fSCL
tBUF
SCL clock frequency
10
100
kHz
Bus free time between STOP and
START conditions
4.7
4
µs
µs
µs
µs
START condition hold time -- SDA fall
to SCL fall delay
tHD;STA
tSU;STA
tSU;STO
Repeated START setup time -- SCL
rise to SDA fall delay
4.7
4
STOP condition setup time -- SCL rise
to SDA rise delay
tHD;DAT
tSU;DAT
tTimeout
tLOW
Data hold time after SCL fall
Data setup time before SCL rise
Clock low time-out
300
250
25
ns
ns
ms
µs
µs
35
Low period of the SCL clock
High period of the SCL clock
4.7
4
tHIGH
50
25
Cumulative clock low extend time
(slave device)
tLOW;SEXT
tLOW;MEXT
From START to STOP
Within each byte
ms
ms
Cumulative clock low extend time
(master device)
10
tr
tf
Rise time of SDA and SCL
Fall time of SDA and SCL
1000
300
ns
ns
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
7.13.6 Serial Communications Interface (SCI)
The SCI is a 2-wire asynchronous serial port, commonly known as a UART. The SCI module supports digital
communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero
(NRZ) format
The SCI receiver and transmitter each have a 16-level-deep FIFO for reducing servicing overhead, and each has
its own separate enable and interrupt bits. Both can be operated independently for half-duplex communication,
or simultaneously for full-duplex communication. To specify data integrity, the SCI checks received data for break
detection, parity, overrun, and framing errors. The bit rate is programmable to different speeds through a 16-bit
baud-select register. Figure 7-76 shows the SCI block diagram.
Features of the SCI module include:
•
Two external pins:
– SCITXD: SCI transmit-output pin
– SCIRXD: SCI receive-input pin
– Baud rate programmable to 64K different rates
Data-word format
•
– One start bit
– Data-word length programmable from 1 to 8 bits
– Optional even/odd/no parity bit
– 1 or 2 stop bits
•
•
•
•
•
Four error-detection flags: parity, overrun, framing, and break detection
Two wakeup multiprocessor modes: idle-line and address bit
Half- or full-duplex operation
Double-buffered receive and transmit functions
Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with
status flags.
– Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY
flag (transmitter-shift register is empty)
– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (break
condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
Separate enable bits for transmitter and receiver interrupts (except BRKDT)
NRZ format
Auto baud-detect hardware logic
16-level transmit and receive FIFO
•
•
•
•
Note
All registers in this module are 8-bit registers. When a register is accessed, the register data is in the
lower byte (bits 7–0), and the upper byte (bits 15–8) is read as zeros. Writing to the upper byte has no
effect.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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TXENA
SCICTL1.1
TXSHF
Register
SCITXD
Frame
Format and Mode
8
Parity
Even/Odd
SCICCR.6
TXEMPTY
SCICTL2.6
0
1
8
Enable
TX FIFO_0
TX FIFO_1
TXINT
To CPU
SCICCR.5
TX Interrupt
Logic
TX FIFO Interrupts
8
TX FIFO_N
TXINTENA
SCICTL2.0
TXRDY
8
1
0
TXWAKE
SCICTL2.7
SCICTL1.3
SCI TX Interrupt Select Logic
8
WUT
Transmit Data
Buffer Register
SCITXBUF.7-0
Auto Baud Detect Logic
RXENA
Baud Rate
MSB/LSB
Registers
SCICTL1.0
LSPCLK
RXSHF
Register
SCIRXD
SCIHBAUD.15-8
SCILBAUD.7-0
RXWAKE
8
SCIRXST.1
0
1
8
SCIFFENA
SCIFFTX.14
RX FIFO_0
RX FIFO_1
RXINT
To CPU
8
RX FIFO Interrupts
RX Interrupt
Logic
RX FIFO_N
RXFFOVF
8
1
SCIFFRX.15
0
RXBKINTENA
SCICTL2.1
RXRDY
SCIRXST.6
RXENA
BRKDT
RXERRINTENA
SCICTL1.6
SCICTL1.0
SCIRXST.5
SCI RX Interrupt Select Logic
8
SCIRXST.5-2
BRKDT FE OE PE
RXERROR
Receive Data
Buffer Register
SCIRXBUF.7-0
SCIRXST.7
Figure 7-76. SCI Block Diagram
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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7.13.7 Serial Peripheral Interface (SPI)
The SPI is a high-speed synchronous serial input/output (I/O) port that allows a serial bit stream of programmed
length (1 to 16 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The SPI is
normally used for communications between the microcontroller and external peripherals or another controller.
Typical applications include external I/O or peripheral expansion through devices such as shift registers, display
drivers, and ADCs. Multidevice communications are supported by the master/slave operation of the SPI. The
port supports 16-level receive and transmit FIFOs for reducing CPU servicing overhead.
The SPI module features include:
•
•
•
•
•
•
•
•
SPISOMI: SPI slave-output/master-input pin
SPISIMO: SPI slave-input/master-output pin
SPISTE: SPI slave transmit-enable pin
SPICLK: SPI serial-clock pin
Two operational modes: master and slave
Baud rate: 125 different programmable rates
Data word length: 1 to 16 data bits
Four clocking schemes (controlled by clock polarity and clock phase bits) include:
– Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling
edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the rising
edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
Simultaneous receive-and-transmit operation (transmit function can be disabled in software)
Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms.
16-level transmit and receive FIFO
Delayed transmit control
3-wire SPI mode
SPISTE inversion for digital audio interface receive mode on devices with two SPI modules
DMA support
High-speed mode for up to 50-MHz full-duplex communication
•
•
•
•
•
•
•
•
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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Figure 7-77 shows the SPI CPU Interface.
PCLKCR8
Low-Speed
LSPCLK
Prescaler
SYSCLK
CPU
Bit
Clock
SYSRS
SPISIMO
SPISOMI
GPIO
SPI
SPIINT
SPITXINT
SPICLK
SPISTE
MUX
PIE
SPIRXDMA
SPITXDMA
DMA
Figure 7-77. SPI CPU Interface
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
7.13.7.1 SPI Electrical Data and Timing
Note
All timing parameters for SPI High-Speed Mode assume a load capacitance of 5 pF on SPICLK,
SPISIMO, and SPISOMI.
For more information about the SPI in High-Speed mode, see the Serial Peripheral Interface (SPI) chapter of the
TMS320F2838x Real-Time Microcontrollers Technical Reference Manual.
To use the SPI in High-Speed mode, the application must use the high-speed enabled GPIOs (see Section
6.5.5).
7.13.7.1.1 SPI Master Mode Timings
Section 7.13.7.1.1.1 lists the SPI master mode timing requirements. Section 7.13.7.1.1.2 lists the SPI master
mode switching characteristics (clock phase = 0). Section 7.13.7.1.1.3 lists the SPI master mode switching
characteristics (clock phase = 1). Figure 7-78 shows the SPI master mode external timing where the clock phase
= 0. Figure 7-79 shows the SPI master mode external timing where the clock phase = 1.
7.13.7.1.1.1 SPI Master Mode Timing Requirements
(BRR + 1)
NO.
MIN
MAX UNIT
CONDITION(1)
High-Speed Mode
8
9
tsu(SOMI)M
th(SOMI)M
Setup time, SPISOMI valid before SPICLK
Hold time, SPISOMI valid after SPICLK
Even, Odd
Even, Odd
1
5
ns
ns
Normal Mode
8
9
tsu(SOMI)M
th(SOMI)M
Setup time, SPISOMI valid before SPICLK
Hold time, SPISOMI valid after SPICLK
Even, Odd
Even, Odd
20
0
ns
ns
(1) The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR is
greater than 3.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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7.13.7.1.1.2 SPI Master Mode Switching Characteristics (Clock Phase = 0)
over recommended operating conditions (unless otherwise noted)
(BRR + 1)
NO.
PARAMETER
MIN
CONDITION(1)
General
Even
Odd
4tc(LSPCLK)
5tc(LSPCLK)
128tc(LSPCLK)
1
2
tc(SPC)M
Cycle time, SPICLK
ns
ns
127tc(LSPCLK)
Even
0.5tc(SPC)M – 1
0.5tc(SPC)M + 1
tw(SPC1)M
Pulse duration, SPICLK, first pulse
0.5tc(SPC)M +0.5tc(LSPCLK)
– 1
0.5tc(SPC)M +0.5tc(LSPCLK)
+ 1
Odd
Even
Odd
0.5tc(SPC)M – 1
0.5tc(SPC)M + 1
Pulse duration, SPICLK, second
pulse
3
tw(SPC2)M
ns
ns
ns
0.5tc(SPC)M –0.5tc(LSPCLK)
1.5tc(SPC)M –3tc(SYSCLK)
1.5tc(SPC)M –4tc(SYSCLK)
–
1
0.5tc(SPC)M –0.5tc(LSPCLK)
+ 1
–
3
1.5tc(SPC)M –3tc(SYSCLK)
+
3
Even
23 td(SPC)M
Delay time, SPISTE active to SPICLK
–
3
1.5tc(SPC)M –4tc(SYSCLK)
+
3
Odd
Even
Odd
0.5tc(SPC)M – 3
0.5tc(SPC)M + 3
Valid time, SPICLK to SPISTE
inactive
24 tv(STE)M
0.5tc(SPC)M –0.5tc(LSPCLK)
–
3
0.5tc(SPC)M –0.5tc(LSPCLK)
+ 3
High-Speed Mode
4
td(SIMO)M
Delay time, SPICLK to SPISIMO valid Even, Odd
1
5
ns
ns
Even
0.5tc(SPC)M – 1
Valid time, SPISIMO valid after
5
tv(SIMO)M
0.5tc(SPC)M –0.5tc(LSPCLK)
–
1
SPICLK
Odd
Normal Mode
4
td(SIMO)M
Delay time, SPICLK to SPISIMO valid Even, Odd
ns
ns
Even
0.5tc(SPC)M – 3
Valid time, SPISIMO valid after
5
tv(SIMO)M
0.5tc(SPC)M –0.5tc(LSPCLK)
–
3
SPICLK
Odd
(1) The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR is
greater than 3.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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7.13.7.1.1.3 SPI Master Mode Switching Characteristics (Clock Phase = 1)
over recommended operating conditions (unless otherwise noted)
(BRR + 1)
NO.
PARAMETER
MIN
MAX UNIT
CONDITION(1)
General
Even
Odd
4tc(LSPCLK)
5tc(LSPCLK)
128tc(LSPCLK)
1
2
tc(SPC)M
Cycle time, SPICLK
ns
ns
127tc(LSPCLK)
Even
0.5tc(SPC)M – 1
0.5tc(SPC)M + 1
Pulse duration, SPICLK, first
pulse
tw(SPCH)M
0.5tc(SPC)M
–
Odd
Even
Odd
0.5tc(SPC)M – 0.5tc(LSPCLK) – 1
0.5tc(SPC)M – 1
0.5tc(LSPCLK) + 1
0.5tc(SPC)M + 1
Pulse duration, SPICLK,
second pulse
3
tw(SPC2)M
ns
0.5tc(SPC)M
+
0.5tc(SPC)M + 0.5tc(LSPCLK) – 1
0.5tc(LSPCLK) + 1
Delay time, SPISTE valid to
SPICLK
2tc(SPC)M – 3tc(SYSCLK)
+
3
23 td(SPC)M
Even, Odd
2tc(SPC)M – 3tc(SYSCLK) – 3
ns
ns
Even
Odd
– 3
– 3
+3
+3
Valid time, SPICLK to SPISTE
invalid
24 tv(STE)M
High-Speed Mode
Even
Odd
0.5tc(SPC)M – 1
0.5tc(SPC)M + 0.5tc(LSPCLK) – 1
0.5tc(SPC)M – 1
Delay time, SPISIMO valid to
SPICLK
4
5
td(SIMO)M
ns
ns
Even
Odd
Valid time, SPISIMO valid after
SPICLK
tv(SIMO)M
0.5tc(SPC)M – 0.5tc(LSPCLK) – 1
Normal Mode
Even
Odd
0.5tc(SPC)M – 5
0.5tc(SPC)M + 0.5tc(LSPCLK) – 5
0.5tc(SPC)M – 3
Delay time, SPISIMO valid to
SPICLK
4
5
td(SIMO)M
ns
ns
Even
Odd
Valid time, SPISIMO valid after
SPICLK
tv(SIMO)M
0.5tc(SPC)M – 0.5tc(LSPCLK) – 3
(1) The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR is
greater than 3.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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7.13.7.1.1.4 SPI Master Mode External Timing
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISIMO
Master Out Data Is Valid
8
9
Master In Data
Must Be Valid
SPISOMI
SPISTE(A)
24
23
A. On the trailing end of the word, SPISTE will go inactive except between back-to-back transmit words in both FIFO and non-FIFO modes.
Figure 7-78. SPI Master Mode External Timing (Clock Phase = 0)
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISIMO
Master Out Data Is Valid
8
9
Master In Data Must
Be Valid
SPISOMI
SPISTE(A)
24
23
A. On the trailing end of the word, SPISTE will go inactive except between back-to-back transmit words in both FIFO and non-FIFO modes.
Figure 7-79. SPI Master Mode External Timing (Clock Phase = 1)
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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7.13.7.1.2 SPI Slave Mode Timings
Section 7.13.7.1.2.1 lists the SPI slave mode timing requirements. Section 7.13.7.1.2.2 lists the SPI slave mode
switching characteristics. Figure 7-80 shows the SPI slave mode external timing where the clock phase = 0.
Figure 7-81 shows the SPI slave mode external timing where the clock phase = 1.
7.13.7.1.2.1 SPI Slave Mode Timing Requirements
NO.
MIN
4tc(SYSCLK)
MAX UNIT
12 tc(SPC)S
13 tw(SPC1)S
14 tw(SPC2)S
19 tsu(SIMO)S
20 th(SIMO)S
Cycle time, SPICLK
ns
ns
ns
ns
ns
Pulse duration, SPICLK, first pulse
Pulse duration, SPICLK, second pulse
Setup time, SPISIMO valid before SPICLK
Hold time, SPISIMO valid after SPICLK
2tc(SYSCLK) – 1
2tc(SYSCLK) – 1
1.5tc(SYSCLK)
1.5tc(SYSCLK)
Setup time, SPISTE valid before
SPICLK (Clock Phase = 0)
2tc(SYSCLK) + 11
ns
25 tsu(STE)S
Setup time, SPISTE valid before
SPICLK (Clock Phase = 1)
2tc(SYSCLK) + 20
1.5tc(SYSCLK)
ns
ns
26 th(STE)S
Hold time, SPISTE invalid after SPICLK
7.13.7.1.2.2 SPI Slave Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER
MIN
0
MAX
UNIT
High-Speed Mode
15
16
td(SOMI)S
tv(SOMI)S
Delay time, SPICLK to SPISOMI valid
Valid time, SPISOMI valid after SPICLK
9
ns
ns
Normal Mode
15
16
td(SOMI)S
tv(SOMI)S
Delay time, SPICLK to SPISOMI valid
Valid time, SPISOMI valid after SPICLK
20
ns
ns
0
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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7.13.7.1.2.3 SPI Slave Mode External Timing
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
15
16
SPISOMI
SPISOMI Data Is Valid
19
20
SPISIMO Data
Must Be Valid
SPISIMO
SPISTE
25
26
Figure 7-80. SPI Slave Mode External Timing (Clock Phase = 0)
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
15
SPISOMI
SPISOMI Data Is Valid
Data Valid
Data Valid
16
19
20
SPISIMO Data
Must Be Valid
SPISIMO
SPISTE
26
25
Figure 7-81. SPI Slave Mode External Timing (Clock Phase = 1)
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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7.13.8 EtherCAT Slave Controller (ESC)
Ethernet for Control Automation Technology ( EtherCAT®) is an Ethernet-based fieldbus system, invented by
Beckhoff Automation and is standardized in IEC 61158. All the slave nodes connected to the bus interpret,
process, and modify the data addressed to them quickly, without having to buffer the frame inside the node. This
real-time behavior, frame processing, and forwarding requirements are implemented by the EtherCAT slave
controller (ESC) hardware. EtherCAT does not require software interaction for data transmission inside the
slaves. EtherCAT only defines the MAC layer while the higher-layer protocols and stack are implemented in
software on the microcontrollers connected to the ESC.
The EtherCAT:
•
Involves master and slave(s) setup where slave nodes are physically connected daisy-chain style but
logically operate on a loop
•
•
Specializes in precise, low-jitter synchronization across slave nodes
Uses IEEE 802.3 Ethernet physical layer and standard Ethernet frames
7.13.8.1 ESC Features
The ESC on this MCU provides the following functionality:
•
•
•
Up to 2 MII ports to connect to EtherCAT PHYs
Process data interface through 16-bit asynchronous interface
64-bit distributed clocking
– Sync output signals to synchronize device events and latch input signals supporting time-stamping for
events
– Distributed clock features of SYNC0/1 (o/ps) and LATCH0/1 able to synchronize GPIOs and allow inputs
from any GPIOs as well as other muxing options for internal device events
8 Field bus Memory Management Units (FMMUs)
•
– Support all native types of RD/, WR/, RDWR, and built-in features of bit- and byte-addressing
8 Sync Managers
I2C EEPROM interface
Up-to 32 general-purpose inputs (GPIs) and 32 general-purpose outputs (GPOs)
2 SYNC and 2 LATCH signals connected to GPIO pads
16KB RAM with parity
•
•
•
•
•
7.13.8.2 ESC Subsystem Integrated Features
In addition to the ESC features, the following are the device-specific features provided by the integration of the
ESC and the MCU:
•
•
•
•
•
•
•
ESC access allocation to either the CM subsystem or CPU1 subsystem during initialization
EtherCAT reset request from master can be routed to NMI or general interrupt controller on MCU
RAM Parity error routed to NMI on MCU
DMA access to EtherCAT RAM
Up to 32 GPIs and up to 32 GPOs feature integrated to 16-bit ASYNC PDI interface
Interface to CLB
Distributed clock feature of SYNC0/1 able to synchronize PWMs, generate interrupt/DMA requests, or trigger
eCAP capture to allow external component action through GPIO access.
EtherCAT SYNC0/1 pulse can trigger a CLA task.
•
•
Distributed clock feature of LATCH0/1 allows inputs from any GPIO or PWM crossbar triggers
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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7.13.8.3 EtherCAT IP Block Diagram
Figure 7-82 shows the general functionality of EtherCAT IP.
MII Ports towards
PHYs
PDI Bus, IRQ, / General
purpose IOs, WD trig
Clocks
(25,,100 MHz)
0
1
Misc.
Config.
Processing Unit
AutoForwarder
+
Loopback
PDI
PHY MDIO
Reset
PHY
Management
PDI Interface
ECAT Interface
Reset
Controller
SYNC
Distributed
clock
Proc.
Memory
Interface
LATCH
RAM
User
&
Process
8KB *2
PROM
Interface
EEPROM
Interface
FMMU
LED
Status
Indicators
Monitoring
Sync Manager
ESC Address Space
Registers
EtherCAT IP Core
Figure 7-82. EtherCAT IP Block Diagram
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.13.8.4 EtherCAT Electrical Data and Timing
Section 7.13.8.4.1 lists the EtherCAT timing requirements. Section 7.13.8.4.2 lists the EtherCAT switching
characteristics. Figure 7-83 through Figure 7-87 show the EtherCAT timing diagrams.
7.13.8.4.1 EtherCAT Timing Requirements
NO.
MIN
NOM
MAX UNIT
EtherCAT
tc(ECATCLK)
tc(TXCLK)
tw(TXCK)
tc(RXCK)
Cycle time, ECATCLK
10
40
ns
ns
MII1
MII2/MII3
MII4
Cycle time, ESC_TXy_CLK
Pulse duration, ESC_TXy_CLK high or low
Cycle time, ESC_RXy_CLK
16
24
24
ns
ns
ns
40
MII5/MII6
tw(RXCK)
Pulse duration, ESC_RXy_CLK high or low
16
10
2
Setup time, receive signals valid before ESC_RXy_CLK
high
MII8
MII9
tsu(RXDV-RXCKH)
th(RXCKH-RXDV)
ns
ns
Hold time, receive signals valid after ESC_RXy_CLK high
MDIO
Setup time, ESC_MDIO_DATA valid before
ESC_MDIO_CLK high
MDIO4
MDIO5
tsu(MDV-MCKH)
th(MCKH-MDV)
20
–1
ns
ns
Hold time, ESC_MDIO_DATA valid after ESC_MDIO_CLK
high
7.13.8.4.2 EtherCAT Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
NO.
PARAMETER
MIN
TYP
MAX UNIT
Auto Shift Compensation
Delay time, ESC_TXy_CLK to
ESC_TXy_DATA[3:0] and
ESC_TXy_ENA
20 + input_dly +
output_dly +
TX_SHIFT*tc(CLK_100)
30 + input_dly +
output_dly +
TX_SHIFT*tc(CLK_100)
MII7
td(TXCLK-TXDV)
ns
MDIO
MDIO1
tc(MCK)
Cycle time, ESC_MDIO_CLK
400
ns
ns
Pulse duration, ESC_MDIO_CLK
high or low
MDIO2/MDIO3 tw(MCK)
MDIO7 td(MCKH-MDV)
tv(MCKH-MDV)
160
240
Delay time, ESC_MDIO_CLK
high to ESC_MDIO_DATA valid
0.5tc(MCK) + 30
ns
ns
Valid time, ESC_MDIO_DATA
valid after ESC_MDIO_CLK high
0.5tc(MCK) – 3.0
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.13.8.4.3 EtherCAT Timing Diagrams
MII1
MII2
MII3
ESC_TXy_CLK
Figure 7-83. EtherCAT Transmit Clock Timing (MII Operation)
MII7
ESC_TXy_CLK (input)
ESC_TXy_DATA3–ESC_TXy_DATA0,
ESC_TXy_EN (outputs)
Figure 7-84. EtherCAT Transmit Interface Timing (MII Operation)
MII4
MII5
MII6
ESC_RXy_CLK
Figure 7-85. EtherCAT Receive Clock Timing (MII Operation)
MII8
MII9
ESC_RXy_CLK (input)
ESC_RXy_DATA3–ESC_RXy_DATA0,
ESC_RXy_DV, ESC_RXy_ERR (inputs)
Figure 7-86. EtherCAT Receive Interface Timing (MII Operation)
MDIO1
MDIO2
MDIO3
ESC_MDIO_CLK
MDIO4
MDIO5
ESC_MDIO_DATA (input)
MDIO7
ESC_MDIO_DATA (output)
Figure 7-87. EtherCAT MDIO Timing Diagrams
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.13.9 Universal Serial Bus (USB) Controller
The USB controller operates as a full-speed or low-speed function controller during point-to-point
communications with USB host or device functions.
The USB module has the following features:
•
•
•
•
USB 2.0 full-speed and low-speed operation
Integrated PHY
Three transfer types: control, interrupt, and bulk
32 endpoints
– One dedicated control IN endpoint and one dedicated control OUT endpoint
– 15 configurable IN endpoints and 15 configurable OUT endpoints
4KB of dedicated endpoint memory
•
Figure 7-88 shows the USB block diagram.
Endpoint Control
Transmit
Receive
EP0 –31
Control
CPU Interface
Interrupt
Control
Interrupts
CPU Bus
Host
Transaction
Scheduler
Combine
Endpoints
EP Reg.
Decoder
Common
Regs
UTM
Synchronization
Packet
Encode/Decode
FIFO RAM
Controller
Rx
Buff
Rx
Buff
Data Sync
Packet Encode
Packet Decode
CRC Gen/Check
Cycle
Control
Tx
Buff
Tx
Buff
HNP/SRP
USB FS/LS
PHY
FIFO
Decoder
Timers
Cycle Control
USB DataLines
D+ andD-
Figure 7-88. USB Block Diagram
Note
The accuracy of the on-chip zero-pin oscillator (Section 7.10.3.5.1, INTOSC Characteristics) will not
meet the accuracy requirements of the USB protocol. An external clock source must be used for
applications using USB. For applications using the USB boot mode, see Section 8.6 for clock
frequency requirements.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.13.9.1 USB Electrical Data and Timing
Section 7.13.9.1.1 lists the USB input ports DP and DM timing requirements. Section 7.13.9.1.2 lists the USB
output ports DP and DM switching characteristics.
7.13.9.1.1 USB Input Ports DP and DM Timing Requirements
MIN
0.8
MAX
UNIT
V
V(CM)
Z(IN)
VCRS
VIL
Differential input common mode range
Input impedance
2.5
300
1.3
kΩ
V
Crossover voltage
2.0
Static SE input logic-low level
Static SE input logic-high level
Differential input voltage
0.8
V
VIH
2.0
0.2
V
VDI
V
7.13.9.1.2 USB Output Ports DP and DM Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
D+, D– single-ended
D+, D– single-ended
D+, D– impedance
TEST CONDITIONS
MIN
MAX
UNIT
VOH
USB 2.0 load conditions
USB 2.0 load conditions
2.8
0
3.6
0.3
44
V
V
Ω
VOL
Z(DRV)
28
Full speed, differential, CL = 50 pF, 10%/90%,
Rpu on D+
tr
tf
Rise time
Fall time
4
4
20
20
ns
ns
Full speed, differential, CL = 50 pF, 10%/90%,
Rpu on D+
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.14 Connectivity Manager (CM) Peripherals
Note
For the actual number of each peripheral on a specific device, see the Device Comparison table.
7.14.1 Modular Controller Area Network (MCAN) [CAN FD]
The Controller Area Network (CAN) is a serial communications protocol that efficiently supports distributed real-
time control with a high level of security. CAN has high immunity to electrical interference and the ability to self-
diagnose and repair data errors. In a CAN network, many short messages are broadcasted to the entire network,
which provides data consistency in every node of the system.
The MCAN module supports both Classic CAN and CAN FD (CAN with flexible data-rate) specifications. The
CAN FD feature allows high throughput and increased payload per data frame. Classic CAN and CAN FD
devices can coexist on the same network without any conflict. The MCAN module is compliant to ISO
11898-1:2015.
The MCAN module implements the following features:
•
•
•
•
•
•
•
•
•
•
•
•
Conforms with CAN Protocol 2.0 A, B and ISO 11898-1:2015
Full CAN FD support (up to 64 data bytes)
AUTOSAR and SAE J1939 support
Up to 32 dedicated transmit buffers
Configurable transmit FIFO, up to 32 elements
Configurable transmit queue, up to 32 elements
Configurable transmit Event FIFO, up to 32 elements
Up to 64 dedicated receive buffers
Two configurable receive FIFOs, up to 64 elements each
Up to 128 filter elements
Loop-back mode for self-test
Maskable interrupt (two configurable interrupt lines, correctable ECC, counter overflow and clock stop/
wakeup)
•
•
•
•
•
Non-maskable interrupt (uncorrectable ECC)
Two clock domains (CAN clock/host clock)
ECC check for Message RAM
Clock stop and wakeup support
Timestamp counter
Non-supported features:
•
•
•
•
Host bus firewall
GPIO is not integrated, such as DCAN
Clock calibration
Debug over CAN
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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Figure 7-89 provides an overview of the MCAN module.
Device
MCANSS
Uncorrectable ECC
CM NMI
NVIC
Correctable ECC
Configurable Interrupts (2 lines)
Counter Overflow and Clock Stop/
Wakeup
mcanss_tx
mcanss_rx
CPU BUS
CM.PERx.SYSCLK
MCAN Bit Clock
Peripheral Clock
Bit Timing Clock
Clock disable/
enable
Wakeup
Clock Stop and Wakeup
CMSOFTPRESET1
Reset
Figure 7-89. MCAN Module Overview
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.14.2 Ethernet Media Access Controller (EMAC)
The Ethernet module enables a host to transmit and receive data over the Ethernet in compliance with IEEE
802.3-2015. The Ethernet module contains the following characteristics:
•
•
•
•
•
IEEE 802.3-2015 for Ethernet MAC, Media Independent Interface (MII)
IEEE 1588-2008 for precision networked clock synchronization
IEEE 802.3az-2010 for Energy Efficient Ethernet (EEE)
Reduced Media Independent Interface (RMII) specification version 1.2 from RMII consortium
Reverse Media Independent Interface (RevMII)
For more information about the Ethernet module, see the Ethernet chapter of the TMS320F2838x Real-Time
Microcontrollers Technical Reference Manual.
7.14.2.1 MAC Features
The Ethernet controller supports a number of Tx and Rx MAC features. The MAC includes the following feature
groups:
•
•
•
MAC Tx and Rx features
MAC Tx features
MAC Rx features
7.14.2.1.1 MAC Tx and Rx Features
The combined features for Tx and Rx are as follows:
•
•
•
Separate transmission, reception, and control interfaces to the application
Little-endian mode for Transmit and Receive paths
10, 100 data transfer rates with the following PHY interfaces:
– IEEE 802.3-compliant MII (default) interface to communicate with an external Ethernet PHY
– RMII interface to communicate with an external Fast Ethernet PHY
– RevMII interface to directly communicate with a remote MAC
Half-duplex operation:
•
– CSMA/CD Protocol support
– Flow control using backpressure support (based on implementation-specific white papers and UNH
Ethernet Clause 4 MAC Test Suite - Annex D)
•
•
•
•
Standard IEEE 802.3az-2010 for Energy Efficient Ethernet in MII PHYs.
Full-duplex flow control operations (IEEE 802.3x Pause packets and Priority flow control)
Network statistics with RMON or MIB Counters (RFC2819/RFC2665)
Support Ethernet packet timestamping as described in IEEE 1588-2002 and IEEE 1588-2008 (64-bit
timestamps given in the Tx or Rx status of PTP packet). Both one-step and two-step timestamping is
supported in the TX direction.
•
•
Flexibility to control the Pulse-Per-Second (PPS) output signal
MDIO (Clause 22 and Clause 45) master interface for PHY device configuration and management
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.14.2.1.2 MAC Tx Features
The MAC Tx features are as follows:
•
•
•
•
•
•
Preamble and start-of-packet data (SFD) insertion
Separate 32-bit status for each packet transmitted from the application
Automatic CRC and pad generation controllable on a per-packet basis
Programmable packet length to support Standard or Jumbo Ethernet packets up to 16KB in size
Programmable Inter Packet Gap (40–96 bit times in steps of 8)
IEEE 802.3x Flow Control automatic transmission of zero-quanta Pause packet when flow control input
transitions from assertion to deassertion (in full-duplex mode)
•
Source Address field insertion or replacement, and VLAN insertion, replacement, and deletion in transmitted
packets with per-packet or static-global control
•
•
Insertion, replacement, or deletion of up to two VLAN tags
Insert, replace, or delete queue/channel-based VLAN tags
7.14.2.1.3 MAC Rx Features
The MAC Rx features are as follows:
•
Flexible address filtering modes:
– Destination Address filters with masks for each byte
– Source Address comparison check with masks for each byte
– 64-bit Hash filter for multicast and unicast (DA) addresses
– Option to pass all multicast addressed packets
– Promiscuous mode to pass all packets without any filtering for network monitoring
– Pass all incoming packets (as per filter) with a status report
Additional packet filtering:
•
– VLAN tag-based: Perfect match and Hash-based filtering. Filtering based on either outer or inner VLAN
tag is possible.
– Layer 3 and Layer 4-based: TCP or UDP over IPv4 or IPv6
– Extended VLAN-tag based filtering 4-filter selection
•
•
•
•
•
IEEE 802.1Q VLAN tag detection and option to delete the VLAN tags in received packets
Module to detect remote wake-up packets and AMD magic packets
Forwarding of received Pause packets to the application (in full-duplex mode)
Receive module for Layer-3/Layer-4 checksum offload for received packets
Stripping of up to two VLAN Tags and providing the tags in the status.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.14.2.2 Ethernet Electrical Data and Timing
Section 7.14.2.2.1 lists the Ethernet timing requirements. Section 7.14.2.2.2 lists the Ethernet switching
characteristics. Figure 7-90 through Figure 7-96 show the Ethernet timing diagrams.
7.14.2.2.1 Ethernet Timing Requirements
NO.
MIN
NOM
MAX
UNIT
MII 100 Mbps
MII1
tc(TXCK)
Cycle time, ENET_MII_TX_CLK
40
ns
ns
ns
ns
MII2/
MII3
tw(TXCK)
tc(RXCK)
tw(RXCK)
Pulse duration, ENET_MII_TX_CLK high or low
Cycle time, ENET_MII_RX_CLK
16
16
24
24
MII4
40
MII5/
MII6
Pulse duration, ENET_MII_RX_CLK high or low
Setup time, receive signals valid before ENET_MII_RX_CLK
high
MII8
MII9
tsu(MRXDV-RXCKH)
th(RXCKH-MRXDV)
10
2
ns
ns
Hold time, receive signals valid after ENET_MII_RX_CLK high
MII 10 Mbps
MII1
tc(TXCK)
Cycle time, ENET_MII_TX_CLK
400
400
ns
ns
ns
ns
MII2/
MII3
tw(TXCK)
tc(RXCK)
tw(RXCK)
Pulse duration, ENET_MII_TX_CLK high or low
Cycle time, ENET_MII_RX_CLK
160
160
240
240
MII4
MII5/
MII6
Pulse duration, ENET_MII_RX_CLK high or low
Setup time, receive signals valid before ENET_MII_RX_CLK
high
MII8
MII9
tsu(MRXDV-RXCKH)
th(RXCKH-MRXDV)
10
2
ns
ns
Hold time, receive signals valid after ENET_MII_RX_CLK high
RMII (Internal Clock) 100 Mbps
RMII5 tsu(MRXDV-RCKH)
RMII6 th(RCKH-MRXDV)
Setup time, receive signals valid before ENET_RMII_CLK high
Hold time, receive signals valid after ENET_RMII_CLK high
4
2
ns
ns
RMII (Internal Clock) 10 Mbps
RMII5 tsu(MRXDV-RCKH)
RMII6 th(RCKH-MRXDV)
Setup time, receive signals valid before ENET_RMII_CLK high
Hold time, receive signals valid after ENET_RMII_CLK high
4
2
ns
ns
RMII (External Clock) 100 Mbps
RMII1 tc(RCK)
Cycle time, ENET_RMII_CLK
20
200
400
ns
ns
RMII2/
tw(RCK)
RMII3
Pulse duration, ENET_RMII_CLK high or low
8
12
120
240
RMII5 tsu(MRXDV-RCKH)
RMII6 th(RCKH-MRXDV)
RMII (External Clock) 10 Mbps
RMII1 tc(RCK)
Setup time, receive signals valid before ENET_RMII_CLK high
Hold time, receive signals valid after ENET_RMII_CLK high
4
2
ns
ns
Cycle time, ENET_RMII_CLK
ns
ns
RMII2/
tw(RCK)
RMII3
Pulse duration, ENET_RMII_CLK high or low
80
RMII5 tsu(MRXDV-RCKH)
RMII6 th(RCKH-MRXDV)
MDIO
Setup time, receive signals valid before ENET_RMII_CLK high
Hold time, receive signals valid after ENET_RMII_CLK high
4
2
ns
ns
MDIO1 tc(MCK)
Cycle time, ENET_MDIO_CLK
ns
ns
MDIO2/
tw(MCK)
MDIO3
Pulse duration, ENET_MDIO_CLK high or low
160
20
Setup time, ENET_MDIO_DATA valid before
ENET_MDIO_CLK high
MDIO4 tsu(MDV-MCKH)
ns
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.14.2.2.1 Ethernet Timing Requirements (continued)
NO.
MIN
NOM
MAX
UNIT
Hold time, ENET_MDIO_DATA valid after ENET_MDIO_CLK
MDIO5 th(MCKH-MDV)
high
–1
ns
7.14.2.2.2 Ethernet Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
NO.
PARAMETER
MIN
TYP
MAX
UNIT
MII 100 Mbps
Delay time, ENET_MII_TX_CLK high to
transmit signals valid
MII7
td(TXCKH-MTXDV)
0
15
ns
MII 10 Mbps Switching Characteristics
Delay time, ENET_MII_TX_CLK high to
transmit signals valid
MII7
td(TXCKH-MTXDV)
0
8
15
ns
RMII (Internal Clk) 100 Mbps
RMII7 tc(RCK)
Cycle time, ENET_RMII_CLK
20
ns
ns
RMII8/
tw(RCK)
RMII9
Pulse duration, ENET_RMII_CLK high or
low
12
14
Delay time, ENET_RMII_CLK high to
transmit signals valid
RMII11 td(RCKH-MTXDV)
ns
RMII (Internal Clk) 10 Mbps
RMII7 tc(RCK)
Cycle time, ENET_RMII_CLK
200
ns
ns
RMII8/
tw(RCK)
RMII9
Pulse duration, ENET_RMII_CLK high or
low
80
0
120
14
Delay time, ENET_RMII_CLK high to
transmit signals valid
RMII11 td(RCKH-MTXDV)
RMII (External Clk) 100 Mbps
RMII11 td(RCKH-MTXDV)
ns
ns
ns
Delay time, ENET_RMII_TX_CLK high to
transmit signals valid
0
0
14
14
RMII (External Clk) 10 Mbps
RMII11 td(RCKH-MTXDV)
Delay time, ENET_RMII_CLK high to
transmit signals valid
MDIO
MDIO1 tc(MCK)
Cycle time, ENET_MDIO_CLK
400
ns
ns
MDIO2/
tw(MCK)
MDIO3
Pulse duration, ENET_MDIO_CLK high or
low
160
240
Delay time, ENET_MDIO_CLK high to
ENET_MDIO_DATA valid
td(MCKH-MDV)
0.5tc(MCK) + 30
ns
ns
MDIO7
Valid time, ENET_MDIO_DATA valid
after ENET_MDIO_CLK high
tv(MCKH-MDV)
0.5tc(MCK)
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.14.2.2.3 Ethernet Timing Diagrams
MII1
MII2
MII3
ENET_MII_TX_CLK
Figure 7-90. Transmit Clock Timing (MII Operation)
MII7
ENET_MII_TX_CLK (input)
ENET_MII_TX_DATA3–ENET_MII_TX_DATA0,
ENET_MII_TX_EN (outputs)
Figure 7-91. Transmit Interface Timing (MII Operation)
MII4
MII5
MII6
ENET_MII_RX_CLK
Figure 7-92. Receive Clock Timing (MII Operation)
MII8
MII9
ENET_MII_RX_CLK (input)
ENET_MII_RX_DATA3–ENET_MII_RX_DATA0,
ENET_MII_RX_DV, ENET_MII_RX_ERR (inputs)
Figure 7-93. Receive Interface Timing (MII Operation)
MDIO1
MDIO2
MDIO3
ENET_MDIO_CLK
MDIO4
MDIO5
ENET_MDIO_DATA (input)
MDIO7
ENET_MDIO_DATA (output)
Figure 7-94. MDIO Timing Diagrams
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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RMII1
RMII3
RMII2
RMII6
RMII5
ENET_RMII_CLK
ENET_MII_RX_DATA1–ENET_MII_RX_DATA0,
ENET_MII_CRS, ENET_MII_RX_ERR (inputs)
Figure 7-95. Receive Interface Timing (RMII Operation)
RMII7
RMII8
RMII9
RMII11
ENET_RMII_CLK
ENET_MII_TX_DATA1–ENET_MII_TX_DATA0,
ENET_MII_TX_EN (outputs)
Figure 7-96. Transmit Interface Timing (RMII Operation)
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.14.2.3 Ethernet REVMII Electrical Data and Timing
Section 7.14.2.3.1 lists the Ethernet REVMII timing requirements. Section 7.14.2.3.2 lists the Ethernet REVMII
switching characteristics.
7.14.2.3.1 Ethernet REVMII Timing Requirements
MIN
NOM
MAX
UNIT
REVMII
tc(RXCK)
tw(RXCK)
Cycle time, ENET_MII_RX_CLK
40
ns
ns
Pulse duration, ENET_MII_RX_CLK high or low
16
15
24
Setup time, ENET_MII_RX_DATA[3:0], ENET_MII_RX_EN valid
before ENET_MII_RX_CLK high
tsu(MRXDV-RXCKH)
th(RXCKH-MRXDV)
ns
ns
Hold time, ENET_MII_RX_DATA[3:0], ENET_MII_RX_EN valid after
ENET_MII_RX_CLK high
0
MDIO
tc(MCK)
Cycle time, ENET_MDIO_CLK
400
ns
ns
ns
ns
tw(MCK)
Pulse duration, ENET_MDIO_CLK high or low
160
30
3
240
tsu(MDV-MCKH)
th(MCKH-MDV)
Setup time, ENET_MDIO_DATA valid before ENET_MDIO_CLK high
Hold time, ENET_MDIO_DATA valid after ENET_MDIO_CLK high
7.14.2.3.2 Ethernet REVMII Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
REVMII
tc(TXCK)
tw(TXCK)
Cycle time, ENET_MII_TX_CLK
40
ns
ns
Pulse duration, ENET_MII_TX_CLK high or low
16
24
10
Delay time, ENET_MII_TX_CLK high to
ENET_MII_TX_DATA[3:0], ENET_MII_TX_DV,
ENET_MII_TX_ERR valid
td(TXCKH-DV)
ns
ns
Valid time, ENET_MII_TX_CLK high to
ENET_MII_TX_DATA[3:0], ENET_MII_TX_DV,
ENET_MII_TX_ERR invalid
tv(TXCKH-DV)
1
MDIO
tc(MCK)
tw(MCK)
Cycle time, ENET_MDIO_CLK
400
ns
ns
Pulse duration, ENET_MDIO_CLK high or low
160
1
240
40
Delay time, ENET_MDIO_CLK high to
ENET_MDIO_DATA valid
td(MCKH-MDV)
tv(MCKH-MDV)
ns
ns
Valid time, ENET_MDIO_DATA valid
after ENET_MDIO_CLK high
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TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
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7.14.3 Inter-Integrated Circuit (CM-I2C)
The CM-I2C bus provides bidirectional data transfer through a two-wire design; a serial data line (SDA) and a
serial clock line (SCL); and interfaces to external I2C devices such as serial memory (RAMs and ROMs),
networking devices, LCDs, tone generators, and so on. The CM-I2C bus can also be used for system testing and
diagnostic purposes in product development and manufacturing.
The CM-I2C modules support the following features:
•
Devices on the CM-I2C bus can be designated as either a master or a slave.
– Support both transmitting and receiving data as either a master or a slave
– Support simultaneous master and slave operation
•
Four CM-I2C modes:
– Master transmit
– Master receive
– Slave transmit
– Slave receive
•
•
Receive FIFO and Transmitter FIFO (8 deep × 8 bits FIFO)
– FIFOs can be independently assigned to master or slave
Three transmission speeds:
– Standard (100 kbps)
– Fast mode (400 kbps)
– Fast-mode plus (1 Mbps)
•
•
Glitch suppression
SMBus support through software
– Clock low time-out interrupt
– Dual slave address capability
– Quick command capability
•
Master and slave interrupt generation
– Master generates interrupts when a transmit or receive operation completes (or aborts because of an
error)
– Slave generates interrupts when data has been transferred or requested by a master or when a START or
STOP condition is detected
•
•
Master with arbitration and clock synchronization, multiple-master support, and 7-bit addressing mode
Efficient transfers using a Micro Direct Memory Access (µDMA) Controller
– Separate channels for transmit and receive
– Ability to execute single data transfers or burst data transfers using the RX and TX FIFOs in the CM-I2C
Figure 7-97 shows the CM-I2C block diagram.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
dma_done dma_req dma_sreq interrupt
Master Core
I2CMSA
RXFIFO
RX_FIFO_7
RX_FIFO_6
RX_FIFO_5
RX_FIFO_4
RX_FIFO_3
RX_FIFO_2
RX_FIFO_1
I2CMCS
I2CMDR
I2CMTPR
I2CMIMR
I2CMRIS
Master I2CSDA
I2CMMIS
I2CMICR
RX_FIFO_0
8 bits
I2CMCR
Data
TX_FIFO_7
TX_FIFO_6
Master I2CSCL
Master I2CSDA
I2CMCLKOCNT
I2CMBMON
I2CMBMLEN
I2CMBCNT
Slave I2CSDA
TX_FIFO_5
TX_FIFO_4
TX_FIFO_3
TX_FIFO_2
TX_FIFO_1
I2CSCL
I2CSDA
Slave I2CSCL
Slave I2CSDA
Slave Core
I2CSOAR
TX_FIFO_0
TXFIFO
I2CSCSR
I2CSDR
I2CSIMR
I2C Status and Control
I2CSRIS
I2CSMIS
I2CFIFODATA
I2CFIFOCTL
I2CFIFOSTATUS
I2CPP
I2CSICR
I2CSSOAR2
I2CSACKCTL
Figure 7-97. CM-I2C Block Diagram
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.14.3.1 CM-I2C Electrical Data and Timing
Section 7.14.3.1.1 lists the CM-I2C timing requirements. Section 7.14.3.1.2 lists the CM-I2C switching
characteristics. Figure 7-98 shows the CM-I2C timing diagram.
7.14.3.1.1 CM-I2C Timing Requirements
NO.
MIN
MAX
UNIT
Standard mode
Hold time, START condition, SCL fall delay after
SDA fall
T1
T2
th(SDA-SCL)START
4.0
4.7
µs
µs
Setup time, Repeated START, SCL rise before SDA
fall delay
tsu(SCL-SDA)START
T3
T4
T5
T6
T7
T8
th(SCL-DAT)
tsu(DAT-SCL)
tr(SDA)
Hold time, data after SCL fall
Setup time, data before SCL rise
Rise time, SDA
0
µs
ns
ns
ns
ns
ns
250
1000
1000
300
tr(SCL)
Rise time, SCL
tf(SDA)
Fall time, SDA
tf(SCL)
Fall time, SCL
300
Setup time, STOP condition, SCL rise before SDA
rise delay
T9
tsu(SCL-SDA)STOP
4.0
µs
Pulse duration of spikes that will be suppressed by
filter
T10
tw(SP)
Cb
tc(CMCLK)
31 * tc(CMCLK)
400
ns
T11
capacitance load on each bus line
pF
Fast mode
Hold time, START condition, SCL fall delay after
SDA fall
T1
T2
th(SDA-SCL)START
tsu(SCL-SDA)START
0.6
0.6
µs
µs
Setup time, Repeated START, SCL rise before SDA
fall delay
T3
T4
T5
T6
T7
T8
th(SCL-DAT)
tsu(DAT-SCL)
tr(SDA)
Hold time, data after SCL fall
Setup time, data before SCL rise
Rise time, SDA
0
100
20
µs
ns
ns
ns
ns
ns
300
300
300
300
tr(SCL)
Rise time, SCL
20
tf(SDA)
Fall time, SDA
11.4
11.4
tf(SCL)
Fall time, SCL
Setup time, STOP condition, SCL rise before SDA
rise delay
T9
tsu(SCL-SDA)STOP
0.6
µs
Pulse duration of spikes that will be suppressed by
filter
T10
T11
tw(SP)
Cb
tc(CMCLK)
31 * tc(CMCLK)
400
ns
capacitance load on each bus line
pF
Fast mode plus
Hold time, START condition, SCL fall delay after
SDA fall
T1
T2
th(SDA-SCL)START
0.26
0.26
µs
µs
Setup time, Repeated START, SCL rise before SDA
fall delay
tsu(SCL-SDA)START
T3
T4
T5
T6
T7
T8
th(SCL-DAT)
tsu(DAT-SCL)
tr(SDA)
Hold time, data after SCL fall
Setup time, data before SCL rise
Rise time, SDA
0
µs
ns
ns
ns
ns
ns
50
120
120
120
120
tr(SCL)
Rise time, SCL
tf(SDA)
Fall time, SDA
11.4
11.4
tf(SCL)
Fall time, SCL
Setup time, STOP condition, SCL rise before SDA
rise delay
T9
tsu(SCL-SDA)STOP
0.26
µs
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
7.14.3.1.1 CM-I2C Timing Requirements (continued)
NO.
MIN
MAX
31 * tc(CMCLK)
550
UNIT
ns
Pulse duration of spikes that will be suppressed by
filter
T10
T11
tw(SP)
Cb
tc(CMCLK)
capacitance load on each bus line
pF
7.14.3.1.2 CM-I2C Switching Characteristics
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER
TEST CONDITIONS
0.1 Vbus < Vi < 0.9 Vbus
0.1 Vbus < Vi < 0.9 Vbus
0.1 Vbus < Vi < 0.9 Vbus
MIN
MAX UNIT
Standard mode
S1
S2
S3
S4
fSCL
SCL clock frequency
0
10
100
kHz
µs
TSCL
SCL clock period
tw(SCLL)
tw(SCLH)
Pulse duration, SCL clock low
Pulse duration, SCL clock high
4.7
4.0
µs
µs
Bus free time between STOP and START
conditions
S5
tBUF
4.7
µs
S6
S7
S8
tv(SCL-DAT)
tv(SCL-ACK)
II
Valid time, data after SCL fall
Valid time, Acknowledge after SCL fall
Input current on pins
3.45
3.45
10
µs
µs
µA
–10
Fast mode
S1
S2
S3
S4
fSCL
SCL clock frequency
0
2.5
1.3
0.6
400
kHz
µs
TSCL
SCL clock period
tw(SCLL)
tw(SCLH)
Pulse duration, SCL clock low
Pulse duration, SCL clock high
µs
µs
Bus free time between STOP and START
conditions
S5
tBUF
1.3
µs
S6
S7
S8
tv(SCL-DAT)
tv(SCL-ACK)
II
Valid time, data after SCL fall
Valid time, Acknowledge after SCL fall
Input current on pins
0.9
0.9
10
µs
µs
µA
–10
Fast mode plus
S1
S2
S3
S4
fSCL
SCL clock frequency
0
1
1000
kHz
µs
TSCL
SCL clock period
tw(SCLL)
tw(SCLH)
Pulse duration, SCL clock low
Pulse duration, SCL clock high
0.5
0.26
µs
µs
Bus free time between STOP and START
conditions
S5
tBUF
0.5
µs
S6
S7
S8
tv(SCL-DAT)
tv(SCL-ACK)
II
Valid time, data after SCL fall
Valid time, Acknowledge after SCL fall
Input current on pins
0.45
0.45
10
µs
µs
µA
–10
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.14.3.1.3 CM-I2C Timing Diagram
STOP
START
SDA
SCL
ACK
Contd...
Contd...
S7
S6
T10
T5
T7
S3
S4
9th
clock
T6
T8
S2
Repeated
START
STOP
S5
SDA
ACK
T2
T9
T1
SCL
9th
clock
Figure 7-98. CM-I2C Timing Diagram
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
7.14.4 Synchronous Serial Interface (SSI)
The SSI module includes the following features:
•
Programmable interface operation for Freescale® SPI, or Texas Instruments Synchronous Serial Interfaces.
In this SSI module, only the Legacy SSI mode is supported.
Master or slave operation
Programmable clock bit rate and prescaler
Separate transmit and receive FIFOs, each 16 bits wide and 8 locations deep
Programmable data frame size from 4 to 16 bits
Internal loopback test mode for diagnostic and debug testing
Standard FIFO-based interrupts and End-of-Transmission interrupt
Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Separate channels for transmit and receive
•
•
•
•
•
•
•
– Receive single request asserted when data is in the FIFO; burst request asserted when FIFO contains
four entries
– Transmit single request asserted when there is space in the FIFO; burst request asserted when FIFO
contains four or more entries are available to be written in the FIFO
– Maskable μDMA interrupts for receive and transmit complete
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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Figure 7-99. SSI Block Diagram
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
7.14.4.1 SSI Electrical Data and Timing
Section 7.14.4.1.1 lists the SSI timing requirements. Section 7.14.4.1.2 lists the SSI switching characteristics.
Figure 7-100 through Figure 7-102 show the SSI timing diagrams.
7.14.4.1.1 SSI Timing Requirements
NO.
MIN
NOM
MAX UNIT
MASTER MODE
S8
S8
S9
tRXDMS
tRXDMS
tRXDMH
Rx Data setup time (high-speed mode)
Rx Data setup time (normal mode)
Rx Data hold time
4
14
2
ns
ns
ns
SLAVE MODE
S1
S2
tCLK_PER
SSIClk cycle time(1)
SSIClk high time
SSIClk low time
12 × tc(CMCLK)
0.4 × tCLK_PER
0.4 × tCLK_PER
0
ns
ns
ns
ns
ns
tCLK_HIGH
tCLK_LOW
tRXDSSU
tRXDSH
S3
S12
S13
Rx Data setup time
Rx Data hold time
4 × tc(CMCLK)
(1) In slave mode, the SSICPSR must be configured to set SSICLK to less than one twelfth of CMCLK.
7.14.4.1.2 SSI Characteristics
over operating free-air temperature range (unless otherwise noted)
NO.
PARAMETER
MIN
TYP
MAX UNIT
MASTER MODE
S1
S2
S3
S6
S7
tCLK_PER
tCLK_HIGH
tCLK_LOW
tTXDMOV
tTXDMOH
SSIClk cycle time(1)
2 × tCMCLK
0.4 × tCLK_PER
0.4 × tCLK_PER
ns
ns
ns
SSIClk high time
SSIClk low time
Tx Data output valid time from SSIClk
Tx Data output hold time after next SSIClk
6
ns
ns
0
SLAVE MODE
S10 tTXDSOV
S11 tTXDSOH
Tx Data output valid time from edge of SSIClk
Tx Data output hold time from next SSIClk
4 × tCMCLK+14
ns
ns
4 × tCMCLK + 4
(1) In master mode, the SSICPSR must be configured to set SSICLK to less than half of CMCLK. For master mode normal mode (non-
high speed), a larger SSICPSR divider may be needed to meet the master RX input setup requirements.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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7.14.4.1.3 SSI Timing Diagrams
S1
S2
SSIClk
S3
SSIFss
SSITx
MSB
LSB
SSIRx
4 to 16 bits
Figure 7-100. SSI Timing for TI Frame Format (FRF = 01), Single Transfer Timing Measurement
S1
S2
SSIClk
(SPO=1)
S3
SSIClk
(SPO=0)
S7
S6
SSITx
(to slave)
MSB
LSB
S8 S9
SSIRx
(from slave)
MSB
LSB
SSIFss
Figure 7-101. Master Mode SSI Timing for SPI Frame Format (FRF = 00), with SPH = 1
S1
S2
SSIClk
(SPO=1)
S3
SSIClk
(SPO=0)
S10
S11
SSITx
(from master)
MSB
LSB
S12
S13
SSIRx
(to master)
LSB
MSB
SSIFss
Figure 7-102. Slave Mode SSI Timing for SPI Frame Format (FRF = 00), with SPH = 1
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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7.14.5 Universal Asynchronous Receiver/Transmitter (CM-UART)
The Universal Asynchronous Receiver/Transmitter (UART) module in this device contains the following features:
•
Programmable baud-rate generator allowing speeds of up to 7.8125 Mbps for regular speed (divide by 16)
and 15.625 Mbps for high speed (divide by 8)
•
Separate 16-level-deep and 8-bit-wide transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service
loading
•
•
•
•
•
Programmable FIFO length, including 1-byte-deep operation providing conventional double-buffered interface
FIFO trigger levels of ⅛, ¼, ½, ¾, and ⅞
Standard asynchronous communication bits for start, stop, and parity
Line-break generation and detection
Fully programmable serial interface characteristics
– 5, 6, 7, or 8 data bits
– Even, odd, stick, or no parity-bit generation and detection
– 1 or 2 stop-bit generation
•
IrDA serial-IR (SIR) encoder and decoder providing:
– Programmable use of IrDA SIR or UART input/output
– Support of IrDA SIR encoder and decoder functions for data rates of up to 115.2 kbps half-duplex
– Support of normal 3/16 and low-power (1.41 to 2.23 μs) bit durations
– Programmable internal clock generator enabling division of reference clock by 1 to 256 for low-power-
mode bit duration
•
•
•
EIA-485 9-bit support
Standard FIFO-level and End-of-Transmission (EOT) interrupts
Efficient transfers using Micro Direct Memory Access (µDMA) Controller
– Separate channels for transmit and receive
– Receive single request asserted when data is in the FIFO; burst request asserted at programmed FIFO
level
– Transmit single request asserted when there is space in the FIFO; burst request asserted at programmed
FIFO level
Figure 7-103 shows the CM-UART module block diagram.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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Clock Control
UARTCC
CMCLK
Baud Clock
UARTCTL
DMA Control
DMA Request
UARTDMACTL
Interrupt Control
TxFIFO
16x8
Interrupt
UARTIFLS
UARTIM
Identification Registers
.
.
.
UARTPCellID0
UARTPCellID1
UARTPCellID2
UARTPCellID3
UARTPeriphID0
UARTPeriphID1
UARTPeriphID2
UARTPeriphID3
UARTPeriphID4
UARTPeriphID5
UARTPeriphID6
UARTPeriphID7
UARTMIS
UARTRIS
UARTICR
UnTx
UnRx
Transmitter
(with SIR
Transmit
Encoder)
Baud Rate
Generator
Data Register
UARTDR
UARTIBRD
UARTFBRD
Receiver
Control/Status
(with SIR
Receive
Decoder)
RxFIFO
16x8
UARTRSR/ECR
UARTFR
UARTLCRH
UARTCTL
.
.
.
UARTILPR
UART9BITADDR
UART9BITAMASK
UARTPP
Figure 7-103. CM-UART Module Block Diagram
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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7.14.6 Trace Port Interface Unit (TPIU)
Trace capability from the Cortex-M4 is supported on the CM subsystem.
The Cortex-M4 supports two trace interfaces:
•
•
Single wire trace, which follows a UART protocol and is asynchronous
Five-pin (four data pins and one clock pin) and parallel trace
Both options are supported on this device. Figure 7-104 shows the high-level clock and signal hook-up to and
from the TPIU.
Cortex-M4 with customizable components
NVIC
DWT
Serial Wire Trace
(SWO)
TRACESWO
Cortex-M4
Core
TRACEDATA[3]
TRACEDATA[2]
FCLK
TPIU
CMCLK
HCLK
TRACEDATA[1]
TRACEDATA[0]
TRACECLK
TRACECLKIN
Divide By 2
Figure 7-104. Debug Trace
Table 7-10 lists the key attributes of the two trace data export mechanisms. For more details about TPIU and
trace mechanisms, see the Arm Architecture Reference Manual.
Table 7-10. Key Attributes of Trace Data Export
ATTRIBUTE PARALLEL TRACE
Protocol
SERIAL WIRE TRACE
PARALLEL TRACE
Trace Data changes on both
edges of TRACECLK.
UART Protocol/Manchester-encoded data stream
Frequency(CMHCLK)/(TPIU_ACPR + 1)
Data throughput rate
Frequency(CMHCLK)/2
You must configure the GPIO mux to select a trace function on the GPIO pin to use it.
7.14.6.1 TPIU Electrical Data and Timing
Section 7.14.6.1.1 lists the trace port switching characteristics.
7.14.6.1.1 Trace Port Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
ns
tc(TRACE_CLK) Cycle time, TRACE_CLK
16
tw(TRACE_CLK) Pulse duration, TRACE_CLK high or low
6
10
2
ns
td(TRACE_DATA,
Delay time, TRACE_CLK high to valid TRACE_DATA
-2
ns
TRACE_SWO)
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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8 Detailed Description
8.1 Overview
The TMS320F2838x is a powerful 32-bit floating-point real-time microcontroller unit (MCU) designed for
advanced closed-loop control applications such as industrial drives and servo motor control; solar inverters and
converters; digital power; electric vehicles; and DSP and sensing applications. The F2838x supports a dual-core
C28x architecture along with a new Connectivity Manager that offloads critical communication tasks, significantly
boosting system performance. The integrated analog and control peripherals with advanced connectivity
peripherals like EtherCAT and Ethernet also let designers consolidate real-time control and real-time
communications architectures reducing requirements for multicontroller systems.
The dual real-time control subsystems are based on TI’s 32-bit C28x floating-point CPUs, which provide
200 MHz of signal processing performance in each core. The C28x CPUs are further boosted by the TMU
accelerator, which enables fast execution of algorithms with trigonometric operations common in transforms and
torque loop calculations.
The F2838x real-time microcontroller family features two CLA real-time control coprocessors. The CLA is an
independent 32-bit floating-point processor that runs at the same speed as the main CPU. The CLA responds to
peripheral triggers and executes code concurrently with the main C28x CPU. This parallel processing capability
can effectively double the computational performance of a real-time control system. By using the CLA to service
time-critical functions, the main C28x CPU is free to perform other tasks, such as communications and
diagnostics. The dual C28x+CLA architecture enables intelligent partitioning between various system tasks. For
example, one C28x+CLA core can be used to track speed and position, while the other C28x+CLA core can be
used to control torque and current loops.
The Connectivity Manager subsystem is based on the Cortex-M4 CPU and has access to advanced
communication IPs like EtherCAT, Ethernet, MCAN (CAN-FD) and AES.
The TMS320F2838x supports up to 1.5MB (512KB per CPU) of flash memory with error correction code (ECC)
and up to 312KB (216KB total for C28x CPU1 and CPU2, and 96KB on the Cortex-M4) of SRAM. Two 128-bit
secure zones are also available on the device for code protection.
Performance analog and control peripherals are also integrated on the F2838x MCU to further enable system
consolidation. Four independent 16-bit ADCs provide precise and efficient management of multiple analog
signals, which ultimately boosts system throughput. The sigma-delta filter module (SDFM) works in conjunction
with the sigma-delta modulator to enable isolated current shunt measurements. The Comparator Subsystem
(CMPSS) with windowed comparators allows for protection of power stages when current limit conditions are
exceeded or not met. Other analog and control peripherals include DACs, PWMs, eCAPs, eQEPs, and other
peripherals.
Peripherals such as EMIFs, CAN modules (ISO 11898-1/CAN 2.0B-compliant), EtherCAT, Ethernet, and MCAN
(CAN-FD) extend the connectivity of the F2838x. Lastly, a USB 2.0 port with MAC and PHY lets users easily add
universal serial bus (USB) connectivity to their application.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
8.2 Functional Block Diagram
Figure 8-1 shows the CPU system and associated peripherals.
Connectivity
Manager (CM)
C28 CPU1
C28 CPU2
CPU1 - CM
IPC
CPU1
CPU1.CLA
CPU1.DMA
FPU64
FPU32
TMU
FPU64
FPU32
TMU
MSGRAM0
MSGRAM1
CPU1.CLA1
CPU2.CLA1
Arm Cortex-M4
VCRC
VCRC
CPU2
CPU2.CLA
CPU2.DMA
AES
CPU Timers
GCRC
NVIC
NMI WD
Windowed WD
CPU2 - CM
IPC
BGCRC
BGCRC
CPU Timers
DCC
ePIE
ERAD
BGCRC
BGCRC
CPU Timers
CM M4 CODE
CM M4 SYS
CM µDMA
CM Bus Matrix
Ethernet DMA
MSGRAM0
CPU - CLA
MSGRAM
CPU - CLA
MSGRAM
ePIE
ERAD
NMI WD
MSGRAM1
NMI WD
Windowed WD
Windowed WD
CPU1 - CPU2
IPC
Boot ROM
Secure
Memories
shown in Red
Boot ROM
Secure ROM
Boot ROM
CLA ROM
CLA ROM
MSGRAM0
MSGRAM1
Secure ROM
Secure ROM
Flash (512KB)
Flash (512KB)
Flash (512KB)
C0-C1 RAM (16KB)
E0 RAM (16KB)
M0-M1 RAM (4KB)
D0-D1 RAM (8KB)
M0-M1 RAM (4KB)
D0-D1 RAM (8KB)
LS0-LS7 RAM
(32KB)
LS0-LS7 RAM
(32KB)
GS0-GS15 RAM
(128KB)
S0-S3 RAM (64KB)
DMA - CLA
MSGRAM
DMA - CLA
MSGRAM
CPU1.DMA
CPU2.DMA
CM µDMA
CM Bus
Matrix
PF3
PF1
PF9
PF2
PF5
PF6
PF10
PF4
MUX
MUX
MUX
MUX
Data
169x GPIO
2x CAN
1x USB 1x CAN-FD
8x FSIRX
2x FSITX
2x McBSP
1x PMBUS
4x SPI
EMIF1
EMIF2
8x CLB
8x CMPSS
3x DAC
2x I2C
4x SCI
Result
DMA
1x EtherCAT
(2 Ports)
1x Ethernet
4x ADC
(16-bit / 12-bit)
INPUT XBAR
OUTPUT XBAR
ePWM XBAR
1x CM-I2C
1x CM-UART
1x SSI
7x eCAP
(2 Hi-Res)
32x ePWM
Channels
(16 Hi-Res)
CLB XBAR
CLB INPUT XBAR
3x eQEP
CLB OUTPUT XBAR
8x SD Filters
Figure 8-1. Functional Block Diagram
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TMS320F28386S-Q1 TMS320F28384S TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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8.3 Memory
8.3.1 C28x Memory Map
Both C28x CPUs on the device have the same memory map except where noted in the C28x Memory Map
table. The GSx_RAM (Global Shared RAM) should be assigned to either CPU by the GSxMSEL register.
Memories accessible by the CLA or DMA (direct memory access) are noted as well.
Table 8-1. C28x Memory Map
START
ADDRESS
CLA
ACCESS
DMA
ACCESS
ECC/
PARITY
ACCESS
PROTECTION
MEMORY
SIZE
END ADDRESS
SECURITY
M0 RAM
M1 RAM
1K x 16
1K x 16
512 x 16
0x0000 0000
0x0000 0400
0x0000 0D00
0x0000 03FF
0x0000 07FF
0x0000 0EFF
ECC
ECC
Yes
Yes
PieVectTable
CPUx.CLA1 to CPUx
MSGRAM
128 x 16
128 x 16
128 x 16
128 x 16
0x0000 1480
0x0000 1500
0x0000 1680
0x0000 1700
0x0000 14FF
0x0000 157F
0x0000 16FF
0x0000 177F
Yes
Yes
Yes
Yes
Parity
Parity
Parity
Parity
CPUx to CPUx.CLA1
MSGRAM
CPUx.CLA1 to CPUx.DMA
MSGRAM
Yes
Yes
CPUx.DMA to CPUx.CLA1
MSGRAM
LS0 RAM
LS1 RAM
LS2 RAM
LS3 RAM
LS4 RAM
LS5 RAM
LS6 RAM
LS7 RAM
D0 RAM
2K x 16
2K x 16
2K x 16
2K x 16
2K x 16
2K x 16
2K x 16
2K x 16
2K x 16
2K x 16
4K x 16
4K x 16
0x0000 8000
0x0000 8800
0x0000 9000
0x0000 9800
0x0000 A000
0x0000 A800
0x0000 B000
0x0000 B800
0x0000 C000
0x0000 C800
0x0000 D000
0x0000 E000
0x0000 87FF
0x0000 8FFF
0x0000 97FF
0x0000 9FFF
0x0000 A7FF
0x0000 AFFF
0x0000 B7FF
0x0000 BFFF
0x0000 C7FF
0x0000 CFFF
0x0000 DFFF
0x0000 EFFF
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
ECC
ECC
ECC
ECC
ECC
ECC
ECC
ECC
ECC
ECC
Parity
Parity
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
D1 RAM
GS0 RAM(1)
GS1 RAM(1)
Yes
Yes
CLA DATA
ROM(5)
GS2 RAM(1)
4K x 16
0x0000 F000
0x0000 FFFF
Yes
Parity
Yes
GS3 RAM(1)
GS4 RAM(1)
GS5 RAM(1)
GS6 RAM(1)
GS7 RAM(1)
GS8 RAM(1)
GS9 RAM(1)
GS10 RAM(1)
GS11 RAM(1)
GS12 RAM(1)
GS13 RAM(1)
GS14 RAM(1)
GS15 RAM(1)
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
0x0001 0000
0x0001 1000
0x0001 2000
0x0001 3000
0x0001 4000
0x0001 5000
0x0001 6000
0x0001 7000
0x0001 8000
0x0001 9000
0x0001 A000
0x0001 B000
0x0001 C000
0x0001 0FFF
0x0001 1FFF
0x0001 2FFF
0x0001 3FFF
0x0001 4FFF
0x0001 5FFF
0x0001 6FFF
0x0001 7FFF
0x0001 8FFF
0x0001 9FFF
0x0001 AFFF
0x0001 BFFF
0x0001 CFFF
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Parity
Parity
Parity
Parity
Parity
Parity
Parity
Parity
Parity
Parity
Parity
Parity
Parity
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
EtherCAT RAM (direct access)
8K x 16
0x0003 0800
0x0003 27FF
Yes
Parity
(2)
CM to CPUx MSGRAM0
CM to CPUx MSGRAM1
CPUx to CM MSGRAM0
CPUx to CM MSGRAM1
CPU1 to CPU2 MSGRAM0
1K x 16
1K x 16
1K x 16
1K x 16
1K x 16
0x0003 8000
0x0003 8400
0x0003 9000
0x0003 9400
0x0003 A000
0x0003 83FF
0x0003 87FF
0x0003 93FF
0x0003 97FF
0x0003 A3FF
Yes
Yes
Yes
Yes
Yes
Parity
Parity
Parity
Parity
Parity
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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Table 8-1. C28x Memory Map (continued)
START
ADDRESS
CLA
ACCESS
DMA
ACCESS
ECC/
PARITY
ACCESS
PROTECTION
MEMORY
SIZE
END ADDRESS
SECURITY
CPU1 to CPU2 MSGRAM1
CPU2 to CPU1 MSGRAM0
CPU2 to CPU1 MSGRAM1
USB RAM(2)
1K x 16
1K x 16
1K x 16
2K x 16
2K x 16
2K x 16
1K x 16
1K x 16
256K x 16
32K x 16
96K x 16
0x0003 A400
0x0003 B000
0x0003 B400
0x0004 1000
0x0004 9000
0x0004 B000
0x0007 0000
0x0007 8000
0x0008 0000
0x003E 0000
0x003E 8000
0x0003 A7FF
0x0003 B3FF
0x0003 B7FF
0x0004 17FF
0x0004 97FF
0x0004 B7FF
0x0007 03FF
0x0007 83FF
0x000B FFFF
0x003E 7FFF
0x003F FFFF
Yes
Yes
Yes
Yes
Parity
Parity
Parity
Yes
Yes
Yes
Yes
CAN A Message RAM
CAN B Message RAM
TI OTP(4)
Parity
Parity
ECC
User OTP
Yes(3)
Yes
Flash
ECC
Parity
Parity
Secure ROM
Yes
Boot ROM
Pie Vector Fetch Error (part of
Boot ROM)
1 x 16
0x003F FFBE
0x003F FFBF
Parity
Parity
Default Vectors (part of Boot
ROM)
64 x 16
4K x 16
0x003F FFC0
0x0100 1000
0x003F FFFF
0x0100 1FFF
CLA Data ROM
(1) Shared between CPU subsystems.
(2) Only on the CPU1 subsystem.
(3) Only CPU1 User OTP is secure. CPU2 User OTP is non-secure.
(4) TI OTP is for TI internal use only.
(5) CLA has its Data ROM mapped at this address space.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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8.3.2 C28x Flash Memory Map
On the F28388D, F28386D, and F28384D devices, each CPU has its own flash bank [512KB (256KW)], the total
flash for each device is 1MB (512KW). Only one bank can be programmed or erased at a time and the code to
program and erase the flash should be executed out of RAM.
The F28388S, F28386S, and F28384S devices have one flash bank of 512KB (256KW) and the code to
program the flash should be executed out of RAM. See Section 7.10.4 for details on flash wait states.
The C28x Flash Memory Map table lists the addresses of the flash sectors.
Table 8-2. C28x Flash Memory Map
SECTOR
SIZE
START ADDRESS
END ADDRESS
OTP Sectors
Sectors
TI OTP
1K x 16
1K x 16
0x0007 0000
0x0007 8000
0x0007 03FF
0x0007 83FF
User OTP(1)
Sector 0
Sector 1
Sector 2
Sector 3
Sector 4
Sector 5
Sector 6
Sector 7
Sector 8
Sector 9
Sector 10
Sector 11
Sector 12
Sector 13
8K x 16
8K x 16
8K x 16
8K x 16
32K x 16
32K x 16
32K x 16
32K x 16
32K x 16
32K x 16
8K x 16
8K x 16
8K x 16
8K x 16
0x0008 0000
0x0008 2000
0x0008 4000
0x0008 6000
0x0008 8000
0x0009 0000
0x0009 8000
0x000A 0000
0x000A 8000
0x000B 0000
0x000B 8000
0x000B A000
0x000B C000
0x000B E000
0x0008 1FFF
0x0008 3FFF
0x0008 5FFF
0x0008 7FFF
0x0008 FFFF
0x0009 7FFF
0x0009 FFFF
0x000A 7FFF
0x000A FFFF
0x000B 7FFF
0x000B 9FFF
0x000B BFFF
0x000B DFFF
0x000B FFFF
Flash ECC Locations
TI OTP ECC
128 x 16
128 x 16
1K x 16
1K x 16
1K x 16
1K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
1K x 16
1K x 16
1K x 16
1K x 16
0x0107 0000
0x0107 1000
0x0108 0000
0x0108 0400
0x0108 0800
0x0108 0C00
0x0108 1000
0x0108 2000
0x0108 3000
0x0108 4000
0x0108 5000
0x0108 6000
0x0108 7000
0x0108 7400
0x0108 7800
0x0108 7C00
0x0107 007F
0x0107 107F
0x0108 03FF
0x0108 07FF
0x0108 0BFF
0x0108 0FFF
0x0108 1FFF
0x0108 2FFF
0x0108 3FFF
0x0108 4FFF
0x0108 5FFF
0x0108 6FFF
0x0108 73FF
0x0108 77FF
0x0108 7BFF
0x0108 7FFF
User OTP ECC
Flash ECC (Sector 0)
Flash ECC (Sector 1)
Flash ECC (Sector 2)
Flash ECC (Sector 3)
Flash ECC (Sector 4)
Flash ECC (Sector 5)
Flash ECC (Sector 6)
Flash ECC (Sector 7)
Flash ECC (Sector 8)
Flash ECC (Sector 9)
Flash ECC (Sector 10)
Flash ECC (Sector 11)
Flash ECC (Sector 12)
Flash ECC (Sector 13)
(1) CPU1 User OTP is used for security (DCSM) configuration; so, it is not available for general-purpose use. CPU2 User OTP is available
for general-purpose use.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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8.3.3 EMIF Chip Select Memory Map
The EMIF1 memory map is the same for both CPU subsystems. EMIF2 is available only on the CPU1
subsystem. The EMIF memory map is shown in the EMIF Chip Select Memory Map table.
Table 8-3. EMIF Chip Select Memory Map
START
EMIF CS
EMIF1 CS0n - Data(1)
SIZE(3)
END ADDRESS
CLA ACCESS
DMA ACCESS
ADDRESS
0x8000 0000
0x0020 0000
0x0010 0000
0x0030 0000
0x0038 0000
0x9000 0000
0x0000 2000
256M x 16
1M x 16
0x8FFF FFFF
0x002F FFFF
0x002F FFFF
0x0037 FFFF
0x003D FFFF
0x91FF FFFF
0x0000 2FFF
Yes
Yes
Yes
Yes
Yes
EMIF1 CS0n - Program + Data(1)
EMIF1 CS2n - Program + Data
EMIF1 CS3n - Program + Data
EMIF1 CS4n - Program + Data
EMIF2 CS0n - Data(2)
2M x 16
512K x 16
393K x 16
32M x 16
4K x 16
EMIF2 CS2n - Program + Data(2)
Yes (Data only)
(1) Dual Map - When EMIF1 CS0n is mapped at address 0x2x_xxxx, EMIF1 CS2n is only avaialble from 0x10_0000 to 0x1F_FFFF (1M x
16).
(2) Only on the CPU1 subsystem.
(3) Available memory size listed in this table is the maximum possible size assuming 32-bit memory. This may not apply to other memory
sizes because of pin mux setting.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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8.3.4 CM Memory Map
The CM Memory Map table shows the CM memory map.
Table 8-4. CM Memory Map
START
ADDRESS
µDMA
ACCESS
ENET DMA
ACCESS
ECC/
PARITY
ACCESS
PROTECTION
MEMORY
Boot ROM
SIZE
END ADDRESS
SECURITY
64K x 8
32K x 8
512K x 8
2K x 8
0x0000 0000
0x0001 0000
0x0020 0000
0x0038 0000
0x003C 0000
0x1FFF C000
0x1FFF E000
0x2000 0000
0x2000 4000
0x2000 8000
0x2000 C000
0x2001 0000
0x2008 0000
0x2008 0800
0x2008 2000
0x2008 2800
0x2008 4000
0x2008 4800
0x2008 6000
0x2008 6800
0x2200 0000
0x4007 2000
0x4007 6000
0x4007 8000
0x400B 1000
0x0000 FFFF
0x0001 7FFF
0x0027 FFFF
0x0038 07FF
0x003C 07FF
0x1FFF DFFF
0x1FFF FFFF
0x2000 3FFF
0x2000 7FFF
0x2000 BFFF
0x2000 FFFF
0x2001 3FFF
0x2008 07FF
0x2008 0FFF
0x2008 27FF
0x2008 2FFF
0x2008 47FF
0x2008 4FFF
0x2008 67FF
0x2008 6FFF
0x23FF FFFF
0x4007 2FFF
0x4007 6FFF
0x4007 C3FF
0x400B 4FFF
Parity
Parity
ECC
Yes(1)
Yes(1)
Yes(1)
Yes(1)
Yes(1)
Yes(1)
Yes(1)
Yes(1)
Yes(1)
Yes(1)
Yes(1)
Yes(1)
Yes(1)
Yes(1)
Yes(1)
Yes(1)
Yes(1)
Yes(1)
Yes(1)
Yes(1)
Yes(1)
Yes(1)
Yes(1)
Yes(1)
Yes(1)
Secure ROM
Yes
Yes
Flash
TI OTP(2)
ECC
USER OTP
2K x 8
ECC
C1 RAM
8K x 8
Parity
Parity
Parity
Parity
Parity
Parity
ECC
Yes
Yes
C0 RAM
8K x 8
S0 RAM
16K x 8
16K x 8
16K x 8
16K x 8
16K x 8
2K x 8
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
S1 RAM
S2 RAM
S3 RAM
E0 RAM
CPU1 to CM MSGRAM0
CPU1 to CM MSGRAM1
CM to CPU1 MSGRAM0
CM to CPU1 MSGRAM1
CPU2 to CM MSGRAM0
CPU2 to CM MSGRAM1
CM to CPU2 MSGRAM0
CM to CPU2 MSGRAM1
Bit Band RAM Zone
CAN A Message RAM
CAN B Message RAM
MCAN Message RAM
EtherCAT RAM (direct access)
Parity
Parity
Parity
Parity
Parity
Parity
Parity
Parity
Parity
Parity
Parity
ECC
Yes
Yes
Yes
Yes
2K x 8
2K x 8
2K x 8
2K x 8
2K x 8
2K x 8
2K x 8
32M x 8
4K x 8
4K x 8
17K x 8
16K x 8
Yes
Parity
(1) Access protection is done via MPU.
(2) TI OTP is for TI internal use only.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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8.3.5 CM Flash Memory Map
The CM Flash Memory Map table shows the CM Flash memory map.
Table 8-5. CM Flash Memory Map
SECTOR
SIZE
START ADDRESS
END ADDRESS
OTP Sectors
TI OTP
2K x 8
2K x 8
0x0038 0000
0x003C 0000
0x0038 07FF
0x003C 07FF
User OTP(1)
Sectors
Sector 0
Sector 1
Sector 2
Sector 3
Sector 4
Sector 5
Sector 6
Sector 7
Sector 8
Sector 9
Sector 10
Sector 11
Sector 12
Sector 13
16K x 8
16K x 8
16K x 8
16K x 8
64K x 8
64K x 8
64K x 8
64K x 8
64K x 8
64K x 8
16K x 8
16K x 8
16K x 8
16K x 8
0x0020 0000
0x0020 4000
0x0020 8000
0x0020 C000
0x0021 0000
0x0022 0000
0x0023 0000
0x0024 0000
0x0025 0000
0x0026 0000
0x0027 0000
0x0027 4000
0x0027 8000
0x0027 C000
0x0020 3FFF
0x0020 7FFF
0x0020 BFFF
0x0020 FFFF
0x0021 FFFF
0x0022 FFFF
0x0023 FFFF
0x0024 FFFF
0x0025 FFFF
0x0026 FFFF
0x0027 3FFF
0x0027 7FFF
0x0027 BFFF
0x0027 FFFF
Flash ECC Locations
TI OTP ECC
256 x 8
256 x 8
2K x 8
2K x 8
2K x 8
2K x 8
8K x 8
8K x 8
8K x 8
8K x 8
8K x 8
8K x 8
2K x 8
2K x 8
2K x 8
2K x 8
0x0088 0000
0x0088 8000
0x0080 0000
0x0080 0800
0x0080 1000
0x0080 1800
0x0080 2000
0x0080 4000
0x0080 6000
0x0080 8000
0x0080 A000
0x0080 C000
0x0080 E000
0x0080 E800
0x0080 F000
0x0080 F800
0x0088 00FF
0x0088 80FF
0x0080 07FF
0x0080 0FFF
0x0080 17FF
0x0080 1FFF
0x0080 3FFF
0x0080 5FFF
0x0080 7FFF
0x0080 9FFF
0x0080 BFFF
0x0080 DFFF
0x0080 E7FF
0x0080 EFFF
0x0080 F7FF
0x0080 FFFF
User OTP ECC
Flash ECC (Sector 0)
Flash ECC (Sector 1)
Flash ECC (Sector 2)
Flash ECC (Sector 3)
Flash ECC (Sector 4)
Flash ECC (Sector 5)
Flash ECC (Sector 6)
Flash ECC (Sector 7)
Flash ECC (Sector 8)
Flash ECC (Sector 9)
Flash ECC (Sector 10)
Flash ECC (Sector 11)
Flash ECC (Sector 12)
Flash ECC (Sector 13)
(1) CM User OTP is available for general-purpose use.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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8.3.6 Memory Types
8.3.6.1 Dedicated RAM (Mx and Dx RAM)
The CPU subsystem has four dedicated ECC-capable RAM blocks: M0, M1, D0, and D1. M0/M1 memories are
small nonsecure blocks that are tightly coupled with the CPU (that is, only the CPU has access to them). D0/D1
memories are secure blocks and also have the access-protection feature (CPU write/CPU fetch protection).
8.3.6.2 Local Shared RAM (LSx RAM)
RAM blocks which are dedicated to each subsystem and are accessible to its CPU and CLA only, are called
local shared RAMs (LSx RAMs).
All LSx RAM blocks have ECC. These memories are secure and have the access protection (CPU write/CPU
fetch) feature.
By default, these memories are dedicated to the CPU only, and the user could choose to share these memories
with the CLA by configuring the MSEL_LSx bit field in the LSxMSEL registers appropriately.
Table 8-6 lists the master access for the LSx RAM.
Table 8-6. Master Access for LSx RAM
(With Assumption That all Other Access Protections are Disabled)
MSEL_LSx
CLAPGM_LSx
CPU ALLOWED ACCESS CLA ALLOWED ACCESS
COMMENT
LSx memory is configured
as CPU dedicated RAM.
00
X
All
All
–
Data Read
Data Write
LSx memory is shared
between CPU and CLA1.
01
01
0
1
Emulation Read
Emulation Write
LSx memory is CLA1
program memory.
Fetch Only
8.3.6.3 Global Shared RAM (GSx RAM)
RAM blocks which are accessible from both the CPU and DMA are called global shared RAMs (GSx RAMs).
Each shared RAM block can be owned by either CPU subsystem based on the configuration of respective bits in
the GSxMSEL register.
All GSx RAM blocks have parity.
When a GSx RAM block is owned by a CPU subsystem, the CPUx and CPUx.DMA will have full access to that
RAM block whereas the other CPUy and CPUy.DMA will only have read access (no fetch/write access).
Table 8-7 lists the master access for the GSx RAM.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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Table 8-7. Master Access for GSx RAM
(With Assumption That all Other Access Protections are Disabled)
INSTRUCTION
FETCH
CPUx.DMA
WRITE
GSxMSEL
CPU
READ
WRITE
CPUx.DMA READ
CPU1
CPU2
CPU1
CPU2
Yes
–
Yes
Yes
Yes
Yes
Yes
–
Yes
Yes
Yes
Yes
Yes
–
0
1
–
–
–
Yes
Yes
Yes
The GSx RAMs have access protection (CPU write/CPU fetch/DMA write).
8.3.6.4 CPU Message RAM (CPU MSGRAM)
These RAM blocks can be used to share data between CPU1 and CPU2. Since these RAMs are used for
interprocessor communication, they are also called IPC RAMs. The CPU MSGRAMs have CPU/DMA read/write
access from its own CPU subsystem, and CPU/DMA read only access from the other subsystem.
This RAM has parity.
8.3.6.5 CLA Message RAM (CLA MSGRAM)
These RAM blocks can be used to share data between the CPU and CLA. The CLA has read and write access
to the CLA-to-CPU MSGRAM. The CPU has read and write access to the CPU-to-CLA MSGRAM. The CPU and
CLA both have read access to both MSGRAMs. This RAM has parity.
8.3.6.6 CLA - DMA Message RAM (CLA-DMA MSGRAM)
These RAM blocks can be used to share data between the DMA and CLA. The CLA has read and write access
to the CLA-to-DMA MSGRAM. The DMA has read and write access to the DMA-to-CLA MSGRAM. The DMA
and CLA both have read access to both MSGRAMs. This RAM has parity.
8.3.6.7 CPUx - CM Message RAM (CPUx-CM MSGRAM)
These RAM blocks can be used to share data between CPU1/CPU2 and the CM. CPU1/CPU2 has read and
write access to the CPUx-to-CM MSGRAM. The CM has read and write access to the CM-to-CPUx MSGRAM.
CPUx and the CM both have read access to both MSGRAMs. This RAM has parity.
8.3.6.8 Dedicated RAM (C0/C1 RAM)
The CM subsystem has two dedicated RAM blocks: C0 and C1. These RAM blocks are tightly coupled with the
Cortex-M4 (that is, only the CPU has access to them) and are connected via the ICODE/DCODE bus. These
RAM blocks have an interleaving feature to improve performance. These RAMs have parity.
8.3.6.9 Shared RAM (E0 and Sx RAM)
The CM subsystem has shared RAMs that are accessible from the Cortex-M4 as well as other masters like
µDMA and EtherNET DMA. These RAMs are connected via the system bus. These RAMs have an interleaving
feature to improve performance. There are two types of shared RAM:
•
•
E0 – This shared RAM block has ECC.
Sx – This shared RAM block has parity.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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8.4 Identification
Table 8-8 lists the Device Identification Registers.
Table 8-8. Device Identification Registers
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
Device part identification number
TMS320F28388D
TMS320F28386D
TMS320F28384D
TMS320F28388S
TMS320F28386S
TMS320F28384S
Silicon revision number
Revision 0
0x03FF 0300
0x03FD 0300
0x03FB 0300
0x03FF 0400
0x03FD 0400
0x03FB 0400
PARTIDH
REVID
0x0005 D00A
2
0x0005 D00C
0x0007 020C
0x0007 0223
2
2
1
0x0000 0000
0x0000 0001
Revision A
Unique identification number. This number is different on each
individual device with the same PARTIDH. This can be used as
a serial number in the application. This number is present only
on TMS devices.
UID_UNIQUE
CPU identification number
CPU1
0xXX01
CPU ID
JTAGID
CPU2
0xXX02
0x0038 0446
N/A
1
CM
0xXX03
N/A
JTAG Device ID
0x0BB4 002F
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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8.5 Bus Architecture – Peripheral Connectivity
The C28x Bus Master Peripheral Access table provides a broad view of the peripheral and configuration register
accessibility from each bus master on the C28x. Peripherals can be individually assigned to the CPU1 or CPU2
subsystem (for example, ePWM can be assigned to CPU1 and eQEP assigned to CPU2).
Table 8-9. C28x Bus Master Peripheral Access
PERIPHERALS (BY BUS ACCESS TYPE)
CPU1.DMA
CPU1.CLA1
CPU1
CPU2
CPU2.CLA1
CPU2.DMA
Peripherals that can be assigned to CPU1 or CPU2 and have Secondary Masters
Peripheral Frame 1:
- ePWM
- SDFM
- eCAP(1)
Y
Y
Y
Y
Y
Y
Y
Y
- eQEP(1)
- CMPSS(1)
- DAC(1)
- HRPWM
Peripheral Frame 2:
- SPI
- McBSP
- FSI
Y
Y
Y
Y
- PMBus
Peripherals that can be assigned to CPU1 or CPU2 subsystems
SCI
Y
Y
Y
Y
Y
Y
Y
I2C
CAN(5)
Y
Y
Y
Y
Y
Y
Y
ADC Configuration
EMIF1
Y
Y
Peripherals and Device Configuration Registers only on CPU1 subsystem
EMIF2
Y
Y
Y
Y
Y
USB(5)
EtherCAT(5)
DCC
Y
Y
Device Capability, Peripheral Reset, Peripheral
CPU Select
Y
GPIO Pin Mapping and Configuration
Analog System Control
Y
Y
Y
Reset Configuration
Accessible by only one CPU at a time with Semaphore
Clock and PLL Configuration
Y
Y
Peripherals and Registers with Unique Copies of Registers for each CPU and CLA Master(2)
System Configuration (WD, NMIWD, LPM,
Peripheral Clock Gating)
Y
Y
Flash Configuration(3)
CPU Timers
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
DMA and CLA Trigger Source Select
ERAD
GPIO Data(4)
Y
Y
Y
Y
ADC Results
Y
Y
(1) These modules are on a Peripheral Frame with DMA access; however, they cannot trigger a DMA transfer.
(2) Each CPUx and CPUx.CLA1 can only access its own copy of these registers.
(3) At any given time, only one CPU can perform program or erase operations on the Flash.
(4) The GPIO Data Registers are unique for each CPUx and CPUx.CLAx. When the GPIO Pin Mapping Register is configured to assign a
GPIO to a particular master, the respective GPIO Data Register will control the GPIO.
(5) Accessible from CM as well.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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The CM Bus Master Peripheral Access table provides details about peripheral sharing between CPUx and the
CM subsystem. It also provides details about accessibility from different masters within the CM subsystem to
peripherals that are only accessible from the CM subsystem. Peripherals can be individually assigned to CPUx
or to the CM subsystem (for example, CAN can be assigned to CPUx and USB assigned to CM).
Table 8-10. CM Bus Master Peripheral Access
ETHERNET
DMA
CPU1
SUBSYSTEM
CPU2
SUBSYSTEM
PERIPHERALS (BY BUS ACCESS TYPE)
µDMA
M4
Peripherals that can be assigned to CM, CPU1, or CPU2 subsystem
CAN
Y
Y
Y
Y
Peripherals that can be assigned to CM or CPU1 subsystem
EtherCAT
USB
Y
Y
Y
Y
Y
Y
Peripherals and System Registers only on CM subsystem
AES
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
GCRC
CM-I2C
CM-UART
SSI
EtherNet
MCAN (CAN-FD)
GPIO Data
Peripheral Reset
CM System Configuration (WD, NMIWD, LPM,
Peripheral Clock Gating)
Y
Flash Configuration
CPU Timers
µDMA
Y
Y
Y
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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8.6 Boot ROM and Peripheral Booting
On every reset, the device executes a boot sequence in the ROM, depending on the reset type and boot
configuration. This sequence initializes the device to run the application code. For CPU1, the boot ROM also
contains peripheral bootloaders that can be used to load an application into RAM. These bootloaders can be
disabled for safety or security purposes.
Table 8-11 summarizes available boot features across CPU1, CPU2, and CM. Table 8-12 lists the sizes of the
various ROMs on the device.
Table 8-11. Boot System Overview
BOOT FEATURE
Initiate boot process
CPU1 (MASTER)
Device Reset
GPIOs
CPU2
CM
CPU1 Application
IPC Register
CPU1 Application
IPC Register
Boot mode selection
Supported boot modes:
•
•
•
Flash boot
Yes
Yes
Yes
Secure Flash boot
RAM boot
Boot to User OTP
No
No
Yes
Yes
No
Yes
Yes
No
Copy from IPC Message RAM and
boot to RAM
Peripheral boot loader support
Yes
Table 8-12. ROM Memory
ROM
CPU1 SIZE
192KB
64KB
CPU2 SIZE
CM SIZE
64KB
32KB
N/A
Unsecure boot ROM
Secure ROM
64KB
64KB
CLA data ROM
8KB
8KB
8.6.1 Device Boot
This section describes the general boot ROM procedure each time a CPU core is reset. CPU1 is the master and
always boots first. Once CPU1 boots to the application, then the user's application code in CPU1 can configure
the CPU2/CM boot IPC registers and release CPU2/CM from reset to boot. Table 8-13, Table 8-14, and Table
8-15 list the general boot-up procedures for each core.
During boot, each CPU's boot ROM code updates a boot status location in RAM that details the actions taken
during this process. Additionally, CPU2 writes the boot status to the CPU2TOCPU1IPCBOOTSTS register and
CM writes to CMTOCPU1IPCBOOTSTS to communicate the statuses to CPU1.
For more details, see the Boot Status information section of the TMS320F2838x Real-Time Microcontrollers
Technical Reference Manual.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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Table 8-13. CPU1 Boot ROM Procedure
STEP
CPU1 ACTION
After reset, check for HWBIST reset. If there is a HWBIST reset, immediately branch and return to the user
application. If there is no HWBIST reset, then continue boot and check the FUSE error register for any errors
and handle accordingly.
1
2
3
4
5
6
Clock configuration and flash power up
Peripheral trimming and device configuration registers are loaded from OTP.
On power-on reset (POR), all CPU1 RAMs are initialized.
Nonmaskable interrupt (NMI) handling is enabled and DCSM initialization is performed.
Device calibration is performed; trimming the specified peripherals with set OTP values.
Determine if polling the GPIO pins are needed for determining the boot mode and, if so, read the boot mode
GPIO pins to determine the boot mode to run.
7
8
Based on the boot mode and options, the appropriate boot sequence is executed. For a flow chart of the CPU1
boot sequences, see the CPU1 Device Boot Flow figure in the TMS320F2838x Real-Time Microcontrollers
Technical Reference Manual.
Table 8-14. CPU2 Boot ROM Procedure
STEP
CPU2 ACTION
1
CPU2 is released from reset by CPU1 application.
Once CPU1TOCPU2IPCFLG0 is set, read the CPU1TOCPU2IPCBOOTMODE register. If it is not set correctly
or has an invalid value, the IPC error command is sent to CPU1, and the CPU2 core will enter an infinite loop
and will not continue booting until the user corrects the register values and reset the CPU2.
2
3
4
5
Flash power up
On POR, all CPU2 RAMs are initialized.
NMI handling is enabled.
Based on the boot mode set in the CPU1TOCPU2IPCBOOTMODE register, CPU2 either enters the "wait for
command" mode to wait for a future CPU1 boot mode command, or CPU2 executes the requested boot
sequence. For a flow chart of the CPU2 boot sequences, see the CPU2 Boot Flow figure in the TMS320F2838x
Real-Time Microcontrollers Technical Reference Manual.
6
Table 8-15. CM Boot ROM Procedure
STEP
CM ACTION
1
CM is released from reset by the CPU1 application.
Once CPU1TOCMIPCFLG0 is set, read the CPU1TOCMIPCBOOTMODE register. If it is not set correctly or
has an invalid value, the IPC error command is sent to CPU1, and the CM will enter an infinite loop and will not
continue booting until the user corrects the register values and reset the CM.
2
3
4
5
Flash power up
On POR, all CM RAMs are initialized.
NMI handling is enabled.
Based on the boot mode set in the CPU1TOCPU2IPCBOOTMODE register, CM either enters the "wait for
command" mode to wait for a future CPU1 boot mode command, or CM executes the requested boot
sequence. For a flow chart of the CM boot sequences, see the CM Boot Flow figure in the TMS320F2838x
Real-Time Microcontrollers Technical Reference Manual.
6
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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8.6.2 Device Boot Modes
This section explains the default boot modes, as well as all the available boot modes, supported on this device.
The CPU1 boot ROM uses the boot-mode select, general-purpose input/output (GPIO) pins to determine the
boot mode configuration. The CPU2 boot ROM uses the CPU1TOCPU2IPCBOOTMODE register to determine
the boot mode configuration. The CM boot ROM uses the CPU1TOCMIPCBOOTMODE register to determine
the boot mode configuration.
Table 8-16 lists the CPU1 boot mode options available for selection by the default boot-mode select pins. Users
have the option to program the device to customize the boot modes selectable in the boot-up table as well as the
boot-mode select pin GPIOs used.
All the available boot modes on the device are listed in Table 8-18.
Table 8-16. Device Default Boot Modes for CPU1
GPIO72
GPIO84
BOOT MODE
(DEFAULT BOOT MODE SELECT PIN 1)
(DEFAULT BOOT MODE SELECT PIN 0)
Parallel IO
SCI/Wait Boot(1)
CAN
0
0
1
1
0
1
0
1
Flash/USB(2)
(1) SCI boot mode can be used as a wait boot mode as long as SCI continues to wait for an 'A' or 'a' during the SCI autobaud lock
process.
(2) On an unprogrammed device, selecting flash boot when the default flash entry address is unprogrammed will switch the boot mode
from flash boot to USB boot. For more details, see Table 8-17.
Table 8-17. CPU1 Flash-to-USB Boot Decision Table
VALUE AT FLASH ENTRY POINT
REASON FOR VALUE
REALIZED BOOT MODE
ADDRESS
0x00000000
Flash is locked/secured
Flash is not programmed
Flash is programmed
Boot to Flash
USB Boot
0xFFFFFFFF
Any other value
Boot to Flash
Note
The switch from flash boot mode to USB boot mode when flash is locked/secured or not programmed
is only available as part of the default boot mode table on an unprogrammed device. Once a custom
boot table is programmed in OTP or RAM, a selection of flash boot mode will not switch to USB boot
even when the flash is unprogrammed.
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Table 8-18. All Available Boot Modes
BOOT MODE
Parallel IO
SCI / Wait
CAN
CPU SUPPORT
DETAILS
CPU1
CPU1
CPU1
Flash
CPU1, CPU2, CM
For functional details of the boot modes, see the Boot
Modes section of the TMS320F2838x Real-Time
Microcontrollers Technical Reference Manual.
Wait
CPU1, CPU2, CM
RAM
SPI
CPU1, CPU2, CM
CPU1
For boot table values and GPIOs for the boot modes, see
Section 8.6.4.
I2C
USB
CPU1
CPU1
Secure Flash
User OTP
CPU1, CPU2, CM
CPU2, CM
CPU2, CM
IPC Message Copy to RAM
Note
All the peripheral boot modes that are supported use the first instance of the peripheral module (SCIA,
SPIA, I2CA, CANA, and so forth). Whenever these boot modes are referred to in this section, such as
SCI boot, it is actually referring to the first module instance, which means the SCI boot on the SCIA
port. The same applies to the other peripheral boots.
8.6.3 Device Boot Configurations
This device supports from 0 boot-mode select pin to up to 3 boot-mode select pins as well as from 1 configured
boot mode to up to 8 configured boot modes.
To change and configure the device from the default settings to custom settings for your application, do the
following steps:
1. Determine all the various ways you want the application to be able to boot. (For example: Primary boot option
of Flash boot for your main application, secondary boot option of CAN boot for firmware updates, tertiary boot
option of SCI boot for debugging, and so forth.)
2. Based on the number of boot modes needed, determine how many boot-mode select pins (BMSPs) are
required to select between your selected boot modes. (For example: 2 BMSPs are required to select between
3 boot-mode options.)
3. Assign the required BMSPs to a physical GPIO pin. (For example, BMSP0 to GPIO50, BMSP1 to GPIO51,
and BMSP2 left as default which is disabled.) For details on performing these configurations, see the
Configuring Boot Mode Pins for CPU1 section of the TMS320F2838x Real-Time Microcontrollers Technical
Reference Manual.
4. Assign the determined boot mode definitions to indexes in your custom boot table that correlate to the
decoded value of the BMSPs. (For example, BOOTDEF0 = Boot to Flash, BOOTDEF1 = CAN Boot,
BOOTDEF2 = SCI Boot; all other BOOTDEFx are left as default/nothing.) For details on setting up and
configuring the custom boot mode table, see the Configuring Boot Mode Table Options for CPU1 section of
the TMS320F2838x Real-Time Microcontrollers Technical Reference Manual.
For example use cases on how to configure the BMSPs and custom boot tables, see the Boot Mode Example
Use Cases section of the TMS320F2838x Real-Time Microcontrollers Technical Reference Manual.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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8.6.4 GPIO Assignments for CPU1
This section details the GPIOs and boot option values used for each CPU1 boot mode set in the BOOT_DEF
memory location located at Z1-OTP-BOOTDEF-LOW/ Z2-OTP-BOOTDEF-LOW and Z1-OTP-BOOTDEF-HIGH/
Z2-OTP-BOOTDEF-HIGH. See the Configuring Boot Mode Table Options for CPU1 section of the
TMS320F2838x Real-Time Microcontrollers Technical Reference Manual on how to configure BOOT_DEF.
When selecting a boot mode option, be sure to verify that the necessary pins are available in the pin mux
options for the specific device package being used.
Note
These configurations only apply to CPU1. For details on configuring CPU2 and CM boot modes, see
the Booting CPU2 and CM section of the TMS320F2838x Real-Time Microcontrollers Technical
Reference Manual.
Table 8-19. SCI Boot Options
OPTION
BOOTDEF VALUE
SCITXDA GPIO
SCIRXDA GPIO
GPIO28
0 (default)
0x01
0x21
0x41
0x61
0x81
0xA1
0xC1
GPIO29
1
2
3
4
5
6
GPIO84
GPIO85
GPIO36
GPIO35
GPIO42
GPIO43
GPIO65
GPIO64
GPIO135
GPIO8
GPIO136
GPIO9
Table 8-20. CAN Boot Options
OPTION
BOOTDEF VALUE
CANTXA GPIO
CANRXA GPIO
GPIO36
0 (default)
0x02
0x22
0x42
0x62
0x82
0xA2
GPIO37
1
2
3
4
5
GPIO71
GPIO70
GPIO63
GPIO62
GPIO19
GPIO18
GPIO4
GPIO5
GPIO31
GPIO30
Table 8-21. I2C Boot Options
OPTION
BOOTDEF VALUE
SDAA GPIO
GPIO91
GPIO32
GPIO42
GPIO0
SCLA GPIO
GPIO92
GPIO33
GPIO43
GPIO1
0
1
2
3
4
0x07
0x27
0x47
0x67
0x87
GPIO104
GPIO105
Table 8-22. USB Boot Options
OPTION
BOOTDEF VALUE
USBDM GPIO
USBDP GPIO
0 (default)
0x09
GPIO42
GPIO43
Table 8-23. RAM Boot Options
RAM ENTRY POINT
(ADDRESS)
OPTION
BOOTDEF VALUE
0
0x05
0x0000 0000
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Table 8-24. Flash Boot Options
FLASH ENTRY POINT
(ADDRESS)
OPTION
BOOTDEF VALUE
FLASH SECTOR
0 (default)
0x03
0x23
0x43
0x63
0x0008 0000
0x0008 8000
0x000A 8000
0x000B E000
CPU1 Bank 0 Sector 0
CPU1 Bank 0 Sector 4
CPU1 Bank 0 Sector 8
CPU1 Bank 0 Sector 13
1
2
3
Table 8-25. Secure Flash Boot Options
FLASH ENTRY POINT
OPTION
BOOTDEF VALUE
(ADDRESS)
FLASH SECTOR
0
1
2
3
0x0A
0x2A
0x4A
0x6A
0x0008 0000
0x0008 8000
0x000A 8000
0x000B E000
CPU1 Bank 0 Sector 0
CPU1 Bank 0 Sector 4
CPU1 Bank 0 Sector 8
CPU1 Bank 0 Sector 13
Table 8-26. Wait Boot Options
OPTION
BOOTDEF VALUE
WATCHDOG
0
1
0x04
0x24
Enabled
Disabled
Table 8-27. SPI Boot Options
OPTION
BOOTDEF VALUE
SPISIMOA
GPIO58
GPIO16
GPIO32
GPIO16
GPIO54
SPISOMIA
GPIO59
GPIO17
GPIO33
GPIO17
GPIO55
SPICLKA
SPISTEA
GPIO61
GPIO19
GPIO35
GPIO57
GPIO57
0
1
2
3
4
0x06
0x26
0x46
0x66
0x86
GPIO60
GPIO18
GPIO34
GPIO56
GPIO56
Table 8-28. Parallel Boot Options
OPTION
BOOTDEF VALUE
D0-D7 GPIO
D0 - GPIO89
D1 - GPIO90
D2 - GPIO58
D3 - GPIO59
D4 - GPIO60
D5 - GPIO61
D6 - GPIO62
D7 - GPIO88
DSP CONTROL GPIO
HOST CONTROL GPIO
0 (default)
0x0
GPIO91
GPIO92
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TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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8.7 Dual Code Security Module (DCSM)
The dual code security module (DCSM) is a security feature incorporated in this device. It prevents access and
visibility to on-chip secure memories (and other secure resources) by unauthorized persons. It also prevents
duplication and reverse-engineering of proprietary code. The term “secure” means that access to on-chip secure
memories and resources is blocked. The term “unsecure” means that access is allowed; that is, the contents of
the memory could be read by any means (for example, through a debugging tool such as Code Composer
Studio™).
There are two security zones, Zone1 (Z1) and Zone2 (Z2). Unlike earlier C2000 devices where each CPU
subsystem had two security zones, on this device, both security zones are shared by each CPU subsystem. This
means secure resources from each CPU subsystem are allocated to Zone1 or Zone2. All the security
configurations are controlled by the CPU1 subsystem only (programmed in CPU1 USER OTP), but other CPU
subsystems have access to these configurations via their own memory map registers.
The security of each zone is ensured by its own 128-bit password (CSM password). The password for each zone
is stored in CPU1 USER OTP memory location based on a zone-specific link pointer. The link pointer value can
be changed to program a different set of security settings (including passwords) in OTP.
ꢀ
Code Security Module Disclaimer
ꢀ
THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED TO
PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY AND IS
WARRANTED BY TEXAS INSTRUMENTS (TI), IN ACCORDANCE WITH ITS STANDARD TERMS
AND CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS FOR THE WARRANTY
PERIOD APPLICABLE FOR THIS DEVICE.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY
CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH
ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR
OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY
OR FITNESS FOR A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,
INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF
YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED
TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR
OTHER ECONOMIC LOSS.
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TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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8.8 C28x (CPU1/CPU2) Subsystem
8.8.1 C28x Processor
The CPU is a 32-bit fixed-point processor. This device draws from the best features of digital signal processing;
reduced instruction set computing (RISC); and microcontroller architectures, firmware, and tool sets.
The CPU features include a modified Harvard architecture and circular addressing. The RISC features are
single-cycle instruction execution, register-to-register operations, and modified Harvard architecture. The
microcontroller features include ease of use through an intuitive instruction set, byte packing and unpacking, and
bit manipulation. The modified Harvard architecture of the CPU enables instruction and data fetches to be
performed in parallel. The CPU can read instructions and data while it writes data simultaneously to maintain the
single-cycle instruction operation across the pipeline. The CPU does this over six separate address/data buses.
For more information on CPU architecture and instruction set, see the TMS320C28x CPU and Instruction Set
Reference Guide. For more information on the C28x Floating Point Unit (FPU), Trigonometric Math Unit, and
Cyclic Redundancy Check (VCRC) instruction sets, see the TMS320C28x Extended Instruction Sets Technical
Reference Manual. A brief overview of the FPU, TMU, and VCRC are provided here.
8.8.1.1 Floating-Point Unit
The C28x plus floating-point (C28x+FPU64) processor extends the capabilities of the C28x fixed-point CPU by
adding registers and instructions to support both IEEE single-precision and double-percision floating-point
operations.
Devices with the C28x+FPU64 include the standard C28x register set plus an additional set of floating-point unit
registers. The additional floating-point unit registers are the following:
•
•
•
Eight floating-point Result registers, RnH (where n = 0–7)
Floating-point Status register (STF)
Repeat Block register (RB)
All of the floating-point registers, except the repeat block register, are shadowed. This shadowing can be used in
high-priority interrupts for fast context save and restore of the floating-point registers.
8.8.1.2 Trigonometric Math Unit
The TMU extends the capabilities of a C28x+FPU64 by adding instructions and leveraging existing FPU
instructions to speed up the execution of common trigonometric and arithmetic operations listed in Table 8-29.
Table 8-29. TMU Supported Instructions
INSTRUCTIONS
MPY2PIF32/64 RaH,RbH
C EQIVALENT OPERATION
PIPELINE CYCLES
a = b * 2pi
a = b / 2pi
a = b/c
2/3
2/3
5
DIV2PIF32/64 RaH,RbH
DIVF32/64 RaH,RbH,RcH
SQRTF32/64 RaH,RbH
a = sqrt(b)
a = sin(b*2pi)
5
SINPUF32/64 RaH,RbH
COSPUF32/64 RaH,RbH
ATANPUF32/64 RaH,RbH
QUADF32/64 RaH,RbH,RcH,RdH
4
a = cos(b*2pi)
4
a = atan(b)/2pi
4
Operation to assist in calculating ATANPU2
5
No changes have been made to existing instructions, pipeline or memory bus architecture. All TMU instructions
use the existing FPU register set (R0H to R7H) to carry out their operations.
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TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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8.8.1.3 Fast Integer Division Unit
The Fast Integer Division (FINTDIV) unit of the C28x CPU uniquely supports three types of integer division
(Truncated, Modulus, Euclidean) of varying data type sizes (16/16, 32/16, 32/32, 64/32, 64/64) in unsigned or
signed formats.
•
•
Truncated integer division is naturally supported by C language (/, % operators).
Modulus and Euclidean divisions are variants that are more efficient for control algorithms and are supported
by C intrinsics.
All three types of integer division produce both a quotient and remainder component, are interruptible, and
execute in a minimum number of deterministic cycles (10 cycles for a 32/32 division). In addition, the Fast
Division capabilities of the C28x CPU uniquely support fast execution of floating-point 32-bit (in 5 cycles) and 64-
bit (in 20 cycles) division.
For more information about fast integer division, see the Fast Integer Division – A Differentiated Offering From
C2000™ Product Family Application Report.
8.8.1.4 VCRC Unit
Cyclic redundancy check (CRC) algorithms provide a straightforward method for verifying data integrity over
large data blocks, communication packets, or code sections. The C28x+VCRC can perform 8-bit, 16-bit, 24-bit,
and 32-bit CRCs. For example, the VCRC can compute the CRC for a block length of 10 bytes in 10 cycles. A
CRC result register contains the current CRC, which is updated whenever a CRC instruction is executed.
The following are the CRC polynomials used by the CRC calculation logic of the VCRC:
•
•
•
•
•
•
CRC8 polynomial = 0x07
CRC16 polynomial1 = 0x8005
CRC16 polynomial2 = 0x1021
CRC24 polynomial = 0x5d6dcb
CRC32 polynomial1 = 0x04c11db7
CRC32 polynomial2 = 0x1edc6f41
This module can calculate CRCs for a byte of data in a single cycle. The CRC calculation for CRC8, CRC16,
CRC24, and CRC32 is done byte-wise (instead of computing on a complete 16-bit or 32-bit data read by the
C28x core) to match the byte-wise computation requirement mandated by various standards.
The VCRC Unit also allows the user to provide the size (1b-32b) and value of any polynomial to fit custom CRC
requirements. The CRC execution time increases to three cycles when using a custom polynomial.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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8.8.2 Embedded Real-Time Analysis and Diagnostic (ERAD)
The ERAD module enhances the debug and system-analysis capabilities of the device. The debug and system-
analysis enhancements provided by the ERAD module is done outside of the CPU. The ERAD module consists
of the Enhanced Bus Comparator units and the System Event Counter units.
•
The Enhanced Bus Comparator units are used to generate hardware breakpoints, hardware watch points,
and other output events.
•
The System Event Counter units are used to analyze and profile the system. The ERAD module is accessible
by the debugger and by the application software.
This significantly increases the debug capabilities of many real-time systems. In the TMS320F2838x devices, the
ERAD module contains eight Enhanced Bus Comparator units (which increases the number of Hardware
breakpoints from two to ten) and four System Event Counter units. Figure 8-2 shows the ERAD module.
ERAD
Cyclic Redundancy
Check (CRC) Units
CRC Qualifiers
C28x
Address Bus
Data Bus
Enhanced Bus
Comparator
(EBC) Units
Program Counter
Debug
Triggers
AU1
AU2
Event
Outputs
System Event
Counter
(SEC) Units
System Events
Counter
Events
Figure 8-2. ERAD Overview
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TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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8.8.3 Background CRC-32 (BGCRC)
The Background CRC (BGCRC) module computes a CRC-32 on a configurable block of memory. It
accomplishes this by fetching the specified block of memory during idle cycles (when the CPU, CLA, or DMA is
not accessing the memory block). The calculated CRC-32 value is compared against a golden CRC-32 value to
indicate a pass or fail. In essence, the BGCRC helps identify memory faults and corruption. There are two
BGCRC modules (CPU_CRC and CLA_CRC) per CPU subsystem. The two BGCRC modules differ only in the
memories they test.
The BGCRC module has the following features:
•
•
•
•
•
•
One cycle CRC-32 computation on 32 bits of data
No CPU bandwidth impact for zero wait state memory
Minimal CPU bandwidth impact for non-zero wait state memory
Dual operation modes (CRC-32 mode and scrub mode)
Watchdog timer to time CRC-32 completion
Ability to pause and resume CRC-32 computation
Figure 8-3 shows the memory map of the BGCRC module.
Figure 8-3. BGCRC Memory Map
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TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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8.8.4 Control Law Accelerator (CLA)
The CLA Type-2 is an independent, fully programmable, 32-bit floating-point math processor that brings
concurrent control-loop execution to the C28x family. The low interrupt-latency of the CLA allows it to read ADC
samples "just-in-time." This significantly reduces the ADC sample to output delay to enable faster system
response and higher frequency control loops. By using the CLA to service time-critical control loops, the main
CPU is free to perform other system tasks such as communications and diagnostics.
The control law accelerator extends the capabilities of the C28x CPU by adding parallel processing. Time-critical
control loops serviced by the CLA can achieve low ADC sample to output delay. Thus, the CLA enables faster
system response and higher frequency control loops. Using the CLA for time-critical tasks frees up the main
CPU to perform other system and communication functions concurrently.
The following is a list of major features of the CLA:
•
•
•
C compilers are available for CLA software development.
Clocked at the same rate as the main CPU (SYSCLKOUT).
An independent architecture allowing CLA algorithm execution independent of the main C28x CPU.
– Complete bus architecture:
•
•
Program Address Bus (PAB) and Program Data Bus (PDB)
Data Read Address Bus (DRAB), Data Read Data Bus (DRDB), Data Write Address Bus (DWAB), and
Data Write Data Bus (DWDB)
– Independent 8-stage pipeline
– 16-bit program counter (MPC)
– Four 32-bit result registers (MR0 to MR3)
– Two 16-bit auxiliary registers (MAR0, MAR1)
– Status register (MSTF)
•
Instruction set includes:
– IEEE single-precision (32-bit) floating-point math operations
– Floating-point math with parallel load or store
– Floating-point multiply with parallel add or subtract
– 1/X and 1/sqrt(X) estimations
– Data type conversions
– Conditional branch and call
– Data load/store operations
•
The CLA program code can consist of up to eight tasks or interrupt service routines, or seven tasks and a
main background task.
– The start address of each task is specified by the MVECT registers.
– There is no limit on task size as long as the tasks fit within the configurable CLA program memory space.
– One task is serviced at a time until its completion. There is no nesting of tasks.
– Upon task completion, a task-specific interrupt is flagged within the PIE.
– When a task finishes, the next highest-priority pending task is automatically started.
– The Type-2 CLA can have a main task that runs continuously in the background, while other high-priority
events trigger a foreground task.
•
Task trigger mechanisms:
– C28x CPU through the IACK instruction
– Task1 to Task8: Up to 256 possible trigger sources from peripherals connected to the shared bus on which
the CLA assumes secondary ownership
– Task8 can be set to be the background task, while Tasks 1 to 7 take peripheral triggers.
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TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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•
Memory and shared peripherals:
– Two dedicated message RAMs for communication between the CLA and the main CPU.
– Two dedicated message RAMs for communication between the CLA and the DMA.
– The C28x CPU can map CLA program and data memory to the main CPU space or CLA space.
Figure 8-4 shows the CLA block diagram.
CLA Control
Register Set
MIFR(16)
MIOVF(16)
MPERINT1
to
MPERINT8
CLA_INT1
to
CLA_INT8
From Shared
Peripherals
MICLR(16)
MICLROVF(16)
MIFRC(16)
C28x
CPU
PIE
INT11
INT12
MIER(16)
MIRUN(16)
LVF
LUF
MCTLBGRND(16)
MSTSBGRND(16)
CLA1SOFTINTEN(16)
CLA1INTFRC(16)
SYSCLK
CLA Clock Enable
SYSRS
MVECT1(16)
MVECT2(16)
MVECT3(16)
MVECT4(16)
MVECT5(16)
MVECT6(16)
MVECT7(16)
MVECT8(16)
CPU Read/Write Data Bus
CLA Program
Memory (LSx)
CLA Program Bus
LSxMSEL[MSEL_LSx]
LSxCLAPGM[CLAPGM_LSx]
MVECTBGRND(16)
MVECTBGRNDACTIVE(16)
MPSACTL(16)
MPSA1(32)
CLA Data
Memory (LSx)
MPSA2(32)
MCTL(16)
CLA Message
RAMs
CLA Execution
Register Set
MPC(16)
MSTF(32)
MR0(32)
MR1(32)
MR2(32)
MR3(32)
Shared
Peripherals
MEALLOW
MAR0(16)
MAR1(16)
CPU Read Data Bus
Figure 8-4. CLA Block Diagram
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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8.8.5 Direct Memory Access (DMA)
Each CPU has its own 6-channel DMA module. The DMA module provides a hardware method of transferring
data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for
other system functions. Additionally, the DMA has the capability to orthogonally rearrange the data as it is
transferred as well as “ping-pong” data between buffers. These features are useful for structuring data into
blocks for optimal CPU processing.
The DMA module is an event-based machine, meaning it requires a peripheral or software trigger to start a DMA
transfer. Although it can be made into a periodic time-driven machine by configuring a timer as the DMA trigger
source, there is no mechanism within the module itself to start memory transfers periodically. The DMA module
has six independent DMA channels that can be configured separately. Each channel contains its own
independent PIE interrupt to let the CPU know when a DMA transfer has either started or completed. Five of the
six channels are exactly the same, while Channel 1 has the ability to be configured at a higher priority than the
others. At the heart of the DMA is a state machine and tightly coupled address control logic. It is this address
control logic that allows for rearrangement of the block of data during the transfer as well as the process of ping-
ponging data between buffers.
DMA features include:
•
•
•
•
Six channels with independent PIE interrupts
Each DMA channel can be triggered from multiple peripheral trigger sources independently.
Word Size: 16-bit or 32-bit (SPI limited to 16-bit)
Throughput: 3 cycles/word without arbitration
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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Figure 8-5 shows a device-level block diagram of the DMA.
Message RAM
CPU1.DMA-CLA
Message RAM
CPU1 - CPU2
Message RAM
CPU2.DMA-CLA
Global Shared
GSxRAM
ADC
RESULTS
CPU1. DMA bus
DMA Trigger
Source Selection
CPU1.
C28x
CPU1.
DMA
DMACHSRCSEL1.CHx
DMACHSRCSEL2.CHx
CHx.MODE.PERINTSEL
(x = 1 to 6)
PIE
DMA Trigger sources
DMA Trigger
Source Selection
CPU2.
C28x
CPU2.
DMA
DMACHSRCSEL1.CHx
DMACHSRCSEL2.CHx
CHx.MODE.PERINTSEL
(x = 1 to 6)
PIE
CPU2. DMA bus
Figure 8-5. DMA Block Diagram
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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8.8.6 Interprocessor Communication (IPC) Module
The Interprocessor Communication (IPC) module allows communications between the CPU subsystems.
IPC features include:
•
•
•
•
•
•
Message RAMs
IPC flags and interrupts
IPC command registers
Flash pump semaphore
Clock configuration semaphore
Free-running counter
All IPC features are independent of each other, and most do not require any specific data format. There are also
two registers for boot mode and status communication. For more information on these registers, see the ROM
Code and Peripheral Booting chapter of the TMS320F2838x Real-Time Microcontrollers Technical Reference
Manual.
This device has three cores [one Cortex-M4 core and two C28x cores (CPU1, CPU2)] and three different IPC
modules:
•
•
CPU1_TO_CPU2 IPC architecture (see Figure 8-6)
CPUx_TO_CM IPC architecture (where x = 1, 2) (see Figure 8-7)
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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SET31
CLR31
ACK31
FLG31
CPU1TOCPU2IPCSET[31:0]
CPU1TOCPU2IPCCLR[31:0]
R=0/W=1
R=0/W=1
SET0
CLR0
CPU2TOCPU1IPCACK[31:0]
ACK0
R=0/W=1
ePIE
R
FLG0
CPU1TOCPU2_IPCINTR[3:0]
Gen Int Pulse
(on FLG 0->1)
CPU1TOCPU2IPCFLG[31:0]
CPU1TOCPU2IPCSTS[31:0]
R
CPU1TOCPU2IPCSENDCOM
CPU1TOCPU2IPCSENDADDR
CPU1TOCPU2IPCSENDDATA
CPU1TOCPU2IPCRECVCOM
CPU1TOCPU2IPCRECVADDR
R/W
R/W
R/W
R
R
R
CPU1TOCPU2IPCRECVDATA
R/W
R
CPU1TOCPU2IPCREPLY
CPU2.HALT
CPU1.HALT
R
64-bit Free Run Counter
PLLSYSCLK
R
IPCCOUNTERH/L[31:0]
R
CPU1TOCPU2IPCBOOTMODE
R/W
CPU1
CPU2
R
CPU2TOCPU1IPCBOOTSTS
CPU2TOCPU1IPCBOOTSTS
R/W
SET31
ACK31
CLR31
FLG31
CPU2TOCPU1IPCSET
CPU2TOCPU1IPCCLR
R=0/W=1
R=0/W=1
SET0
CLR0
ACK0
CPU1TOCPU2IPCACK[31:0]
R=0/W=1
FLG0
CPU2TOCPU1_IPCINTR[3:0]
ePIE
Gen Int Pulse
(on FLG 0->1)
CPU2TOCPU1IPCSTS[31:0]
CPU2TOCPU1IPCFLG[31:0]
R
R
R
CPU2TOCPU1IPCRECVCOM
CPU2TOCPU1IPCRECVADDR
CPU2TOCPU1IPCRECVDATA
CPU2TOCPU1IPCSENDCOM
CPU2TOCPU1IPCSENDADDR
R/W
R/W
R/W
R
R
CPU2TOCPU1IPCSENDDATA
CPU1TOCPU2IPCREPLY
R/W
R
Figure 8-6. CPU1_TO_CPU2 IPC Module
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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SET31
CLR31
ACK31
FLG31
CPUxTOCMIPCSET[31:0]
CPUxTOCMIPCCLR[31:0]
R=0/W=1
R=0/W=1
SET0
CLR0
CMTOCPUxIPCACK[31:0]
ACK0
R=0/W=1
NVIC
R
FLG0
CPUxTOCM_IPCINTR[7:0]
Gen Int Pulse
(on FLG 0->1)
CPUxTOCMIPCFLG[31:0]
CPUxTOCMIPCSTS[31:0]
R
CPUxTOCMIPCSENDCOM
CPUxTOCMIPCSENDADDR
CPUxTOCMIPCSENDDATA
R
CPUxTOCMIPCRECVCOM
CPUxTOCMIPCRECVADDR
R/W
R/W
R/W
R
R
R
CPUxTOCMIPCRECVDATA
CMTOCPUxIPCREPLY
R/W
PLLSYSCLK
CPUx.HALT
R
64-bit Free Run Counter
M4.HALT
IPCCOUNTERH/L[31:0]
R
R
CPUxTOCMIPCBOOTMODE
R/W
CPUx
M4
R
CMTOCPU1IPCBOOTSTS
CMTOCPU1IPCBOOTSTS
R/W
SET31
ACK31
CLR31
FLG31
CMTOCPUxIPCSET
CMTOCPUxIPCCLR
R=0/W=1
R=0/W=1
SET0
CLR0
ACK0
CPUxTOCMIPCACK[31:0]
R=0/W=1
FLG0
CMTOCPUx_IPCINTR[3:0]
ePIE
Gen Int Pulse
(on FLG 0->1)
CMTOCPUxIPCSTS[31:0]
CMTOCPUxIPCFLG[31:0]
R
R
R
CMTOCPUxIPCRECVCOM
CMTOCPUxIPCRECVADDR
CMTOCPUxIPCRECVDATA
R/W
CMTOCPUxIPCSENDCOM
CMTOCPUxIPCSENDADDR
R/W
R/W
R/W
R
R
CMTOCPUxIPCSENDDATA
CPUxTOCMIPCREPLY
R
Where,
x can be 1 (or) 2
Figure 8-7. CPUx_to_CM IPC Module
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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8.8.7 C28x Timers
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. The
timers have a 32-bit count-down register that generates an interrupt when the counter reaches zero. The counter
is decremented at the CPU clock speed divided by the prescale value setting. When the counter reaches zero, it
is automatically reloaded with a 32-bit period value.
CPU-Timer 0 is for general use and is connected to the PIE block. CPU-Timer 1 is also for general use and is
connected to INT13 of the CPU. CPU-Timer 2 is reserved for TI-RTOS. It is connected to INT14 of the CPU. If
TI-RTOS is not being used, CPU-Timer 2 is available for general use.
CPU-Timer 2 can be clocked by any one of the following:
•
•
•
•
•
SYSCLK (default)
Internal zero-pin oscillator 1 (INTOSC1)
Internal zero-pin oscillator 2 (INTOSC2)
X1 (XTAL)
AUXPLLCLK
8.8.8 Dual-Clock Comparator (DCC)
There are three Dual-Clock Comparators (DCC0, DCC1, and DCC2) on the device. All three DCCs are only
accessible through CPU1. The DCC module is used for evaluating and monitoring the clock input based on a
second clock, which can be a more accurate and reliable version. This instrumentation is used to detect faults in
clock source or clock structures, thereby enhancing the system's safety metrics.
8.8.8.1 Features
The DCC has the following features:
•
•
•
•
•
Allows the application to ensure that a fixed ratio is maintained between frequencies of two clock signals.
Supports the definition of a programmable tolerance window in terms of the number of reference clock cycles.
Supports continuous monitoring without requiring application intervention.
Supports a single-sequence mode for spot measurements.
Allows the selection of a clock source for each of the counters, resulting in several specific use cases.
8.8.8.2 Mapping of DCCx (DCC0, DCC1, and DCC2) Clock Source Inputs
Table 8-30. DCCx Clock Source0 Table
DCCxCLKSRC0[3:0]
CLOCK NAME
XTAL/X1
0x0
0x1
0x2
0x5
0x6
INTOSC1
INTOSC2
CPU1.SYSCLK
CPU2.SYSCLK
0xC
INPUT XBAR (Output16 of input-xbar)
Reserved
others
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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Table 8-31. DCCx Clock Source1 Table
DCCxCLKSRC1[4:0]
CLOCK NAME
PLLRAWCLK
AUXPLLRAWCLK
INTOSC1
0x0
0x1
0x2
0x3
0x5
0x6
INTOSC2
CMCLK
CPU1.SYSCLK
0x7
0x8
Ethernet RX Clock (ENET_MII_RX_CLK)
CPU2.SYSCLK
Input XBAR (Output15 of the input-xbar)
AUXCLKIN
0x9
0xA
0xB
0xC
0xD
0xE
0xF
EPWMCLK
LSPCLK
Ethercat MII0 RX Clock (ESC_RX0_CLK)
WDCLK
CAN0BITCLK
0x17
others
Ethercat MII1 RX Clock (ESC_RX1_CLK)
Reserved
8.8.9 Nonmaskable Interrupt With Watchdog Timer (NMIWD)
The NMIWD module is used to handle system-level errors. There is an NMIWD module for each CPU. The
conditions monitored are:
•
•
•
•
•
•
•
•
•
•
•
Missing system clock due to oscillator failure
Uncorrectable ECC error on CPU access to flash memory
Uncorrectable ECC or parity error on CPU, CLA, or DMA access to RAM
Parity error on CPU access to ROM
Vector fetch error on the other CPU
CRC Fail error from BGCRC module
Reset request from EtherCAT master or uncorrectable error on access to EtherCAT RAM
CPU1/CPU2 HWBIST error
NMI from ERAD module
CPU1 only: Watchdog or NMI watchdog reset on CPU2
CPU1 only: NMIWD reset on CM (configurable)
If the CPU does not respond to the latched error condition, then the NMI watchdog will trigger a reset after a
programmable time interval. The default time is 65536 SYSCLK cycles.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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8.8.10 Watchdog
The watchdog module is the same as the one on previous TMS320C2000 devices, but with an optional lower
limit on the time between software resets of the counter. This windowed countdown is disabled by default, so the
watchdog is fully backwards-compatible.
The watchdog generates either a reset or an interrupt. It is clocked from the internal oscillator with a selectable
frequency divider.
Figure 8-8 shows the various functional blocks within the watchdog module.
WDCR.WDPRECLKDIV
WDCR.WDPS
WDCR.WDDIS
WDCNTR
8-bit
Watchdog
Counter
WDCLK
(INTOSC1)
WDCLK
Divider
Watchdog
Prescaler
Overflow
1-count
delay
SYSRSn
Clear
Count
WDWCR.MIN
WDKEY (7:0)
Watchdog
Window
Detector
Out of Window
Good Key
Watchdog
Key Detector
55 + AA
WDCR(WDCHK(2:0))
Bad Key
WDRSTn
WDINTn
Generate
512-WDCLK
Output Pulse
1
0
1
Watchdog Time-out
SCSR.WDENINT
Figure 8-8. Windowed Watchdog
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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8.8.11 Configurable Logic Block (CLB)
The C2000 configurable logic block (CLB) is a collection of blocks that can be interconnected using software to
implement custom digital logic functions or enhance existing on-chip peripherals. The CLB is able to enhance
existing peripherals through a set of crossbar interconnections, which provide a high level of connectivity to
existing control peripherals such as enhanced pulse width modulators (ePWM), enhanced capture modules
(eCAP), and enhanced quadrature encoder pulse modules (eQEP). The crossbars also allow the CLB to be
connected to external GPIO pins. In this way, the CLB can be configured to interact with device peripherals to
perform small logical functions such as comparators, or to implement custom serial data exchange protocols.
Through the CLB, functions that would otherwise be accomplished using external logic devices can now be
implemented inside the MCU.
The CLB peripheral is configured through the CLB tool. For more information on the CLB tool, available
examples, application reports and users guide, please refer to the following location in your C2000Ware package
(C2000Ware_2_00_00_03 and higher):
C2000WARE_INSTALL_LOCATION\utilities\clb_tool\clb_syscfg\doc
•
•
•
CLB Tool User's Guide
Designing With the C2000™ Configurable Logic Block (CLB) Application Report
How to Migrate Custom Logic From an FPGA/CPLD to C2000™ Microcontrollers Application Report
The CLB module and its interconnects are shown in Figure 8-9.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
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Figure 8-9. CLB Overview
Absolute encoder protocol interfaces are now provided as Position Manager solutions in the C2000Ware
MotorControl SDK. Configuration files, application programmer interface (API), and use examples for such
solutions are provided with C2000Ware MotorControl SDK. In some solutions, the TI-configured CLB is used
with other on-chip resources, such as the SPI port or the C28x CPU, to perform more complex functionality.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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8.9 Connectivity Manager (CM) Subsystem
The TMS320F2838x supports dual-core C28x architecture along with a new Connectivity Manager subsystem.
The CM subsystem is based on the industry-standard 32-bit Arm® Cortex®-M4 CPU and features a wide variety
of communication peripherals, including EtherCAT, Ethernet, USB, MCAN (CAN-FD), DCAN, UART, SSI, I2C,
and so on. Targeting performance and flexibility, the CM is based on 125-MHz Cortex-M4 architecture and
provides a variety of integrated memories as well as multiple programmable GPIOs.
8.9.1 Arm Cortex-M4 Processor
The Arm Cortex-M4 processor provides a high-performance, low-cost platform that meets the system
requirements of minimal memory implementation, reduced pin count, and low power consumption, while
delivering outstanding computational performance and exceptional system response to interrupts.
The Arm Cortex-M4 processor includes the following:
•
•
•
32-bit Arm Cortex-M4 architecture optimized for small-footprint embedded applications
Arm Cortex-M4 CPU can be operated at maximum frequency of 125 MHz
Arm® Thumb®-2 mixed, 16-/32-bit instruction set delivers the high performance expected of a 32-bit Arm core
in a compact memory size usually associated with 8- and 16-bit devices, typically in the range of a few
kilobytes of memory for microcontroller-class applications
– Single-cycle multiply instruction and hardware divide
– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined peripheral
control
– Unaligned data access, enabling data to be efficiently packed into memory
Fast code execution permits slower processor clock or increases sleep mode time
Harvard architecture characterized by separate buses for instruction and data
Efficient processor core, system and memories
Deterministic, high-performance interrupt handling for time-critical applications
Memory protection unit (MPU) to provide a privileged mode for protected operating system functionality
Enhanced system debug with extensive breakpoint and trace capabilities
•
•
•
•
•
•
8.9.2 Nested Vectored Interrupt Controller (NVIC)
The NVIC multiplexes interrupts from various peripherals into the CM interrupt lines. In essence, the NVIC is the
PIE (Peripheral Interrupt Expansion) equivalent for the CM. The features supported by the NVIC are as follows:
•
•
80 interrupts
A programmable priority level of 0–7 for each interrupt. A higher level corresponds to a lower priority, so level
0 is the highest interrupt priority.
•
•
•
•
•
•
Low-latency exception and interrupt handling.
Level and pulse detection of interrupt signals.
Dynamic reprioritization of interrupts.
Grouping of priority values into group priority and subpriority fields.
Interrupt tail-chaining.
An external nonmaskable interrupt.
For more information about the NVIC, see the Nested Vectored Interrupt Controller (NVIC) section of the
TMS320F2838x Real-Time Microcontrollers Technical Reference Manual.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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8.9.3 Advance Encryption Standard (AES) Accelerator
The AES module provides hardware-accelerated data encryption and decryption operations based on a binary
key. The AES is a symmetric cipher module that supports a 128-, 192-, or 256-bit key in hardware for encryption
and decryption. The AES module is based on a symmetric algorithm, which means that the encryption and
decryption keys are identical. To encrypt data means to convert it from plain text to an unintelligible form called
cipher text. Decrypting cipher text converts previously encrypted data to its original plain text form. The main
features of the AES accelerator are discussed below.
Basic AES encrypt and decrypt operations are supported by:
•
•
•
Galois/Counter mode (GCM), with basic GHASH operation
Counter mode with CBC-MAC (CCM)
XTS mode
The following feedback operating modes are available:
•
•
•
•
•
•
•
•
•
•
•
Electronic code book mode (ECB)
Cipher block chaining mode (CBC)
Counter mode (CTR)
Cipher feedback mode (CFB), 128-bit
F8 mode
Key sizes: 128, 192, and 256 bits
Support for CBC_MAC and Fedora 9 (F9) authentication modes
Basic GHASH operation (when selecting no encryption)
Key scheduling in hardware
Support for µDMA transfers
Fully synchronous design
Figure 8-10 shows the AES block diagram.
I/O Control FSM/µDMA Request
Interface
Mode
Control
FSM
AES
Feedback
Mode
Control
AES Core
Context
Registers
Polynomial
Multiplication
HASH Block
Figure 8-10. AES Block Diagram
For more information about the AES accelerator, see the Advance Encryption Standard Accelerator (AES)
chapter of the TMS320F2838x Real-Time Microcontrollers Technical Reference Manual.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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8.9.4 Generic Cyclic Redundancy Check (GCRC) Module
The Generic CRC (GCRC) is a designated Connectivity Manager module for computing the CRC value on a
configurable block of memory. It accomplishes this by fetching the specified block of memory and using the
integrated CRC engine. The calculated CRC value can be compared against a golden CRC value in software to
indicate a pass or fail. In essence, the GCRC can help identify memory faults and corruption in the Conectivity
Manager's accessible raw data.
The Generic CRC (GCRC) module has the following features:
•
•
•
•
•
Support for programmable polynomials of any order between 1 and 32
Calculate a CRC on byte (8-bit), halfword (16-bit), and word (32-bit) data blocks
Define the endianness and data type of the source data
Reverse the bit order
Select which data bits participate in the CRC computation
Figure 8-11 shows the block diagram of the GCRC module.
CRC Engine is triggered
when a write function to the
CRCDATAIN/CRCDATAOUT
register is performed.
CRCTRIGGER
CRCPOLY
DATASIZE
CRCDATAIN
CRCDATATRANS
CRC Engine
CRCDATAOUT
CRCDATAMASK
ENDIANNESS
BITREVERSE
POLYSIZE
CRCCTRL
DATATYPE
REMAINDER [31:0]
Figure 8-11. GCRC Block Diagram
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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8.9.5 CM Nonmaskable Interrupt (CMNMI) Module
The CM subsystem has the capability of detecting all serious errors that could occur in the entire system
(including all the subsystems), and informing the main CPU core about the errors. An NMI exception to the
Cortex-M4 CPU on the CM subsystem will be generated only when at least one or more of the below NMI error
sources become active. For more details on each of the sources, see the CM Subsystem NMI Sources section
of the TMS320F2838x Real-Time Microcontrollers Technical Reference Manual.
1. RAM/ROM uncorrectable error
2. Reset request from the EtherCAT
3. Clock failure
4. MCAN uncorrectable error
5. CM windowed watchdog timed out
6. Flash uncorrectable error
All these NMI sources are "OR-ed" to generate the NMI input to the Cortex-M4 NVIC. The NMI triggers a
CMNMIWD counter running at the CM subsystem frequency. The CMNMIWD counter will stop counting only if all
the pending NMIs are acknowledged by clearing the pending flags in the CMNMIFLG register. If the pending NMI
is not acknowledged before the CMNMIWD counter reaches the value programmed in the NMI Watchdog period
register (CMNMIWDPRD), an NMIWD reset is generated to the CM subsystem, which will reset the entire
device.
Figure 8-12 shows different sources that can trigger an NMI to the Cortex-M4 on the CM subsystem and the
registers associated with them.
Figure 8-12. CM Subsystem NMI Sources and NMIWD
All the NMI sources shown in Figure 8-12 are enabled by default on reset. CMNMICFG.NMIE is disabled on
reset and needs to be enabled by setting it to 1.
For more information about the CMNMI, see the CM Subsystem Non-Maskable Interrupt (CMNMI) Module
section of the TMS320F2838x Real-Time Microcontrollers Technical Reference Manual.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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8.9.6 Memory Protection Unit (MPU)
The CM subsystem has multiple masters accessing the memory blocks and peripherals. Below is the list of
masters on the CM subsystem:
•
•
•
Cortex-M4
µDMA
EtherNET DMA
In a multi-master system, it is important to have a protection mechanism to prevent unauthorized access to
critical code, data, or peripherals from different masters or threads. This protection mechanism will:
•
•
•
Prevent a process or a task from accessing memory that is not allocated to it.
Protect Cortex-M4 code from unintended corruption by other bus masters on the CM subsystem.
Protect stack corruption by other bus masters on CM systems.
The Cortex-M4 has the ARM native MPU (Cortex-M4 MPU) that provides such protection (see the Memory
Protection Unit chapter of the ARM® Cortex®-M4 Processor Technical Reference Manual). For other masters
(µDMA and Ethernet DMA), a generic memory protection unit (CM-MPU) has been provided, which users can
configure based on the use case, to enable the protection. Basically, one MPU for each master is provided to
protect the accesses from that master. For more details, see the Memory Controller Module section of the
TMS320F2838x Real-Time Microcontrollers Technical Reference Manual.
Cx RAM
ICODE
Bus Matrix-1
Flash
ROM
M
P
U
DCODE
SBUS
Cortex-M4
Sx RAM
MSGx RAM
µDMA
MPU
µDMA
Bus Matrix-2
Peripherals
- EtherNET
- EtherCAT
- DCAN
EtherNET
MPU
- MCAN
- USB etc
EtherNET
DMA
ET
EtherN
Figure 8-13. CM Block Diagram
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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8.9.7 Micro Direct Memory Access (µDMA)
The µDMA controller provides a way to offload data transfer tasks from the Arm Cortex-M4 processor, allowing
for more efficient use of the processor and the available bus bandwidth. The µDMA controller can perform
transfers between memory and peripherals. It has dedicated channels for each supported on-chip module and
can be programmed to automatically perform transfers between peripherals and memory when the peripheral is
ready to transfer more data.
The µDMA controller provides the following features:
•
•
Arm® PrimeCell® 32-channel configurable µDMA controller
Support for memory-to-memory, memory-to-peripheral, and peripheral-to-memory in multiple transfer modes:
– Basic mode
– Ping-pong mode
– Memory scatter-gather mode
– Peripheral scatter-gather mode
– Auto request mode
•
Highly flexible and configurable channel operation
– Independently configured and operated channels
– Dedicated channels for supported on-chip modules
– Flexible channel assignments
– One channel each for receive and transmit path for bidirectional modules
– Dedicated channel for software-initiated transfers
– Per-channel configurable priority scheme
– Optional software-initiated requests for any channel
Two levels of priority
Data sizes of 8, 16, and 32 bits
Programmable transfer size in binary steps from 1 to 1024
Source and destination address increment size of byte, halfword, word, or no increment
Maskable peripheral requests
•
•
•
•
•
•
Supports two interrupts:
– µDMA Software interrupt: µDMA generates an interrupt when a software channel completes all its
transfers
– µDMA Error interrupt: µDMA generates an interrupt an when error is detected on a DMA transfer
DMA transfers triggered by a peripheral event generates a corresponding peripheral interrupt when DMA
completes all its transfers.
•
Figure 8-14 shows the µDMA block diagram.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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System Memory
CH Control Table
µDMA
Controller
DMA Error
DMASTAT
DMASRCENDP
DMADSTENDP
DMACHCTRL
DMACFG
DMACTLBASE
DMAALTBASE
DMAWAITSTAT
DMASWREQ
dma_req
General Peripheral N
Registers
dma_sreq
IRQ
dma_done
•
•
•
DMAUSEBURSTSET
DMAUSEBURSTCLR
DMAREQMASKSET
DMAREQMASKCLR
DMAENASET
DMASRCENDP
DMADSTENDP
DMACHCTRL
dma_req
dma_sreq
dma_done
DMAENACLR
General Peripheral N
Registers
Nested Vectored
Interrupt
DMAALTSET
IRQ
DMAALTCLR
Transfer Buffers Used by
µDMA
Controller
(NVIC)
DMAPRIOSET
DMAPRIOCLR
DMAERRCLR
DMACHMAPn
Arm
Cortex-M4
Figure 8-14. µDMA Block Diagram
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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8.9.8 Watchdog
The Connectivity Manager (CM) has one watchdog (also referred to as windowed watchdog) timer. The
functionality of this watchdog timer is the same as the one used on CPUx subsystems. For details about this
module, see the Watchdog Timers section of the System Control chapter in the TMS320F2838x Real-Time
Microcontrollers Technical Reference Manual. Following are some differences in the configuration of the
watchdog timer on the CM versus CPUx:
•
The Watchdog timer on CM is disabled by default. Software needs to clear the WDDIS bit in the WDCR
register to enable the watchdog.
•
Whenever the watchdog counter (WDCR) overflows or an incorrect value is written to WDCR[WDCHK], an
NMI gets generated (not reset or interrupt such as CPUx watchdog timers) to the CMNMIWD module. If
software is not able to service the NMI, then the NMIWD module will trigger a reset to the CM.
The CM watchdog timer counter stops incrementing when the Cortex-M4 is halted during the debug session.
8.9.9 CM Clocking
8.9.9.1 CM Clock Sources
Table 8-32 lists four possible clock sources. Figure 8-15 provides an overview of the device's clocking system.
Table 8-32. Possible Reference Clock Sources
CLOCK SOURCE
MODULES CLOCKED
COMMENTS
INTOSC1
Can be used to provide clock for:
Internal oscillator 1.
Zero-pin overhead 10-MHz internal oscillator.
•
•
•
Watchdog block
Main PLL
CPU-Timer 2
INTOSC2(1)
Can be used to provide clock for:
Internal oscillator 2.
Zero-pin overhead 10-MHz internal oscillator.
•
•
•
Main PLL
Auxiliary PLL
CPU-Timer 2
XTAL
Can be used to provide clock for:
External crystal or resonator connected between the X1 and X2 pins
or single-ended clock connected to the X1 pin.
•
•
•
Main PLL
Auxiliary PLL
CPU-Timer 2
AUXCLKIN
Can be used to provide clock for:
Single-ended 3.3-V level clock source. GPIO133/AUXCLKIN pin
should be used to provide the input clock.
•
•
Auxiliary PLL
CPU-Timer 2
(1) On reset, internal oscillator 2 (INTOSC2) is the default clock source for both system PLL (OSCCLK) and auxiliary PLL (AUXOSCCLK).
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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AUXPLLCLKEN
AUXCLKDIV
AUXOSCCLK
AUX PLL
AUXCLK
Divider
SYSCLKDIVSEL
AUXCLKSRCCEL
SYS
PLLRAWCLK
Divider
SYS PLL
AUXPLLRAWCLK
USBBITCLK
PLLSYSCLK
PLLCLKEN
OSCCLKSRCSEL
DIVSRCSEL
PLLSYSCLK
CMDIVSRCSEL
ETHERNETCLK
CMCLK
DIVIDER
CMCLK
CPU2
CPU1
ETHDIV
ETHERNETCLK
Divider
One per CMCLK peripheral
CMPCLKCRx.PERx
ETHERNET_SS_CLK100
ETHERNET_SS_CLK50
ETHERNET
CM.PERx.SYSCLK
CMCLK
CM.PERx.SYSCLK
PALLOCATE0
.USB
CM Flash
GPIO
I2C
SSI
UART
MCAN
CANx
DCSM
MSG RAMs
IPC
WD
ETHERCAT
ETHERNET
GCRC
AES
UDMA
CPUTimers
USB
CPU1.PCLKCRx
CPU2.PCLKCRx
CPU1/CPU2/CM
.PERx.SYSCLK
CPU1.PERx.SYSCLK
CPU2.PERx.SYSCLK
CANx
PALLOCATE0.CANx
CPUSELx.CANx
X1 (XTAL)
AUXCLKIN
CANxBCLKSEL
CANxBIT Clock
MCANBCLKSEL
MCANBIT Clock
Figure 8-15. Clocking System
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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8.9.10 CM Timers
The Connectivity Manager (CM) has three 32-bit timers that are identical, with 16-bit clock prescaling. These
timers operate on CMCLK. The timers have a 32-bit count-down register that generates an interrupt when the
counter reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting.
When the counter reaches zero, it is automatically reloaded with a 32-bit period value.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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9 Applications, Implementation, and Layout
Note
Information in the following sections is not part of the TI component specification, and TI does not
warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of
components for their purposes. Customers should validate and test their design implementation to
confirm system functionality.
9.1 TI Reference Design
The TI Reference Design Library is a robust reference design library spanning analog, embedded processor,
and connectivity. Created by TI experts to help you jump start your system design, all reference designs include
schematic or block diagrams, BOMs, and design files to speed your time to market. Search and download
designs at Select TI reference designs.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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10 Device and Documentation Support
10.1 Device and Development Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320
MCU devices and support tools. Each TMS320™ MCU commercial family member has one of three prefixes:
TMX, TMP, or TMS (for example, TMS320F28386D). Texas Instruments recommends two of three possible
prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of
product development from engineering prototypes (with TMX for devices and TMDX for tools) through fully
qualified production devices and tools (with TMS for devices and TMDS for tools).
Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device's electrical specifications and
may not use production assembly flow.
TMP Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical
specifications.
TMS Production version of the silicon die that is fully qualified.
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.
TMDS Fully-qualified development-support product.
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, ZWT) and temperature range (for example, S). Figure 10-1 provides a legend for reading the
complete device name for any family member.
For device part numbers and further ordering information, see the TI website (www.ti.com) or contact your TI
sales representative.
For additional description of the device nomenclature markings on the die, see the TMS320F2838x Real-Time
MCUs Silicon Errata.
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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-Q1
Q
Generic Part Number: TMS 320
F
F
28386D
Orderable Part Number:
PREFIX(A)
X
(blank)
28386D ZWT
R
SHIPPING OPTIONS
experimental device
qualified device
TMX (X) =
Tray
Tape and Reel
(blank)
R
=
=
TMS (blank) =
QUALIFICATION (in Generic Part Number)
DEVICE FAMILY
Non-Automotive
Q1 refers to Automotive AEC Q100 Grade 1 qualification.
blank
-Q1
=
=
320 = TMS320 MCU Family
TEMPERATURE RANGE (in Orderable Part Number)
TECHNOLOGY
−40°C to 125°C (TJ)
S
=
=
Q
F = Flash
−40°C to 125°C (TA)
PACKAGE TYPE
337-Ball ZWT New Fine Pitch Ball Grid Array (nFBGA)
176-Pin PTP PowerPAD Thermally Enhanced Low-Profile Quad Flatpack (HLQFP)
DEVICE
28388D
28386D
28384D
28388S
28386S
28384S
A. Prefix X is used in orderable part numbers.
Figure 10-1. Device Nomenclature
10.2 Markings
Figure 10-2 shows the package symbolization and Table 10-1 lists the silicon revision codes.
=
YMLLLLS
Lot Trace Code
=
=
=
=
=
YM
LLLL
S
$$
#
2-Digit Year/Month Code
Assembly Lot
Assembly Site Code
Wafer Fab Code as applicable
Silicon Revision Code
F28388DZWTS
$$#-YMLLLLS
G1
F28388DPTPS
$$#-YMLLLLS
G4
Package
Pin 1
Package
Pin 1
Figure 10-2. Package Symbolization
Table 10-1. Revision Identification
REVID(1)
Address: 0x5D00C
SILICON REVISION CODE
SILICON REVISION
COMMENTS
Blank
A
0
0x0000 0000
This silicon revision is available as TMX.
This silicon revision is available as TMX and
TMS.
A
0x0000 0001
(1) Silicon Revision ID
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TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
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SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
10.3 Tools and Software
TI offers an extensive line of development tools. Some of the tools and software to evaluate the performance of
the device, generate code, and develop solutions are listed below. To view all available tools and software for
C2000™ real-time control MCUs, visit the C2000 real-time control MCUs – Design & development page.
Development Tools
F28388D controlCARD for C2000 Real time control development kit
HSEC180 controlCARD development tool for the F2838xD and F2838xS series. controlCARDs are ideal to use
for initial evaluation and system prototyping. They are complete board-level modules that provide a low-profile,
single-board controller solution.
F28388D Experimenter Kit
The Experimenter Kit is an evaluation bundle that consists of a controlCARD and a TMDSHSECDOCK
Baseboard Docking Station. The docking station provides power to the included controlCARD and has a
breadboard area for prototyping. Access to the controller’s key signals is available using a series of header pins.
Software Tools
C2000Ware for C2000 MCUs
C2000Ware for C2000 microcontrollers is a cohesive set of development software and documentation designed
to minimize software development time. From device-specific drivers and libraries to device peripheral examples,
C2000Ware provides a solid foundation to begin development and evaluation. C2000Ware is now the
recommended content delivery tool versus controlSUITE™.
Code Composer Studio™ (CCS) Integrated Development Environment (IDE) for C2000 Microcontrollers
Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and
Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug
embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build environment,
debugger, profiler, and many other features. The intuitive IDE provides a single user interface taking the user
through each step of the application development flow. Familiar tools and interfaces allow users to get started
faster than ever before. Code Composer Studio combines the advantages of the Eclipse software framework
with advanced embedded debug capabilities from TI resulting in a compelling feature-rich development
environment for embedded developers.
Pin mux tool
The Pin Mux Utility is a software tool which provides a Graphical User Interface for configuring pin multiplexing
settings, resolving conflicts and specifying I/O cell characteristics for TI MPUs.
F021 Flash Application Programming Interface (API)
The F021 Flash Application Programming Interface (API) provides a software library of functions to program,
erase, and verify F021 on-chip Flash memory.
UniFlash Standalone Flash Tool
UniFlash is a standalone tool used to program on-chip flash memory through a GUI, command line, or scripting
interface.
Models
Various models are available for download from the product Design & development pages. These models
include I/O Buffer Information Specification (IBIS) Models and Boundary-Scan Description Language (BSDL)
Models. To view all available models, visit the Design tools & simulation section of the Design & development
page for each device.
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Submit Document Feedback 293
Product Folder Links: TMS320F28388D TMS320F28386D TMS320F28386D-Q1 TMS320F28384D
TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
www.ti.com
Training
To help assist design engineers in taking full advantage of the C2000 microcontroller features and performance,
TI has developed a variety of training resources. Utilizing the online training materials and downloadable hands-
on workshops provides an easy means for gaining a complete working knowledge of the C2000 microcontroller
family. These training resources have been designed to decrease the learning curve, while reducing
development time, and accelerating product time to market. For more information on the various training
resources, visit the C2000™ real-time control MCUs – Support & training site.
10.4 Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
The current documentation that describes the processor, related peripherals, and other technical collateral is
listed below.
Errata
TMS320F2838x Real-Time MCUs Silicon Errata describes known advisories on silicon and provides
workarounds.
Technical Reference Manual
TMS320F2838x Real-Time Microcontrollers Technical Reference Manual details the integration, the
environment, the functional description, and the programming models for each peripheral and subsystem in the
2838x microcontrollers.
CPU User's Guides
TMS320C28x CPU and Instruction Set Reference Guide describes the central processing unit (CPU) and the
assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). This Reference
Guide also describes emulation features available on these DSPs.
TMS320C28x Extended Instruction Sets Technical Reference Manual describes the architecture, pipeline, and
instruction set of the TMU, VCU-II, and FPU accelerators.
Peripheral Guides
C2000 Real-Time Control Peripherals Reference Guide describes the peripheral reference guides of the 28x
DSPs.
Tools Guides
TMS320C28x Assembly Language Tools v20.8.0.STS User's Guide describes the assembly language tools
(assembler and other tools used to develop assembly language code), assembler directives, macros, common
object file format, and symbolic debugging directives for the TMS320C28x device.
TMS320C28x Optimizing C/C++ Compiler v20.8.0.STS User's Guide describes the TMS320C28x C/C++
compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly
language source code for the TMS320C28x device.
Application Reports
The SMT & packaging application notes website lists documentation on TI’s surface mount technology (SMT)
and application notes on a variety of packaging-related topics.
Semiconductor Packing Methodology describes the packing methodologies employed to prepare semiconductor
devices for shipment to end users.
Calculating Useful Lifetimes of Embedded Processors provides a methodology for calculating the useful lifetime
of TI embedded processors (EPs) under power when used in electronic systems. It is aimed at general
engineers who wish to determine if the reliability of the TI EP meets the end system reliability requirement.
Copyright © 2021 Texas Instruments Incorporated
294 Submit Document Feedback
Product Folder Links: TMS320F28388D TMS320F28386D TMS320F28386D-Q1 TMS320F28384D
TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
www.ti.com
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
An Introduction to IBIS (I/O Buffer Information Specification) Modeling discusses various aspects of IBIS
including its history, advantages, compatibility, model generation flow, data requirements in modeling the input/
output structures and future trends.
Serial Flash Programming of C2000™ Microcontrollers discusses using a flash kernel and ROM loaders for
serial programming a device.
Fast Integer Division – A Differentiated Offering From C2000™ Product Family provides an overview of the
different division and modulo (remainder) functions and its associated properties.
C2000™ Key Technology Guide provides a deeper look into the components that differentiate the C2000
Microcontroller Unit (MCU) as it pertains to Real-Time Control Systems.
10.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.6 Trademarks
PowerPAD™, C2000™, Code Composer Studio™, TMS320™, controlSUITE™, TI E2E™ are trademarks of Texas
Instruments.
NXP™ is a trademark of NXP B.V.
Arm®, Cortex®, Thumb®, PrimeCell® are registered trademarks of Arm Limited (or its subsidiaries) in the US
and/or elsewhere.
EtherCAT® are registered trademarks of Beckhoff Automation GmbH, Germany.
Bosch® are registered trademarks of Robert Bosch GmbH.
Freescale® is a registered trademark of NXP USA, INC.
All trademarks are the property of their respective owners.
10.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.8 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 295
Product Folder Links: TMS320F28388D TMS320F28386D TMS320F28386D-Q1 TMS320F28384D
TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
www.ti.com
11 Mechanical, Packaging, and Orderable Information
11.1 Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
To learn more about TI packaging, visit the Packaging information website.
Copyright © 2021 Texas Instruments Incorporated
296 Submit Document Feedback
Product Folder Links: TMS320F28388D TMS320F28386D TMS320F28386D-Q1 TMS320F28384D
TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
www.ti.com
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
PACKAGE OUTLINE
TM
PowerPAD HLQFP - 1.6 mm max height
PTP0176F
SCALE 0.550
PLASTIC QUAD FLATPACK
24.2
23.8
NOTE 3
B
PIN 1 ID
133
176
1
132
24.2
23.8
NOTE 3
26.2
25.8
TYP
44
89
88
45
0.27
0.17
176X
C
A
172X 0.5
0.08
C A B
4X 21.5
SEATING PLANE
1.6 MAX
SEE DETAIL A
(0.13)
TYP
45
88
89
44
0.25
GAGE PLANE
(1.4)
4X 0.78 MAX
NOTE 4
4X
0.54 MAX
NOTE 4
0.15
0.05
0.08 C
7.33
6.78
0 -7
177
0.75
0.45
DETAIL A
TYPICAL
4X
0.2 MAX
NOTE 4
EXPOSED
THERMAL PAD
1
132
176
133
8.07
7.53
4223382/A 03/2017
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs.
4. Strap features my not present.
5. Reference JEDEC registration MS-026.
www.ti.com
DETAIL
A
S
C
A
L
E
:
1
2
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 297
Product Folder Links: TMS320F28388D TMS320F28386D TMS320F28386D-Q1 TMS320F28384D
TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
www.ti.com
EXAMPLE BOARD LAYOUT
PowerPADTM HLQFP - 1.6 mm max height
PTP0176F
PLASTIC QUAD FLATPACK
(8.07)
SYMM
SOLDER MASK
DEFINED PAD
176
133
176X (1.45)
1
132
176X (0.3)
172X (0.5)
177
SYMM
(7.33)
(1.5 TYP)
(25.5)
( 22)
NOTE 10
(R0.05) TYP
(
0.2) TYP
VIA
89
44
SEE DETAILS
45
88
METAL COVERED
BY SOLDER MASK
(1.5 TYP)
(25.5)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:4X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223382/A 03/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. See technical brief, Powerpad thermally enhanced package,
Texas Instruments Literature No. SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
10. Size of metal pad may vary due to creepage requirement.
Copyright © 2021 Texas Instruments Incorporated
298 Submit Document Feedback
Product Folder Links: TMS320F28388D TMS320F28386D TMS320F28386D-Q1 TMS320F28384D
TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1
TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S
TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1
www.ti.com
SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021
EXAMPLE STENCIL DESIGN
PowerPADTM HLQFP - 1.6 mm max height
PTP0176F
PLASTIC QUAD FLATPACK
(8.07)
BASED ON
0.125 THICK STENCIL
SYMM
176
133
176X (1.45)
1
132
176X (0.3)
172X (0.5)
(25.5)
(7.33)
BASED ON
SYMM
177
0.125 THICK
STENCIL
(R0.05) TYP
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
44
89
METAL COVERED
BY SOLDER MASK
45
88
(25.5)
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:4X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
9.02 X 8.2
8.07 X 7.33 (SHOWN)
7.37 X 6.69
0.125
0.150
0.175
6.82 X 6.2
4223382/A 03/2017
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 299
Product Folder Links: TMS320F28388D TMS320F28386D TMS320F28386D-Q1 TMS320F28384D
TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S
TMS320F28384S-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Mar-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
F28384DPTPQR
F28384DPTPS
F28384DZWTQR
F28384DZWTS
ACTIVE
ACTIVE
ACTIVE
ACTIVE
HLQFP
HLQFP
NFBGA
NFBGA
PTP
PTP
ZWT
ZWT
176
176
337
337
200
40
RoHS & Green
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
F28384DPTPQ
NIPDAU
SNAGCU
SNAGCU
F28384DPTPS
F28384DZWTQ
F28384DZWTS
1000 RoHS & Green
90
RoHS & Green
F28384SPTPQR
F28384SPTPS
PREVIEW
ACTIVE
HLQFP
HLQFP
PTP
PTP
176
176
200
40
RoHS & Green
RoHS & Green
NIPDAU
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
F28384SPTPQ
F28384SPTPS
F28384SZWTS
F28386DPTPQ
F28386DPTPQR
F28386DPTPS
F28386DZWTQ
F28386DZWTQR
F28386DZWTS
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
NFBGA
HLQFP
HLQFP
HLQFP
NFBGA
NFBGA
NFBGA
ZWT
PTP
PTP
PTP
ZWT
ZWT
ZWT
337
176
176
176
337
337
337
90
40
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
SNAGCU
NIPDAU
NIPDAU
NIPDAU
SNAGCU
SNAGCU
SNAGCU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
F28384SZWTS
F28386DPTPQ
F28386DPTPQ
F28386DPTPS
F28386DZWTQ
F28386DZWTQ
F28386DZWTS
200
40
90
1000 RoHS & Green
90
RoHS & Green
F28386SPTPQR
F28386SPTPS
PREVIEW
ACTIVE
HLQFP
HLQFP
PTP
PTP
176
176
200
40
RoHS & Green
RoHS & Green
NIPDAU
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
F28386SPTPQ
F28386SPTPS
F28386SZWTS
F28388DPTPS
F28388DPTPSR
F28388DZWTS
F28388DZWTSR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
NFBGA
HLQFP
HLQFP
NFBGA
NFBGA
ZWT
PTP
PTP
ZWT
ZWT
337
176
176
337
337
90
40
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
SNAGCU
NIPDAU
NIPDAU
SNAGCU
SNAGCU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
F28386SZWTS
F28388DPTPS
F28388DPTPS
F28388DZWTS
F28388DZWTS
200
90
1000 RoHS & Green
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Mar-2021
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
F28388SPTPS
F28388SPTPSR
F28388SZWTS
F28388SZWTSR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
HLQFP
HLQFP
NFBGA
NFBGA
PTP
PTP
ZWT
ZWT
176
176
337
337
40
200
90
RoHS & Green
RoHS & Green
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
F28388SPTPS
NIPDAU
SNAGCU
SNAGCU
F28388SPTPS
F28388SZWTS
F28388SZWTS
1000 RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
11-Mar-2021
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TMS320F28384D, TMS320F28384D-Q1, TMS320F28384S, TMS320F28384S-Q1, TMS320F28386D, TMS320F28386D-Q1, TMS320F28386S,
TMS320F28386S-Q1 :
Catalog: TMS320F28384D, TMS320F28384S, TMS320F28386D, TMS320F28386S
•
Automotive: TMS320F28384D-Q1, TMS320F28384S-Q1, TMS320F28386D-Q1, TMS320F28386S-Q1
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 3
PACKAGE OUTLINE
ZWT0337A
NFBGA - 1.4 mm max height
SCALE 0.950
PLASTIC BALL GRID ARRAY
16.1
15.9
A
B
BALL A1 CORNER
16.1
15.9
1.4 MAX
C
SEATING PLANE
0.12 C
0.45
0.35
BALL TYP
TYP
14.4 TYP
SYMM
(0.8) TYP
(0.8) TYP
W
V
U
T
R
P
N
M
L
14.4
TYP
SYMM
K
J
H
G
F
0.55
337X
0.45
E
D
C
0.15
0.05
C A B
C
B
A
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
0.8 TYP
0.8 TYP
BALL A1 CORNER
4223381/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
ZWT0337A
NFBGA - 1.4 mm max height
PLASTIC BALL GRID ARRAY
(0.8) TYP
337X ( 0.4)
11
12
13 14 15 16 17 18 19
1
3
4
6
7
8
9
10
2
5
A
B
C
(0.8) TYP
D
E
F
G
H
J
SYMM
K
L
M
N
P
R
T
U
V
W
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:7X
METAL UNDER
SOLDER MASK
0.05 MAX
0.05 MIN
(
0.4)
METAL
EXPOSED METAL
(
0.4)
SOLDER MASK
OPENING
EXPOSED METAL
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4223381/A 02/2017
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).
www.ti.com
EXAMPLE STENCIL DESIGN
ZWT0337A
NFBGA - 1.4 mm max height
PLASTIC BALL GRID ARRAY
(
0.4) TYP
(0.8) TYP
11
12
13 14 15 16 17 18 19
1
3
4
6
7
8
9
10
2
5
A
B
C
(0.8) TYP
D
E
F
G
H
J
SYMM
K
L
M
N
P
R
T
U
V
W
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.15 mm THICK STENCIL
SCALE:7X
4223381/A 02/2017
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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Copyright © 2021, Texas Instruments Incorporated
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