F28M35H22C1RFPT [TI]
Concerto Microcontrollers Embedded Memory; 协奏曲微控制器的嵌入式内存型号: | F28M35H22C1RFPT |
厂家: | TEXAS INSTRUMENTS |
描述: | Concerto Microcontrollers Embedded Memory |
文件: | 总192页 (文件大小:1379K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
www.ti.com
SPRS742D –JUNE 2011–REVISED AUGUST 2012
Concerto Microcontrollers
1 F28M35x ( Concerto™) MCUs
1.1 Features
12345
• Master Subsystem — ARM® Cortex™-M3
– 100 MHz
• Control Subsystem — TMS320C28x™ 32-Bit
CPU
– 150 MHz
– Embedded Memory
– Embedded Memory
•
•
•
•
Up to 512KB Flash (ECC)
Up to 32KB RAM (ECC or Parity)
Up to 64KB Shared RAM
2KB IPC Message RAM
•
•
•
•
Up to 512KB Flash (ECC)
Up to 36KB RAM (ECC or Parity)
Up to 64KB Shared RAM
2KB IPC Message RAM
– 5 Universal Asynchronous
Receiver/Transmitters (UARTs)
– 4 Synchronous Serial Interfaces (SSIs)/
Serial Peripheral Interface (SPI)
– 2 Inter-integrated Circuits (I2Cs)
– Universal Serial Bus On-the-Go (USB-OTG) +
PHY
– IEEE-754 Single-Precision Floating-Point
Unit (FPU)
– Viterbi, Complex Math, CRC Unit (VCU)
– Serial Communications Interface (SCI)
– Serial Peripheral Interface (SPI)
– Inter-integrated Circuit (I2C)
– 10/100 ENET 1588 MII
– 6-Channel Direct Memory Access (DMA)
– 2 Controller Area Networks (CANs)
– 32-Channel Direct Memory Access (µDMA)
– 9 Enhanced Pulse Width Modulator (ePWM)
Modules
– Dual Security Zones (128-Bit Password per
Zone)
•
18 Outputs (16 High-Resolution)
– 6 32-Bit Enhanced Capture (eCAP) Modules
– External Peripheral Interface (EPI)
– Micro Cyclic Redundancy Check (µCRC)
Module
– 3 32-Bit Enhanced Quadrature Encoder
(eQEP) Modules
– Multichannel Buffered Serial Port (McBSP)
– External Peripheral Interface (EPI)
– One Security Zone (128-Bit Password)
– 3 32-Bit Timers
– 4 General-Purpose Timers
– 2 Watchdog Timer Modules
– Endianness: Little Endian
• Clocking
– Endianness: Little Endian
– On-chip Crystal Oscillator/External Clock
Input
– Dynamic PLL Ratio Changes Supported
• 1.2-V Digital, 1.8-V Analog, 3.3-V I/O Design
• Analog Subsystem
– Dual 12-Bit Analog-to-Digital Converters
(ADCs)
– Up to 2.88 MSPS
– Up to 20 Channels
– 4 Sample-and-Hold (S/H) Circuits
• Interprocessor Communications (IPC)
– 32 Handshaking Channels
– 4 Channels Generate IPC Interrupts
– Can be Used to Coordinate Transfer of Data
Through IPC Message RAMs
– Up to 6 Comparators With 10-Bit Digital-to-
Analog Converter (DAC)
• Package
• Up to 74 Individually Programmable,
Multiplexed GPIO Pins
– 144-Pin RFP PowerPAD™ Thermally
Enhanced Thin Quad Flatpack (HTQFP)
– Glitch-free I/Os
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Concerto, TMS320C28x, PowerPAD, C28x, C2000, Piccolo, Delfino, XDS are trademarks of Texas Instruments.
Cortex is a trademark of ARM Limited.
ARM is a registered trademark of ARM Ltd or its subsidiaries.
All other trademarks are the property of their respective owners.
2
3
4
5
PRODUCT PREVIEW information concerns products in the formative or design phase of
development. Characteristic data and other specifications are design goals. Texas
Instruments reserves the right to change or discontinue these products without notice.
Copyright © 2011–2012, Texas Instruments Incorporated
F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
1.2 Description
The Concerto™ family is a multi-core system-on-chip microcontroller (MCU) with independent
communication and real-time control subsystems. The F28M35x is the first series in the Concerto family.
The communications subsystem is based on the industry-standard 32-bit ARM® Cortex™-M3 CPU and
features a wide variety of communication peripherals, including Ethernet 1588, USB OTG with PHY, CAN,
UART, SSI, I2C, and an external interface.
The real-time control subsystem is based on TI’s industry-leading proprietary 32-bit C28x™ Floating-Point
CPU and features the most flexible and high-precision control peripherals, including ePWMs with fault
protection, and encoders and captures—all as implemented by TI’s C2000™ Piccolo™ and Delfino™
families. In addition, the C28-CPU has been enhanced with the addition of the Viterbi, Complex Math,
CRC Unit (VCU) instruction accelerator that implements efficient Viterbi, Complex Arithmetic, 16-bit FFTs
and CRC algorithms.
A high-speed analog subsystem and supplementary RAM memory is shared, along with on-chip voltage
regulation and redundant clocking circuitry. Safety considerations also include Error Correction Code
(ECC), Parity, and Code Secure Memory, as well as documentation to assist with system-level industrial
safety certification.
2
F28M35x ( Concerto™) MCUs
Copyright © 2011–2012, Texas Instruments Incorporated
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
www.ti.com
SPRS742D –JUNE 2011–REVISED AUGUST 2012
1.3 Functional Block Diagram
1.8V
1.2V
VREG
VREG
SECURE
C1
C3
1.8V
1.2V
RAM
8 KB
RAM
8 KB
GPIO_MUX1
VMON
VMON
SECURE
FLASH
(ECC)
(parity)
BOOT
ROM
SECURE
C0
C2
512 KB
(ECC)
RAM
8 KB
RAM
8 KB
64 KB
(ECC)
(parity)
APB BUS
REGS
ONLY
AHB BUS
uDMA BUS
10
ADC
ADC_1
M3
BUS
MPU
NVIC
INPUTS
M3
MODULE
M3 CPU
uDMA
MATRIX
I-CODE BUS
D-CODE BUS
4
COMP
INPUTS
M3 SYSTEM BUS
INTER-
PROC
C28 CPU/DMA
ACCESS TO EPI
COMM
CLOCKS
FREQ
RESETS
GASKET
6
MTOC
MSG
CTOM
COMPARE
S0
S1
S2
S3
S4
S5
S6
S7
MSG
RAM
6
+ DAC
UNITS
MEM32
TO AHB
BUS
RAM
NMI
IPC
COMP
OUT
8 KB 8 KB 8 KB 8 KB 8 KB 8 KB 8 KB 8 KB
S0-S7 SHARED RAM (parity)
(parity)
2 KB
(parity)
2 KB
PUTS
BRIDGE
DEBUG
SECURITY
INTER-
PROC
COMM
4
C28 DMA BUS
COMP
INPUTS
C28 CPU
C28
C28
C28
FPU
ADC_2
10
DMA
VCU
PIE
MODULE
ADC
INPUTS
C28 CPU BUS
ANALOG
SUBSYSTEM
16-
BIT
PF2
32-
BIT
PF1
32-
BIT
PF3
16/32
- BIT
PF0
BOOT
ROM
SECURE
L3
M1
L1
RAM
8 KB
(ECC)
RAM
8 KB
RAM
2 KB
64 KB
SECURE
FLASH
(parity)
(ECC)
M0
SECURE
L0
L2
512 KB
(ECC)
GPIO_MUX1
66 PINS
RAM
8 KB
RAM
8 KB
RAM
2 KB
(ECC)
(parity)
(ECC)
Figure 1-1. Functional Block Diagram
Copyright © 2011–2012, Texas Instruments Incorporated
F28M35x ( Concerto™) MCUs
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
1
F28M35x ( Concerto™) MCUs ........................ 1
1.1 Features ............................................. 1
1.2 Description ........................................... 2
1.3 Functional Block Diagram ........................... 3
3
4
Device Pins ............................................. 87
3.1 Pin Assignments .................................... 87
3.2 Terminal Functions ................................. 88
Device Operating Conditions ...................... 111
4.1 Absolute Maximum Ratings ....................... 111
4.2 Recommended Operating Conditions ............. 111
4.3 Electrical Characteristics .......................... 112
Electrical Specifications ............................ 113
5.1 Current Consumption ............................. 113
5.2 Thermal Design Considerations .................. 114
5.3 Timing Parameter Symbology ..................... 115
Revision History .............................................. 5
2
Device Overview ....................................... 10
2.1 Device Characteristics .............................. 11
2.2 Memory Maps ...................................... 13
2.3 Master Subsystem .................................. 23
2.4 Control Subsystem ................................. 29
2.5 Analog Subsystem .................................. 33
2.6 Master Subsystem NMIs ........................... 36
2.7 Control Subsystem NMIs ........................... 36
2.8 Resets .............................................. 38
5
5.4
Clock Frequencies, Requirements, and
Characteristics .................................... 116
5.5 Power Sequencing ................................ 119
Peripheral Information and Timings ............. 123
6.1 Analog and Shared Peripherals ................... 123
6.2 Master Subsystem Peripherals .................... 151
6.3 Control Subsystem Peripherals ................... 166
Device and Documentation Support ............. 185
7.1 Device Support .................................... 185
7.2 Documentation Support ........................... 186
7.3 Community Resources ............................ 186
6
7
8
2.9
Internal Voltage Regulation and Monitoring ........ 43
2.10 Input Clocks and PLLs ............................. 47
2.11 Master Subsystem Clocking ........................ 57
2.12 Control Subsystem Clocking ....................... 60
2.13 Analog Subsystem Clocking ....................... 63
2.14 Shared Resources Clocking ........................ 63
2.15 Loss of Input Clock (NMI Watchdog Function) ..... 63
2.16 GPIOs and Other Pins .............................. 65
2.17 Emulation/JTAG .................................... 81
2.18 Code Security Module (CSM) ...................... 84
2.19 µCRC Module ...................................... 85
Mechanical Packaging and Orderable
Information ............................................ 187
8.1 Thermal Data for Package ........................ 187
8.2 Packaging Information ............................ 187
4
Contents
Copyright © 2011–2012, Texas Instruments Incorporated
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
www.ti.com
SPRS742D –JUNE 2011–REVISED AUGUST 2012
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
This data sheet revision history highlights the technical changes made to the SPRS742C device-specific
data sheet to make it an SPRS742D revision.
Scope:
Added new sections.
See table below.
LOCATION
ADDITIONS, DELETIONS, AND MODIFICATIONS
Section 1.1
Features:
•
Changed "Up to 72 Individually Programmable, Multiplexed GPIO Pins" to "Up to 74 Individually
Programmable, Multiplexed GPIO Pins"
–
Added "Glitch-free I/Os" feature
Control Subsystem — TMS320C28x™ 32-Bit CPU:
Added "External Peripheral Interface (EPI)" feature
Analog Subsystem:
Removed "On-chip Temperature Sensor"
•
•
–
–
Figure 1-1
Table 2-1
Updated Functional Block Diagram
Hardware Features:
•
12-Bit ADC 1:
–
Removed "Temperature Sensor"
•
•
Updated "Voltage Regulator and Monitor"
Updated "Clocking"
Table 2-3
Table 2-8
Control Subsystem Peripheral Frame 0 (Includes Analog):
0000 1780 – 0000 17FF: Added C Hardware Logic BIST Registers
Control Subsystem Flash, ECC, OTP, Boot ROM:
•
•
•
•
•
•
•
Added "M Address (Byte-Aligned)" column
Added "µDMA Access" column
0030 0000 – 003F 7FFF: Added EPI0
003F 8000 – 003F FFFF: Added C28x Boot ROM
Added "The letter "M" refers to the Master Subsystem" footnote
Added "The Control Subsystem has no direct access to EPI in silicon revision 0 devices" footnote
Table 2-12
Master Subsystem Analog and EPI:
•
•
•
•
•
Added "C Address (x16 Aligned)" column
Added "C DMA Access" column
6000 0000 – DFFF FFFF: Updated the above two new columns
Added "The letter "C" refers to the Control Subsystem" footnote
Added "The Control Subsystem has no direct access to EPI in silicon revision 0 devices" footnote
Section 2.3
Master Subsystem:
Updated "The Master Subsystem includes ..." paragraph
Cortex™-M3 CPU:
Removed "MPU is not available on silicon revision 0 devices" NOTE
•
Section 2.3.1
•
Section 2.3.2
Figure 2-1
Added "Cortex™-M3 Core Hardware Logic Built-In Test (LBIST)" section
Updated "Master Subsystem" figure
Table 2-14
Interrupts from NVIC to Cortex™-M3:
•
Interrupt Number: Changed 91 to "91–133". Updated "Vector Number" column. Updated "Vector
Address or Offset" column.
Section 2.3.6
Section 2.3.8
Cortex™-M3 Local Peripherals:
Updated "The Cortex™-M3 local peripherals include two Watchdogs ..." paragraph
Cortex™-M3 Accessing Shared Resources and Analog Peripherals:
•
•
•
•
Updated "There are several memories ..." paragraph
Updated "The Shared Resources ..." paragraph
Updated "The Analog Subsystem has ADC1 ..." paragraph
Copyright © 2011–2012, Texas Instruments Incorporated
Contents
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
LOCATION
Section 2.4
ADDITIONS, DELETIONS, AND MODIFICATIONS
Control Subsystem:
Updated "The Control Subsystem includes ..." paragraph
•
Figure 2-2
Table 2-16
Updated "Control Subsystem" figure
PIE Peripheral Interrupts:
•
INTx.3, INT12: Changed from "C28FLFSM" to "Reserved"
C28x Local Peripherals:
Updated "The C28x local peripherals include an NMI Watchdog ..." paragraph
C28x Accessing Shared Resources and Analog Peripherals:
Updated "The Shared Resources ..." paragraph
Analog Subsystem:
Updated "The Analog Subsystem has ADC1 ..." paragraph
ADC1:
Section 2.4.5
Section 2.4.7
Section 2.5
•
•
•
Section 2.5.1
•
Updated "The ADC1 consists of a 12-bit Analog-to-Digital converter ..." paragraph
Figure 2-3
Updated "Analog Subsystem" figure
Analog Common Interface Bus (ACIB):
Section 2.5.4
•
Updated "The ACIB bus links the Master and Control Subsystems ..." paragraph
Master Subsystem NMIs:
Updated "The inputs to the Cortex™-M3 NMI block include ..." paragraph
Control Subsystem NMIs:
Updated "The inputs to the C28x NMI block include ..." paragraph
Section 2.6
Section 2.7
•
•
Figure 2-4
Section 2.8
Updated "Cortex™-M3 NMI and C28x NMI" figure
Resets:
•
Updated "The XRS pin can receive an external reset signal ..." paragraph
Figure 2-5
Updated "Resets" figure
Section 2.8.3
Analog Subsystem and Shared Resources Resets:
•
Added "EPI is a shared peripheral ..." paragraph
Section 2.8.4
Table 2-17
Device Boot Sequence:
•
•
•
Updated "Boot Mode 7 ..." paragraph
Updated "Boot Mode 1 causes the Master boot program to branch ..." paragraph
Updated "Boot Modes 0, 2, 3, ..." paragraph
Master Subsystem Boot Mode Selection:
•
•
Added Boot Modes 8–15
Updated and added footnotes
Section 2.9
Section 2.10
Figure 2-10
Section 2.12
Added "Internal Voltage Regulation and Monitoring" section
Added "Input Clocks and PLLs" section
Updated "Cortex™-M3 Clocks and Low-Power Modes" figure
Control Subsystem Clocking:
•
Updated "The C28x processor outputs two clocks ..." paragraph
Figure 2-11
Updated "C28x Clocks and Low-Power Modes" figure
C28x Standby Mode:
Section 2.12.3
•
•
Updated "In Standby Mode, the C28x processor stops executing instructions ..." paragraph
Added NOTE about GPIO_MUX1 pins PF6_GPIO38 and PG6_GPIO46
Section 2.14
Shared Resources Clocking:
•
•
Updated "... are clocked by PLLSYSCLK." paragraph
Added "EPI is a shared peripheral ..." paragraph
Section 2.15
Section 2.16
Added "Loss of Input Clock (NMI Watchdog Function)" section
GPIOs and Other Pins:
•
Updated "Most of the I/O pins of the Concerto™ MCU ..." paragraph
6
Contents
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
LOCATION
ADDITIONS, DELETIONS, AND MODIFICATIONS
Section 2.16.1
GPIO_MUX1:
•
•
•
•
•
Updated " ... pins of the GPIO_MUX1 block can be selectively mapped ..." paragraph
Updated "Pin-Level Mux assigns Master Subsystem peripheral signals ..." paragraph
Updated "The configuration registers for the muxing of Master Subsystem peripherals ..." paragraph
Updated "In addition to passing mostly digital signals ..." paragraph
Added NOTE about GPIO_MUX1 pins PF6_GPIO38 and PG6_GPIO46
Figure 2-13
Figure 2-14
Figure 2-15
Table 2-27
Updated "GPIOs and Other Pins" figure
Updated "GPIO_MUX1 Block" figure
Updated "GPIO_MUX1 Pin Mapping Through Register Set A" figure
GPIO_MUX1 Pin Assignments (M3 Primary Modes):
•
•
•
•
•
•
•
PB6_GPIO14: Updated "M3 Primary Mode 8" column
PB7_GPIO15: Updated "M3 Primary Mode 8" column
PE4_GPIO28: Updated "M3 Primary Mode 8" column
PE5_GPIO29: Updated "M3 Primary Mode 8" column
PF2_GPIO34: Updated "M3 Primary Mode 8" column
PF3_GPIO35: Updated "M3 Primary Mode 8" column
PF6_GPIO38:
–
–
–
–
Updated "M3 Primary Mode 1" column
Updated "M3 Primary Mode 3" column
Updated "M3 Primary Mode 8" column
Updated "M3 Primary Mode 10" column
•
•
•
PG2_GPIO42: Updated "M3 Primary Mode 8" column
PG5_GPIO45: Updated "M3 Primary Mode 8" column
PG6_GPIO46:
–
–
–
Updated "M3 Primary Mode 3" column
Updated "M3 Primary Mode 8" column
Updated "M3 Primary Mode 10" column
•
Added footnote about muxing option availability
Table 2-28
GPIO_MUX1 Pin Assignments (M3 Alternate Modes):
•
•
•
PA6_GPIO6: Updated "M3 Alternate Mode 12" column
PE4_GPIO28: Updated "M3 Alternate Mode 14" column
Added footnote about muxing option availability
Table 2-29
GPIO_MUX1 Pin Assignments (C28x Peripheral Modes):
•
•
PF6_GPIO38: Updated "C28x Peripheral Mode 0" column
PG6_GPIO46: Updated "C28x Peripheral Mode 0" column
Section 2.16.2
GPIO_MUX2:
•
Updated "Peripheral Modes 0, 1, 2, and 3 are chosen ..." paragraph
Table 2-30
Figure 2-16
Section 2.17
Section 2.18
Section 2.19
Figure 3-1
Updated "GPIO_MUX2 Pin Assignments (C28x Peripheral Modes)" table
Updated "Pin Muxing on AIO_MUX1, AIO_MUX2, and GPIO_MUX2" figure
Added "Emulation/JTAG" section
Added "Code Security Module (CSM)" section
Added "µCRC Module" section
144-Pin RFP PowerPAD™ HTQFP (Top View):
•
•
•
•
•
•
•
•
•
•
•
Pin 109: Changed signal name from "GPIO199/COMP5OUT" to "GPIO135/COMP5OUT"
Pin 110: Changed signal name from "GPIO198" to "GPIO134"
Pin 111: Changed signal name from "GPIO197/COMP4OUT" to "GPIO133/COMP4OUT"
Pin 112: Changed signal name from "GPIO196/COMP3OUT" to "GPIO132/COMP3OUT"
Pin 118: Changed signal name from "ADC1VREFLO, VSSA1" to "VSSA1
Pin 135: Changed signal name from "ADC2VREFLO, VSSA2" to "VSSA2
Pin 140: Changed signal name from "GPIO192" to "GPIO128"
"
"
Pin 141: Changed signal name from "GPIO193/COMP1OUT" to "GPIO129/COMP1OUT"
Pin 142: Changed signal name from "GPIO194/COMP6OUT" to "GPIO130/COMP6OUT"
Pin 143: Changed signal name from "GPIO195/COMP2OUT" to "GPIO131/COMP2OUT"
Added footnote about GPIO135
Copyright © 2011–2012, Texas Instruments Incorporated
Contents
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
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LOCATION
Section 3.2
ADDITIONS, DELETIONS, AND MODIFICATIONS
Terminal Functions:
Removed "Input Clock Configurations" figure. This figure is being replaced by the new "Connecting
Input Clocks to a Concerto Device" figure (Figure 2-7).
Terminal Functions:
•
Table 3-1
•
•
•
•
Made extensive updates to Terminal Functions table
Added footnote about pullup and pulldown
Added footnote about GPIO135
Added footnote about muxing option availability
Section 4.1
Section 4.2
Absolute Maximum Ratings:
Added Free-Air temperature, TA
Recommended Operating Conditions:
•
•
•
•
Added Free-Air temperature, TA
Updated Junction temperature, TJ
Removed footnote about ambient temperature
Section 5
Section 5
Added "Electrical Specifications" section
Electrical Specifications:
•
Moved "Current Consumption" section from "Peripheral Information and Timings" section to "Electrical
Specifications" section
•
Moved "Power Sequencing" section from "Peripheral Information and Timings" section to "Electrical
Specifications" section
Table 5-1
Table 5-1
Changed table title from "F28M35Hx Current Consumption at 150-MHz C28x SYSCLKOUT and 75-MHz
M3SSCLK" to "Current Consumption at 150-MHz C28x SYSCLKOUT and 75-MHz M3SSCLK"
Updated "Current Consumption at 150-MHz C28x SYSCLKOUT and 75-MHz M3SSCLK" table and
footnotes
Section 5.2
Section 5.3
Section 5.4
Section 5.5
Section 5.5.1
Table 5-14
Section 6.1
Figure 6-1
Added "Thermal Design Considerations" section
Added "Timing Parameter Symbology" section
Added "Clock Frequencies, Requirements, and Characteristics" section
Updated "Power Sequencing" section
Added "Changing the Frequency of the Main PLL" section
Updated "Power Management and Supervisory Circuit Solutions" table
Updated "Analog and Shared Peripherals" section
Updated "ADC" figure
Section 6.1.1.3
Section 6.1.2
Figure 6-2
Updated "Analog Inputs" section
Updated "Comparator + DAC Units" section
Updated "Comparator + DAC Units" figure
Section 6.1.3
Figure 6-3
Updated "Inter-Processor Communications (IPC)" section
Updated "Interprocessor Communications (IPC)" figure
Updated "External Peripheral Interface (EPI)" section
Master Subsystem Peripherals:
Section 6.1.4
Section 6.2
•
Updated "Master Subsystem peripherals are located on the APB Bus and AHB Bus ..." paragraph
Section 6.2.1
Section 6.2.2
Section 6.2.3
Section 6.2.4
Section 6.2.5
Section 6.2.6
Section 6.3
Added "Synchronous Serial Interface (SSI)" section
Added "Universal Asynchronous Receiver/Transmitter (UART)" section
Added "Cortex™-M3 Inter-Integrated Circut (I2C)" section
Added "Cortex™-M3 Controller Area Network (CAN)" section
Added "Cortex™-M3 Universal Serial Bus (USB) Controller" section
Added "Cortex™-M3 Ethernet Media Access Controller (EMAC)" section
Control Subsystem Peripherals:
•
Updated "Control Subsystem peripherals are accessible from the C28x CPU ..." paragraph
Section 6.3.1
Section 6.3.1
Changed section title from "Pulse Width Modulator (PWM) and High-Resolution PWM (HRPWM) Modules"
to "High-Resolution PWM (HRPWM) and Enhanced PWM (ePWM) Modules"
High-Resolution PWM (HRPWM) and Enhanced PWM (ePWM) Modules:
•
Updated "There are 9 SOCA PWM outputs and 9 SOCB PWM outputs ..." paragraph
8
Contents
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
LOCATION
Figure 6-15
ADDITIONS, DELETIONS, AND MODIFICATIONS
Changed figure caption from "ePWM, eQEP, eCAP" to "PWM, eCAP, eQEP"
Figure 6-15
Figure 6-16
Figure 6-16
Section 6.3.2
Section 6.3.3
Section 6.3.4
Section 6.3.5
Section 6.3.6
Section 6.3.7
Section 8.1
Updated "PWM, eCAP, eQEP" figure
Changed figure caption from "ePWM/HRPWM" to "Internal Structure of PWM"
Updated "Internal Structure of PWM" figure
Added "Enhanced Capture (eCAP) Module" section
Added "Enhanced Quadrature Encoder Pulse (eQEP) Module" section
Added "C28x Inter-Integrated Circuit Module (I2C)" section
Added "C28x Serial Communications Interface (SCI)" section
Added "C28x Serial Peripheral Interface (SPI)" section
Added "C28x Multichannel Buffered Serial Port (McBSP)" section
Added "Thermal Data for Package" section
Copyright © 2011–2012, Texas Instruments Incorporated
Contents
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
2 Device Overview
The Concerto™ microcontroller (MCU) comprises three subsystems: the Master Subsystem, the Control
Subsystem, and the Analog Subsystem. While the Master and Control Subsystem each have dedicated
local memories and peripherals, they can also share data and events through shared memories and
peripherals. The Analog Subsystem has two ADC converters and six Analog Comparators. Both the
Master and Control Subsystems access the Analog Subsystem through the Analog Common Interface
Bus (ACIB). The NMI Blocks force communication of critical events to the Master and Control Subsystem
processors and their Watchdog Timers. The Reset Block responds to Watchdog Timer NMI Reset,
External Reset, and other events to initialize subsystem processors and the rest of the chip to a known
state. The Clocking Blocks support multiple low-power modes where clocks to the processors and
peripherals can be slowed down or stopped in order to manage power consumption.
NOTE
Throughout this document, the Master Subsystem is denoted by the color "blue"; the Control
Subsystem is denoted by the color "green"; and the Analog Subsystem is denoted by the
color "orange".
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
2.1 Device Characteristics
Table 2-1 lists the features of the F28M35Hx devices.
Table 2-1. Hardware Features
FEATURE
TYPE(1)
H20B1
H20C1
H22B1
H22C1
H32B1
H32C1
H50B1
H50C1
H52B1
H52C1
Master Subsystem — ARM® Cortex™-M3
Speed (MHz)
Flash (KB)
–
–
–
–
–
–
0
0
100(2)
256
16
100(2)
256
16
100(2)
256
16
100(2)
256
16
100(2)
256
16
100(2)
512
16
100(2)
512
16
100(2)
512
16
100(2)
512
16
100(2)
512
16
RAM ECC (KB)
RAM Parity (KB)
16
16
16
16
16
16
16
16
16
16
IPC Message RAM Parity (KB)
Security Zones
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
10/100 ENET 1588 MII
USB OTG FS
No
No
Yes
Yes
No
No
Yes
Yes
No
No
Yes
Yes
No
No
Yes
Yes
No
No
Yes
Yes
Synchronous Serial Interface (SSI)/
Serial Peripheral Interface (SPI)
0
4
4
4
4
4
4
4
4
4
4
Universal Asynchronous Receiver/Transmitter (UART)
Inter-integrated circuit (I2C)
0
0
0
0
0
0
–
–
5
5
5
5
5
5
5
5
5
5
2
2
2
2
2
2
2
2
2
2
Controller Area Network (CAN)
2
2
2
2
2
2
2
2
2
2
Direct Memory Access (µDMA)
32-ch
32-ch
32-ch
32-ch
32-ch
32-ch
32-ch
32-ch
32-ch
32-ch
External Peripheral Interface (EPI)
Micro Cyclic Redundancy Check (µCRC) Module
General-Purpose Timers
1
1
4
2
1
1
4
2
1
1
4
2
1
1
4
2
1
1
4
2
1
1
4
2
1
1
4
2
1
1
4
2
1
1
4
2
1
1
4
2
Watchdog Timer Modules
Control Subsystem — C28x Floating-Point Unit (FPU)/Viterbi, Complex Math, CRC Unit (VCU)
Speed (MHz)
150
256
20
16
2
150
256
20
16
2
150
256
20
16
2
150
256
20
16
2
150
512
20
16
2
150
256
20
16
2
150
512
20
16
2
150
512
20
16
2
150
512
20
16
2
150
512
20
16
2
Flash (KB)
RAM ECC (KB)
RAM Parity (KB)
IPC Message RAM Parity (KB)
Security Zones
1
1
1
1
1
1
1
1
1
1
Enhanced Pulse Width Modulator (ePWM) modules
High-Resolution PWM outputs
2
2
9: 18 outputs
16 outputs
Enhanced Capture (eCAP) modules/
PWM outputs
0
6 (32-bit)
3 (32-bit)
Enhanced Quadrature Encoder (eQEP) modules
Fault Trip Zones
0
–
12 on any of 64 GPIO pins
(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor differences between devices that do not affect the
basic functionality of the module. These device-specific differences are listed in the TMS320x28xx, 28xxx DSP Peripheral Reference Guide (literature number SPRU566) and in the
peripheral reference guides.
(2) An integer divide ratio must be maintained between the C28x and Cortex™-M3 clock frequencies; thus, when the C28x is configured to run at maximum frequency of 150 MHz, the fastest
allowable frequency for the Cortex™-M3 will be 75 MHz.
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
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Table 2-1. Hardware Features (continued)
FEATURE
TYPE(1)
H20B1
H20C1
H22B1
H22C1
H32B1
H32C1
H50B1
H50C1
H52B1
H52C1
Multichannel Buffered Serial Port (McBSP)/
Serial Peripheral Interface (SPI)
1
1
1
1
1
1
1
1
1
1
1
Serial Communications Interface (SCI)
Serial Peripheral Interface (SPI)
Inter-integrated circuit (I2C)
Direct Memory Access (DMA)
32-Bit Timers
0
0
0
0
–
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
6-ch
3
6-ch
3
6-ch
3
6-ch
3
6-ch
3
6-ch
3
6-ch
3
6-ch
3
6-ch
3
6-ch
3
Shared
Supplemental RAM (KB)
MSPS
0
2.88
350 ns
10
0
2.88
350 ns
10
64
2.88
350 ns
10
64
2.88
350 ns
10
64
2.88
350 ns
10
64
2.88
350 ns
10
0
2.88
350 ns
10
0
2.88
350 ns
10
64
2.88
350 ns
10
64
2.88
350 ns
10
Conversion Time
12-Bit ADC 1
Channels
3
Sample-and-Hold (S/H)
MSPS
2
2
2
2
2
2
2
2
2
2
2.88
350 ns
10
2.88
350 ns
10
2.88
350 ns
10
2.88
350 ns
10
2.88
350 ns
10
2.88
350 ns
10
2.88
350 ns
10
2.88
350 ns
10
2.88
350 ns
10
2.88
350 ns
10
Conversion Time
12-Bit ADC 2
Channels
3
0
Sample-and-Hold (S/H)
Comparators with Integrated DACs
Voltage Regulator and Monitor
Clocking
2
2
2
2
2
2
2
2
2
2
6
6
6
6
6
6
6
6
6
6
Yes – Uses 3.3-V Single Supply (3.3-V/1.2-V recommended for 125ºC)
See Section 2.10
Additional Safety
Master Subsystem
Control Subsystem
Shared
2 Watchdogs, NMI Watchdog: CPU, Memory
NMI Watchdog: CPU, Memory
Critical Register and I/O Function Lock Protection; RAM Fetch Protection
Packaging
144-Pin RFP PowerPAD™
Package Type
HTQFP
Available at Prototype Sampling
T: –40°C to 105°C
–
–
–
–
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
Temperature options
Product status(6)
S: –40°C to 125°C
Q: –40°C to 125°C(3)(4)(5)
No
No
No
No
No
No
No
No
No
No
xF28M35...
xF28M35...
xF28M35...
xF28M35...
xF28M35...
xF28M35...
xF28M35...
xF28M35...
xF28M35...
xF28M35...
(3) "Q" refers to Q100 qualification for automotive applications.
(4) The "Q" temperature option is not available for the F28M35Mxxx1 series.
(5) The "Q" temperature option is not available for the F28M35ExxC1 series, but this temperature option will be available for the F28M35ExxB1 series.
(6) The "xF28M35..." product status denotes an experimental device that is not necessarily representative of the final device's electrical specifications. See Section 7.1.2, Device
Nomenclature, for descriptions of device stages.
12
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
2.2 Memory Maps
Section 2.2.1 shows the Control Subsystem Memory Map. Section 2.2.2 shows the Master Subsystem
Memory Map.
2.2.1 Control Subsystem Memory Map
Table 2-2. Control Subsystem M0, M1 RAM
C Address
Size
(Bytes)
C DMA Access(1)
Control Subsystem M0, M1 RAM
(x16 Aligned)(1)
no
no
0000 0000 – 0000 03FF
0000 0400 – 0000 07FF
M0 RAM (ECC)
M1 RAM (ECC)
2K
2K
(1) The letter "C" refers to the Control Subsystem.
Table 2-3. Control Subsystem Peripheral Frame 0 (Includes Analog)
C Address
Control Subsystem Peripheral Frame 0
(Includes Analog)
Size
(Bytes)
C DMA Access(1)
(x16 Aligned)(1)
0000 0800 – 0000 087F
Reserved
Control Subsystem Device Configuration Registers (Read
Only)
no
0000 0880 – 0000 0890
34
0000 0891 – 0000 0ADF
0000 0AE0 – 0000 0AEF
0000 0AF0 – 0000 0AFF
0000 0B00 – 0000 0B0F
0000 0B10 – 0000 0B3F
0000 0B40 – 0000 0B4F
0000 0B50 – 0000 0BFF
0000 0C00 – 0000 0C07
0000 0C08 – 0000 0C0F
0000 0C10 – 0000 0C17
0000 0C18 – 0000 0CDF
0000 0CE0 – 0000 0CFF
0000 0D00 – 0000 0DFF
0000 0E00 – 0000 0EFF
0000 0F00 – 0000 0FFF
0000 1000 – 0000 11FF
0000 1200 – 0000 16FF
0000 1700 – 0000 177F
0000 1780 – 0000 17FF
0000 1800 – 0000 3FFF
Reserved
no
C28x CSM Registers
Reserved
32
32
32
yes
yes
ADC1 Result Registers
Reserved
ADC2 Result Registers
Reserved
no
no
no
CPU Timer 0
16
16
16
CPU Timer 1
CPU Timer 2
Reserved
no
no
no
PIE Registers
64
PIE Vector Table
PIE Vector Table Copy (Read Only)
Reserved
512
512
no
C28x DMA Registers
Reserved
1K
no
no
Analog Subsystem Control Registers
C Hardware Logic BIST Registers
Reserved
256
256
(1) The letter "C" refers to the Control Subsystem.
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
Table 2-4. Control Subsystem Peripheral Frame 3
C Address
Control Subsystem
Peripheral Frame 3
Size
(Bytes)
M Address
µDMA
Access
C DMA Access(1)
(x16 Aligned)(1)
(Byte-Aligned)(2)
no
0000 4000 – 0000 4181
0000 4182 – 0000 42FF
C28x Flash Control Registers
Reserved
772
C28x Flash ECC Error Log
Registers
no
0000 4300 – 0000 4323
72
0000 4324 – 0000 43FF
0000 4400 – 0000 443F
0000 4440 – 0000 48FF
0000 4900 – 0000 497F
0000 4980 – 0000 49FF
Reserved
M Clock Control Registers(2)
no
no
128
256
400F B800 – 400F B87F
400F B200 – 400F B2FF
no
no
Reserved
RAM Configuration Registers
Reserved
RAM ECC/Parity/Access Error
Log Registers
no
0000 4A00 – 0000 4A7F
256
400F B300 – 400F B3FF
400F B700 – 400F B77F
no
no
0000 4A80 – 0000 4DFF
0000 4E00 – 0000 4E3F
0000 4E40 – 0000 4FFF
0000 5000 – 0000 503F
0000 5040 – 0000 50FF
0000 5100 – 0000 517F
0000 5180 – 0000 51FF
0000 5200 – 0000 527F
0000 5280 – 0000 52FF
0000 5300 – 0000 537F
0000 5380 – 0000 53FF
0000 5400 – 0000 547F
0000 5480 – 0000 54FF
0000 5500 – 0000 557F
0000 5580 – 0000 57FF
Reserved
no
CtoM and MtoC IPC Registers
Reserved
128
128
yes
McBSP-A
Reserved
yes
yes
yes
yes
yes
yes
yes
yes
yes
EPWM1 (Hi-Resolution)
EPWM2 (Hi-Resolution)
EPWM3 (Hi-Resolution)
EPWM4 (Hi-Resolution)
EPWM5 (Hi-Resolution)
EPWM6 (Hi-Resolution)
EPWM7 (Hi-Resolution)
EPWM8 (Hi-Resolution)
EPWM9
256
256
256
256
256
256
256
256
256
Reserved
(1) The letter "C" refers to the Control Subsystem.
(2) The letter "M" refers to the Master Subsystem.
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
Table 2-5. Control Subsystem Peripheral Frame 1
C Address
Size
(Bytes)
C DMA Access(1)
Control Subsystem Peripheral Frame 1
Reserved
(x16 Aligned)(1)
0000 5800 – 0000 59FF
0000 5A00 – 0000 5A1F
0000 5A20 – 0000 5A3F
0000 5A40 – 0000 5A5F
0000 5A60 – 0000 5A7F
0000 5A80 – 0000 5A9F
0000 5AA0 – 0000 5ABF
0000 5AC0 – 0000 5AFF
0000 5B00 – 0000 5B3F
0000 5B40 – 0000 5B7F
0000 5B80 – 0000 5BBF
0000 5BC0 – 0000 5F7F
0000 5F80 – 0000 5FFF
0000 6000 – 0000 63FF
0000 6400 – 0000 641F
0000 6420 – 0000 643F
0000 6440 – 0000 645F
0000 6460 – 0000 647F
0000 6480 – 0000 649F
0000 64A0 – 0000 64BF
0000 64C0 – 0000 6F7F
0000 6F80 – 0000 6FFF
no
no
no
no
no
no
ECAP1
64
64
64
64
64
64
ECAP2
ECAP3
ECAP4
ECAP5
ECAP6
Reserved
no
no
no
EQEP1
128
128
128
EQEP2
EQEP3
Reserved
C GPIO Group 1 Registers(1)
no
256
Reserved
no
no
no
no
no
no
COMP1 Registers
COMP2 Registers
COMP3 Registers
COMP4 Registers
COMP5 Registers
COMP6 Registers
Reserved
64
64
64
64
64
64
no
C GPIO Group 2 Registers and AIO Mux Registers(1)
256
(1) The letter "C" refers to the Control Subsystem.
Table 2-6. Control Subsystem Peripheral Frame 2
C Address
Size
(Bytes)
C DMA Access(1)
Control Subsystem Peripheral Frame 2
Reserved
(x16 Aligned)(1)
0000 7000 – 0000 70FF
0000 7010 – 0000 702F
0000 7030 – 0000 703F
0000 7040 – 0000 704F
0000 7050 – 0000 705F
0000 7060 – 0000 706F
0000 7070 – 0000 707F
0000 7080 – 0000 70FF
no
C28x System Control Registers
64
Reserved
no
no
no
no
SPI-A
32
32
32
32
SCI-A
NMI Watchdog Interrupt Registers
External Interrupt Registers
Reserved
ADC1 Configuration Registers
(Only 16-bit read/write access supported)
no
no
0000 7100 – 0000 717F
0000 7180 – 0000 71FF
256
256
ADC2 Configuration Registers
(Only 16-bit read/write access supported)
0000 7200 – 0000 78FF
0000 7900 – 0000 793F
0000 7940 – 0000 7FFF
Reserved
I2C-A
no
128
Reserved
(1) The letter "C" refers to the Control Subsystem.
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
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Table 2-7. Control Subsystem RAMs
C Address
Size
(Bytes)
M Address
µDMA
Access
C DMA Access(1)
Control Subsystem RAMs
(x16 Aligned)(1)
(Byte-Aligned)(2)
no
0000 8000 – 0000 8FFF
0000 9000 – 0000 9FFF
0000 A000 – 0000 AFFF
0000 B000 – 0000 BFFF
0000 C000 – 0000 CFFF
0000 D000 – 0000 DFFF
0000 E000 – 0000 EFFF
0000 F000 – 0000 FFFF
0001 0000 – 0001 0FFF
0001 1000 – 0001 1FFF
0001 2000 – 0001 2FFF
0001 3000 – 0001 3FFF
0001 4000 – 0003 F7FF
L0 RAM (ECC, Secure)
L1 RAM (ECC, Secure)
L2 RAM (Parity, Interleaving)
L3 RAM (Parity, Interleaving)
S0 RAM (Parity, Shared)
S1 RAM (Parity, Shared)
S2 RAM (Parity, Shared)
S3 RAM (Parity, Shared)
S4 RAM (Parity, Shared)
S5 RAM (Parity, Shared)
S6 RAM (Parity, Shared)
S7 RAM (Parity, Shared)
Reserved
8K
8K
8K
8K
8K
8K
8K
8K
8K
8K
8K
8K
no
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
2000 8000 – 2000 9FFF
2000 A000 – 2000 BFFF
2000 C000 – 2000 DFFF
2000 E000 – 2000 FFFF
2001 0000 – 2001 1FFF
2001 2000 – 2001 3FFF
2001 4000 – 2001 5FFF
2001 6000 – 2001 7FFF
yes
yes
yes
yes
yes
yes
yes
yes
yes
read only
yes
0003 F800 – 0003 FBFF
0003 FC00 – 0003 FFFF
CtoM MSG RAM (Parity)
MtoC MSG RAM (Parity)
2K
2K
2007 F000 – 2007 F7FF
2007 F800 – 2007 FFFF
yes
read only
yes
0004 0000 – 0004 7FFF
0004 8000 – 0004 8FFF
0004 9000 – 0004 9FFF
0004 A000 – 0004 AFFF
0004 B000 – 0004 BFFF
0004 C000 – 0004 CFFF
0004 D000 – 0004 DFFF
0004 E000 – 0004 EFFF
0004 F000 – 0004 FFFF
0005 0000 – 0005 0FFF
0005 1000 – 0005 1FFF
0005 2000 – 0005 2FFF
0005 3000 – 0005 3FFF
0005 4000 – 0007 EFFF
0007 F000 – 0007 F3FF
0007 F400 – 0007 F7FF
0007 F800 – 0007 FBFF
0007 FC00 – 0007 FFFF
0008 0000 – 0009 FFFF
Reserved
no
no
no
no
no
no
no
no
no
no
no
no
L0 RAM - ECC Bits
L1 RAM - ECC Bits
L2 RAM - Parity Bits
L3 RAM - Parity Bits
S0 RAM - Parity Bits
S1 RAM - Parity Bits
S2 RAM - Parity Bits
S3 RAM - Parity Bits
S4 RAM - Parity Bits
S5 RAM - Parity Bits
S6 RAM - Parity Bits
S7 RAM - Parity Bits
Reserved
8K
8K
8K
8K
8K
8K
8K
8K
8K
8K
8K
8K
2008 8000 – 2008 9FFF
2008 A000 – 2008 BFFF
2008 C000 – 2008 DFFF
2008 E000 – 2008 FFFF
2009 0000 – 2009 1FFF
2009 2000 – 2009 3FFF
2009 4000 – 2009 5FFF
2009 6000 – 2009 7FFF
no
no
no
no
no
no
no
no
no
no
no
no
M0 RAM - ECC Bits
M1 RAM - ECC Bits
CtoM MSG RAM - Parity Bits
MtoC MSG RAM - Parity Bits
Reserved
2K
2K
2K
2K
200F F000 – 200F F7FF
200F F800 – 200F FFFF
no
no
(1) The letter "C" refers to the Control Subsystem.
(2) The letter "M" refers to the Master Subsystem.
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
Table 2-8. Control Subsystem Flash, ECC, OTP, Boot ROM
C Address
Control Subsystem
Flash, ECC, OTP, Boot ROM
Size
(Bytes)
M Address
µDMA
Access
C DMA Access(1)
(x16 Aligned)(1)
(Byte-Aligned)(2)
Sector N (not available for
256KB Flash configuration)
no
no
no
no
no
no
no
0010 0000 – 0010 1FFF
0010 2000 – 0010 3FFF
0010 4000 – 0010 5FFF
0010 6000 – 0010 7FFF
0010 8000 – 0010 FFFF
0011 0000 – 0011 7FFF
0011 8000 – 0011 FFFF
16K
16K
16K
16K
64K
64K
64K
Sector M (not available for
256KB Flash configuration)
Sector L (not available for
256KB Flash configuration)
Sector K (not available for
256KB Flash configuration)
Sector J (not available for
256KB Flash configuration)
Sector I (not available for
256KB Flash configuration)
Sector H (not available for
256KB Flash configuration)
no
no
no
no
no
no
0012 0000 – 0012 7FFF
0012 8000 – 0012 FFFF
0013 0000 – 0013 7FFF
0013 8000 – 0013 9FFF
0013 A000 – 0013 BFFF
0013 C000 – 0013 DFFF
Sector G
Sector F
Sector E
Sector D
Sector C
Sector B
64K
64K
64K
16K
16K
16K
Sector A
no
0013 E000 – 0013 FFFF
(CSM password in the high
address)
16K
0014 0000 – 001F FFFF
0020 0000 – 0020 7FFF
Reserved
Flash - ECC Bits
(1/8 of Flash used = 64 KBytes)
no
no
64K
1K
0020 8000 – 0024 01FF
0024 0200 – 0024 03FF
0024 0400 – 002F FFFF
Reserved
TI OTP
Reserved
EPI0
yes
no
0030 0000 – 003F 7FFF
003F 8000 – 003F FFFF
(External Peripheral/Memory
2G
6000 0000 – DFFF FFFF
yes
Interface)(3)
C28x Boot ROM (64 KBytes)
64K
(1) The letter "C" refers to the Control Subsystem.
(2) The letter "M" refers to the Master Subsystem.
(3) The Control Subsystem has no direct access to EPI in silicon revision 0 devices.
Copyright © 2011–2012, Texas Instruments Incorporated
Device Overview
17
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
2.2.2 Master Subsystem Memory Map
Table 2-9. Master Subsystem Flash, ECC, OTP, Boot ROM
M Address
Size
(Bytes)
µDMA Access
Master Subsystem Flash, ECC, OTP, Boot ROM
(Byte-Aligned)(1)
Boot ROM - Dual-mapped to 0x0100 0000
(Both maps access same physical location.)
no
0000 0000 – 0000 FFFF
0001 0000 – 001F FFFF
0020 0000 – 0020 3FFF
64K
Reserved
Sector N
no
16K
(Zone 1 CSM password in the low address.)
no
no
no
no
no
no
no
no
no
no
no
no
0020 4000 – 0020 7FFF
0020 8000 – 0020 BFFF
0020 C000 – 0020 FFFF
0021 0000 – 0021 FFFF
0022 0000 – 0022 FFFF
0023 0000 – 0023 FFFF
0024 0000 – 0024 FFFF
0025 0000 – 0025 FFFF
0026 0000 – 0026 FFFF
0027 0000 – 0027 3FFF
0027 4000 – 0027 7FFF
0027 8000 – 0027 BFFF
Sector M
16K
16K
16K
64K
64K
64K
64K
64K
64K
16K
16K
16K
Sector L
Sector K
Sector J
Sector I (not available for 256KB Flash configuration)
Sector H (not available for 256KB Flash configuration)
Sector G (not available for 256KB Flash configuration)
Sector F (not available for 256KB Flash configuration)
Sector E
Sector D
Sector C
Sector B
Sector A
no
0027 C000 – 0027 FFFF
0028 0000 – 005F FFFF
0060 0000 – 0060 FFFF
16K
(Zone 2 CSM password in the high address.)
Reserved
Flash - ECC Bits
(1/8 of Flash used = 64 KBytes)
no
64K
0061 0000 – 0068 047F
0068 0480 – 0068 07FF
0068 0800
Reserved
no
no
TI OTP
896
4
OTP – Security Lock
Reserved
0068 0804
0068 0808
Reserved
no
no
no
0068 080C
OTP – Zone 2 Flash Start Address
OTP – EMAC Address 0
OTP – EMAC Address 1
Reserved
4
4
4
0068 0810
0068 0814
0068 0818 – 0070 00FF
OTP – ECC Bits – Application Use
(1/8 of OTP used = 3 Bytes)
no
no
0070 0100 – 0070 0102
0070 0103 – 00FF FFFF
0100 0000 – 0100 FFFF
0101 0000 – 03FF FFFF
3
Reserved
Boot ROM – Dual-mapped to 0x0000 0000
(Both maps access same physical location.)
64K
Reserved
ROM/Flash/OTP/Boot ROM – Mirror-mapped for µCRC.
Accessing this area of memory by the µCRC peripheral
will cause an access in 0000 0000 – 03FF FFFF
memory space.
Mirrored boot ROM: 0x0400 0000 – 0x0400 FFFF (Not
dual-mapped ROM address)
no
0400 0000 – 07FF FFFF
0800 0000 – 1FFF FFFF
64M
Mirrored Flash bank: 0x0420 0000 – 0x042F FFFF
Mirrored Flash OTP: 0x0468 0000 – 0x0468 1FFF
(Read cycles from this space cause the µCRC peripheral
to continuously update data checksum inside a register,
when reading a block of data.)
Reserved
(1) The letter "M" refers to the Master Subsystem.
18 Device Overview
Copyright © 2011–2012, Texas Instruments Incorporated
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
www.ti.com
SPRS742D –JUNE 2011–REVISED AUGUST 2012
Table 2-10. Master Subsystem RAMs
µDMA
Access
M Address
Size
(Bytes)
C Address
Master Subsystem RAMs
C DMA Access(2)
(Byte-Aligned)(1)
(x16 Aligned)(2)
no
2000 0000 – 2000 1FFF
2000 2000 – 2000 3FFF
2000 4000 – 2000 5FFF
2000 6000 – 2000 7FFF
2000 8000 – 2000 9FFF
2000 A000 – 2000 BFFF
2000 C000 – 2000 DFFF
2000 E000 – 2000 FFFF
2001 0000 – 2001 1FFF
2001 2000 – 2001 3FFF
2001 4000 – 2001 5FFF
2001 6000 – 2001 7FFF
2001 8000 – 2007 EFFF
C0 RAM (ECC, Secure)
C1 RAM (ECC, Secure)
C2 RAM (Parity)
8K
8K
8K
8K
8K
8K
8K
8K
8K
8K
8K
8K
no
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
C3 RAM (Parity)
S0 RAM (Parity, Shared)
S1 RAM (Parity, Shared)
S2 RAM (Parity, Shared)
S3 RAM (Parity, Shared)
S4 RAM (Parity, Shared)
S5 RAM (Parity, Shared)
S6 RAM (Parity, Shared)
S7 RAM (Parity, Shared)
Reserved
0000 C000 – 0000 CFFF
0000 D000 – 0000 DFFF
0000 E000 – 0000 EFFF
0000 F000 – 0000 FFFF
0001 0000 – 0001 0FFF
0001 1000 – 0001 1FFF
0001 2000 – 0001 2FFF
0001 3000 – 0001 3FFF
yes
yes
yes
yes
yes
yes
yes
yes
yes
read only
2007 F000 – 2007 F7FF
2007 F800 – 2007 FFFF
CtoM MSG RAM (Parity)
MtoC MSG RAM (Parity)
2K
2K
0003 F800 – 0003 FBFF
0003 FC00 – 0003 FFFF
yes
yes
read only
yes
no
no
no
no
no
no
no
no
no
no
no
no
2008 0000 – 2008 1FFF
2008 2000 – 2008 3FFF
2008 4000 – 2008 5FFF
2008 6000 – 2008 7FFF
2008 8000 – 2008 9FFF
2008 A000 – 2008 BFFF
2008 C000 – 2008 DFFF
2008 E000 – 2008 FFFF
2009 0000 – 2009 1FFF
2009 2000 – 2009 3FFF
2009 4000 – 2009 5FFF
2009 6000 – 2009 7FFF
2009 8000 – 200F EFFF
200F F000 – 200F F7FF
200F F800 – 200F FFFF
2010 0000 – 21FF FFFF
C0 RAM - ECC Bits
C1 RAM - ECC Bits
C2 RAM - Parity Bits
C3 RAM - Parity Bits
S0 RAM - Parity Bits
S1 RAM - Parity Bits
S2 RAM - Parity Bits
S3 RAM - Parity Bits
S4 RAM - Parity Bits
S5 RAM - Parity Bits
S6 RAM - Parity Bits
S7 RAM - Parity Bits
Reserved
8K
8K
8K
8K
8K
8K
8K
8K
8K
8K
8K
8K
0004 C000 – 0004 CFFF
0004 D000 – 0004 DFFF
0004 E000 – 0004 EFFF
0004 F000 – 0004 FFFF
0005 0000 – 0005 0FFF
0005 1000 – 0005 1FFF
0005 2000 – 0005 2FFF
0005 3000 – 0005 3FFF
no
no
no
no
no
no
no
no
no
no
CtoM MSG RAM - Parity Bits
MtoC MSG RAM - Parity Bits
Reserved
2K
2K
0007 F800 – 0007 FBFF
0007 FC00 – 0007 FFFF
no
no
Bit Banded RAM Zone
(Dedicated address for each
RAM bit of Cortex™-M3 RAM
blocks above)
yes
2200 0000 – 23FF FFFF
32M
All RAM Spaces – Mirror-
Mapped for µCRC.
Accessing this memory by the
µCRC peripheral will cause an
access to
2000 0000 – 23FF FFFF
memory space.
yes
2400 0000 – 27FF FFFF
2800 0000 – 3FFF FFFF
64M
(Read cycles from this space
cause the µCRC peripheral to
continuously update data
checksum inside a register
when reading a block of data.)
Reserved
(1) The letter "M" refers to the Master Subsystem.
(2) The letter "C" refers to the Control Subsystem.
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Device Overview
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
Table 2-11. Master Subsystem Peripherals
µDMA
Access
M Address
Master Subsystem
Peripherals
Size
(Bytes)
C Address
C DMA Access(2)
(Byte-Aligned)(1)
(x16 Aligned)(2)
yes
yes
4000 0000 – 4000 0FFF
4000 1000 – 4000 1FFF
4000 2000 – 4000 3FFF
4000 4000 – 4000 4FFF
4000 5000 – 4000 5FFF
4000 6000 – 4000 6FFF
4000 7000 – 4000 7FFF
4000 8000 – 4000 8FFF
4000 9000 – 4000 9FFF
4000 A000 – 4000 AFFF
4000 B000 – 4000 BFFF
4000 C000 – 4000 CFFF
4000 D000 – 4000 DFFF
4000 E000 – 4000 EFFF
4000 F000 – 4000 FFFF
4001 0000 – 4001 0FFF
4001 1000 – 4001 FFFF
4002 0000 – 4002 07FF
4002 0800 – 4002 0FFF
4002 1000 – 4002 17FF
4002 1800 – 4002 1FFF
4002 2000 – 4002 3FFF
4002 4000 – 4002 4FFF
4002 5000 – 4002 5FFF
4002 6000 – 4002 6FFF
4002 7000 – 4002 7FFF
4002 8000 – 4002 FFFF
4003 0000 – 4003 0FFF
4003 1000 – 4003 1FFF
4003 2000 – 4003 2FFF
4003 3000 – 4003 3FFF
4003 4000 – 4003 CFFF
4003 D000 – 4003 DFFF
4003 E000 – 4003 FFFF
4004 8000 – 4004 8FFF
4004 9000 – 4004 FFFF
4005 0000 – 4005 0FFF
4005 1000 – 4005 7FFF
4005 8000 – 4005 8FFF
4005 9000 – 4005 9FFF
4005 A000 – 4005 AFFF
4005 B000 – 4005 BFFF
4005 C000 – 4005 CFFF
4005 D000 – 4005 DFFF
4005 E000 – 4005 EFFF
Watchdog Timer 0 Registers
Watchdog Timer 1 Registers
Reserved
M GPIO Port A (APB Bus)(1)
M GPIO Port B (APB Bus)(1)
M GPIO Port C (APB Bus)(1)
M GPIO Port D (APB Bus)(1)
SSI0
4K
4K
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
4K
4K
4K
4K
4K
4K
4K
4K
4K
4K
4K
4K
4K
SSI1
SSI2
SSI3
UART0
UART1
UART2
UART3
UART4
Reserved
no
no
no
no
I2C0 Master
2K
2K
2K
2K
I2C0 Slave
I2C1 Master
I2C1 Slave
Reserved
yes
yes
yes
yes
M GPIO Port E (APB Bus)(1)
M GPIO Port F (APB Bus)(1)
M GPIO Port G (APB Bus)(1)
M GPIO Port H (APB Bus)(1)
Reserved
4K
4K
4K
4K
yes
yes
yes
yes
GP Timer 0
4K
4K
4K
4K
GP Timer 1
GP Timer 2
GP Timer 3
Reserved
M GPIO Port J (APB Bus)(1)
yes
yes
yes
4K
4K
4K
Reserved
ENET MAC0
Reserved
USB MAC0
Reserved
yes
yes
yes
yes
yes
yes
yes
M GPIO Port A (AHB Bus)(1)
M GPIO Port B (AHB Bus)(1)
M GPIO Port C (AHB Bus)(1)
M GPIO Port D (AHB Bus)(1)
M GPIO Port E (AHB Bus)(1)
M GPIO Port F (AHB Bus)(1)
M GPIO Port G (AHB Bus)(1)
4K
4K
4K
4K
4K
4K
4K
(1) The letter "M" refers to the Master Subsystem.
(2) The letter "C" refers to the Control Subsystem.
20
Device Overview
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
www.ti.com
SPRS742D –JUNE 2011–REVISED AUGUST 2012
Table 2-11. Master Subsystem Peripherals (continued)
µDMA
Access
M Address
Master Subsystem
Peripherals
Size
(Bytes)
C Address
C DMA Access(2)
(Byte-Aligned)(1)
(x16 Aligned)(2)
yes
yes
4005 F000 – 4005 FFFF
4006 0000 – 4006 0FFF
4006 1000 – 4006 FFFF
4007 0000 – 4007 3FFF
4007 4000 – 4007 7FFF
4007 8000 – 400C FFFF
400D 0000 – 400D 0FFF
400D 1000 – 400F 9FFF
400F A000 – 400F A303
400F A304 – 400F A5FF
M GPIO Port H (AHB Bus)(1)
M GPIO Port J (AHB Bus)(1)
Reserved
4K
4K
no
no
CAN0
16K
16K
CAN1
Reserved
no
no
EPI0 (Registers only)
Reserved
M Flash Control Registers(1)
4K
772
Reserved
M Flash ECC Error Log
Registers(1)
no
400F A600 – 400F A647
72
400F A648 – 400F B1FF
400F B200 – 400F B2FF
Reserved
no
no
RAM Configuration Registers
256
256
0000 4900 – 0000 497F
0000 4A00 – 0000 4A7F
no
no
RAM ECC/Parity/Access Error
Log Registers
400F B300 – 400F B3FF
no
no
400F B400 – 400F B5FF
400F B600 – 400F B67F
400F B680 – 400F B6FF
400F B700 – 400F B77F
400F B780 – 400F B7FF
400F B800 – 400F B87F
400F B880 – 400F B8BF
400F B8C0 – 400F B8FF
M CSM Registers(1)
512
128
µCRC
Reserved
no
CtoM and MtoC IPC Registers
Reserved
M Clock Control Registers(1)
M LPM Control Registers(1)
M Reset Control Registers(1)
128
0000 4E00 – 0000 4E3F
0000 4400 – 0000 443F
no
no
no
no
no
128
64
64
0000 0880 – 0000 0890
(Read Only)
no
400F B900 – 400F B93F
Device Configuration Registers
64
400F B940 – 400F B97F
400F B980 – 400F B9FF
400F BA00 – 400F BA7F
400F BA80 – 400F EFFF
400F F000 – 400F FFFF
4010 0000 – 41FF FFFF
Reserved
no
no
M Write Protect Registers(1)
M NMI Registers(1)
Reserved
128
128
no
µDMA Registers
Reserved
4K
Bit Banded Peripheral Zone
(Dedicated address for each
register bit of Cortex™-M3
peripherals above.)
yes
4200 0000 – 43FF FFFF
4400 0000 – 4FFF FFFF
32M
Reserved
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Device Overview
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
Table 2-12. Master Subsystem Analog and EPI
µDMA
Access
M Address
Master Subsystem
Analog and EPI
Size
(Bytes)
C Address
C DMA Access(2)
(Byte-Aligned)(1)
(x16 Aligned)(2)
5000 0000 – 5000 15FF
5000 1600 – 5000 161F
5000 1620 – 5000 167F
5000 1680 – 5000 169F
5000 16A0 – 5FFF FFFF
Reserved
yes
yes
ADC1 Result Registers
Reserved
32
32
ADC2 Result Registers
Reserved
EPI0
yes
6000 0000 – DFFF FFFF
(External Peripheral/Memory
Interface)
2G
0030 0000 – 003F 7FFF(3)
yes
(1) The letter "M" refers to the Master Subsystem.
(2) The letter "C" refers to the Control Subsystem.
(3) The Control Subsystem has no direct access to EPI in silicon revision 0 devices.
Table 2-13. Cortex™-M3 Private Bus
µDMA
Access
Cortex™-M3 Address
Size
(Bytes)
Cortex™-M3 Private Bus
(Byte-Aligned)
no
no
no
E000 0000 – E000 0FFF
E000 1000 – E000 1FFF
E000 2000 – E000 2FFF
E000 3000 – E000 E007
E000 E008 – E000 E00F
E000 E010 – E000 E01F
E000 E020 – E000 E0FF
E000 E100 – E000 E4EF
E000 E4F0 – E000 ECFF
E000 ED00 – E000 ED3F
E000 ED40 – E000 ED8F
E000 ED90 – E000 EDB8
E000 EDB9 – E000 EEFF
E000 EF00 – E000 EF03
E000 EF04 – FFFF FFFF
ITM (Instrumentation Trace Macrocell)
DWT (Data Watchpoint and Trace)
FPB (Flash Patch and Breakpoint)
Reserved
4K
4K
4K
no
no
System Control Block
System Timer
8
16
Reserved
no
no
no
no
Nested Vectored Interrupt Controller (NVIC)
Reserved
1008
64
System Control Block
Reserved
Memory Protection Unit
Reserved
41
Nested Vectored Interrupt Controller (NVIC)
Reserved
4
NOTE
MPU is not available on silicon revision 0 devices.
22
Device Overview
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
www.ti.com
SPRS742D –JUNE 2011–REVISED AUGUST 2012
2.3 Master Subsystem
The Master Subsystem includes the Cortex™-M3 CPU, µDMA, Nested Vectored Interrupt Controller
(NVIC), Cortex™-M3 Peripherals, and Local Memory. Additionally, the Cortex™-M3 CPU and µDMA can
access the Control Subsystem through Shared Resources: IPC (CPU only), Message RAM, and Shared
RAM; and read ADC Result Registers via the Analog Common Interface Bus. The Master Subsystem can
also receive events from the NMI block and send events to the Resets block.
Figure 2-1 shows the Master Subsystem.
2.3.1 Cortex™-M3 CPU
The 32-bit Cortex™-M3 processor offers high performance, fast interrupt handling, and access to a variety
of communication peripherals (including Ethernet and USB). The Cortex™-M3 features a Memory
Protection Unit (MPU) to provide a privileged mode for protected operating system functionality. A bus
bridge adjacent to the MPU can route program instructions and data on the I-CODE and D-CODE buses
that connect to the Boot ROM and Flash. Other data is typically routed through the Cortex™-M3 System
Bus connected to the local RAMs. The System Bus also goes to the Shared Resources block (also
accessible by the Control Subsystem) and to the Analog Subsystem through the Analog Common
Interface Bus (ACIB). Another bus bridge allows bus cycles from both the Cortex™-M3 System Bus and
those of the µDMA bus to access the Master Subsystem peripherals (via the APB bus or the AHP bus).
Most of the interrupts to the Cortex™-M3 CPU come from the Nested Vectored Interrupt Controller
(NVIC), which manages the interrupt requests from peripherals and assigns handling priorities. There are
also several exceptions generated by Cortex™-M3 CPU that can return to the Cortex™-M3 as interrupts
after being prioritized with other requests inside the NVIC. In addition to programmable priority interrupts,
there are also three levels of fixed-priority interrupts of which the highest priority, level-3, is given to
M3PORRST and M3SYSRST resets from the Resets block. The next highest priority, level-2, is assigned
to the M3NMIINT, which originates from the NMI block. The M3HRDFLT (Hard Fault) interrupt is assigned
to level-1 priority, and this interrupt is caused by one of the error condition exceptions (Memory
Management, Bus Fault, Usage Fault) escalating to Hard Fault because they are not enabled or not
properly serviced.
The Cortex™-M3 CPU has two low-power modes: Sleep and Deep Sleep.
2.3.2 Cortex™-M3 Core Hardware Logic Built-In Test (LBIST)
The Concerto™ microcontroller Cortex™-M3 CPU core includes a Logic Built-In Self Test (LBIST)
controller for testing the CPU core logic for errors. Tests are initiated by software whenever convenient (at
start-up, idle, and so on), which allows for periodic logic tests to ensure that the CPU core logic is working
correctly. During a test cycle, all interrupts are logged by the LBIST controller and re-issued after the test
cycle completes to ensure that no interrupts are missed. In the event of a logic error, the LBIST controller
generates an NMI on both cores to signal that an error has been detected. This action allows for the
software to gracefully handle any detected logic errors.
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Device Overview
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
M3PORRST
M3SYSRST
3
2
1
M3 NMI
RESETS
FIXED
M3NMIINT
M3NMI
M3NMIINT
M3NMIINT
M3HRDFLT
PRIORITY
INTERRUPTS
M3NMIRST
M3WDRST
(1:0)
NVIC
M3 PERIPHERALS
PERIPHERAL
I/O s
M3SWRST
M3DBGRST
APB BUS
AHB BUS
M3
GPTA/B
CPU
USB
MAC
REQ
EMACRX
EMACTX
REQ
UART
(5:1)
REQ
(3:0)
(3:0)
REQ
SSI
EPI
(3:0)
REQ
REQ
BUS
uDMA
MATRIX
DMA INTRS
CAN0/1
(1:0)
USAGE FAULT
SVCALL
ADC
INT
GPIO
(S:A)
IRQ
USB
MAC
IRQ
I2C
UART
(1:5)
IRQ
SSI
GPTA/B DMA
DMA
SW
WDT
(1:0)
IRQ
(0:3)
IRQ
(3:0)
(3:0)
IRQ
ERR
IRQ
(1:0)
IRQ
EPI
EMAC
IRQ
EXCEPTIONS
(1:0)
DBG MONITOR
PENDING SV
SYS TICK
(8:1)
IRQ
IRQ
FROM M3 CORE
IRQ
NVIC
INTERRUPTS
PROGRAM-
MABLE
(NESTED VECTORED INTERRUPT CONTROLLER)
PRIORITY
INTERRUPTS
RAMSINGERR
FLSINGER
FLFSM
CTOM IPC (4:1)
APB BUS (REG ACCESS ONLY)
uDMA BUS
M3 SYSTEM BUS
LOCAL MEMORY
FREQ
GASKET
SECURE
C2 - C3
SECURE
FLASH
(ECC)
S0-S7
MTOC
MSG
CTOM
DATA
MPU /
BOOT
IPC
C0/C1
RAM
RAM
SHARED
RAM
MSG
RAM
BRIDGE
ROM
REGS
INSTRUCTIONS
(parity)
RAM
BUS
(ECC)
(parity)
(parity)
(parity)
BRIDGE
SHARED RESOURCES
I-CODE BUS
D-CODE BUS
RAMACCVIOL
RAMUNCERR
FLASHUNCERR
RAMUNCERR
CONTROL SUBSYSTEM
BUSFAULT
BUS CNTRL/FAULT LOGIC
Figure 2-1. Master Subsystem
24
Device Overview
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
2.3.3 Cortex™-M3 DMA and NVIC
The Cortex™-M3 direct memory access (µDMA) module provides a hardware method of transferring data
between peripherals, between memory, and between peripherals and memory without intervention from
the Cortex™-M3 CPU. The Nested Vectored Interrupt Controller (NVIC) manages and prioritizes interrupt
handling for the Cortex™-M3 CPU.
The Cortex™-M3 peripherals use REQ/DONE handshaking to coordinate data transfer requests with the
µDMA. If a DMA channel is enabled for a given peripheral, REQ/DONE from the peripheral will trigger the
data transfer, following which an IRQ request may be sent from the µDMA to the NVIC to announce to the
Cortex™-M3 that the transfer has completed. If a DMA channel is not enabled for a given peripheral,
REQ/DONE will directly drive IRQ to the NVIC so that the Cortex™-M3 CPU can transfer the data. For
those peripherals that are not supported by the µDMA, IRQs are supplied directly to the NVIC, bypassing
the DMA. This case is true for both Watchdogs, CANs, I2Cs, and the Analog-to-Digital Converters sending
ADCINT[8:1] interrupts from the Analog Subsystem. The NMI Watchdog does not send any events to the
µDMA or the NVIC (only to the Resets block).
2.3.4 Cortex™-M3 Interrupts
Table 2-14 shows all interrupt assignments for the Cortex™-M3 processor. Most interrupts (16–107) are
associated with interrupt requests from Cortex™-M3 peripherals. The first 15 interrupts (1–15) are
processor exceptions generated by the Cortex™-M3 core itself. These processor exceptions are detailed
in Table 2-15.
Table 2-14. Interrupts from NVIC to Cortex™-M3
Interrupt Number
(Bit in Interrupt Registers)
Vector Number
Vector Address or Offset
Description
–
0
0–15
16
0x0000.0000–0x0000.003C
0x0000.0040
0x0000.0044
0x0000.0048
0x0000.004C
0x0000.0050
0x0000.0054
0x0000.0058
0x0000.005C
0x0000.0060
–
Processor exceptions
GPIO Port A
GPIO Port B
GPIO Port C
GPIO Port D
GPIO Port E
UART0
1
17
2
18
3
19
4
20
5
21
6
22
UART1
7
23
SSI0
8
24
I2C0
9–17
18
19
20
21
22
23
24
25–27
28
29
30
31
32
33
34
25–33
34
Reserved
0x0000.0088
0x0000.008C
0x0000.0090
0x0000.0094
0x0000.0098
0x0000.009C
0x0000.00A0
–
Watchdog Timers 0 and 1
Timer 0A
35
36
Timer 0B
37
Timer 1A
38
Timer 1B
39
Timer 2A
40
Timer 2B
41–43
44
Reserved
0x0000.00B0
0x0000.00B4
0x0000.00B8
0x0000.00BC
0x0000.00C0
0x0000.00C4
0x0000.00C8
System Control
Flash State Machine
GPIO Port F
GPIO Port G
GPIO Port H
UART2
45
46
47
48
49
50
SSI1
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
Table 2-14. Interrupts from NVIC to Cortex™-M3 (continued)
Interrupt Number
(Bit in Interrupt Registers)
Vector Number
Vector Address or Offset
Description
35
36
51
52
0x0000.00CC
Timer 3A
Timer 3B
I2C1
0x0000.00D0
0x0000.00D4
–
37
53
38–41
42
54–57
58
Reserved
0x0000.00E8
0x0000.00F0
–
Ethernet Controller
USB
44
60
45
61
Reserved
µDMA Software
µDMA Error
Reserved
EPI
46
62
0x0000.00F8
0x0000.00FC
–
47
63
48–52
53
64–68
69
0x0000.0114
0x0000.0118
–
54
70
GPIO Port J
Reserved
SSI 2
55–56
57
71–72
73
0x0000.0124
0x0000.0128
0x0000.012C
0x0000.0130
–
58
74
SSI 3
59
75
UART3
60
76
UART4
61–63
64
77–79
80
Reserved
CAN1 INT0
CAN1 INT1
CAN1 INT0
CAN1 INT1
Reserved
ADCINT1
ADCINT2
ADCINT3
ADCINT4
ADCINT5
ADCINT6
ADCINT7
ADCINT8
CTOMIPC1
CTOMIPC2
CTOMIPC3
CTOMIPC4
Reserved
RAM Single Error
0x0000.0140
0x0000.0144
0x0000.0148
0x0000.014C
–
65
81
66
82
67
83
68–71
72
84–87
88
0x0000.0160
0x0000.0164
0x0000.0168
0x0000.016C
0x0000.0170
0x0000.0174
0x0000.0178
0x0000.017C
0x0000.0180
0x0000.0184
0x0000.0188
0x0000.018C
–
73
89
74
90
75
91
76
92
77
93
78
94
79
95
80
96
81
97
82
98
83
99
84–87
88
100–103
104
105
106
107–149
0x0000.01A0
0x0000.01A4
0x0000.01A8
–
89
System / USB PLL Out of Lock
M3 Flash Single Error
Reserved
90
91–133
26
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
Table 2-15. Exceptions from Cortex™-M3 Core to NVIC
Vector Address or
Offset(2)
Exception Type
Priority(1)
Vector Number
Activation
Stack top is loaded from
the first entry of the vector
table on reset.
–
–
0
1
0x0000.0000
0x0000.0004
Reset
–3 (highest)
Asynchronous
Asynchronous
On Concerto devices
activated by clock fail
condition, C28 PIE error,
external M3GPIO NMI
input signal, and C28 NMI
WD timeout reset.
Non-Maskable Interrupt
(NMI)
–2
2
0x0000.0008
Hard Fault
–1
3
4
0x0000.000C
0x0000.0010
–
Memory Management
programmable(3)
Synchronous
Synchronous when
precise and asynchronous
when imprecise.
On Concerto devices
activated by memory
access errors and RAM
and flash uncorrectable
data errors.
Bus Fault
programmable(3)
5
0x0000.0014
Usage Fault
–
programmable(3)
–
6
0x0000.0018
–
Synchronous
Reserved
7–10
SVCall
programmable(3)
programmable(3)
–
11
0x0000.002C
0x0000.0030
–
Synchronous
Synchronous
Reserved
Debug Monitor
–
12
13
PendSV
SysTick
Interrupts
programmable(3)
programmable(3)
14
15
0x0000.0038
0x0000.003C
Asynchronous
Asynchronous
(4)
programmable
16 and above
0x0000.0040 and above Asynchronous
(1) 0 is the default priority for all the programmable priorities
(2) See the "Vector Table" subsection of the "Exception Model" section in the Cortex-M3 Processor chapter of the Concerto F28M35x
Technical Reference Manual (literature number SPRUH22).
(3) See SYSPRI1 in the Cortex-M3 Peripherals chapter of the Concerto F28M35x Technical Reference Manual (literature number
SPRUH22).
(4) See PRIn registers in the Cortex-M3 Peripherals chapter of the Concerto F28M35x Technical Reference Manual (literature number
SPRUH22).
2.3.5 Cortex™-M3 Vector Table
Each peripheral interrupt of Table 2-14 is assigned an address offset containing the location of the
peripheral interrupt handler (relative to the vector table base) for that particular interrupt (vector numbers
16–107).
Similarly, each exception interrupt of Table 2-15 (including Reset) is also assigned an address offset
containing the location of the exception interrupt handler (relative to the vector table base) for that
particular interrupt (vector numbers 1–15).
In addition to interrupt vectors, the vector table also contains the initial stack pointer value at table
location 0.
Following system reset, the vector table base is fixed at address 0x0000.0000. Privileged software can
write to the Vector Table Offset (VTABLE) register to relocate the vector table start address to a different
memory location, in the range 0x0000 0200 to 0x3FFF FE00. Note that when configuring the VTABLE
register, the offset must be aligned on a 512-byte boundary.
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
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2.3.6 Cortex™-M3 Local Peripherals
The Cortex™-M3 local peripherals include two Watchdogs, an NMI Watchdog, four General-Purpose
Timers, four SSI peripherals, two CAN peripherals, five UARTs, two I2C peripherals, Ethernet, USB +
PHY, EPI, and µCRC (Cyclic Redundancy Check). The USB and EPI are accessible through the AHB Bus
(Advanced High-Performance Bus). The EPI peripheral is also accessible from the Control Subsystem.
The remaining peripherals are accessible through the APB Bus (Advanced Peripheral Bus). The APB and
AHB bus cycles originate from the CPU System Bus or the µDMA Bus via a bus bridge.
While the Cortex™-M3 CPU has access to all the peripherals, the µDMA has access to most, with the
exception of the µCRC, Watchdogs, NMI Watchdog, CAN peripherals, and the I2C peripheral. The
Cortex™-M3 peripherals connect to the Concerto™ device pins via GPIO_MUX1. Most of the peripherals
also generate event signals for the µDMA and the NVIC. The Watchdogs receive M3SWRST from the
NVIC (triggered by software) and send M3WDRST[1:0] reset requests to the Reset block. The NMI
Watchdog receives the M3NMI event from the NMI block and sends the M3NMIRST request to the Resets
block.
See Section 6.2 for more information on the Cortex™-M3 peripherals.
2.3.7 Cortex™-M3 Local Memory
The Local Memory includes Boot ROM; Secure Flash with Error Correction Code (ECC); Secure C0/C1
RAM with ECC; and C2/C3 RAM with Parity Error Checking. The Boot ROM and Flash are both
accessible through the I-CODE and D-CODE Buses. Flash registers can also be accessed by the
Cortex™-M3 CPU through the APB Bus. All Local Memory is accessible from the Cortex™-M3 CPU; the
C2/C3 RAM is also accessible by the µDMA.
Two types of error correction events can be generated during access of the Local Memory: uncorrectable
errors and single errors. The uncorrectable errors (including one from the Shared Memories) generate a
Bus Fault Exception to the Cortex™-M3 CPU. The less critical single errors go to the NVIC where they
can result in maskable interrupts to the Cortex™-M3 CPU.
2.3.8 Cortex™-M3 Accessing Shared Resources and Analog Peripherals
There are several memories, digital peripherals, and analog peripherals that can be accessed by both the
Master and Control Subsystems. They are grouped into Shared Resources and the Analog Subsystem.
The Shared Resources include the External Peripheral Interface (EPI), Inter-Processor Communications
(IPC) registers, MTOC Message RAM, CTOM Message RAM, and eight individually configurable Shared
RAM blocks. The RAMs of the Shared Resources block have Parity Error Checking.
The Message RAMs and the Shared RAMs can be accessed by the Cortex™-M3 CPU and µDMA. The
MTOC Message RAM is intended for sending data from the Master Subsystem to the Control Subsystem,
having r/w access for the Cortex™-M3/µDMA and read-only access for the C28x/DMA. The CTOM
Message RAM is intended for sending data from the Control Subsystem to the Master Subsystem, having
r/w access for the C28x/DMA and read-only access for the Cortex™-M3/µDMA.
The IPC registers provide up to 32 handshaking channels to coordinate the transfer of data through the
Message RAMs by polling. Four of these channels are also backed up by four interrupts to PIE on the
Control Subsystem side, and four interrupts to the NVIC on the Master Subsystem side (to reduce delays
associated with polling).
The eight Shared RAM blocks are similar to the Message RAMs, in that the data flow is only one way;
however, the direction of the data flow can be individually set for each block to be from Master to Control
Subsystem or from Control to Master Subsystem.
28
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
The Analog Subsystem has ADC1, ADC2, and Analog Comparator peripherals that can be accessed
through the Analog Common Interface Bus. The ADC Result Registers are accessible by CPUs and
DMAs of the Master and Control Subsystems. All other Analog Peripheral Registers are accessible by the
C28x CPU only. The Cortex™-M3 CPU accesses the ACIB through the System Bus, and the µDMA
through the µDMA Bus. The ACIB arbitrates for access to the ADC and Analog Comparator registers
between CPU/DMA bus cycles of the Master Subsystem with those of the Control Subsystem. In addition
to managing bus cycles, the ACIB also transfers End-of-Conversion ADC interrupts to the Master
Subsystem (as well as to the Control Subsystem). The eight EOC sources from ADC1 and the eight EOC
sources from ADC2 are AND-ed together by the ACIB, with the resulting eight ADC interrupts going to
destinations in both the Master Subsystem and the Control Subsystem.
See Section 6.1 for more information on shared resources and analog peripherals.
2.4 Control Subsystem
The Control Subsystem includes the C28x CPU/FPU/VCU, Peripheral Interrupt Expansion (PIE) block,
DMA, C28x Peripherals, and Local Memory. Additionally, the C28x CPU and DMA have access to Shared
Resources: IPC (CPU only), Message RAM, and Shared RAM; and to Analog Peripherals via the Analog
Common Interface Bus.
Figure 2-2 shows the Control Subsystem.
2.4.1 C28x CPU/FPU/VCU
The F28M35x Concerto™ MCU family is a member of the TMS320C2000™ MCU platform. The
Concerto™ C28x CPU/FPU has the same 32-bit fixed-point architecture as TI's existing Piccolo™ MCUs,
combined with a single-precision (32-bit) IEEE 754 floating-point unit (FPU) of TI’s existing Delfino™
MCUs. Each F28M35x device is a very efficient C/C++ engine, enabling users to develop their system
control software in a high-level language. Each F28M35x device also enables math algorithms to be
developed using C/C++. The device is equally efficient at DSP math tasks and at system control tasks.
The 32 x 32-bit MAC 64-bit processing capabilities enable the controller to handle higher numerical
resolution problems efficiently. With the addition of the fast interrupt response with automatic context save
of critical registers, the device is capable of servicing many asynchronous events with minimal latency.
The device has an 8-level-deep protected pipeline with pipelined memory accesses. This pipelining
enables the device to execute at high speeds without resorting to expensive high-speed memories.
Special branch-look-ahead hardware minimizes the latency for conditional discontinuities. Special
conditional store operations further improve performance. The VCU extends the capabilities of the C28x
CPU and C28x+FPU processors by adding additional instructions to accelerate Viterbi, Complex
Arithmetic, 16-bit FFTs, and CRC algorithms. No changes have been made to existing instructions,
pipeline, or memory bus architecture. Therefore, programs written for the C28x are completely compatible
with the C28x+VCU.
There are two events generated by the FPU block that go to the C28x Peripheral Interrupt Expansion
(PIE): LVF and LUV. Inside PIE, these and other events from C28x peripherals and memories result in 12
PIE interrupts PIEINTS[12:1] into the C28x CPU. The C28x CPU also receives three additional interrupts
directly (instead of through PIE) from Timer 1 (TINT1), from Timer 2 (TINT2), and from the NMI block
(C28uNMIINT).
The C28x has two low-power modes: Idle and Standby.
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
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RAMUNCERR
RAMUNCERR
GPIO_MUX1
EPI
MASTER SUBSYSTEM
C28x NMI
GPI (63:0) MINUS
GPI 39 AND GPI 44
(NOT PINNED OUT)
ECCDBLERR
FLASHUNCERR
SHARED RESOURCES
C28x LOCAL MEMORY
M0/M1
L2/L3
FREQ
S0-S7
MTOC
MSG
CTOM
MSG
SECURE
L0/L1
RAM
LPM WAKEUP
LPMWAKE
GASKET
SHARED
RAM
SECURE
BOOT
IPC
RAM
RAM
RAM
FLASH
(ECC)
RAM
ROM
REGS
(ECC)
BUS
(parity)
(parity)
(parity)
(ECC)
(parity)
BRIDGE
MTOCIPC (4:1)
LVF
LUF
RAMACCVIOL
FLSINGERR
FLFSM
RAMSINGERR
C28x
FPU
ANALOG
SUBSYSTEM
PIE (PERIPHERAL INTERRUPT EXPANSION)
PIEINTRS (12:1)
DINTCH (6:1)
ADCINT (8:1)
ADCINT (4:1)
MXINTA, MRINTA
TINT 0,1,2
I2CINT1A, I2CINT2A
SCIRXINTA, SCITXINTA
SPIRXINTA, SPITXINTA
EQEP(3:1)INT
C28x
CPU
C28x
TINT 0,1,2
XINT 2
DMA
XINT 1,2,3
EPWM(9:1)INT
EPWM(9:1)TZINT
ECAP(6:1)INT
SOCA (9:1), SOCB(9:1)
SOCA (9:1), SOCB(9:1)
C28 DMA BUS
C28 CPU BUS
TINT1
TINT2
C28x
VCU
C28x PERIPHERALS
PERIPHERAL
I/O s
EQEP
ERR
C28NMI
C28NMIINT
ECCDBLERR
EMUSTOP
PIENMIERR
GPTRIP
(12:1)
GPTRIP
(12:7)
GPTRIP
(6:4)
CLOCKFAIL
C28NMIRST
SOCAO
SOCBO
SYNCO
GPIO_MUX1
GPIO_MUX1
M3 CLOCKS
RESETS
M3 NMI
C28x NMI
Figure 2-2. Control Subsystem
30
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
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2.4.2 C28x™ Core Hardware Logic Built-In Test (LBIST)
The Concerto™ microcontroller C28x CPU core includes a Logic Built-In Self Test (LBIST) controller for
testing the CPU core logic for errors. Tests are initiated by software whenever convenient (at start-up, idle,
and so on), which allows for periodic logic tests to ensure that the CPU core logic is working correctly.
During a test cycle, all interrupts are logged by the LBIST controller and re-issued after the test cycle
completes to ensure that no interrupts are missed. In the event of a logic error, the LBIST controller
generates an NMI on both cores to signal that an error has been detected. This action allows for the
software to gracefully handle any detected logic errors.
2.4.3 C28x Peripheral Interrupt Expansion (PIE)
The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The
PIE block can support up to 96 peripheral interrupts. On the F28M35x, 66 of the possible 96 interrupts are
used. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 CPU interrupt lines
(INT1 to INT12). Each of 12 interrupt lines supports up to 8 simultaneously active interrupts. Each of the
96 interrupts has its own vector stored in a dedicated RAM block that can be overwritten by the user. The
vector is automatically fetched by the CPU on servicing the interrupt. Eight CPU clock cycles are needed
to fetch the vector and save critical CPU registers. Hence, the CPU can quickly respond to interrupt
events. Prioritization of interrupts is controlled in hardware and software. Each individual interrupt can be
enabled or disabled within the PIE block. See Table 2-16 for PIE interrupt assignments.
Table 2-16. PIE Peripheral Interrupts(1)
PIE INTERRUPTS
CPU INTERRUPTS
INTx.8
INTx.7
INTx.6
INTx.5
INTx.4
INTx.3
INTx.2
INTx.1
C28.LPMWAKE
(C28LPM)
TINT0
(TIMER 0)
0x0D4C
Reserved
–
0x0D4A
XINT2
–
0x0D48
XINT1
–
0x0D46
Reserved
–
0x0D44
ADCINT2
(ADC)
0x0D42
ADCINT1
(ADC)
0x0D40
INT1
INT2
INT3
INT4
INT5
INT6
INT7
INT8
INT9
INT10
INT11
INT12
0x0D4E
EPWM8_TZINT
(ePWM8)
EPWM7_TZINT
(ePWM7)
EPWM6_TZINT
(ePWM6)
EPWM5_TZINT
(ePWM5)
EPWM4_TZINT
(ePWM4)
EPWM3_TZINT
(ePWM3)
EPWM2_TZINT
(ePWM2)
EPWM1_TZINT
(ePWM1)
0x0D5E
0x0D5C
0x0D5A
0x0D58
0x0D56
0x0D54
0x0D52
0x0D50
EPWM8_INT
(ePWM8)
0x0D6E
EPWM7_INT
(ePWM7)
0x0D6C
EPWM6_INT
(ePWM6)
0x0D6A
EPWM5_INT
(ePWM5)
0x0D68
EPWM4_INT
(ePWM4)
0x0D66
EPWM3_INT
(ePWM3)
0x0D64
EPWM2_INT
(ePWM2)
0x0D62
EPWM1_INT
(ePWM1)
0x0D60
EPWM9_TZINT
(ePWM9)
Reserved
–
0x0D7C
ECAP6_INT
(eCAP6)
0x0D7A
ECAP5_INT
(eCAP5)
0x0D78
ECAP4_INT
(eCAP4)
0x0D76
ECAP3_INT
(eCAP3)
0x0D74
ECAP2_INT
(eCAP2)
0x0D72
ECAP1_INT
(eCAP1)
0x0D70
0x0D7E
EPWM9_INT
(ePWM9)
0x0D8E
Reserved
–
0x0D8C
Reserved
–
0x0D8A
Reserved
–
0x0D88
Reserved
–
0x0D86
EQEP3_INT
(eQEP3)
0x0D84
EQEP2_INT
(eQEP2)
0x0D82
EQEP1_INT
(eQEP1)
0x0D80
Reserved
–
0x0D9E
Reserved
–
0x0D9C
MXINTA
(McBSPA)
0x0D9A
MRINTA
(McBSPA)
0x0D98
Reserved
–
0x0D96
Reserved
–
0x0D94
SPITXINTA
(SPIA)
0x0D92
SPIRXINTA
(SPIA)
0x0D90
Reserved
–
0x0DAE
Reserved
–
0x0DAC
DINTCH6
(C28 DMA)
0x0DAA
DINTCH5
(C28 DMA)
0x0DA8
DINTCH4
(C28 DMA)
0x0DA6
DINTCH3
(C28 DMA)
0x0DA4
DINTCH2
(C28 DMA)
0x0DA2
DINTCH1
(C28 DMA)
0x0DA0
Reserved
–
0x0DBE
Reserved
–
0x0DBC
Reserved
–
0x0DBA
Reserved
–
0x0DB8
Reserved
–
0x0DB6
Reserved
–
0x0DB4
I2CINT2A
(I2CA)
0x0DB2
I2CINT1A
(I2CA)
0x0DB0
Reserved
–
0x0DCE
Reserved
–
0x0DCC
Reserved
–
0x0DCA
Reserved
–
0x0DC8
Reserved
–
0x0DC6
Reserved
–
0x0DC4
SCITXINTA
(SCIA)
0x0DC2
SCIRXINTA
(SCIA)
0x0DC0
ADCINT8
(ADC)
0x0DDE
ADCINT7
(ADC)
0x0DDC
ADCINT6
(ADC)
0x0DDA
ADCINT5
(ADC)
0x0DD8
ADCINT4
(ADC)
0x0DD6
ADCINT3
(ADC)
0x0DD4
ADCINT2
(ADC)
0x0DD2
ADCINT1
(ADC)
0x0DD0
Reserved
–
0x0DEE
Reserved
–
0x0DEC
Reserved
–
0x0DEA
Reserved
–
0x0DE8
MTOCIPCINT4
(IPC)
0x0DE6
MTOCIPCINT3
(IPC)
0x0DE4
MTOCIPCINT2
(IPC)
0x0DE2
MTOCIPCINT1
(IPC)
0x0DE0
LUF
(C28FPU)
0x0DFE
LVF
(C28FPU)
0x0DFC
EPI_INT
(EPI)
0x0DFA
C28RAMACCVIOL C28RAMSINGERR
Reserved
–
0x0DF4
C28FLSINGERR
(Memory)
XINT3
(Ext. Int. 3)
0x0DF0
(Memory)
0x0DF8
(Memory)
0x0DF6
0x0DF2
(1) Out of the 96 possible interrupts, 66 interrupts are currently used. The remaining interrupts are reserved for future devices. These
interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is
being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while
modifying the PIEIFR. To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:
1) No peripheral within the group is asserting interrupts.
2) No peripheral interrupts are assigned to the group (example PIE group 11).
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
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2.4.4 C28x DMA
The C28x direct memory access (DMA) module provides a hardware method of transferring data between
peripherals, between memory, and between peripherals and memory without intervention from the CPU,
thereby freeing up bandwidth for other system functions. Additionally, the DMA has the capability to
orthogonally rearrange the data as the data is transferred as well as “ping-pong” data between buffers.
These features are useful for structuring data into blocks for optimal CPU processing. The interrupt trigger
source for each of the six DMA channels can be configured separately and each channel contains its own
independent PIE interrupt to notify the CPU when a DMA transfer has either started or completed. Five of
the six channels are exactly the same, while Channel 1 has one additional feature: the ability to be
configured at a higher priority than the others.
2.4.5 C28x Local Peripherals
The C28x local peripherals include an NMI Watchdog, three Timers, four Serial Port Peripherals (SCI,
SPI, McBSP, I2C), an External Peripheral Interface (EPI), and three types of Control Peripherals (ePWM,
eQEP, eCAP). All peripherals are accessible by the C28x CPU via the C28x Memory Bus. Additionally,
the McBSP and ePWM are accessible by the C28x DMA Bus. The EPI peripheral is also accessible from
the Master Subsystem. The Serial Port Peripherals and the Control Peripherals connect to Concerto’s pins
via the GPIO_MUX1 block. Internally, the C28x peripherals generate events to the PIE block, C28x DMA,
and the Analog Subsystem. The C28x NMI Watchdog receives a C28NMI event from the NMI block and
sends a counter timeout event to the Cortex™-M3 NMI block and the Resets block to flag a potentially
critical condition.
The ePWM peripheral receives events that can be used to trip the ePWM outputs EPWMxA and
EPWMxB. These events include ECCDBLERR event from the C28x Local Memory, PIENMIERR and
EMUSTOP events from the C28x CPU, and up to 12 trips from GPIO_MUX1.
See Section 6.3 for more information on C28x peripherals.
2.4.6 C28x Local Memory
The C28x Local Memory includes Boot ROM; Secure Flash with Error Correction Code (ECC); Secure
L0/L1 RAM with ECC; L2/L3 RAM with Parity Error Checking; and M0/M1 with ECC. All local memories
are accessible from the C28x CPU; the L2/L3 RAM is also accessible by the C28x DMA. Two types of
error correction events can be generated during access of the C28x Local Memory: uncorrectable errors
and single errors. The uncorrectable errors propagate to the NMI block where they can become the
C28NMI to the C28x NMI Watchdog and the C28NMIINT non-maskable interrupt to the C28x CPU. The
less critical single errors go to the PIE block where they can become maskable interrupts to the C28x
CPU.
2.4.7 C28x Accessing Shared Resources and Analog Peripherals
There are several memories, digital peripherals, and analog peripherals that can be accessed by both the
Master and Control Subsystems. They are grouped into the Shared Resources and the Analog
Subsystem.
The Shared Resources include the External Peripheral Interface (EPI), Inter-Processor Communications
(IPC) registers, MTOC Message RAM, CTOM Message RAM, and eight individually configurable Shared
RAM blocks.
The Message RAMs and the Shared RAMs can be accessed by the C28x CPU and DMA and have Parity-
Error Checking. The MTOC Message RAM is intended for sending data from the Master Subsystem to the
Control Subsystem, having r/w access for the Cortex™-M3/µDMA and read-only access for the
C28x/DMA. The CTOM Message RAM is intended for sending data from the Control Subsystem to the
Master Subsystem, having r/w access for the C28x/DMA and read-only access for the Cortex™-
M3/µDMA.
32
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
The IPC registers provide up to 32 handshaking channels to coordinate transfer of data through the
Message RAMs by polling. Four of these channels are also backed up by four interrupts to PIE on the
Control Subsystem side, and four interrupts to the NVIC on the Master Subsystem side (to reduce delays
associated with polling).
The eight Shared RAM blocks are similar to the Message RAMs, in that the data flow is only one way;
however, the direction of the data flow can be individually set for each block to be from Master to Control
Subsystem or from Control to Master Subsystem.
See Section 6.1 for more information on shared resources and analog peripherals.
2.5 Analog Subsystem
The Analog Subsystem has ADC1, ADC2, and six Analog Comparator + DAC units that can be accessed
via the Analog Common Interface Bus. The ADC Result Registers are accessible by CPUs and DMAs of
the Master and Control Subsystems. All other Analog Peripheral Registers are accessible by the C28x
CPU only. The C28x CPU accesses the ACIB through the C28x Memory Bus, and the C28x DMA through
the C28x DMA Bus. The ACIB arbitrates for access to ADC and Analog Comparator registers between
CPU/DMA bus cycles of the C28x Subsystem with those of the Cortex™-M3 Subsystem. In addition to
managing bus cycles, the ACIB also transfers Start-Of-Conversion triggers to the Analog Subsystem and
returns End-Of-Conversion ADC interrupts to both the Master Subsystem and the Control Subsystem.
There are 22 possible SOC (Start-Of-Conversion) sources from the C28x Subsystem that are mapped to a
total of 8 possible SOC triggers inside the Analog Subsystem (to ADC1 and ADC2).
Going the other way, eight EOC (End-Of-Conversion) sources from ADC1 and eight EOC sources from
ADC2 are AND-ed together to form eight interrupts going to destinations in both the Master and Control
Subsystems. Inside the C28x Subsystem, all eight EOC interrupts go to the PIE, but only four of the same
eight go to the C28x DMA.
The Concerto™ MCU Analog Subsystem has two independent Analog-to-Digital Converters (ADC1,
ADC2); six Analog Comparators + DAC units; and an Analog Common Interface Bus (ACIB) to facilitate
analog data communications with Concerto’s two digital subsystems (Cortex™-M3 and C28x).
Figure 2-3 shows the Analog Subsystem.
2.5.1 ADC1
The ADC1 consists of a 12-bit Analog-to-Digital converter with up to 16 analog input channels of which
10 are currently pinned out. The analog channels are internally pre-assigned to two Sample-and-Hold
(S/H) units A and B, both feeding an Analog Mux whose output is converted to a 12-bit digital value and
stored in ADC1 result registers. The two S/H units enable simultaneous sampling of two analog signals at
a time. Additional channels or channel pairs are converted sequentially. Start-of-Conversion (SOC)
triggers from the Control Subsystem initiate analog-to-digital conversions. End-of-Conversion (EOC)
interrupts from ADCs notify the Master and Control Subsystems that the conversion results are ready to
be read from ADC1 result registers. See Section 6.1.1 for more information on ADC peripherals.
2.5.2 ADC2
The ADC2 consists of a 12-bit Analog-to-Digital converter with up to 16 analog input channels of which
10 are currently pinned out. The analog channels are internally preassigned to two Sample-and-Hold (S/H)
units A and B, both feeding an Analog Mux whose output is converted to a 12-bit digital value and stored
in the ADC2 result registers. The two S/H units enable simultaneous sampling of two analog signals at a
time. Additional channels or channel pairs are converted sequentially. Start-of-Conversion (SOC) triggers
from the Control Subsystem initiate analog-to-digital conversions. End-of-Conversion (EOC) interrupts
from ADCs notify the Master and Control Subsystems that the conversion results are ready to be read
from ADC2 result registers. See Section 6.1.1 for more information on ADC peripherals.
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
10
AIO_MUX1
GPIO
MUX
4
ANALOG
COMMON
INTERFACE
BUS
ADC1INA0
ADC1INA2
ADC1INA3
ADC1INA4
ADC1INA6
ADC1INA7
ADC1INB0
ADC1INB3
ADC1INB4
ADC1INB7
ANALOG BUS
M3
M3
MCIBSTATUS REG
CPU
uDMA
TRIGS (8:1)
ADC
1
M3
SYSTEM
BUS
M3
uDMA
BUS
COMPA1
COMPA2
COMPA3
COMPB2
EOC
INTER-
RUPTS
(8:1)
ADC1INT (8:1)
ADC2INT (8:1)
VDDA
ADCINT(8:1)
(3.3V)
6
COMPARATOR
+ DAC UNITS
8
COMPOUT (6:1)
VSSA
(0V)
C28
CPU
BUS
C28
DMA
BUS
8
COMPA4
COMPB5
COMPA5
COMPA6
C28x
CPU
C28x
DMA
CCIBSTATUS REG
ADCINT
(4:1)
TRIGS (8:1)
ADC
2
SOC
TRIG-
GERS
(8:1)
TINT (2:0)
XINT2
ADC2INA0
ADC2INB0
ADC2INB3
ADC2INB4
ADC2INB7
ADC2INA2
ADC2INA3
ADC2INA4
ADC2INA6
ADC2INA7
SOC (9:1) A
SOC (9:1) B
TRIG8SEL REG
TRIG7SEL REG
. . .
GPIO
MUX
TRIG2SEL REG
TRIG1SEL REG
TIMER
(3)
XINT2
EPWM
(9)
4
AIO_MUX2
10
Figure 2-3. Analog Subsystem
34
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
2.5.3 Analog Comparator + DAC
There are six Comparator blocks enabling simultaneous comparison of multiple pairs of analog inputs,
resulting in six digital comparison outputs. The external analog inputs that are being compared in the
comparators come from AIO_MUX1 and AIO_MUX2 blocks. These analog inputs can be compared
against each other or the outputs of 10-bit DACs (Digital-to-Analog Converters) inside individual
Comparator modules. The six comparator outputs go to the GPIO_MUX2 block where they can be
mapped to six out of eight available pins.
Note that in order to use these comparator outputs to trip the C28x EPWMA/B outputs, they must be first
routed externally from pins of the GPIO_MUX2 block to selected pins of the GPIO_MUX1 block before
they can be assigned to selected 12 ePWM Trip Inputs.
See Section 6.1.2 for more information on the analog comparator + DAC.
2.5.4 Analog Common Interface Bus (ACIB)
The ACIB links the Master and Control Subsystems with the Analog Subsystem. The ACIB enables the
Cortex™-M3 CPU/µDMA and C28x CPU/DMA to access Analog Subsystem registers, to send SOC
Triggers to the Analog Subsystem, and to receive EOC Interrupts from the Analog Subsystem. The
Cortex™-M3 uses its System Bus and the µDMA Bus to read from ADC Result registers. The C28x uses
its Memory Bus and the DMA bus to access ADC Result registers and other registers of the Analog
Subsystem. The ACIB arbitrates between up to four possibly simultaneously occurring bus cycles on the
Master/Control Subsystem side of ACIB to access the ADC and Analog Comparator registers on the
Analog Subsystem side.
Additionally, ACIB maps up to 22 SOC trigger sources from the Control Subsystem to 8 SOC trigger
destinations inside the Analog Subsystem (shared between ADC1 and ADC2), and up to 16 ADC EOC
interrupt sources from the Analog Subsystem to 8 destinations inside the Master and Control Subsystems.
The eight ADC interrupts are the result of AND-ing of eight EOC interrupts from ADC1 with 8 EOC
interrupts from ADC2. The total of 16 possible ADC1 and ADC2 interrupts are sharing the 8 interrupt lines
because it is unlikely that any application would need all 16 interrupts at the same time.
Eight registers (TRIG1SEL–TRIG8SEL) configure eight corresponding SOC triggers to assign 1 of 22
possible trigger sources to each SOC trigger.
There are two registers that provide status of ACIB to the Master Subsystem and to the Control
Subsystem.
The Cortex™-M3 can read the MCIBSTATUS register to verify that the Analog Subsystem is properly
powered up; the Analog System Clock (ASYSCLK) is present; and that the bus cycles, triggers, and
interrupts are correctly propagating between the Master, Control, and Analog subsystems.
The C28x can read the CCIBSTATUS register to verify that the Analog Subsystem is properly powered
up; the Analog System Clock (ASYSCLK) is present; and that the bus cycles, triggers, and interrupts are
correctly propagating between the Master, Control, and Analog subsystems.
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Device Overview
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
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2.6 Master Subsystem NMIs
The Cortex™-M3 NMI Block generates an M3NMIINT non-maskable interrupt to the Cortex™-M3 CPU
and an M3NMI event to the NMI Watchdog in response to potentially critical conditions existing inside or
outside the Concerto™ MCU. When able to respond to the M3NMIINT interrupt, the Cortex™-M3 CPU
may address the NMI condition and disable the NMI Watchdog. Otherwise, the NMI Watchdog counts out
and an M3NMIRST reset signal is sent to the Resets block.
The inputs to the Cortex™-M3 NMI block include the C28NMIRST, PIENMIERR, CLOCKFAIL, ACIBERR,
VREGWARN, EXTGPIO, MLBISTERR, and CLBISTERR signals. The C28NMIRST comes from the C28x
NMI Watchdog; C28NMIRST indicates that the C28x was not able to prevent the C28x NMI Watchdog
counter from counting out. PIENMIERR indicates that an error condition was generated during the NMI
vector fetch from the C28x Peripheral Interrupt Expansion (PIE) block. The CLOCKFAIL input comes from
the Master Clocks Block, announcing a missing clock source to the Main Oscillator. ACIBERR indicates
an abnormal condition inside the Analog Common Interface Bus. The VREGWARN input communicates a
power anomaly. EXTGPIO comes from the GPIO_MUX1 to announce an external emergency.
MLBISTERR is generated by the Cortex™-M3 core to signal that a BIST time-out or signature mismatch
error has been detected. CLBISTERR is generated by the C28x core to signal that a BIST time-out or
signature mismatch error has been detected.
The Cortex™-M3 NMI block can be accessed via the Cortex™-M3 NMI configuration registers—including
the MNMIFLG, MNMIFLGCLR, and MNMIFLGFRC registers—to examine flag bits for the NMI sources,
clear the flags, and force the flags to active state, respectively.
Figure 2-4 shows the Cortex™-M3 NMI and C28x NMI.
2.7 Control Subsystem NMIs
The C28x NMI Block generates a C28NMIINT non-maskable interrupt to the C28x CPU and a C28NMI
event to the C28x NMI Watchdog in response to potentially critical conditions existing inside the
Concerto™ MCU. When able to respond to the C28NMIINT interrupt, the C28x CPU may address the NMI
condition and disable the C28x NMI Watchdog. Otherwise, the C28x NMI Watchdog counts out and the
C28NMIRST reset signal is sent to the Resets block and the Cortex™-M3 NMI Block, where the Cortex™-
M3 NMI Block can generate an NMI to the Cortex™-M3 processor.
The inputs to the C28x NMI block include the CLOCKFAIL, ACIBERR, RAMUNCERR, FLASHUNCERR,
PIENMIERR, CLBISTERR, and MLBISTERR signals. The CLOCKFAIL input comes from the Clocks
Block, announcing a missing clock source to the Main Oscillator. ACIBERR indicates an abnormal
condition inside the Analog Common Interface Bus. The RAMUCERR and FLASHUNCERR announce the
occurrence of uncorrectable error conditions during access to the Flash or RAM (local or shared).
PIENMIERR indicates that an error condition was generated during NMI vector fetch from the C28x
Peripheral Interrupt Expansion (PIE) block. MLBISTERR is generated by the Cortex™-M3 core to signal
that a BIST time-out or signature mismatch error has been detected. CLBISTERR is generated by the
C28x core to signal that a BIST time-out or signature mismatch error has been detected.
The C28x NMI block can be accessed via the C28x NMI configuration registers—including the CNMIFLG,
CNMIFLGCLR, and CNMIFLGFRC registers—to examine flag bits for the NMI sources, clear the flags,
and force the flags to active state, respectively.
Figure 2-4 shows the Cortex™-M3 NMI and C28x NMI.
36
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
M3
1.2V
M3 NMI
WDOG
M3 WDOG
(2)
BIST
VREG
M3BISTERR
VREGWARN
M3NMI
M3NMIRST
M3WDRST (1:0)
NMI
M3BISTERR
M3EXTNMI
C28BISTERR
M3NMI
M3NMIINT
C28NMIRST
GPIO_MUX
M3 NMI
M3 CPU
ACIBERR
CLOCKFAIL
M3BISTERR
ANALOG
M3WDRST (1:0)
M3NMIRST
SUBSYSTEM
RESETS
C28NMIRST
CLOCKS
PIENMIERR
C28NMIINT
C28NMI
C28x CPU
RAMUNCERR
C28BISTERR
C28x NMI
SHARED RAM
C28x LOCAL
RAM
C28BISTERR
FLASHUNCERR
C28NMI
C28NMIRST
C28x NMI
WDOG
C28x
BIST
C28x
FLASH
Figure 2-4. Cortex™-M3 NMI and C28x NMI
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
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2.8 Resets
The Concerto™ MCU has two external reset pins: XRS for the Master and Control Subsystems, and ARS
for the Analog Subsystem. TI recommends that these two pins be externally tied together with a board
signal trace.
The XRS pin can receive an external reset signal from outside into the chip, and the pin can drive a reset
signal out from inside of the chip. A reset pulse driven into the XRS pin resets the Master and Control
Subsystems. A reset pulse can also be driven out of the XRS pin by the voltage monitoring block of the
Master and Control Subsystems (see Section 2.9). A reset pulse can be driven out of the XRS pin when
the two Cortex™-M3 Watchdogs or the Cortex™-M3 NMI Watchdog time out.
There are some requirements on the XRS pin:
1. During power up, the XRS pin must be held low for at least eight X1 cycles after the input clock is
stable. This requirement is to enable the entire device to start from a known condition.
2. During power down, the XRS pin must be pulled low at least 8 µs prior to VDDIO reaching 1.5 V. This
requirement is to enhance Flash reliability.
3. TI recommends that no voltage larger than 0.7 V be applied to any pin prior to powering up the device.
Voltages applied to pins on an unpowered device can lead to unpredictable results.
The ARS pin can receive an external reset signal from outside into the chip, and the pin can drive a reset
signal out from inside of the chip. A reset pulse driven into the ARS pin resets the Analog Subsystem. A
reset pulse can be driven out of the ARS pin by the voltage monitoring block of the Analog Subsystem.
Figure 2-5 shows the resets.
2.8.1 Cortex™-M3 Resets
The Cortex™-M3 CPU and NVIC (Nested Vectored Interrupt Controller) are both reset by the POR
(Power-On Reset) or the M3SYSRST reset signal. In both cases, the Cortex™-M3 CPU restarts program
execution from the address provided by the reset entry in the vector table. A register can later be
referenced to determine the source of the reset. The M3SYSRST signal also propagates to the Cortex™-
M3 peripherals and the rest of the Cortex™-M3 Subsystem.
The M3SYSRST has four possible sources: XRS, M3WDOGS, M3SWRST, and M3DBGRST. The
M3WDOGS is set in response to time-out conditions of the two Cortex™-M3 Watchdogs or the Cortex™-
M3 NMI Watchdog. The M3SWRST is a software-generated reset output by the NVIC. The M3DBGRS is
a debugger-generated reset that is also output by the NVIC. In addition to driving M3SYSRST, these two
resets also propagate to the C28x Subsystem and the Analog Subsystem.
The M3RSNIN bit can be set inside the CRESCNF register to selectively reset the C28x Subsystem from
the Cortex™-M3, and ACIBRST bit of the same register selectively resets the Analog Common Interface
Bus. In addition to driving reset signals to other parts of the chip, the Cortex™-M3 can also detect a
C28SYSRST reset being set inside the C28x Subsystem by reading the CRES bit of the CRESSTS
register.
Cortex™-M3 software can also set bits in the SRCR register to selectively reset individual Cortex™-M3
peripherals, provided they are enabled inside the DC (Device Configuration) register. The Reset Cause
register (MRESC) can be read to find out if the latest reset was caused by External Reset,
VMON/POR/BOR, Watchdog Timer 0, Watchdog Timer 1, or Software Reset from NVIC.
38
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
www.ti.com
SPRS742D –JUNE 2011–REVISED AUGUST 2012
M3 WDOG (1)
M3 WDOG (0)
M3WDOGS
JTAG
CRESSTS REG
CRESCNF REG
CONTROLLER
M3 BIST
MLBISTRST
( SETS DEFAULT VALUES ) XRS
SOFTWARE
M3PORRST
POR
VOLTAGE
REGULATION
AND
M3
M3
M3
NMI
MONITORING
XRS
NVIC
CPU
WDOG
M3SYSRST
XRS
FLASH PUMP
M3SYSRST
M3SWRST
PERIPHERAL SOFTWARE RESETS
SRCR REG
M3DBGRST
M3
SUBSYSTEM
MRESC REG
DC REG
CONTAINS RESET CAUSES
GLOBAL PERIPHERAL ENABLES
ARS
PIN
ACIBRST
SRXRST
ANALOG
SUBSYSTEM
XRS
GPIO_MUX
SHARED
RESOURCES
M3WDOGS
POR
C28x BIST
CLBISTRST
C28x
SUBSYSTEM
‘0’
XRS
PIN
C28RSTIN
C28SYSRST
XRS
C28x
CPU
SYNC
DEGLITCH
M3SSCLK
C28x
NMI
XRS
WDOG
RESET INPUT SIGNAL STATUS
C28NMIWD
DEVICECNF REG
Figure 2-5. Resets
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
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2.8.2 C28x Resets
The C28x CPU is reset by the C28RSTIN signal, and the C28x CPU in turn resets the rest of the C28x
Subsystem with the C28SYSRST signal. When reset, the C28x restarts program execution from the
address provided at the top of the Boot ROM Vector Table.
The C28RSTIN has five possible sources: XRS, C28NMIWD, M3SWRST, M3DBGRST, and the
M3RSNIN. The C28NMIWD is set in response to time-out conditions of the C28x NMI Watchdog. The
M3SWRST is a software-generated reset output by the NVIC. The M3DBGRS is a debugger-generated
reset that is also output by the NVIC. These two resets must be first enabled by the Cortex™-M3
processor in order to propagate to the C28x Subsystem. M3RSNIN reset comes from the Cortex™-M3
Subsystem to selectively reset the C28x Subsystem from Cortex™-M3 software.
The C28x processor can learn the status of the internal ACIBRST reset signal and the external XRS pin
by reading the DEVICECNF register.
2.8.3 Analog Subsystem and Shared Resources Resets
Both the Analog Subsystem and the resources shared between the C28x and Cortex™-M3 subsystems
(IPC, MSG RAM, Shared RAM) are reset by the SRXRST reset signal. Additionally, the Analog
Subsystem is also reset by the internal ACIBRST signal from the Cortex™-M3 Subsystem and the
external ARS pin (which should be externally tied to the XRS pin).
The SRXRST has three possible sources: XRS, M3SWRST, and M3DBGRST. The M3SWRST is a
software-generated reset output by the NVIC. The M3DBGRS is a debugger-generated reset that is also
output by the NVIC. These two resets must be first enabled by the Cortex™-M3 processor in order to
propagate to the Analog Subsystem and the Shared Resources.
Although EPI is a shared peripheral, it is physically located inside the Cortex™-M3 Subsystem; therefore,
EPI is reset by M3SYSRST.
2.8.4 Device Boot Sequence
Concerto’s boot sequence is used to configure the Master Subsystem and the Control Subsystem for
execution of application code. The boot sequence involves both internal resources, and resources external
to the device. These resources include: Master Subsystem Bootloader code (M-Bootloader) factory-
programmed inside the Master Subsystem Boot ROM (M-Boot ROM); Control Subsystem Bootloader code
(C-Bootloader) factory-programmed inside the Control Subsystem Boot ROM (C-Boot ROM); four
GPIO_MUX pins for Master boot mode selection; internal Flash and RAM memories; and selected
Cortex™-M3 and C28x peripherals for loading the application code into the Master and Control
Subsystems.
The boot sequence starts when the Master Subsystem comes out of reset, which can be caused by
device power up, external reset, debugger reset, software reset, Cortex™-M3 watchdog reset, or
Cortex™-M3 NMI watchdog reset. While the M-Bootloader starts executing first, the C-Bootloader starts
soon after, and then both bootloaders work in tandem to configure the device, load application code for
both processors (if not already in the Flash), and branch the execution of each processor to a selected
location in the application code.
Execution of the M-Bootloader commences when an internal reset signal goes from active to inactive
state. At that time, the Control Subsystem and the Analog Subsystem continue to be in reset state until
the Master Subsystem takes them out of reset. The M-Bootloader first initializes some device-level
functions, then the M-Bootloader initializes the Master Subsystem. Next, the M-Bootloader takes the
Control Subsystem and the Analog Subsystem/ACIB out of reset. When the Control Subsystem comes out
of reset, its own C-Bootloader starts executing in parallel with the M-Bootloader. After initializing the
Control Subsystem, the C-Bootloader enters the C28x processor into the idle mode (to wait for the M-
Bootloader to wake up the C28x processor later via the MTOCIPC1 interrupt). Next, the M-Bootloader
reads four GPIO pins (see Table 2-17) to determine the boot mode for the rest of the M-Bootloader
operation.
40
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
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Table 2-17. Master Subsystem Boot Mode Selection
PF2_GPIO34
PF3_GPIO35
PG7_GPIO47 PG3_GPIO43
Boot Mode No.
Master Subsystem Boot Modes
Boot from Parallel GPIO
(BOOT_3)(1)
(BOOT_2)(1)
(BOOT_1)(1)
(BOOT_0)(1)
0(2)
1(2)
0
0
0
0
0
0
0
1
Boot to Master Subsystem RAM
Boot from Master Subsystem serial
peripherals (UART0/SSI0/I2C0)
2(2)
3(2)
4(2)
0
0
0
0
0
1
1
1
0
0
1
0
Boot from Master Subsystem CAN interface
Boot from Master Subsystem Ethernet
interface
Not supported (Defaults to Boot-to-Flash),
future boot from Cortex™-M3 USB
5(2)
0
1
0
1
6(2)
7(2)
8(3)
Not supported (Defaults to Boot-to-Flash)
Boot to Master Subsystem Flash memory
Not supported (Defaults to Boot-to-Flash)
0
0
1
1
1
0
1
1
0
0
1
0
Boot from Master Subsystem serial
peripheral – SSI0 Master
9(3)
1
1
0
0
0
1
1
0
Boot from Master Subsystem serial
peripheral – I2C0 Master
10(3)
11(3)
12(3)
13(3)
14(3)
15(3)(4)(5)
Not supported (Defaults to Boot-to-Flash)
Not supported (Defaults to Boot-to-Flash)
Not supported (Defaults to Boot-to-Flash)
Not supported (Defaults to Boot-to-Flash)
Boot to Master Subsystem Flash memory
1
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
(1) By default, GPIO terminals are not pulled up (they are floating).
(2) Boot Modes 0–7 are pin-compatible with future members of the Concerto family (they use same GPIO terminals).
(3) Boot Modes 8–15 are not supported on silicon revision 0.
(4) This Boot Mode uses a faster Flash power-up sequence. The maximum supported OSCCLK frequency for this mode is 30 MHz.
(5) This Boot Mode is the same as Boot Mode 7, but in Fast Mode.
Boot Mode 7 and Boot Mode 15 cause the Master program to branch execution to the application in the
Master Flash memory. This branching requires that the Master Flash be already programmed with valid
code; otherwise, a hard fault exception is generated and the Cortex™-M3 goes back to the above reset
sequence. (Therefore, for a factory-fresh device, the M-Bootloader will be in a continuous reset loop until
the emulator is connected and a debug session started.) If the Master Subsystem Flash has already been
programmed, the application code will start execution. Typically, the Master Subsystem application code
will then establish data communication with the C28x [through the IPC (Interprocessor Communications
peripheral)] to coordinate the rest of the boot process with the Control Subsystem. Boot Mode 15 (Fast
Boot to Flash Mode) supported on this device is a special boot to Flash mode, which configures Flash for
a faster power up, thus saving some boot time. Boot Mode 7 and other modes which default to Flash do
not configure Flash for a faster power up like Boot Mode 15 does. Note that following reset, the internal
pullup resistors on GPIOs are disabled. Therefore, Boot Mode 15, for example, will typically require four
external pullups.
Boot Mode 1 causes the Master boot program to branch to Cortex™-M3 RAM, where the Cortex™-M3
processor starts executing code that has been preloaded earlier. Typically, this mode is used during
development of application code meant for Flash, but which has to be first tested running out of RAM. In
this case, the user would typically load the application code into RAM using the debugger, and then issue
a debugger reset, while setting the four boot pins to 0001b. From that point on, the rest of the boot
process on the Master Subsystem side is controlled by the application code.
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
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Boot Modes 0, 2, 3, 4, 9, 10, and 12 are used to load the Master application code from an external
peripheral before branching to the application code. This process is different from the process in Boot
Modes 1, 7, and 15, where the application code was either already programmed in Flash or loaded into
RAM by the emulator. If the boot mode selection pins are set to 0000b, the M-Bootloader (running out of
M-Boot ROM) will start uploading the Master application code from preselected Parallel GPIO_MUX pins.
If the boot pins are set to 0010b, the application code will be loaded from the Master Subsystem UART0,
SSI0, or I2C0 peripheral. (SSI0 and I2C0 are configured to work in Slave mode in this Boot Mode.) If the
boot pins are set to 0011b, the application code will be loaded from the Master Subsystem CAN interface.
Furthermore, if the boot pins are set to 0100b, the application code will be loaded through the Master
Subsystem Ethernet interface; the IOs used in this Boot Mode are compatible with the F28M35x device. If
the boot pins are set to 1001b or 1010b, then the application code will be loaded through the SSI0 or I2C0
interface, respectively. SSI0 and I2C0 loaders work in Master Mode in this boot mode. If the boot pins are
set to 1100b, then the application code will be loaded through the Master Subsystem Ethernet interface;
the IOs used in this Boot Mode are F28M35x IOs, which are available only in a BGA package.
Regardless of the type of boot mode selected, once the Master application code is resident in Master
Flash or RAM, the next step for the M-Bootloader is to branch to Master Flash or RAM. At that point, the
application code takes over control from the M-Bootloader, and the boot process continues as prescribed
by the application code. At this stage, the Master application program typically establishes communication
with the C-Bootloader, which by now, would have already initialized the Control Subsystem and forced the
C28x to go into Idle mode. To wake the Control Subsystem out of Idle mode, the Master application
issues the Master-to-Control-IPC-interrupt 1 (MTOCIPCINT1). Once the data communication has been
established through the IPC, the boot process can now also continue on the Control Subsystem side.
The rest of the Control Subsystem boot process is controlled by the Master Subsystem application issuing
IPC instructions to the Control Subsystem, with the C-Bootloader interpreting the IPC commands and
acting on them to continue the boot process. At this stage, a boot mode for the Control Subsystem can be
established. The Control Subsystem boot modes are similar to the Master Subsystem boot modes, except
for the mechanism by which they are selected. The Control Subsystem boot modes are chosen through
the IPC commands from the Master application code to the C-Bootloader, which interprets them and acts
accordingly. The choices are, as above, to branch to already existing Control application code in Flash, to
branch to preloaded code in RAM (development mode), or to upload the Control application code from
one of several available peripherals (see Table 2-18). As before, once the Control application code is in
place (in Flash or RAM), the C-Bootloader branches to Flash or RAM, and from that point on, the
application code takes over.
Table 2-18. Control Subsystem Boot Mode Selection
Control Subsystem
Boot Modes
MTOCIPCBOOTMODE
Register Value
Description
Upon receiving this command from the Master Subsystem, C-Boot
ROM will branch to the Control Subsystem RAM entry point location
and start executing code from there.
BOOT_FROM_RAM
0x0000 0001
0x0000 0002
Upon receiving this command, C-Boot ROM will branch to the
Control Subsystem FLASH entry point and start executing code from
there.
BOOT_FROM_FLASH
Upon receiving this command, C-Boot ROM will boot from the
Control Subsystem SCI peripheral.
BOOT_FROM_SCI
BOOT_FROM_SPI
0x0000 0003
0x0000 0004
0x0000 0005
0x0000 0006
Upon receiving this command, C-Boot ROM will boot from the
Control Subsystem SPI interface.
Upon receiving this command, C-Boot ROM will boot from the
Control Subsystem I2C interface.
BOOT_FROM_I2C
Upon receiving this command, C-Boot ROM will boot from the
Control Subsystem GPIO.
BOOT_FROM_PARALLEL
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
The boot process can be considered completed once the Cortex™-M3 and C28x are both running out of
their respective application programs. Note that following the boot sequence, the C-Bootloader is still
available to interpret and act upon an assortment of IPC commands that can be issued from the Master
Subsystem to perform a variety of configuration, housekeeping, and other functions. See the Concerto
F28M35x Technical Reference Manual (literature number SPRUH22) for additional information on
Concerto boot modes, IPC commands, and the underlying boot philosophy.
2.9 Internal Voltage Regulation and Monitoring
While Concerto’s analog functions draw power from a single dedicated external power source—VDDA, its
digital circuits are powered by three separate rails: 3.3-V VDDIO, 1.8-V VDD18, and 1.2-V VDD12. This section
describes the sourcing, regulation, monitoring, and other considerations for these three digital power rails.
Concerto devices can be internally divided into an Analog Subsystem and a Digital Subsystem (having the
Cortex™-M3-based Master Subsystem and the C28x-based Control Subsystem). The Digital Subsystem
uses VDD12 to power the two processors, internal memory, and peripherals. The Analog Subsystem uses
VDD18 to power the digital logic associated with the analog functions. Both Digital and Analog Subsystems
share a common VDDIO rail to power their 3.3-V I/O buffers through which Concerto’s digital signals
communicate with the outside world.
The Analog and Digital Subsystems each have their own power regulation and monitoring functions that
operate independently, but which can—when the ARS and XRS reset pins are externally tied
together—simultaneously reset the entire Concerto device when power loss is imminent. See Figure 2-6
for a snapshot of the digital power regulation and monitoring functions provided within Concerto’s Analog
and Digital Subsystems.
2.9.1 Analog Subsystem Voltage Regulation and Monitoring
The Analog Subsystem internally provides voltage regulation and monitoring functions. Internal voltage
monitoring features consist of the Power-On Reset (POR) function that holds the device in reset state
during power up, and the Brown-Out Reset (BOR) functions that reset the device just before the VDDIO and
VDD18 power rails dip or VDD18 spikes outside of operational voltage range.
2.9.1.1 Analog Subsystem’s Internal 1.8-V VREG
The internal 1.8-V Voltage Regulator (VREG) generates VDD18 power from VDDIO. The 1.8-V VREG is
enabled by pulling the VREG18EN pin to a low state. When enabled, the 1.8-V VREG provides 1.8 V to
digital logic associated with the analog functions of the Analog Subsystem.
When the internal 1.8-V VREG function is enabled, the 1.8 V power no longer has to be provided
externally; however, a 1.2-µF capacitor is required for each VDD18 pin to stabilize the internally generated
voltages. These load capacitors are not required if the internal 1.8-V VREG is disabled, and the 1.8 V is
provided from an external supply.
Note that the same VREG18EN pin that enables the internal 1.8-V VREG also enables the 1.8-V BOR
function of the Analog Subsystem. Also note that while removing the need for an external power supply,
enabling the internal VREG will increase the VDDIO power consumption.
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
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CONNECT THE 2 RESET PINS EXTERNALLY THROUGH A BOARD TRACE
ARS
PIN
XRS
PIN
CONCERTO
DEVICE
M3WDOGS
POR
ARS
XRS
DE-GLITCH
DE-GLITCH
‘0’
‘0’
VOLTAGE MONITORING
(ANALOG SUBSYSTEM)
VOLTAGE MONITORING
(DIGITAL SUBSYSTEM)
3.3V
VMON
1.8V
BOR
3.3V
BOR
3.3V
POR
3.3V
POR
1.2V
POR
1.2V
1.8V
1.2V
BOW
CHECKS FOR
HI/LOW
CHECKS
CHECKS FOR
HI/LOW
VREGWARN NMI
FOR LOW
DIGITAL LOGIC
M3 CPU
M3 NMI
(DIGITAL SUBSYSTEM)
M3
M3 WDOGS
(0,1)
M3 NMI
WDOG
NVIC
DIGITAL LOGIC
RESETS
(ANALOG SUBSYSTEM)
ACIBRST M3RSNIN
CONTROL
SUB-
I/O
I/O
SYSTEM
RST
1.8V
1.2V
CRESCNF REG
1.8V
3.3V
1.2V
3.3V
1.8V VREG
1.2V VREG
(ANALOG SUBSYSTEM)
(DIGITAL SUBSYSTEM)
1.8V
SUPPLY SUPPLY SUPPLY
PINS PINS PINS
3.3V
1.2V
VREG18EN
PIN
VREG12EN
PIN
Figure 2-6. Voltage Regulation and Monitoring
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
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2.9.1.2 Analog Subsystem’s Voltage Monitoring
The Voltage Monitoring Block of the Analog Subsystem consists of the POR function and BOR functions.
POR holds the device in reset during power up, until power stabilizes and voltage levels reach operational
range. Once the device is properly powered up, the BOR functions search for power dips and spikes, and
assert ARS when voltage levels venture outside of operational range.
2.9.1.2.1 Analog Subsystem’s POR
POR keeps the ARS reset signal asserted during device power up, and deasserts the signal only when
the 3.3-V power rail reaches operational voltage level. While in most applications, the POR-generated
reset has a long enough duration to also reset other system ICs, some applications may require a longer-
lasting reset pulse. In these cases, the ARS reset pin (which is open-drain) can also be driven from
outside in, to match the time the device is held in reset state with the rest of the system.
When POR (or BOR) drives the ARS pin low, POR (or BOR) also resets the digital logic associated with
analog functions, and puts the GPIO pins of the Analog Subsystem General-Purpose IO block in a high-
impedance state.
2.9.1.2.2 Analog Subsystem’s BOR
The Analog Subsystem has two BOR functions that assert ARS when VDDIO or VDD18 dips below minimum
voltage levels, or when VDD18 surges above the maximum operational voltage. The internal 1.8-V VREG
must be enabled to activate the VDD18 BOR function (by pulling the VREG18EN pin low).
When BOR (or POR) drives the ARS pin low, BOR (or POR) also resets the digital logic associated with
analog functions, and puts the GPIO pins of the Analog Subsystem General-Purpose IO block in a high-
impedance state.
2.9.2 Digital Subsystem Voltage Regulation and Monitoring
The internal voltage monitoring features of the Digital Subsystem consist of the POR function that holds
the device in reset state during power up, and the BOW (Brown-Out Warning) function that issues a non-
maskable interrupt (NMI) to warn the device before impending power loss on the VDD12 rail. The NMI
allows software to safely shut down the device and for the reset of the system before power falls into
regions outside of specification, and potentially causing unexpected or erroneous system behavior.
2.9.2.1 Digital Subsystem’s Internal 1.2-V VREG
The internal 1.2-V VREG generates VDD12 power from VDDIO. The 1.2-V VREG is enabled by pulling the
VREG12EN pin to a low state. When enabled, the 1.2-V VREG internally provides 1.2 V to digital logic
associated with the processors, memory, and peripherals of the Digital Subsystem.
When the internal 1.2-V VREG function is enabled, the 1.2 V power no longer has to be provided
externally; however, a 492-nF capacitor is required for each VDD12 pin to stabilize the internally generated
voltages. These load capacitors are not required if the internal 1.2-V VREG is disabled and the 1.2 V is
provided from an external supply.
Note that while removing the need for an external power supply, enabling the internal VREG will increase
the VDDIO power consumption.
2.9.2.2 Digital Subsystem’s Voltage Monitoring
The Voltage Monitoring Block of the Digital Subsystem consists of POR functions and a BOW function.
POR functions hold the device in reset during power up, until power stabilizes and voltage levels reach
operational range. Once the device is properly powered up, the BOW function searches for dips and
spikes on the 1.2-V rail, and asserts VREGWARN NMI when voltage levels venture outside of minimum or
maximum values.
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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2.9.2.2.1 Digital Subsystem’s POR
POR keeps the XRS reset signal asserted during device power up, and deasserts the signal only when
the 1.2-V and 3.3-V power rails reach operational range. While in most applications, the POR-generated
reset has a long enough duration to also reset other system ICs, some applications may require a longer-
lasting system reset pulse. In these cases, the XRS reset pin (which is open-drain) can also be driven
from outside in, to match the time the device is held in reset state with the rest of the system.
When POR drives the XRS pin low, POR also resets all digital logic of the Digital Subsystem, and puts the
GPIO pins of the Digital Subsystem General-Purpose IO block in a high-impendance state.
In addition to the POR reset, the Digital Subsystem’s Resets block also receives reset inputs from NVIC,
the Cortex™-M3 Watchdogs (0, 1), and from the Cortex™-M3 NMI Watchdog. The resulting reset output
signal is then fed back to the XRS pin after being ANDed with the POR reset (see Figure 2-6).
On a related note, only the Master Subsystem comes out of reset state immediately following the device
power up. The Control and Analog Subsystems continue to be held in reset until the Master Processor
(Cortex™-M3) brings them out of reset by writing a "1" to the M3RSNIN and ACIBRST bits of the
CRESCNF Register (see Figure 2-6).
2.9.2.2.2 Digital Subsystem’s BOW
The Digital Subsystem has a BOW function that can send a VREGWARN NMI (Non-Maskable Interrupt)
to the Cortex™-M3 NMI block when VDD12 starts drifting outside of operational range. The NMI block
simultaneously sends the M3NMIINT to the Cortex™-M3 NVIC/CPU and starts the counter inside the
Cortex™-M3 NMI Watchdog.
While the NMI Watchdog is counting down, the Cortex™-M3 CPU can attempt to safely shut down the
device and the system. When the count reaches "0", the NMI Watchdog asserts a reset input to the
Resets block, forcing the entire Digital Subsystem to go into a reset state, including the CRESCNF
register, which by default also resets the Analog and Control Subsystems.
By default, the BOW function is disabled after reset.
2.9.3 Connecting ARS and XRS Pins
In most Concerto applications, TI recommends that the ARS and XRS pins be tied together by external
means—such as through a signal trace on a PCB board. Tying the ARS and XRS pins enables the
internal BOR functions of the Analog Subsystem to also reset the Digital Subsystem during internally
detected power brown-out conditions. Tying the ARS and XRS pins also ensures that other reset sources
will cause both the Analog and Digital Subsystems to enter the reset state together, regardless of where
the reset condition occurs.
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
2.10 Input Clocks and PLLs
Concerto devices have multiple input clock pins from which all internal clocks and the output clock are
derived. Figure 2-7 shows the recommended methods of connecting crystals, resonators, and oscillators
to pins X1/X2 and XCLKIN.
CONCERTO DEVICE
CONCERTO DEVICE
X1
X2
X1
X2
v
v
ssosc
ssosc
RESONATOR
CRYSTAL
R
C
C
D
L2
L1
CONCERTO DEVICE
CONCERTO DEVICE
X1
X2
XCLKIN
v
ssosc
NC
NC
3.3V
CLK
3.3V
CLK
VDD
OUT
GND
VDD
OUT
GND
3.3V OSCILLATOR
3.3V OSCILLATOR
Figure 2-7. Connecting Input Clocks to a Concerto Device
2.10.1 Internal Oscillator (Zero-Pin)
Each Concerto device contains a zero-pin internal oscillator. This oscillator outputs two fixed-frequency
clocks: 10MHZCLK and 32MHZCLK. These clocks are not configurable by the user. They are used inside
the Master Subsystem to implement low-power modes. The 10MHZCLK is also used by the Missing Clock
Detect circuit.
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
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2.10.2 Crystal Oscillator/Resonator (Pins X1/X2 and VSSOSC
)
The main oscillator circuit connects to an external crystal through pins X1 and X2. If a resonator is used
(version of a crystal with built-in load capacitors), its ground terminal should be connected to the pin
VSSOSC (not board ground). The VSSOSC pin should also be used to ground the external load capacitors
connected to the two crystal terminals as shown in Figure 2-7.
2.10.3 External Oscillators (Pins X1 and XCLKIN)
Concerto has two pins (X1 and XCLKIN) into which a single-ended clock can be driven from external
oscillators or other clock sources. When connecting an external clock source through the X1 terminal, the
X2 terminal should be left unconnected. Most internal clocks of this device are derived from the X1 clock
input (or X1/X2 crystal) . The XCLKIN clock is only used by the USB PLL and CAN peripherals. Figure 2-7
shows how to connect external oscillators to the X1 and XCLKIN terminals.
When connecting an external oscillator, use good design practices to minimize EMI as well as clock jitter
induced by external noise sources. Minimize the loop area formed between the forward current path (from
the oscillator OUT terminal to the MCU X1 or XCLKIN terminal) and the return path (from the MCU VSS
terminal to the oscillator GND terminal).
Locate the external oscillator as close to the MCU as practical. Ideally, the return ground trace should be
an isolated trace directly underneath the forward trace or run adjacent to the trace on the same layer.
Spacing should be kept minimal, with any other nearby traces double-spaced away, so that the
electromagnetic fields created by the two opposite currents cancel each other out as much as possible,
thus reducing parasitic inductances that radiate EMI.
2.10.4 Main PLL
The Main PLL uses the reference clock from pins X1 (external oscillator) or X1/X2 (external
crystal/resonator). The input clock is multiplied by an integer multiplier and a fractional multiplier as
selected by the SPLLIMULT and SPLLFMULT fields of the SYSPLLMULT register. The output clock from
the Main PLL must be between 110 MHz and 550 MHz. The PLL output clock is then divided by 2 before
entering a mux that selects between this clock and the PLL input clock – OSCCLK (used in PLL bypass
mode). The PLL bypass mode is selected by setting the SPLLIMULT field of the SYSPLLMULT register
to 0. The output clock from the mux next enters a divider controlled by the SYSDIVSEL register, after
which the output clock becomes the PLLSYSCLK. Figure 2-8 shows the Main PLL function and
configuration examples. Table 2-19 to Table 2-22 list the integer multiplier configuration values.
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
SYSPLLMULT REG
SYSPLLCTL REG
SYSDIVSEL REG
(2)
SPLLIMULT
SPLLFMULT
SPLLEN
SPLLCLKEN
SYSDIVSEL (1:0)
= 00 ( /1 )
OSCCLK
0
7
2
/1
/2
MAIN PLL
PLLSYSCLK
/4
/8
PIN
X1
INTEGER
FRACTIONAL
MULTIPLIER
MULTIPLIER
(1)
PLLOUT
MAIN
OSC
/2
1
OSCCLK
0000000 : x 1
0000001 : x 1
OUPUT OF
MAIN PLL
0000010 : x 2
00: NOT USED
0000011 : x 3
01:
10:
11:
x 0.25
x 0.50
x 0.75
IS ALWAYS
DIVIDED BY 2
.
.
.
1111101: x 125
1111110: x 126
1111111: x 127
(1) OUPUT OF THE MAIN PLL MUST RANGE BETWEEN 110- 550 MHz
(2) WHEN SPLLEN BIT = 0, THE MAIN PLL IS POWERED OFF
EXAMPLE 1:
EXAMPLE 2:
EXAMPLE 3:
X1 = 100 MHZ
X1 = 10 MHz
X1 = 20 MHz
SPLLIMULT = 0000000 ( BYPASS PLL)
N/A
PLLSYSCLK = 100 MHz
PLLSYSCLK = [ ( 10 x 20)
SPLLIMULT = 0010100 ( x 20 )
SPLLIMULT = 0111100 ( x 60 )
SPLLFM ULT = 00 ( NOT USED)
SPLLF MULT = 01 ( x 0.25 )
/ 2 ] / 1 = 100 MHz
PLLSYSCLK = [ ( 20 x 60 x 0.25 ) / 2 ] / 1 = 150 MHz
Figure 2-8. Main PLL
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
Table 2-19. Main PLL Integer Multiplier Configuration
(Bypass PLL to x 31)
SPLLIMULT(6:0)
MULT VALUE
0000000 b
0000001 b
0000010 b
0000011 b
0000100 b
0000101 b
0000110 b
0000111 b
Bypass PLL
x 1
x 2
x 3
x 4
x 5
x 6
x 7
0001000 b
0001001 b
0001010 b
0001011 b
0001100 b
0001101 b
0001110 b
0001111 b
x 8
x 9
x 10
x 11
x 12
x 13
x 14
x 15
0010000 b
0010001 b
0010010 b
0010011 b
0010100 b
0010101 b
0010110 b
0010111 b
x 16
x 17
x 18
x 19
x 20
x 21
x 22
x 23
0011000 b
0011001 b
0011010 b
0011011 b
0011100 b
0011101 b
0011110 b
0011111 b
x 24
x 25
x 26
x 27
x 28
x 29
x 30
x 31
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
Table 2-20. Main PLL Integer Multiplier Configuration
(x 32 to x 63)
SPLLIMULT(6:0)
0100000 b
0100001 b
0100010 b
0100011 b
0100100 b
0100101 b
0100110 b
0100111 b
MULT VALUE
x 32
x 33
x 34
x 35
x 36
x 37
x 38
x 39
0101000 b
0101001 b
0101010 b
0101011 b
0101100 b
0101101 b
0101110 b
0101111 b
x 40
x 41
x 42
x 43
x 44
x 45
x 46
x 47
0110000 b
0110001 b
0110010 b
0110011 b
0110100 b
0110101 b
0110110 b
0110111 b
x 48
x 49
x 50
x 51
x 52
x 53
x 54
x 55
0111000 b
0111001 b
0111010 b
0111011 b
0111100 b
0111101 b
0111110 b
0111111 b
x 56
x 57
x 58
x 59
x 60
x 61
x 62
x 63
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
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Table 2-21. Main PLL Integer Multiplier Configuration
(x 64 to x 95)
SPLLIMULT(6:0)
1000000 b
1000001 b
1000010 b
1000011 b
1000100 b
1000101 b
1000110 b
1000111 b
MULT VALUE
x 64
x 65
x 66
x 67
x 68
x 69
x 70
x 71
1001000 b
1001001 b
1001010 b
1001011 b
1001100 b
1001101 b
1001110 b
1001111 b
x 72
x 73
x 74
x 75
x 76
x 77
x 78
x 79
1010000 b
1010001 b
1010010 b
1010011 b
1010100 b
1010101 b
1010110 b
1010111 b
x 80
x 81
x 82
x 83
x 84
x 85
x 86
x 87
1011000 b
1011001 b
1011010 b
1011011 b
1011100 b
1011101 b
1011110 b
1011111 b
x 88
x 89
x 90
x 91
x 92
x 93
x 94
x 95
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
www.ti.com
SPRS742D –JUNE 2011–REVISED AUGUST 2012
Table 2-22. Main PLL Integer Multiplier Configuration
(x 96 to x 127)
SPLLIMULT(6:0)
1100000 b
1100001 b
1100010 b
1100011 b
1100100 b
1100101 b
1100110 b
1100111 b
MULT VALUE
x 96
x 97
x 98
x 99
x 100
x 101
x 102
x 103
1101000 b
1101001 b
1101010 b
1101011 b
1101100 b
1101101 b
1101110 b
1101111 b
x 104
x 105
x 106
x 107
x 108
x 109
x 110
x 111
1110000 b
1110001 b
1110010 b
1110011 b
1110100 b
1110101 b
1110110 b
1110111 b
x 112
x 113
x 114
x 115
x 116
x 117
x 118
x 119
1111000 b
1111001 b
1111010 b
1111011 b
1111100 b
1111101 b
1111110 b
1111111 b
x 120
x 121
x 122
x 123
x 124
x 125
x 126
x 127
2.10.5 USB PLL
The USB PLL uses the reference clock selectable between the input clock arriving at the XCLKIN pin, or
the internal OSCCLK (originating from the external crystal or oscillator via the X1/X2 pins). An input mux
selects the source of the USB PLL reference based on the UPLLCLKSRC bit of the UPLLCTL Register
(see Figure 2-9). The input clock is multiplied by an integer multiplier and a fractional multiplier as selected
by the UPLLIMULT and UPLLFMULT fields of the UPLLMULT register. The output clock from the USB
PLL must always be 240 MHz. The PLL output clock is then divided by 4—resulting in 60 MHz that the
USB needs—before entering a mux that selects between this clock and the PLL input clock (used in the
PLL bypass mode). The PLL bypass mode is selected by setting the UPLLIMULT field of the UPLLMULT
register to 0. The output clock from the mux becomes the USBPLLCLK (there is not another clock divider).
Figure 2-9 shows the USB PLL function and configuration examples. Table 2-23 and Table 2-24 list the
integer multiplier configuration values.
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
UPLLMULT REG
UPLLCTL REG
(2)
UPLLCLKSRC
UPLLIMULT
UPLLFMULT
UPLLEN
UPLLCLKEN
0
6
2
PIN
X1
USB PLL
USBPLLCLK
OSCCLK
XCLKIN
MAIN
OSC
0
INTEGER
FRACTIONAL
MULTIPLIER
MULTIPLIER
(1)
PLLOUT
/4
1
PLLINP
000000 : x 1
000001 : x 1
OUPUT OF
1
000010 : x 2
00: NOT USED
THE USB PLL
IS ALWAYS
DIVIDED BY 4
000011 : x 3
01:
10:
11:
x 0.25
x 0.50
x 0.75
PIN
.
.
.
XCLKIN
111101: x 61
111110: x 62
111111: x 63
(1) OUPUT OF THE USB PLL MUST BE ALWAYS 240MHz ( SO THAT USBPLLCLK IS 60MHZ )
(2) WHEN UPLLEN BIT = 0, THE USB PLL IS POWERED OFF
EXAMPLE 1:
EXAMPLE 2:
EXAMPLE 3:
X1 OR XCLKIN = 60 MHZ
X1 OR XCLKIN = 10 MHz
X1 OR XCLKIN = 30 MHz
UPLLIMULT = 000000 ( BYPASS PLL)
UPLLIMULT = 011000 ( x 24 )
UPLLIMULT = 010000 ( x 16 )
N/A
PLLSYSCLK = 60 MHz
PLLSYSCLK = ( 10 x 24)
UPLLFMULT = 00 ( NOT USED)
UPLLFMULT = 10 ( x 0.50)
/ 4 = 60 MHz
PLLSYSCLK = ( 30 x 16 x 0.50 ) / 4 = 60 MHz
Figure 2-9. USB PLL
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
Table 2-23. USB PLL Integer Multiplier Configuration
(Bypass PLL to x 31)
SPLLIMULT(5:0)
MULT VALUE
000000 b
000001 b
000010 b
000011 b
000100 b
000101 b
000110 b
000111 b
Bypass PLL
x 1
x 2
x 3
x 4
x 5
x 6
x 7
001000 b
001001 b
001010 b
001011 b
001100 b
001101 b
001110 b
001111 b
x 8
x 9
x 10
x 11
x 12
x 13
x 14
x 15
010000 b
010001 b
010010 b
010011 b
010100 b
010101 b
010110 b
010111 b
x 16
x 17
x 18
x 19
x 20
x 21
x 22
x 23
011000 b
011001 b
011010 b
011011 b
011100 b
011101 b
011110 b
011111 b
x 24
x 25
x 26
x 27
x 28
x 29
x 30
x 31
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
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Table 2-24. USB PLL Integer Multiplier Configuration
(x 32 to x 63)
SPLLIMULT(5:0)
100000 b
100001 b
100010 b
100011 b
100100 b
100101 b
100110 b
100111 b
MULT VALUE
x 32
x 33
x 34
x 35
x 36
x 37
x 38
x 39
101000 b
101001 b
101010 b
101011 b
101100 b
101101 b
101110 b
101111 b
x 40
x 41
x 42
x 43
x 44
x 45
x 46
x 47
110000 b
110001 b
110010 b
110011 b
110100 b
110101 b
110110 b
110111 b
x 48
x 49
x 50
x 51
x 52
x 53
x 54
x 55
111000 b
111001 b
111010 b
111011 b
111100 b
111101 b
111110 b
111111 b
x 56
x 57
x 58
x 59
x 60
x 61
x 62
x 63
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
2.11 Master Subsystem Clocking
The internal PLLSYSCLK clock, normally used as a source for all Master Subsystem clocks, is a divided-
down output of the Main PLL or X1 external clock input, as defined by the SPLLCKEN bit of the
SYSPLLCTL register.
There is also a second oscillator that internally generates two clocks: 32KHZCLK and 10MHZCLK. The
10MHZCLK is used by the Missing Clock Circuit to detect a possible absence of an external clock source
to the Main Oscillator that drives the Main PLL. Detection of a missing clock results in a substitution of the
10MHZCLK for the PLLSYSCLK. The CLKFAIL signal is also sent to the NMI Block and the Control
Subsystem where this signal can trip the ePWM peripherals.
The 32KHZCLK and 10MMHZCLK clocks are also used by the Cortex™-M3 Subsystem as possible
sources for the Deep Sleep Clock.
There are four registers associated with the Main PLL: SYSPLLCTL, SYSPLLMULT, SYSPLLSTAT and
SYSDIVSEL. Typically, the Cortex™-M3 processor writes to these registers, while the C28x processor has
read access. The C28x can request write access to the above registers through the CLKREQEST register.
Cortex™-M3 can regain write ownership of these registers through the MCLKREQUEST register.
The Master Subsystem operates in one of three modes: Run Mode, Sleep Mode, or Deep Sleep Mode.
Table 2-25 shows the Master Subsystem low-power modes and their effect on both CPUs, clocks, and
peripherals. Figure 2-10 shows the Cortex™-M3 clocks and the Master Subsystem low-power modes.
Table 2-25. Master Subsystem Low-Power Modes
Register
Used to
Gate Clocks Main
to Cortex™-
M3
Cortex™-M3
Low-Power Cortex™-M3
State of
Clock to
Cortex™-M3
Peripherals
Clock to
Analog
Subsystem
USB
PLL
Clock to Shared
Resources
Clock to C28x
PLL
Mode
CPU
Peripherals
Run
Active
M3SSCLK(1)
M3SSCLK(1)
RCGC
On
On
On
On
PLLSYSCLK(2)
PLLSYSCLK(2)
PLLSYSCLK(2)
PLLSYSCLK(2)
ASYSCLK(3)
ASYSCLK(3)
RCGC or
SCGC(4)
Sleep
Stopped
RCGC or
DCGC(4)
Deep Sleep
Stopped
M3DSDIVCLK(5)
Off
Off
Off
Off
Off
(1) PLLSYSCLK or OSCCLK divided-down per the M3SSDIVSEL register. In case of a missing source clock, M3SSCLK becomes
10MHZCLK divided-down per the M3SSDIVSEL register.
(2) PLLSYSCLK normally refers to the output of the Main PLL divided-down per the SYSDIVSEL register. In case the PLL is bypassed, the
PLLSYSCLK becomes the OSCCLK divided-down per the SYSDIVSEL register. In case of a missing source clock, the 10MHZCLK is
substituted for the PLLSYSCLK.
(3) PLLSYSCLK or OSCCLK divided-down per the CCLKCTL register. In case of a missing source clock, ASYSCLK becomes 10MHZCLK.
(4) Depends on the ACG bit of the RCC register.
(5) 32KHZCLK or 10MHZCLK or OSCCLK chosen/divided-down per the DSLPCLKCFG register, then again divided by the M3SSDIVSEL
register (source determined inside the DSLPCLKCFG register).
2.11.1 Cortex™-M3 Run Mode
In Run Mode, the Cortex™-M3 processor, memory, and most of the peripherals are clocked by the
M3SSCLK, which is a divide-down version of the PLLSYSCLK (from Main PLL). The USB is clocked from
a dedicated USB PLL, the CAN peripherals are clocked by M3SSCLK, OSCCLK, or XCLKIN, and one of
two watchdogs (WDOG1) is also clocked by the OSCCLK. Clock selection for these peripherals is
accomplished via corresponding peripheral configuration registers. Clock gating for individual peripherals
is defined inside the RCGS register. RCGS, SCGS, and DCGS clock-gating settings only apply to
peripherals that are enabled in a corresponding DC (Device Configuration) register.
Execution of the WFI instruction (Wait-for-Interrupt) shuts down the HCLK to the Cortex™-M3 CPU and
forces the Cortex™-M3 Subsystem into Sleep or Deep Sleep low-power mode, depending on the state of
the SLEEPDEEP bit of the Cortex™-M3 SYSCTRL register. To come out of a low-power mode, any
properly configured interrupt event terminates the Sleep or Deep Sleep Mode and returns the Cortex™-M3
processor/subsystem to Run Mode.
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
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M3 CPU
INTR
ASSERT ANY INTERRUPT
NVIC
TO EXIT SLEEP OR DEEP SLEEP
execution of WFI or WFE instr
activates low power modes
REGISTER
ACCESS
REGISTER
ACCESS
SELECTS TYPE
OF WAKEUP
SLEEPONEXIT
FCLK
HCLK
M3CLKENBx
M3SSCLK
M3SSCLK
M3SSCLK
PERIPH
LOGIC
SYSCTRL REG
OSCCLK
M3SSCLK
WDOG 0
WDOG 1
SELECTS BETWEEN SLEEP
AND DEEP SLEEP MODES
SLEEPDEEP
ENTER A LOW POWER MODE
M3SSCLK
RCC REG
ENABLE
CLOCK MODE
PERIPH
LOGIC
uCRC
NMI WDOG
GP TIMER (4)
SSI (4)
OSCCLK
XCLKIN
CAN
1,2
ACG (Auto Clock Gate)
CLOCKS
M3RUN
PERIPHERAL
CLOCK
M3SLEEP
M3CLKENBx
USB + PHY
(OTG)
M3DEEPSLEEP
ENABLES
USBPLLCLK
( CLOCK GATING – RUN )
( CLOCK GATING – SLEEP )
RCGC REG
SCGS REG
M3DEEPSLEEP
PLL
DIS
USB
PLL
( CLOCK GATING – DEEP SLEEP )
DCGC REG
DC REG
UART (5)
I2C (2)
DSLPCLKCFG REG
DSOSCSRC
M3SSDIVSEL REG
OSCCLK
XCLKIN
( GLOBAL PERIPHERAL ENABLES )
DSDIVOVRIDE
M3SSDIVSEL
32KHZCLK
10MHZCLK
OSCCLK
/1
/2
…
/1
/2
/4
M3DSDIVCLK
1
0
M3SSCLK
OSCCLK
EMAC
/16
XCLKIN
GPIO_MUX1
EPI
MCLKREQUEST REG
SYSDIVSEL REG
uDMA
SYSDIVSEL
SYSPLLSTAT REG
SYSPLLMULT REG
SYSPLLCTL REG
32KHZCLK
10MHZCLK
OSCCLK
IPC
X2
X1
M3SSCLK
MAIN OSC
OFF
OSCCLK
/2
SHARED
RAMS
1
0
PLLSYSCLK
0
1
/1
/2
/4
/8
INTERNAL
OSC
MISSING
PLL
DIS
MAIN
PLL
CLK DETECT
MSG
RAMS
10MHZCLK
CLOCKFAIL
CLOCKFAIL
CLPMSTAT REG
M3 NMI
SHARED
10MHZCLK
CLOCKFAIL
OSCCLK
RESOURCES
CONTROL SUBSYSTEM
Figure 2-10. Cortex™-M3 Clocks and Low-Power Modes
58
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
2.11.2 Cortex™-M3 Sleep Mode
In Sleep Mode, the Cortex™-M3 processor and memory are prevented from clocking, and thus the code is
no longer executing. The gating for the peripheral clocks may change based on the ACG bit of the RCC
register. When ACG = 0, the peripheral clock gating is used as defined by the RCGS registers (same as in
Run Mode); and when ASC = 1, the clock gating comes from the SCGS register. RCGS and SCGS clock-
gating settings only apply to peripherals that are enabled in a corresponding DC register. Peripheral clock
frequency for the enabled peripherals in Sleep Mode is the same as during the Run Mode.
Sleep Mode is terminated by any properly configured interrupt event. Exiting from the Sleep Mode
depends on the Sleeponexit bit of the SYSCTRL register. When the Sleeponexit bit is 1, the processor will
temporarily wake up only for the duration of the ISR of the interrupt causing the wake-up. After that, the
processor goes back to Sleep Mode. When the Sleeponexit bit is 0, the processor wakes up permanently
(for the ISR and thereafter).
2.11.3 Cortex™-M3 Deep Sleep Mode
In Deep Sleep Mode, the Cortex™-M3 processor and memory are prevented from clocking and thus the
code is no longer executing. The Main PLL, USB PLL, ASYSCLK to the Analog Subsystem, and input
clock to the C28x CPU and Shared Resources are turned off. The gating for the peripheral clocks may
change based on the ACG bit of the RCC register. When ACG = 0, the peripheral clock gating is used as
defined by the RCGS registers (same as in Run Mode); and when ASC = 1, the clock gating comes from
the DCGS register. RCGS and DCGS clock gating settings only apply to peripherals that are enabled in a
corresponding DC register.
Peripheral clock frequency for the enabled peripherals in Deep Sleep Mode is different from the Run
Mode. One of three sources for the Deep Sleep clocks (32KHZCLK, 10MHZCLK, or OSCLK) is selected
with the DSOSCSRC bits of the DSLPCLKCFG register. This clock is divided-down according to
DSDIVOVRIDE bits of the DSLPCLKCFG register. The output of this Deep Sleep Divider is further
divided-down per the M3SSDIVSEL bits of the D3SSDIVSEL register to become the Deep Sleep Clock. If
32KHXCLK or 10MHZCLK is selected in Deep Sleep mode, the internal oscillator circuit (that generates
OSCCLK) is turned off.
The Cortex™-M3 processor should enter the Deep Sleep mode only after first confirming that the C28x is
already in the Standby mode. Typically, just before entering the Standby mode, the C28x will record in the
CLPMSTAT that it is about to do so. The Cortex™-M3 processor can read the CLPMSTAT register to
check if the C28x is in Standby mode, and only then should the Cortex™-M3 processor go into Deep
Sleep. The reason for the Cortex™-M3 processor to confirm that the C28x is in Standby mode before the
Cortex™-M3 processor enters the Deep Sleep mode is that the Deep Sleep mode shuts down the clock to
C28x and its peripherals, and if this clock shutdown is not expected by the C28x, unintended
consequences could result for some of the C28x control peripherals.
Deep Sleep Mode is terminated by any properly configured interrupt event. Exiting from the Deep Sleep
Mode depends on the Sleeponexit bit of the SYSCTRL register. When the Sleeponexit bit is 1, the
processor will temporarily wake up only for the duration of the ISR of the interrupt causing the wake-up.
After that, the processor goes back to Deep Sleep Mode. When the Sleeponexit bit is 0, the processor
wakes up permanently (for the ISR and thereafter).
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
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2.12 Control Subsystem Clocking
The CLKIN input clock to the C28x processor is normally a divided-down output of the Main PLL or X1
external clock input. There are four registers associated with the Main PLL: SYSPLLCTL, SYSPLLMULT,
SYSPLLSTAT and SYSDIVSEL. Typically, the Cortex™-M3 processor writes to these registers, while the
C28x processor has read access. The C28x can request write access to the above registers through the
CLKREQEST register. The Cortex™-M3 can regain write ownership of these registers through the
MCLKREQUEST register.
Individual C28x peripherals can be turned on or off by gating C28SYSCLK to those peripherals, which is
done via the CPCLKCR0,2,3 registers.
The C28x processor outputs two clocks: C28CPUCLK and C28SYSCLK. The C28SYSCLK is used by
C28x peripherals, C28x Timer 0, C28x Timer 1, and C28x Timer 2. C28x Timer 2 can also be clocked by
OSCCLK or 10MHZCLK (see Figure 2-11). The C28CPUCLK is used by the C28x CPU, FPU, VCU, and
PIE.
The Control Subsystem operates in one of three modes: Normal Mode, Idle Mode, or Standby Mode.
Table 2-26 shows the Control Subsystem low-power modes and their effect on the C28x CPU, clocks, and
peripherals. Figure 2-11 shows the Control Subsystem clocks and low-power modes.
Table 2-26. Control Subsystem Low-Power Modes(1)
Registers Used to Gate
C28x Low-Power Mode
State of C28x CPU
C28CPUCLK(2)
C28SYSCLK(3)
Clocks to C28x
Peripherals
Normal
Idle
Active
On
Off
Off
On
On
Off
CPCLKCR0,1,3
CPCLKCR0,1,3
N/A
Stopped
Stopped
Standby
(1) The input clock to the C28x CPU is PLLSYSCLK from the Master Subsystem. This clock is turned off when the Master Subsystem
enters the Deep Sleep mode.
(2) C28CPUCLK is an output from the C28x CPU. C28CPUCLK clocks the C28x FPU, VCU, and PIE.
(3) C28SYSCLK is an output from the C28x CPU. C28SYSCLK clocks C28x peripherals.
2.12.1 C28x Normal Mode
In Normal Mode, the C28x processor, Local Memory, and C28x peripherals are clocked by the
C28SYSCLK, which is derived from the C28CLKIN input clock to the C28x processor. The FPU, VCU, and
PIE are clocked by the C28CPUCLK, which is also derived from the C28CLKIN. Timer 2 can also be
clocked by the TMR2CLK, which is a divided-down version of one of three source clocks—C28SYSCLK,
OSCCLK, and 10MHZCLK—as selected by the CLKCTL register. Additionally, the LOSPCP register can
be programmed to provide a dedicated clock (C28LSPCLK) to the SCI, SPI, and McBSP peripherals; and
the HISPCP register can be programmed to provide a dedicated clock (C28HSPCLK) to stretch three
outputs from ePWM peripherals.
Clock gating for individual peripherals is defined inside the CPCLKCR0,1,3 registers. Execution of the
IDLE instruction stops the C28x processor from clocking and activates the IDLES signal. The IDLES
signal is gated with two LPM bits of the CPCLKCR0 register to enter the C28x Subsystem into Idle mode
or Standby Mode.
2.12.2 C28x Idle Mode
In Idle Mode, the C28x processor stops executing instructions and the C28CPUCLK is turned off. The
C28SYSCLK continues to run. Exit from Idle Mode is accomplished by any enabled interrupt or the
C28NMIINT (C28x non-maskable interrupt).
Upon exit from Idle Mode, the C28CPUCLK is restored. If LPMWAKE interrupt is enabled, the LPMWAKE
ISR is executed. Next, the C28x processor starts fetching instructions from a location immediately
following the IDLE instruction that originally triggered the Idle Mode.
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
GPIO_MUX1
C28x NMI
MASTER SUBSYSTEM
ACIBRST
ASYSRST
SRXRST
CCLKCTL REG
CLKDIV
CLOCKFAIL
SYSDIVSEL REG
SYSPLLSTAT REG
SYSPLLMULT REG
SYSPLLCTL REG
CLPMSTAT REG
10MHZCLK
OSCCLK
OFF
/1
HISPCP REG
HSPCLK
ASYSCLK
/2
/4
/8
CCLKREQUEST REG
PLLSYSCLK
M3SSCLK
/1
/2
/4
C28HSPCLK
CXCLK REG
XCLKOUTDIV
XPLLCLKCFG REG
XPLLCLKOUTDIV
PULSE
STRETCH
…
C28SYSCLK
/14
OFF
/4
/2
0
C28SYSCLK
XCLKOUT
1
2
3
GPIO_MUX1
/4
/1
OFF
LOSPCP REG
LSPCLK
CLKOFF REG
EPWM (9)
(NOTE: IN REVISION 0 OF SILICON, XCLKOUT = PLLSYSCLK DIVIDED DOWN BY 1, 2 OR 4)
‘0’
TINT2
/1
/2
TIMER 2
C28LSPCLK
STANDBY
MODE
/4
C28CLKIN
McBSP
SCI
…
TINT 1
/14
TIMER 1
C28x CPU
EXIT
STANDBY
MODE
EXIT
IDLE
TIMER 0
execution of IDLE instruction
activates the IDLES signal
MODE
SPI
PIEINTRS (1)
C28 XINT(3)
I2C
PIEINTRS (12:1)
C28NMIINT
ENTER
STANDBY
MODE
ENTER
IDLE
IDLES
C28x
PIE
MTOCIPC(1)
MODE
C28 DMA
EQEP (3)
ECAP (6)
C28 FPU/VCU
C28x
PIE
LPM(1)
LPM(0)
CLPMCR0 REG
C28CPUCLK
C28SYSCLK
C28SYSCLK
CLKCTL REG
LPMWAKE
SELECT QUALIFICATION
SELECT ONE OF 62 GPIs
CPCLKCR3 REG
CPCLKCR1 REG
CPCLKCR0 REG
LPM WAKEUP
CTMR2CLK
PRESCALE
TMR2CLKSRCSEL
GPI (63:0) MINUS
LPMSEL1 REG
LPMSEL2 REG
GPI 39 AND GPI 44
(NOT PINNED OUT)
/1
C28SYSCLK
OSCCLK
/2
/4
C28CLKENBx
/8
GPIO_MUX1
IPC
C28x NMI
/16
10MHZCLK
Figure 2-11. C28x Clocks and Low-Power Modes
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
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2.12.3 C28x Standby Mode
In Standby Mode, the C28x processor stops executing instructions and the C28CLKIN, C28CPUCLK, and
C28SYSCLK are turned off. Exit from Standby Mode is accomplished by 1 of 62 GPIOs from the
GPIO_MUX1 block, or MTOCIPCINT1 (interrupt from MTOC IPC peripheral). The wakeup GPIO selected
inside the GPIO_MUX block enters the Qualification Block as the LPMWAKE signal. Inside the
Qualification Block, the LPMWAKE signal is sampled per the QUALSTDBY bits (bits [7:2] of the
CPCLKCR0 register) before propagating into the wake request logic.
Cortex™-M3 should use CLPMSTAT register bits to tell the C28x to go into Standby mode before going
into Deep Sleep mode. Otherwise, the clock to the C28x will be turned off suddenly when the control
software is not expecting this clock to shut off. When the device is in Deep Sleep/Standby mode, wake-up
should happen only from the Master Subsystem, since all C28x clocks are off (C28CLKIN, C28CPUCLK,
C28SYSCLK), thus preventing the C28x from waking up first.
Upon exit from STANDBY Mode, the C28CLKIN, C28SYSCLK, and C28CPUCLK are restored. If the
LPMWAKE interrupt is enabled, the LPMWAKE ISR is executed. Next, the C28x processor starts fetching
instructions from a location immediately following the IDLE instruction that originally triggered the Standby
Mode.
NOTE
For GPIO_MUX1 pins PF6_GPIO38 and PG6_GPIO46, only the corresponding USB function
is available on silicon revision 0 devices (GPIO and other functions listed in Table 3-1 are not
available).
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
www.ti.com
SPRS742D –JUNE 2011–REVISED AUGUST 2012
2.13 Analog Subsystem Clocking
The Analog Subsystem is clocked by ASYSCLK, which is a divided-down version of the PLLSYSCLK as
defined by CLKDIV bits of the CCLKCTL register. The CCLKCTL register is exclusively accessible by the
C28x processor. The CCLKCTL register is reset by ASYSRST, which is derived from two Analog
Subsystem resets—ACIBRST and SRXRST. Therefore, while normally the C28x controls the frequency of
ASYSCLK, it is possible for the Cortex™-M3 software to restore the ASYSCLK to its default value by
resetting the Analog Subsystem.
The ASYSCLK is shut down when the Cortex™-M3 processor enters the Deep Sleep mode.
2.14 Shared Resources Clocking
The IPC, Shared RAMs, and Message RAMs are clocked by PLLSYSCLK. EPI is clocked by M3SSCLK.
The PLLSYSCLK normally refers to the output of the Main PLL divided-down per the SYSDIVSEL register.
In case the PLL is bypassed, the PLLSYSCLK becomes the OSCCLK divided-down per the SYSDIVSEL
register. In case of a missing source clock, the 10MHZCLK is substituted for the PLLSYSCLK.
Although EPI is a shared peripheral, it is physically located inside the Cortex™-M3 Subsystem; therefore,
EPI is clocked by M3SSCLK.
2.15 Loss of Input Clock (NMI Watchdog Function)
The Concerto devices use two type of input clocks. The main clock, for clocking most of the digital logic of
the Master, Control, and Analog subsystems, enters the chip through pins X1 and X2 when using external
crystal or just pin X1 when using an external oscillator. The second clock enters the chip through the
XCLKIN pin and this second clock can be used to clock the USB PLL and CAN peripherals. Only the main
clock has a built-in Missing Clock Detection circuit to recognize when the clock source vanishes and to
enable other chip components to take corrective or recovery action from such event (see Figure 2-12).
The Missing Clock Detection circuit itself is clocked by the 10MHZCLK (from an internal zero-pin oscillator)
so that, if the main clock disappears, the circuit is still working. Immediately after detecting a missing
source clock, the Missing Clock Detection circuit outputs the CLOCKFAIL signal to the Cortex™-M3 NMI
circuit, the C28x NMI, ePWM peripherals, and the PLLSYSCLK mux. When the PLLSYSCLK mux senses
an active CLOCKFAIL signal, the PLLSYSCLK mux revives the PLLSYSCLK using the 10MHZCLK.
Simultaneously, the ePWM peripherals can use the CLOCKFAIL signal to stop down driving motor control
outputs. The NMI blocks respond to the CLOCKFAIL signal by sending an NMI interrupt to a
corresponding CPU, while starting the associated NMI watchdog counter.
If the software does not respond to the clock-fail condition, the watchdog timers will overflow, resulting in
the device reset. If the software does react to the NMI, the software can prevent the impending reset by
disabling the watchdog timers, and then the software can initiate necessary corrective action such as
switching over to an alternative clock source (if available) or the software can initiate a shut-down
procedure for the system.
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
X2
1
PIN
MAIN
OSC
OSCCLK
X1
PIN
MAIN
PLL
4
ADDITIONAL CLOCK CONTROL LOGIC
PLLSYSCLK
10MHZCLK
MISSING
M3SSCLK
C28CLKIN
CLK DETECT
3
M3
2
INTERNAL
OSC
CPU
7
5
3
CLOCKFAIL
M3 NMI
M3 NMI WDOG
M3NMI
CLOCKFAIL
OTHER NMI
SOURCES
RESETS
TYPICAL ACTIVITY FOLLOWING
A MISSING CLOCK DETECTION :
3
C28NMI
C28x NMI
C28x NMI WDOG
THE INPUT CLOCK IS DISRUPTED
1
2
3
4
5
6
7
CLOCKFAIL
5
CLOCKFAIL SIGNAL BECOMES ACTIVE
3
7
CLOCK FAIL SIGNAL IS SENT TO M3 NMI BLOCK, C28 NMI
BLOCK, EPWM MODULES AND THE PLLSYSCLK MUX
C28x
CPU
EPWM
6
PLLSYSCLK SWITCHES TO THE 10MHZCLK
EPWM_A
EPWM_B
C28CLKIN
CPUS RESPOND TO NMIS AND THE
WATCHDOGS START COUNTING
GPIO_MUX1
SOFTWARE TAKES CORRECTIVE/RECOVERY ACTION
IF SOFTWARE DOES NOT STOP THE WATCHDOG COUNTERS, THE
WATCHDOGS WILL RESET THE DEVICE AFTER THE COUNT RUNS OUT
PIN
PIN
Figure 2-12. Missing Clock Detection
64
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
www.ti.com
SPRS742D –JUNE 2011–REVISED AUGUST 2012
2.16 GPIOs and Other Pins
Most Concerto external pins are shared among many internal peripherals. This sharing of pins is
accomplished through several I/O muxes where a specific physical pin can be assigned to selected
signals of internal peripherals.
Most of the I/O pins of the Concerto™ MCU can also be configured as programmable GPIOs. Exceptions
include the X1 and X2 oscillator inputs; the XRS digital reset and ARS analog reset; the VREG12EN and
VREG18EN internal voltage regulator enables; and five JTAG pins. The 74 primary GPIOs are grouped in
2 programmable blocks: GPIO_MUX1 block (66 pins) and GPIO_MUX2 block (8 pins). Additionally, eight
secondary GPIOs are available through the AIO_MUX1 block (four pins) and AIO_MUX2 block (four pins).
Figure 2-13 shows the GPIOs and other pins.
2.16.1 GPIO_MUX1
Sixty-six pins of the GPIO_MUX1 block can be selectively mapped through corresponding sets of registers
to all Cortex™-M3 peripherals, to all C28x peripherals, to 66 General-Purpose Inputs, to 66 General-
Purpose Outputs, or a mixture of all of the above. Sixty-two pins of GPIO_MUX1 (GPIO0–GPIO63 minus
GPIO39 and GPIO44) can also be mapped to 12 ePWM Trip Inputs, 6 eCAP inputs, 3 External Interrupts
to the C28x PIE, and the C28x Standby Mode Wakeup signal (LMPWAKE). Additionally, each
GPIO_MUX1 pin can have a pullup enabled or disabled. By default, all pullups and outputs are disabled
on reset, and all pins of the GPIO_MUX1 block are mapped to Cortex™-M3 peripherals (and not to C28x
peripherals).
Figure 2-14 shows the internal structure of GPIO_MUX1. The blue blocks represent the Master
Subsystem side of GPIO_MUX1, and the green blocks are the Control Subsystem side. The grey block in
the center, Pin-Level Mux, is where the GPIO_MUX1 pins are individually assigned between the two
subsystems, based on how the configuration registers are programmed in the blue and green blocks (see
Figure 2-15 for the configuration registers).
Pin-Level Mux assigns Master Subsystem peripheral signals, Control Subsystem peripheral signals, or
GPIOs to the 66 GPIO_MUX1 pins. In addition to connecting peripheral I/Os of the two subsystems to
pins, the Pin-Level Mux also provides other signals to the subsystems: XCLKIN and GPIO[A:J] IRQ
signals to the Master Subsystem, plus GPTRIP[12:1] and GPI[63:0] signals to the Control Subsystem.
XCLKIN carries a clock from an external pin to USB PLL and CAN modules. The nine GPIO[A:J] IRQ
signals are interrupt requests from selected external pins to the NVIC interrupt controller. The 12
GPTRIP[12:1] signals carry trip events from selected external pins to C28x control peripherals—ePWM,
eCAP, and eQEP. Sixty-four GPI signals go to the C28x LPM GPIO Select block where one of them can
be selected to wake up the C28x CPU from Low-Power Mode. Sixty-six (66) GPI signals go to the C28x
QUAL block where they can be configured with a qualification sampling period (see Figure 2-15).
The configuration registers for the muxing of Master Subsystem peripherals are organized in nine sets
(A–J), with each set being responsible for eight pins. These nine sets of registers are programmable by
the Cortex™-M3 CPU via the AHB bus or the APB bus. The configuration register for the muxing of
Control Subsystem peripherals are organized in three sets (A–C), with each set being responsible for up
to 32 pins. These registers are programmable by the C28x CPU via the C28x CPU bus. Figure 2-15
shows set A of the Master Subsystem GPIO configuration registers, set A of the Control Subsystem
registers, and the muxing logic for one GPIO pin as driven by these registers.
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
10
AIO_MUX1
GPIO
MUX
4
ADC1INA0
ADC1INA2
ADC1INA3
ADC1INA4
ADC1INA6
ADC1INA7
ADC1INB0
ADC1INB3
ADC1INB4
ADC1INB7
USB
PLL
EPI
USB
EMAC
M3
UART
(5)
CAN
SSI
(4)
I2C
(2)
NVIC
NMI
(2)
COMPA1
COMPA2
COMPA3
COMPB2
ADC
1
VDDA
(3.3V)
GPIO_MUX1
GPIO
MUX
6
66
66
COMPARATOR
+ DAC UNITS
8
GPI (63:0) MINUS
GPI 39 AND GPI 44
COMPOUT (6:1)
(NOT PINNED OUT)
VSSA
(0V)
8
LPM WAKEUP
LPMWAKE
C28X
CPU
EPWM
(9)
XINT
(3)
ECAP
(6)
EQEP
(3)
SPI
I2C
SCI
COMPA4
COMPB5
ADC
2
COMPA5
COMPA6
McBSP
ADC2INA0
ADC2INA2
ADC2INA3
ADC2INA4
ADC2INA6
ADC2INA7
ADC2INB0
ADC2INB3
ADC2INB4
ADC2INB7
VREGS
DEBUG
RESETS
CLOCKS
NMI
GPIO
MUX
4
AIO_MUX2
10
Figure 2-13. GPIOs and Other Pins
66
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
www.ti.com
SPRS742D –JUNE 2011–REVISED AUGUST 2012
M3 AHB BUS
M3 APB BUS
BUS BRIDGE
XCLKIN
XCLKIN
CAN
USB
PLL
UART
(5)
SSI
(4)
I2C
(2)
USB
EPI
EMAC
(2)
M3
M3
uDMA
CPU
M3
NMI
M3
EXT
NMI
INTERRUPTS
M3 PERIPHERAL SIGNAL ROUTING
NVIC
M3 MUX A
8
M3 MUX B
M3 MUX D
8
M3 MUX E
8
M3 MUX F
7
M3 MUX G
7
M3 MUX H
8
M3 MUX J
8
M3 MUX C
XCLKIN
GPIO
8
4
(H:A)
IRQ
PIN - LEVEL MUX
66
(TERMINALS GPIO 39 AND GPIO 44 ARE
NOT PINNED OUT ON THIS DEVICE)
GPTRIP
(12:1)
32
30
4
C28 MUX A
C28 MUX B
C28 MUX C
GPI (63:0) MINUS
GPI 39 AND GPI 44
(NOT PINNED OUT)
LPM
WAKEUP
C28 PERIPHERAL SIGNAL ROUTING
LPM
WAKE
C28x
DMA
C28x
CPU
EQEP
(3)
ECAP
(6)
EPWM
(9)
XINT
(3)
McBSP
SCI
SPI
I2C
GPTRIP (12:7)
GPTRIP (12:1)
GPTRIP (6:4)
C28 CPU BUS
C28 DMA BUS
Figure 2-14. GPIO_MUX1 Block
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
PERIPHERALS 1-15 REPRESENT A SET OF UP TO
BLUE REGISTER SET A
REPRESENTS 8 OF 66 GPIOs.
REMAINING 58 GPIOs ARE
CONTROLLED BY SIMILAR
REGISTER SETS B, C, D, E, F,
I, J, H
TO/FROM M3 PERIPH 1-11
TO/FROM M3 PERIPH 12-15
M3 CLOCKS
A-H INTR REQUESTS TO M3
15 M3 PERIPHERALS SPECIFIC TO ONE I/O PIN
GPIO63 XCLKIN
ONLY
GPIO (A)
IRQ
GPIOPCTL REG
PRIMARY
ALT
M3 REG SET A
M3 REG SET A
GPIOAMSEL REG
GPIOIS REG
GPIOIBE REG
GPIOIEV REG
GPIOIM REG
GPIORIS REG
GPIOMIS REG
GPIOICR REG
GREY LOGIC IS SPECIFIC TO
ONE DEVICE I/O PIN
M3 REG SET A
PRIMARY
AT RESET
GPIOAPSEL REG
(USB ANALOG SIGNALS)
M3 REG SET A
ENB
GPIODATA REG
GPIODIR REG
GPIOPUR REG
M3 REG SET A
GPIOODR REG
GPIOCSEL REG
GPIODEN REG
GPIOAFSEL REG
GPIOLOCK REG
GPIOCR REG
PULL-UP
DISABLED
ON RESET
M3 REG SET A
NORMAL
AT RESET
SELECT M3
AT RESET
I/O DISABLED
AT RESET
GPIO MODE
AT RESET
‘1’
PULL UP
INPUT
(4 PINS ONLY)
ANALOG USB
SIGNALS
‘0’
(M3 GPIO)
ONE OF 66
OUTPUT
GPIO_MUX1 PINS
OUTPUT
DISABLED
OPEN
DRAIN
LOGIC
GPIOAMSEL REG
OE
OE
AFTER RESET
OE
‘1’
ASYNC INPUT
ORANGE LOGIC SHOWS
USB ANALOG FUNCTIONS
(APPLIES TO 4 PINS ONLY)
OE
XRS
SYNC INPUT
SYNC
C28 REG SET A
GPACTRL REG
QUAL
GREEN REGISTER SET A
SHOWN REPRESENTS 32
OF 66 GPIOs. THE
(C28 GPIO)
C28SYSCLK
C28 REG SET A
6 SAMPLES
3 SAMPLES
REMAINING 34 GPIOs ARE
CONTROLLED BY SIMILAR
REGISTER SETS B AND C
GPASET REG
GPACLEAR REG
GPATOGGLE REG
GPADIR REG
GPASEL1 REG
GPASEL2 REG
OUTPUTS
SYNC INPUT
AT RESET
GPIO
SEL(1:0)
C28 REG SET A
AT RESET
EACH I/O PIN HAS A
DEDICATED PAIR OF
BITS FOR MUX SELECT
GPADAT REG
GPAMUX1 REG
GPAMUX2 REG
EACH I/O PIN HAS A
DEDICATED PAIR OF
BITS FOR MUX SELECT
SEL(1:0)
SEL(1:0)
INPUTS
N/C AT RESET
TO C28x CPU WAKE-UP FROM
A LOW POWER MODE
C28 REG SET A
N/C
GPTRIP1SEL REG
…
GPTRIP12SEL REG
PERIPHERALS 1-3 REPRESENT A SET OF UP TO
THREE C28 PERIPHERALS SPECIFIC TO ONE I/O PIN
GPI (63:0) MINUS
GPI 39 AND GPI 64
GPTRIP (12:1)
TO XINT, ECAP, EPWM
FROM C28 PERIPH 1-3
TO C28 PERIPH 1-3
Figure 2-15. GPIO_MUX1 Pin Mapping Through Register Set A
68
Device Overview
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
www.ti.com
SPRS742D –JUNE 2011–REVISED AUGUST 2012
For each of the 8 pins in set A of the Cortex™-M3 GPIO registers, register GPIOPCTL selects between
1 of 11 possible primary Cortex™-M3 peripheral signals, or 1 of 4 possible alternate peripheral signals.
Register GPIOAPSEL then picks one output to propagate further along the muxing chain towards a given
pin. The input takes the reverse path. See Table 2-27 and Table 2-28 for the mapping of Cortex™-M3
peripheral signals to GPIO_MUX1 pins.
Similarly, on the C28x side, GPAMUX1 and GPAMUX2 registers select 1 of 4 possible C28x peripheral
signals for each of 32 pins of set A. The selected C28x peripheral output then propagates further along
the muxing chain towards a given pin. The input takes the reverse path. See Table 2-29 for the mapping
of C28x peripheral signals to GPIO_MUX1 pins.
In addition to passing mostly digital signals, four GPIO_MUX1 pins can also be assigned to analog
signals. The GPIO Analog Mode Select (GPIOAMSEL) Register is used to assign four pins to analog USB
signals. PF6_GPIO38 becomes USB0VBUS, PG2_GPIO42 becomes USB0DM, PG5_GPIO45 becomes
USB0DP, and PG6_GPIO46 becomes USB0ID. When analog mode is selected, these four pins are not
available for digital GPIO_MUX1 options as described above.
Another special case is the External Oscillator Input signal (XCLKIN). This signal, available through pin
PJ7_GPIO63, is directly tied to USBPLLCLK (clock input to USB PLL) and two CAN modules. XCLKIN is
always available at these modules where it can be selected through local registers.
NOTE
For GPIO_MUX1 pins PF6_GPIO38 and PG6_GPIO46, only the corresponding USB function
is available on silicon revision 0 devices (GPIO and other functions listed in Table 3-1 are not
available).
Copyright © 2011–2012, Texas Instruments Incorporated
Device Overview
69
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
Table 2-27. GPIO_MUX1 Pin Assignments (M3 Primary Modes)(1)
Analog
Mode
(USB Pins)
M3
Primary
Mode 1
M3
Primary
Mode 2
M3
Primary
Mode 3
M3
Primary
Mode 4
M3
Primary
Mode 5
M3
Primary
Mode 6
M3
Primary
Mode 7
M3
Primary
Mode 8
M3
Primary
Mode 9
M3
Primary
Mode 10
M3
Primary
Mode 11
Device
Pin Name
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
PA0_GPIO0
PA1_GPIO1
PA2_GPIO2
PA3_GPIO3
PA4_GPIO4
PA5_GPIO5
PA6_GPIO6
PA7_GPIO7
PB0_GPIO8
PB1_GPIO9
PB2_GPIO10
PB3_GPIO11
PB4_GPIO12
PB5_GPIO13
PB6_GPIO14
PB7_GPIO15
PD0_GPIO16
PD1_GPIO17
PD2_GPIO18
PD3_GPIO19
PD4_GPIO20
PD5_GPIO21
PD6_GPIO22
PD7_GPIO23
PE0_GPIO24
PE1_GPIO25
PE2_GPIO26
PE3_GPIO27
PE4_GPIO28
PE5_GPIO29
PE6_GPIO30
PE7_GPIO31
U0RX
U0TX
SSI0CLK
SSI0FSS
SSI0RX
SSI0TX
I2C1SCL
I2C1SDA
CCP0
CCP2
I2C0SCL
I2C0SDA
–
–
–
–
–
–
–
I2C1SCL
U1RX
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
I2C1SDA
U1TX
–
–
MMI_TXD2
–
–
–
–
–
–
–
–
MMI_TXD1
–
–
–
–
–
–
–
–
MMI_TXD0
–
CAN0RX
–
–
–
–
–
–
MMI_RXDV
–
CAN0TX
–
–
–
–
–
CCP1
MMI_RXCK
–
–
CAN0RX
–
USB0EPEN
U1CTS
–
CCP4
MMI_RXER
–
–
CAN0TX
CCP3
USB0PFLT
U1DCD
–
–
–
–
U1RX
–
–
–
–
–
–
–
CCP1
U1TX
–
–
–
USB0EPEN
USB0PFLT
EPI0S23
EPI0S22
EPI0S37(2)
EPI0S36(2)
–
–
–
–
–
CCP3
CCP0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
U2RX
CAN0RX
–
U1RX
–
–
–
CCP5
CCP7
–
CCP6
CCP0
CAN0TX
CCP2
U1TX
–
–
CCP1
–
–
–
–
CCP5
–
–
–
–
NMI
–
–
MII_RXD1
–
–
PWM0
PWM1
U1RX
U1TX
CCP0
CCP2
Fault0
IDX0
CAN0RX
CAN0TX
CCP6
CCP7
CCP3
CCP4
–
–
U2RX
U1RX
CCP6
MII_RXDV
U1CTS
–
–
U2TX
U1TX
CCP7
MII_TXER
–
U1DCD
CCP2
–
CCP5
–
–
–
EPI0S20
EPI0S21
–
–
–
–
CCP0
–
–
–
–
–
–
MII_TXD3
–
–
–
U1RI
EPI0S19
–
MII_TXD2
–
–
–
–
U2RX
EPI0S28
–
MII_TXD1
–
–
–
–
U2TX
EPI0S29
–
CCP1
MII_TXD0
–
–
–
–
–
U1DTR
EPI0S30
PWM4
PWM5
CCP4
CCP1
CCP3
CCP5
–
SSI1CLK
SSI1FSS
SSI1RX
SSI1TX
–
CCP3
–
–
–
EPI0S8
EPI0S9
EPI0S24
EPI0S25
EPI0S34(2)
EPI0S35(2)
–
USB0PFLT
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
CCP2
CCP6
CCP2
CCP7
U2TX
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
CCP2
MII_RXD0
–
–
–
–
–
–
–
–
–
–
U1CTS
U1DCD
–
–
–
–
(1) Blank fields represent Reserved functions.
(2) This muxing option is only available on silicon Revision A devices; this muxing option is not available on silicon Revision 0 devices.
70
Device Overview
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
www.ti.com
SPRS742D –JUNE 2011–REVISED AUGUST 2012
Table 2-27. GPIO_MUX1 Pin Assignments (M3 Primary Modes)(1) (continued)
Analog
Mode
(USB Pins)
M3
Primary
Mode 1
M3
Primary
Mode 2
M3
Primary
Mode 3
M3
Primary
Mode 4
M3
Primary
Mode 5
M3
Primary
Mode 6
M3
Primary
Mode 7
M3
Primary
Mode 8
M3
Primary
Mode 9
M3
Primary
Mode 10
M3
Primary
Mode 11
Device
Pin Name
–
PF0_GPIO32
PF1_GPIO33
PF2_GPIO34
PF3_GPIO35
PF4_GPIO36
PF5_GPIO37
PF6_GPIO38
CAN1RX
CAN1TX
–
–
–
–
–
–
–
–
–
MII_RXCK
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
U1DSR
U1RTS
SSI1CLK
SSI1FSS
SSI1RX
SSI1TX
–
–
–
–
–
–
–
–
–
–
–
MII_RXER
–
CCP3
EPI0S32(2)
EPI0S33(2)
EPI0S12
EPI0S15
EPI0S38(2)
–
MII_PHYINTR
MII_MDC
MII_MDIO
MII_RXD3
MII_RXD2
–
–
–
–
–
–
–
–
–
–
CCP0
CCP2
CCP1
–
–
–
USB0VBUS
U1RTS
PF7_GPIO39
(no pin)
–
–
–
–
–
–
–
–
–
–
–
–
–
PG0_GPIO40
PG1_GPIO41
PG2_GPIO42
PG3_GPIO43
U2RX
U2TX
–
–
–
–
–
I2C1SCL
I2C1SDA
MII_COL
MII_CRS
–
–
–
–
–
–
–
–
–
–
–
–
USB0EPEN
EPI0S13
EPI0S14
EPI0S39(2)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
USB0DM
–
–
–
–
–
PG4_GPIO44
(no pin)
–
–
–
–
–
–
–
–
–
–
–
–
EPI0S40(2)
EPI0S41(2)
CCP5
USB0DP
PG5_GPIO45
PG6_GPIO46
PG7_GPIO47
PH0_GPIO48
PH1_GPIO49
PH2_GPIO50
PH3_GPIO51
PH4_GPIO52
PH5_GPIO53
PH6_GPIO54
PH7_GPIO55
PJ0_GPIO56
PJ1_GPIO57
PJ2_GPIO58
PJ3_GPIO59
PJ4_GPIO60
PJ5_GPIO61
PJ6_GPIO62
CCP5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MII_TXEN
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
U1DTR
–
USB0ID
–
MII_TXCK
–
U1RI
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MII_TXER
–
EPI0S31
–
–
–
CCP6
MII_PHYRST
–
EPI0S6
–
–
CCP7
–
–
EPI0S7
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
EPI0S1
MII_TXD3
MII_TXD2
MII_TXD1
MII_TXD0
MII_RXDV
–
–
–
–
USB0EPEN
EPI0S0
–
–
–
USB0PFLT
EPI0S10
EPI0S11
EPI0S26
EPI0S27
EPI0S16
EPI0S17
EPI0S18
EPI0S19
EPI0S28
EPI0S29
EPI0S30
–
SSI1CLK
–
–
–
–
–
–
–
–
–
–
–
–
SSI1FSS
–
–
–
SSI1RX
MII_RXCK
SSI1TX
MII_RXER
–
–
I2C1SCL
–
–
–
–
–
–
USB0PFLT
CCP0
–
I2C1SDA
–
–
–
–
–
–
U1CTS
U1DCD
U1DSR
U1RTS
CCP6
CCP4
CCP2
CCP1
PJ7_GPIO63/
XCLKIN
–
–
–
–
–
–
–
–
–
U1DTR
CCP0
–
Copyright © 2011–2012, Texas Instruments Incorporated
Device Overview
71
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
Table 2-27. GPIO_MUX1 Pin Assignments (M3 Primary Modes)(1) (continued)
Analog
Mode
(USB Pins)
M3
Primary
Mode 1
M3
Primary
Mode 2
M3
Primary
Mode 3
M3
Primary
Mode 4
M3
Primary
Mode 5
M3
Primary
Mode 6
M3
Primary
Mode 7
M3
Primary
Mode 8
M3
Primary
Mode 9
M3
Primary
Mode 10
M3
Primary
Mode 11
Device
Pin Name
PC0_GPIO64
(no pin)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
PC1_GPIO65
(no pin)
PC2_GPIO66
(no pin)
PC3_GPIO67
(no pin)
–
–
–
–
PC4_GPIO68
PC5_GPIO69
PC6_GPIO70
PC7_GPIO71
CCP5
CCP1
CCP3
CCP4
–
–
–
–
MII_TXD3
–
–
CCP2
CCP3
U1RX
U1TX
CCP4
USB0EPEN
CCP0
–
EPI0S2
EPI0S3
EPI0S4
EPI0S5
CCP1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
USB0PFLT
–
CCP0
USB0PFLT
72
Device Overview
Copyright © 2011–2012, Texas Instruments Incorporated
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
www.ti.com
SPRS742D –JUNE 2011–REVISED AUGUST 2012
Table 2-28. GPIO_MUX1 Pin Assignments (M3 Alternate Modes)(1)
M3
Alternate
Mode 12
M3
Alternate
Mode 13
M3
Alternate
Mode 14
M3
Alternate
Mode 15
Analog Mode
(USB Pins)
Device Pin Name
–
PA0_GPIO0
PA1_GPIO1
PA2_GPIO2
PA3_GPIO3
PA4_GPIO4
PA5_GPIO5
PA6_GPIO6
PA7_GPIO7
PB0_GPIO8
PB1_GPIO9
PB2_GPIO10
PB3_GPIO11
PB4_GPIO12
PB5_GPIO13
PB6_GPIO14
PB7_GPIO15
PD0_GPIO16
PD1_GPIO17
PD2_GPIO18
PD3_GPIO19
PD4_GPIO20
PD5_GPIO21
PD6_GPIO22
PD7_GPIO23
PE0_GPIO24
PE1_GPIO25
PE2_GPIO26
PE3_GPIO27
PE4_GPIO28
PE5_GPIO29
PE6_GPIO30
PE7_GPIO31
PF0_GPIO32
PF1_GPIO33
PF2_GPIO34
PF3_GPIO35
PF4_GPIO36
PF5_GPIO37
PF6_GPIO38
–
–
–
–
SSI1FSS
–
–
–
–
–
–
–
–
–
U1CTS
U1DCD
U1DSR
U1RTS
U1DTR
U1RI
–
–
SSI1CLK
–
–
–
–
–
–
–
–
–
MII_TXD3
–
–
–
MII_RXD1
–
–
–
–
SSI2TX
SSI2RX
SSI2CLK
SSI2FSS
–
CAN1TX
–
U4TX
–
–
–
–
–
CAN1RX
U1RX
CAN1TX
CAN1RX
U1TX
U4RX
–
–
–
–
–
SSI1TX
SSI1RX
SSI1CLK
SSI1FSS
USB0EPEN
USB0PFLT
CAN0RX
CAN0TX
CAN1TX
CAN1RX
U1TX
U1RX
SSI1TX
SSI1RX
SSI1CLK
SSI1FSS
USB0EPEN
USB0PFLT
–
–
–
–
–
MII_CRS
I2C0SDA
I2C0SCL
SSI0TX
SSI0RX
SSI0CLK
SSI0FSS
–
–
–
U1RX
CAN1TX
CAN1RX
U1TX
–
MII_RXD2
–
MII_COL
–
–
–
–
U1RX
U3TX
–
–
–
–
–
U3RX
I2C1SDA
I2C1SCL
CAN0RX
CAN0TX
U2RX
U2TX
–
–
–
–
–
–
–
–
SSI3TX
SSI3RX
SSI3CLK
SSI3FSS
U0RX
U0TX
CAN0RX
CAN0TX
I2C0SDA
I2C0SCL
–
–
–
–
–
–
–
–
–
EPI0S38(2)
–
MII_TXER
–
–
MII_MDIO
–
–
MII_RXD3
–
–
–
–
–
–
–
–
–
–
TRACED2
TRACED3
TRACECLK
TRACED0
–
–
–
–
–
XCLKOUT
–
–
U0TX
U0RX
–
–
–
–
–
MII_TXEN
–
USB0VBUS
–
–
PF7_GPIO39
(no pin)
–
–
–
–
–
(1) Blank fields represent Reserved functions.
(2) This muxing option is only available on silicon Revision A devices; this muxing option is not available on silicon Revision 0 devices.
Copyright © 2011–2012, Texas Instruments Incorporated
Device Overview
73
Submit Documentation Feedback
F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
Table 2-28. GPIO_MUX1 Pin Assignments (M3 Alternate Modes)(1) (continued)
M3
Alternate
Mode 12
M3
Alternate
Mode 13
M3
Alternate
Mode 14
M3
Alternate
Mode 15
Analog Mode
(USB Pins)
Device Pin Name
–
PG0_GPIO40
PG1_GPIO41
PG2_GPIO42
PG3_GPIO43
MII_RXD2
MII_RXD1
–
U4RX
U4TX
–
–
MII_TXCK
–
USB0DM
–
–
–
MII_TXER
–
–
MII_RXDV
–
TRACED1
PG4_GPIO44
(no pin)
–
–
–
–
–
USB0DP
PG5_GPIO45
PG6_GPIO46
PG7_GPIO47
PH0_GPIO48
PH1_GPIO49
PH2_GPIO50
PH3_GPIO51
PH4_GPIO52
PH5_GPIO53
PH6_GPIO54
PH7_GPIO55
PJ0_GPIO56
PJ1_GPIO57
PJ2_GPIO58
PJ3_GPIO59
PJ4_GPIO60
PJ5_GPIO61
PJ6_GPIO62
–
–
–
–
USB0ID
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MII_CRS
MII_TXD3
MII_TXD2
MII_TXD1
MII_TXD0
MII_COL
MII_PHYRST
MII_PHYINTR
MII_MDC
MII_MDIO
MII_RXD3
MII_RXD2
MII_RXD1
MII_RXD0
MII_RXDV
MII_RXER
–
MII_RXD0
–
SSI3TX
SSI3RX
SSI3CLK
SSI3FSS
U3TX
–
–
–
–
–
–
–
–
U3RX
–
MII_TXEN
MII_TXCK
–
SSI0TX
SSI0RX
SSI0CLK
SSI0FSS
SSI0CLK
SSI0FSS
SSI1CLK
SSI1FSS
U2RX
–
–
–
MII_RXDV
MII_RXCK
MII_MDC
MII_COL
MII_CRS
MII_PHYINTR
–
U0TX
U0RX
–
–
–
PJ7_GPIO63/
XCLKIN
–
–
–
–
–
MII_PHYRST
U2TX
–
–
–
–
–
MII_RXCK
PC0_GPIO64
(no pin)
–
–
–
–
–
–
–
–
–
–
–
–
PC1_GPIO65
(no pin)
PC2_GPIO66
(no pin)
PC3_GPIO67
(no pin)
–
–
–
–
PC4_GPIO68
PC5_GPIO69
PC6_GPIO70
PC7_GPIO71
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
74
Device Overview
Copyright © 2011–2012, Texas Instruments Incorporated
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
www.ti.com
SPRS742D –JUNE 2011–REVISED AUGUST 2012
Table 2-29. GPIO_MUX1 Pin Assignments (C28x Peripheral Modes)(1)
C28x
Peripheral
Mode 0
C28x
Peripheral
C28x
Peripheral
Mode 2
C28x
Peripheral
Mode 3
Analog Mode
(USB Pins)
Device Pin Name
Mode 1
EPWM1A
EPWM1B
EPWM2A
EPWM2B
EPWM3A
EPWM3B
EPWM4A
EPWM4B
EPWM5A
EPWM5B
EPWM6A
EPWM6B
EPWM7A
EPWM7B
EPWM8A
EPWM8B
SPISIMOA
SPISOMIA
SPICLKA
SPISTEA
EQEP1A
EQEP1B
EQEP1S
EQEP1I
ECAP1
–
PA0_GPIO0
PA1_GPIO1
PA2_GPIO2
PA3_GPIO3
PA4_GPIO4
PA5_GPIO5
PA6_GPIO6
PA7_GPIO7
PB0_GPIO8
PB1_GPIO9
PB2_GPIO10
PB3_GPIO11
PB4_GPIO12
PB5_GPIO13
PB6_GPIO14
PB7_GPIO15
PD0_GPIO16
PD1_GPIO17
PD2_GPIO18
PD3_GPIO19
PD4_GPIO20
PD5_GPIO21
PD6_GPIO22
PD7_GPIO23
PE0_GPIO24
PE1_GPIO25
PE2_GPIO26
PE3_GPIO27
PE4_GPIO28
PE5_GPIO29
PE6_GPIO30
PE7_GPIO31
PF0_GPIO32
PF1_GPIO33
PF2_GPIO34
PF3_GPIO35
PF4_GPIO36
PF5_GPIO37
PF6_GPIO38
GPIO0
–
–
–
GPIO1
ECAP6
–
–
GPIO2
–
–
–
GPIO3
ECAP5
–
–
GPIO4
–
–
–
GPIO5
MFSRA
ECAP1
–
GPIO6
–
EPWMSYNCO
–
GPIO7
MCLKRA
ECAP2
–
GPIO8
–
ADCSOCAO
–
GPIO9
–
ECAP3
–
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
–
ADCSOCBO
–
–
ECAP4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MDXA
–
–
MDRA
–
–
MCLKXA
–
–
MFSXA
–
–
EQEP2A
–
–
ECAP2
EQEP2B
–
–
ECAP3
EQEP2I
–
–
ECAP4
EQEP2S
–
–
SCIRXDA
SCITXDA
–
–
–
–
–
–
–
–
EPWM9A
–
–
–
EPWM9B
–
I2CASDA
I2CASCL
ECAP1
SCIRXDA
ADCSOCAO
–
EPWMSYNCO
ADCSOCBO
–
SCIRXDA
XCLKOUT
–
SCITXDA
SCIRXDA
ECAP2
–
–
–
–
–
–
–
–
–
–
USB0VBUS
–
PF7_GPIO39
(no pin)
–
–
–
–
–
(1) Blank fields represent Reserved functions.
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
Table 2-29. GPIO_MUX1 Pin Assignments (C28x Peripheral Modes)(1) (continued)
C28x
Peripheral
Mode 0
C28x
Peripheral
Mode 1
C28x
Peripheral
Mode 2
C28x
Peripheral
Mode 3
Analog Mode
(USB Pins)
Device Pin Name
–
PG0_GPIO40
PG1_GPIO41
PG2_GPIO42
PG3_GPIO43
GPIO40
GPIO41
GPIO42
GPIO43
–
–
–
–
–
–
–
–
–
–
–
–
–
USB0DM
–
PG4_GPIO44
(no pin)
–
–
–
–
–
USB0DP
PG5_GPIO45
PG6_GPIO46
PG7_GPIO47
PH0_GPIO48
PH1_GPIO49
PH2_GPIO50
PH3_GPIO51
PH4_GPIO52
PH5_GPIO53
PH6_GPIO54
PH7_GPIO55
PJ0_GPIO56
PJ1_GPIO57
PJ2_GPIO58
PJ3_GPIO59
PJ4_GPIO60
PJ5_GPIO61
PJ6_GPIO62
GPIO45
GPIO46
GPIO47
GPIO48
GPIO49
GPIO50
GPIO51
GPIO52
GPIO53
GPIO54
GPIO55
GPIO56
GPIO57
GPIO58
GPIO59
GPIO60
GPIO61
GPIO62
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
USB0ID
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ECAP5
ECAP6
EQEP1A
EQEP1B
EQEP1S
EQEP1I
SPISIMOA
SPISOMIA
SPICLKA
SPISTEA
MCLKRA
MFSRA
–
–
–
–
–
–
–
EQEP3A
EQEP3B
EQEP3S
EQEP3I
EPWM7A
EPWM7B
EPWM8A
EPWM8B
EPWM9A
–
–
PJ7_GPIO63/
XCLKIN
–
–
–
–
–
GPIO63
–
–
–
–
–
–
–
–
–
–
EPWM9B
PC0_GPIO64
(no pin)
–
–
–
–
–
–
–
–
PC1_GPIO65
(no pin)
PC2_GPIO66
(no pin)
PC3_GPIO67
(no pin)
–
–
–
–
PC4_GPIO68
PC5_GPIO69
PC6_GPIO70
PC7_GPIO71
GPIO68
GPIO69
GPIO70
GPIO71
–
–
–
–
–
–
–
–
–
–
–
–
76
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
www.ti.com
SPRS742D –JUNE 2011–REVISED AUGUST 2012
2.16.2 GPIO_MUX2
The eight pins of the GPIO_MUX2 block can be selectively mapped to eight General-Purpose Inputs, eight
General-Purpose Outputs, or six COMPOUT outputs from the Analog Comparator peripheral. Each
GPIO_MUX2 pin can have a pullup enabled or disabled. On reset, all pins of the GPIO_MUX2 block are
configured as analog inputs, and the GPIO function is disabled. The GPIO_MUX2 block is programmed
through a separate set of registers from those used to program GPIO_MUX1.
The multiple registers responsible for configuring the GPIO_MUX2 pins are organized in register set G.
They are accessible by the C28x CPU only. The middle portion of Figure 2-16 shows set G of Control
Subsystem registers, plus muxing logic for the associated eight GPIO pins. The GPGMUX1 register
selects one of six possible digital output signals from analog comparators, or one of eight general-purpose
GPIO digital outputs. The GPGPUD register disables pullups for the GPIO_MUX2 pins when a
corresponding bit of that register is set to “1”. Other registers of set G allow reading and writing of the
eight GPIO bits, as well as setting the direction for each of the bits (read or write). See Table 2-30 for the
mapping of comparator outputs and GPIO to the eight pins of GPIO_MUX2.
Peripheral Modes 0, 1, 2, and 3 are chosen by setting selected bit pairs of GPGMUX1 register to “00”,
“01”, “10”, and “11”, respectively. For example, setting bits 5–4 of the GPGMUX1 register to “00”
(Peripheral Mode 0) assigns pin GPIO130 to internal signal GPIO130 (digital GPIO). Setting bits 5–4 of
the GPGMUX1 register to “11” (Peripheral Mode 3) assigns pin GPIO130 to internal signal COMP6OUT
coming from Analog Comparator 6. Peripheral Modes 1 and 2 are reserved and are not currently
available.
Table 2-30. GPIO_MUX2 Pin Assignments (C28x Peripheral Modes)(1)
C28x
Peripheral
Mode 0
C28x
Peripheral
Mode 1
C28x
Peripheral
Mode 2
C28x
Peripheral
Mode 3
Device Pin Name
GPIO128
GPIO129
GPIO130
GPIO131
GPIO132
GPIO133
GPIO134
GPIO135
GPIO128
GPIO129
GPIO130
GPIO131
GPIO132
GPIO133
GPIO134
GPIO135
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
COMP1OUT
COMP6OUT
COMP2OUT
COMP3OUT
COMP4OUT
–
COMP5OUT
(1) Blank fields represent Reserved functions.
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
ADC1INA0 ADC1INB0
ADC1INA2 ADC1INB3
ADC1INA3 ADC1INB4
ADC1INA4 ADC1INB7
ADC1INA6
ADC
1
ADC1INA7
ONE OF 10
AIO_MUX1
PINS
AIO2
AIO4
AIO6
AIO12
AIO_MUX1
AIOMUX1 REG
AIODIR REG
AIOSET REG
AIOCLEAR REG
AIOTOGGLE REG
AIODIR REG
COMPA1
COMPA2
COMPA3
AIODAT REG
COMPB2
ANALOG
COMMON
INTERFACE
BUS
COMPOUT1
COMPOUT2
COMPOUT3
COMPOUT4
COMPOUT5
COMPOUT6
6
COMPARATOR
+ DAC UNITS
DIS
GPGPUDREG
‘1’
PULL-UP
COMPA4
COMPA5
COMPA6
DISABLED
ON RESET
C28
CPU
BUS
ANALOG BUS
C28x
CPU
GPIO128
GPIO129
GPIO130
GPIO131
GPIO132
GPIO133
GPIO134
GPIO135
GPIO_MUX2
COMPB5
PULL UP
GPGMUX1 REG
GPGSET REG
GPGCLEAR REG
GPGTOGGLE REG
GPGDIR REG
GPGDIR REG
ONE OF 8
GPIO_MUX2
PINS
GPGDAT REG
ADC2INA0 ADC2INB0
ADC2INA2 ADC2INB3
ADC2INA3 ADC2INB4
ADC2INA4 ADC2INB7
ADC2INA6
ADC
2
ADC2INA7
ONE OF 10
AIO_MUX2
PINS
AIO18
AIO20
AIO22
AIO28
AIO_MUX2
AIOSET REG
AIOCLEAR REG
AIOTOGGLE REG
AIODIR REG
AIOMUX2 REG
AIODIR REG
AIODAT REG
Figure 2-16. Pin Muxing on AIO_MUX1, AIO_MUX2, and GPIO_MUX2
78
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
2.16.3 AIO_MUX1
The ten pins of AIO_MUX1 can be selectively mapped through a dedicated set of registers to 12 analog
inputs for ADC1 peripheral, six analog inputs for Comparator peripherals, four General-Purpose Inputs, or
four General-Purpose Outputs. Note that while AIO_MUX1 has been named after the analog signals
passing through it, the GPIOs (here called AIOs) are still digital, although with fewer features than those in
the GPIO_MUX1 and GPIO_MUX2 blocks—for example, they do not offer pullups. On reset, all pins of the
AIO_MUX1 block are configured as analog inputs and the GPIO function is disabled. The AIO_MUX1
block is programmed through a separate set of registers from those used to program AIO_MUX2.
The multiple registers responsible for configuring the AIO_MUX1 pins are accessible by the C28x CPU
only. The top portion of Figure 2-16 shows Control Subsystem registers and muxing logic for the
associated ten AIO pins. The AIOMUX1 register selects one of ten possible analog input signals or one of
four general-purpose AIO inputs. Other registers allow reading and writing of the four AIO bits, as well as
setting the direction for each of the bits (read or write). See Table 2-31 for the mapping of analog inputs
and AIOs to the ten pins of AIO_MUX1.
AIO Mode 0 is chosen by setting selected odd bits of the AIOMUX1 register to ‘0’. AIO Mode 1 is chosen
by setting selected odd bits of the AIOMUX1 register to ‘1’. For example, setting bit 5 of the AIOMUX1
register to ‘0’ assigns pin ADC1INA2 to internal signal AIO2 (digital GPIO). Setting bit 5 of the AIOMUX1
register to ‘1’ assigns pin ADC1INA2 to analog inputs ADC1INA2 or COMPA1 (only one should be
enabled at a time in the respective analog module). Currently, all even bits of the AIOMUX1 register are
“don’t cares”.
Table 2-31. AIO_MUX1 Pin Assignments (C28x AIO Modes)(1)(2)
Device Pin Name
ADC1INA0
ADC1INA2
ADC1INA3
ADC1INA4
ADC1INA6
ADC1INA7
ADC1INB0
ADC1INB3
ADC1INB4
ADC1INB7
C28x AIO Mode 0(3)
C28x AIO Mode 1(4)
ADC1INA0
–
AIO2
–
ADC1INA2, COMPA1
ADC1INA3
AIO4
AIO6
–
ADC1INA4, COMPA2
ADC1INA6, COMPA3
ADC1INA7
–
ADC1INB0
–
ADC1INB3
AIO12
–
ADC1INB4, COMPB2
ADC1INB7
(1) Blank fields represent Reserved functions.
(2) For each field with two pins (for example, ADC1INA2, COMPA1), only one pin should be enabled at a time; the other pin should be
disabled. Use registers inside the respective destination analog peripherals to enable or disable these inputs.
(3) AIO Mode 0 represents digital general-purpose inputs or outputs.
(4) AIO Mode 1 represents analog inputs for ADC1 or the Comparator module.
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
2.16.4 AIO_MUX2
The ten pins of AIO_MUX2 can be selectively mapped through a dedicated set of registers to 12 analog
inputs for ADC2 peripheral, six analog inputs for Comparator peripherals, four General-Purpose Inputs, or
four General-Purpose Outputs. Note that while AIO_MUX2 has been named after the analog signals
passing through it, the GPIOs (here called AIOs) are still digital, although with fewer features than those in
the GPIO_MUX1 and GPIO_MUX2 blocks—for example, they do not offer pullups. On reset, all pins of the
AIO_MUX2 block are configured as analog inputs and the GPIO function is disabled. The AIO_MUX2
block is programmed through a separate set of registers from those used to program AIO_MUX1.
The multiple registers responsible for configuring the AIO_MUX2 pins are accessible by the C28x CPU
only. The bottom portion of Figure 2-16 shows Control Subsystem registers and muxing logic for the
associated ten AIO pins. The AIOMUX2 register selects one of ten possible analog input signals or one of
four general-purpose AIO inputs. Other registers allow reading and writing of the four AIO bits, as well as
setting the direction for each of the bits (read or write). See Table 2-32 for the mapping of analog inputs
and AIOs to the ten pins of AIO_MUX2. Peripheral Modes 1 and 2 are currently not available.
AIO Mode 0 is chosen by setting selected odd bits of the AIOMUX2 register to ‘0’. AIO Mode 1 is chosen
by setting selected odd bits of the AIOMUX2 register to ‘1’. For example, setting bit 9 of the AIOMUX2
register to ‘0’ assigns pin ADC2INA4 to internal signal AIO20 (digital GPIO). Setting bit 9 of the AIOMUX2
register to ‘1’ assigns pin ADC2INA4 to analog inputs ADC2INA4 or COMPA5 (only one should be
enabled at a time in the respective analog module). Currently, all even bits of the AIOMUX2 register are
“don’t cares”.
Table 2-32. AIO_MUX2 Pin Assignments (C28x AIO Modes)(1)(2)
Device Pin Name
ADC2INA0
ADC2INA2
ADC2INA3
ADC2INA4
ADC2INA6
ADC2INA7
ADC2INB0
ADC2INB3
ADC2INB4
ADC2INB7
C28x AIO Mode 0(3)
C28x AIO Mode 1(4)
ADC2INA0
–
AIO18
ADC2INA2, COMPA4
ADC2INA3
–
AIO20
ADC2INA4, COMPA5
ADC2INA6, COMPA6
ADC2INA7
AIO22
–
–
ADC2INB0
–
AIO28
–
ADC2INB3
ADC2INB4, COMPB5
ADC2INB7
(1) Blank fields represent Reserved functions.
(2) For each field with two pins (for example, ADC2INA6, COMPA6), only one pin should be enabled at a time; the other pin should be
disabled. Use registers inside the respective destination analog peripherals to enable or disable these inputs.
(3) AIO Mode 0 represents digital general-purpose inputs or outputs.
(4) AIO Mode 1 represents analog inputs for ADC2 or the Comparator module.
80
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
2.17 Emulation/JTAG
Concerto devices have two types of emulation ports to support debug operations: the 7-pin TI JTAG port
and the 5-pin Cortex™-M3 Instrumentation Trace Macrocell (ITM) port. The 7-pin TI JTAG port can be
used to connect to debug tools via the TI 14-pin JTAG header or the TI 20-pin JTAG header. The 5-pin
Cortex™-M3 ITM port can only be accessed through the TI 20-pin JTAG header.
The JTAG port has seven dedicated pins: TRST, TMS, TDI, TDO, TCK, EMU0, and EMU1. The TRST
signal should always be pulled down via a 2.2-kΩ pulldown resistor on the board. EMU0 and EMU1
signals should be pulled up through a pair of pullups ranging from 2.2 kΩ to 4.7 kΩ (depending on the
drive strength of the debugger ports). The JTAG port is TI’s standard debug port.
The ITM port uses five GPIO pins that can be mapped to internal Cortex™-M3 ITM trace signals:
TRACE0, TRACE1, TRACE2, TRACE3, and TRACECLK. This port is typically used for advanced
software debug.
TI emulators, and those from other manufacturers, can connect to Concerto devices via TI’s 14-pin JTAG
header or 20-pin JTAG header. See Figure 2-17 to see how the 14-pin JTAG header connects to
Concerto’s JTAG port signals. Note that the 14-pin header does not support the ITM debug mode.
Figure 2-18 shows two possible ways to connect the 20-pin header to Concerto’s emulation pins. The left
side of the drawing shows all seven JTAG signals connecting to the 20-pin header similar to the way the
14-pin header was connected. Note that the JTAG EMU0 and EMU1 signals are mapped to the
corresponding terminals on the 20-pin header. In this mode, header terminals EMU2, EMU3, and EMU4
are left unconnected and the ITM trace mode is not available.
The right side of the drawing shows the same 20-pin header now connected to five ITM signals and five of
seven JTAG signals. Note that Concerto’s EMU0 and EMU1 signals are left unconnected in this mode;
thus, the emulation functions associated with these two signals are not available when debugging with
ITM trace.
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
CONCERTO F28M35x
85
TRST
2.2K
3.3V
1
3
5
7
9
87
2
4
nTRST
TDIS
KEY
TMS
TMS
88
TDI
PD
TDI
6
84
8
GND
GND
TDO
TDO
10
12
14
4.7K
4.7K
RTCK
TCK
11
13
89
GND
TCK
83
EMU1
EMU0
EMU0
86
EMU1
TI 14-PIN
JTAG HEADER
JTAG
PINS
GPIO PINS
81
NC
TRACED0
TRACED1
TRACECLK
TRACED2
TRACED3
PF3_GPIO35
PG3_GPIO43
PF2_GPIO34
PF0_GPIO32
PF1_GPIO33
78
82
NC
NC
NC
NC
104
103
ITM trace
from M3
PROCESSOR
Figure 2-17. Connecting to TI 14-Pin JTAG Emulator Header
82
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
www.ti.com
SPRS742D –JUNE 2011–REVISED AUGUST 2012
CONCERTO F28M35x
CONCERTO F28M35x
85
85
TRST
TRST
2.2K
2.2K
3.3V
3.3V
1
3
5
7
9
1
3
5
7
9
87
88
2
4
87
88
2
4
nTRST
TDIS
KEY
nTRST
TDIS
KEY
TMS
TMS
TMS
TDI
TMS
TDI
TDI
PD
TDI
PD
6
6
84
8
84
8
GND
GND
GND
EMU1
GND
GND
GND
GND
EMU1
GND
TDO
TDO
TDO
TDO
10
12
14
16
18
20
10
12
14
16
18
20
4.7K
4.7K
RTCK
TCK
4.7K
4.7K
RTCK
TCK
11
11
89
83
86
89
83
86
TCK
TCK
13
15
17
19
13
15
17
19
EMU0
RESETn
EMU2
EMU4
EMU0
RESETn
EMU2
EMU4
NC
NC
EMU0
EMU1
EMU0
EMU1
EMU3
GND
EMU3
GND
NC
NC
NC
JTAG
PINS
JTAG
PINS
TI 20-PIN
JTAG HEADER
TI 20-PIN
JTAG HEADER
GPIO PINS
GPIO PINS
81
78
81
78
NC
TRACED0
PF3_GPIO35
PG3_GPIO43
PF2_GPIO34
PF0_GPIO32
PF1_GPIO33
TRACED0
TRACED1
TRACECLK
TRACED2
TRACED3
PF3_GPIO35
PG3_GPIO43
PF2_GPIO34
PF0_GPIO32
PF1_GPIO33
NC
NC
NC
NC
TRACED1
TRACECLK
TRACED2
TRACED3
82
82
104
103
104
103
OPEN
OPEN
DRAIN
DRAIN
ITM trace
from M3
ITM trace
from M3
PROCESSOR
PROCESSOR
A LOW PULSE FROM THE EMULATOR CAN BE TIED
WITH OTHER RESET SOURCES TO RESET THE BOARD
A LOW PULSE FROM THE EMULATOR CAN BE TIED
WITH OTHER RESET SOURCES TO RESET THE BOARD
Figure 2-18. Connecting to TI 20-Pin JTAG Emulator Header
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
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2.18 Code Security Module (CSM)
The Code Security Module (CSM) is a security feature incorporated in Concerto™ devices. The CSM
prevents access and visibility to on-chip secure memories by unauthorized persons—that is, the CSM
prevents duplication and reverse-engineering of proprietary code. The word "secure" means that access to
on-chip secure memories is protected. The word "unsecure" means that access to on-chip secure memory
is not protected—that is, the contents of the memory could be read by any means (for example, by using a
debugging tool such as Code Composer Studio™).
2.18.1 Functional Description
The security module restricts the CPU access to on-chip secure memory without interrupting or stalling
CPU execution. When a read occurs to a protected memory location, the read returns a zero value and
CPU execution continues with the next instruction. This process, in effect, blocks read and write access to
various memories through the JTAG port or external peripherals. Security is defined with respect to the
access of on-chip secure memories and prevents unauthorized copying of proprietary code or data.
The zone is secure when CPU access to the on-chip secure memories associated with that zone is
restricted. When secure, two levels of protection are possible, depending on where the program counter is
currently pointing. If code is currently running from inside secure memory, only an access through JTAG is
blocked (that is, through the emulator). This process allows secure code to access secure data.
Conversely, if code is running from unsecure memory, all accesses to secure memories are blocked. User
code can dynamically jump in and out of secure memory, thereby allowing secure function calls from
unsecure memory. Similarly, interrupt service routines can be placed in secure memory, even if the main
program loop is run from unsecure memory.
The code security mechanism present in this device offers dual-zone security for the Cortex™-M3 code
and single-zone security for the C28x code. In case of dual-zone security on the master subsystem, the
different secure memories (RAMs and flash sectors) can be assigned to different security zones by
configuring the GRABRAM and GRABSECT registers associated with each zone. Flash Sector N and
Flash Sector A are dedicated to Zone1 and Zone2, respectively, and cannot be allocated to any other
zone by configuration. Similarly, flash sectors get assigned to different zones based on the setting in the
GRABSECT registers.
Security is provided by a CSM password of 128 bits of data (four 32-bit words) that is used to secure or
unsecure the zones. Each zone has its own 128-bit CSM password. The zone can be unsecured by
executing the password match flow (PMF).
The CSM password for each zone is stored in its dedicated flash sector. The password storage locations
in the flash sector store the CSM password. The password is selected by the system designer. If the
password locations of a zone have all 128 bits as ones, the zone is considered "unsecure". Since new
flash devices have erased flash (all ones), only a read of the password locations is required to bring any
zone into unsecure mode. If the password locations of a zone have all 128 bits as zeros, the zone is
considered "secure", regardless of the contents of the CSMKEY registers. The user should not use all
zeros as a password or reset the device during an erase of the flash. Resetting the device during an erase
routine can result in either an all-zero or unknown password. If a device is reset when the password
locations are all zeros, the device cannot be unlocked by the password match flow. Using a password of
all zeros will seriously limit the user’s ability to debug secure code or reprogram the flash.
NOTE
If a device is reset while the password locations of a zone contain all zeros or an unknown
value, that zone will be permanently locked unless a method to run the flash erase routine
from secure SARAM is embedded into the flash or OTP. Care must be taken when
implementing this procedure to avoid introducing a security hole.
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
2.19 µCRC Module
The µCRC module is part of the master subsystem. This module can be used by Cortex™-M3 software to
compute CRC on data and program, which are stored at memory locations that are addressable by
Cortex™-M3. On this device, the Cortex™-M3 Flash Bank and ROM are mapped to the code space that is
only accessed by the ICODE/DCODE bus of Cortex™-M3; and RAMs are mapped on the SRAM space
that is accessible by the SYSTEM bus. Hence, the µCRC module snoops both the DCODE and SYSTEM
buses to support CRC calculation for data and program.
2.19.1 Functional Description
The µCRC module snoops both the DCODE and SYSTEM buses to support CRC calculation for data and
program. To allow interrupts execution in between CRC calculations for a block of data and to discard the
Cortex™-M3 literal pool accesses in between executions of the program (which reads data for CRC
calculation), the Cortex™-M3 ROM, Flash, and RAMs are mapped to a mirrored memory location. The
µCRC module grabs data from the bus to calculate CRC only if the address of the read data belongs to
mirrored memory space. After grabbing, the µCRC module performs the CRC calculation on the grabbed
data and updates the µCRC Result Register (µCRCRES). This register can be read at any time to get the
calculated CRC for all the previous read data. The µCRC module only supports CRC calculation for byte
accesses. So, in order to calculate the CRC on a block of data, software must perform byte accesses to
all the data. For half-word and word accesses, the µCRC module discards the data and does not update
the µCRCRES register.
NOTE
If a read to a mirrored address space is thrown from the debugger (Code Composer Studio
or any other debug platform), the µCRC module ignores the read data and does not update
the CRC result for that particular read.
2.19.2 CRC Polynomials
The following are the CRC polynomials that are supported by the µCRC module:
•
•
•
•
CRC8 Polynomial = 0x07
CRC16 Polynomial-1 = 0x8005
CRC16 Polynomial-2 = 0x1021
CRC32 Polynomial = 0x04C11DB7
2.19.3 CRC Calculation Procedure
The software procedure for calculating CRC for a set of data that is stored in Cortex™-M3 addressable
memory space is as follows:
1. Save the current value of the µCRC Result Register (µCRCRES) into the stack to allow calculation of
CRC in nested interrupt
2. Clear the µCRC Result Register (µCRCRES) by setting the CLEAR field of the µCRC Control Register
(µCRCCONTROL) to "1"
3. Configure the µCRC polynomials (CRC8, CRC16-P1, CRC16-P2, or CRC32) in the µCRC
Configuration Register (µCRCCONFIG)
4. Read the data from memory locations for which CRC needs to be calculated using mirrored address
5. Read the µCRCRES register to get the calculated CRC value. Pop the last saved value of the CRC
from the stack and store this value into the µCRC Result Register (uCRCRES)
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
2.19.4 CRC Calculation for Data Stored In Secure Memory
This device has dual-zone security for the Cortex™-M3 subsystem. Since ZoneX (X → 1/2) software does
not have access to program/data in ZoneY (Y → 2/1), code running from ZoneX cannot calculate CRC on
data stored in ZoneY memory. Similarly, in the case of Exe-Only flash sectors, even though software is
running from same secure zone, the software cannot read the data stored in Exe-Only sectors. However,
hardware does allow CRC computation on data stored in Exe-Only flash sectors as long as the read
access for this data is initiated by code running from same secure zone. These reads are just dummy
reads and, in this case, read data only goes to the µCRC module, not to the CPU.
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
3 Device Pins
3.1 Pin Assignments
Figure 3-1 shows the 144-pin RFP PowerPAD™ Thermally Enhanced Thin Quad Flatpack (HTQFP) pin
assignments.
GPIO135/COMP5OUT(A)
GPIO134
GPIO133/COMP4OUT
GPIO132/COMP3OUT
VREG18EN
PG5_GPIO45
PG2_GPIO42
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
PG6_GPIO46
PF6_GPIO38
PD7_GPIO23
VDDIO
ADC1INB7
ADC1INB4
ADC1INB3
ADC1INB0
VDD12
PD4_GPIO20
PD5_GPIO21
PJ0_GPIO56
PJ1_GPIO57
VSSA1
VDDA1
ADC1VREFHI
ADC1INA0
ADC1INA2
ADC1INA3
ADC1INA4
ADC1INA6
ADC1INA7
ADC2INA7
ADC2INA6
PJ2_GPIO58
PJ3_GPIO59
VDDIO
VDD12
PJ4_GPIO60
PJ5_GPIO61
VDD12
VDDIO
PJ6_GPIO62
PG7_GPIO47
PF5_GPIO37
PG1_GPIO41
PG0_GPIO40
PF4_GPIO36
PH5_GPIO53
PH4_GPIO52
PE1_GPIO25
VDDIO
PE0_GPIO24
PH1_GPIO49
PH0_GPIO48
PC7_GPIO71
PC6_GPIO70
PC5_GPIO69
PC4_GPIO68
ADC2INA4
ADC2INA3
ADC2INA2
ADC2INA0
ADC2VREFHI
VDDA2
VSSA2
ADC2INB0
ADC2INB3
ADC2INB4
ADC2INB7
GPIO128
GPIO129/COMP1OUT
GPIO130/COMP6OUT
GPIO131/COMP2OUT
ARS
A. All I/Os, except for GPIO135, are glitch-free during power up and power down. See Section 2.11.
B. See Table 3-1, Terminal Functions, for the complete multiplexed signal names.
Figure 3-1. 144-Pin RFP PowerPAD™ HTQFP (Top View)
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
3.2 Terminal Functions
Table 3-1 describes the signals.
Table 3-1. Terminal Functions(1)
TERMINAL
PU
or
OUTPUT
BUFFER
STRENGTH
I/O/Z(2)
DESCRIPTION
RFP
PIN NO.
PD(3)
NAME
ADC 1 Reference Inputs, Analog Comparator Inputs, DAC Inputs, AIO Group 1
ADC1 External High Reference – used only when
in ADC external reference mode.
ADC1VREFHI
120
I
I
ADC1 External Low Reference – used only when
in ADC external reference mode.
ADC1VREFLO
see VSSA1
121
ADC1INA0
ADC1INA2
COMPA1
AIO2
I
ADC1 Group A, Channel 0 input
ADC1 Group A, Channel 2 input
Comparator Input A1
I
122
123
124
I
4 mA
I/O
Digital AIO2
ADC1INA3
ADC1INA4
COMPA2
AIO4
I
ADC1 Group A, Channel 3 input
ADC1 Group A, Channel 4 input
Comparator Input A2
I
I
4 mA
4 mA
I/O
Digital AIO4
ADC1INA6
COMPA3
AIO6
I
ADC1 Group A, Channel 6 input
Comparator Input A3
125
I
I/O
Digital AIO6
ADC1INA7
ADC1INB0
ADC1INB3
ADC1INB4
COMPB2
AIO12
126
117
116
I
ADC1 Group A, Channel 7 input
ADC1 Group B, Channel 0 input
ADC1 Group B, Channel 3 input
ADC1 Group B, Channel 4 input
Comparator Input B2
I
I
I
115
114
I
I/O
I
4 mA
Digital AIO12
ADC1INB7
ADC1 Group B, Channel 7 input
ADC 2 Reference Inputs, Analog Comparator Inputs, DAC Inputs, AIO Group 2
ADC2 External High Reference – used only when
in ADC external reference mode.
ADC2VREFHI
ADC2VREFLO
133
I
I
ADC2 External Low Reference – used only when
in ADC external reference mode.
see VSSA2
132
ADC2INA0
ADC2INA2
COMPA4
AIO18
I
ADC2 Group A, Channel 0 input
ADC2 Group A, Channel 2 input
Comparator Input A4
I
131
130
129
I
4 mA
I/O
Digital AIO18
ADC2INA3
ADC2INA4
COMPA5
AIO20
I
ADC2 Group A, Channel 3 input
ADC2 Group A, Channel 4 input
Comparator Input A5
I
I
4 mA
4 mA
I/O
Digital AIO20
ADC2INA6
COMPA6
AIO22
I
ADC2 Group A, Channel 6 input
Comparator Input A6
128
I
I/O
Digital AIO22
ADC2INA7
ADC2INB0
ADC2INB3
127
136
137
I
I
I
ADC2 Group A, Channel 7 input
ADC2 Group B, Channel 0 input
ADC2 Group B, Channel 3 input
88
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F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
Table 3-1. Terminal Functions(1) (continued)
TERMINAL
PU
or
OUTPUT
BUFFER
STRENGTH
I/O/Z(2)
DESCRIPTION
RFP
PIN NO.
PD(3)
NAME
ADC2INB4
COMPB5
AIO28
I
ADC2 Group B, Channel 4 input
Comparator Input B5
138
139
I
I/O
I
4 mA
Digital AIO28
ADC2INB7
ADC2 Group B, Channel 7 input
ADC Modules Analog Power and Ground
3.3-V Analog Module 1 Power Pin. Tie with
a 2.2-µF capacitor (typical) close to the pin.
VDDA1
VDDA2
VSSA1
VSSA2
119
134
118
135
3.3-V Analog Module 2 Power Pin. Tie with
a 2.2-µF capacitor (typical) close to the pin.
Analog ground for ADC1, ADC1VREFLO
,
COMP1–3, and DAC1–3
Analog ground for ADC2, ADC2VREFLO
COMP4–6, and DAC4–6
,
Analog Comparator Results (Digital) and GPIO Group 2 (C28x Access Only)
GPIO128
140
I/O
I/O
O
General-purpose input/output 128
PU
PU
4 mA
4 mA
GPIO129
General-purpose input/output 129
141
COMP1OUT
GPIO130
Compare result from Analog Comparator 1
General-purpose input/output 130
I/O
O
142
143
112
PU
PU
PU
4 mA
4 mA
8 mA
COMP6OUT
GPIO131
Compare result from Analog Comparator 6
General-purpose input/output 131
I/O
O
COMP2OUT
GPIO132
Compare result from Analog Comparator 2
General-purpose input/output 132
I/O
O
COMP3OUT
GPIO133
Compare result from Analog Comparator 3
General-purpose input/output 133
I/O
O
111
110
109
PU
PU
PU
4 mA
4 mA
8 mA
COMP4OUT
GPIO134
GPIO135(4)
Compare result from Analog Comparator 4
General-purpose input/output 134
I/O
I/O
O
General-purpose input/output 135
COMP5OUT
Compare result from Analog Comparator 5
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F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
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Table 3-1. Terminal Functions(1) (continued)
TERMINAL
PU
or
OUTPUT
BUFFER
STRENGTH
I/O/Z(2)
DESCRIPTION
RFP
PIN NO.
PD(3)
NAME
GPIO Group 1 and Peripheral Signals
PA0_GPIO0
I/O/Z
I
General-purpose input/output 0
UART-0 receive data
M_U0RX
M_I2C1SCL
M_U1RX
5
6
7
8
I/OD
I
I2C-1 clock open-drain bidirectional port
UART-1 receive data
PU
PU
PU
PU
4 mA
4 mA
4 mA
4 mA
C_EPWM1A
PA1_GPIO1
M_U0TX
O
Enhanced PWM-1 output A
General-purpose input/output 1
UART-0 transmit data
I/O/Z
O
M_I2C1SDA
M_U1TX
I/OD
O
I2C-1 data open-drain bidirectional port
UART-1 data transmit
M_SSI1FSS
C_EPWM1B
C_ECAP6
I/O
O
SSI-1 frame
Enhanced PWM-1 output B
Enhanced Capture-6 input/output
General-purpose input/output 2
SSI-0 clock
I/O
I/O/Z
I/O
O
PA2_GPIO2
M_SSI0CLK
M_MIITXD2
M_U1CTS
C_EPWM2A
PA3_GPIO3
M_SSI0FSS
M_MIITXD1
M_U1DCD
M_SSI1CLK
C_EPWM2B
C_ECAP5
EMAC MII transmit data bit 2
UART-1 clear-to-send modem status
Enhanced PWM-2 output A
General-purpose input/output 3
SSI-0 frame
I
O
I/O/Z
I/O
O
EMAC MII transmit data bit 1
UART-1 data carrier detect
SSI-1 clock
I
I/O
O
Enhanced PWM-2 output B
Enhanced Capture-5 input/output
General-purpose input/output 4
SSI-0 receive data
I/O
I/O/Z
I
PA4_GPIO4
M_SSI0RX
M_MIITXD0
M_CAN0RX
M_U1DSR
C_EPWM3A
PA5_GPIO5
M_SSI0TX
M_MIIRXDV
M_CAN0TX
M_U1RTS
C_EPWM3B
C_MFSRA
C_ECAP1
O
EMAC MII transmit data bit 0
CAN-0 receive data
9
PU
4 mA
I
I
UART-1 data set ready
O
Enhanced PWM-3 output A
General-purpose input/output 5
SSI-0 transmit data
I/O/Z
O
I
EMAC MII receive data valid
CAN-0 transmit data
O
12
PU
4 mA
O
UART-1 request-to-send
Enhanced PWM-3 output B
McBSP-A receive frame sync
Enhanced Capture-1 input/output
O
I
I/O
90
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
Table 3-1. Terminal Functions(1) (continued)
TERMINAL
PU
or
OUTPUT
BUFFER
STRENGTH
I/O/Z(2)
DESCRIPTION
RFP
PIN NO.
PD(3)
NAME
PA6_GPIO6
M_I2C1SCL
I/O/Z
I/OD
General-purpose input/output 6
I2C-1 clock open-drain bidirectional port
Capture/Compare/PWM-1
(General-purpose Timer)
M_CCP1
I/O
M_MIIRXCK
M_CAN0RX
I
I
EMAC MII receive clock
CAN-0 receive data
13
PU
4 mA
USB-0 external power enable
(optionally used in host mode)
M_USB0EPEN
O
M_U1CTS
M_U1DTR
C_EPWM4A
I
O
UART-1 clear-to-send modem status
UART-1 data terminal ready
O
Enhanced PWM-4 output A
C_EPWMSYNCO
PA7_GPIO7
O
Enhanced PWM-4 external sync pulse
General-purpose input/output 7
I2C-1 data open-drain bidirectional port
I/O/Z
I/OD
M_I2C1SDA
Capture/Compare/PWM-4
(General-purpose Timer)
M_CCP4
I/O
M_MIIRXER
M_CAN0TX
I
EMAC MII receive error
CAN-0 transmit data
O
Capture/Compare/PWM-3
(General-purpose Timer)
M_CCP3
I/O
I
14
PU
4 mA
USB-0 external power error state
(optionally used in the host mode)
M_USB0PFLT
M_U1DCD
M_MIIRXD1
M_U1RI
I
UART-1 data carrier detect
EMAC MII receive data 1
I
I
O
UART-1 ring indicator modem status
Enhanced PWM-4 output B
McBSP-A receive clock
C_EPWM4B
C_MCLKRA
C_ECAP2
PB0_GPIO8
I
I/O
I/O/Z
Enhanced Capture-1 input/output
General-purpose input/output 8
Capture/Compare/PWM-0
(General-purpose Timer)
M_CCP0
I/O
M_U1RX
I
O
UART-1 data receive data
SSI-2 transmit data
M_SSI2TX
M_CAN1TX
M_U4TX
15
PU
4 mA
O
CAN-1 transmit data
O
UART-4 transmit data
C_EPWM5A
C_ADCSOCAO
PB1_GPIO9
O
Enhanced PWM-5 output A
ADC start-of-conversion A
General-purpose input/output 9
O
I/O/Z
Capture/Compare/PWM-2
(General-purpose Timer)
M_CCP2
M_CCP1
I/O
I/O
Capture/Compare/PWM-1
(General-purpose Timer)
18
PU
4 mA
M_U1TX
O
I
UART-1 transmit data
M_SSI2RX
C_EPWM5B
C_ECAP3
SSI-2 receive data
O
Enhanced PWM-5 output B
Enhanced Capture-3 input/output
I/O
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F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
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Table 3-1. Terminal Functions(1) (continued)
TERMINAL
PU
or
OUTPUT
BUFFER
STRENGTH
I/O/Z(2)
DESCRIPTION
RFP
PIN NO.
PD(3)
NAME
PB2_GPIO10
I/O/Z
I/OD
General-purpose input/output 10
M_I2C0SCL
I2C-0 clock open-drain bidirectional port
Capture/Compare/PWM-3
(General-purpose Timer)
M_CCP3
I/O
I/O
O
Capture/Compare/PWM-0
(General-purpose Timer)
M_CCP0
USB-0 external power enable
(optionally used in the host mode)
19
PU
4 mA
M_USB0EPEN
M_SSI2CLK
M_CAN1RX
M_U4RX
I/O
SSI-2 clock
I
I
CAN-1 receive data
UART-4 receive data
C_EPWM6A
C_ADCSOCBO
PB3_GPIO11
M_I2C0SDA
O
Enhanced PWM-6 output A
ADC start-of-conversion B
General-purpose input/output 11
I2C-0 data open-drain bidirectional port
O
I/O/Z
I/OD
USB-0 external power error state
(optionally used in the host mode)
M_USB0PFLT
I
20
PU
4 mA
M_SSI2FSS
M_U1RX
I/O
SSI-2 frame
I
O
UART-1 receive data
C_EPWM6B
C_ECAP4
Enhanced PWM-6 output B
Enhanced Capture-4 input/output
General-purpose input/output 12
UART-2 receive data
I/O
I/O/Z
I
PB4_GPIO12
M_U2RX
M_CAN0RX
M_U1RX
I
CAN-0 receive data
I
UART-1 receive data
30
PU
4 mA
M_EPI0S23
M_CAN1TX
M_SSI1TX
C_EPWM7A
PB5_GPIO13
I/O
O
EPI-0 signal 23
CAN-1 transmit data
O
SSI-1 transmit data
O
Enhanced PWM-7 output A
General-purpose input/output 13
I/O/Z
Capture/Compare/PWM-5
(General-purpose Timer)
M_CCP5
M_CCP6
I/O
I/O
Capture/Compare/PWM-6
(General-purpose Timer)
Capture/Compare/PWM-0
(General-purpose Timer)
M_CCP0
I/O
O
M_CAN0TX
M_CCP2
CAN-0 transmit data
31
PU
4 mA
Capture/Compare/PWM-2
(General-purpose Timer)
I/O
M_U1TX
O
I/O
I
UART-1 transmit data
EPI-0 signal 22
M_EPI0S22
M_CAN1RX
M_SSI1RX
C_EPWM7B
CAN-1 receive data
SSI-1 receive data
I
O
Enhanced PWM-7 output B
92
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
Table 3-1. Terminal Functions(1) (continued)
TERMINAL
PU
or
OUTPUT
BUFFER
STRENGTH
I/O/Z(2)
DESCRIPTION
RFP
PIN NO.
PD(3)
NAME
PB6_GPIO14
M_CCP1
I/O/Z
I/O
General-purpose input/output 14
Capture/Compare/PWM-1
(General-purpose Timer)
Capture/Compare/PWM-7
(General-purpose Timer)
M_CCP7
M_CCP5
I/O
I/O
Capture/Compare/PWM-5
(General-purpose Timer)
26
PU
4 mA
M_EPI0S37(5)
M_MIICRS
M_I2C0SDA
M_U1TX
I/O
EPI-0 signal 37
I
EMAC MII carrier sense
I2C-0 data open-drain bidirectional port
UART-1 transmit data
I/OD
O
M_SSI1CLK
C_EPWM8A
PB7_GPIO15
M_EXTNMI
M_MIIRXD1
M_EPI0S36(5)
M_I2C0SCL
M_U1RX
I/O
SSI-1 clock
O
Enhanced PWM-8 output A
General-purpose input/output 15
Cortex™-M3 external non-maskable interrupt
EMAC MII receive data 1
EPI-0 signal 36
I/O/Z
I
I
I/O
27
PU
4 mA
I/OD
I2C-0 clock open-drain bidirectional port
UART-1 receive data
I
M_SSI1FSS
C_EPWM8B
PD0_GPIO16
M_CAN0RX
M_U2RX
I/O
SSI-1 frame
O
Enhanced PWM-8 output B
General-purpose input/output 16
CAN-0 receive data
I/O/Z
I
I
I
UART-2 receive data
M_U1RX
UART-1 receive data
Capture/Compare/PWM-6
(General-purpose Timer)
M_CCP6
I/O
M_MIIRXDV
M_U1CTS
I
I
EMAC MII receive data valid
UART-1 clear-to-send modem status
EMAC MII receive data 2
SSI-0 transmit data
102
PU
4 mA
M_MIIRXD2
M_SSI0TX
M_CAN1TX
I
O
O
CAN-1 transmit data
USB-0 external power enable
(optionally used in the host mode)
M_USB0EPEN
C_SPISIMOA
O
I/O
SPI-A slave in, master out
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
Table 3-1. Terminal Functions(1) (continued)
TERMINAL
PU
or
OUTPUT
BUFFER
STRENGTH
I/O/Z(2)
DESCRIPTION
RFP
PIN NO.
PD(3)
NAME
PD1_GPIO17
I/O/Z
O
General-purpose input/output 17
CAN-0 transmit data
M_CAN0TX
M_U2TX
O
UART-2 transmit data
M_U1TX
O
UART-1 transmit data
Capture/Compare/PWM-7
(General-purpose Timer)
M_CCP7
I/O
M_MIITXER
M_U1DCD
O
I
EMAC MII transmit error
UART-1 data carrier detect
98
PU
4 mA
Capture/Compare/PWM-2
(General-purpose Timer)
M_CCP2
I/O
M_MIICOL
M_SSI0RX
M_CAN1RX
I
I
I
EMAC MII collision detect
SSI-0 receive data
CAN-1 receive data
USB-0 external power error state
(optionally used in the host mode)
M_USB0PFLT
I
C_SPISOMIA
PD2_GPIO18
M_U1RX
I/O
I/O/Z
I
SPI-A master in, slave out
General-purpose input/output 18
UART-1 receive data
Capture/Compare/PWM-6
(General-purpose Timer)
M_CCP6
M_CCP5
I/O
I/O
Capture/Compare/PWM-5
(General-purpose Timer)
28
PU
4 mA
M_EPI0S20
M_SSI0CLK
M_U1TX
I/O
I/O
O
EPI-0 signal 20
SSI-0 clock
UART-1 transmit data
CAN-0 receive data
SPI-A clock
M_CAN0RX
C_SPICLKA
PD3_GPIO19
M_U1TX
I
I/O
I/O/Z
O
General-purpose input/output 19
UART-1 transmit data
Capture/Compare/PWM-7
(General-purpose Timer)
M_CCP7
M_CCP0
I/O
I/O
Capture/Compare/PWM-0
(General-purpose Timer)
29
PU
4 mA
M_EPI0S21
M_SSI0FSS
M_U1RX
I/O
I/O
I
EPI-0 signal 21
SSI-0 frame
UART-1 receive data
CAN-0 transmit data
SPI-A slave transmit enable
M_CAN0TX
C_SPISTEA
O
I/O
94
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
www.ti.com
SPRS742D –JUNE 2011–REVISED AUGUST 2012
Table 3-1. Terminal Functions(1) (continued)
TERMINAL
PU
or
OUTPUT
BUFFER
STRENGTH
I/O/Z(2)
DESCRIPTION
RFP
PIN NO.
PD(3)
NAME
PD4_GPIO20
M_CCP0
I/O/Z
I/O
General-purpose input/output 20
Capture/Compare/PWM-0
(General-purpose Timer)
Capture/Compare/PWM-3
(General-purpose Timer)
M_CCP3
I/O
M_MIITXD3
M_U1RI
O
I
EMAC MII transmit data 3
UART-1 ring indicator modem status
EPI-0 signal 19
65
PU
4 mA
M_EPI0S19
M_U3TX
I/O
O
UART-3 transmit data
M_CAN1TX
C_EQEP1A
C_MDXA
O
CAN-1 transmit data
I
Enhanced QEP-1 input A
McBSP-A transmit data
General-purpose input/output 21
O
PD5_GPIO21
I/O/Z
Capture/Compare/PWM-2
(General-purpose Timer)
M_CCP2
M_CCP4
I/O
I/O
Capture/Compare/PWM-4
(General-purpose Timer)
M_MIITXD2
M_U2RX
O
EMAC MII transmit data 2
UART-2 receive data
64
PU
6 mA
I
I/O
I
M_EPI0S28
M_U3RX
EPI-0 signal 28
UART-3 receive data
M_CAN1RX
C_EQEP1B
C_MDRA
I
CAN-1 receive data
I
Enhanced QEP-1 input B
McBSP-A receive data
General-purpose input/output 22
EMAC MII transmit data 1
UART-2 transmit data
I
PD6_GPIO22
M_MIITXD1
M_U2TX
I/O/Z
O
O
M_EPI0S29
M_I2C1SDA
M_U1TX
I/O
I/OD
O
EPI-0 signal 29
73
PU
6 mA
I2C-0 data open-drain bidirectional port
UART-1 transmit data
C_EQEP1S
C_MCLKXA
PD7_GPIO23
I/O
O
Enhanced QEP-1 strobe
McBSP-A transmit clock
General-purpose input/output 23
I/O/Z
Capture/Compare/PWM-1
(General-purpose Timer)
M_CCP1
I/O
M_MIITXD0
M_U1DTR
M_EPI0S30
M_I2C1SCL
M_U1RX
O
O
EMAC MII transmit data 0
UART-1 data terminal ready
EPI-0 signal 30
68
PU
6 mA
I/O
I/OD
I
I2C-1 clock open-drain bidirectional port
UART-1 receive data
C_EQEP1I
C_MFSXA
I/O
O
Enhanced QEP-1 index
McBSP-A transmit frame sync
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
Table 3-1. Terminal Functions(1) (continued)
TERMINAL
PU
or
OUTPUT
BUFFER
STRENGTH
I/O/Z(2)
DESCRIPTION
RFP
PIN NO.
PD(3)
NAME
PE0_GPIO24
I/O/Z
I/O
General-purpose input/output 24
SSI-1 clock
M_SSI1CLK
Capture/Compare/PWM-3
(General-purpose Timer)
M_CCP3
I/O
I/O
I
M_EPI0S8
M_USB0PFLT
EPI-0 signal 8
USB-0 external power error state
(optionally used in the host mode)
43
45
32
33
PU
PU
PU
PU
4 mA
4 mA
4 mA
4 mA
M_SSI3TX
M_CAN0RX
M_SSI1TX
C_ECAP1
O
I
SSI-3 transmit data
CAN-1 receive data
O
SSI-1 transmit data
I/O
I
Enhanced Capture-1 input/output
Enhanced QEP-2 input A
General-purpose input/output 25
SSI-1 frame
C_EQEP2A
PE1_GPIO25
M_SSI1FSS
I/O/Z
I/O
Capture/Compare/PWM-2
(General-purpose Timer)
M_CCP2
M_CCP6
I/O
I/O
Capture/Compare/PWM-6
(General-purpose Timer)
M_EPI0S9
M_SSI3RX
M_CAN0TX
M_SSI1RX
C_ECAP2
I/O
I
EPI-0 signal 9
SSI-3 receive data
O
CAN-1 transmit data
O
SSI-1 receive data
I/O
I
Enhanced Capture-2 input/output
Enhanced QEP-2 input B
General-purpose input/output 26
C_EQEP2B
PE2_GPIO26
I/O/Z
Capture/Compare/PWM-4
(General-purpose Timer)
M_CCP4
M_SSI1RX
M_CCP2
I/O
I
SSI-1 receive data
Capture/Compare/PWM-2
(General-purpose Timer)
I/O
M_EPI0S24
M_SSI3CLK
M_U2RX
I/O
I/O
I
EPI-0 signal 24
SSI-3 clock
UART-2 receive data
SSI-1 clock
M_SSI1CLK
C_ECAP3
I/O
I/O
I/O
I/O/Z
Enhanced Capture-3 input/output
Enhanced QEP-2 index
General-purpose input/output 27
C_EQEP2I
PE3_GPIO27
Capture/Compare/PWM-1
(General-purpose Timer)
M_CCP1
M_SSI1TX
M_CCP7
I/O
O
SSI-1 transmit data
Capture/Compare/PWM-7
(General-purpose Timer)
I/O
M_EPI0S25
M_SSI3FSS
M_U2TX
I/O
I/O
O
EPI-0 signal 25
SSI-3 frame
UART-2 transmit data
SSI-1 frame
M_SSI1FSS
C_ECAP4
I/O
I/O
I/O
Enhanced Capture-4 input/output
Enhanced QEP-2 strobe
C_EQEP2S
96
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
www.ti.com
SPRS742D –JUNE 2011–REVISED AUGUST 2012
Table 3-1. Terminal Functions(1) (continued)
TERMINAL
PU
or
OUTPUT
BUFFER
STRENGTH
I/O/Z(2)
DESCRIPTION
RFP
PIN NO.
PD(3)
NAME
PE4_GPIO28
M_CCP3
I/O/Z
I/O
O
General-purpose input/output 28
Capture/Compare/PWM-3
(General-purpose Timer)
M_U2TX
UART-2 transmit data
Capture/Compare/PWM-2
(General-purpose Timer)
M_CCP2
I/O
M_MIIRXD0
M_EPI0S34(5)
M_U0RX
I
EMAC MII receive data 0
EPI-0 signal 34
77
PU
4 mA
I/O
I
UART-0 receive data
EPI-0 signal 38
M_EPI0S38(5)
I/O
USB-0 external power enable
(optionally used in the host mode)
M_USB0EPEN
O
C_SCIRXDA
PE5_GPIO29
I
SCI-A receive data
I/O/Z
General-purpose input/output 29
Capture/Compare/PWM-5
(General-purpose Timer)
M_CCP5
I/O
M_EPI0S35(5)
M_MIITXER
M_U0TX
I/O
O
EPI-0 signal 35
76
EMAC MII transmit error
UART-0 transmit data
PU
4 mA
O
USB-0 external power error state
(optionally used in the host mode)
M_USB0PFLT
I
C_SCITXDA
PE6_GPIO30
M_U1CTS
O
SCI-A transmit data
I/O/Z
General-purpose input/output 30
UART-1 clear-to-send modem status
EMAC management data input/output
CAN-0 receive data
I
M_MDIOD
22
23
I/O
PU
PU
4 mA
4 mA
M_CAN0RX
C_EPWM9A
PE7_GPIO31
M_U1DCD
I
O
Enhanced PWM-9 output A
General-purpose input/output 31
UART-1 data carrier detect
EMAC MII receive data 3
CAN-0 transmit data
I/O/Z
I
M_MIIRXD3
M_CAN0TX
C_EPWM9B
PF0_GPIO32
M_CAN1RX
M_MIIRXCK
M_U1DSR
I
O
O
Enhanced PWM-9 output B
General-purpose input/output 32
CAN-1 receive data
I/O/Z
I
I
EMAC MII receive clock
I
I/OD
O
UART-1 data set ready
M_I2C0SDA
M_TRACED2
C_I2CASDA
C_SCIRXDA
C_ADCSOCAO
104
I2C-0 data open-drain bidirectional port
Trace data 2
PU
4 mA
I/OD
I
I2C-A data open-drain bidirectional port
SCI-A receive data
ADC start-of-conversion A(6)
O
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F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
Table 3-1. Terminal Functions(1) (continued)
TERMINAL
PU
or
OUTPUT
BUFFER
STRENGTH
I/O/Z(2)
DESCRIPTION
RFP
PIN NO.
PD(3)
NAME
PF1_GPIO33
I/O/Z
General-purpose input/output 33
CAN-1 transmit data
M_CAN1TX
M_MIIRXER
M_U1RTS
O
I
EMAC MII receive error
UART-1 request-to-send
O
Capture/Compare/PWM-3
(General-purpose Timer)
M_CCP3
I/O
103
PU
4 mA
M_I2C0SCL
M_TRACED3
C_I2CASCL
I/OD
O
I2C-0 clock open-drain bidirectional port
Trace data 3
I/OD
O
I2C-A clock open-drain bidirectional port
Enhanced PWM sync out
ADC start-of-conversion B(6)
General-purpose input/output 34
EMAC PHY MII interrupt
EPI-0 signal 32
C_EPWMSYNCO
C_ADCSOCBO
PF2_GPIO34
M_MIIPHYINTR
M_EPI0S32(5)
M_SSI1CLK
M_TRACECLK
M_XCLKOUT
C_ECAP1
O
I/O/Z
I
I/O
I/O
O
SSI-1 clock
Trace clock
82
PU
4 mA
O
External output clock
Enhanced Capture-1 input/output
SCI-A receive data
I/O
I
C_SCIRXDA
C_XCLKOUT
BOOT_3
O
External output clock
Boot pin 3
I
PF3_GPIO35
M_MDIOCK
M_EPI0S33(5)
M_SSI1FSS
M_U0TX
I/O/Z
I
General-purpose input/output 35
EMAC management data clock
EPI-0 signal 33
I/O
I/O
O
SSI-1 frame
81
PU
4 mA
UART-0 transmit data
Trace data 0
M_TRACED0
C_SCITXDA
BOOT_2
O
O
SCI-A transmit data
I
Boot pin 2
PF4_GPIO36
I/O/Z
General-purpose input/output 36
Capture/Compare/PWM-0
(General-purpose Timer)
M_CCP0
I/O
M_MDIOD
M_EPI0S12
M_SSI1RX
M_U0RX
I/O
EMAC management data input/output
EPI-0 signal 12
48
PU
4 mA
I/O
I
SSI-1 receive data
I
I
UART-0 receive data
C_SCIRXDA
PF5_GPIO37
SCI-A receive data
I/O/Z
General-purpose input/output 37
Capture/Compare/PWM-2
(General-purpose Timer)
M_CCP2
I/O
M_MIIRXD3
M_EPI0S15
M_SSI1TX
M_MIITXEN
C_ECAP2
I
EMAC MII receive data 3
EPI-0 signal 15
51
PU
4 mA
I/O
O
SSI-1 transmit data
O
EMAC MII transmit enable
Enhanced Capture-2 input/output
I/O
98
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
Table 3-1. Terminal Functions(1) (continued)
TERMINAL
PU
or
OUTPUT
BUFFER
STRENGTH
I/O/Z(2)
DESCRIPTION
RFP
PIN NO.
PD(3)
NAME
General-purpose input/output 38.
NOTE: For this pin, only the USB0VBUS function
is available on silicon revision 0 devices (GPIO
and the four other functions listed are not
available).
PF6_GPIO38
I/O/Z
M_USB0VBUS
M_CCP1
Analog
I/O
USB0 VBUS power (5-V tolerant)
69
PU
4 mA
Capture/Compare/PWM-1
(General-purpose Timer)
M_MIIRXD2
M_EPI0S38(5)
M_U1RTS
I
I/O
EMAC MII receive data 2
EPI-0 signal 38
O
UART-1 request-to-send
PF7_GPIO39
PG0_GPIO40
M_U2RX
No Pin
No Pin
I/O/Z
I
General-purpose input/output 39 is not pinned out.
General-purpose input/output 40
UART-2 receive data
M_I2C1SCL
I/OD
I2C-1 clock open-drain bidirectional port
USB-0 external power enable
(optionally used in the host mode)
M_USB0EPEN
O
49
PU
4 mA
M_EPI0S13
M_MIIRXD2
M_U4RX
I/O
EPI-0 signal 13
I
EMAC MII receive data 2
UART-4 receive data
I
M_MIITXCK
PG1_GPIO41
M_U2TX
I
EMAC MII transmit clock
General-purpose input/output 41
UART-2 transmit data
I/O/Z
O
M_I2C1SDA
M_EPI0S14
M_MIIRXD1
M_U4TX
I/OD
I2C-1 data open-drain bidirectional port
EPI-0 signal 14
50
71
I/O
PU
4 mA
I
EMAC MII receive data 1
UART-4 transmit data
O
M_MIITXER
PG2_GPIO42
M_USB0DM
M_MIICOL
M_EPI0S39(5)
PG3_GPIO43
M_MIICRS
M_MIIRXDV
M_TRACED1
BOOT_0
O
EMAC MII transmit error
General-purpose input/output 42
USB0 data minus
I/O/Z
Analog
PU
PU
4 mA
4 mA
I
EMAC MII collision detect
EPI-0 signal 39
I/O
I/O/Z
General-purpose input/output 43
EMAC MII carrier sense
EMAC MII receive data valid
Trace data 1
I
78
I
O
I
Boot pin 0
PG4_GPIO44
PG5_GPIO45
M_USB0DP
No Pin
No Pin
I/O/Z
Analog
General-purpose input/output 44 is not pinned out.
General-purpose input/output 45
USB0 data plus
Capture/Compare/PWM-5
(General-purpose Timer)
M_CCP5
I/O
72
PU
4 mA
M_MIITXEN
M_EPI0S40(5)
M_U1DTR
O
I/O
O
EMAC MII transmit enable
EPI-0 signal 40
UART-1 data terminal ready
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
Table 3-1. Terminal Functions(1) (continued)
TERMINAL
PU
or
OUTPUT
BUFFER
STRENGTH
I/O/Z(2)
DESCRIPTION
RFP
PIN NO.
PD(3)
NAME
General-purpose input/output 46.
NOTE: For this pin, only the USB0ID function is
available on silicon revision 0 devices (GPIO and
the three other functions listed are not available).
PG6_GPIO46
I/O/Z
70
PU
4 mA
M_USB0ID
M_MIITCK
M_EPI0S41(5)
M_U1RI
Analog
USB0 ID (5-V tolerant)
EMAC MII transmit clock
EPI-0 signal 41
I
I/O
I
UART-1 receive data
PG7_GPIO47
M_MIITXER
I/O/Z
O
General-purpose input/output 47
EMAC MII transmit error
Capture/Compare/PWM-5
(General-purpose Timer)
M_CCP5
I/O
52
PU
6 mA
M_EPI0S31
M_MIICRS
BOOT_1
I/O
EPI-0 signal 31
I
I
EMAC MII carrier sense
Boot pin 1
PH0_GPIO48
I/O/Z
General-purpose input/output 48
Capture/Compare/PWM-6
(General-purpose Timer)
M_CCP6
I/O
M_MIIPHYRST
M_EPI0S6
O
I/O
O
EMAC PHY MII reset
41
PU
4 mA
EPI-0 signal 6
M_SSI3TX
SSI-3 transmit data
M_MIITXD3
C_ECAP5
O
EMAC MII transmit data 3
Enhanced Capture-5 input/output
General-purpose input/output 49
I/O
I/O/Z
PH1_GPIO49
Capture/Compare/PWM-7
(General-purpose Timer)
M_CCP7
I/O
M_EPI0S7
I/O
I
EPI-0 signal 7
42
36
35
PU
PU
PU
4 mA
4 mA
4 mA
M_MIIRXD0
M_SSI3RX
M_MIITXD2
C_ECAP6
EMAC MII receive data 0
SSI-3 receive data
I
O
EMAC MII transmit data 2
Enhanced Capture-6 input/output
General-purpose input/output 50
EPI-0 signal 1
I/O
I/O/Z
I/O
O
PH2_GPIO50
M_EPI0S1
M_MIITXD3
M_SSI3CLK
M_MIITXD1
C_EQEP1A
PH3_GPIO51
EMAC MII transmit data 3
SSI-3 clock
I/O
O
EMAC MII transmit data 1
Enhanced QEP-1 input A
General-purpose input/output 51
I
I/O/Z
USB-0 external power enable
(optionally used in the host mode)
M_USB0EPEN
O
M_EPI0S0
M_MIITXD2
M_SSI3FSS
M_MIITXD0
C_EQEP1B
I/O
O
EPI-0 signal 0
EMAC MII transmit data 2
SSI-3 frame
I/O
O
EMAC MII transmit data 0
Enhanced QEP-1 input B
I
100
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
Table 3-1. Terminal Functions(1) (continued)
TERMINAL
PU
or
OUTPUT
BUFFER
STRENGTH
I/O/Z(2)
DESCRIPTION
RFP
PIN NO.
PD(3)
NAME
PH4_GPIO52
M_USB0PFLT
I/O/Z
I
General-purpose input/output 52
USB-0 external power error state
(optionally used in the host mode)
M_EPI0S10
M_MIITXD1
M_SSI1CLK
M_U3TX
I/O
O
EPI-0 signal 10
EMAC MII transmit data 1
SSI-1 clock
46
PU
4 mA
I/O
O
UART-3 transmit data
EMAC MII collision detect
Enhanced QEP-1 strobe
General-purpose input/output 53
EPI-0 signal 11
M_MIICOL
I
C_EQEP1S
PH5_GPIO53
M_EPI0S11
M_MIITXD0
M_SSI1FSS
M_U3RX
I/O
I/O/Z
I/O
O
EMAC MII transmit data 0
SSI-1 frame
47
I/O
I
PU
4 mA
UART-3 receive data
M_MIIPHYRST
C_EQEP1I
O
EMAC PHY MII reset
Enhanced QEP-1 index
General-purpose input/output 54
EPI-0 signal 26
I/O
I/O/Z
I/O
I
PH6_GPIO54
M_EPI0S26
M_MIIRXDV
M_SSI1RX
M_MIITXEN
M_SSI0TX
EMAC MII receive data valid
SSI-1 receive data
I
79
O
EMAC MII transmit enable
SSI-0 transmit data
PU
4 mA
O
M_MIIPHYINTR
C_SPISIMOA
C_EQEP3A
PH7_GPIO55
M_MIIRXCK
M_EPI0S27
M_SSI1TX
I
EMAC PHY MII interrupt
SPI-A slave in, master out
Enhanced QEP-1 input A
General-purpose input/output 55
EMAC MII receive clock
EPI-0 signal 27
I/O
I
I/O/Z
I
I/O
O
SSI-1 transmit data
M_MIITXCK
M_SSI0RX
M_MDIOCK
C_SPISOMIA
C_EQEP3B
PJ0_GPIO56
M_MIIRXER
M_EPI016
80
I
EMAC MII transmit clock
SSI-0 receive data
PU
4 mA
I
O
EMAC management data clock
SPI-A master in, slave out
Enhanced QEP-3 input B
General-purpose input/output 56
EMAC MII receive error
EPI-0 signal 16
I/O
I
I/O/Z
I
I/O
I/OD
I/O
I/O
I/O
I/O
M_I2C1SCL
M_SSI0CLK
M_MDIOD
I2C-1 clock open-drain bidirectional port
SSI-0 clock
63
PU
4 mA
EMAC management data input/output
SPI-A clock
C_SPICLKA
C_EQEP3S
Enhanced QEP-3 strobe
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
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Table 3-1. Terminal Functions(1) (continued)
TERMINAL
PU
or
OUTPUT
BUFFER
STRENGTH
I/O/Z(2)
DESCRIPTION
RFP
PIN NO.
PD(3)
NAME
PJ1_GPIO57
I/O/Z
I/O
General-purpose input/output 57
EPI-0 signal 17
M_EPI0S17
USB-0 external power error state
(optionally used in the host mode)
M_USB0PFLT
I
M_I2C1SDA
M_MIIRXDV
M_SSI0FSS
M_MIIRXD3
C_SPISTEA
C_EQEP3I
I/OD
I
I2C-1 data open-drain bidirectional port
EMAC MII receive data valid
SSI-0 frame
62
PU
4 mA
I/O
I
EMAC MII receive data 3
SPI-A slave transmit enable
Enhanced QEP-3 index
General-purpose input/output 58
EPI-0 signal 18
I/O
I/O
I/O/Z
I/O
PJ2_GPIO58
M_EPI0S18
Capture/Compare/PWM-0
(General-purpose Timer)
M_CCP0
I/O
M_MIIRXCK
M_SSI0CLK
M_U0TX
I
EMAC MII receive clock
SSI-0 clock
61
PU
4 mA
I/O
O
UART-0 transmit data
EMAC MII receive data 2
McBSP-A receive clock
Enhanced PWM-7 output A
General-purpose input/output 59
EPI-0 signal 19
M_MIIRXD2
C_MCLKRA
C_EPWM7A
PJ3_GPIO59
M_EPI0S19
M_U1CTS
I
I
O
I/O/Z
I/O
I
UART-1 clear-to-send
Capture/Compare/PWM-6
(General-purpose Timer)
M_CCP6
I/O
M_MDIOCK
M_SSI0FSS
M_U0RX
O
EMAC management data clock
SSI-0 frame
60
PU
4 mA
I/O
I
UART-0 receive data
M_MIIRXD1
C_MFSRA
C_EPWM7B
PJ4_GPIO60
M_EPI0S28
M_U1DCD
I
EMAC MII receive data 1
McBSP-A receive frame sync
Enhanced PWM-7 output B
General-purpose input/output 60
EPI-0 signal 28
I
O
I/O/Z
I/O
I
UART-1 data carrier detect
Capture/Compare/PWM-4
(General-purpose Timer)
M_CCP4
I/O
57
PU
6 mA
M_MIICOL
I
I/O
I
EMAC MII collision detect
SSI-1 clock
M_SSI1CLK
M_MIIRXD0
C_EPWM8A
EMAC MII receive data 0
Enhanced PWM-8 output A
O
102
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www.ti.com
SPRS742D –JUNE 2011–REVISED AUGUST 2012
Table 3-1. Terminal Functions(1) (continued)
TERMINAL
PU
or
OUTPUT
BUFFER
STRENGTH
I/O/Z(2)
DESCRIPTION
RFP
PIN NO.
PD(3)
NAME
PJ5_GPIO61
M_EPI0S29
M_U1DSR
I/O/Z
I/O
I
General-purpose input/output 61
EPI-0 signal 29
UART-1 data set ready
Capture/Compare/PWM-2
(General-purpose Timer)
M_CCP2
I/O
56
PU
6 mA
M_MIICRS
M_SSI1FSS
M_MIIRXDV
C_EPWM8B
PJ6_GPIO62
M_EPI0S30
M_U1RTS
I
I/O
I
EMAC MII carrier sense
SSI-1 frame
EMAC MII receive data valid
Enhanced PWM-8 output B
General-purpose input/output 62
EPI-0 signal 30
O
I/O/Z
I/O
O
UART-1 request-to-send
Capture/Compare/PWM-1
(General-purpose Timer)
M_CCP1
I/O
53
PU
6 mA
M_MIIPHYINTR
M_U2RX
I
EMAC PHY MII interrupt
UART-2 receive data
I
I
M_MIIRXER
C_EPWM9A
PJ7_GPIO63
M_U1DTR
EMAC MII receive error
O
Enhanced PWM-9 output A
General-purpose input/output 63
UART-1 data terminal ready
I/O/Z
O
Capture/Compare/PWM-0
(General-purpose Timer)
M_CCP0
I/O
M_MIIPHYRST
M_U2TX
O
O
I
EMAC PHY MII reset
UART-2 transmit data
EMAC MII receive clock
97
PU
4 mA
M_MIIRXCK
External oscillator input for USB PLL and CAN
(always available, see Figure 2-15)
M_XCLKIN
I
C_EPWM9B
PC0_GPIO64
PC1_GPIO65
PC2_GPIO66
PC3_GPIO67
PC4_GPIO68
O
Enhanced PWM-9 output B
No Pin
No Pin
No Pin
No Pin
No Pin
No Pin
No Pin
No Pin
I/O/Z
General-purpose input/output 64 is not pinned out.
General-purpose input/output 65 is not pinned out.
General-purpose input/output 66 is not pinned out.
General-purpose input/output 67 is not pinned out.
General-purpose input/output 68
Capture/Compare/PWM-5
(General-purpose Timer)
M_CCP5
I
O
I
M_MIITXD3
M_CCP2
EMAC MII transmit data 3
Capture/Compare/PWM-2
(General-purpose Timer)
37
PU
4 mA
Capture/Compare/PWM-4
(General-purpose Timer)
M_CCP4
M_EPI0S2
M_CCP1
I
I/O
I
EPI-0 signal 2
Capture/Compare/PWM-1
(General-purpose Timer)
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
Table 3-1. Terminal Functions(1) (continued)
TERMINAL
PU
or
OUTPUT
BUFFER
STRENGTH
I/O/Z(2)
DESCRIPTION
RFP
PIN NO.
PD(3)
NAME
PC5_GPIO69
I/O/Z
I
General-purpose input/output 69
Capture/Compare/PWM-1
(General-purpose Timer)
M_CCP1
Capture/Compare/PWM-3
(General-purpose Timer)
M_CCP3
38
I
PU
4 mA
USB-0 external power enable
(optionally used in the host mode)
M_USB0EPEN
O
M_EPI0S3
I/O
EPI-0 signal 3
PC6_GPIO70
I/O/Z
General-purpose input/output 70
Capture/Compare/PWM-3
(General-purpose Timer)
M_CCP3
M_U1RX
M_CCP0
I
I
I
UART-1 receive data
39
PU
4 mA
Capture/Compare/PWM-0
(General-purpose Timer)
USB-0 external power error state
(optionally used in the host mode)
M_USB0PFLT
I
M_EPI0S4
I/O
EPI-0 signal 4
PC7_GPIO71
I/O/Z
General-purpose input/output 71
Capture/Compare/PWM-4
(General-purpose Timer)
M_CCP4
I
Capture/Compare/PWM-0
(General-purpose Timer)
M_CCP0
I
O
I
40
PU
4 mA
M_U1TX
UART-1 transmit data
USB-0 external power error state
(optionally used in the host mode)
M_USB0PFLT
M_EPI0S5
I/O
EPI-0 signal 5
104
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
Table 3-1. Terminal Functions(1) (continued)
TERMINAL
PU
or
OUTPUT
BUFFER
STRENGTH
I/O/Z(2)
DESCRIPTION
RFP
PIN NO.
PD(3)
NAME
Resets
Digital Subsystem Reset (in) and
Watchdog/Brown-out Reset (out). In most
applications, TI recommends that the XRS pin be
tied with the ARS pin. The Digital Subsystem has
a built-in power-on-reset (POR) and brown-out-
reset (BOR) circuitry. As such, no external circuitry
is needed to generate a reset pulse. During a
power-on or brown-out condition, this pin is driven
low by the Digital Subsystem. This pin is also
driven low by the Digital Subsystem when a
watchdog reset occurs. During watchdog reset,
the XRS pin is driven low for the watchdog reset
duration of 512 OSCCLK cycles. If need be, an
external circuitry may also drive this pin to assert
device reset. In this case, TI recommends that this
pin be driven by an open-drain device. An R-C
circuit must be connected to this pin for noise
immunity reasons. Regardless of the source, a
device reset causes the Digital Subsystem to
terminate execution. The Cortex™-M3 program
counter points to the address contained at the
location 0x00000004. The C28 program counter
points to the address contained at the location
0x3FFFC0. When reset is deactivated, execution
begins at the location designated by the program
counter. The output buffer of this pin is an open-
drain with an internal pullup.
XRS
4
I/OD
PU
4 mA
Analog Subsystem Reset (in) and Brown-out
Reset (out). In most applications, TI recommends
that the ARS pin be tied with the XRS pin. The
Digital Subsystem has a built-in brown-out-reset
(BOR) circuitry. As such, no external circuitry is
needed to generate a reset pulse. During a power-
on or brown-out condition, this pin is driven low by
the Analog Subsystem. If need be, an external
circuitry may also drive this pin to assert a device
reset. In this case, TI recommends that this pin be
driven by an open-drain device. An R-C circuit
must be connected to this pin for noise immunity
reasons. Regardless of the source, the Analog
Subsystem reset causes the digital logic
ARS
144
I/OD
PU
4 mA
associated with the Analog Subsystem, to enter
reset state. The output buffer of this pin is an
open-drain with an internal pullup.
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
Table 3-1. Terminal Functions(1) (continued)
TERMINAL
PU
or
OUTPUT
BUFFER
STRENGTH
I/O/Z(2)
DESCRIPTION
RFP
PIN NO.
PD(3)
NAME
Clocks
External oscillator input or on-chip crystal-
oscillator input. To use the on-chip oscillator, a
quartz crystal or a ceramic resonator must be
connected across X1 and X2. See Figure 2-7.
X1
X2
93
95
I
On-chip crystal-oscillator output. A quartz crystal
or a ceramic resonator must be connected across
X1 and X2. If X2 is not used, it must be left
unconnected. See Figure 2-7.
O
Clock Oscillator Ground Pin. Use this pin to
connect the GND of external crystal load
capacitors or the ground pin of 3-terminal ceramic
resonators with built-in capacitors. Do not connect
to board ground. See Figure 2-7.
VSSOSC
XCLKIN
94
External oscillator input. This pin feeds a clock
from an external 3.3-V oscillator to internal USB
PLL module and to the CAN peripherals.
see
PJ7_GPIO63
I
External oscillator output. This pin outputs a clock
divided-down from the internal PLL System Clock.
The divide ratio is defined in the XCLKCFG
register.
see
PF2_GPIO34
XCLKOUT
O/Z
Boot Pins
One of four boot mode pins. BOOT_0 selects a
specific configuration source from which the
Concerto device boots on start-up.
see
PG3_GPIO43
BOOT_0
BOOT_1
BOOT_2
BOOT_3
I
I
I
I
PU
PU
PU
PU
One of four boot mode pins. BOOT_1 selects a
specific configuration source from which the
Concerto device boots on start-up.
see
PG7_GPIO47
One of four boot mode pins. BOOT_2 selects a
specific configuration source from which the
Concerto device boots on start-up.
see
PF3_GPIO35
One of four boot mode pins. BOOT_3 selects a
specific configuration source from which the
Concerto device boots on start-up.
see
PF2_GPIO34
JTAG
JTAG test reset with internal pulldown. TRST,
when driven high, gives the scan system control of
the operations of the device. If this signal is not
connected or driven low, the device operates in its
functional mode, and the test reset signals are
ignored. NOTE: TRST is an active-low test pin
and must be maintained low during normal device
operation. An external pulldown resistor is
required on this pin. The value of this resistor
should be based on drive strength of the debugger
pods applicable to the design. A 2.2-kΩ resistor
generally offers adequate protection. Since the
value of the resistor is application-specific, TI
recommends that each target board be validated
for proper operation of the debugger and the
application.
TRST
85
I
PD
TCK
TMS
89
87
I
I
JTAG test clock
JTAG test-mode select (TMS) with internal pullup.
This serial control input is clocked into the TAP
controller on the rising edge of TCK.
PU
PU
JTAG test data input (TDI) with internal pullup.
TDI is clocked into the selected register
TDI
88
I
(instruction or data) on a rising edge of TCK.
106
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
Table 3-1. Terminal Functions(1) (continued)
TERMINAL
PU
or
OUTPUT
BUFFER
STRENGTH
I/O/Z(2)
DESCRIPTION
RFP
PIN NO.
PD(3)
NAME
JTAG scan out, test data output (TDO). The
contents of the selected register (instruction or
data) are shifted out of TDO on the falling edge of
TCK.
TDO
84
O
4 mA
Emulator pin 0. When TRST is driven high, this
pin is used as an interrupt to or from the emulator
system and is defined as input/output through the
JTAG scan. This pin is also used to put the device
into boundary-scan mode. With the EMU0 pin at a
logic-high state and the EMU1 pin at a logic-low
state, a rising edge on the TRST pin would latch
the device into boundary-scan mode.
NOTE: An external pullup resistor is required on
this pin. The value of this resistor should be based
on the drive strength of the debugger pods
applicable to the design. A 2.2-kΩ to 4.7-kΩ
resistor is generally adequate. Since the value of
the resistor is application-specific, TI recommends
that each target board be validated for proper
operation of the debugger and the application.
NOTE: If EMU0 is 0 and EMU1 is 1 when coming
out of reset, the device enters Wait-in-Reset
mode. WIR suspends bootloader execution,
allowing the Emulator to connect to the device and
to modify FLASH contents.
EMU0
83
I/O/Z
PU
4 mA
Emulator pin 1. When TRST is driven high, this
pin is used as an interrupt to or from the emulator
system and is defined as input/output through the
JTAG scan. This pin is also used to put the device
into boundary-scan mode. With the EMU0 pin at a
logic-high state and the EMU1 pin at a logic-low
state, a rising edge on the TRST pin would latch
the device into boundary-scan mode.
NOTE: An external pullup resistor is required on
this pin. The value of this resistor should be based
on the drive strength of the debugger pods
applicable to the design. A 2.2-kΩ to 4.7-kΩ
resistor is generally adequate. Since the value of
the resistor is application-specific, TI recommends
that each target board be validated for proper
operation of the debugger and the application.
NOTE: If EMU0 is 0 and EMU1 is 1 when coming
out of reset, the device enters Wait-in-Reset
mode. WIR suspends bootloader execution,
allowing the Emulator to connect to the device and
to modify FLASH contents.
EMU1
86
I/O/Z
PU
4 mA
ITM Trace (ARM® Instrumentation Trace Macrocell)
see
PF3_GPIO35
TRACED0
TRACED1
TRACED2
TRACED3
TRACECLK
O
O
O
O
O
ITM Trace data 0
ITM Trace data 1
ITM Trace data 2
ITM Trace data 3
ITM Trace clock
4 mA
4 mA
4 mA
4 mA
4 mA
see
PG3_GPIO43
see
PF0_GPIO32
see
PF1_GPIO33
see
PF2_GPIO34
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
Table 3-1. Terminal Functions(1) (continued)
TERMINAL
PU
or
OUTPUT
BUFFER
STRENGTH
I/O/Z(2)
DESCRIPTION
RFP
PIN NO.
PD(3)
NAME
Test Pins
FLASH Test Pin 1. Reserved for TI. Must be left
unconnected.
FLT1
FLT2
16
21
I/O
I/O
FLASH Test Pin 2. Reserved for TI. Must be left
unconnected.
Internal Voltage Regulator Control
Internal 1.8-V VREG Enable/Disable for VDD18
Pull low to enable the internal 1.8-V voltage
regulator (VREG18), pull high to disable VREG18.
.
VREG18EN
VREG12EN
113
101
PD
PD
Internal 1.2-V VREG Enable/Disable for VDD12
Pull low to enable the internal 1.2-V voltage
.
regulator (VREG12), pull high to disable VREG12.
Digital Logic Power Pins for I/Os, Flash, USB, and Internal Oscillators
3.3-V Digital I/O and FLASH Power Pin. Tie with a
0.1-µF capacitor (typical) close to the pin.
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
107
3.3-V Digital I/O and FLASH Power Pin. Tie with a
0.1-µF capacitor (typical) close to the pin.
10
3.3-V Digital I/O and FLASH Power Pin. Tie with a
0.1-µF capacitor (typical) close to the pin.
25
3.3-V Digital I/O and FLASH Power Pin. Tie with a
0.1-µF capacitor (typical) close to the pin.
34
3.3-V Digital I/O and FLASH Power Pin. Tie with a
0.1-µF capacitor (typical) close to the pin.
44
3.3-V Digital I/O and FLASH Power Pin. Tie with a
0.1-µF capacitor (typical) close to the pin.
54
3.3-V Digital I/O and FLASH Power Pin. Tie with a
0.1-µF capacitor (typical) close to the pin.
59
3.3-V Digital I/O and FLASH Power Pin. Tie with a
0.1-µF capacitor (typical) close to the pin.
105
3.3-V Digital I/O and FLASH Power Pin. Tie with a
0.1-µF capacitor (typical) close to the pin.
3
3.3-V Digital I/O and FLASH Power Pin. Tie with a
0.1-µF capacitor (typical) close to the pin.
67
3.3-V Digital I/O and FLASH Power Pin. Tie with a
0.1-µF capacitor (typical) close to the pin.
74
3.3-V Digital I/O and FLASH Power Pin. Tie with a
0.1-µF capacitor (typical) close to the pin.
92
3.3-V Digital I/O and FLASH Power Pin. Tie with a
0.1-µF capacitor (typical) close to the pin.
100
3.3-V Digital I/O and FLASH Power Pin. Tie with a
0.1-µF capacitor (typical) close to the pin.
96
3.3-V Digital I/O and FLASH Power Pin. Tie with a
0.1-µF capacitor (typical) close to the pin.
17
3.3-V Digital I/O and FLASH Power Pin. Tie with a
0.1-µF capacitor (typical) close to the pin.
2
3.3-V Digital I/O and FLASH Power Pin. Tie with a
0.1-µF capacitor (typical) close to the pin.
106
108
Device Pins
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
Table 3-1. Terminal Functions(1) (continued)
TERMINAL
PU
or
OUTPUT
BUFFER
STRENGTH
I/O/Z(2)
DESCRIPTION
RFP
PIN NO.
PD(3)
NAME
Digital Logic Power Pins (Analog Subsystem)
1.8-V Digital Logic Power Pins (associated with
the Analog Subsystem) - no supply needed when
using internal VREG18. Tie with 2.2-µF (minimum)
ceramic capacitor (10% tolerance) to ground when
using internal VREG. Higher value capacitors may
be used but could impact supply-rail ramp-up time.
VDD18
1
1.8-V Digital Logic Power Pins (associated with
the Analog Subsystem) - no supply needed when
using internal VREG18. Tie with 2.2-µF (minimum)
ceramic capacitor (10% tolerance) to ground when
using internal VREG. Higher value capacitors may
be used but could impact supply-rail ramp-up time.
VDD18
108
Digital Logic Power Pins (Master and Control Subsystems)
1.2-V Digital Logic Power Pins - no supply needed
when using internal VREG12. Tie with 470-nF
(minimum) ceramic capacitor (10% tolerance) to
ground when using internal VREG. Higher value
capacitors may be used but could impact supply-
rail ramp-up time.
VDD12
VDD12
VDD12
VDD12
VDD12
VDD12
VDD12
24
55
66
99
75
58
11
1.2-V Digital Logic Power Pins - no supply needed
when using internal VREG12. Tie with 470-nF
(minimum) ceramic capacitor (10% tolerance) to
ground when using internal VREG. Higher value
capacitors may be used but could impact supply-
rail ramp-up time.
1.2-V Digital Logic Power Pins - no supply needed
when using internal VREG12. Tie with 470-nF
(minimum) ceramic capacitor (10% tolerance) to
ground when using internal VREG. Higher value
capacitors may be used but could impact supply-
rail ramp-up time.
1.2-V Digital Logic Power Pins - no supply needed
when using internal VREG12. Tie with 470-nF
(minimum) ceramic capacitor (10% tolerance) to
ground when using internal VREG. Higher value
capacitors may be used but could impact supply-
rail ramp-up time.
1.2-V Digital Logic Power Pins - no supply needed
when using internal VREG12. Tie with 470-nF
(minimum) ceramic capacitor (10% tolerance) to
ground when using internal VREG. Higher value
capacitors may be used but could impact supply-
rail ramp-up time.
1.2-V Digital Logic Power Pins - no supply needed
when using internal VREG12. Tie with 470-nF
(minimum) ceramic capacitor (10% tolerance) to
ground when using internal VREG. Higher value
capacitors may be used but could impact supply-
rail ramp-up time.
1.2-V Digital Logic Power Pins - no supply needed
when using internal VREG12. Tie with 470-nF
(minimum) ceramic capacitor (10% tolerance) to
ground when using internal VREG. Higher value
capacitors may be used but could impact supply-
rail ramp-up time.
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Table 3-1. Terminal Functions(1) (continued)
TERMINAL
PU
or
OUTPUT
BUFFER
STRENGTH
I/O/Z(2)
DESCRIPTION
RFP
PIN NO.
PD(3)
NAME
1.2-V Digital Logic Power Pins - no supply needed
when using internal VREG12. Tie with 470-nF
(minimum) ceramic capacitor (10% tolerance) to
ground when using internal VREG. Higher value
capacitors may be used but could impact supply-
rail ramp-up time.
VDD12
90
Digital Logic Ground (Analog, Master, and Control Subsystems)
Digital Ground Power Pad (located on the bottom
of the chip)
VSS
NC
PWR PAD
No Connect Pins
No connect
91
(1) Throughout this table, Master Subsystem signals are denoted by the color "blue"; Control Subsystem signals are denoted by the color
"green"; and Analog Subsystem signals are denoted by the color "orange".
(2) I = Input, O = Output, Z = High Impedance, OD = Open Drain
(3) PU = Pullup, PD = Pulldown
–
–
–
–
–
GPIO_MUX1 pullups can be enabled or disabled by Cortex™-M3 software (disabled on reset).
GPIO_MUX2 pullups can be enabled or disabled by C28x software (disabled on reset).
AIO_MUX1 and AIO_MUX2 terminals do not have pullups or pulldowns.
All other pullups are always enabled (XRS, ARS, TMS, TDI, EMU0, EMU1).
All pulldowns are always enabled (VREG18EN, VREG12EN, TRST).
(4) All I/Os, except for GPIO135, are glitch-free during power up and power down. See Section 2.11.
(5) This muxing option is only available on silicon Revision A devices; this muxing option is not available on silicon Revision 0 devices.
(6) Output from the Concerto ePWM is meant for the external ADC (if present).
110
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
4 Device Operating Conditions
4.1 Absolute Maximum Ratings(1) (2)
Supply voltage range, VDDIO (I/O and Flash)
Supply voltage range, VDD18
with respect to VSS
with respect to VSS
with respect to VSS
with respect to VSSA
–0.3 V to 4.6 V
–0.3 V to 2.5 V
–0.3 V to 1.5 V
–0.3 V to 4.6 V
–0.3 V to 4.6 V
–0.3 V to 4.6 V
±20 mA
Supply voltage range, VDD12
Analog voltage range, VDDA
Input voltage range, VIN (3.3 V)
Output voltage range, VO
(3)
Input clamp current, IIK (VIN < 0 or VIN > VDDIO
)
Output clamp current, IOK (VO < 0 or VO > VDDIO
Free-Air temperature, TA
)
±20 mA
–40°C to 125°C
–40°C to 150°C
–65°C to 150°C
(4)
Junction temperature range, TJ
(4)
Storage temperature range, Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 4.2 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
(3) Continuous clamp current per pin is ± 2 mA.
(4) Long-term high-temperature storage or extended use at maximum temperature conditions may result in a reduction of overall device life.
For additional information, see IC Package Thermal Metrics Application Report (literature number SPRA953) and Reliability Data for
TMS320LF24xx and TMS320F28xx Devices Application Report (literature number SPRA963).
4.2 Recommended Operating Conditions
MIN NOM
MAX
3.46
UNIT
(1)
Device supply voltage, I/O, VDDIO
3.14
1.71
3.3
1.8
V
Device supply voltage, Analog Subsystem, VDD18
(when internal VREG is disabled and 1.8 V is
supplied externally)
1.995
V
V
Device supply voltage, Master and Control
Subsystems, VDD12
(when internal VREG is disabled and 1.2 V is
supplied externally)
1.14
1.2
1.26
3.47
Supply ground, VSS
0
3.3
0
V
V
(1)
Analog supply voltage, VDDA
3.14
Analog ground, VSSA
V
Device clock frequency (system clock)
High-level input voltage, VIH (3.3 V)
Low-level input voltage, VIL (3.3 V)
High-level output source current, VOH = VOH(MIN) , IOH All GPIO/AIO pins
Group 2(2)
2
VDDIO * 0.7
VSS – 0.3
60
MHz
V
VDDIO + 0.3
VDDIO * 0.3
V
–4
–8
mA
mA
mA
mA
Low-level output sink current, VOL = VOL(MAX), IOL
All GPIO/AIO pins
Group 2(2)
4
8
Free-Air temperature, TA
T version
–40
–40
–40
–40
–40
–40
105
125
125
125
150
150
S version
°C
°C
Q version (Q100 qualification)
T version
Junction temperature, TJ
S version
Q version (Q100 qualification)
(1) VDDIO and VDDA should be maintained within approximately 0.3 V of each other.
(2) Group 2 pins are as follows: PD3_GPIO19, PE2_GPIO26, PE3_GPIO27, PH6_GPIO54, PH7_GPIO55, EMU0, TDO, EMU1,
PD0_GPIO16, AIO7, AIO4.
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4.3 Electrical Characteristics(1)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VDDIO * 0.8
VDDIO – 0.2
TYP
MAX UNIT
IOH = IOH MAX
IOH = 50 μA
VOH
VOL
High-level output voltage
Low-level output voltage
V
IOL = IOL MAX
VDDIO * 0.2
V
All GPIO/AIO
–140
–300
Pin with pullup
enabled
VDDIO = 3.3 V, VIN = 0 V
Input current
(low level)
XRS pin and ARS pin
IIL
μA
Pin with pulldown
enabled
VDDIO = 3.3 V, VIN = 0 V
VDDIO = 3.3 V, VIN = VDDIO
VDDIO = 3.3 V, VIN = VDDIO
VO = VDDIO or 0 V
±2
±2
50
±2
Pin with pullup
enabled
Input current
(high level)
IIH
μA
μA
Pin with pulldown
enabled
Output current, pullup or
pulldown disabled
IOZ
CI
Input capacitance
2
2.78
35
pF
V
VDDIO BOR trip point
VDDIO BOR hysteresis
Falling VDDIO
mV
Supervisor reset release
delay time
Time after BOR/POR/OVR event is removed to
XRS release
600
μs
VREG VDD18 output
VREG VDD12 output
Internal VREG18 on
Internal VREG12 on
1.8
1.2
V
V
(1) When the on-chip VREGs are used, their output is monitored by the POR/BOR circuits, which will reset the device should the core
voltages (VDD18, VDD12) go out of range.
112
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
5 Electrical Specifications
5.1 Current Consumption
Table 5-1. Current Consumption at 150-MHz C28x SYSCLKOUT and 75-MHz M3SSCLK(1)(2)
VREG ENABLED
VREG DISABLED
IDD12 IDDIO
TYP(5)
MODE
TEST CONDITIONS(3)
IDDIO
TYP(5)
IDDA
IDD18
IDDA
(4)
(4)
MAX
TYP(5)
MAX
TYP(5)
MAX
TYP(5)
MAX
MAX
TYP(5)
MAX
The following Cortex™-M3
peripherals are exercised:
•
•
•
•
•
•
•
•
•
•
•
I2C1
SSI1, SSI2
UART0, UART1, UART2
CAN0
USB
µDMA
Timer0, Timer1
µCRC
WDOG0, WDOG1
Flash
Internal Oscillator 1,
Internal Oscillator 2
The following C28x peripherals are
exercised:
•
•
•
McBSP
Operational
(RAM)
eQEP1, eQEP2
445 mA
TBD
32 mA
TBD
20 mA
TBD
367 mA
TBD
33 mA
TBD
32 mA
TBD
eCAP1, eCAP2,
eCAP3, eCAP4
•
•
•
•
•
•
•
SCI-A
SPI-A
I2C
DMA
VCU
FPU
Flash
The following Analog peripherals
are exercised:
•
•
ADC1, ADC2
Comparator 1,
Comparator 2,
Comparator 3,
Comparator 4,
Comparator 5,
Comparator 6
(1) Currently only typical current consumption data is available, maximum numbers will come in another release of this data sheet.
(2) The numbers in Table 5-1 are not assured at this time, and are subject to change.
(3) The following is done in a loop:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Code is running out of RAM.
All I/O pins are left unconnected.
All the communication peripherals are exercised in loop-back mode.
USB – Only logic is exercised by loading and unloading FIFO.
µDMA does memory-to-memory transfer.
DMA does memory-to-memory transfer.
VCU – CRC calculated and checked.
FPU – Float operations performed.
ePWM – 6 enabled and generates 150-kHz PWM output on 12 pins, HRPWM clock enabled.
Timers and Watchdog serviced.
eCAP in APWM mode generates 36.6-kHz output on 4 pins.
ADC performs continuous conversion.
FLASH is continuously read and in active state.
XCLKOUT is turned off.
(4) IDDIO current is dependent on the electrical loading on the I/O pins.
(5) The TYP numbers are applicable over room temperature and nominal voltage.
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Table 5-1. Current Consumption at 150-MHz C28x SYSCLKOUT and 75-MHz M3SSCLK(1)(2) (continued)
VREG ENABLED
VREG DISABLED
IDD12 IDDIO
TYP(5)
MODE
TEST CONDITIONS(3)
IDDIO
TYP(5)
IDDA
IDD18
IDDA
(4)
(4)
MAX
TYP(5)
MAX
TYP(5)
MAX
TYP(5)
MAX
MAX
TYP(5)
MAX
•
•
PLL is on.
Cortex™-M3 CPU is not
executing.
•
•
•
•
•
M3SSCLK is on.
SLEEP IDLE
80 mA
71 mA
24 mA
–
315 µA
–
14 mA
–
51 mA
–
15 mA
14 mA
3 mA
–
315 µA
–
C28CLKIN is on.
C28x™ CPU is not executing.
C28CPUCLK is off.
C28SYSCLK is on.
•
•
PLL is on.
Cortex™-M3 CPU is not
executing.
•
•
•
•
•
M3SSCLK is on.
SLEEP
STANDBY
–
210 µA
–
15 mA
–
42 mA
–
–
205 µA
–
C28CLKIN is off.
C28x™ CPU is not executing.
C28CPUCLK is off.
C28SYSCLK is off.
•
•
PLL is off.
Cortex™-M3 CPU is not
executing.
•
•
•
•
•
M3SSCLK is 32 kHz.
C28CLKIN is off.
DEEP SLEEP
STANDBY
–
200 µA
–
2 mA
–
19 mA
–
–
195 µA
–
C28x™ CPU is not executing.
C28CPUCLK is off.
C28SYSCLK is off.
NOTE
The peripheral-I/O multiplexing implemented in the device prevents all available peripherals
from being used at the same time because more than one peripheral function may share an
I/O pin. It is, however, possible to turn on the clocks to all the peripherals at the same time,
although such a configuration is not useful. If the clocks to all the peripherals are turned on
at the same time, the current drawn by the device will be more than the numbers specified in
the current consumption table.
5.2 Thermal Design Considerations
Based on the end-application design and operational profile, the IDD12, IDD18, and IDDIO currents could vary.
Systems that exceed the recommended maximum power dissipation in the end product may require
additional thermal enhancements. Ambient temperature (TA) varies with the end application and product
design. The critical factor that affects reliability and functionality is TJ, the junction temperature, not the
ambient temperature. Hence, care should be taken to keep TJ within the specified limits. Tcase should be
measured to estimate the operating junction temperature TJ. Tcase is normally measured at the center of
the package top-side surface. For more details about thermal metrics and definitions, see the
Semiconductor and IC Package Thermal Metrics Application Report (literature number SPRA953) and the
Reliability Data for TMS320LF24xx and TMS320F28xx Devices Application Report (literature number
SPRA963).
114
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5.3 Timing Parameter Symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the
symbols, some of the pin names and other related terminology have been abbreviated as follows:
Lowercase subscripts and their
meanings:
Letters and symbols and their
meanings:
a
c
d
access time
H
L
High
Low
cycle time (period)
delay time
V
Valid
Unknown, changing, or don't care
level
f
fall time
X
Z
h
r
hold time
High impedance
rise time
su
t
setup time
transition time
valid time
v
w
pulse duration (width)
5.3.1 General Notes on Timing Parameters
All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that
all output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual
cycles. For actual cycle examples, see the appropriate cycle description section of this document.
5.3.2 Test Load Circuit
This test load circuit is used to measure all switching characteristics provided in this document.
DATA SHEET
TESTER PIN ELECTRONICS
TIMING
REFERENCE
(A)
POINT
Z0 = 50 W
TD = 6 ns
25 W
15 W
TRANSMISSION LINE
DEVICE PIN(B)
20 pF
20 pF
OUTPUT
UNDER
TEST
CONCERTO DEVICE
A. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the
device pin.
B. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to
produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to
add or subtract the transmission line delay (2 ns or longer) from the data sheet timing.
Figure 5-1. 3.3-V Test Load Circuit
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5.4 Clock Frequencies, Requirements, and Characteristics
This section provides the frequencies and timing requirements of the input clocks; PLL lock times;
frequencies of the internal clocks; and the frequency and switching characteristics of the output clock.
5.4.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
Table 5-2 shows the frequency requirements for the input clocks to the F28M35x devices. Table 5-3
shows the input clock cycle time. Table 5-4, Table 5-5, Table 5-6, and Table 5-7 show the timing
requirements for the input clocks to the F28M35x devices. Table 5-8 shows the PLL lock times for the
Main PLL and the USB PLL. The Main PLL operates from the X1 or X1/X2 input clock pins, and the USB
PLL operates from the XCLKIN input clock pin.
Table 5-2. Input Clock Frequency
MIN
2
MAX UNIT
f(OSC)
f(OCI)
f(OCI)
f(XCI)
Frequency, X1/X2, from external crystal or resonator
Frequency, X1, from external oscillator (PLL enabled)
Frequency, X1, from external oscillator (PLL disabled)
Frequency, XCLKIN, from external oscillator
20
30
MHz
MHz
MHz
MHz
2
2
100
60
2
Table 5-3. Input Clock Cycle Time
NO.
C1
C2
C2
C3
MAX
MIN UNIT
tc(OSC)
tc(OCI)
tc(OCI)
tc(XCI)
Cycle time, X1/X2, from external crystal or resonator
Cycle time, X1, from external oscillator (PLL enabled)
Cycle time, X1, from external oscillator (PLL disabled)
Cycle time, XCLKIN, from external oscillator
500
500
500
500
50
33.3
10
ns
ns
ns
ns
16.6
Table 5-4. X1 Timing Requirements - PLL Enabled(1)
NO.
C4
C5
C6
C7
MIN
MAX UNIT
tf(OCI)
Fall time, X1
6
6
ns
ns
%
%
tr(OCI)
Rise time, X1
tw(OCL)
tw(OCH)
Pulse duration, X1 low as a percentage of tc(OCI)
Pulse duration, X1 high as a percentage of tc(OCI)
45
45
55
55
(1) The possible Main PLL configuration modes are shown in Table 2-19 to Table 2-22.
Table 5-5. X1 Timing Requirements - PLL Disabled
NO.
MIN
MAX UNIT
C4
tf(OCI)
Fall time, X1
Rise time, X1
Up to 20 MHz
6
2
ns
20 MHz to 100 MHz
Up to 20 MHz
C5
tr(OCI)
6
ns
20 MHz to 100 MHz
2
C6
C7
tw(OCL)
tw(OCH)
Pulse duration, X1 low as a percentage of tc(OCI)
Pulse duration, X1 high as a percentage of tc(OCI)
45
45
55
55
%
%
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
Table 5-6. XCLKIN Timing Requirements - PLL Enabled(1)
MIN
MAX UNIT
C8
C9
tf(XCI)
tr(XCI)
Fall time, XCLKIN
6
6
ns
ns
%
%
Rise time, XCLKIN
C10 tw(XCL)
C11 tw(XCH)
Pulse duration, XCLKIN low as a percentage of tc(XCI)
Pulse duration, XCLKIN high as a percentage of tc(XCI)
45
45
55
55
(1) The possible USB PLL configuration modes are shown in Table 2-23 and Table 2-24.
Table 5-7. XCLKIN Timing Requirements - PLL Disabled
NO.
MIN
MAX UNIT
C8
tf(XCI)
Fall time, XCLKIN
Rise time, XCLKIN
Up to 20 MHz
6
2
ns
20 MHz to 100 MHz
Up to 20 MHz
C9
tr(XCI)
6
ns
20 MHz to 100 MHz
2
C10 tw(XCL)
C11 tw(XCH)
Pulse duration, XCLKIN low as a percentage of tc(XCI)
Pulse duration, XCLKIN high as a percentage of tc(XCI)
45
45
55
55
%
%
Table 5-8. PLL Lock Times
MIN
NOM
MAX
UNIT
input clock
cycles
t(PLL)
t(USB)
Lock time, Main PLL (X1, from external oscillator)
2000(1)
2000(1)
input clock
cycles
Lock time, USB PLL (XCLKIN, from external oscillator)
(1) For example, if the input clock to the PLL is 10 MHz, then the PLL lock time is 100 ns x 2000 = 200 µs.
5.4.2 Internal Clock Frequencies
Table 5-9 provides the clock frequencies for the internal clocks of the F28M35x devices.
Table 5-9. Internal Clock Frequencies (150-MHz Devices)
MIN
NOM
MAX
UNIT
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
kHz
f(USB)
f(PLL)
f(OCK)
f(M3C)
f(ADC)
f(SYS)
f(HSP)
f(LSP)
f(10M)
f(32K)
Frequency, USBPLLCLK
Frequency, PLLSYSCLK
Frequency, OSCCLK
60
2
2
2
2
2
2
2
150
100
100(1)
Frequency, M3SSCLK
Frequency, ASYSCLK
Frequency, C28SYSCLK
Frequency, C28HSPCLK
Frequency, C28LSPCLK(2)
Frequency, 10MHzCLK
Frequency, 32KHzCLK
37.5
150(1)
150(1)
150(1)
37.5(3)
10
32
(1) An integer divide ratio must be maintained between the C28x and Cortex™-M3 clock frequencies. For example, when the C28x is
configured to run at a maximum frequency of 150 MHz, the fastest allowable frequency for the Cortex™-M3 will be 75 MHz. See
Figure 2-10 and Figure 2-11 to see the internal clocks and clock divider options.
(2) Lower LSPCLK will reduce device power consumption.
(3) This is the default reset value if C28SYSCLK = 150 MHz.
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5.4.3 Output Clock Frequency and Switching Characteristics
Table 5-10 provides the frequency of the output clock from the F28M35x devices. Table 5-11 shows the
switching characteristics of the output clock from the F28M35x devices, XCLKOUT.
Table 5-10. Output Clock Frequency
NO.
MIN
MAX UNIT
C14 f(XCO)
Frequency, XCLKOUT
2
37.5 MHz
Table 5-11. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)(1)(2)
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER
MIN
TYP
MAX
UNIT
ns
C15 tf(XCO)
C16 tr(XCO)
C17 tw(XCOL)
C18 tw(XCOH)
Fall time, XCLKOUT
Rise time, XCLKOUT
5
5
ns
Pulse duration, XCLKOUT low
Pulse duration, XCLKOUT high
H – 2
H – 2
H + 2
H + 2
ns
ns
(1) A load of 40 pF is assumed for these parameters.
(2) H = 0.5tc(XCO)
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5.5 Power Sequencing
There is no power sequencing requirement needed to ensure the device is in the proper state after reset
or to prevent the I/Os from glitching during power up and power down. (All I/Os, except for GPIO135, are
glitch-free during power up and power down.) No voltage larger than a diode drop (0.7 V) above VDDIO
should be applied to any digital pin (for analog pins, this value is 0.7 V above VDDA) prior to powering up
the device. Voltages applied to pins on an unpowered device can bias internal p-n junctions in unintended
ways and produce unpredictable results.
VDDIO, VDDA
(3.3 V)
VDD12, VDD18
X1/X2
tOSCST
(B)
(A)
XCLKOUT
User-code dependent
t
w(RSL1)
XRS(D)
Address/data valid, internal boot-ROM code execution phase
Address/Data/
Control
(Internal)
User-code execution phase
User-code dependent
t
d(EX)
(C)
h(boot-mode)
t
Boot-Mode
Pins
GPIO pins as input
Peripheral/GPIO function
Boot-ROM execution starts
(E)
Based on boot code
GPIO pins as input (state depends on internal PU/PD)
I/O Pins
User-code dependent
A. Upon power up, PLLSYSCLK is OSCCLK/8. Since the XCLKOUTDIV bits in the XCLK register come up with a reset
state of 0, PLLSYSCLK is further divided by 4 before PLLSYSCLK appears at XCLKOUT. XCLKOUT = OSCCLK/32
during this phase.
B. Boot ROM configures the SYSDIVSEL bits for /1 operation. XCLKOUT = OSCCLK/4 during this phase. Note that
XCLKOUT will not be visible at the pin until explicitly configured by user code.
C. After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code
branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in
debugger environment), the boot code execution time is based on the current M3SSCLK speed. The M3SSCLK will
be based on user environment and could be with or without PLL enabled.
D. Using the XRS pin is optional due to the on-chip power-on reset (POR) circuitry.
E. The internal pullup or pulldown will take effect when BOR is driven high.
Figure 5-2. Power-On Reset
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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Table 5-12. Reset (XRS) Timing Requirements
MIN
14000tc(M3C)
32tc(OCK)
MAX
UNIT
cycles
cycles
(1)
th(boot-mode)
tw(RSL2)
Hold time for boot-mode pins
Pulse duration, XRS low on warm reset
(1) The minimum hold time for boot mode pins is 23 times longer for silicon revision 0 devices.
Table 5-13. Reset (XRS) Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
600
MAX
UNIT
μs
tw(RSL1)
tw(WDRS)
td(EX)
Pulse duration, XRS driven by device
Pulse duration, reset pulse generated by watchdog
Delay time, address/data valid after XRS high
Start up time, internal zero-pin oscillator
On-chip crystal-oscillator start-up time
512tc(OCK)
32tc(OCK)
3
cycles
cycles
μs
tINTOSCST
(1)
tOSCST
1
10
ms
(1) Dependent on crystal/resonator and board design.
X1/X2
XCLKOUT
User-Code Dependent
t
w(RSL2)
XRS
User-Code Execution Phase
t
d(EX)
Address/Data/
User-Code Execution
Control
(Internal)
(A)
t
Boot-ROM Execution Starts
GPIO Pins as Input
h(boot-mode)
Boot-Mode
Pins
Peripheral/GPIO Function
User-Code Dependent
Peripheral/GPIO Function
User-Code Execution Starts
I/O Pins
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
A. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code
branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in
debugger environment), the Boot code execution time is based on the current M3SSCLK speed. The M3SSCLK will
be based on user environment and could be with or without PLL enabled.
Figure 5-3. Warm Reset
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
5.5.1 Changing the Frequency of the Main PLL
Figure 5-4 shows how to change the frequency of the Main PLL. The three steps are described below:
1. The PLL must first be placed in bypass mode (by writing to the SYSPLLCTL register) before any
changes are made to the SPLLIMULT and SPLLFMULT fields of the SYSPLLMULT Register. Figure 5-
4 shows that before being placed in bypass mode, the internal PLLSYSCLK clock was operating at
100 MHz. After entering the bypass mode, the PLLSYSCLK becomes 10 MHz, which is the frequency
of OSCCLK, the input clock to the PLL
2. Once the PLL is placed in bypass mode, the SYSPLLMULT register can be modified to increase the
PLLSYSCLK frequency to 150 MHz. See Figure 5-4 for the settings of the SPLLIMULT (integer) and
SPLLFMULT (fractional) multiply fields of the SYSPLLMULT register for this step, and see Figure 2-8
for the functional description of the Main PLL. The PLL bypass mode must be maintained for at least
2000 OSCCLK cycles in order for the PLL to properly lock to the new frequency.
3. Finally, the SYSPLLCTL register is written to again, this time to take the PLL out of the bypass mode.
Following this step, the PLLSYSCLK switches over from 10 MHz to the new frequency of 150 MHz.
STEP 1
STEP 2
STEP 3
WRITE TO SYSPLLCTL
REGISTER TO PUT PLL
IN BYPASS MODE
WRITE TO SYSPLLMULT
REGISTGER TO CHANGE PLL
MULTIPLIER CONFIGURATION
WRITE TO SYSPLLCTL
REGISTER TO TAKE PLL
OUT OF BYPASS MODE
PLLSYSCLK
10 MHz
100 MHz
150 MHz
(MINIMUM 2000 OSCCLK CYCLES)
INPUT CLK TO
PLL IS OSCCLK
OSCCLK BYPASSES
THE PLL
INPUT CLK TO
PLL IS OSCCLK
SYSPLLMULT REG
10 MHz
10 MHz
10 MHz
SYSPLLMULT REG
SPLLIMULT = 40
SPLLFMULT = 2
PLL OUTPUT / 2
SYSDIVSEL = 0
10 MHz x 40 =
400 MHz / 2 =
200 MHz / 2 =
100 MHz / 1 =
10 MHz x 60 =
600MHz / 2 =
300 MHz / 2 =
150 MHz / 1 =
SPLLIMULT = 60
SPLLFMULT = 2
PLL OUTPUT / 2
SYSDIVSEL = 0
100 MHz / 1 =
10 MHz
SYSDIVSEL REG
100 MHz
150 MHz
SYSDIVSEL REG
PLLSYSCLK
BEFORE THE
CHANGE
PLLSYSCLK
DURING THE
CHANGE
PLLSYSCLK
AFTER THE
CHANGE
Figure 5-4. Changing the Frequency of the Main PLL
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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5.5.2 Power Management and Supervisory Circuit Solutions
Table 5-14 lists the power management and supervisory circuit solutions for F28M35x devices. LDO
selection depends on the total power consumed in the end application. Go to www.ti.com and click on
Power Management for a complete list of TI power ICs or select the Power Management Selection Guide
link for specific power reference designs.
Table 5-14. Power Management and Supervisory Circuit Solutions
SUPPLIER
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
TYPE
DC/DC
DC/DC
LDO
PART
DESCRIPTION
TPS62160/170
TPS62140/150
TPS7A8001
TPS7A7001
TPS75005
1/0.5-A, 3–17-V input, step-down converter in 2x2 QFN package
2/1-A, 3–17-V input, step-down converter in 3x3 QFN package
Low-noise, high-bandwidth PSRR, 1A low-dropout linear regulator
2A, single-output, very-low input, adjustable low-dropout linear regulator
Dual, 500-mA, low-dropout regulators and triple-voltage rail monitor
LDO
LDO/SVS
DC/DC
LM22672/1
1/0.5-A, 4.5–42-V input SIMPLE SWITCHER®, step-down voltage regulator
with features
Texas Instruments
Texas Instruments
Texas Instruments
DC/DC
Module
SVS
TPS54160/060
LMZ10501
3.5-V to 60-V input, 1.5/0.5-A step-down converter with Eco-Mode
1A SIMPLE SWITCHER® Nano Module with 5.5-V maximum input voltage
TPS386000/040
Quad supply voltage supervisors with programmable delay and watchdog
timer
Texas Instruments
Texas Instruments
LDO
LDO
TPS73719
TPS73534
Single-output LDO, 1-A, fixed (1.9-V), reverse-current protection
Single-output LDO, 500-mA, fixed (3.4-V), low-quiescent current, low-noise,
high PSRR
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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6 Peripheral Information and Timings
6.1 Analog and Shared Peripherals
Concerto Shared Peripherals are accessible from both the Master Subsystem and the Control Subsystem.
The Analog Shared Peripherals include two 12-bit ADCs (Analog-to-Digital Converters), and six
Comparator + DAC (10-bit) modules. The ADC Result Registers are accessible by CPUs and DMAs of the
Master and Control Subsystems. All other analog registers, such as the ADC Configuration and
Comparator Registers, are accessible by the C28x CPU only. The Digital Shared Peripherals include the
Inter-Processor Communications (IPC) peripheral and the External Peripheral Interface (EPI). IPC is
accessible by both CPUs; EPI is accessible by both CPUs and both DMAs.
IPC is used for sending and receiving synchronization events between Master and Control subsystems to
coordinate execution of software running on both processors, or exchanging of data between the two
processors. EPI is used by this device to communicate with external memory and other devices.
6.1.1 Analog-to-Digital Converter (ADC)
Figure 6-1 shows the internal structure of each of the two ADC peripherals that are present on Concerto.
Each ADC has 16 channels that can be programmed to select analog inputs, select start-of-conversion
trigger, set the sampling window, and select end-of-conversion interrupt to prompt a CPU or DMA to read
16 result registers. The 16 ADC channels can be used independently or in pairs, based on the
assignments inside the SAMPLEMODE register. Pairing up the channels allows two analog inputs to be
sampled simultaneously—thereby, increasing the overall conversion performance.
6.1.1.1 Sample Mode
Each ADC has 16 programmable channels that can be independently programmed for analog-to-digital
conversion when corresponding bits in the SAMPLEMODE register are set to Sequential Mode. For
example, if bit 2 in the SAMPLEMODE register is set to 0, ADC channels 4 and 5 are set to sequential
mode. Both the SOC4CTL and SOC5CTL registers can then be programmed to configure channels 4 and
5 to independently perform analog-to-digital conversions with results being stored in the RESULT4 and
RESULT5 registers. "Independently" means that channel 4 may use a different Start-Of-Conversion (SOC)
trigger, different analog input, and different sampling window than the trigger, input, and window assigned
to channel 5.
The 16 programmable channels for each ADC may also be grouped in 8 channel pairs when
corresponding bits in the SAMPLEMODE register are set to Simultaneous Mode. For example, if bit 2 in
the SAMPLEMODE register is set to 1, ADC channels 4 and 5 are set to Simultaneous Mode. The
SOC4CTL register now contains configuration parameters for both channel 4 and channel 5, and the
SOC5CTL register is ignored. While channel 4 and channel 5 are still using dedicated analog inputs (now
selected as pairs in the CHSEL field of SOC4CTL), they both share the same SOC trigger and Sampling
Window, with the results being stored in the RESULT4 and RESULT5 registers.
The Simultaneous mode is made possible by two sample-and-hold units present in each ADC. Each
sample-and-hold unit has its own mux for selecting analog inputs (see Figure 6-1). By programming the
SAMPLEMODE register, the 16 available channels can be configured as 16 independent channels,
8 channel pairs, or any combination thereof (for example, 10 sequential channels and 3 simultaneous
pairs).
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F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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ADC_INT(8:1)
TRIGS(8:1)
INTSOCSEL1 REG
INTSOCSEL2 REG
ADCINT1
ADCINT2
SOC0CTL REG
SOC1CTL REG
SOC2CTL REG
SOC3CTL REG
SOC4CTL REG
SOC5CTL REG
SOC6CTL REG
SOC7CTL REG
SOC8CTL REG
SOC9CTL REG
SOC10CTL REG
SOC11CTL REG
SOC12CTL REG
SOC13CTL REG
SOC14CTL REG
SOC15CTL REG
INTSEL1N2 REG
INTSEL3N4 REG
INTSEL5N6 REG
INTSEL7N8 REG
INTFLG REG
INTFLGCLR REG
INTOVF REG
SOCFLG REG
SOCFRC REG
SOCOVF REG
ADC INTERUPT
CONTROL
SOCx TRIGGER
CONTROL
INTOVFCLR REG
SOCOVFCLR REG
SOCPRICTL REG
EOC(15:0)
SOC(15:0)
SAMPLEMODE REG
ADC CONTROL
4
ASEL
SHSEL
SOC
REGSEL
ANALOG BUS
ADC_INA0
0
1
2
3
4
5
6
7
N/C
ADC_INA2
ADC_INA3
ADC_INA4
RESULT0 REG
RESULT1 REG
RESULT2 REG
RESULT3 REG
RESULT4 REG
RESULT5 REG
RESULT6 REG
RESULT7 REG
RESULT8 REG
RESULT9 REG
RESULT10 REG
RESULT11 REG
RESULT12 REG
RESULT13 REG
RESULT14 REG
RESULT15 REG
N/C
ADC_INA6
ADC_INA7
S / H
A
A
STORE
RESULT
12-BIT ADC
CONVERTER
ADCCTL1 REG
VREFLOCONV
BSEL
S / H
B
0
1
2
3
4
5
6
7
B
ADC_INB0
N/C
N/C
ADCCTL1 REG
REFTRIM REG
OFFTRIM REG
REV REG
ADC_INB3
ADC_INB4
VREFLO 1
N/C
ADC_INB7
(1) CURRENTLY DEFAULT IS “NO CONNECT”, CHANGE ADDCCTL1 REGISTER TO CONNECT TO VREFLO
Figure 6-1. ADC
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
6.1.1.2 Start-of-Conversion (SOC) Triggers
There are eight external SOC triggers that go to each of the two ADC modules (from the Control
Subsystem). In addition to the eight external SOC triggers, there are also two internal SOC triggers
derived from End-Of-Conversion (EOC) interrupts inside each ADC module (ADCINT1 and ADCINT2).
Registers INTSOCSEL1 and 2 are used to configure each of the 16 ADC channels for internal or external
SOC sources. If internal SOC is chosen for a given channel, the INTSOCSEL1 and 2 registers also select
whether the internal source is ADCINT1 or ADCINT2. If external SOC is chosen for a given ADC channel,
the TRIGSEL field of the corresponding SOCxCTL register selects which of the eight external triggers is
used for SOC in that channel. One analog-to-digital conversion can be performed at a time by the 12-bit
ADC. The analog-to-digital conversion priority is managed according to the state of the PRICTL register.
6.1.1.3 Analog Inputs
Analog inputs to each of the two ADC modules are organized in two groups—A and B, with each group
having a dedicated mux and sample-and-hold unit (see Figure 6-1). Mux A selects one of six possible
analog inputs via AIO MUX. Mux B selects one of five possible analog inputs—four external inputs via AIO
MUX, and one from the internal VREFLO signal, which is currently tied to the Analog Ground. The Mux A
and Mux B inputs can be simultaneously or sequentially sampled by the two sample-and-hold units
according to the sampling window chosen in the SOCxCTL register for the corresponding channel.
6.1.1.4 ADC Result Registers and EOC Interrupts
Concerto analog-to-digital conversion results are stored in 32 Results Registers (16 for ADC1 and 16 for
ADC2). The 16 ADCx channels can be programmed via the INTSELxNy registers to trigger up to eight
ADCINT interrupts per ADC module, when their results are ready to be read. The eight ADCINT interrupts
from ADC1 and the eight ADCINT interrupts from ADC2 are AND-ed together before propagating to both
the Master Subsystem and the Control Subsystem, announcing that the Result Registers are ready to be
read by a CPU or DMA (see Figure 2-3).
6.1.2 Comparator + DAC Units
Figure 6-2 shows the internal structure of the six analog Comparator + DAC units present in Concerto
devices. Each unit compares two analog inputs (A and B) and assigns a value of ‘1’ when the voltage of
the A input is greater than that of the B input, or a value of ‘0’ when the opposite is true. The six A inputs
and two B inputs come from AIO_MUX1 and AIO_MUX2. All six B inputs can also be provided by the 10-
bit digital-to-analog units that are present in each comparator DAC. The 10-bit value for each DAC unit is
programmed in the respective DACVAL register. Another comparator register, COMPCTL, can be
programmed to select the source of the B input, to enable or disable the comparator circuit, to invert
comparator output, to synchronize comparator output to C28x SYSCLK, and to select the qualification
period (number of clock cycles). All six output signals from the six comparators can be routed out to the
device pins via GPIO_MUX2 pin mux.
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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AIO_MUX1
COMPA(1)
GPIO_MUX2
COMPOUT(1)
COMP1
DAC1
N/C
4
4
COMP2
COMPCTL REG
COMPSOURCE
COMPDACE
COMPINV
QUALSEL
SYNCSEL
1
0
COMPA(2)
COMPB(2)
+
0
1
COMPOUT(2)
10
COMP2
_
1
0
SYNC / QUAL
VDDA
VSSA
10-BIT
DAC2
V
C28SYSCLK
COMPSTS
COMPSTS REG
V = ( DACVAL * ( VDDA-VSSA ) ) / 1023
DACVAL(8:0)
DACVAL REG
COMP = 0 WHEN VOLTAGE A < VOLTAGE B
COMP = 1 WHEN VOLTAGE A > VOLTAGE B
COMPA(3)
COMPOUT(3)
COMP3
DAC3
N/C
8
AIO_MUX2
COMPA(4)
COMPOUT(4)
COMPOUT(5)
COMPOUT(6)
COMP4
COMP5
COMP6
DAC4
DAC5
DAC6
N/C
4
COMPA(5)
COMPB(5)
10
COMPA(6)
N/C
Figure 6-2. Comparator + DAC Units
126
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F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
6.1.3 Inter-Processor Communications (IPC)
Figure 6-3 shows the internal structure of the IPC peripheral used to synchronize program execution and
exchange of data between the Cortex™-M3 and the C28x CPU. IPC can be used by itself when
synchronizing program execution or it can be used in conjunction with Message RAMs when coordinating
data transfers between processors. In either case, the operation of the IPC is the same. There are two
independent sides to the IPC peripheral—MTOC (Master to Control) and CTOM (Control to Master).
The MTOC IPC is used by the Master Subsystem to send events to the Control Subsystem. The MTOC
IPC typically sends events to the Control Subsystem by using the following registers: MTOCIPCSET,
MTOCIPCFLG/MTOCIPCSTS (1), and MTOCIPCACK. Each of the 32 bits of these registers represents 32
independent channels through which the Cortex™-M3 CPU can send up to 32 events to the C28x CPU
via software handshaking. Additionally, the first 4 bits of the MTOCIPC registers are supplemented with
interrupts. To send an event via channel 2 from Cortex™-M3 to C28x, for example, the Cortex™-M3 and
C28x CPUs use bit 2 of the MTOCIPCSET, MTOCIPCFLG/MTOCIPCSTS, MTOCIPCACK registers. The
handshake starts with the Cortex™-M3 polling bit 2 of the MTOCIPCFLG register to make sure bit 2 is ‘0’.
Next, the Cortex™-M3 writes a ‘1’ into bit 2 of the MTOCIPCSET register to start the handshake. In the
mean time, the C28x is continually polling the MTOCIPCSTS register while waiting for the message. As
soon as the Cortex™-M3 writes ‘1’ to bit
2
of the MTOCIPCSET register, bit
2
of
MTOCIPCFLG/MTOCIPCSTS also turns ‘1’, thus announcing the event to the C28x. As soon as the C28x
CPU reads a ‘1’ from the MTOCIPCSTS register, the C28x CPU should acknowledge by writing a ‘1’ to bit
2 of the MTOCIPCACK register, which in turn, clears bit 2 of the MTOCIPCFLG/MTOCIPCSTS register,
enabling the Cortex™-M3 to send another message. Since the first four channels (bits 0, 1, 2, 3) are
backed up by interrupts, both processors in the above example can use IPC interrupt 2 instead of polling
to increase performance.
A similar handshake is also used when sending data (not just event) from the Master Subsystem to the
Control Subsystem, but with two additional steps. Before setting a bit in the MTOCIPCSET register, the
Cortex™-M3 should first load the MTOC Message RAM with a block of data that is to be made available
to the C28x. In the second additional step, the C28x should read the data before setting a bit in the
MTOCIPCACK register. This way, no data gets lost during multiple data transfers through a given block of
the message RAM.
The CTOM IPC is used by the Control Subsystem to send events to the Master Subsystem. The CTOM
IPC typically sends events to the Master Subsystem by using the following three registers: CTOMIPCSET,
CTOMIPCFLG/CTOMIPCSTS, and CTOMIPCACK. The process is exactly the same as that for the MTOC
IPC communication above.
(1) Note that physically MTOCIPCFLG/MTOCIPCSTS is one register, but it is referred to as the MTOCIPCFLG register when the Cortex™-
M3 CPU reads it, and as the MTOCIPCSTS register when the C28x CPU reads it.
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
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CTOM
IPC
INTRS
STS(3:0)
M3
NVIC
INT
CPU
(3:0)
WRDATA
(31:0)
RDDATA
(31:0)
SET(31:0)
FLG(31:0)
STS(31:0)
ACK(31:0)
M3 SYSTEM BUS
M3
32 MTOC IPC CHANNELS
3
4
ACK
STS
FLG
SET
MTOCIPCSET REG
MTOC IPC
CTOMIPCSACK REG
SYNC HANDSHAKE
FOR ONE OF 32
. . .
SET REG 31
FLG REG 31
31
0
1
2
C28
MTOC CHANNELS
. . .
. . .
0
0
STS REG
ACK REG
MTOC MSG RAM
PHYSICALLY THIS IS ONE REGISTER
PHYSICALLY THIS IS ONE REGISTER
WITH TWO DIFFERENT NAMES – FLG
FOR THE C28 AND STS FOR THE M3
MTOCIPCFLG REG
MTOCIPCSTS REG
CTOMIPCSTS REG
CTOMIPCSFLG REG
WITH TWO DIFFERENT NAMES – FLG
FOR THE M3 AND STS FOR THE C28
. . .
31
0
0
0
ACK REG
STS REG
CTOM IPC
CTOM MSG RAM
. . .
. . .
FLG REG 31
SET REG 31
SYNC HANDSHAKE
FOR ONE OF 32
MTOC CHANNELS
M3
1
2
MTOCIPCACK REG
CTOMIPCSET REG
SET
FLG
STS
ACK
3
4
C28
32 CTOM IPC CHANNELS
C28 CPU BUS
RDDATA
(31:0)
ACK(31:0)
STS(31:0)
FLG(31:0)
SET(31:0)
WRDATA
(31:0)
MTOC
IPC
STS(3:0)
INTRS
C28x
CPU
PIE
INT
(3:0)
Figure 6-3. Interprocessor Communications (IPC)
128
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
6.1.4 External Peripheral Interface (EPI)
The External Peripheral Interface (EPI) provides a high-speed parallel bus for interfacing external
peripherals and memory. EPI is accessible from both the Master Subsystem and the Control Subsystem.
EPI has several modes of operation to enable glueless connectivity to most types of external devices.
Some EPI modes of operation conform to standard microprocessor address/data bus protocols, while
others are tailored to support a variety of fast custom interfaces, such as those communicating with field-
programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs).
The EPI peripheral can be accessed by the Cortex™-M3 CPU, the Cortex™-M3 DMA, the C28x CPU, and
the C28x DMA over the high-performance AHB bus. The Cortex™-M3 CPU and the µDMA drive AHB bus
cycles directly through the Cortex™-M3 Bus Matrix. The C28x CPU and DMA also connect to the
Cortex™-M3 Bus Matrix, but not directly. Before entering the Cortex™-M3 Bus Matrix, the native C28x
CPU and DMA bus cycles are first converted to AHB protocol inside the MEM32-to-AHB Bus Bridge. After
that, they pass through the Frequency Gasket to reduce the bus frequency by a factor of 2 or 4. Inside the
Cortex™-M3 Bus Matrix, the Cortex™-M3 bus cycles may have to compete with C28x bus cycles for
access to the AHB bus on the way to the EPI peripheral. See Figure 6-4 to see how EPI interfaces to the
Concerto Master Subsystem, the Concerto Control Subsystem, Resets, Clocks, and Interrupts.
NOTE
The Control Subsystem has no direct access to EPI in silicon revision 0 devices.
Depending on how the Real-Time Window registers are configured inside the Bus Matrix, the arbitration
between the Cortex™-M3 and C28x bus cycles is fixed-priority with Cortex™-M3 having higher priority
than C28x, or the C28x having the option to own the Bus Matrix for a fixed period of time
(window)—effectively stalling all Cortex™-M3 accesses during that time. Another EPI register inside the
Cortex™-M3 Bus Matrix is the Memory Protection Register, which enables assignments of chip-select
spaces to Cortex™-M3 or C28x EPI accesses (or both). The assignments of chip-select spaces prevent a
bus cycle (from any processor) that does not own a given chip-select space, from getting through to EPI.
The Real-time Window registers are the only EPI-related registers that are configurable by the C28x. The
Memory Protection Register is configurable only by the Cortex™-M3 CPU, as are all configuration
registers inside the EPI peripheral. Figure 6-4 shows the EPI registers and how they relate to individual
blocks within the EPI.
Once a bus cycle arrives at the AHB bus interface inside the EPI peripheral, the bus cycle is routed to the
General-Purpose Block, SDRAM Block, or the Host Bus Module, depending on the operating mode
chosen through the EPI Configuration Register. Write cycles are buffered in a 4-word-deep Write FIFO;
therefore, in most cases, the write cycles do not stall the CPU or DMA unless the Write FIFO becomes
full. Read cycles can be handled in two different ways: blocking read cycles and non-blocking read cycles.
Blocking read cycles are implemented when the content of a Read Data Register is 0. Blocking reads stall
the CPU or DMA until the bus transaction completes. Non-blocking read cycles are triggered when a non-
zero value is written into a Read Data Register. A non-zero value being written into a Read Data register
triggers EPI to autonomously perform multiple data reads in the background (without involving CPU or
DMA) according to values stored inside the Read Address Register and the Read Size Register. The
incoming data is then temporarily stored in the Non-Blocking Read (NBR) FIFO until an EPI interrupt is
generated to prompt the CPU or DMA to read the FIFO without risk of stalling. Furthermore, EPI has
actually two sets of Data/Address/Size registers (set 0 and set 1) to enable ping-pong operation of non-
blocking reads. In a ping-pong operation, while the previously fetched data is being read by the CPU or
DMA from one end of the NBR FIFO, the next set of data words is simultaneously being deposited into the
other end of the NBR FIFO.
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
EPI
42 PINS
EPI MUX
GENERAL PURPOSE INTERFACE
SDRAM INTERFACE
SDRAMCFGREG
HOST BUS INTERFACE
GPCONFIGREG
GPCONFIG2REG
HB-8CONFIGREG
HB-16CONFIGREG
HB-16CONFIG2REG
16-BIT MODE
EPI CONFIG REG
EPI STATUS REG
GPIO_MUX1
HB-8CONFIG2REG
8-BIT MODE
EPI RD SIZE0 REG
EPI RD ADDR0 REG
EPI RD DATA0 REG
EPI INTERRUPT
4X32 WR FIFO
8X32 NBR FIFO
READ FIFO ALIAS 1
READ FIFO ALIAS 2
READ FIFO ALIAS 3
READ FIFO ALIAS 4
READ FIFO ALIAS 5
READ FIFO ALIAS 6
READ FIFO ALIAS 7
INT MASK REG
MASK INT STAT REG
RAW INT STAT REG
ERR INT STAT/CLR
WR FIFO CNT REG
READ FIFO CNT REG
READ FIFO REG
EPI NON-BLOCKING
ACCESS REGISTERS
FIFO LEVEL SEL REG
EPI RD SIZE0 REG
EPI RD ADDR0 REG
EPI RD DATA1 REG
INTERRUPT
SOURCES
FIFO READ
NON-FIFO READ
(BLOCKING)
EPI CLK
EPI RST
(NON-BLOCKING)
WRITE
BAUD RATE CONTROL
AHB BUS INTERFACE
EPI ADDRMAPREG
EPI BAUD REG
M3SSCLK
M3SYSRST
AHB BUS
APB BUS
MEMORY PROTECTION LOGIC ASSIGNS CS
SPACES TO C28 ONLY, M3 ONLY, OR BOTH
EPI REQ
MEMPROT REG
RTWEPIREG REG
RTWEPICNTR REG
RTWEPIWD REG
CEPISTATUS REG
M3
M3 CLOCKS
RESETS
M3
NVIC
EPI
CPU
M3 BUS
MATRIX
uDMA
CHAN 20
CHAN 22
VECT# 69
REAL-TIME WINDOW MODE
ALLOWS UN-INTERRUPTED ACCESS
TO EPI FROM C28 CPU/DMA, WHILE
STALLING M3 CPU/DMA CYCLES
FREQ
INT12/INTx.6
EPI
GASKET
MEM32
TO AHB
BUS
MEM32 TO AHB BUS BRIDGE
C28
C28
CPU
THE M3 FREQUENCY GASKET REDUCES AHB
BUS ACCESS FREQUENCY FOR C28 CPU/DMA
CYCLES BY FACTOR OF 2 OR FACTOR OF 4
PIE
CONVERTS C28 CPU/DMA BUS
CYCLES TO M3 AHB BUS CYCLES
DMA
BRIDGE
Figure 6-4. External Peripheral Interface (EPI)
130
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
EPI can directly interrupt the Cortex™-M3 CPU, the Cortex™-M3 uDMA, and the C28x CPU (but not the
C28x DMA) via the EPI interrupt. Typically, EPI interrupts are used to prompt the CPU or DMA to move
data to and from EPI. There are four EPI Interrupt registers that control various facets of interrupt
generation, clearing, and masking. The EPI Interrupt can trigger µDMA to perform reads and writes
through DMA Channels 20 and 22. If a CPU is the intended recipient, the Cortex™-M3 CPU is interrupted
by Nested Vectored Interrupt Controller (NVIC) vector 69, and the C28x CPU is interrupted through the
INT12/INTx6 vector to the PIE.
During EPI bus cycles, addresses entering the EPI module can propagate unchanged to the pins, or be
remapped to different addresses according to values stored in the EPI Address Map Register in
conjunction with the most significant bit of the incoming address.
The EPI's three primary operating modes are: the General-Purpose Mode, the SDRAM Mode, and the
Host Bus Mode (including 8-bit and 16-bit versions).
6.1.4.1 EPI General-Purpose Mode
The EPI General-Purpose Mode is designed for high-speed clocked interfaces such as ones
communicating with FPGAs and CPLDs. The high-speed clocked interfaces are different from the slower
Host Bus interfaces, which have more relaxed timings that are compatible with established protocols like
ones used to communicate with 8051 devices. Support of bus cycle framing and precisely controlled
clocking are the additional features of the General-Purpose Mode that differentiate the General-Purpose
Mode from the 8-bit and 16-bit Host Bus Modes.
Framing allows multiple bus transactions to be grouped together with an output signal called FRAME. The
slave device responding to the bus cycles may use this signal to recognize related words of data and to
speed up their transfers. The frame lengths are programmable and may vary from 1 to 30 clocks,
depending on the clocking mode used.
Precise clocking is accomplished with a dedicated clock output pin (CLK). Devices responding the bus
cycles can synchronize to CLK for faster transfers. The clock frequency can be precisely controlled
through the Baud Rate Control block. This output clock can be gated or free-running. A gated approach
uses a setup-time model in which the EPI clock controls when bus transactions are starting and stopping.
A free-running EPI clock requires another method for determining when data is live, such as the frame pin
or RD/WR strobes.
These and numerous other aspects of the General-Purpose Mode are controlled through the General-
Purpose Configuration Register and the General-Purpose Configuration2 Register. The clocking for the
General-Purpose Mode is configured through the EPI Baud Register of the EPI Baud Rate Control block.
See Figure 6-5 for a snapshot of the General-Purpose Mode registers, modes, and features. For more
detailed maps of the General-Purpose Mode, see Table 6-1.
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www.ti.com
EPI CONFIG REG
GP CONFIG REG
MODE = GEN PURP
ASIZE = 3
ASIZE = 2
ASIZE = 1
ASIZE = 0
DSIZE = 0
DSIZE = 1
DSIZE = 2
DSIZE = 3
ADDRESS
RANGE
DATA
SIZE
FRAME
SIGNAL
READY
SIGNAL
FRMPIN = 1
RDYEN = 1
RDYEN = 0
A0 – A18
A0 – A18
8
8
YES
YES
YES
NO
FRMPIN = 1
RDYEN = 1
RDYEN = 0
A0 – A19
A0 – A19
8
8
NO
NO
YES
NO
FRMPIN = 1
RDYEN = 1
RDYEN = 0
A0 – A10
A0 – A10
16
16
YES
YES
YES
NO
FRMPIN = 1
RDYEN = 1
RDYEN = 0
A0 – A11
A0 – A11
16
16
NO
NO
YES
NO
FRMPIN = 1
RDYEN = 1
RDYEN = 0
A0 – A2
A0 – A2
24
24
YES
YES
YES
NO
FRMPIN = 1
RDYEN = 1
RDYEN = 0
A0 – A3
A0 – A3
24
24
NO
NO
YES
NO
FRMPIN = X
RDYEN = X
N/A
32
NO
NO
Figure 6-5. EPI General-Purpose Modes
132
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
Table 6-1. EPI MODES – General-Purpose Mode (EPICFG/MODE = 0x0)
EPI PORT NAME
EPI SIGNAL FUNCTION
General-Purpose General-Purpose General-Purpose General-Purpose
DEVICE PIN
Accessible by
Cortex™-M3
Accessible by
C28x
(Available GPIOMUX_1
Muxing Choices for EPI)
Signal
Signal
Signal
Signal
(D8, A20)
(D16, A12)
(D24, A4)
(D30, No Addr)
EPI0S0
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
A4
A5
A6
A7
D0
D1
D0
D1
D0
D1
PH3_GPIO51
EPI0S1
EPI0S2
EPI0S3
EPI0S4
EPI0S5
EPI0S6
EPI0S7
EPI0S8
EPI0S9
EPI0S10
EPI0S11
EPI0S12
EPI0S13
EPI0S14
EPI0S15
PH2_GPIO50
PC4_GPIO68
PC5_GPIO69
PC6_GPIO70
PC7_GPIO71
PH0_GPIO48
PH1_GPIO49
PE0_GPIO24
PE1_GPIO25
PH4_GPIO52
PH5_GPIO53
PF4_GPIO36
PG0_GPIO40
PG1_GPIO41
PF5_GPIO37
D2
D2
D2
D3
D3
D3
D4
D4
D4
D5
D5
D5
D6
D6
D6
D7
D7
D7
D8
D8
D8
D9
D9
D9
D10
D11
D12
D13
D14
D15
D10
D11
D12
D13
D14
D15
D10
D11
D12
D13
D14
D15
EPI0S16
EPI0S17
EPI0S18
EPI0S19
EPI0S20
EPI0S21
EPI0S22
EPI0S23
EPI0S24
EPI0S25
EPI0S26
EPI0S27
EPI0S28
EPI0S29
EPI0S30
EPI0S31
A8
A9
A0
A1
D16
D17
D18
D19
D29
D21
D22
D23
A0
D16
D17
D18
D19
D29
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
PJ0_GPIO56
PJ1_GPIO57
PJ2_GPIO58
PD4_GPIO20
PD2_GPIO18
PD3_GPIO19
PB5_GPIO13
PB4_GPIO12
PE2_GPIO26
PE3_GPIO27
PH6_GPIO54
PH7_GPIO55
PD5_GPIO21
PD6_GPIO22
PD7_GPIO23
PG7_GPIO47
A10
A2
A11
A3
PJ3_GPIO59
A12
A4
A13
A5
A14
A6
A15
A7
A16
A8
A17
A9
A1
A18
A10
A11/RDY
WR
RD
A2
A19/RDY
WR
A3/RDY
WR
PJ4_GPIO60
PJ5_GPIO61
PJ6_GPIO62
RD
RD
FRAME
CLK
FRAME
CLK
FRAME
CLK
EPI0S32
EPI0S33
EPI0S34
EPI0S35
EPI0S36
EPI0S37
EPI0S38
EPI0S39
EPI0S40
EPI0S41
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
PF2_GPIO34
PF3_GPIO35
PE4_GPIO28
PE5_GPIO29
PB7_GPIO15
PB6_GPIO14
PF6_GPIO38
PG2_GPIO42
PG5_GPIO45
PG6_GPIO46
PC0_GPIO64
PC1_GPIO65
PC3_GPIO67
PC2_GPIO66
PE4_GPIO28
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6.1.4.2 EPI SDRAM Mode
The EPI SDRAM Mode combines high performance, low cost, and low pin utilization to access up to
512 megabits (Mb) of external memory. Main features of the EPI SDRAM interface are:
•
•
•
•
•
Supports x16 (single data rate) SDRAM
Supports low-cost SDRAMs up to 64 megabytes (MB) [or 512Mb]
Includes automatic refresh and access to all banks, rows
Includes Sleep/Standby Mode to keep contents active with minimal power drain
Multiplexed address/data interface for reduced pin count
See Figure 6-6 for a snapshot of the SDRAM Mode registers and supported memory sizes. For more
detailed maps of the SDRAM Mode, see Table 6-2.
EPI CONFIG REG
SDRAM CFG REG
SDRAM
SIZE
DATA
SIZE
MODE = SDRAM
SIZE = 0
SIZE = 1
SIZE = 2
SIZE = 3
16 MBit
128 MBit
256 MBit
512 MBit
16
16
16
16
Figure 6-6. EPI SDRAM Mode
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
Table 6-2. EPI MODES – SDRAM Mode (EPICFG/MODE = 0x1)
EPI PORT NAME
Accessible by
EPI SIGNAL FUNCTION
DEVICE PIN
(Available GPIOMUX_1
Muxing Choices for EPI)
Accessible by C28x
Column/Row Address
Data
Cortex™-M3
EPI0S0
A0
A1
D0
D1
PH3_GPIO51
EPI0S1
EPI0S2
EPI0S3
EPI0S4
EPI0S5
EPI0S6
EPI0S7
EPI0S8
EPI0S9
EPI0S10
EPI0S11
EPI0S12
EPI0S13
EPI0S14
PH2_GPIO50
PC4_GPIO68
PC5_GPIO69
PC6_GPIO70
PC7_GPIO71
PH0_GPIO48
PH1_GPIO49
PE0_GPIO24
PE1_GPIO25
PH4_GPIO52
PH5_GPIO53
PF4_GPIO36
PG0_GPIO40
PG1_GPIO41
A2
D2
A3
D3
A4
D4
A5
D5
A6
D6
A7
D7
A8
D8
A9
D9
A10
A11
A12
BA0
BA1
D10
D11
D12
D13
D14
EPI0S15
EPI0S16
EPI0S17
EPI0S18
EPI0S19
EPI0S28
EPI0S29
EPI0S30
EPI0S31
D15
DQML
DQMH
CAS
RAS
WE
PF5_GPIO37
PJ0_GPIO56
PJ1_GPIO57
PJ2_GPIO58
PD4_GPIO20
PD5_GPIO21
PD6_GPIO22
PD7_GPIO23
PG7_GPIO47
PJ3_GPIO59
PJ4_GPIO60
PJ5_GPIO61
PJ6_GPIO62
CS
CKE
CLK
EPI0S20
EPI0S21
EPI0S22
EPI0S23
EPI0S24
EPI0S25
EPI0S26
EPI0S27
x
x
x
x
x
x
x
x
PD2_GPIO18
PD3_GPIO19
PB5_GPIO13
PB4_GPIO12
PE2_GPIO26
PE3_GPIO27
PH6_GPIO54
PH7_GPIO55
EPI0S32
EPI0S33
EPI0S34
EPI0S35
EPI0S36
EPI0S37
EPI0S38
EPI0S39
EPI0S40
EPI0S41
x
x
x
x
x
x
x
x
x
x
PF2_GPIO34
PF3_GPIO35
PE4_GPIO28
PE5_GPIO29
PB7_GPIO15
PB6_GPIO14
PF6_GPIO38
PG2_GPIO42
PG5_GPIO45
PG6_GPIO46
PC0_GPIO64
PC1_GPIO65
PC3_GPIO67
PC2_GPIO66
PE4_GPIO28
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
6.1.4.3 EPI Host Bus Mode
There are two versions of the EPI Host Bus Mode: an 8-bit version (HB-8) and a 16-bit version (HB-16).
Section 6.1.4.3.1 discusses the EPI 8-Bit Host Bus Mode. Section 6.1.4.3.2 discusses the EPI 16-Bit Host
Bus Mode.
6.1.4.3.1 EPI 8-Bit Host Bus (HB-8) Mode
The 8-Bit Host Bus (HB-8) Mode uses fewer data pins than the 16-Bit Host Bus (HB-16) Mode; hence,
more pins are available for address. The HB-8 Mode is also slower than the General-Purpose Mode in
order to accommodate older logic. The HB-8 Mode is selected with the MODE field of EPI Configuration
Register. Within the HB-8 Mode, two additional registers are used to select address/data muxing, chip
selects, and other options. These registers are the HB-8 Configuration Register and the HB-8
Configuration2 Register. See Figure 6-7 for a snapshot of HB-8 registers, modes, and features.
EPI CONFIG REG
HP8 CONFIG REG
HB8 CONFIG2 REG
MODE = HB-8
ADDRESS
RANGE
DATA
SIZE
READY
SIGNAL
MODE = MUXED
CSCFG = ALE
CSCFG = 1 CS
A0 – A27
A0 – A27
A0 – A26
A0 – A25
8
8
8
8
NO
NO
NO
NO
CSCFG = 2 CS
CSCFG = ALE + 2 CS
MODE = NOMUX
CSCFG = ALE
CSCFG = 1 CS
A0 – A19
A0 – A19
A0 – A18
A0 – A17
8
8
8
8
NO
NO
NO
NO
CSCFG = 2 CS
CSCFG = ALE + 2 CS
MODE = FIFO
CSCFG = 2 CS
N/A
N/A
8
8
NO
NO
CSCFG = ALE + 2 CS
Figure 6-7. EPI 8-Bit Host Bus Mode
6.1.4.3.1.1 HB-8 Muxed Address/Data Mode
The HB-8 Muxed Mode multiplexes address signals with low-order data signals. For this reason, the
Muxed Mode allows for a larger address space as compared to the Non-Muxed Mode. The HB-8 Muxed
Mode is selected with the MODE field of the HB-8 Configuration Register. In addition to data and address
signals, the HB-8 Muxed Mode also features the ALE signal (indicating to an external latch to capture
address and hold the address until the data phase); RD and WR data strobes; and 1–4 Chip Select (CS)
signals to enable one of four external peripherals. The ALE and CS options are chosen with the CSCFG
field of the HB-8 Configuration2 Register. For more detailed maps of the HB-8 Muxed Mode, see Table 6-
3.
136
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
Table 6-3. EPI MODES – 8-Bit Host-Bus Mode (EPICFG/MODE = 0x2),
Muxed (EPIHB16CFG/MODE = 0x0)
EPI PORT NAME
EPI SIGNAL FUNCTION
DEVICE PIN
With
Address Latch
Enable
With
One
Chip Select
(CSCFG = 0x1)
With
Two
Chip Selects
(CSCFG = 0x2)
With
Accessible by
Cortex™-M3
Accessible by
C28x
ALE and Two
Chip Selects
(CSCFG = 0x3)
(Available GPIOMUX_1
Muxing Choices for EPI)
(CSCFG = 0x0)
EPI0S0
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
PH3_GPIO51
EPI0S1
EPI0S2
EPI0S3
EPI0S4
EPI0S5
EPI0S6
EPI0S7
PH2_GPIO50
PC4_GPIO68
PC5_GPIO69
PC6_GPIO70
PC7_GPIO71
PH0_GPIO48
PH1_GPIO49
EPI0S8
EPI0S9
A8
A8
A9
A8
A8
PE0_GPIO24
PE1_GPIO25
PH4_GPIO52
PH5_GPIO53
PF4_GPIO36
PG0_GPIO40
PG1_GPIO41
PF5_GPIO37
PJ0_GPIO56
PJ1_GPIO57
PJ2_GPIO58
PD4_GPIO20
PD2_GPIO18
PD3_GPIO19
PB5_GPIO13
PB4_GPIO12
PE2_GPIO26
PE3_GPIO27
PH6_GPIO54
PH7_GPIO55
PD7_GPIO23
A9
A9
A9
EPI0S10
EPI0S11
EPI0S12
EPI0S13
EPI0S14
EPI0S15
EPI0S16
EPI0S17
EPI0S18
EPI0S19
EPI0S20
EPI0S21
EPI0S22
EPI0S23
EPI0S24
EPI0S25
EPI0S26
EPI0S27
EPI0S30
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
ALE
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
CS0
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
CS1
CS0
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
CS0
CS1
ALE
PJ3_GPIO59
PJ6_GPIO62
EPI0S29
EPI0S28
WR
RD
WR
RD
WR
RD
WR
RD
PD6_GPIO22
PD5_GPIO21
PJ5_GPIO61
PJ4_GPIO60
EPI0S31
EPI0S32
EPI0S33
EPI0S34
EPI0S35
EPI0S36
EPI0S37
EPI0S38
EPI0S39
EPI0S40
EPI0S41
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
PG7_GPIO47
PF2_GPIO34
PF3_GPIO35
PE4_GPIO28
PE5_GPIO29
PB7_GPIO15
PB6_GPIO14
PF6_GPIO38
PG2_GPIO42
PG5_GPIO45
PG6_GPIO46
PC0_GPIO64
PC1_GPIO65
PC3_GPIO67
PC2_GPIO66
PE4_GPIO28
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
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6.1.4.3.1.2 HB-8 Non-Muxed Address/Data Mode
The HB-8 Non-Muxed Mode uses dedicated pins for address and data signals. For this reason, the Non-
Muxed Mode has reduced address reach as compared to the Muxed Mode. The HB-8 Non-Muxed Mode
is selected with the MODE field of the HB-8 Configuration Register. In addition to data and address
signals, the HB-8 Non-Muxed Mode also features the ALE signal (indicating to an external latch to capture
address and hold the address until the data phase); RD and WR data strobes; and 1–4 Chip Select (CS)
signals to enable one of four external peripherals. The ALE and CS options are chosen with the CSCFG
field of the HB-8 Configuration2 Register. For more detailed maps of the HB-8 Non-Muxed Mode, see
Table 6-4.
Table 6-4. EPI MODES – 8-Bit Host-Bus Mode (EPICFG/MODE = 0x2),
Non-Muxed (EPIHB16CFG/MODE = 0x1)
EPI PORT NAME
EPI SIGNAL FUNCTION
DEVICE PIN
With
Address Latch
Enable
With
One
Chip Select
(CSCFG = 0x1)
With
Two
Chip Selects
(CSCFG = 0x2)
With
Accessible by
Cortex™-M3
Accessible by
C28x
ALE and Two
Chip Selects
(CSCFG = 0x3)
(Available GPIOMUX_1
Muxing Choices for EPI)
(CSCFG = 0x0)
EPI0S0
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
PH3_GPIO51
EPI0S1
EPI0S2
EPI0S3
EPI0S4
EPI0S5
EPI0S6
EPI0S7
PH2_GPIO50
PC4_GPIO68
PC5_GPIO69
PC6_GPIO70
PC7_GPIO71
PH0_GPIO48
PH1_GPIO49
EPI0S8
EPI0S9
A0
A1
A0
A1
A0
A1
A0
A1
PE0_GPIO24
PE1_GPIO25
PH4_GPIO52
PH5_GPIO53
PF4_GPIO36
PG0_GPIO40
PG1_GPIO41
PF5_GPIO37
PJ0_GPIO56
PJ1_GPIO57
PJ2_GPIO58
PD4_GPIO20
PD2_GPIO18
PD3_GPIO19
PB5_GPIO13
PB4_GPIO12
PE2_GPIO26
PE3_GPIO27
PH6_GPIO54
PH7_GPIO55
PD7_GPIO23
EPI0S10
EPI0S11
EPI0S12
EPI0S13
EPI0S14
EPI0S15
EPI0S16
EPI0S17
EPI0S18
EPI0S19
EPI0S20
EPI0S21
EPI0S22
EPI0S23
EPI0S24
EPI0S25
EPI0S26
EPI0S27
EPI0S30
A2
A2
A2
A2
A3
A3
A3
A3
A4
A4
A4
A4
A5
A5
A5
A5
A6
A6
A6
A6
A7
A7
A7
A7
A8
A8
A8
A8
A9
A9
A9
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
ALE
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
CS0
A10
A11
A12
A13
A14
A15
A16
A17
A18
CS1
CS0
A10
A11
A12
A13
A14
A15
A16
A17
CS0
CS1
ALE
PJ3_GPIO59
PJ6_GPIO62
EPI0S29
EPI0S28
WR
RD
WR
RD
WR
RD
WR
RD
PD6_GPIO22
PD5_GPIO21
PJ5_GPIO61
PJ4_GPIO60
EPI0S31
EPI0S32
EPI0S33
x
x
x
x
x
x
x
x
x
x
x
x
PG7_GPIO47
PF2_GPIO34
PF3_GPIO35
PC0_GPIO64
PC1_GPIO65
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
www.ti.com
SPRS742D –JUNE 2011–REVISED AUGUST 2012
Table 6-4. EPI MODES – 8-Bit Host-Bus Mode (EPICFG/MODE = 0x2),
Non-Muxed (EPIHB16CFG/MODE = 0x1) (continued)
EPI PORT NAME
EPI SIGNAL FUNCTION
DEVICE PIN
With
Address Latch
Enable
With
One
Chip Select
(CSCFG = 0x1)
With
Two
Chip Selects
(CSCFG = 0x2)
With
Accessible by
Cortex™-M3
Accessible by
C28x
ALE and Two
Chip Selects
(CSCFG = 0x3)
(Available GPIOMUX_1
Muxing Choices for EPI)
(CSCFG = 0x0)
EPI0S34
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
PE4_GPIO28
EPI0S35
EPI0S36
EPI0S37
EPI0S38
EPI0S39
EPI0S40
EPI0S41
PE5_GPIO29
PB7_GPIO15
PB6_GPIO14
PF6_GPIO38
PG2_GPIO42
PG5_GPIO45
PG6_GPIO46
PC3_GPIO67
PC2_GPIO66
PE4_GPIO28
6.1.4.3.1.3 HB-8 FIFO Mode
The HB-8 FIFO Mode uses 8 bits of data, removes ALE and address pins, and optionally adds external
FIFO Full/Empty flag inputs. This scheme is used by many devices, such as radios, communication
devices (including USB2 devices), and some FPGA configuration (FIFO throughblock RAM). This FIFO
Mode presents the data side of the normal Host-Bus interface, but is paced by FIFO control signals. It is
important to consider that the FIFO Full/Empty control inputs may stall the EPI interface and can
potentially block other CPU or DMA accesses. For more detailed maps of the HB-8 FIFO Mode, see
Table 6-5.
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
Table 6-5. EPI MODES – 8-Bit Host-Bus Mode (EPICFG/MODE = 0x2),
FIFO Mode (EPIHB16CFG/MODE = 0x3)
EPI PORT NAME
EPI SIGNAL FUNCTION
DEVICE PIN
With One
Chip Select
(CSCFG = 0x1)
With Two
Chip Selects
(CSCFG = 0x2)
Accessible by
Cortex™-M3
(Available GPIOMUX_1
Muxing Choices for EPI)
Accessible by C28x
EPI0S0
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
PH3_GPIO51
EPI0S1
EPI0S2
EPI0S3
EPI0S4
EPI0S5
EPI0S6
EPI0S7
PH2_GPIO50
PC4_GPIO68
PC5_GPIO69
PC6_GPIO70
PC7_GPIO71
PH0_GPIO48
PH1_GPIO49
EPI0S25
EPI0S30
x
CS1
CS0
PE3_GPIO27
PD7_GPIO23
CS0
PJ6_GPIO62
EPI0S27
EPI0S26
EPI0S29
EPI0S28
FFULL
FEMPTY
WR
FFULL
FEMPTY
WR
PH7_GPIO55
PH6_GPIO54
PD6_GPIO22
PD5_GPIO21
PJ5_GPIO61
PJ4_GPIO60
RD
RD
EPI0S8
EPI0S9
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
PE0_GPIO24
PE1_GPIO25
PH4_GPIO52
PH5_GPIO53
PF4_GPIO36
PG0_GPIO40
PG1_GPIO41
PF5_GPIO37
PJ0_GPIO56
PJ1_GPIO57
PJ2_GPIO58
PD4_GPIO20
PD2_GPIO18
PD3_GPIO19
PB5_GPIO13
PB4_GPIO12
PE2_GPIO26
PF2_GPIO34
PG7_GPIO47
PF3_GPIO35
PE4_GPIO28
PE5_GPIO29
PB7_GPIO15
PB6_GPIO14
PF6_GPIO38
PG2_GPIO42
PG5_GPIO45
PG6_GPIO46
EPI0S10
EPI0S11
EPI0S12
EPI0S13
EPI0S14
EPI0S15
EPI0S16
EPI0S17
EPI0S18
EPI0S19
EPI0S20
EPI0S21
EPI0S22
EPI0S23
EPI0S24
EPI0S32
EPI0S31
EPI0S33
EPI0S34
EPI0S35
EPI0S36
EPI0S37
EPI0S38
EPI0S39
EPI0S40
EPI0S41
PJ3_GPIO59
PC0_GPIO64
PC1_GPIO65
PC3_GPIO67
PC2_GPIO66
PE4_GPIO28
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
www.ti.com
SPRS742D –JUNE 2011–REVISED AUGUST 2012
6.1.4.3.2 EPI 16-Bit Host Bus (HB-16) Mode
The 16-Bit Host Bus (HB-16) Mode uses fewer address pins than the 8-Bit Host Bus (HB-8) Mode; hence,
more pins are available for data. The HB-16 Mode is also slower than the General-Purpose Mode in order
to accommodate older logic. The HB-16 Mode is selected with the MODE field of EPI Configuration
Register. Within the HB-16 Mode, two additional registers are used to select address/data muxing, byte
selects, chip selects, and other options. These registers are the HB-16 Configuration Register and the HB-
16 Configuration2 Register. See Figure 6-8 for a snapshot of HB-16 registers, modes, and features.
EPI CONFIG REG
HP16 CONFIG REG
HB16 CONFIG2 REG
MODE = HB-16
MODE = MUXED
ADDRESS
RANGE
DATA
SIZE
READY
SIGNAL
BSEL = YES
CSCFG = ALE
CSCFG = 1 CS
A0 – A25
A0 – A25
A0 – A24
A0 – A23
16
16
16
16
NO
NO
NO
NO
CSCFG = 2 CS
CSCFG = ALE + 2 CS
BSEL = NO
CSCFG = ALE
CSCFG = 1 CS
A0 – A27
A0 – A27
A0 – A26
A0 – A25
16
16
16
16
NO
NO
NO
NO
CSCFG = 2 CS
CSCFG = ALE + 2 CS
MODE = NOMUX
BSEL = YES
CSCFG = ALE
CSCFG = 1 CS
A0 – A9
A0 – A9
A0 – A8
A0 – A7
A0 – A16
A0 – A14
16
16
16
16
16
16
NO
YES
YES
YES
YES
YES
CSCFG = 2 CS
CSCFG = ALE + 2 CS
CSCFG = 3 CS
CSCFG = 4 CS
BSEL = NO
CSCFG = ALE
CSCFG = 1 CS
A0 – A11
A0 – A11
A0 – A10
A0 – A9
16
16
16
16
16
16
NO
YES
YES
YES
YES
YES
CSCFG = 2 CS
CSCFG = ALE + 2 CS
CSCFG = 3 CS
A0 – A18
A0 – A16
CSCFG = 4 CS
MODE = FIFO
BSEL = DON’T CARE
CSCFG = 2 CS
N/A
N/A
16
16
NO
NO
CSCFG = ALE + 2 CS
Figure 6-8. EPI 16-Bit Host Bus Mode
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
6.1.4.3.2.1 HB-16 Muxed Address/Data Mode
The HB-16 Muxed Mode multiplexes address signals with low-order data signals. For this reason, the
Muxed Mode allows for a larger address space as compared to the Non-Muxed Mode. The HB-16 Muxed
Mode is selected with the MODE field of the HB-16 Configuration Register. In addition to data and address
signals, the HB-16 Muxed Mode also features the ALE signal (indicating to an external latch to capture
address and hold the address until the data phase); RD and WR data strobes; 1–4 Chip Select (CS)
signals to enable one of four external peripherals; and two Byte Select (BSEL) signals to accommodate
byte accesses to lower or upper half of 16-bit data. The Byte Selects are chosen with the BSEL field of the
HB-16 Configuration Register. The ALE and CS options are chosen with the CSCFG field of the HB-16
Configuration2 Register. For more detailed maps of the HB-16 Muxed Mode without Byte Selects, see
Table 6-6. For more detailed maps of the HB-16 Muxed Mode with Byte Selects, see Table 6-7.
Table 6-6. EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE = 0x3),
Muxed (EPIHB16CFG/MODE = 0x0), Without Byte Selects (EPIHB16CFG/BSEL = 0x1),
and With Chip Selects (EPIHB16CFG2/CSCFG = 0x0,1,2,3)
EPI PORT NAME
EPI SIGNAL FUNCTION
DEVICE PIN
With
Address Latch
Enable
With
One
Chip Select
(CSCFG = 0x1)
With
Two
Chip Selects
(CSCFG = 0x2)
With
Accessible by
Cortex™-M3
Accessible by
C28x
ALE and Two
Chip Selects
(CSCFG = 0x3)
(Available GPIOMUX_1
Muxing Choices for EPI)
(CSCFG = 0x0)
EPI0S0
AD0
AD1
AD0
AD1
AD0
AD1
AD0
AD1
PH3_GPIO51
EPI0S1
EPI0S2
EPI0S3
EPI0S4
EPI0S5
EPI0S6
EPI0S7
EPI0S8
EPI0S9
PH2_GPIO50
PC4_GPIO68
PC5_GPIO69
PC6_GPIO70
PC7_GPIO71
PH0_GPIO48
PH1_GPIO49
PE0_GPIO24
PE1_GPIO25
PH4_GPIO52
PH5_GPIO53
PF4_GPIO36
PG0_GPIO40
PG1_GPIO41
PF5_GPIO37
AD2
AD2
AD2
AD2
AD3
AD3
AD3
AD3
AD4
AD4
AD4
AD4
AD5
AD5
AD5
AD5
AD6
AD6
AD6
AD6
AD7
AD7
AD7
AD7
AD8
AD8
AD8
AD8
AD9
AD9
AD9
AD9
EPI0S10
EPI0S11
EPI0S12
EPI0S13
EPI0S14
EPI0S15
AD10
AD11
AD12
AD13
AD14
AD15
AD10
AD11
AD12
AD13
AD14
AD15
AD10
AD11
AD12
AD13
AD14
AD15
AD10
AD11
AD12
AD13
AD14
AD15
EPI0S16
EPI0S17
EPI0S18
EPI0S19
EPI0S20
EPI0S21
EPI0S22
EPI0S23
EPI0S24
EPI0S25
EPI0S26
EPI0S27
EPI0S30
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
ALE
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
CS0
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
CS1
CS0
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
CS0
CS1
ALE
PJ0_GPIO56
PJ1_GPIO57
PJ2_GPIO58
PD4_GPIO20
PD2_GPIO18
PD3_GPIO19
PB5_GPIO13
PB4_GPIO12
PE2_GPIO26
PE3_GPIO27
PH6_GPIO54
PH7_GPIO55
PD7_GPIO23
PJ3_GPIO59
PJ6_GPIO62
EPI0S29
EPI0S28
WR
RD
WR
RD
WR
RD
WR
RD
PD6_GPIO22
PD5_GPIO21
PJ5_GPIO61
PJ4_GPIO60
142
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
www.ti.com
SPRS742D –JUNE 2011–REVISED AUGUST 2012
Table 6-6. EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE = 0x3),
Muxed (EPIHB16CFG/MODE = 0x0), Without Byte Selects (EPIHB16CFG/BSEL = 0x1),
and With Chip Selects (EPIHB16CFG2/CSCFG = 0x0,1,2,3) (continued)
EPI PORT NAME
EPI SIGNAL FUNCTION
DEVICE PIN
With
Address Latch
Enable
With
One
Chip Select
(CSCFG = 0x1)
With
Two
Chip Selects
(CSCFG = 0x2)
With
Accessible by
Cortex™-M3
Accessible by
C28x
ALE and Two
Chip Selects
(CSCFG = 0x3)
(Available GPIOMUX_1
Muxing Choices for EPI)
(CSCFG = 0x0)
EPI0S31
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
PG7_GPIO47
EPI0S32
EPI0S33
EPI0S34
EPI0S35
EPI0S36
EPI0S37
EPI0S38
EPI0S39
EPI0S40
EPI0S41
PF2_GPIO34
PF3_GPIO35
PE4_GPIO28
PE5_GPIO29
PB7_GPIO15
PB6_GPIO14
PF6_GPIO38
PG2_GPIO42
PG5_GPIO45
PG6_GPIO46
PC0_GPIO64
PC1_GPIO65
PC3_GPIO67
PC2_GPIO66
PE4_GPIO28
Table 6-7. EPI MODES – 16-Bit Host-Bus (EPICFG/MODE = 0x3),
Muxed (EPIHB16CFG/MODE = 0x0), With Byte Selects (EPIHB16CFG/BSEL = 0x0),
and With Chip Selects (EPIHB16CFG2/CSCFG=0x0,1,2,3)
EPI PORT NAME
EPI SIGNAL FUNCTION
DEVICE PIN
With
Address Latch
Enable
With
One
Chip Select
(CSCFG = 0x1)
With
Two
Chip Selects
(CSCFG = 0x2)
With
Accessible by
Cortex™-M3
Accessible by
C28x
ALE and Two
Chip Selects
(CSCFG = 0x3)
(Available GPIOMUX_1
Muxing Choices for EPI)
(CSCFG = 0x0)
EPI0S0
AD0
AD1
AD0
AD1
AD0
AD1
AD0
AD1
PH3_GPIO51
EPI0S1
EPI0S2
EPI0S3
EPI0S4
EPI0S5
EPI0S6
EPI0S7
EPI0S8
EPI0S9
EPI0S10
EPI0S11
EPI0S12
EPI0S13
EPI0S14
EPI0S15
PH2_GPIO50
PC4_GPIO68
PC5_GPIO69
PC6_GPIO70
PC7_GPIO71
PH0_GPIO48
PH1_GPIO49
PE0_GPIO24
PE1_GPIO25
PH4_GPIO52
PH5_GPIO53
PF4_GPIO36
PG0_GPIO40
PG1_GPIO41
PF5_GPIO37
AD2
AD2
AD2
AD2
AD3
AD3
AD3
AD3
AD4
AD4
AD4
AD4
AD5
AD5
AD5
AD5
AD6
AD6
AD6
AD6
AD7
AD7
AD7
AD7
AD8
AD8
AD8
AD8
AD9
AD9
AD9
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD10
AD11
AD12
AD13
AD14
AD15
AD10
AD11
AD12
AD13
AD14
AD15
AD10
AD11
AD12
AD13
AD14
AD15
EPI0S16
EPI0S17
EPI0S18
EPI0S19
EPI0S20
EPI0S21
EPI0S22
EPI0S23
EPI0S24
EPI0S25
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A16
A17
A16
A17
PJ0_GPIO56
PJ1_GPIO57
PJ2_GPIO58
PD4_GPIO20
PD2_GPIO18
PD3_GPIO19
PB5_GPIO13
PB4_GPIO12
PE2_GPIO26
PE3_GPIO27
A18
A18
A19
A19
PJ3_GPIO59
A20
A20
A21
A21
A22
A22
A23
A23
A24
BSEL0
BSEL1
BSEL0
Copyright © 2011–2012, Texas Instruments Incorporated
Peripheral Information and Timings
143
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
Table 6-7. EPI MODES – 16-Bit Host-Bus (EPICFG/MODE = 0x3),
Muxed (EPIHB16CFG/MODE = 0x0), With Byte Selects (EPIHB16CFG/BSEL = 0x0),
and With Chip Selects (EPIHB16CFG2/CSCFG=0x0,1,2,3) (continued)
EPI PORT NAME
EPI SIGNAL FUNCTION
DEVICE PIN
With
Address Latch
Enable
With
One
Chip Select
(CSCFG = 0x1)
With
Two
Chip Selects
(CSCFG = 0x2)
With
Accessible by
Cortex™-M3
Accessible by
C28x
ALE and Two
Chip Selects
(CSCFG = 0x3)
(Available GPIOMUX_1
Muxing Choices for EPI)
(CSCFG = 0x0)
EPI0S26
BSEL0
BSEL1
ALE
BSEL0
BSEL1
CS0
BSEL1
CS1
CS0
CS1
ALE
PH6_GPIO54
EPI0S27
EPI0S30
PH7_GPIO55
PD7_GPIO23
CS0
PJ6_GPIO62
EPI0S29
EPI0S28
WR
RD
WR
RD
WR
RD
WR
RD
PD6_GPIO22
PD5_GPIO21
PJ5_GPIO61
PJ4_GPIO60
EPI0S31
EPI0S32
EPI0S33
EPI0S34
EPI0S35
EPI0S36
EPI0S37
EPI0S38
EPI0S39
EPI0S40
EPI0S41
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
PG7_GPIO47
PF2_GPIO34
PF3_GPIO35
PE4_GPIO28
PE5_GPIO29
PB7_GPIO15
PB6_GPIO14
PF6_GPIO38
PG2_GPIO42
PG5_GPIO45
PG6_GPIO46
PC0_GPIO64
PC1_GPIO65
PC3_GPIO67
PC2_GPIO66
PE4_GPIO28
6.1.4.3.2.2 HB-16 Non-Muxed Address/Data Mode
The HB-16 Non-Muxed Mode uses dedicated pins for address and data signals. For this reason, the Non-
Muxed Mode has reduced address reach as compared to the Muxed Mode. The HB-16 Non-Muxed Mode
is selected with the MODE field of the HB-16 Configuration Register. In addition to data and address
signals, the HB-16 Non-Muxed Mode also features the ALE signal (indicating to an external latch to
capture address and hold the address until the data phase); RD and WR data strobes; 1–4 Chip Select
(CS) signals to enable one of four external peripherals; and two Byte Select (BSEL) signals to
accommodate byte accesses to lower or upper half of 16-bit data. The Byte Selects are chosen with the
BSEL field of the HB-16 Configuration Register. The ALE and CS options are chosen with the CSCFG
field of the HB-16 Configuration2 Register. For Non-Muxed bus cycles, most of the CSCFG modes also
support a RDY signal. The RDY input to EPI is used by an external peripheral to extend bus cycles when
the peripheral needs more time to complete reading or writing of data. While most EPI modes use up to
32 pins, the Non-Muxed CSCFG modes with 3 and 4 Chip Selects use 10 additional pins to extend the
address reach and the number of CS signals. For detailed maps of HB-16 Non-Muxed Modes without
Byte Selects, see Table 6-8 and Table 6-9. For detailed maps of HB-16 Non-Muxed Modes with Byte
Selects, see Table 6-10 and Table 6-11.
144
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
www.ti.com
SPRS742D –JUNE 2011–REVISED AUGUST 2012
Table 6-8. EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE = 0x3),
Non-Muxed (EPIHB16CFG/MODE = 0x1), Without Byte Selects (EPIHB16CFG/BSEL = 0x1),
and With Chip Selects (EPIHB16CFG2/CSCFG = 0x0,1,2,3)
EPI PORT NAME
EPI SIGNAL FUNCTION
DEVICE PIN
With
Address Latch
Enable
With
One
Chip Select
(CSCFG = 0x1)
With
Two
Chip Selects
(CSCFG = 0x2)
With
Accessible by
Cortex™-M3
ALE and Two
Chip Selects
(CSCFG = 0x3)
(Available GPIOMUX_1
Muxing Choices for EPI)
Accessible by C28x
(CSCFG = 0x0)
EPI0S0
D0
D1
D0
D1
D0
D1
D0
D1
PH3_GPIO51
EPI0S1
EPI0S2
EPI0S3
EPI0S4
EPI0S5
EPI0S6
EPI0S7
EPI0S8
EPI0S9
EPI0S10
EPI0S11
EPI0S12
EPI0S13
EPI0S14
EPI0S15
PH2_GPIO50
PC4_GPIO68
PC5_GPIO69
PC6_GPIO70
PC7_GPIO71
PH0_GPIO48
PH1_GPIO49
PE0_GPIO24
PE1_GPIO25
PH4_GPIO52
PH5_GPIO53
PF4_GPIO36
PG0_GPIO40
PG1_GPIO41
PF5_GPIO37
D2
D2
D2
D2
D3
D3
D3
D3
D4
D4
D4
D4
D5
D5
D5
D5
D6
D6
D6
D6
D7
D7
D7
D7
D8
D8
D8
D8
D9
D9
D9
D9
D10
D11
D12
D13
D14
D15
D10
D11
D12
D13
D14
D15
D10
D11
D12
D13
D14
D15
D10
D11
D12
D13
D14
D15
EPI0S16
EPI0S17
EPI0S18
EPI0S19
EPI0S20
EPI0S21
EPI0S22
EPI0S23
EPI0S24
EPI0S25
EPI0S26
EPI0S27
EPI0S30
A0
A1
A0
A1
A0
A1
A0
A1
PJ0_GPIO56
PJ1_GPIO57
PJ2_GPIO58
PD4_GPIO20
PD2_GPIO18
PD3_GPIO19
PB5_GPIO13
PB4_GPIO12
PE2_GPIO26
PE3_GPIO27
PH6_GPIO54
PH7_GPIO55
PD7_GPIO23
A2
A2
A2
A2
A3
A3
A3
A3
PJ3_GPIO59
A4
A4
A4
A4
A5
A5
A5
A5
A6
A6
A6
A6
A7
A7
A7
A7
A8
A8
A8
A8
A9
A9
A9
A9
A10
A11
ALE
A10
A11
CS0
A10
CS1
CS0
CS0
CS1
ALE
PJ6_GPIO62
EPI0S29
EPI0S28
EPI0S32
WR
RD
x
WR
RD
WR
RD
WR
RD
PD6_GPIO22
PD5_GPIO21
PF2_GPIO34
PJ5_GPIO61
PJ4_GPIO60
PC0_GPIO64
RDY
RDY
RDY
EPI0S31
EPI0S33
EPI0S34
EPI0S35
EPI0S36
EPI0S37
EPI0S38
EPI0S39
EPI0S40
EPI0S41
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
PG7_GPIO47
PF3_GPIO35
PE4_GPIO28
PE5_GPIO29
PB7_GPIO15
PB6_GPIO14
PF6_GPIO38
PG2_GPIO42
PG5_GPIO45
PG6_GPIO46
PC1_GPIO65
PC3_GPIO67
PC2_GPIO66
PE4_GPIO28
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
Table 6-9. EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE=0x3),
Non-Muxed (EPIHB16CFG/MODE = 0x1), Without Byte Selects (EPIHB16CFG/BSEL = 0x1),
and With Additional Chip Selects (EPIHB16CFG2/CSCFG = 0x5,7)
EPI SIGNAL
FUNCTION
EPI SIGNAL
FUNCTION
EPI PORT NAME
DEVICE PIN
EPI PORT NAME
DEVICE PIN
With
Three
Chip Selects
(CSCFG = 0x7)
With
Four
Chip Selects
(CSCFG = 0x5)
Accessible
Accessible
by
C28x
Accessible
Accessible
by
C28x
(Available GPIOMUX_1
Muxing Choices for EPI)
(Available GPIOMUX_1
Muxing Choices for EPI)
by
by
Cortex™-M3
Cortex™-M3
EPI0S0
D0
D1
PH3_GPIO51
PH2_GPIO50
PC4_GPIO68
PC5_GPIO69
PC6_GPIO70
PC7_GPIO71
PH0_GPIO48
PH1_GPIO49
PE0_GPIO24
PE1_GPIO25
PH4_GPIO52
PH5_GPIO53
PF4_GPIO36
PG0_GPIO40
PG1_GPIO41
PF5_GPIO37
EPI0S0
D0
D1
PH3_GPIO51
PH2_GPIO50
PC4_GPIO68
PC5_GPIO69
PC6_GPIO70
PC7_GPIO71
PH0_GPIO48
PH1_GPIO49
PE0_GPIO24
PE1_GPIO25
PH4_GPIO52
PH5_GPIO53
PF4_GPIO36
PG0_GPIO40
PG1_GPIO41
PF5_GPIO37
EPI0S1
EPI0S2
EPI0S3
EPI0S4
EPI0S5
EPI0S6
EPI0S7
EPI0S8
EPI0S9
EPI0S10
EPI0S11
EPI0S12
EPI0S13
EPI0S14
EPI0S15
EPI0S1
EPI0S2
EPI0S3
EPI0S4
EPI0S5
EPI0S6
EPI0S7
EPI0S8
EPI0S9
EPI0S10
EPI0S11
EPI0S12
EPI0S13
EPI0S14
EPI0S15
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
D8
D8
D9
D9
D10
D11
D12
D13
D14
D15
D10
D11
D12
D13
D14
D15
EPI0S16
EPI0S17
EPI0S18
EPI0S19
EPI0S20
EPI0S21
EPI0S22
EPI0S23
EPI0S24
EPI0S25
EPI0S26
EPI0S36
EPI0S37
EPI0S38
EPI0S39
EPI0S27
EPI0S35
EPI0S40
EPI0S41
EPI0S30
EPI0S34
EPI0S33
A0
A1
PJ0_GPIO56
PJ1_GPIO57
PJ2_GPIO58
EPI0S16
EPI0S17
EPI0S18
EPI0S19
EPI0S20
EPI0S21
EPI0S22
EPI0S23
EPI0S24
EPI0S25
EPI0S26
EPI0S36
EPI0S37
EPI0S38
EPI0S39
EPI0S40
EPI0S41
EPI0S30
EPI0S27
EPI0S34
EPI0S33
A0
A1
PJ0_GPIO56
PJ1_GPIO57
PJ2_GPIO58
A2
A2
A3
PD4_GPIO20
PD2_GPIO18
PD3_GPIO19
PB5_GPIO13
PB4_GPIO12
PE2_GPIO26
PE3_GPIO27
PH6_GPIO54
PB7_GPIO15
PB6_GPIO14
PF6_GPIO38
PG2_GPIO42
PH7_GPIO55
PE5_GPIO29
PG5_GPIO45
PG6_GPIO46
PD7_GPIO23
PE4_GPIO28
PF3_GPIO35
PJ3_GPIO59
A3
PD4_GPIO20
PD2_GPIO18
PD3_GPIO19
PB5_GPIO13
PB4_GPIO12
PE2_GPIO26
PE3_GPIO27
PH6_GPIO54
PB7_GPIO15
PB6_GPIO14
PF6_GPIO38
PG2_GPIO42
PG5_GPIO45
PG6_GPIO46
PD7_GPIO23
PH7_GPIO55
PE4_GPIO28
PF3_GPIO35
PJ3_GPIO59
A4
A4
A5
A5
A6
A6
A7
A7
A8
A8
A9
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
CS0
CS2
CS3
A10
A11
A12
A13
A14
A15
A16
CS0
CS1
CS2
CS3
PC3_GPIO67
PC2_GPIO66
PE4_GPIO28
PC3_GPIO67
PC2_GPIO66
PE4_GPIO28
PJ6_GPIO62
PC1_GPIO65
PJ6_GPIO62
PC1_GPIO65
EPI0S29
EPI0S28
EPI0S32
WR
RD
PD6_GPIO22
PD5_GPIO21
PF2_GPIO34
PJ5_GPIO61
PJ4_GPIO60
PC0_GPIO64
EPI0S29
EPI0S28
EPI0S32
WR
RD
PD6_GPIO22
PD5_GPIO21
PF2_GPIO34
PJ5_GPIO61
PJ4_GPIO60
PC0_GPIO64
RDY
RDY
EPI0S31
EPI0S35
x
x
PG7_GPIO47
PE5_GPIO29
EPI0S31
x
PG7_GPIO47
146
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
www.ti.com
SPRS742D –JUNE 2011–REVISED AUGUST 2012
Table 6-10. EPI MODES – 16-Bit Host-Bus (EPICFG/MODE = 0x3),
Non-Muxed (EPIHB16CFG/MODE = 0x1), With Byte Selects (EPIHB16CFG/BSEL = 0x0),
and With Chip Selects (EPIHB16CFG2/CSCFG = 0x0,1,2,3)
EPI PORT NAME
EPI SIGNAL FUNCTION
DEVICE PIN
With
Address Latch
Enable
With
One
Chip Select
(CSCFG = 0x1)
With
Two
Chip Selects
(CSCFG = 0x2)
With
Accessible by
Cortex™-M3
ALE and Two
Chip Selects
(CSCFG = 0x3)
(Available GPIOMUX_1
Muxing Choices for EPI)
Accessible by C28x
(CSCFG = 0x0)
EPI0S0
D0
D1
D0
D1
D0
D1
D0
D1
PH3_GPIO51
EPI0S1
EPI0S2
EPI0S3
EPI0S4
EPI0S5
EPI0S6
EPI0S7
EPI0S8
EPI0S9
EPI0S10
EPI0S11
EPI0S12
EPI0S13
EPI0S14
EPI0S15
PH2_GPIO50
PC4_GPIO68
PC5_GPIO69
PC6_GPIO70
PC7_GPIO71
PH0_GPIO48
PH1_GPIO49
PE0_GPIO24
PE1_GPIO25
PH4_GPIO52
PH5_GPIO53
PF4_GPIO36
PG0_GPIO40
PG1_GPIO41
PF5_GPIO37
D2
D2
D2
D2
D3
D3
D3
D3
D4
D4
D4
D4
D5
D5
D5
D5
D6
D6
D6
D6
D7
D7
D7
D7
D8
D8
D8
D8
D9
D9
D9
D9
D10
D11
D12
D13
D14
D15
D10
D11
D12
D13
D14
D15
D10
D11
D12
D13
D14
D15
D10
D11
D12
D13
D14
D15
EPI0S16
EPI0S17
EPI0S18
EPI0S19
EPI0S20
EPI0S21
EPI0S22
EPI0S23
EPI0S24
EPI0S25
EPI0S26
EPI0S27
EPI0S30
A0
A1
A0
A1
A0
A1
A0
A1
PJ0_GPIO56
PJ1_GPIO57
PJ2_GPIO58
PD4_GPIO20
PD2_GPIO18
PD3_GPIO19
PB5_GPIO13
PB4_GPIO12
PE2_GPIO26
PE3_GPIO27
PH6_GPIO54
PH7_GPIO55
PD7_GPIO23
A2
A2
A2
A2
A3
A3
A3
A3
PJ3_GPIO59
A4
A4
A4
A4
A5
A5
A5
A5
A6
A6
A6
A6
A7
A7
A7
A7
A8
A8
A8
BSEL0
BSEL1
CS0
CS1
ALE
A9
A9
BSEL0
BSEL1
CS1
CS0
BSEL0
BSEL1
ALE
BSEL0
BSEL1
CS0
PJ6_GPIO62
EPI0S29
EPI0S28
EPI0S32
WR
RD
x
WR
RD
WR
RD
WR
RD
PD6_GPIO22
PD5_GPIO21
PF2_GPIO34
PJ5_GPIO61
PJ4_GPIO60
PC0_GPIO64
RDY
RDY
RDY
EPI0S31
EPI0S33
EPI0S34
EPI0S35
EPI0S36
EPI0S37
EPI0S38
EPI0S39
EPI0S40
EPI0S41
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
PG7_GPIO47
PF3_GPIO35
PE4_GPIO28
PE5_GPIO29
PB7_GPIO15
PB6_GPIO14
PF6_GPIO38
PG2_GPIO42
PG5_GPIO45
PG6_GPIO46
PC1_GPIO65
PC3_GPIO67
PC2_GPIO66
PE4_GPIO28
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
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Table 6-11. EPI MODES – 16-Bit Host-Bus (EPICFG/MODE = 0x3),
Non-Muxed (EPIHB16CFG/MODE = 0x1), With Byte Selects (EPIHB16CFG/BSEL = 0x0),
and With Additional Chip Selects (EPIHB16CFG2/CSCFG = 0x5,7)
EPI SIGNAL
FUNCTION
EPI SIGNAL
FUNCTION
EPI PORT NAME
DEVICE PIN
EPI PORT NAME
DEVICE PIN
With
Three
Chip Selects
(CSCFG = 0x7)
With
Four
Chip Selects
(CSCFG = 0x5)
Accessible
Accessible
by
C28x
Accessible
Accessible
by
C28x
(Available GPIOMUX_1
Muxing Choices for EPI)
(Available GPIOMUX_1
Muxing Choices for EPI)
by
by
Cortex™-M3
Cortex™-M3
EPI0S0
D0
D1
PH3_GPIO51
PH2_GPIO50
PC4_GPIO68
PC5_GPIO69
PC6_GPIO70
PC7_GPIO71
PH0_GPIO48
PH1_GPIO49
PE0_GPIO24
PE1_GPIO25
PH4_GPIO52
PH5_GPIO53
PF4_GPIO36
PG0_GPIO40
PG1_GPIO41
PF5_GPIO37
EPI0S0
D0
D1
PH3_GPIO51
PH2_GPIO50
PC4_GPIO68
PC5_GPIO69
PC6_GPIO70
PC7_GPIO71
PH0_GPIO48
PH1_GPIO49
PE0_GPIO24
PE1_GPIO25
PH4_GPIO52
PH5_GPIO53
PF4_GPIO36
PG0_GPIO40
PG1_GPIO41
PF5_GPIO37
EPI0S1
EPI0S2
EPI0S3
EPI0S4
EPI0S5
EPI0S6
EPI0S7
EPI0S8
EPI0S9
EPI0S10
EPI0S11
EPI0S12
EPI0S13
EPI0S14
EPI0S15
EPI0S1
EPI0S2
EPI0S3
EPI0S4
EPI0S5
EPI0S6
EPI0S7
EPI0S8
EPI0S9
EPI0S10
EPI0S11
EPI0S12
EPI0S13
EPI0S14
EPI0S15
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
D8
D8
D9
D9
D10
D11
D12
D13
D14
D15
D10
D11
D12
D13
D14
D15
EPI0S16
EPI0S17
EPI0S18
EPI0S19
EPI0S20
EPI0S21
EPI0S22
EPI0S23
EPI0S24
EPI0S40
EPI0S41
EPI0S36
EPI0S37
EPI0S38
EPI0S39
EPI0S27
EPI0S35
EPI0S25
EPI0S26
EPI0S30
EPI0S34
EPI0S33
A0
A1
PJ0_GPIO56
PJ1_GPIO57
PJ2_GPIO58
EPI0S16
EPI0S17
EPI0S18
EPI0S19
EPI0S20
EPI0S21
EPI0S22
EPI0S23
EPI0S24
EPI0S40
EPI0S41
EPI0S36
EPI0S37
EPI0S38
EPI0S39
EPI0S25
EPI0S26
EPI0S30
EPI0S27
EPI0S34
EPI0S33
A0
A1
PJ0_GPIO56
PJ1_GPIO57
PJ2_GPIO58
A2
A2
A3
PD4_GPIO20
PD2_GPIO18
PD3_GPIO19
PB5_GPIO13
PB4_GPIO12
PE2_GPIO26
PG5_GPIO45
PG6_GPIO46
PB7_GPIO15
PB6_GPIO14
PF6_GPIO38
PG2_GPIO42
PH7_GPIO55
PE5_GPIO29
PE3_GPIO27
PH6_GPIO54
PD7_GPIO23
PE4_GPIO28
PF3_GPIO35
PJ3_GPIO59
A3
PD4_GPIO20
PD2_GPIO18
PD3_GPIO19
PB5_GPIO13
PB4_GPIO12
PE2_GPIO26
PG5_GPIO45
PG6_GPIO46
PB7_GPIO15
PB6_GPIO14
PF6_GPIO38
PG2_GPIO42
PE3_GPIO27
PH6_GPIO54
PD7_GPIO23
PH7_GPIO55
PE4_GPIO28
PF3_GPIO35
PJ3_GPIO59
A4
A4
A5
A5
A6
A6
A7
A7
A8
A8
A9
A9
A10
A11
A12
A13
A14
A15
A16
BSEL0
BSEL1
CS0
CS2
CS3
A10
A11
A12
A13
A14
BSEL0
BSEL1
CS0
CS1
CS2
CS3
PC3_GPIO67
PC2_GPIO66
PE4_GPIO28
PC3_GPIO67
PC2_GPIO66
PE4_GPIO28
PJ6_GPIO62
PC1_GPIO65
PJ6_GPIO62
PC1_GPIO65
EPI0S29
EPI0S28
EPI0S32
WR
RD
PD6_GPIO22
PD5_GPIO21
PF2_GPIO34
PJ5_GPIO61
PJ4_GPIO60
PC0_GPIO64
EPI0S29
EPI0S28
EPI0S32
WR
RD
PD6_GPIO22
PD5_GPIO21
PF2_GPIO34
PJ5_GPIO61
PJ4_GPIO60
PC0_GPIO64
RDY
RDY
EPI0S31
EPI0S35
x
x
PG7_GPIO47
PE5_GPIO29
EPI0S31
x
PG7_GPIO47
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
6.1.4.3.2.3 HB-16 FIFO Mode
The HB-16 FIFO Mode uses 16 bits of data, removes ALE and address pins, and optionally adds external
FIFO Full/Empty flag inputs. This scheme is used by many devices, such as radios, communication
devices (including USB2 devices), and some FPGA configuration (FIFO throughblock RAM). This FIFO
Mode presents the data side of the normal Host-Bus interface, but is paced by FIFO control signals. It is
important to consider that the FIFO Full/Empty control inputs may stall the EPI interface and can
potentially block other CPU or DMA accesses. For detailed maps of the HB-16 FIFO Mode, see Table 6-
12.
Table 6-12. EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE = 0x3),
FIFO Mode (EPIHB16CFG/MODE = 0x3)
EPI PORT NAME
EPI SIGNAL FUNCTION
DEVICE PIN
With One
Chip Select
(CSCFG = 0x1)
With Two
Chip Selects
(CSCFG = 0x2)
Accessible by
Cortex™-M3
(Available GPIOMUX_1
Muxing Choices for EPI)
Accessible by C28x
EPI0S0
D0
D1
D0
D1
PH3_GPIO51
EPI0S1
EPI0S2
EPI0S3
EPI0S4
EPI0S5
EPI0S6
EPI0S7
EPI0S8
EPI0S9
EPI0S10
EPI0S11
EPI0S12
EPI0S13
EPI0S14
EPI0S15
PH2_GPIO50
PC4_GPIO68
PC5_GPIO69
PC6_GPIO70
PC7_GPIO71
PH0_GPIO48
PH1_GPIO49
PE0_GPIO24
PE1_GPIO25
PH4_GPIO52
PH5_GPIO53
PF4_GPIO36
PG0_GPIO40
PG1_GPIO41
PF5_GPIO37
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
D8
D8
D9
D9
D10
D11
D12
D13
D14
D15
D10
D11
D12
D13
D14
D15
EPI0S25
EPI0S30
x
CS1
CS0
PE3_GPIO27
PD7_GPIO23
CS0
PJ6_GPIO62
EPI0S27
EPI0S26
EPI0S29
EPI0S28
EPI0S32
FFULL
FEMPTY
WR
FFULL
FEMPTY
WR
PH7_GPIO55
PH6_GPIO54
PD6_GPIO22
PD5_GPIO21
PF2_GPIO34
PJ5_GPIO61
PJ4_GPIO60
PC0_GPIO64
RD
RD
x
x
EPI0S16
EPI0S17
EPI0S18
EPI0S19
EPI0S20
EPI0S21
EPI0S22
EPI0S23
EPI0S24
EPI0S31
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
PJ0_GPIO56
PJ1_GPIO57
PJ2_GPIO58
PD4_GPIO20
PD2_GPIO18
PD3_GPIO19
PB5_GPIO13
PB4_GPIO12
PE2_GPIO26
PG7_GPIO47
PJ3_GPIO59
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
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Table 6-12. EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE = 0x3),
FIFO Mode (EPIHB16CFG/MODE = 0x3) (continued)
EPI PORT NAME
EPI SIGNAL FUNCTION
DEVICE PIN
With One
Chip Select
(CSCFG = 0x1)
With Two
Chip Selects
(CSCFG = 0x2)
Accessible by
Cortex™-M3
(Available GPIOMUX_1
Muxing Choices for EPI)
Accessible by C28x
EPI0S33
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
PF3_GPIO35
PC1_GPIO65
EPI0S34
EPI0S35
EPI0S36
EPI0S37
EPI0S38
EPI0S39
EPI0S40
EPI0S41
PE4_GPIO28
PE5_GPIO29
PB7_GPIO15
PB6_GPIO14
PF6_GPIO38
PG2_GPIO42
PG5_GPIO45
PG6_GPIO46
PC3_GPIO67
PC2_GPIO66
PE4_GPIO28
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
6.2 Master Subsystem Peripherals
Master Subsystem peripherals are located on the APB Bus and AHB Bus, and are accessible from the
Cortex™-M3 CPU/µDMA. The AHB peripherals include EPI, USB, and two CAN modules. The APB
peripherals include EMAC, two I2Cs, five UARTs, four SSIs, four GPTIMERs, two WDOGs, NMI WDOG,
and a µCRC module (Cyclic Redundancy Check). The Cortex™-M3 CPU/µDMA also have access to
Analog (Result Registers only) and Shared peripherals (see Section 6.1).
6.2.1 Synchronous Serial Interface (SSI)
This device has four Synchronous Serial Interface (SSI) modules. Each SSI has a Master or Slave
interface for synchronous serial communication with peripheral devices that have Texas Instruments™
Synchronous Serial interfaces, SPI, MICROWIRE®, or Freescale™ serial format.
The SSI peripheral performs serial-to-parallel conversion on data received from a peripheral device. The
CPU accesses data, control, and status information. The transmit and receive paths are buffered with
internal FIFO memories, allowing up to eight 16-bit values to be stored independently in both transmit and
receive modes. The SSI also supports µDMA transfers. The transmit and receive FIFOs can be
programmed as destination/source addresses in the µDMA module. An µDMA operation is enabled by
setting the appropriate bit or bits in the SSIDMACTL register.
Figure 6-9 shows the SSI peripheral.
6.2.1.1 Bit Rate Generation
The SSI includes a programmable bit-rate clock divider and prescaler to generate the serial output clock.
Bit rates are supported to 2 MHz and higher, although maximum bit rate is determined by peripheral
devices. The serial bit rate is derived by dividing-down the input clock (SysClk). The clock is first divided
by an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale
(SSICPSR) register. The clock is further divided by a value from 1 to 256, which is 1 + SCR, where SCR
is the value programmed in the SSI Control 0 (SSICR0) register. The frequency of the output clock SSIClk
is defined by:
SSIClk = SysClk / [CPSDVSR * (1 + SCR)]
NOTE
For master mode, the system clock must be at least four times faster than SSIClk, with the
restriction that SSIClk cannot be faster than 25 MHz. For slave mode, the system clock must
be at least 12 times faster than SSIClk.
6.2.1.2 Transmit FIFO
The transmit FIFO is a 16-bit-wide, 8-location-deep, first-in, first-out memory buffer. The CPU writes data
to the FIFO through the SSI Data (SSIDR) register, and data is stored in the FIFO until the data is read
out by the transmission logic. When configured as a master or a slave, parallel data is written into the
transmit FIFO prior to serial conversion and transmission to the attached slave or master, respectively,
through the SSITx pin.
In slave mode, the SSI transmits data each time the master initiates a transaction. If the transmit FIFO is
empty and the master initiates a transaction, the slave transmits the 8th most recent value in the transmit
FIFO. If less than eight values have been written to the transmit FIFO since the SSI module clock was
enabled using the SSI bit in the RGCG1 register, then "0" is transmitted. Care should be taken to ensure
that valid data is in the FIFO as needed. The SSI can be configured to generate an interrupt or an µDMA
request when the FIFO is empty.
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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SSIxIRQ
INTR
M3
M3 CLOCKS
M3 NVIC
CPU
M3SSCLK
M3CLKENBx
REGISTER
ACCESS
SSI
DMA
CLOCK
CONTROL
PRESCALER
DMAxREQ
M3
uDMA
SSICPSR REG
SSIDMACTL REG
TX/RX FIFO
ACCESS
SSIxCLK
SSITX
SSIRX
SSICLK
SSIFSS
TX FIFO
CONTROL
( 8 x 16 )
PIN
PIN
PIN
PIN
/ STATUS
SSICR0 REG
SSICR1 REG
SSISR REG
TX
RX
TRANSMIT
/ RECEIVE
LOGIC
FIFO
STAT
FIFO
STAT
SSIDR REG
RX FIFO
( 8 x 16 )
SSIIM REG
SSIPCELLID0 REG
SSIPCELLID1 REG
SSIPCELLID2 REG
SSIPCELLID3 REG
SSIPERIPHLD0 REG
SSIPERIPHLD1REG
SSIPERIPHLD2 REG
SSIPERIPHLD3 REG
SSIPERIPHLD4 REG
SSIPERIPHLD5 REG
SSIPERIPHLD6 REG
SSIPERIPHLD7 REG
SSIMIS REG
SSIRIS REG
SSIICR REG
INTxREQ
INTR CONTROL
IDENTIFICATION REGISTERS
Figure 6-9. SSI
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
6.2.1.3 Receive FIFO
The receive FIFO is a 16-bit-wide, 8-location-deep, first-in, first-out memory buffer. Received data from the
serial interface is stored in the buffer until read out by the CPU, which accesses the read FIFO by reading
the SSIDR register. When configured as a master or slave, serial data received through the SSIRx pin is
registered prior to parallel loading into the attached slave or master receive FIFO, respectively.
6.2.1.4 Interrupts
The SSI can generate interrupts when the following conditions are observed:
•
•
•
•
•
Transmit FIFO service (when the transmit FIFO is half full or less)
Receive FIFO service (when the receive FIFO is half full or more)
Receive FIFO time-out
Receive FIFO overrun
End of transmission
All of the interrupt events are ORed together before being sent to the interrupt controller, so the SSI
generates a single interrupt request to the controller regardless of the number of active interrupts. Each of
the four individual maskable interrupts can be masked by clearing the appropriate bit in the SSI Interrupt
Mask (SSIIM) register. Setting the appropriate mask bit enables the interrupt.
The individual outputs, along with a combined interrupt output, allow the use of either a global interrupt
service routine or modular device drivers to handle interrupts. The transmit and receive dynamic data-flow
interrupts have been separated from the status interrupts so that data can be read or written in response
to the FIFO trigger levels. The status of the individual interrupt sources can be read from the SSI Raw
Interrupt Status (SSIRIS) and SSI Masked Interrupt Status (SSIMIS) registers.
The receive FIFO has a time-out period that is 32 periods at the rate of SSIClk (whether or not SSIClk is
currently active) and is started when the RX FIFO goes from EMPTY to not-EMPTY. If the RX FIFO is
emptied before 32 clocks have passed, the time-out period is reset. As a result, the ISR should clear the
Receive FIFO Time-out Interrupt just after reading out the RX FIFO by writing a "1" to the RTIC bit in the
SSI Interrupt Clear (SSIICR) register. The interrupt should not be cleared so late that the ISR returns
before the interrupt is actually cleared, or the ISR may be reactivated unnecessarily.
The End-of-Transmission (EOT) interrupt indicates that the data has been transmitted completely. This
interrupt can be used to indicate when it is safe to turn off the SSI module clock or enter sleep mode. In
addition, because transmitted data and received data complete at exactly the same time, the interrupt can
also indicate that read data is ready immediately, without waiting for the receive FIFO time-out period to
complete.
6.2.1.5 Frame Formats
Each data frame is between 4 bits and 16 bits long, depending on the size of data programmed, and is
transmitted starting with the MSB. Three basic frame types can be selected:
•
•
•
Texas Instruments™ Synchronous Serial
Freescale™ SPI
MICROWIRE®
For all three formats, the serial clock (SSIClk) is held inactive while the SSI is idle, and SSIClk transitions
at the programmed frequency only during active transmission or reception of data. The idle state of SSIClk
is utilized to provide a receive time-out indication that occurs when the receive FIFO still contains data
after a time-out period.
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F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
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6.2.2 Universal Asynchronous Receiver/Transmitter (UART)
This device has five Universal Asynchronous Receiver/Transmitter (UART) modules. The CPU accesses
data, control, and status information. The UART also supports µDMA transfers. Each UART performs
functions of parallel-to-serial and serial-to-parallel conversions. Each of the five UART modules is similar
in functionality to a 16C550 UART, but is not register-compatible.
The UART is configured for transmit and receive via the TXE bit and the RXE bit, respectively, of the
UART Control (UARTCTL) register. Transmit and receive are both enabled out of reset. Before any control
registers are programmed, the UART must be disabled by clearing the UARTEN bit in UARTCTL. If the
UART is disabled during a TX or RX operation, the current transaction is completed prior to the UART
stopping.
The UART module also includes a serial IR (SIR) encoder/decoder block that can be connected to an
infrared transceiver to implement an IrDA SIR physical layer. The SIR function is programmed using the
UARTCTL register.
Figure 6-10 shows the UART peripheral.
6.2.2.1 Baud-Rate Generation
The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part. The
number formed by these two values is used by the baud-rate generator to determine the bit period. Having
a fractional baud-rate divider allows the UART to generate all the standard baud rates.
The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) register, and the 6-
bit fractional part is loaded with the UART Fractional Baud-Rate Divisor (UARTFBRD) register. The baud
rate divisor (BRD) has the following relationship to the system clock (where BRDI is the integer part of the
BRD, and BRDF is the fractional part, separated by a decimal place).
BRD = BRDI + BRDF = UARTSysClk / (ClkDiv * Baud Rate)
where UARTSysClk is the system clock connected to the UART, and ClkDiv is either 16 (if HSE in
UARTCTL is clear) or 8 (if HSE is set).
The 6-bit fractional number (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register) can
be calculated by taking the fractional part of the baud-rate divisor, multiplying this fractional part by 64,
and adding 0.5 to account for rounding errors:
UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5)
The UART generates an internal baud-rate reference clock at 8x or 16x the baud rate [referred to as
Baud8 and Baud16, depending on the setting of the HSE bit (bit 5 in UARTCTL)]. This reference clock is
divided by 8 or 16 to generate the transmit clock, and is used for error detection during receive operations.
Along with the UART Line Control, High Byte (UARTLCRH) register, the UARTIBRD and UARTFBRD
registers form an internal 30-bit register. This internal register is only updated when a write operation to
UARTLCRH is performed, so any changes to the baud-rate divisor must be followed by a write to the
UARTLCRH register for the changes to take effect.
6.2.2.2 Transmit and Receive Logic
The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO. The
control logic outputs the serial bit stream beginning with a start bit and followed by the data bits (LSB first),
parity bit, and the stop bits according to the programmed configuration in the control registers.
The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start pulse
has been detected. Overrun, parity, frame error checking, and line-break detection are also performed,
and their status accompanies the data that is written to the receive FIFO.
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F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
UARTxIRQ
INTR
M3
M3 CLOCKS
M3 NVIC
CPU
M3SSCLK
UARTCLKENBx
REGISTER
ACCESS
UART
UARTxCLK
DMA
BAUDE RATE
CONTROL
DMAxREQ
GENERATOR
M3
uDMA
UARTIBRD REG
UARTFBRD REG
UARTDMACTL REG
TX/RX FIFO
ACCESS
XCLK
TRANSMITTER
UxTX
TX FIFO
CONTROL
(WITH SIR TRANSMIT
ENCODER)
( 8 x 16 )
/ STATUS
PIN
UARTCR0 REG
UARTCR1 REG
UARTSR REG
TX
RX
FIFO
STAT
FIFO
STAT
UARTDR REG
RECEIVER
UxRX
RX FIFO
(WITH SIR RECEIVE
DECODER)
( 8 x 16 )
PIN
UARTIFLS REG
UARTPCELLID0
UARTPCELLID1
UARTPCELLID2
UARTPCELLID3
UARTPERIPHLD0
UARTPERIPHLD1
UARTPERIPHLD2
UARTPERIPHLD3
UARTPERIPHLD4
UARTPERIPHLD5
UARTPERIPHLD6
UARTPERIPHLD7
UARTIM REG
UARTMIS REG
UARTRIS REG
UARTICR REG
INTxREQ
IDENTIFICATION REGISTERS
INTR CONTROL
Figure 6-10. UART
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
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6.2.2.3 Data Transmission and Reception
Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra four
bits per character for status information. For transmission, data is written into the transmit FIFO. If the
UART is enabled, a data frame starts transmitting with the parameters indicated in the UARTLCRH
register. Data continues to be transmitted until there is no data left in the transmit FIFO. The BUSY bit in
the UART Flag (UARTFR) register is asserted as soon as data is written to the transmit FIFO (that is, if
the FIFO is non-empty) and remains asserted while data is being transmitted. The BUSY bit is negated
only when the transmit FIFO is empty, and the last character has been transmitted from the shift register,
including the stop bits. The UART can indicate that it is busy even though the UART may no longer be
enabled.
When the receiver is idle (the UnRx signal is continuously "1"), and the data input goes Low (a start bit
has been received), the receive counter begins running and data is sampled on the eighth cycle of
Baud16 or the fourth cycle of Baud8, depending on the setting of the HSE bit (bit 5 in UARTCTL).
The start bit is valid and recognized if the UnRx signal is still low on the eighth cycle of Baud16 (HSE
clear) or the fourth cycle of Baud 8 (HSE set), otherwise the start bit is ignored. After a valid start bit is
detected, successive data bits are sampled on every 16th cycle of Baud16 or 8th cycle of Baud8 (that is,
one bit period later), according to the programmed length of the data characters and value of the HSE bit
in UARTCTL. The parity bit is then checked if parity mode is enabled. Data length and parity are defined
in the UARTLCRH register.
Lastly, a valid stop bit is confirmed if the UnRx signal is High, otherwise a framing error has occurred.
When a full word is received, the data is stored in the receive FIFO along with any error bits associated
with that word.
6.2.2.4 Interrupts
The UART can generate interrupts when the following conditions are observed:
•
•
•
•
•
•
Overrun Error
Break Error
Parity Error
Framing Error
Receive Time-out
Transmit (when the condition defined in the TXIFLSEL bit in the UARTIFLS register is met, or if the
EOT bit in UARTCTL is set, when the last bit of all transmitted data leaves the serializer)
•
Receive (when the condition defined in the RXIFLSEL bit in the UARTIFLS register is met)
All of the interrupt events are ORed together before being sent to the interrupt controller, so the UART can
only generate a single interrupt request to the controller at any given time. Software can service multiple
interrupt events in a single interrupt service routine by reading the UART Masked Interrupt Status
(UARTMIS) register.
The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt Mask
(UARTIM) register by setting the corresponding IM bits. If interrupts are not used, the raw interrupt status
is always visible via the UART Raw Interrupt Status (UARTRIS) register.
Interrupts are always cleared (for both the UARTMIS and UARTRIS registers) by writing a "1" to the
corresponding bit in the UART Interrupt Clear (UARTICR) register.
The receive time-out interrupt is asserted when the receive FIFO is not empty, and no further data is
received over a 32-bit period. The receive time-out interrupt is cleared either when the FIFO becomes
empty through reading all the data (or by reading the holding register), or when a "1" is written to the
corresponding bit in the UARTICR register.
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
6.2.3 Cortex™-M3 Inter-Integrated Circut (I2C)
This device has two Cortex™-M3 I2C peripherals. The Cortex™-M3 Inter-Integrated Circuit (I2C) bus
provides bidirectional data transfer through a two-wire design (a serial data line SDA and a serial clock
line SCL), and interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking
devices, LCDs, tone generators, and so on. The I2C bus may also be used for system testing and
diagnostic purposes in product development and manufacture. The microcontroller includes two I2C
modules, providing the ability to interact (both transmit and receive) with other I2C devices on the bus.
The two Cortex™-M3 I2C modules include the following features:
•
Devices on the I2C bus can be designated as either a master or a slave
–
–
Supports both transmitting and receiving data as either a master or a slave
Supports simultaneous master and slave operation
•
Four I2C modes
–
–
–
–
Master transmit
Master receive
Slave transmit
Slave receive
•
•
Two transmission speeds: Standard (100 Kbps) and Fast (400 Kbps)
Master and slave interrupt generation
–
Master generates interrupts when a transmit or receive operation completes (or aborts due to an
error)
–
Slave generates interrupts when data has been transferred or requested by a master or when a
START or STOP condition is detected
•
Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode
Figure 6-11 shows the Cortex™-M3 I2C peripheral.
6.2.3.1 Functional Overview
Each I2C module comprises both master and slave functions. For proper operation, the SDA and SCL
pins must be configured as open-drain signals.
The I2C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL. SDA is the bidirectional
serial data line and SCL is the bidirectional serial clock line. The bus is considered idle when both lines
are high.
Every transaction on the I2C bus is nine bits long, consisting of eight data bits and a single acknowledge
bit. The number of bytes per transfer (defined as the time between a valid START and STOP condition) is
unrestricted, but each byte has to be followed by an acknowledge bit, and data must be transferred MSB
first. When a receiver cannot receive another complete byte, the receiver can hold the clock line SCL Low
and force the transmitter into a wait state. The data transfer continues when the receiver releases the
clock SCL.
6.2.3.2 Available Speed Modes
The I2C bus can run in either standard mode (100 Kbps) or fast mode (400 Kbps). The selected mode
should match the speed of the other I2C devices on the bus.
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
I2CxIRQ
INTR
M3
M3 CLOCKS
M3 NVIC
CPU
M3SSCLK
M3CLKENBx
REGISTER
ACCESS
I2CxCLK
I2C (M3)
I2CSCL_M
I2CSDA_M
I2C
I2CMSA REG
I2CxSCL
CONTROL
I2C MASTER CORE
I2CMCS REG
I2CMTPR REG
I2CMCR REG
PIN
I2CSOAR REG
I2CSCSR REG
I2C I/O
SELECT
I2CMDR REG
I2CMIMR REG
I2CMRISREG
I2CMMIS REG
I2CMICR REG
I2CSDR REG
I2CSIMR REG
I2CSRISREG
I2CSMIS REG
I2CSICR REG
I2CSCL_S
I2CSDA_S
I2CxSDA
I2C SLAVE CORE
PIN
Figure 6-11. I2C (Cortex™-M3)
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
6.2.4 Cortex™-M3 Controller Area Network (CAN)
This device has two Cortex™-M3 Controller Area Network (CAN) peripherals. CAN is a serial
communications protocol that efficiently supports distributed real-time control with a high level of security.
The CAN module supports bit rates up to 1 Mbit/s and is compliant with the CAN 2.0B protocol
specification.
CAN implements the following features:
•
•
•
•
•
•
•
•
•
•
•
•
•
CAN protocol version 2.0 part A, B
Bit rates up to 1 Mbit/s
Multiple clock sources
32 message objects
Individual identifier mask for each message object
Programmable FIFO mode for message objects
Programmable loop-back modes for self-test operation
Suspend mode for debug support
Software module reset
Automatic bus on after Bus-Off state by a programmable 32-bit timer
Message RAM parity check mechanism
Two interrupt lines
Global power down and wakeup support
Figure 6-12 shows the Cortex™-M3 CAN peripheral.
6.2.4.1 Functional Overview
CAN performs CAN protocol communication according to ISO 11898-1 (identical to Bosch® CAN protocol
specification 2.0 A, B). The bit rate can be programmed to values up to 1 Mbit/s. Additional transceiver
hardware is required for the connection to the physical layer (CAN bus).
For communication on a CAN network, individual message objects can be configured. The message
objects and identifier masks are stored in the Message RAM. All functions concerning the handling of
messages are implemented in the message handler. Those functions are: acceptance filtering, the transfer
of messages between the CAN Core and the Message RAM, and the handling of transmission requests.
The register set of the CAN is accessible directly by the CPU via the module interface. These registers are
used to control/configure the CAN Core and the message handler, and to access the message RAM.
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
CANxIRQ
INTR
M3
M3 CLOCKS
M3 NVIC
CPU
M3SSCLK
M3CLKENBx
REGISTER
ACCESS
CANxCLK
CAN (M3)
CANxTX
MODULE INTERFACE
PIN
MESSAGE
RAM
REGISTERS AND MESSAGE
OBJECT ACCESS (IFX)
CAN
CORE
32 MESSAGE
OBJECTS
CANxRX
MESSAGE RAM
INTERFACE
MESSAGE HANDLER
PIN
Figure 6-12. CAN (Cortex™-M3)
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
6.2.5 Cortex™-M3 Universal Serial Bus (USB) Controller
This device has one Cortex™-M3 USB controller. The USB controller operates as a full-speed or low-
speed function controller during point-to-point communications with the USB Host, Device, or OTG
functions. The controller complies with the USB 2.0 standard, which includes SUSPEND and RESUME
signaling. Thirty-two endpoints, which comprised of 2 hardwired endpoints for control transfers (one
endpoint for IN and one endpoint for OUT) and 30 endpoints defined by firmware, along with a dynamic
sizable FIFO, support multiple packet queuing. DMA access to the FIFO allows minimal interference from
system software. Software-controlled connect and disconnect allow flexibility during USB device start-up.
The controller complies with the OTG standard's Session Request Protocol (SRP) and Host Negotiation
Protocol (HNP).
The USB controller includes the following features:
•
•
•
•
•
Complies with USB-IF certification standards
USB 2.0 full-speed (12-Mbps) and low-speed (1.5-Mbps) operation
Integrated PHY
Four transfer types: Control, Interrupt, Bulk, and Isochronous
32 endpoints:
–
–
One dedicated control IN endpoint and one dedicated control OUT endpoint
15 configurable IN endpoints and 15 configurable OUT endpoints
•
4KB dedicated endpoint memory: one endpoint may be defined for double-buffered 1023-byte
isochronous packet size
•
•
VBUS droop and valid ID detection and interrupt
Efficient transfers using direct memory access controller (DMA):
–
–
Separate channels for transmit and receive for up to three IN endpoints and three OUT endpoints
Channel requests asserted when FIFO contains required amount of data
Figure 6-13 shows the USB peripheral.
6.2.5.1 Functional Description
The USB controller provides full OTG negotiation by supporting both the Session Request Protocol (SRP)
and the Host Negotiation Protocol (HNP). The SRP allows devices on the B side of a cable to request the
A-side devices' turn on VBUS. The HNP is used after the initial session request protocol has powered the
bus and provides a method to determine which end of the cable will act as the Host controller. When the
device is connected to non-OTG peripherals or devices, the controller can detect which cable end was
used and provides a register to indicate if the controller should act as the Host controller or the Device
controller. This indication and the mode of operation are handled automatically by the USB controller. This
autodetection allows the system to use a single A/B connector instead of having both A and B connectors
in the system, and supports full OTG negotiations with other OTG devices.
In addition, the USB controller provides support for connecting to non-OTG peripherals or Host controllers.
The USB controller can be configured to act as either a dedicated Host or Device, in which case, the
USB0VBUS and USB0ID signals can be used as GPIOs. However, when the USB controller is acting as a
self-powered Device, a GPIO input must be connected to VBUS and configured to generate an interrupt
when the VBUS level drops. This interrupt is used to disable the pullup resistor on the USB0DP signal.
NOTE
When the USB is used in the system, the minimum system frequency is 20 MHz.
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
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INTR
M3
M3 CLOCKS
M3 NVIC
CPU
M3SSCLK
USBCLKENB
USBPLLCLK
REGISTER
ACCESS
USBMAC_IRQ
USB
CPU
ENDPOINT CONTROL
INTERFACE
EP REGISTER
DECODER
TRANSMIT
EP 0-31
CONTROL
USB0EPEN
USB0PFLT
RECEIVE
COMMON
REGS
PIN
PIN
CYCLE
HOST TRANSACTION
SCHEDULER
COMBINE
CONTROL
ENDPOINTS
PHY
FIFO DECODER
USB0VBUS
FIFO RAM CONTROLLER
PACKET
UTM
(5V TOLERANT)
INTERRUPT
CONTROL
ENCODE / DECODE
SYNCHRONIZATION
PIN
PIN
PIN
PIN
TX
TX
BUFF
BUFF
USB0ID
PACKET ENCODE
PACKET DECODE
CRC GEN/CHECK
DATA SYNC
(5V TOLERANT)
RX
RX
DMAxREQ
USB0DM
USB0DP
HNP / SRP
TIMERS
BUFF
BUFF
M3
uDMA
TX/RX FIFO
ACCESS
CYCLE CONTROL
USBMAC REQ
Figure 6-13. USB
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
6.2.6 Cortex™-M3 Ethernet Media Access Controller (EMAC)
The Cortex™-M3 Ethernet Media Access Controller (EMAC) conforms to IEEE 802.3 specifications and
fully supports 10BASE-T and 100BASE-TX standards. This device has one Ethernet Media Access
Controller.
The EMAC module has the following features:
•
Conforms to the IEEE 802.3-2002 specification
10BASE-T/100BASE-TX IEEE-802.3 compliant
Multiple operational modes
–
•
–
–
–
Full- and half-duplex 100-Mbps
Full- and half-duplex 10-Mbps
Power-saving and power-down modes
•
Highly configurable:
–
–
–
–
Programmable MAC address
Promiscuous mode support
CRC error-rejection control
User-configurable interrupts
•
•
IEEE 1588 Precision Time Protocol: Provides highly accurate time stamps for individual packets
Efficient transfers using the Micro Direct Memory Access Controller (µDMA)
–
–
–
Separate channels for transmit and receive
Receive channel request asserted on packet receipt
Transmit channel request asserted on empty transmit FIFO
Figure 6-14 shows the EMAC peripheral.
6.2.6.1 Functional Overview
The Ethernet Controller is functionally divided into two layers: the Media Access Controller (MAC) layer
and the Network Physical (PHY) layer. The MAC resides inside the device, and the PHY outside of the
device. These layers correspond to the OSI model layers 2 and 1, respectively. The CPU accesses the
Ethernet Controller via the MAC layer. The MAC layer provides transmit and receive processing for
Ethernet frames. The MAC layer also provides the interface to the external PHY layer via an internal
Media Independent Interface (MII). The PHY layer communicates with the Ethernet bus.
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
EMAC_IRQ
INTR
M3
M3 CLOCKS
M3 NVIC
CPU
M3SSCLK
EMACCLKENB
REGISTER
ACCESS
EMAC
MII_TXCLK
MII_TXEN
DMAxREQ
M3
RECEIVE
INTR CONTROL
PIN
PIN
PIN
uDMA
CONTROL
TX/RX FIFO
ACCESS
MACRIS REG
MACIACK REG
MACIM REG
MACRCTL REG
MACNP REG
MII_TXD(3:0)
TRANSMIT
FIFO
EMACRX_REQ
EMACTX_REQ
MII_CRS
MII_COL
DATA ACCESS
PIN
PIN
MACDDATA REG
TIMER SUPPORT
MACTS REG
MII_RXCLK
MII_RXDV
TRANSMIT
CONTROL
PIN
PIN
PIN
PIN
RECEIVE
FIFO
MACTCTL REG
MACTHR REG
MACTR REG
MII_RXER
MII_RXD(3:0)
MII CONTROL
INDIVIDUAL
ADDRESS
MACMCTL REG
MACMDV REG
MACMTXD REG
MACMRXD REG
MADIX REG
MDIO_CK
MDIO_D
MACIA0 REG
MACIA1 REG
PIN
PIN
MDIO
MACMAR REG
Figure 6-14. EMAC
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
6.2.6.2 MII Signals
The individual EMAC and MDIO signals for the MII interface are summarized in Table 6-13.
Table 6-13. EMAC and MDIO Signals for MII Interface
SIGNAL
TYPE(1)
DESCRIPTION
Transmit clock. The transmit clock is a continuous clock that provides the timing reference
for transmit operations. The MII_TXD and MII_TXEN signals are tied to this clock. The clock
is generated by the PHY and is 2.5 MHz at 10-Mbps operation and 25 MHz at 100-Mbps
operation.
MII_TXCK
I
Transmit data. The transmit data pins are a collection of four data signals comprising 4 bits
of data. MTDX0 is the least-significant bit (LSB). The signals are synchronized by
MII_TXCLK and are valid only when MII_TXEN is asserted.
MII_TXD[3-0]
MII_TXEN
O
O
Transmit enable. The transmit enable signal indicates that the MII_TXD pins are generating
nibble data for use by the PHY. MII_TXEN is driven synchronously to MII_TXCLK.
Collision detected. In half-duplex operation, the MII_COL pin is asserted by the PHY when
the PHY detects a collision on the network. The MII_COL pin remains asserted while the
collision condition persists. This signal is not necessarily synchronous to MII_TXCLK or
MII_RXCLK. In full-duplex operation, the MII_COL pin is used for hardware transmit flow
control. Asserting the MII_COL pin will stop packet transmissions; packets in the process of
being transmitted when MII_COL is asserted will complete transmission. The MII_COL pin
should be held low if hardware transmit flow control is not used.
MII_COL
I
Carrier sense. In half-duplex operation, the MII_CRS pin is asserted by the PHY when the
network is not idle in either transmit or receive. The pin is deasserted when both transmit
and receive are idle. This signal is not necessarily synchronous to MII_TXCLK or
MII_RXCLK. In full-duplex operation, the MII_CRS pin should be held low.
MII_CRS
I
I
Receive clock. The receive clock is a continuous clock that provides the timing reference for
receive operations. The MII_RXD, MII_RXDV, and MII_RXER signals are tied to this clock.
The clock is generated by the PHY and is 2.5 MHz at 10-Mbps operation and 25 MHz at
100-Mbps operation.
MII_RXCK
Receive data. The receive data pins are a collection of four data signals comprising 4 bits of
data. MRDX0 is the least-significant bit (LSB). The signals are synchronized by MII_RXCLK
and are valid only when MII_RXDV is asserted.
MII_RXD[3-0]
MII_RXDV
MII_RXER
I
I
I
Receive data valid. The receive data valid signal indicates that the MII_RXD pins are
generating nibble data for use by the EMAC. MII_RXDV is driven synchronously to
MII_RXCLK.
Receive error. The receive error signal is asserted for one or more MII_RXCLK periods to
indicate that an error was detected in the received frame. The MII_RXER signal being
asserted is meaningful only during data reception when MII_RXDV is active.
Management data clock. The MDIO data clock is sourced by the MDIO module on the
system. MDIO_CK is used to synchronize MDIO data access operations done on the MDIO
pin. The frequency of this clock is controlled by the CLKDIV bits in the MDIO Control
Register (CONTROL).
MDIO_CK
MDIO_D
O
Management data input output. The MDIO data pin drives PHY management data into and
out of the PHY by way of an access frame that consists of start-of-frame, read/write
indication, PHY address, register address, and data bit cycles. The MDIO_D pin acts as an
output for all but the data bit cycles, at which time the pin is an input for read operations.
I/O
(1) I = Input, O = Output, I/O = Input/Output
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6.3 Control Subsystem Peripherals
Control Subsystem peripherals are accessible from the C28x CPU via the C28x Memory Bus, and from
the C28x DMA via the C28x DMA Bus. They include one NMI Watchdog, three Timers, four Serial Port
Peripherals (SCI, SPI, McBSP, I2C), and three types of Control Peripherals (ePWM, eQEP, eCAP).
Additionally, the C28x CPU/DMA also have access to the External Peripheral Interface (EPI), and to
Analog and Shared peripherals (see Section 6.1).
6.3.1 High-Resolution PWM (HRPWM) and Enhanced PWM (ePWM) Modules
There are nine PWM modules in the Concerto device. Eight of these are of the High-Resolution PWM
(HRPWM) type with high-resolution control on both A and B signal outputs, and one is of the Enhanced
PWM (ePWM) type. The HRPWM modules have all the features of the ePWM plus they offer significantly
higher PWM resolution (time granularity on the order of 150 ps). Figure 6-15 shows the eight HRPWM
modules (PWM 1–8) and one ePWM module (PWM 9).
The synchronization inputs to the PWM modules include the SYNCI signal from the GPTRIP1 output of
GPIO_MUX1, and the TBCLKSYNC signal from the CPCLKCR0 register. Synchronization output
SYNCO1 comes from the ePWM1 module and is stretched by 8 HSPCLK cycles before entering
GPIO_MUX1. There are two groups of trip signal inputs to PWM modules. TRIP1–15 inputs come from
GPTRIP1–12 (from GPIO_MUX1), ECCDBLERR signal (from C28x Local and Shared RAM), and PIEERR
signal from the C28x CPU. TZ1–6 (Trip Zone) inputs come from GPTRIP 1–3 (from GPIO_MUX1),
EQEPERR (from the eQEP peripheral), CLOCKFAIL (from M3 CLOCKS), and EMUSTOP (from the C28x
CPU).
There are 9 SOCA PWM outputs and 9 SOCB PWM outputs—a pair from each PWM module. The
9 SOCA outputs are OR-ed together and stretched by 32 HSPCLK cycles before entering GPIO_MUX1 as
a single SOCAO signal. The 9 SOCB outputs are OR-ed together and stretched by 32 HSPCLK cycles
before entering GPIO_MUX1 as a single SOCBO signal. The 18 SOCA/B outputs from PWM1–PWM9
also go to the Analog Subsystem, where they can be selected to become conversion triggers to ADC
modules.
The nine PWM modules also drive two other sets of outputs which can interrupt the C28x CPU via the
C28x PIE block. These are nine EPWMINT interrupts and nine EPWMTZINT trip-zone interrupts. See
Figure 6-16 for the internal structure of the HRPWM and ePWM modules. The green-colored blocks are
common to both ePWM and HRPWM modules, but only the HRPWMs have the grey-colored hi-resolution
blocks.
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
SOCA (9:1)
SOCB(9:1)
PULSE STRETCH
SOCAO
SOCBO
32 HSPCLK CYCLES
PULSE STRETCH
32 HSPCLK CYCLES
GPTRIP6
EPWM (9:1) A
SYNCI
TRIPIN1
GPTRIP1
GPTRIP2
GPTRIP3
GPTRIP4
GPTRIP5
GPTRIP6
GPTRIP7
GPTRIP8
GPTRIP9
GPTRIP10
GPTRIP11
GPTRIP12
‘0’
TRIPIN2
TRIPIN3
TRIPIN4
TRIPIN5
TRIPIN6
TRIPIN7
TRIPIN8
TRIPIN9
TRIPIN10
TRIPIN11
TRIPIN12
TRIPIN13
TRIPIN14
TRIPIN15
PWM
1
PWM
2
PWM
3
SYNCO
GPTRIP1
GPTRIP2
GPTRIP3
EQEPERR
CLOCKFAIL
EMUSTOP
TZ1
TZ2
TZ3
TZ4
TZ5
TZ6
PWM
4
PWM
5
PWM
6
PWM
7
PWM
8
PWM
9
ECCDBLERR
PIEERR
EPWM (9:1) B
EPWM
TBCLKSYNC
EPWM (9:1) TZINT
EPWM (9:1) INT
SYNCO
SYNCO1
PULSE STRETCH
8 HSPCLK CYCLES
CPCLKCR0 REG
EQEP(3:1)INT
ECAP(6:1)INT
EQEP1A
EQEP1S
EQEP1I
SYNCI
EQEP1B
EQEP 1
ECAP
1
ECAP
ECAP
GPTRIP7
GPTRIP8
GPTRIP9
GPTRIP10
GPTRIP11
GPTRIP12
ECAP1INP
SYNCO
2
3
ECAP2INP
ECAP3INP
ECAP4INP
ECAP5INP
ECAP6INP
EQEP2A
EQEP2B
EQEP2S
EQEP2I
EQEP 2
ECAP
ECAP
ECAP
EQEP3A
EQEP3B
EQEP3S
EQEP3I
4
5
6
ECAP
EQEP
EQEP3
ECAP(6:1)
LEGEND:
PWM
1-8
EPWM +
GPTRIP(1-12)
GPIO_MUX1
ECCDBLERR
PIEERR
EMUSTOP
EQEPERR
CLOCKFAIL
HiRES PWM
PWM
9
EPWM
ONLY
C28x
CPU
C28x
C28x LOCAL RAM
SHARED RAM
CLOCKS
Figure 6-15. PWM, eCAP, eQEP
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
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C28SYSCLK
TBCLKSYNC
TRIPIN(15:1)
(1)
SYNCO
SYNCI
DCAEVT1.SYNC
DCBEVT1.SYNC
DCAEVT1.SOC
DCBEVT1.SOC
TIME BASE
(TB)
PHS
PRD
DIGITAL
TBCLK
CTR=ZER
CTR=PRD
COMPARE
CTR=
(DC)
CMPB
TBCTR
(15:0)
CTR=ZER
TBCTR
(15:0)
HiRES
TBCLK
CTR=PRD
CTR_DIR
CONTROL
CMPA
CMPB
CAL
CNTRL
DCAEVT1.FORCE DCBEVT1.FORCE
DCAEVT2.FORCE DCBEVT2.FORCE
DCAEVT1.SYNC
DCBEVT1.SYNC
COUNTER
COMPARE
RED
FED
DCAEVT1.INTER DCBEVT1.INTER
DCAEVT2.INTER DCBEVT2.INTER
(CC)
CTR=ZER
CTR=PRD
CTR_DIR
EPWM_A
EPWM_B
ACTION
DEAD
BAND
PWM
TRIP
HiRES
PWM
QUALIFIER
CHOPPER
ZONE
CTR=CMPA
CTR=CMPB
(AQ)
(DB)
(PC)
(TZ)
(HRPWM)
SWFSYNC
SYNCI
CTR=ZER
CTR=PRD
C28SYSCLK
CTR=CMPA
CTR=CMPB
CTR=CMPC
CTR=CMPD
DCAEVT1.SOC
DCBEVT1.SOC
EVENT
SYNCI
TRIGGER
(ET)
EPWM_TZINT
EPWM_INT
EPWM_INT
SOCA
SOCB
TZ (6:1)
(1) NOTE THAT SYNCO OUTPUTS FROM PWM MODULES 3,6 AND 9 ARE NOT CONNECTED, THUS THEY ARE NOT USEABLE
Figure 6-16. Internal Structure of PWM
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6.3.2 Enhanced Capture (eCAP) Module
There are six identical eCAP modules in Concerto devices: eCAP1, 2, 3, 4, 5, and 6. Each eCAP module
represents one complete capture channel. Its main function is to accurately capture the timings of external
events. One can also use eCAP modules for PWM, when they are not being used for input captures. This
secondary function is selected by flipping the CAP/APWM bit of the ECCTL2 Register. For PWM function,
the counter operates in count-up mode, providing a time base for asymmetrical pulse width (PWM)
waveforms. The CAP1 and CAP2 registers become the period and compare registers, respectively; while
the CAP3 and CAP4 registers become the shadow registers of the main period and capture registers,
respectively.
The left side of Figure 6-17 shows internal components associated with the capture block, and the right
side depicts the PWM block. The two blocks share a set of four registers that are used in both Capture
and PWM modes. Other components include the Counter block that uses the SYNCIN and SYNCOUT
ports to synchronize with other modules; and the Interrupt Trigger and Flag Control block that sends
Capture, PWM, and Counter events to the C28x PIE block via the ECAPxINT output. There are six
ECAPxINT interrupts—one for each eCAP module.
The eCAP peripherals are clocked by C28SYSCLK, and its registers are accessible by the C28x CPU.
This peripheral clock can be enabled or disabled by flipping a bit in one of the system control registers.
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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EPWM1 OR
OTHER ECAP
SYNCIN
PERIPHERALS
SYNC IN
ECAPx
CTR_OVF
CTR(31:0)
PRD(31:0)
CMP(31:0)
COUNTER
CTRPHS REG
TSCTR REG
SYNCOUT
SYNC OUT
RST
OTHER ECAP
PERIPHERALS
DELTA
MODE
CAPTURE
MODE
PWM
MODE
LD1
LD2
LD3
LD4
POLARITY
CAP1/PERIOD REG
CAP2/COMP REG
CAP3/PER SHDW
CAP4/CMP SHDW
MASTER
SELECT
SUBSYSTEM
C28CLKIN
POLARITY
SELECT
CAPTURE
EVENT
C28SYSCLK
QUALIFIER
POLARITY
SELECT
ECAPxENCLK
PWM
COMPARE
LOGIC
SYSTEM
CONTROL
REGISTERS
POLARITY
SELECT
REGISTER
ACCESS
C28x
CPU
4
4
CTR=PER
CTR=CMP
CTR_OVF
EVENT
PRE-SCALE
CAPTURE
CONTROL
CEVT (4:1)
INTERRUPT TRIGGER
AND FLAG CONTROL
(CAPTURE EVENTS)
MODE
SELECT
ECAPx
PIN
ECCTL2 REG
ECAPxINT
C28x PIE
Figure 6-17. eCAP
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
6.3.3 Enhanced Quadrature Encoder Pulse (eQEP) Module
The Enhanced Quadrature Encoder Pulse (eQEP) module interfaces directly with linear or rotary
incremental encoders to obtain position, direction, and speed information from rotating machines used in
high-performance motion and position-control systems. There are three Type 0 eQEP modules in each
Concerto device.
Each eQEP peripheral comprises five major functional blocks: Quadrature Capture Unit (QCAP), Position
Counter/Control Unit (PCCU), Quadrature Decoder (QDU), Unit Time Base for speed and frequency
measurement (UTIME), and Watchdog timer for detecting stalls (QWDOG). The C28x CPU controls and
communicates with these modules through a set of associated registers (see Figure 6-18). The eQEP
peripherals are clocked by C28SYSCLK, and its registers are accessible by the C28x CPU. This
peripheral clock can be enabled or disabled by flipping a bit in one of the system control registers.
Each eQEP peripheral connects through the GPIO_MUX1 block to four device pins. Two of the four pins
are always inputs, while the other two can be inputs or outputs, depending on the operating mode. The
PCCU block of each eQEP also drives one interrupt to the C28x PIE. There is a total of three EQEPxINT
interrupts—one from each of the three eQEP modules.
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
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MASTER
SUBSYSTEM
EQEPx
QCPRD REG
QCTMR REG
QCAPCTL REG
16
C28CLKIN
16
C28SYSCLK
QUADRATURE CAPTURE UNIT
OCTMRLAT REG
EQEPxENCLK
QCPRDLAT REG
( QCAP )
16
SYSTEM
CONTROL
REGISTERS
REGISTER
ACCESS
C28x
CPU
QUTMR REG
QUPRD REG
QWDTMR REG
QWDPRD REG
REGISTERS USED
32
16
BY MULTIPLE UNITS
QEPCTL REG
QEPSTS REG
QFLG REG
QDECCTL REG
UTOUT
UTIME
QWDOG
16
WDTOUT
EQEPxAIN
EQEPxA
/XCLK
PIN
PIN
PIN
PIN
QCLK
QDIR
QI
EQEPxINT
EQEPxB
/XDIR
EQEPxBIN
POSITION COUNTER/CONTROL UNIT
( PCCU )
QS
QUADRATURE
DECODER
QPOSLAT REG
QPOSSLAT REG
QPOSILAT REG
PHE
PCSOUT
( QDU )
EQEPxIIN
EQEPxIOUT
EQEPxIOE
16
EQEPxI
EQEPxS
32
32
16
QPOSCNT REG
QPOSINIT REG
QPOSMAX REG
QPOSCMP REG
QEINT REG
QFRC REG
EQEPxSIN
EQEPxSOUT
EQEPxSOE
QCLR REG
QPOSCTL REG
Figure 6-18. eQEP
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
6.3.4 C28x Inter-Integrated Circuit Module (I2C)
This device has one C28x inter-integrated circuit (I2C) peripheral. The I2C provides an interface between
a Concerto device and devices compliant with the Philips® I2C-Bus Specification Version 2.1 and
connected by way of an I2C Bus®. External components attached to this 2-wire serial bus can transmit
1-bit to 8-bit data to and receive 1-bit to 8-bit data from the device through the I2C module .
NOTE
A unit of data transmitted or received by the I2C module can have fewer than 8 bits;
however, for convenience, a unit of data is called a data byte in this section. The number of
bits in a data byte is selectable via the BC bits of the mode register, I2CMDR.
The I2C module has the following features:
•
Compliance with the Philips® I2C-Bus Specification Version 2.1:
–
–
–
–
–
–
–
–
Support for 1-bit to 8-bit format transfers
7-bit and 10-bit addressing modes
General call
START byte mode
Support for multiple master-transmitters and slave-receivers
Support for multiple slave-transmitters and master-receivers
Combined master transmit-and-receive and receive-and-transmit mode
Data transfer rate of from 10 Kbps up to 400 Kbps (I2C Fast-mode rate)
•
•
One 4-word receive FIFO and one 4-word transmit FIFO
One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the
following conditions:
–
–
–
–
–
–
–
Transmit-data ready
Receive-data ready
Register-access ready
No-acknowledgment received
Arbitration lost
Stop condition detected
Addressed as slave
•
•
•
An additional interrupt that can be used by the CPU when in FIFO mode
Module enable or disable capability
Free data format mode
The I2C module does not support:
•
•
High-speed mode (Hs-mode)
CBUS-compatibility mode
Figure 6-19 shows the C28x I2C peripheral.
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
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MASTER
I2C (C28)
SUBSYSTEM
REGISTER
C28CLKIN
ACCESS CLK
C28SYSCLK
MASTER CLOCK
DIVIDER
I2CCLK
I2CCLK
I2CPSC REG
I2CA_ENCLK
I2CCLKH REG
I2CCLKL REG
CLOCK
PRESCALER
SYSTEM
CONTROL
REGISTERS
SLAVE CLOCK
I2CASCL
SYNCHRONIZER
MODE AND STATUS
REGISTERS
PIN
C28x
CPU
I2CFFTX REG
I2CMDR REG
I2CSTR REG
REGISTER
ACCESS
TX FIFO
I2CDXR REG
INTR
I2CXSR REG
I2CINT2A
I2CINT1A
I2COAR REG
I2CSAR REG
I2CCNT REG
C28x PIE
I2CASDA
PIN
I2CIER REG
I2CISRC REG
I2CRXR REG
INTERRUPT
CONTROL AND
ARBITRATION
RX FIFO
I2CDRR REG
TX/RX
LOGIC
I2CFFRX REG
Figure 6-19. I2C (C28x)
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SPRS742D –JUNE 2011–REVISED AUGUST 2012
6.3.4.1 Functional Overview
Each device connected to an I2C Bus is recognized by a unique address. Each device can operate as
either a transmitter or a receiver, depending on the function of the device. A device connected to the I2C
Bus can also be considered as the master or the slave when performing data transfers. A master device is
the device that initiates a data transfer on the bus and generates the clock signals to permit that transfer.
During this transfer, any device addressed by this master is considered a slave. The I2C module supports
the multi-master mode, in which one or more devices capable of controlling an I2C Bus can be connected
to the same I2C Bus.
For data communication, the I2C module has a serial data pin (SDA) and a serial clock pin (SCL). These
two pins carry information between the C28x device and other devices connected to the I2C Bus. The SDA
and SCL pins both are bidirectional. They each must be connected to a positive supply voltage using a
pullup resistor. When the bus is free, both pins are high. The driver of these two pins has an open-drain
configuration to perform the required wired-AND function. There are two major transfer techniques:
1. Standard Mode: Send exactly n data values, where n is a value you program in an I2C module
register.
2. Repeat Mode: Keep sending data values until you use software to initiate a STOP condition or a new
START condition.
The I2C module consists of the following primary blocks:
•
•
A serial interface: one data pin (SDA) and one clock pin (SCL)
Data registers and FIFOs to temporarily hold receive data and transmit data traveling between the
SDA pin and the CPU
•
•
Control and status registers
A peripheral bus interface to enable the CPU to access the I2C module registers and FIFOs.
6.3.4.2 Clock Generation
The device clock generator receives a signal from an external clock source and produces an I2C input
clock with a programmed frequency. The I2C input clock is equivalent to the CPU clock and is then
divided twice more inside the I2C module to produce the module clock and the master clock.
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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
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6.3.5 C28x Serial Communications Interface (SCI)
This device has one serial communication interface (SCI) peripheral. SCI is a two-wire asynchronous
serial port, commonly known as a UART. The SCI module supports digital communications between the
CPU and other asynchronous peripherals that use the standard non-return-to-zero (NRZ) format
The SCI receiver and transmitter each have a 16-level-deep FIFO for reducing servicing overhead, and
each has its own separate enable and interrupt bits. Both can be operated independently for half-duplex
communication, or simultaneously for full-duplex communication. To specify data integrity, the SCI checks
received data for break detection, parity, overrun, and framing errors. The bit rate is programmable to
different speeds through a 16-bit baud-select register.
Features of the SCI module include:
•
Two external pins:
–
–
SCITXD: SCI transmit-output pin
SCIRXD: SCI receive-input pin
NOTE: Both pins can be used as GPIO if not used for SCI.
Baud rate programmable to 64K different rates
–
•
Data-word format
–
–
–
–
One start bit
Data-word length programmable from one to eight bits
Optional even/odd/no parity bit
One or two stop bits
•
•
•
•
•
Four error-detection flags: parity, overrun, framing, and break detection
Two wake-up multiprocessor modes: idle-line and address bit
Half- or full-duplex operation
Double-buffered receive and transmit functions
Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms
with status flags.
–
Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX
EMPTY flag (transmitter-shift register is empty)
–
Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag
(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
•
•
Separate enable bits for transmitter and receiver interrupts (except BRKDT)
NRZ (non-return-to-zero) format
NOTE
All registers in this module are 8-bit registers that are connected to Peripheral Frame 2.
When a register is accessed, the register data is in the lower byte (bits 7–0), and the upper
byte (bits 15–8) is read as zeros. Writing to the upper byte has no effect.
•
•
Auto baud-detect hardware logic
4-level transmit and receive FIFO
Figure 6-20 shows the C28x SCI peripheral.
176
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
www.ti.com
SPRS742D –JUNE 2011–REVISED AUGUST 2012
MASTER
SCI (C28)
SUBSYSTEM
SCICTL2 REG
SCICTL1A REG
TX INTERRUPT LOGIC
SCIFFTXA REG
AUTO-BAUD DETECT LOGIC
SCEFFCT REG
C28CLKIN
C28SYSCLK
REGISTER
ACCESS
TX FIFO
SCITXBUF REG
TX DELAY
SCIA_ENCLK
/1
/2
SYSTEM
CONTROL
REGISTERS
/4
C28LSPCLK
SCITXDA
BAUD-RATE GEN
TXSHF REG
…
/14
SCIHBAUD REG
SCILBAUD REG
PIN
C28x
CPU
SCIRXDA
SCICCRA REG
RXSHF REG
REGISTER ACCESS
PIN
SCIRXEMUA REG
SCIRXBUF REG
TX/RX
LOGIC
RX FIFO
INTR
SCIFFRXA REG
SCIPRI REG
SCIRXINA
SCITXINA
RX INTERRUPT LOGIC
C28x PIE
SCRXST REG
Figure 6-20. SCI (C28x)
Copyright © 2011–2012, Texas Instruments Incorporated
Peripheral Information and Timings
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
6.3.5.1 Architecture
The major elements used in full-duplex operation include:
•
•
A transmitter (TX) and its major registers:
–
SCITXBUF register – Transmitter Data Buffer register. Contains data (loaded by the CPU) to be
transmitted
–
TXSHF register – Transmitter Shift register. Accepts data from the SCITXBUF register and shifts
data onto the SCITXD pin, one bit at a time
A receiver (RX) and its major registers:
–
–
RXSHF register – Receiver Shift register. Shifts data in from the SCIRXD pin, one bit at a time
SCIRXBUF register – Receiver Data Buffer register. Contains data to be read by the CPU. Data
from a remote processor is loaded into the RXSHF register and then into the SCIRXBUF and
SCIRXEMU registers
•
•
A programmable baud generator
Data-memory-mapped control and status registers enable the CPU to access the I2C module registers
and FIFOs.
The SCI receiver and transmitter can operate either independently or simultaneously.
6.3.5.2 Multiprocessor and Asynchronous Communication Modes
The SCI has two multiprocessor protocols: the idle-line multiprocessor mode and the address-bit
multiprocessor mode. These protocols allow efficient data transfer between multiple processors.
The SCI offers the universal asynchronous receiver/transmitter (UART) communications mode for
interfacing with many popular peripherals. The asynchronous mode requires two lines to interface with
many standard devices such as terminals and printers that use RS-232-C formats.
Data transmission characteristics include:
•
•
•
•
One start bit
One to eight data bits
An even/odd parity bit or no parity bit
One or two stop bits with a programmed frequency. The I2C input clock is equivalent to the CPU clock
and is then divided twice more inside the I2C module to produce the module clock and the master
clock.
178
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
www.ti.com
SPRS742D –JUNE 2011–REVISED AUGUST 2012
6.3.6 C28x Serial Peripheral Interface (SPI)
This device has one C28x serial peripheral interface (SPI). The serial peripheral interface (SPI) is a high-
speed synchronous serial input/output (I/O) port that allows a serial bit stream of programmed length (1 to
16 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The SPI is normally
used for communications between the DSP controller and external peripherals or another controller.
Typical applications include external I/O or peripheral expansion via devices such as shift registers,
display drivers, and analog-to-digital converters (ADCs). Multi-device communications are supported by
the master/slave operation of the SPI. The port supports a 16-level, receive-and-transmit FIFO for
reducing CPU servicing overhead.
The SPI module features include:
•
•
•
•
SPISOMI: SPI slave-output/master-input pin
SPISIMO: SPI slave-input/master-output pin
SPISTE: SPI slave transmit-enable pin
SPICLK: SPI serial-clock pin
NOTE: All four pins can be used as GPIO, if the SPI module is not used.
Two operational modes: master and slave
•
•
Baud rate: 125 different programmable rates. The maximum baud rate that can be employed is limited
by the maximum speed of the I/O buffers used on the SPI pins.
•
•
Data word length: 1 to 16 data bits
Four clocking schemes (controlled by clock polarity and clock phase bits) include:
–
–
–
–
Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
•
•
Simultaneous receive-and-transmit operation (transmit function can be disabled in software)
Transmitter and receiver operations are accomplished through either interrupt-driven or polled
algorithms.
•
Twelve SPI module control registers: Located in control register frame beginning at address 7040h.
NOTE
All registers in this module are 16-bit registers that are connected to Peripheral Frame 2.
When a register is accessed, the register data is in the lower byte (bits 7−0), and the upper
byte (bits 15−8) is read as zeros. Writing to the upper byte has no effect.
•
•
16-level transmit and receive FIFO
Delayed transmit control
Figure 6-21 shows the C28x SPI peripheral.
Copyright © 2011–2012, Texas Instruments Incorporated
Peripheral Information and Timings
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
MASTER
SPI (C28)
SUBSYSTEM
TX INTERRUPT LOGIC
SPIFFTX REG
C28CLKIN
SPICTL REG
SPISIMOA
SPISOMIA
SPISTEA
SPIFFCT REG
TX DELAY
PIN
PIN
PIN
PIN
C28SYSCLK
REGISTER
(1)
TX FIFO
SPITXBUF REG
ACCESS
SPIA_ENCLK
/1
/2
SYSTEM
SPI BIT RATE
SPIBRR REG
C28LSPCLK
/4
CONTROL
SPIDAT REG
…
REGISTERS
/14
SPICCR REG
C28x
CPU
REGISTER ACCESS
(1)
TX/RX
LOGIC
RX FIFO
SPICLKA
SPIRXBUF REG
SPIRXEMU REG
INTR
SPIFFRX REG
SPIPRI REG
SPITXINA
SPIRXINA
SPIST REG
RX INTERRUPT LOGIC
C28x PIE
(1) RX FIFO AND TX FIFO CAN BE BYPASSED BY CONFIGURING BIT SPIFFENA OF THE SPIFFTX REGISTER
Figure 6-21. SPI (C28x)
180
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
www.ti.com
SPRS742D –JUNE 2011–REVISED AUGUST 2012
6.3.6.1 Functional Overview
The SPI operates in master or slave mode. The master initiates data transfer by sending the SPICLK
signal. For both the slave and the master, data is shifted out of the shift registers on one edge of the
SPICLK and latched into the shift register on the opposite SPICLK clock edge. If the CLOCK PHASE bit
(SPICTL.3) is high, data is transmitted and received a half-cycle before the SPICLK transition. As a result,
both controllers send and receive data simultaneously. The application software determines whether the
data is meaningful or dummy data. There are three possible methods for data transmission:
•
•
•
Master sends data; slave sends dummy data
Master sends data; slave sends data
Master sends dummy data; slave sends data
The master can initiate a data transfer at any time because it controls the SPICLK signal. The software,
however, determines how the master detects when the slave is ready to broadcast data.
Copyright © 2011–2012, Texas Instruments Incorporated
Peripheral Information and Timings
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
6.3.7 C28x Multichannel Buffered Serial Port (McBSP)
This device provides one high-speed multichannel buffered serial port (McBSP) that allows direct interface
to codecs and other devices. The CPU accesses data, control, and status information. The MCBSP also
supports µDMA transfers.
The McBSP consists of a data-flow path and a control path connected to external devices by six pins.
Data is communicated to devices interfaced with the McBSP via the data transmit (DX) pin for
transmission and via the data receive (DR) pin for reception. Control information in the form of clocking
and frame synchronization is communicated via the following pins: CLKX (transmit clock), CLKR (receive
clock), FSX (transmit frame synchronization), and FSR (receive frame synchronization).
The CPU and the DMA controller communicate with the McBSP through 16-bit-wide registers accessible
via the internal peripheral bus. The CPU or the DMA controller writes the data to be transmitted to the
data transmit registers (DXR1, DXR2). Data written to the DXRs is shifted out to DX via the transmit shift
registers (XSR1, XSR2). Similarly, receive data on the DR pin is shifted into the receive shift registers
(RSR1, RSR2) and copied into the receive buffer registers (RBR1, RBR2). The contents of the RBRs is
then copied to the DRRs, which can be read by the CPU or the DMA controller. This method allows
simultaneous movement of internal and external data communications.
DRR2, RBR2, RSR2, DXR2, and XSR2 are not used (written, read, or shifted) if the serial word length is
8 bits, 12 bits, or 16 bits. For larger word lengths, these registers are needed to hold the most significant
bits.
The frame and clock loop-back is implemented at chip level to enable CLKX and FSX to drive CLKR and
FSR. If the loop-back is enabled, the CLKR and FSR get their signals from the CLKX and FSX pads
instead of the CLKR and FSR pins.
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
www.ti.com
SPRS742D –JUNE 2011–REVISED AUGUST 2012
McBSP features include:
•
•
•
•
•
•
•
Full-duplex communication
Double-buffered transmission and triple-buffered reception, allowing a continuous data stream
Independent clocking and framing for reception and transmission
The capability to send interrupts to the CPU and to send DMA events to the DMA controller
128 channels for transmission and reception
Multichannel selection modes that enable or disable block transfers in each of the channels
Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially
connected A/D and D/A devices
•
•
Support for external generation of clock signals and frame-synchronization signals
A programmable sample rate generator for internal generation and control of clock signals and frame
synchronization signals
•
•
Programmable polarity for frame-synchronization pulses and clock signals
Direct interface to:
–
–
–
–
–
T1/E1 framers
IOM-2 compliant devices
AC97-compliant devices (the necessary multi-phase frame capability is provided)
I2S compliant devices
SPI devices
•
A wide selection of data sizes: 8, 12, 16, 20, 24, and 32 bits
NOTE
A value of the chosen data size is referred to as a serial word or word in this section.
Elsewhere, word is used to describe a 16-bit value.
•
•
•
•
µ-law and A-law companding
The option of transmitting/receiving 8-bit data with the LSB first
Status bits for flagging exception/error conditions
ABIS mode is not supported
Figure 6-22 shows the C28x McBSP peripheral.
Copyright © 2011–2012, Texas Instruments Incorporated
Peripheral Information and Timings
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
MASTER
MCBSP
SUBSYSTEM
MCR2 REG
MCR1 REG
XCERA REG
XCERB REG
XCERC REG
XCERD REG
XCERE REG
XCERF REG
XCERG REG
XCERH REG
RCERA REG
RCERB REG
RCERC REG
RCERD REG
RCERE REG
RCERF REG
RCERG REG
RCERH REG
C28CLKIN
MULTI -
CHANNEL
SELECTION
(128 CHAN)
C28SYSCLK
REG
ACCESS
MCBSPA_ENCLK
/1
/2
SYSTEM
CONTROL
REGISTERS
/4
C28LSPCLK
PERIPH
LOGIC
…
/14
MCLKXA
MFSXA
MDXA
SPCR2 REG
XCR2 REG
SPCR2 REG
SRGR2 REG
SPCR1 REG
XCR1 REG
SPCR1 REG
SRGR1 REG
PIN
PIN
PIN
C28x
CPU
ALL REG
ACCESS
GENERATION AND CONTROL
OF CLOCK AND FRAME SYNC
INTR
PCR REG
C28x PIE
MCLKRA
MFSRA
MDRA
MXINTA
MRINTA
RX/TX
INTERRUPT
LOGIC
MFFINT REG
PIN
PIN
PIN
COMPRESS
EXPAND
DXR2 REG
DRR1 REG
DXR1 REG
DRR2 REG
XSR REG
RSR REG
C28
DMA
DRR / DXR
RBR REG
REG ACCESS
Figure 6-22. McBSP (C28x)
184
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
www.ti.com
SPRS742D –JUNE 2011–REVISED AUGUST 2012
7 Device and Documentation Support
7.1 Device Support
7.1.1 Development Support
TI offers an extensive line of development tools, including tools to evaluate the performance of the
processors, generate code, develop algorithm implementations, and fully integrate and debug software
and hardware modules. The tool's support documentation is electronically available within the Code
Composer Studio™ Integrated Development Environment (IDE).
The following products support development of processor applications:
Software Development Tools: Code Composer Studio™ Integrated Development Environment (IDE):
including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (SYS/BIOS), which provides the basic run-time target software
needed to support any processor application.
Hardware Development Tools: Extended Development System ( XDS™) Emulator
For a complete listing of development-support tools for the processor platform, visit the Texas Instruments
website at www.ti.com. For information on pricing and availability, contact the nearest TI field sales office
or authorized distributor.
7.1.2 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
Concerto™ MCU devices and support tools. Each Concerto™ MCU commercial family member has one
of three prefixes: x, p, or no prefix (for example, xF28M35H52C1RFPT). Texas Instruments recommends
two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent
evolutionary stages of product development from engineering prototypes (with prefix x for devices and
TMDX for tools) through fully qualified production devices/tools (with no prefix for devices and TMDS,
instead of TMDX, for tools).
xF28M35...
pF28M35...
F28M35...
Experimental device that is not necessarily representative of the final device's
electrical specifications
Final silicon die that conforms to the device's electrical specifications but has
not completed quality and reliability verification
Fully qualified production device
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal
qualification testing
TMDS Fully qualified development-support product
Devices with prefix x or p and TMDX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality
and reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices with prefix of x or p have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.
Copyright © 2011–2012, Texas Instruments Incorporated
Device and Documentation Support
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
SPRS742D –JUNE 2011–REVISED AUGUST 2012
www.ti.com
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, RFP) and temperature range (for example, T).
For device part numbers and further ordering information of F28M35x devices in the RFP package type,
see the TI website (www.ti.com) or contact your TI sales representative.
For additional description of the device nomenclature markings on the die, see the F28M35H20B1,
F28M35H20C1, F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1, F28M35H50B1,
F28M35H50C1, F28M35H52B1, F28M35H52C1 Concerto MCU Silicon Errata (literature number
SPRZ357).
x
F28M3
5
H
5
2
C
1
RFP
T
PREFIX
TEMPERATURE RANGE
=
=
=
experimental device
prototype device
qualified device
−40°C to 105°C
−40°C to 125°C
−40°C to 125°C
(Q refers to Q100 qualification
for automotive applications.)
x
p
T
S
Q
=
=
=
no prefix
DEVICE FAMILY
F28M3 = ConcertoTM
PACKAGE TYPE
144-Pin RFP PowerPADTM
Thermally Enhanced Thin Quad Flatpack (HTQFP)
SERIES NUMBER
PINS
1 = 144 pins
PERFORMANCE
(C28xTM Speed / CortexTM-M3 Speed)
=
=
=
H
M
E
150 / 75 MHz or 100 / 100 MHz
75 / 75 MHz
60 / 60 MHz
PERIPHERALS
=
=
Connectivity
Base
C
B
FLASH
2 = 256KB each core
3 = additional 256KB to one core(A)
5 = 512KB each core
RAM
=
=
0
2
72KB
additional 64KB of masterable RAM
A. The additional 256KB is added to the Cortex™-M3 core (Connectivity Devices) or to the C28x™ core (Base Devices).
Figure 7-1. Device Nomenclature
7.2 Documentation Support
The following documents describe the MCU. Copies of these documents are available on the Internet at
www.ti.com. Tip: Enter the literature number in the search box.
SPRUH22 Concerto F28M35x Technical Reference Manual
SPRZ357
F28M35H20B1,
F28M35H20C1,
F28M35H22B1,
F28M35H22C1,
F28M35H32B1,
F28M35H32C1, F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 Concerto
MCU Silicon Errata
7.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and
help solve problems with fellow engineers.
TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help
developers get started with Embedded Processors from Texas Instruments and to foster
innovation and growth of general knowledge about the hardware and software surrounding
these devices.
186
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F28M35H20B1, F28M35H20C1
F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1
F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1
www.ti.com
SPRS742D –JUNE 2011–REVISED AUGUST 2012
8 Mechanical Packaging and Orderable Information
8.1 Thermal Data for Package
Table 8-1 shows the thermal data. See Section 5.2 for more information on thermal design considerations.
Table 8-1. Thermal Model 144-Pin RFP Results
AIR FLOW
PARAMETER
0 lfm
18.8
0.3
150 lfm
11.5
0.2
250 lfm
10.0
0.3
500 lfm
8.6
θJA [°C/W] High k PCB
ΨJT [°C/W]
ΨJB
0.3
4.8
4.6
4.5
4.4
θJC
6.3
θJB
4.4
8.2 Packaging Information
The following packaging information and addendum reflect the most current data available for the
designated devices. This data is subject to change without notice and without revision of this document.
Copyright © 2011–2012, Texas Instruments Incorporated
Mechanical Packaging and Orderable Information
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PACKAGE OPTION ADDENDUM
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20-Jun-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
F28M35H20B1RFPQ
F28M35H20B1RFPS
F28M35H20B1RFPT
F28M35H20C1RFPQ
F28M35H20C1RFPS
F28M35H20C1RFPT
F28M35H22B1RFPQ
F28M35H22B1RFPS
F28M35H22B1RFPT
F28M35H22C1RFPQ
F28M35H22C1RFPS
F28M35H22C1RFPT
F28M35H32B1RFPQ
F28M35H32B1RFPS
F28M35H32B1RFPT
F28M35H32C1RFPQ
F28M35H32C1RFPS
F28M35H32C1RFPT
F28M35H50B1RFPQ
F28M35H50B1RFPS
F28M35H50B1RFPT
F28M35H50C1RFPQ
F28M35H50C1RFPS
F28M35H50C1RFPT
F28M35H52B1RFPQ
F28M35H52B1RFPS
F28M35H52B1RFPT
F28M35H52C1RFPQ
F28M35H52C1RFPS
F28M35H52C1RFPT
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
RFP
RFP
RFP
RFP
RFP
RFP
RFP
RFP
RFP
RFP
RFP
RFP
RFP
RFP
RFP
RFP
RFP
RFP
RFP
RFP
RFP
RFP
RFP
RFP
RFP
RFP
RFP
RFP
RFP
RFP
144
144
144
144
144
144
144
144
144
144
144
144
144
144
144
144
144
144
144
144
144
144
144
144
144
144
144
144
144
144
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
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Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
20-Jun-2012
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
XF28M35H52C1RFPT
ACTIVE
HTQFP
RFP
144
1
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(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE
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