GC6016IZEV_技术文档

GC6016

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SLWS227A –NOVEMBER 2010–REVISED MARCH 2011

Wideband Transmit-Receive Digital Signal Processors

Check for Samples: GC6016

1

FEATURES

APPLICATIONS

•

Multi-Standard Base Stations

3GPP (LTE, W-CDMA, TDS-CDMA)

MC-GSM

WiMAX and WiBro (OFDMA)

Multi-Carrier Power Amplifiers (MCPAs)

Wireless Infrastructure Repeaters

•

Integrated Transmit and Receive Digital IF

Solution

•

Up to 4 TX, 8 RX

TX-Transmit Includes DUC, CFR, TX Equalizer,

and Bulk Upconverter

•

CFR: 6-dB PAR for WCDMA, 7-db LTE Signals

With EVM Meeting 3GPP Specs; Configurable

for All Major Wireless Infrastructure Standards

Digital Radio Instrumentation and Test

Equipment

DESCRIPTION

RX-Receive Includes DC-Offset Cancellation,

Front-End and Back-End AGC, Bulk

Downconverter, RX Equalizer, I/Q Imbalance

Correction, DDC

The GC6016 is a wideband transmit and receive

signal processor that includes digital downconverter /

upconverter (DDUC), transmit, receive, and capture

buffer blocks. The transmit path includes crest factor

reduction (CFR), complex equalization, and bulk

upconversion.

•

4 DDUCs, 1–12 Channels per DDUC, Each

DDUC Can Be Programmed to TX or RX, at a

Common Resampler Rate – Multimode

Support

The GC6016 is a related product to the GC5330, with

the DPD block not functional. The GC6016 has an

identical package and footprint with the GC5330.The

receive path includes wideband and narrowband

automatic gain control (AGC), bulk downconversion,

complex equalization, and I/Q imbalance correction.

•

Seamless Interface to TI High-Speed Data

Converters

4 TX Aggregate Output to DACs up to

930 MSPS Complex

The DDUC section consists of four identical DDUC

blocks, each supporting up to 12 channels. Each

channel has independent fractional resamplers and

NCOs to enable flexible carrier configurations.

Multi-mode/multi-standard

supported by configuring the individual DDUC blocks

to different filtering and oversampling scenarios.

8 RX Aggregate Input From ADCs up to

1.24 GSPS Real

•

16-Tap (Complex) RX Equalizers

Two 4K Complex Word Capture Buffers for

Signal Analysis, and Adaptive Filtering

operation

can

be

•

1.1-V Core, 3.3-V I/O CMOS, 1.8-V I/O LVDS

Power Consumption, 3.5 W Typical

DAC3484

TRF3703/3720

I/Q Mod

C6748

DSP

Complex

TX

PA

484-Ball TE-PBGA Package, 23 mm × 23 mm

DAC

I/Q

I/Q Mod

DAC

I/Q

FB

ADS61B49

ADC

Subsampled

Feedback

SW

Mixer/BPF

Baseband

Data

GC6016

DUC-CFR

DDC

ADS62P49

ADC

RX

Mixer/BPF

LNA

Real

RX

ADC

LNA

ADS62P49

ADC

RX

Mixer/BPF

LNA

Real

RX

ADC

B0441-02

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

GC6016

SLWS227A –NOVEMBER 2010–REVISED MARCH 2011

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

DESCRIPTION (Continued)

The CFR block reduces the peak-to-average ratio (PAR) of the digital transmit signals, such as those used in

third-generation (3G) code division multiple access (CDMA) and orthogonal frequency-division multiple-access

(OFDMA) applications.

By reducing the PAR of the digital signal and the PA nonlinearity, the operational efficiency of follow-on power

amplifiers can be substantially improved.

In Table 1, feedback is normally associated with a DPD system. The GC6016 can use the feedback input as a

calibration antenna input to the capture buffer. Several architectures that provide performance and cost

optimization are listed in Table 1

Table 1. Sample Configurations for GC6016

Figure

TX Antenna

RX Antenna

Other

2 typical at 250 Msps, up to 4 at

250 Msps

Figure 1

2-62 MHz

Lower-cost 2-antenna solution

2 at 250Msps, 4 with lower-rate

RX ADC

Figure 2

Figure 3

Figure 4

2-62 MHz

4-31 MHz

2-antenna solution with full-rate real feedback

2 at 250Msps, 4 with lower-rate

RX ADC

2-antenna solution with complex feedback, lower

subsampling ratio

4 at 250Msps, 8 with lower-rate

RX ADC

Lower-cost 4 antenna solution

ANTENNA MODE EXAMPLE DIAGRAMS

C6748

DSP

DAC3283/3482

TRF3703/3720

Complex

TX

I/Q

I/Q Mod

DAC

PA

I/Q Mod

Baseband

Data

ADS41B49

ADC

FB

GC6016

DUC-CFR

DDC

Subsampled

Feedback

Mixer/BPF

SW

ADS62P49

ADC

RX

Mixer/BPF

LNA

Real

RX

ADC

LNA

B0442-02

Figure 1. Two-Antenna-Mode Subsampled-Feedback Diagram

2

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C6748

DSP

DAC3283/3482

DAC

TRF3703/3720

Complex

TX

I/Q

I/Q Mod

PA

I/Q Mod

DAC

Baseband

Data

ADS5474

ADC

RX

GC6016

DUC-CFR

DDC

Real

Feedback

Mixer/BPF

SW

ADS62P49

ADC

RX

Mixer/BPF

LNA

Real

RX

ADC

LNA

B0443-02

Figure 2. Two-Antenna-Mode Full-Rate Real-Feedback Diagram

C6748

DSP

DAC3283/3482

DAC

TRF3703/3720

I/Q Mod

Complex

TX

I/Q

PA

I/Q Mod

DAC

ADS62P49

ADC

RX

Baseband

Data

Complex

Feedback

I/Q Demod

SW

GC6016

DUC-CFR

DDC

ADC

ADS62P49

ADC

RX

Mixer/BPF

LNA

Real

RX

ADC

LNA

B0435-02

Figure 3. Two-Antenna-Mode Complex-Feedback Diagram

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DAC3484

DAC

TRF3703/3720

I/Q Mod

C6748

DSP

Complex

TX

PA

I/Q

I/Q Mod

DAC

I/Q

FB

ADS61B49

ADC

Subsampled

Feedback

SW

Mixer/BPF

Baseband

Data

GC6016

DUC-CFR

DDC

ADS62P49

ADC

RX

Mixer/BPF

LNA

Real

RX

ADC

LNA

ADS62P49

ADC

RX

Mixer/BPF

LNA

Real

RX

ADC

B0441-02

Figure 4. Four-Antenna-Mode Subsampled Real-Feedback Example Diagram

GENERAL DESCRIPTION

The GC6016 is

a

wideband transmit and receive signal processor that includes digital

downconverter/upconverter (DDUC), transmit, receive, and capture buffer blocks. The transmit path includes

crest factor reduction (CFR), complex equalization, and bulk upconversion. The receive path includes wideband

and narrowband automatic gain control (AGC), bulk downconversion, complex equalization, and I/Q imbalance

correction.

The architecture supports different RX, TX, and feedback modes of operation. This provides for many

configurations to optimize performance and cost.

•

RX – real or complex input

TX – real, complex, complex with envelope tracking

The RX path can be configured for one or two multichannel ADC input ports. The RX block provides each ADC

channel with a front-end AGC, IQ demodulation correction, real-to-complex conversion, complex mixing,

decimation, and complex equalization. The RX block output is input to the DDUC block. The output of the DDUC

block goes through gain and back-end AGC and is formatted for the baseband output.

4

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There are four DDUC blocks. Each can be used for the RX DDC downconversion or TX DUC upconversion, one

at a time. The DDUC has a complex mixer, cascade integrator comb filter, resampler, and a programmable FIR

filter. Each DDUC can support 1 to 12 channels.

The TX path can be configured for one, two, or four antenna streams. In addition, with one or two antenna

streams, an envelope modulator output is available. The DAC and envelope modulator share the same output

ports. The TX input is from the baseband input, through the DDUC to create complex antenna streams. The CFR

block provides for gain adjustment, peak reduction, and peak limiting. Additional interpolation stages after CFR

expand the antenna stream bandwidth.

Specialized capture logic collects the RX input, feedback input, RX output, CFR output, and DPD output for the

DSP processor to support built-in test. The capture logic can also be used for performance monitoring and power

measurement.

AVAILABLE OPTIONS

PART NUMBER

T_C

PACKAGE

THERMAL PROPERTIES

GC6016IZEV

–40°C to 85°C

484 ball 23-mm × 23-mm PBGA

Heat transfer through package top

GC6016

40 LVDS (1.8V)

TX

1–2 Streams

1–12 Channel DDUC Block

(config as TX or RX, showing TX)

ET

NCO

X

Baseband

Interface

TX

Format

and

DAC

Interface

24 LVDS (1.8V)

40 LVDS (1.8V)

Mux

and

Sum

(TX)

or

TX

IF

Mux

and

Sum

FIR

TX

Eq

X

Farrow

1–1024´

CIC

1–3´

UC

1/2´

24 LVDS (1.8V)

1´,

2´

CFR

BUC

Power

Meter,

per

1–4 TX Streams

Up to 8 DACs

(2 40-Pin Ports)

IF NCO

2´

Dist

(RX)

Channel

Includes

interp

40% BW,

90 dB stop

1/2/3/4´

80% BW,

90 dB stop;

90% BW,

80 dB stop

before or

after CFR,

80% BW,

90 dB stop

beAGC

(RX

Only)

per

Channel

DVGA

Format/

GPIO

16 CMOS (3.3V)

Capture Buffer A

Capture Buffer B

ADC

inter-

face

(port

AB)

TX

Interval Based Power Meter

Running Avg Power Meter

60 LVDS (1.8V)

Complex

Gain per

Channel

RX 1/2/4 Streams

Up to 8 ADCs

(2 30-Pin Ports)

Eq

(16

I/Q

Imbal

DC

Offset

Cancel

IF

NCO

fe-

AGC

BDC

Switch

R2C

ADC

inter-

face

Taps)

Correction

16 LVDS (1.8V)

1/2/4/8/16´

1 ADC

(1 16-Pin Port)

(port C)

When I/Q correction

enabled, IF NCO is disabled

2 LVDS

4 LVDS

2 LVDS

DPD clk

High-

Sync A, B in

Sync out

Speed

Sync,

Clocks

Control and Sync CMOS (3.3 V)

JTAG CMOS (3.3 V)

LVDS

showing

the number

of pins;

16

8

4

2

4

each signal

is a diff. pair

uP data uP addr uP ctrl

INT

TESTMOD, SPI en, SPIDIO SPIDO

RESET

SPI clk (SPARE)

JTAG

B0445-02

NOTE: UC1 and UC2 are for CFR interpolation; UC2 can only be used if UC1 is also used.

Figure 5. GC6016 Block Diagram

GC6016 Introduction

The GC6016 is a flexible transmit and receive digital signal processor that includes receiver and transmitter

blocks, digital downconverter / upconverter (DDUC) blocks, crest factor reduction (CFR) engine, flexible LVDS

data converter and baseband interfaces, and capture buffers for adaptive filtering algorithms.

Each of the four DDUC blocks can be configured as either a digital downconverter (DDC) or a digital upconverter

(DUC). Typically, a system can be implemented as both TX and RX, with both DDC and DUC functions. The

DDUC blocks provide programmable FIR filters with flexible numbers of taps, depending on signal bandwidth and

number of channels, as well as fractional resamplers, CIC filters, and complex mixers. The DDUC complex

mixers support static or hopping tuning functions.

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beAGC after the DDC is part of the baseband interface. Static gain is applied in the BB block for both the DDC

output and DUC input.

The receiver block provides dc offset correction, front-end AGC, real-to-complex conversion, complex mixing,

decimating filters, a complex equalizer, and a blind RX IQ imbalance correction function.

The CFR block reduces the peak-to-average ratio (PAR) of complex, arbitrary TX signals. Reducing the PAR of

the TX signal allows wireless-infrastructure (WI) base stations and repeaters to use smaller and lower-cost

multi-carrier power amplifiers (MCPAs).

In WI applications, the GC6016 meets multi-carrier 3G and 4G performance standards (PCDE, composite EVM,

and ACLR) at PAR levels down to 6 dB for WCDMA and 7 dB for LTE. The GC6016 integrates easily into the

transmit/receive signal chain between Texas Instruments’ high-performance data converters and baseband

processors such as the TI TMS320C64xx family. In wireless repeater applications, the GC6016 can provide

seamless interfaces to TI data converters, along with receive and transmit filtering, DDC, and DUC functions.

The GC6016 is extremely flexible and can be used in system architectures with different signal types and

TX-by-RX antenna configurations such as 2×2, 2×4, 4×4, and 4×8.

The GC6016 EVM system provides an example sector transmit-receive signal chain solution, from the

multi-carrier baseband to the RF antenna.

ABSOLUTE MAXIMUM RATINGS

over recommended operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

–0.5

–20

MAX UNIT

V_DD

Core supply voltage

1.32

V

V_DDA

V_DDS

V_DDSHV

V_IN

PLL analog voltage

2

Digital supply voltage for TX

Digital supply voltage

2

V

3.6

V_DDSHV+ 0.5

20

V

Input voltage (under/overshoot)

Clamp current for an input/output

Storage temperature

V

mA

°C

T_stg

–65

140

ESD classification

Moisture sensitivity

Class 2 (2.5 kV HBM, 500 V CDM, 150 V MM)

Moisture sensitivity Class 3 (1 week floor life at 30°C / 60% H)

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6

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RECOMMENDED OPERATING CONDITIONS

MIN

1.05

1.71

3.15

–40

TYP MAX UNIT

(1)(2)(3)

V_DD

Core supply voltage

310 MHz, 5.7 A max.

60 mA max. (each)⁽¹⁾

700 mA max.⁽¹⁾

1.1 1.15

1.8 1.89

3.3 3.45

V

V_DDA

V_DDS

Analog supply for PLLs

Digital supply voltage for LVDS I/O

V

V_DDSHVDigital supply voltage CMOS I/O

PC board design dependent

V

T_C

T_J

Case temperature

30

90

°C

(4)

Junction temperature

See

105

(1) Chip specifications are production tested to 90°C case temperature. QA tests are performed at 85°C.

(2) Production tested hot using checksum at 310 MHz and maximum supplies. Power scales linearly with frequency with a dc consumption

around 350 mA typical, 700 mA worst case.

(3) Power consumption is a strong function of the configuration. A calculator is available to estimate power for a specific configuration.

(4) Reliability calculations presume junction temperature 105°C or below. Operation above 105°C junction temperature reduces product

lifetime.

THERMAL INFORMATION

GC6016

THERMAL METRIC

ZEV

484 PINS

15.4

2.1

UNIT

θ_JA

Junction-to-ambient thermal resistance⁽¹⁾

Junction-to-case (top) thermal resistance⁽²⁾

Junction-to-board thermal resistance⁽³⁾

Junction-to-top characterization parameter⁽⁴⁾

Junction-to-board characterization parameter⁽⁵⁾

Junction-to-case (bottom) thermal resistance⁽⁶⁾

°C/W

θ_JCtop

θ_JB

7.6

ψ_JT

0.5

ψ_JB

7.5

θ_JCbot

N/A

(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific

JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(4) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(5) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

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Pin Assignment and Descriptions (Top View)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

SYNC

OUTN

SYNC

OUTP

A

B

C

D

E

F

NC

BBIN5P BBIN4P BBIN3P BBIN1P SPIDENB SPICLK

CEB

UPA5

UPA2

UPD15 UPD12 UPD8

UPD5

UPD1 VSSA2 SYNCBN

TXA1N TXA2P

NC

A

B

C

D

E

BBIN7N BBIN7P BBIN5N BBIN4N BBIN3N BBIN1N SPIDIO INTERRPT UPA6

BBIN8N BBIN8P BBIN6P BBIN6N VSSA1 BBIN2P BBIN0P EMIFENA UPA7

UPA3

UPA4

VSS

WEB

UPA0

UPA1

VDD

UPD13 UPD9

UPD6

UPD2

UPD0 VDDA2 SYNCBP TXA0N TXA1P TXA2N TXA5N

UPD14 UPD10 UPD7

UPD3 SYNCAPDPDCLKP TXA0P TXA3P TXA4P TXA4N TXA5P

NC

BBIN9N BBIN9P

NC

VDDA1 BBIN2N BBIN0N

VSS

VDD

OEB

VDD

VSS

VDD

UPD11

VDD

VSS

VDD

UPD4 SYNCAN DPDCLKN TXA3N TXA6N TXA7N TXA8N TXA9P

BBOUT0P BBIN10P BBIN10N BBIN11P BBIN11N VDD

VDD

VDDS1

VSS

NC

TXA6P TXA7P TXA8P TXA9N

TXA11N TXA11P TXA10N TXA10P

BBOUT0N BBOUT2N BBOUT2P BBOUT1N BBOUT1P

BBOUT4N BBOUT4P BBOUT3N BBOUT3P VDDS2

BBOUT6N BBOUT6P BBOUT5N BBOUT5P VDD

BBOUT8N BBOUT8P BBOUT7N BBOUT7P VDD

BBOUT10NBBOUT10P BBOUT9N BBOUT9P VDDS2

NC

VDDS2 VDDSHV1 VDD VDDSHV1 VDD VDDSHV1 VDD VDDSHV1 VDD

VDD

F

G

H

J

VSS

VDDS2

VDD

VSS

VDD

TMS

TDI

VSS

NC

VDD TXA13P TXA13N TXA12P TXA12N

VDDS1 TXA15P TXA15N TXA14N TXA14P

VDD TXA17P TXA17N TXA16N TXA16P

VDDS1 TXA19N TXA19P TXA18N TXA18P

G

H

J

VSS

K

L

VSS

K

L

RXA13P RXA14N RXA14P BBOUT11P BBOUT11N VSS

VSS

VDD

TXB1P TXB1N TXB0P TXB0N

M

N

P

R

T

RXA13N RXA12P RXA11N RXA11P VDDS2

VSS

NC

VSS

VDDS1 TXB3P TXB3N TXB2P TXB2N

M

N

P

RXA12N RXA10P RXA9N RXA9P

VDD

VSS

VDD

TXB5P TXB5N TXB4P TXB4N

TXB7P TXB7N TXB6P TXB6N

RXA10N RXA8N RXA8P RXA7N RXA7P

VSS

RXA6N RXA6P RXA5N RXA5P

VDD

VSS

VDDS1 TXB9P TXB9N TXB8P TXB8N

R

T

RXA4N RXA3N RXA3P RXA2N RXA2P

VSS

VDD

TXB11P TXB11N TXB10P TXB10N

U

V

W

Y

RXA4P RXA1P RXA0N RXA0P

RXA1N RXB14N RXB10N RXB10P

VDD

NC

VDD VDDSHV2 VDD VDDSHV2 VDD VDDSHV2 VDD

VDDS1

VDD

VDD TXB13P TXB13N TXB12P TXB12N

U

V

NC

VDD

VPP

VDD

VSS

VDD

VPP

VDD

VSS

VDD

VSS

VDD

TDO

NC

TXB15P TXB15N TXB14N TXB14P

TXB17P TXB17N TXB16P TXB16N

RXB14P RXB13P

NC

RXB6P RXB6N RXB4P RXB2P

DVGA6

RXC6N RXC4N

W

Y

RXB13N RXB12N RXB8N RXB8P RXB5P RXB4N RXB2N VDDMON RESETB DVGA13 DVGA10 DVGA7 DVGA3 DVGA0

RXC6P RXC5N RXC4P TXB19N TXB19P TXB18N TXB18P

SPIDO

(SPARE)

AA RXB12P RXB11P RXB9P RXB7N RXB5N RXB3P RXB1N VSSMON

DVGA14 DVGA11 DVGA8 DVGA4 DVGA1 TRSTB RXC7N RXC5P RXC3P RXC2N RXC2P RXC0N

NC

AA

AB

NC

RXB11N RXB9N RXB7P

NC

RXB3N RXB1P RXB0P RXB0N TESTMOD DVGA15 DVGA12 DVGA9 DVGA5 DVGA2

TCK

RXC7P RXC3N RXC1N RXC1P RXC0P

NC

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

= 1.1 V

= 1.8 V, 3.3 V

= GND

P0131-01

Figure 6. GC6016 Pinout (Top View)

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Pin Functions

NAME

NUMBER

TYPE

DESCRIPTION

POWER AND BIASING

VDD

E6, E7, E8, E9, E10, E11, E12, E13, E14, E15, E16, F9,

F11, F13, F15, F18, G18, H5, J5, J18, L18, N5, N18, P18,

R5, T18, U5, U8, U10, U12, U14, U15, U18, V7, V8, V9,

V10, V11, V12, V13, V14, V15, V16

PWR 1.1-V power supply

VDDSHV2

VDDSHV1

VDDS1

VDDS2

VPP

U9, U11, U13

PWR 3.3-V power supply for CMOS I/O

PWR 1.8-V power supply for LVDS I/O

PWR 1.1-V E-fuse supply, connect to VDD

F8, F10, F12, F14

F16, H18, K18, M18, R18, U16,

F7, G5, K5, M5, U7

W8, W10

Y8

VDDMON

VSSMON

VDDA2

VDDA1

VSSA2

VSSA1

VSS

NC

Do not connect, internal monitor point

AA8

B17

D5

PWR 1.8-V power for PLL (requires filtering)

PWR Ground for PLL (requires filtering)

PWR Ground

A16

C5

D8, D10, D12, D14, G6, G7. G8, G9, G10, G11, G12, G13,

G14, G15, G16, G17, H6, H7, H8, H9, H10, H11, H12, H13,

H14, H15, H16, H17, J6, J7, J8, J9,J10, J11, J12, J13, J14,

J15, J16, J17, K6, K7, K8, K9, K10, K11, K12, K13, K14,

K15, K16, K17, L6, L7, L8, L9, L10, L11, L12, L13, L14,

L15, L16, L17, M6, M7, M8, M9, M10, M11, M12, M13, M14,

M15, M16, M17, N6, N7, N8, N9, N10, N11, N12, N13, N14,

N15, N16, N17, P6, P7, P8, P9, P10, P11, P12, P13, P14,

P15, P16, P17, R6, R7, R8, R9, R10, R11, R12, R13, R14,

R15, R16, R17, T6, T7, T8, T9, T10, T11, T12, T13, T14,

T15, T16, T17,W9, W11, W13

NC

E17, E18, F6, F17, U6, U17, V5, V6, V17, V18

NC

No connection. Recommend connecting to ground

No connection

A1, A22, D1, D4, W3, W18, AA22, AB1, AB5, AB22,

BASEBAND INPUT/OUTPUT

BBIN[11:0]P

E4, E2, D3, C2, B2, C3, A2, A3, A4, C6, A5, C7

I

Baseband input – LVDS positive

Baseband input – LVDS negative

Baseband output – LVDS positive

Baseband output – LVDS negative

BBIN[11:0]N

BBOUT[11:0]P

BBOUT[11:0]N

E5, E3, D2, C1, B1, C4, B3, B4, B5, D6, B6, D7

L4, K2, K4, J2, J4, H2, H4, G2, G4, F3, F5, E1

L5, K1, K3, J1, J3, H1, H3, G1, G3, F2, F4, F1

I

O

TX DAC INTERFACE

TXA[19:0]P

TXA[19:0]N

TXB[19:0]P

TXB[19:0]N

K20, K22, J19, J22, H19, H22, G19, G21, F20, F22, D22,

E21, E20, E19, C22, C20, C19, A21, B20, C18

O

DAC TX port A – LVDS positive

DAC TX port A – LVDS negative

DAC TX port B – LVDS positive

DAC TX port B – LVDS negative

K19, K21, J20, J21, H20, H21, G20, G22, F19, F21, E22,

D21, D20, D19, B22, C21, D18, B21, A20, B19

Y20, Y22, W19, W21, V19, V22, U19, U21, T19, T21, R19,

R21, P19, P21, N19, N21, M19, M21, L19, L21

Y19, Y21, W20, W22, V20, V21, U20, U22, T20, T22, R20,

R22, P20, P22, N20, N22, M20, M22, L20, L22

RX and FB ADC INTERFACE

RXA[14:0]P

RXA[14:0]N

RXB[14:0]P

L3, L1, M2, M4, N2, N4, P3, P5, R2, R4, U1, T3, T5, U2, U4

I

ADC receive port A – LVDS positive

ADC receive port A – LVDS negative

ADC receive port B – LVDS positive

L2, M1, N1, M3, P1, N3, P2, P4, R1, R3, T1, T2, T4, V1, U3

W1, W2, AA1, AA2, V4, AA3, Y4, AB4, W4, Y5, W6, AA6,

W7, AB7, AB8

RXB[14:0]N

V2, Y1, Y2, AB2, V3, AB3, Y3, AA4, W5, AA5, Y6, AB6, Y7,

AA7, AB9

I

ADC receive port B – LVDS negative

RXC[7:0]P

RXC[7:0]N

AB17, Y16, AA17, Y18, AA18, AA20, AB20, AB21

AA16, W16, Y17, W17, AB18, AA19, AB19, AA21

I

ADC receive port C – LVDS positive

ADC receive port C – LVDS negative

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Pin Functions (continued)

NAME

NUMBER

TYPE

DESCRIPTION

DVGA INTERFACE

DVGA[15:0]

AB11, AA10, Y10, AB12, AA11, Y11, AB13, AA12, Y12,

W12, AB14, AA13, Y13, AB15, AA14, Y14

O

MPU INTERFACE

UPD[15:0]

A11, C12, B12, A12, D13, C13, B13, A13, C14, B14, A14,

D15, C15, B15, A15, B16

I/O

UPA[7:0]

WEB

C9, B9, A9, C10, B10, A10, D11, C11

I

B11

C8

Write enable, active-low

EMIFENA

EMIFENA switches between address/data µP

access and SPI access. Its value may be changed

at any time, but both address/data access and SPI

access must be idle during the change. Logic 1 =

EMIF, logic 0 = SPI pin has internal pullup.

OEB

CEB

D9

A8

I

Read and output enable, active-low

Chip enable, active-low

JTAG INTERFACE

TRSTB

AA15

I

JTAG reset (active-low); pull down if JTAG is not

used.

TMS

W15

W14

Y15

I

O

I

JTAG mode select

JTAG data out

JTAG data in

JTAG clock

TDO

TDI

TCK

AB16

I

SPI INTERFACE

SPIDENB

SPICLK

SPIDIO

A6

A7

B7

I

Serial interface enable

Serial interface clock

I/O

O

Serial interface data

SPIDO(SPARE) AA9

Serial interface data out in four-wire SPI mode

MISCELLANEOUS

TESTMOD

RESETB

AB10

Y9

I

Test mode for GC6016, typically grounded

Chip reset – required – active-low

Output interrupt

INTERRPT

DPDCLKP

DPDCLKN

SYNCOUTP

SYNCOUTN

SYNCAP

B8

O

I

C17

D17

A19

A18

C16

D16

B18

A17

DPD CLK input – LVDS positive

DPD CLK input – LVDS negative

Sync output – LVDS positive

Sync output – LVDS negative

Sync input A – LVDS positive

Sync input A – LVDS negative

Sync input B – LVDS positive

Sync input B – LVDS negative

I

O

I

SYNCAN

I

SYNCBP

I

SYNCBN

I

Ferrite Bead

50 Ω

R = 0 Ω

1.8V

GND

VDDA1 or VDDA2

C = 0.01 μF

C = 0.1 μF

50 Ω

VSSA1 or VSSA2

Ferrite Bead

S0510-01

NOTE: 0-Ω R0603 resistor is used to accommodate series resistor if needed.

Figure 7. GC6016 PLL Filtering

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The two GC6016 PLLs require a filtered power supply. The supply can be generated by filtering the digital supply

(VDDS1, VSSA1, VDDS2, and VSSA2). A representative filter is shown in Figure 7. The two PLLs should have

separate filters that are located as close as is reasonable to their respective pins (especially the bypass

capacitors). The ferrite beads should be series 50R (similar to Murata P/N: BLM31P500SPT, Description: IND FB

BLM31P500SPT 50R 1206).

Sub-Chip Descriptions

Figure 8 shows the TX functional block diagram, and Figure 9 shows the RX functional block diagram. Note that

each figure shows up to four DUC or DDC blocks in the TX or RX paths, and there are a total of four DDUC

blocks that may be configured as either DUC or DDC each.

TX Block

1–12 Channel DUC Block

NCO

1–2 Streams

FIR

1´, 2´

Farrow

1–1024´

CIC

1–3´

X

UC

1/2´

UC

1/2/4´

Mux

and

CFR

TxEQ

IF

NCO

IF

Sum

TX BB

BUC

1 to 4 TX

Streams

Sum

80% BW,

90 dBstop

40% BW, Includes

90 dBstop 16-tap Eq

1/2/3/4´

80% BW,

90 dBstop;

90% BW,

80% dB stop

B0446-02

Figure 8. TX Functional Block Diagram

RX Block

1–12 Channel DDC Block

1/2/4 Streams

NCO

1 to 9

ADC

Inputs

X

RX

Equalizer

16 Taps

I/Q

Imbalance

Correction

BDC

FIR

1´, 2x

Farrow

1–1024´

CIC

1–3´

X

R2C;

Format;

feAGC;

DC Offset

Correction

IF

Mux

RX BB

IF NCO

X

Mux

1/2/4/8/16´

When I/Q

correction

enabled,

IF NCO

DVGA Outputs

B0447-01

is disabled

IF NCO

Figure 9. RX Functional Block Diagram

TX Baseband Input Formatter

The TX baseband (BB) input-formatter block accepts TX baseband inputs from the FPGA or baseband processor

and formats them for the DUC blocks. There are 12 unidirectional LVDS pairs for the TX input formatter, and

their function depends on the operational mode. There are three operational modes for the TX BB input

formatter: byte mode (B, 8 or 9 bits), nibble mode (N, 4 bits), and serial mode (S, 2 bits) to allow multiple BB

input rates. The GC6016 can accept up to three different BB input data rates. Table 2 and Table 3 summarize

each mode and the pin assignments. In Table 3, BBIN[X] is the BBIN differential pair (assumed positive and

negative connections), and BB0, BB1, and BB2 represent three different TX baseband ports at arbitrary rates.

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Table 2. TX BB Formatter Modes

Maximum Complex Interface Rate per Channel

N is the number of channels.

MODE

1B

DESCRIPTION

Total Number of Interface Pins

Byte mode, 1 interface rate

10 or 11 = 8 or 9 data + 1 clk + 1

sync

(Clk × 4/4)/N; maximum 192.31 MSPS total (for all

channels)

1N

Nibble mode, 1 interface rate

6 = 4 data + 1 clk + 1 sync

(Clk × 4/8)/N; maximum 125 (Nibble 0), 96.15 (Nibble

1) MSPS total

1S

2N

Serial mode, 1 interface rate

Nibble mode, 2 interface rates

4 = 2 data + 1 clk + 1 sync

(Clk × 4/16)/N; maximum 48.07 MSPS total

(Clk × 4/8)/N × 2; maximum 221.15 MSPS total

12 = 4 data + 1 clk + 1 sync + 4

data + 1 clk + 1 sync

2N’⁽¹⁾

Nibble + byte mode, 2 interface

rates,

RX-ADC input pins used for

byte-mode port.

16 = 4 data + 1 clk + 1 sync + 8

data + 1 clk + 1 sync

Nibble port: (Clk × 4/8)/N; maximum 125 MSPS total

Byte port: (Clk × 2/4)/N; maximum 125, 250 MSPS

total

2S

3S

Serial mode, 2 interface rates

8 = 2 data + 1 clk + 1 sync + 2 data (Clk × 4/16)/N; maximum 96.15 MSPS total

+ 1 clk + 1 sync

Serial mode, 3 interface rates

12 = 2 data + 1 clk+1 sync + 2 data (Clk × 4/16)/N; maximum 144.23 MSPS total

+ 1 clk + 1 sync + 2 data + 1 clk + 1

sync

(1) 2N’ is the only configuration that allows a special mode to re-use RX input port A as baseband TX inputs

Table 3. TX BB Pin Assignments

LVDS PAIR BBI[11:0]

BBIN[0] pos. and neg.

BYTE MODE

BB0_DATA_0

BB0_DATA_1

BB0_DATA_2

Spare

NIBBLE MODE

BB0_DATA_0

BB0_DATA_1

BB0_SYNC

BB0_CLOCK

BB0_DATA_2

BB0_DATA_3

BB1_SYNC

BB1_CLOCK

BB1_DATA_0

BB1_DATA_1

BB1_DATA_2

BB1_DATA_3

2

SERIAL MODE

BB0_DATA_0

BB0_DATA_1

BB0_SYNC

BB0_CLOCK

BB1_DATA_0

BB1_DATA_1

BB1_SYNC

BB1_CLOCK

BB2_DATA_0

BB2_DATA_1

BB2_SYNC

BB2_CLOCK

3

BBIN[1] pos. and neg.

BBIN[2] pos. and neg.

BBIN[3] pos. and neg.

BBIN[4] pos. and neg.

BB0_DATA_3

BB0_DATA_4

BB0_SYNC

BB0_CLOCK

BB0_DATA_5

BB0_DATA_6

BB0_DATA_7

BB0_DATA_8

1

BBIN[5] pos. and neg.

BBIN[6] pos. and neg.

BBIN[7] pos. and neg.

BBIN[8] pos. and neg.

BBIN[9] pos. and neg.

BBIN[10] pos. and neg.

BBIN[11] pos. and neg.

Number of BBdata streams

Number of DDR clocks to transfer 1 complex sample

2

4

8

The actual data transfer rate in nibble mode is 2 times higher than the byte mode for the same total throughput. If

two ports are required (e.g., to support two different sample rates), and a lower speed on the interface is desired,

the GC6016 can re-use the RX ADC input port A as a baseband TX input bus. RX ADC port A has 15 pairs of

LVDS input pins and supports one set of baseband input data in byte mode. When RX port A is used as a

baseband TX input, it cannot be also used as an RX input port.

The baseband interface supports a full-clock or gated-clock format. These formats are shown in Figure 10

The mapping for the RX port A pins when in BB TX input mode is:

•

RXA14: clock

RXA13: sync

RXA12–5: BB0_DATA7–0

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BBIN Clk 0

BBIN Sync 0

BBIN Data 0

Mode 1B

I0-O

I0-E

Q0-O

Q0-E

I1-O

I1-E

Q1-O

Q1-E

In-O

In-E

Qn-O

Qn-E

00

I0-O

I0-E

Q0-O

Q0-E

‘n’ can be up to 47, ‘O’ is odd numbered bits (1, 3, 5, ...), ‘E’ is even numbered bits (0, 2, 4, ...)

BBIN Clk 0

BBIN Sync 0

BBIN Data 0

I0-A

I0-B

I0-C

I0-D

Q0-A

Q0-B

Q0-C

Q0-D

In-A

In-B

In-C

In-D

Qn-A

Qn-B

Qn-C

Qn-D

00

I0-A

Mode 1N (1 Rate)

Mode 2N (2 Rates)

BBIN Clk 1

BBIN Sync 1

I0-A

I0-B

I0-C

I0-D

Q0-A

Q0-B

Q0-C

Q0-D

In-A

In-B

In-C

In-D

Qn-A

Qn-B

Qn-C

Qn-D

00

I0-A

BBIN Data 1

‘n’ can be up to 47, ‘A’ is 4 MSBs, ‘B’ is next 4 bits, ‘C’ is next 4 bits and ‘D’ is 4 LSBs

BBIN Clk 0

BBIN Sync 0

I0-A

I0-B

I0-C

I0-D

I0-E

I0-F

I0-G

I0-H

Qn-A

Qn-B

Qn-C

Qn-D

Qn-E

Qn-F

Qn-G

Qn-H

00

I0-A

BBIN Data 0

BBIN Clk 1

Mode 1S (1 Rate)

Mode 2S (2 Rates)

Mode 3S (3 Rates)

BBIN Sync 1

BBIN Data 1

BBIN Clk 2

BBIN Sync 2

BBIN Data 2

‘n’ can be up to 47, ‘A’ is 2 MSBs, ‘B’ is next 2 bits, ‘C’ is next 2 bits, ... and ‘H’ is 2 LSBs

T0504-01

Figure 10. TX BB Formats

The TX formatter block includes a per-channel TX gain adjust via a 16-bit complex digital word which can be set

to have gain between –∞ and 9 dB.

Digital Down- and Upconverters (DDUCs)

The GC6016 has four identical and independent DDUC blocks that can be configured as either DDC or DUC.

Each DDUC can support up to 12 channels with scalable bandwidth.

The only difference between the DUC and DDC configurations is the interpolate (DUC) versus decimate (DDC)

functions and the data path direction as shown in Figure 11. Both DDC and DUC are described in this section.

Note that each DDUC block must be configured statically as a DUC or DDC and cannot switch modes

dynamically in TDD applications.

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1–12 Channel DUC Block

NCO

From BB

Interface

Block

FIR

1´, 2´

Farrow

1–1024´

CIC

1–3´

To Mux and

Sum Block

X

Mixer

All 3 Blocks Interpolate

DUC Configuration

1–12 Channel DDC Block

NCO

To BB

Interface

Block

From

Distributor

Block

FIR

1´, 2´

Farrow

1–1024´

CIC

1–3´

X

Mixer

All 3 Blocks Decimate

DDC Configuration

B0448-01

Figure 11. DUC and DDC Functional Block Diagram

In combination with the follow-on mux and sum block, the DUC block interpolates, filters, mixes each carrier, and

combines multiple channels into one to four wideband, composite TX signal streams. Any input channel can be

mapped to any TX stream in the mux and sum block.

The DDC configuration accepts an RX stream from the distributor block and provides mixing, decimation filtering,

fractional resampling, and filtering to RX channels. The RX block outputs are mapped to the mixer CIC stream

via the distributor block.

Each DDUC block contains a finite impulse response (FIR) filter, a fractional resampler (Farrow filter), a

cascaded integrator-comb (CIC) filter, a complex mixer and NCO for channel placement in the composite stream,

and a programmable frequency hopper (see Figure 11).

The number of taps available in the FIR filter depends on various parameters such as the BBclk rate (derived

from DPDCLK) , input sample rate, interpolate and decimate settings, and number of channels. Different tap

values may be used for each channel (however, that reduces the number of filter taps available).

Note that the input sample rate is the input from the TX BB input formatter for the DUC configuration and the

input from the distributor block for DDC configuration. The number of taps for various wireless standards and

configurations is shown in Table 4.

The Farrow filter supports one real channel or 1–12 complex channels and can be configured for any resampling

ratio from 1 to 1024 with 32-bit resolution. A different delay value for each channel is supported. The Farrow filter

is used to resample different TX BB input sample rates to a common CFR rate, and it provides 95-dB rejection at

±0.25 output f_S(sample rate), 83-dB rejection at ±0.375 output f_S, and 56-dB rejection at ±0.4 output f_S.

The CIC interpolates or decimates by a factor of 1, 2, or 3. If each DDUC must support more than eight carriers,

the CIC must interpolate/decimate by 3. If each DDUC must support between four and eight carriers, the CIC can

interpolate/decimate by 2 or 3. If each DDUC must support fewer than four carriers, the CIC can interpolate by 1,

2, or 3.

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The NCO contains a 48-bit frequency word and 48-bit accumulator, and operates at the DUC output sample rate.

The minimum resolution is the DUC output sample rate or DDC input sample rate divided by 2⁴⁸, or about

0.2 μHz for a 61.44-MSPS DUC output rate. The mixer and NCO can be used for frequency planning or fine

frequency control.

Per-channel phase can be adjusted in the mixer/NCO block with a 16-bit phase word, while per channel

fractional delay can be adjusted in the Farrow block.

Table 4. Number of FIR Filter Taps for Example Signal Types

Input

Sample

Rate

DUC Mode

Interp.

DDC Mode

Decim.

BBclk

Filter Type

No. of

Name

Max. Taps

Channels

Sym or

Un-Sym

MHz

MSPS

1 or 2

lte20_1

245.76

246.4

245.76

243.8

250

30.72

15.36

7.68

44.8

22.4

44.8

22.4

44.8

22.4

11.2

22.4

11.2

22.4

11.2

5.6

S

U

S

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

159

79

lte20_2

lte10_2

2

159

99

lte10_3

3

lte10_4

4

79

lte5_4

4

159

79

lte5_8

8

wimax20_r3

wimax20_t3

wimax20_r2

wimax20_t2

wimax20_r1

wimax20_t1

wimax10_r2

wimax10_t2

wimax10_r3

wimax10_t3

wimax10_r4

wimax10_t4

wimax5_r4

wimax5_t4

wimax5_r8

wimax5_t8

wbcdma_r4

wbcdma_t4

wbcdma_r8

wbcdma_t8

cdma_r12

cdma_t12

tdscdma_r12

tdscdma_t12

gsm_12

3

59

3

39

2

99

2

79

1

219

199

219

199

139

119

99

1

2

3

4

79

4

219

199

99

4

11.2

5.6

8

79

7.68

3.84

7.68

3.84

2.4576

1.2288

2.56

1.28

0.5417

1.625

75

4

159

319

79

4

8

159

99

12

1

100

99

199

99

eedge_12

99

wideband_60MHz_r

wideband_60MHz_t

59

250

75

1

39

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MUX and SUM (TX Direction)

The MUX and SUM block maps any channel from the DUC to any TX stream for subsequent per-stream

processing.

Crest Factor Reduction (CFR)

The CFR blocks include the CFR function and two interpolate-by-2 filters (referred to here as UC1 and UC2).

The two CFR blocks together can support 1, 2, or 4 TX streams. The CFR function selectively reduces the

peak-to-average ratio (PAR) of wideband digital signals provided in quadrature (I and Q) format, such as those

used in 3G and 4G wireless applications. For example, the CFR function can reduce the PAR of WCDMA Test

Model 1 signals to 5.7 dB, while still meeting all 3GPP requirements for ACLR, composite EVM, and peak code

domain error (PCDE).

The CFR blocks can be configured in eleven different modes, depending on the number of TX streams, and the

signal sample rates. Relative to previous TI CFR products, the GC6016 CFR has enhanced features such as:

•

Constant PAR mode

Constant input-to-output power mode

Dynamic PAR target levels for different portions of the time-domain signal

Up to 25% less latency for certain configurations

Enhanced CFR performance for narrowband signals

Automatic (i.e., no host interaction required) CFR coefficient generation for frequency-hopping signals

The UC1 and UC2 blocks can be set to 1× or 2× interpolation and may be used to provide optimum selection of

signal oversampling ratio at CFR. UC1 may be positioned before or after the CFR function, while UC2 is always

at the output of CFR. Since UC2 has only a 40% bandwidth image rejection (90 dB) filter, it is only used if

preceded by UC1, which has an 80% bandwidth image-rejection (90 dB) filter.

TX IF Sub-Chip

The TX IF sub-chip includes a bulk upconverter (BUC), four IF mixer/NCO blocks, and TX stream MUX and

SUM.

The BUC block has interpolations of 1×, 1.5×, 2×, 3×, and 4×.

NOTE

BUC 1.5× is a combination of the BUC 3× interpolation and output-format decimation of 2.

There are four parallel NCO/MIX blocks to allow frequency translation of each composite TX stream. The NCO is

48 bits and is referenced to the TX output rate. The NCO/MIX block (change) can be used to modify the stream

IF frequency.

The TX stream MUX and SUM block allows summing of TX streams to create composite TX streams.

TX DAC Formatter

The DAC output consists of two 20-pair LVDS blocks that can be configured by the DAC formatter block for

several TI DACs and system configurations. The formatter can support up to 8 DACs for 4 TX streams in

complex mode. The DAC formatter block supports the TI DAC5682, DAC328x, and DAC348x families. Table 5

illustrates the pin connections the different DAC and envelope [ET] modulator types.

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Table 5. GC6016 DAC Interface Pin Map

GC6016

328x (ET)

P1-d7

3482 Byte

P1-d7

5682

P1-sync

P1-d15

P1-d14

P1-d13

P1-d12

P1-d11

P1-d10

P1-d9

P1-d8

P1-dataclk

NA

3484

P1-sync

P1-d15

P1-d14

P1-d13

P1-d12

P1-d11

P1-d10

P1-d9

3482 Word

P1-sync

P1-d15

P1-d14

P1-d13

P1-d12

P1-d11

P1-d10

P1-d9

TXA0

TXA1

P1-d6

TXA2

P1-d5

TXA3

P1-d4

TXA4

P1-dataclk

P1-frame

P1-d3

P1-dataclk

P1-frame

P1-d3

TXA5

TXA6

TXA7

P1-d2

TXA8

P1-d1

P1-d8

TXA9

P1-d0

P1-dataclk

P1-frame

P1-d7

P1-dataclk

NA

TXA10

TXA11

TXA12

TXA13

TXA14

TXA15

TXA16

TXA17

TXA18

TXA19

TXB0

P2-d7

P2-d6

P1-d7

P1-d6

P1-d5

P1-d4

P1-d3

P1-d2

P1-d1

P1-d0

NA

P1-d7

P2-d5

P1-d6

P2-d4

P1-d5

P2-dataclk

P2-frame

P2-d3

P2-dataclk

P2-frame

P2-d3

P1-d4

P1-d3

P1-d2

P2-d2

P1-d1

P2-d1

P1-d0

P2-d0

P1-parity

P2-sync

P2-d15

P2-d14

P2-d13

P2-d12

P2-d11

P2-d10

P2-d9

P1-parity

P2-sync

P2-d15

P2-d14

P2-d13

P2-d12

P2-d11

P2-d10

P2-d9

P3-d7

P2- sync

P2-d15

P2-d14

P2-d13

P2-d12

P2-d11

P2-d10

P2-d9

P2-d8

P2-dataclk

NA

TXB1

P3-d6

TXB2

P3-d5

TXB3

P3-d4

TXB4

P3-dataclk

P3-frame

P3-d3

P3-dataclk

P3-frame

P3-d3

TXB5

TXB6

TXB7

P3-d2

TXB8

P3-d1

P2-d8

TXB9

P3-d0

P2-dataclk

P2-frame

P2-d7

P2-dataclk

NA

TXB10

TXB11

TXB12

TXB13

TXB14

TXB15

TXB16

TXB17

TXB18

TXB19

P4-d7

P4-d6

P2-d7

P2-d6

P2-d5

P2-d4

P2-d3

P2-d2

P2-d1

P2-d0

NA

P2-d7

P4-d5

P2-d6

P4-d4

P2-d5

P4-dataclk

P4-frame

P4-d3

P4-dataclk

P4-frame

P4-d3

P2-d4

P2-d3

P2-d2

P4-d2

P2-d1

P4-d1

P2-d0

P4-d0

P2-parity

Note: P1, P2, P3, and P4 are used to identify a specific DAC port. Different ports have different timing.

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RX ADC Formatter

There are three ADC input ports: two 15-pair LVDS ports (referred to as ports A and B) and one 8-pair LVDS

port (referred to as port C and typically used for the DPD feedback path). Depending on the ADCs selected,

these three ports can accommodate up to 17 ADCs (e.g., using two octals and a single). The formatter block can

route any port to either the capture buffer block or the RX signal processing blocks. The pin connections for the

ADCs are shown in Table 6.

The GC6016 works seamlessly with the following TI ADCs.

Single: 5400, 12-bit, 1 GSPS, may need special routing on the PCB.

5463, 12-bit, 500 MSPS, may need clock-to-data-skew special routing on the PCB.

54RF63, 12-bit, 550 MSPS, may need clock-to-data-skew special routing on the PCB.

5474, 14-bit, 400 MSPS, may need clock clock-to-data-skew special routing on the PCB.

5493, 16-bit, 130 MSPS

548x, 16-bit, 80-200 MSPS

612x, 12-bit, 65–250 MSPS

614x, 14-bit, 65-250 MSPS

58B18, 11-bit, 200 MSPS

414x, 14-bit, 160–250 MSPS

412x, 12-bit, 160–250 MSPS

552x, 12-bit, 170–210 MSPS

554x, 14-bit, 170–210 MSPS

5517, 11-bit, 200 MSPS

Dual:

62c15, 11-bit, 125 MSPS

62c17, 11-bit, 200 MSPS

58c28, 11-bit, 200 MSPS

62p4x, 14-bit, 65-250 MSPS

62p2x, 12-bit, 65-250 MSPS

624x, 14-bit, 65-125 MSPS

622x, 12-bit, 65-125 MSPS

Quad:

642x, 12-bit, 65–125 MSPS

644x, 14-bit, 65–125 MSPS

Octal:

527x, 12-bit, 65 MSPS

528x, 12-bit, 65 MSPS

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Table 6. GC6016 ADC Interface Pin Map

58c48 42x9

64p4x

62p4x

58b18 5517

4149 61B49 548x 6145

5547

GC6016

Pin Name

5463 5444

5474

5400L

5400R

642x 644x

527x 528x

Two 624x

62c15

RXA0

RXA1

RXA2

RXA3

RXA4

RXA5

RXA6

RXA7

RXA8

RXA9

RXA10

RXA11

RXA12

RXA13

RXA14

RXB0

RXB1

RXB2

RXB3

RXB4

RXB5

RXB6

RXB7

RXB8

RXB9

RXB10

RXB11

RXB12

RXB13

RXB14

RXC0

RXC1

RXC2

RXC3

RXC4

RXC5

RXC6

RXC7

0

2

4

0

2

0

1

[12]⁽¹⁾

syncout

[istrobe]

11

0

4

2

10

1

d1

d0

b1

b0

f

6

8

0

2

6

3

9

2

8

4

8

3

c1

10

12

clk

[14]

4

10

12

clk

0

5

7

4

c0

c1

clk

c2

c3

c4

c5

c6

c7

fr

a1

a0

clk

6

5

frame

clk

b1

clk

8

7

clk

8

5

6

10

12

14

2

9

4

7

b0

b1

b0

f

4

10

11

12

13

clk

0

3

8

a1

6

2

9

a0

8

1

10

a1

a0

clk

10

12

0

11

[istrobe]

syncout

[12]

0

2

[12]

syncout

2

1

11

0

1

4

2

10

6

0

2

6

3

9

2

8

4

8

3

10

12

clk

[14]

4

10

12

clk

0

5

7

4

6

5

clk

8

7

clk

6

8

5

10

12

14

2

9

4

7

4

10

11

12

13

clk

3

8

6

2

9

8

1

0

10

11

[12]

10

12

[istrobe]

syncout

0

2

4

6

8

10

12

clk

(1) [ ] indicates assignment if pins available

Feedback Processing

The feedback path is input to RXC as a real ADC. This is captured in the capture buffer and sent to the DSP. In

cases where a higher-rate real ADC (>250 Msps) or a complex feedback path is desired, for better feedback

performance, one of the RX ADC inputs can be used for the feedback path, and one RX ADC input is used for

the RX path. Note: both RX downconverters can still be used for the RX path, or one can be used for feedback.

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The widest-band feedback is seen directly from the ADC interface to the capture buffer.

RX Sub-Chips

Each of two RX sub-chips consists of the following blocks (each block may be optionally bypassed), which

operate on a per-stream basis:

•

DC offset cancellation

Front-end automatic gain control (feAGC)

Real-to-Complex (R2C) conversion

Switch for replicating or moving streams across the four paths (per sub-chip)

IF NCO for complex mixing (frequency translation)

Bulk downconverter (BDC)

Equalizer

IQ imbalance correction

DC offset cancellation

The dc offset canceller can be programmed to integrate a number of input samples automatically, divide by a

power of 2, and subtract the mean offset or a programmed offset from the input. The input can be real or

complex. Each input ADC has a separate cancellation for each RX block channel.

Front-end AGC

The feAGC block is used to control the RX ADC input level by controlling an external DVGA.

The feAGC has multiple channels in each RX block:

•

1 real stream up to 4 × DPD clock rate (only use one block)

2 real (using both blocks) or 1 complex stream (only use one block) up to 2 × DPD clock rate each

4 real or 2 complex streams up to DPD clock rate each (uses both blocks)

8 real or 4 complex streams up to 1/2 DPD clock rate each (uses both blocks)

The feAGC has both threshold comparison and an integrated power measurement. The feAGC has an error

accumulation. The error accumulation can be mapped to a specific ADC desired operating point. The integral

controller outputs the DVGA value to control the ADC input. DVGA controls are mapped to the specific DVGA

outputs, supporting multiple DVGA types. Multipliers in the data path can be used to compensate for external

DVGA gain changes (from the feAGC output control word). A delay block aligns the gain value applied to the

internal multiplier with the point in time on the data samples where the external gain change was applied. Use of

this multiplier minimizes gain steps that would cause transients in the downstream digital filters and allows

relative power measurements on the digital signals.

The AGC operation may be suspended during certain conditions. The internal controlled-delay AGC update and

special clock gating can be used to suspend the AGC operation.

The control word outputs from the feAGC blocks are applied to external DVGA parts via the DVGA pins. There

are 16 DVGA pins (3.3-V CMOS) which may be individually configured as DVGA output signals or GPIO (input or

output) signals. When used as DVGA control signals, there are two modes:

•

Transparent mode – parallel output words are connected directly to DVGAs that are being used in a mode

without a clock or latch signal to clock-in the gain word. This is the minimum latency mode. There can be two

ports of 8 bits each, three ports of 5 bits each, four ports of 4 bits each, or five ports of 3 bits each.

•

Clocked mode – eight latch enable (LE) signals and one 8-bit output word. This mode allows up to eight

control signals, up to 8 bits each, but with increased latency. The LE signal may be a positive or negative

pulse, with programmable width.

R2C

In the real-to-complex conversion block, real signal inputs are up- or downconverted by f_S/4, filtered to isolate the

selected sideband, and decimated by a factor of 2. Real-to-complex conversion is bypassed for complex inputs.

The rejection of the R2C decimation filter is:

•

For 90% bandwidth signal, –68 dB, stop band

For 80% bandwidth signal, –106 dB, stop band

Switch

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Any of the up to eight complex RX antenna/signal inputs across both sub-chips may be switched to one or more

of the up to 4 output streams of each sub-chip.

IF NCO

The NCO/mixer block generates in-phase and quadrature sinusoidal signals (cos/sin) and mixes them with the

switched antenna streams to frequency-translate the RX signals. The NCO contains a 48-bit frequency word and

48-bit accumulator.

BDC

The BDC supports the following modes and sample rates at its input (across both sub-chips):

•

Single – 4 × DPD clock rate real, 2× DPD clock rate complex

Dual – 2 × DPD clock rate real, DPD clock rate complex

Quad – DPD clock rate real, 1/2 DPD clock rate complex

Octal – 1/2 DPD clock rate real

Total decimation factors may be 1, 2, 4, 8, or 16. The decimation filtering is achieved with the cascade of the

real-to-complex filter (R2C), a fixed filter F1, and a fixed filter F2. The rejection of the F1 and F2 filters is:

•

Filter F1 (decimate by 1 or 2)

–

If used, always followed by filter F2, so relaxed requirements

45% bandwidth, –107 dB stopband

•

Filter F2

–

Recirculated 1–3 times to provide 2, 4, or 8× decimation factor

90% bandwidth, –75 dB, stop band

80% bandwidth, –106 dB, stop band

Equalizer

The receive equalizer is full-complex 16-tap filter that performs the following signal-processing functions:

•

Programmable spectral inversion at the input

Equalization of analog signal paths

Channel equalization for repeater applications

Gain/phase/fractional delay adjust (MIMO/smart antenna support)

Fixed dc offset compensation at the output

Independent complex coefficients for real and imaginary signal data allow full flexibility for independent

equalization of the direct- and cross-IQ signal components, as well as frequency-dependent IQ gain and phase

imbalance compensation. The programmable 16-bit coefficient sets (i.e., C_ii, C_qq, C_iqand C_qi,for each tap) can be

updated on the fly.

IQ imbalance correction

Automatic correction of IQ imbalance is provided with a 1-tap blind adaptive algorithm. The correction coefficients

also may be programmed to fixed values. This block supports programmable integration intervals and flexible

gating of loop operation.

RX Distributor

The outputs from the RX sub-chips are routed to the RX distributor block, which enables arbitrary assignment of

RX streams to DDC channels and blocks.

RX Baseband Output Formatter

The RX baseband (BB) output formatter block accepts data from the DDC and formats the data for output on the

BB LVDS pins. A back-end AGC (beAGC) function is included that optionally adjusts the gain of each channel

and provides multiple format options. There are 12 unidirectional LVDS pairs for the RX BB interface.

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Back-end AGC

The beAGC function is available for receive channels from DDUC3 and DDUC2 (DDUC1 and DDUC0 may also

be used for receive—with the formats as described following—but without the beAGC function). When the

floating-point format is selected (described following), the beAGC is not used. For the fixed-point formats, the

beAGC may be on or off. There are separate beAGC blocks associated with DDUC3 and DDUC2, and each

block can process up to 12 channels. Within a block, there are two sets of control parameters. This provides

support for two different signal types sharing the same DDUC block. Each channel may have a

programmable-gain starting point or a fixed gain, and there is a per-channel flexible gating signal to control

freeze/operate intervals for TDD signal types. The beAGC has approximately a 100 dB dynamic range. The

beAGC algorithm adjusts the gain to drive the median magnitude of gain-loop output data to a target threshold

value. There are four step-sizes used (two for above and two for below the threshold), depending on distance

from the threshold value.

Output formatter

There are three operational modes for the RX BB output formatter: byte mode (B, 9 bits), nibble mode (N, 4 bits),

and serial mode (S, 2 bits). The nibble and serial modes allow multiple BB output rates and the use of fewer pins

on the interface. The GC6016 can provide up to three different BB output data rates. Table 7 and Table 8

summarize the different modes and pin assignments for the byte, nibble, and serial modes. As can be seen in

Table 8, there are two data formats supported:

•

Floating point (indicated with an F in the mode label; 14- or 16-bit mantissa, 4-bit exponent)

Fixed point without gain word (16- or 18-bit options)

In Table 8, BBOUT[X] is the BBOUT differential pair (assumed positive and negative connections), and BB0,

BB1, and BB2 represent three different RX differential baseband input signals that can be at arbitrary rates.

Figure 12 shows the BB output formats. The maximum-data-rate configurations have the DDR clock out

transitioning synchronously with the data (referred to as DDR Mode 0 in the table). At half the maximum possible

data rate (referred to as DDR Mode 1 in the table) and a quarter of the maximum possible data rate (referred to

as DDR Mode 2 in the table), the DDR clock out transitions in the middle of the data-steady time .

Table 7. RX BB Formatter Modes

Total Number of Interface

Pins

Maximum Complex Interface Rate per Channel

N is the number of channels

MODE

Description

1B

1 interface rate (up to 18 bits)

11 = 9 data + 1 clk + 1 sync

10 = 8 data + 1 clk + 1 sync

(Clk4/4)/N/2; maximum 125 MSPS total (for all channels)

1BF

1 interface rate (up to 16 bits) + exponent (4

bits)

1N

1NF

1S

1 interface rate (16 bits)

6 = 4 data + 1 clk + 1 sync

4 = 2 data + 1 clk + 1 sync

(Clk4/8)/N; maximum 96.15 (Nibble0), 125 (Nibble1) MSPS total

(Clk4/16)/N; maximum 48.07 MSPS total

1 interface rate (14 bits) + exponent (4 bits)

1 interface rate (16 bits)

1SF

2N

1 interface rate (14 bits) + exponent (4 bits)

2 interface rates (16 bits)

(Clk4/16)/N; maximum 48.07 MSPS total

12 = 4 data + 1 clk + 1 sync + (Clk4/8)/N; maximum 221.15 MSPS total

4 data + 1 clk + 1 sync

2NF

2S

2 interface rates (14 bits) + exponent (4 bits)

2 interface rates (16 bits)

12 = 4 data + 1 clk + 1 sync + (Clk4/8)/N; maximum 221.15 MSPS total

4 data + 1 clk + 1 sync

8 = 2 data + 1 clk + 1 sync +

2 data + 1 clk + 1 sync

(Clk4/16)/N; maximum 96.15 MSPS total

2SF

3S

2 interface rates (14 bits)+ exponent (4 bits)

3 interface rates (16 bits)

8 = 2 data + 1 clk + 1 sync +

2 data + 1 clk + 1 sync

(Clk4/16)/N; maximum 96.15 MSPS total

12 = 2 data + 1 clk + 1 sync + (Clk4/16)/N; maximum 144.23 MSPS total

2 data + 1 clk + 1 sync +

2 data + 1 clk + 1 sync

3SF

3 interface rates (14 bits)+ exponent (4 bits)

12 = 2 data + 1 clk + 1 sync + (Clk4/16)/N; maximum 144.23 MSPS total

2 data + 1 clk + 1 sync +

2 data + 1 clk + 1sync

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Table 8. RX BB Pin Assignments

LVDS Pair BBI[11:0]

Byte Mode

BB0_DATA_0

BB0_DATA_1

BB0_DATA_2

Spare

Nibble Mode

BB0_DATA_0

BB0_DATA_1

BB0_SYNC

BB0_CLOCK

BB0_DATA_2

BB0_DATA_3

BB1_SYNC

BB1_CLOCK

BB1_DATA_0

BB1_DATA_1

BB1_DATA_2

BB1_DATA_3

2

Serial Mode

BB0_DATA_0

BB0_DATA_1

BB0_SYNC

BB0_CLOCK

BB1_DATA_0

BB1_DATA_1

BB1_SYNC

BB1_CLOCK

BB2_DATA_0

BB2_DATA_1

BB2_SYNC

BB2_CLOCK

3

BBOUT[0] pos. and neg.

BBOUT[1] pos. and neg.

BBOUT[2] pos. and neg.

BBOUT[3] pos. and neg.

BBOUT[4] pos. and neg.

BBOUT[5] pos. and neg.

BBOUT[6] pos. and neg.

BBOUT[7] pos. and neg.

BBOUT[8] pos. and neg.

BBOUT[9] pos. and neg.

BBOUT[10] pos. and neg.

BBOUT[11] pos. and neg.

Number of BBdata streams

Number of DDR clocks to transfer 1 complex sample

BB0_DATA_3

BB0_DATA_4

BB0_SYNC

BB0_CLOCK

BB0_DATA_5

BB0_DATA_6

BB0_DATA_7

BB0_DATA_8

1

2

4

8

BBOUT Clk 0

(if DDR Mode 0)

Mode 1B

18 bit I/Q Data

9I, 9I, 9Q, 9Q

BBOUT Clk 0

(if DDR Mode 1 or 2)

BBOUT Sync 0

BBOUT Data 0

Mode 1BF

16 bit I/Q Data + 4 bits gain

8I +1G, 8I + 1G, 8Q + 1G, 8Q + 1G

I0-O

I0-E

Q0-O

Q0-E

I1-O

I1-E

Q1-O

Q1-E

In-O

In-E

Qn-O

Qn-E

I0-O

I0-E

Q0-O

Q0-E

‘n’ can be up to 47, ‘O’ is 8 (or 9) odd numbered bits (1, 3, 5, ...), ‘E’ is 8 (or 9) even numbered bits (0, 2, 4, ...), with 0 being the LSB

BBOUT Clk 0

(if DDR Mode 0)

BBOUT Clk 0

(if DDR Mode 1 or 2)

BBOUT Sync 0

BBOUT Data 0

Modes 1N, 2N

16 bit I/Q Data

4I, 4I, 4I, 4I, 4Q, 4Q, 4Q, 4Q

I0-A

I0-B

I0-C

I0-D

Q0-A

Q0-B

Q0-C

Q0-D

In-A

In-B

In-C

In-D

Qn-A

Qn-B

Qn-C

Qn-D

BBOUT Clk 1

(if DDR Mode 0)

Modes 1NF, 2NF

14 bit I/Q Data + 4 bits gain

4I, 4I, 4I, 2I +2Q, 4Q, 4Q, 4Q, 4G

BBOUT Clk 1

(if DDR Mode 1 or 2)

BBOUT Sync 1

BBOUT Data 1

I0-A

I0-B

I0-C

I0-D

Q0-A

Q0-B

Q0-C

Q0-D

In-A

In-B

In-C

In-D

Qn-A

Qn-B

Qn-C

Qn-D

‘n’ can be up to 47, ‘A’ is 4 MSBs, ‘B’ is next 4 bits, ‘C’ is next 4 bits and ‘D’ is 4 LSBs

BBOUT ClkOUT 0

(if DDR Mode 0)

BBOUT Clk 0

(if DDR Mode 1 or 2)

BBOUT Sync 0

BBOUT Data 0

I0-A

I0-B

I0-C

I0-D

I0-E

I0-F

I0-G

I0-H

Qn-A

Qn-B

Qn-C

Qn-D

Qn-E

Qn-F

Qn-G

Qn-H

BBOUT Clk 1

(if DDR Mode 0)

Modes 1S, 2S, 3S

16 bit I/Q Data

4I, 4I, 4I, 4I, 4Q, 4Q, 4Q, 4Q

BBOUT Clk 1

(if DDR Mode 1 or 2)

BBOUT Sync 1

BBOUT Data 1

Modes 1SF, 2SF, 3SF

14 bit I/Q Data + 4 bits gain

4I, 4I, 4I, 2I +2Q, 4Q, 4Q, 4Q, 4G

BBOUT Clk 2

(if DDR Mode 0)

BBOUT Clk 2

(if DDR Mode 1 or 2)

BBOUT Sync 2

BBOUT Data 2

‘n’ can be up to 47, ‘A’ is 2 MSBs, ‘B’ is next 2 bits, ‘C’ is next 2 bits, ... and ‘H’ is 2 LSBs

T0505-01

Figure 12. RX BB Formats

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Capture Buffers

The GC6016 has two capture buffers, each 4096 complex words (18-bits I, 18-bits Q) deep, which are

periodically read by the external coefficient update controller (DSP). The capture buffers can be configured to

sample data signals at the following points in the GC6016:

● CFR output

(Referred to as node A)

(Node B)

● TX equalizer output

● Not used for GC6016

● RX AB input

(Node C)

(Node D)

(Node E)

● RX path 0/1 output

● RX C (feedback) input

● Testbus

(Node F)

(Node G)

The capture buffers can be triggered via an external sync signal, through a software trigger, or when the

monitored signal exceeds the user-configurable thresholds. The capture buffers can be programmed to monitor

the signal statistics continuously and only capture data when certain requirements are met, as well as to

generate an interrupt when a qualified buffer is captured. The capture buffers can be read by the DSP via the

MPU interface.

The capture buffers also allow synchronized multi-chip data capture. In systems with multiple GC5330s and

GC6016s, the sync input can be used to capture the selected input node; the capture is the pre-trigger event.

The SYNCOUT signal can be used to daisy-chain (e.g., connecting to SYNCA on the next chip) across the

GC6016 devices in the system. The SYNCOUT signal indicates the end of the data capture and can be used as

a capture trigger in all chips.

Microprocessor (MPU) Interface

The MPU interface is designed to interface with external memory interface (EMIF) ports on TI DSPs operating in

asynchronous mode. It consists of a 16-bit bidirectional data bus, an 8-bit address bus, and WEB, OEB, CEB,

and EMIFENA control signals. The interface supports the TI ‘C6748 as an EMIF asynchronous interface. The

MPU interface has two address spaces: a paged address space and an auto-increment address space.

To enable the EMIF interface, pin EMIFENA must be set to logic high.

In an MPU write cycle, a GC6016 internal MPUCLK signal is generated by NORing CEB and WEB. The

MPUCLK signal goes high when both CEB and WEB are asserted and goes low as soon as either CEB or WEB

is de-asserted. The MPU data is latched on the rising edge of the MPUCLK signal. For the auto-increment

address spaces, the auto-increment address increments on the falling edge of the MPUCLK signal.

In an MPU read cycle, a GC6016 internal MPUCLK signal is generated by NORing CEB and OEB. The MPUCLK

signal goes high when both CEB and OEB are asserted and goes low as soon as either CEB or OEB is

de-asserted. The MPU readback data is available soon after the rising edge of the MPUCLK signal. For the

auto-increment address spaces, the auto-increment address increments on the failing edge of the MPUCLK

signal.

Figure 13 shows the MPU interface timing diagram. The timing specifications are provided in Table 26 and

Table 27.

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Write Cycle

Read Cycle

CEB

Addr

OEB

WEB

Data

T0506-01

Figure 13. MPU Interface Format

Serial Peripheral Interface (SPI)

The MPU and SPI interfaces can be only enabled one at a time. EMIFENA must be set to logic low to enable the

SPI interface. A three- or four-wire SPI interface is supported in the GC6016. It consists of SPIDENB, SPICLK ,

SPIDIO, and SPIDO-(SPARE) (output in four-wire mode) signals. See Table 25 and Figure 24.

JTAG Interface

The GC6016 includes a five-pin JTAG interface that supports boundary scan for all CMOS pads in the chip,

aside from the TESTMOD pin. The BBIN, BBOUT, RX, TX, and SYNC pins are all LVDS and do not get JTAG

boundary scan. IMPORTANT NOTE: if not using JTAG, the TRSTB signal should be grounded (or pulled to

ground through R ≤ 1 kΩ); otherwise, the JTAG port may take control of the pins. See Table 24 and Figure 23.

A BSDL file is available on the GC6016 Web page.

Input and Output Syncs

The GC6016 features two LVDS input syncs (SYNCA and SYNCB) and one LVDS output (SYNCOUT)

user-programmable sync. These are typically used as trigger/synchronization mechanisms to activate features

within the device. The input syncs can be used to trigger events such as:

•

Power measurements

DUC channel delay, mixer phase and dither

Initializing/loading filter coefficients

Capturing and sourcing of data in the capture buffers

Controlling gating intervals for AGC and other adaptive loops

Frequency NCO changes, or hopping synchronization

The SYNCA signal is used for device startup. The SYNCB signal can be used for shared feedback

synchronization between multiple GC6016 devices. The sync signal is active-high. The width (number of positive

edges of the DPD clock) of the sync signal depends on the configuration. See the GC6016 sync and MPU

application note to determine the proper sync duration. A typical sync-pulse duration is four DPD clocks. The

sync must be periodic, and usually starts at the beginning of the TX frame.

The output sync can be programmed to reflect triggering of specific events within the GC6016, and is primarily

used to output the capture-buffer sync out signal.

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Programmable Power Meters

Interval-Based Power Meter

There are three interval-based power meters which compute magnitude-squared sample values during

programmable time intervals and provide the following results:

•

Integrated magnitude-squared power

Peak power

Number of magnitude-squared values above a first threshold

Number of magnitude-squared values above a second threshold

An interrupt bit is set when new measurement results are available. For its input, each power meter can

independently select from the same set of internal node sources as the capture buffers.

Running-Average Power Meter for PA Protection

The running-average power meter monitors up to four signal streams on a single node, which is selectable from

the same set of internal sources as the capture buffers. For each signal stream, it measures running-average

power and counts instantaneous power values above a threshold (referred to as peaks). It can be used in

conjunction with hardware alarms for monitoring power levels for PA protection.

The running-average power meter has the following features:

•

Running average mode, with programmable forgetting factor exponent, u (0 < u < 15)

AAA y(k+1) = (1 – 2^-u) × y(k) + 2^-u× |x(k)|²,

AAA where x(k) is the signal sample and y(k) is the power meter output.

AAA Typically, one must set u = 11 to get 0.5-dB accuracy, u = 14 to get 0.1-dB accuracy.

•

Peak count mode: counts the number of power values, |x(k)|², above a threshold in a specified number of

samples (window). The number of power values, threshold, and window are all programmable.

Flexible gating of the operation interval

Alarms

The output, y(k), from the running-average power meter can be compared on an ongoing basis to programmable

high and low thresholds (always positive). There are two alarms, alarm0 and alarm1. Each alarm is triggered (if it

is enabled) based on the programmed mode:

(0) Disabled

(1) Average power alarm. The alarm is triggered based on the following conditions:

If alarm polarity = 0 (see the alm_polarity register), y(k) > high_threshold

If alarm polarity = 1, y(k) < low_threshold

If alarm polarity = 2, y(k) > high_threshold or y(k) < low_threshold

(2) Peak power alarm. The alarm is triggered based on the following conditions:

If the count of power values |x(k)|²> peak_threshold exceeds the programmed number of

samples, peak_samples, in a programmed window, peak_window

(3) The alarm is triggered if either (1) or (2) occurs.

Alarm checks are computed on a per-antenna-stream basis. Each antenna stream y(k) result is compared to

per-stream programmable thresholds.

Once an alarm has been triggered, the output INTERRPT pin is asserted and the appropriate (alarm0 or alarm1)

alarm interrupt bit is set and, for alarm1, a programmable action takes place. The programmable action is the

same for all antenna streams, but the alarm triggering is independent for each antenna stream.

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Programmable trigger actions for alarm1:

(0) No action

(1) Reduce gain of CFR output by programmable scale factor (programmed with

stream[n].gain_reduce), only if alarm caused by y(k) > high_threshold and alm_polarit = 0 or 2.

The gain reduction is applied at the CFR input. A control signal from the capture buffer block is

used to select the programmed gain value for the multiplier at the CFR input. When the host

resets this alarm by writing to the appropriate register, the control signal returns to 0 (state that is

not selecting the programmed gain value).

GENERAL SPECIFICATIONS

General Electrical Characteristics

This section describes the electrical characteristics for the CMOS interfaces (DVGA, MPU, JTAG, SPI,

TESTMOD, RESETB and INTERRPT) and LVDS interfaces (BBIN, BBOUT, TXA, TXB, RXA, RXB, RXC, SYNC,

DPDCLK) over recommended operating conditions (unless otherwise noted).

Table 9. General Electrical Characteristics, CMOS Interface

PARAMETER

Voltage input low

Voltage input high

Voltage output low

Voltage output high

Pullup current

TEST CONDITIONS

MIN NOM

MAX UNIT

(1)

V_IL

See

0.8

V_DDSHV

0.5

V

V_IH

V_OL

V_OH

2

I_OL= 2 mA⁽¹⁾

I_OH= –2 mA⁽¹⁾

V_IN= 0 V⁽¹⁾

V

2.4

V_DDSHV

250

V

|I_PU

|

30 100

µA

(1)

|I_PD

Pulldown current

Leakage current

V_IN= V_DDSHV

V_IN= 0 or V_DDSHV

250

(1)(2)

|I_IN

|

20

(1) Chip specifications are production tested at 90°C case temperature for the given specification. Early production lots are sample tested

at –40°C.

(2) For inputs with no pullup or pulldown, inputs with pullup and V_IN= V_DDSHV, inputs with pulldown and V_IN= 0, and bidirectionals in input

mode in either state.

Table 10. General Electrical Characteristics, LVDS Interfaces

PARAMETER

TEST CONDITIONS

(1)

MIN NOM

700

MAX

1500

700

UNIT

mV

Ω

V_ICM

Input common mode voltage (V_P– V_N)/2

Input differential voltage

See

(1)

(2)

(1)

|V_P– V_N|

R_IN

150

Input differential impedance

Output common-mode voltage

Ouput differential voltage

80

1125

250

92

120

V_COM

V_OD

1200

1275

500

mV

(1) Chip specifications are production tested at 90°C case temperature for the given specification. Early production lots are sample tested

at –40°C.

(2) Characteristics are determined by design.

General Switching Characteristics

The baseband interface TX has a single DDR interface input mode. The customer logic and trace routing must

meet the listed t_suand t_hinput timing.

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Table 11. General Switching Characteristics, TX BB LVDS Input

PARAMETER

BASEBAND INTERFACE DDR LVDS

f_{CLK(BB-Serial)}

TEST CONDITIONS

MIN NOM MAX UNIT

384

500(Nibble0)

MHz

(1)

f_{CLK(BB-Nibble)}

Baseband input clock frequency

See

384(Nibble1)

f_CLK(BB-Byte)

f_CLK(RXA)

t_su(BBS0)

t_hi(BBS0)

t_su(BBS1)

t_hi(BBS1)

t_su(BBS2)

t_hi(BBS2)

t_su(BBN0)

t_h(BBN0)

t_su(BBN1)

t_h(BBN1)

t_su(BB)

384

(1)

Baseband input clock frequency, using RXA

BBIN3 Clk, BBIN1:0 Data, BBIN2 Sync

BBIN7 Clk, BBIN5:4 Data, BBIN6 Sync

BBIN11 Clk, BBIN9:8 Data, BBIN10 Sync

BBIN3 Clk, BBIN5,4,1,0 Data, BBIN2 Sync

BBIN7 Clk, BBIN11:8 Data, BBIN6 Sync

BBIN7 Clk, BBIN11:8,5:4,2:0 Data, BBIN6 Sync

See

250

MHz

ps

(1)(2)

250

200

210

250

240

190

250

220

250

220

280

250

t_h(BB)

(1) Chip specifications are production tested at 90°C case temperature for the given specification. Early production lots are sample tested

at –40°C.

(2) Setup and hold times are measured from differential data crossing zero to differential clock crossing zero.

BBIN Clk

BBIN Data, BBIN Sync

t_su

t_h

t_su

T0507-01

Figure 14. TX Baseband LVDS Input Timing Specifications

The BB LVDS RX outputs have three different output timing modes, DDR0, DDR1 and DDR2. DDR1 and DDR2

modes output data, and the BBclk output is centered over the data. In DDR0 mode, the data and clock are

edge-aligned. Different BBOUT pins are used for clock, frame, and data pins depending on the byte, nibble, and

serial modes. The DDR1 and DDR2 modes are shown in Table 12 and Figure 15. The DDR0 mode is shown in

Table 13 and Figure 16. Table 12 and Figure 15. DDR1 mode is used upto a BBclk frequency of 310 MHz.

DDR2 mode is used upto a BBclk frequency of 155 MHz. When the data rate is higher than 500 MHz, BBclk

above 250 MHz, the operating mode is DDR0. In this mode, the clock is aligned with the output data transition. In

DDR0 mode, the customer must delay the clock to meet the t_suand t_hitarget for the baseband input. The t_skw

time is measured as the relative skew for the data and frame to the clock output. This is shown in Figure 12 and

Table 17.

In receive (uplink) mode, the GC6016 outputs data using the LVDS pins BBOUT. The BBOUT port may be

operated in three modes, DDR0, DDR1, and DDR2.

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The lowest-rate outputs use DDR2 mode, where the output clock changes on one rising edge of the internal

clock and the output data changes on the subsequent rising edge. In DDR2 mode, the output bit rate (per LVDS

pair) is half of the internal clock. Middle-rate outputs use DDR1 mode, where the output clock changes on the

falling edge of the internal clock and the output data changes on the rising edge of the internal clock, which

results in an output bit rate equal to the internal clock rate. Both DDR1 and DDR2 result in the output clock edge

occurring in the middle of output data-stable time. The DDR1 and DDR2 modes are shown in Table 12 and

Figure 15.

The highest-rate outputs use DDR0 mode, where both the output clock and output data change with both the

rising and falling edges of the internal clock. The DDR0 output bit rate is twice the internal clock rate. DDR0

results in the clock and data changing at the same time, and typically requires extra trace length on the PC board

for the clockout signal to provide the required setup time for the receiving chip. The DDR0 mode is shown in

Table 13 and Figure 16.

Table 12. General Switching Characteristics, RX BB LVDS Output – DDR1, DDR2

PARAMETER

BASEBAND INTERFACE DDR LVDS

f_CLK(BB-DDR2)

TEST CONDITIONS

MIN NOM

MAX UNIT

See ⁽¹⁾. Applies to BBOUT byte,

nibble, or serial

155

MHz

310

Baseband output clock frequency

f_CLK(BB-DDR1)

t_{skmin(BB)Serial0}

t_{skmax (BB)Serial0}BBOUT3 Clk, BBOUT1:0 Data, BBOUT2 Sync

t_{skmin(BB)Serial1}BBOUT7 Clk, BBOUT5:4 Data, BBOUT6 Sync

t_{skmax (BB)Serial1}BBOUT7 Clk, BBOUT5:4 Data, BBOUT6 Sync

(2)(3)

BBOUT3 Clk, BBOUT1:0 Data, BBOUT2 Sync

See

–20

350

15

ps

(2)(3)

See

(2)(3)

See

(2)(3)

See

310

60

(2)(3)

t_{skmin(BB)Serial2}

BBOUT11 Clk, BBOUT9:8 Data, BBOUT10 Sync

See

(2)(3)

See

300

170

340

55

(2)(3)

t_{skmax(BB)Nibble0}BBOUT3 Clk, BBOUT5,4,1,0 Data, BBOUT2 Sync

t_{skmin(BB)Nibble1}BBOUT7 Clk, BBOUT11:8 Data, BBOUT6 Sync

t_{skmax(BB)Nibble1}BBOUT7 Clk, BBOUT11:8 Data, BBOUT6 Sync

See

(2)(3)

See

(2)(3)

See

(2)(3)

See

305

BBOUT7 Clk, BBOUT11:8,5:4,2:0 Data, BBOUT6

Sync

(2)(3)

t_{skmin(BB)Byte}

t_{skmax(BB)Byte}

See

250

255

ps

BBOUT7 Clk, BBOUT11:8,5:4,2:0 Data, BBOUT6

Sync

(2)(3)

See

(1) Chip specifications are production tested at 90°C case temperature for the given specification. Early production lots are sample tested

at –40°C.

(2) Skew measured for RX BBOUT data and frame signals, relative to the BBclk signal at zero crossing. BBclk is measured at threshold

crossing. Lab measurement +signal → 50 Ω → Vcommon → 50 Ω → –signal. Vcommon has a 0.01-µF filter capacitor to GND.

Differential probe used for measurement.

(3) t_sucalculation: 1/4 BBclk period – t_skmin; t_hcalculation: 1/4 BBclk period – t_skmax

BBOUT Clk

BBOUT Sync

BBOUT Data

t_su

t_h

T0508-01

Figure 15. RX Baseband LVDS DDR1, DDR2 Output Timing Specifications

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Table 13. General Switching Characteristics, RX BB LVDS Output – DDR0

PARAMETER

TEST CONDITIONS

MIN NOM

MAX UNIT

BASEBAND INTERFACE DDR LVDS

f_CLK(Byte)

Baseband output clock frequency

See⁽¹⁾

384

500

384

MHz

ps

f_CLK(Nibble0)

f_CLK(Nibble1)

f_CLK(Serial)

t_{skmax(BB)Serial0}

BBOUT3 Clk, BBOUT1:0 Data, BBOUT2

Sync

See⁽²⁾⁽³⁾

–60

400

–130

500

–45

425

0

t_{skmin(BB)Serial0}

t_{skmax(BB)Serial1}

t_{skmin(BB)Serial1}

t_{skmax(BB)Serial2}

t_{skmin(BB)Serial2}

t_{skmax(BB)Nibble0}

t_{skmin(BB)Nibble0}

t_{skmax(BB)Nibble1}

t_{skmin(BB)Nibble1}

t_{skmax(BB)Byte}

BBOUT3 Clk, BBOUT1:0 Data, BBOUT2

Sync

See^(2)(3)(4)

See⁽²⁾⁽³⁾

See^(2)(3)(4)

See⁽⁵⁾⁽⁶⁾

ps

BBOUT3 Ck, BBOUT1:0 Data, BBOUT2

Sync

BBOUT3 Clk, BBOUT1:0 Data, BBOUT2

Sync

BBOUT7 Clk, BBOUT5:4 Data, BBOUT6

Sync

BBOUT7 Clk, BBOUT5:4 Data, BBOUT6

Sync

BBOUT3 Clk, BBOUT5,4,1,0 Data, BBOUT2 See⁽⁵⁾⁽⁶⁾

Sync

BBOUT3 Clk, BBOUT5,4,1,0 Data, BBOUT2 See^(5)(6)(7)

Sync

See^(5)(6)(7)

400

10

BBOUT7 Clk, BBOUT11:8 Data, BBOUT6

Sync

See⁽⁵⁾⁽⁶⁾

BBOUT7 Clk, BBOUT11:8 Data, BBOUT6

Sync

See^(5)(6)(7)

See⁽⁵⁾⁽⁶⁾

460

0

BBOUT7 Clk, BBOUT11:8,5:4,2:0 Data,

BBOUT6 Sync

t_{skmin(BB)Byte}

BBOUT7 Clk, BBOUT11:8,5:4,2:0 Data,

BBOUT6 Sync

See^(5)(6)(7)

480

(1) Chip specifications are production tested at 90°C case temperature for the given specification. Early production lots are sample tested

at –40°C.

(2) Skew measured for RX BBOUT data and frame signals, relative to the BBclk signal at zero crossing. BBclk is measured at threshold

crossing. Lab measurement +signal → 50 Ω → Vcommon → 50 Ω → –signal. Vcommon has a 0.01-µF filter capacitor to GND.

Differential probe used for measurement.

(3) The customer interface design modifies the trace lengths based on the desired receiver timing and clock delays.

(4) t_su= –t_skmax; t_hold= 1/4 BBclk period – t_skmin

.

(5) Skew measured for RX BBOUT data and frame signals, relative to the BBclk signal at zero crossing. BBclk is measured at threshold

crossing. Lab measurement +signal → 50 Ω → Vcommon → 50 Ω → –signal. Vcommon has a 0.01-µF filter capacitor to GND.

Differential probe used for measurement.

(6) The customer interface design modifies the trace lengths based on the desired receiver timing and clock delays.

(7) t_su= –t_skmax; t_hold= 1/4 BBclk period – t_skmin

.

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BBOUT Data, BBOUT Sync

BBOUT Clk

t_skmax

t_skmin

t_skmax

t_skmin

Ideal

Data

Placement

Ideal

Data

Placement

T0509-01

Figure 16. RX Baseband LVDS DDR0 Output Timing Specifications

The DAC TX interface has a 40-signal output bus. The DAC TX bus can provide 4-byte-wide or 2-word-wide

interfaces. Table 5 shows the different DAC devices that can be connected to the TX output ports. The DAC TX

interface has two styles of clock output, one where the DDR clock is centered over the output data-stable time,

and one where the clock transition is aligned with the data transition. If the output clock rate is greater than

500 MHz, the GC6016 must be configured for clock transition aligned with the data transition. Depending on the

DAC type selected, the clock, frame, and data for the DAC may require a trace routing delay for proper

alignment. See Table 14, Table 15, and Table 16.

Table 14. TX DAC and Envelope Modulator Characteristics

DAC or Envelope Modulator

Timing Model

Clock centered over data

DAC Data Rate Table Number Figure Number

Type

DAC3282, 3283 byte-envelope

modulator

<1000 Mbyte/s

Table 15

Figure 17

DAC3282, 3283 byte-envelope

modulator

Clock aligned with data at GC6016, routing

provides timing skew for clock centered over data

≥1000 Mbyted/s

<1000 Mword/s

≥1000 Mword/s

Table 16

Table 15

Table 16

Figure 18

Figure 17

Figure 18

DAC3484, 3482 word

Clock centered over data

Clock aligned with data at GC6016, routing

provides timing skew for clock centered over data

DAC3484, 3482 word

Clock aligned with data at GC6016. PC board

routing may be required to provide some timing

skew for optimum performance.

DAC5682

All

Table 16

Figure 18

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Table 15. TX DAC Clock Centered Over Data Switching Characteristics (See Table 5 for Connections)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

DDR LVDS

f_CLK(DAC)

DAC output clock frequency

See⁽¹⁾

620

MHz

MIN

SKEW

MAX

SKEW

CLOCK

DATA

TEST CONDITIONS

UNIT

(2)(3)

TXA4

TXA14

TXA9

TXB4

TXB14

TXB9

TXA9:5, 3:0

See

–190

–241

–200

–169

–198

–145

139

205

155

238

146

235

ps

(2)(3)

TXA19:15, 13:10

TXA19:10, 8:0

TXB9:5, 3:0

TXB19:15, 13:10

TXB19:10, 8:0

(1) Chip specifications are production tested at 90°C case temperature for the given specification. Early production lots are sample tested

at –40°C.

(2) Skew measured from DAC DATA desired P/N crossing to DATA P/N crossing. A negative skew is when the data arrives prior to the

clock.

(3) t_su= 1/4 DAC clock period – Max. Skew, t_h= 1/4 DAC clock period + Min. Skew

Table 16. TX DAC Clock Aligned With Data Switching Characteristics (See Table 5 for Connections)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

DDR LVDS

f_CLK(DAC)

(1)

DAC output clock frequency

See

620

MHz

MIN

SKEW

MAX

SKEW

CLOCK

DATA

TEST CONDITIONS

UNIT

(2)

TXA4

TXA14

TXA9

TXB4

TXB14

TXB9

TXA9:5, 3:0

See

–190

–241

–200

–169

–198

–145

139

205

155

238

146

235

ps

TXA19:15, 13:10

TXA19:10, 8:0

TXB9:5, 3:0

TXB19:15, 13:10

TXB19:10, 8:0

(1) Chip specifications are production tested at 90°C case temperature for the given specification. Early production lots are sample tested

at –40°C.

(2) Skew measured from DAC DATA desired P/N crossing to DATA P/N crossing. A negative skew is when the data arrives prior to the

clock.

DAC Data, DAC Frame

DAC Data Clock

Min

Skew

Max

Skew

Max

Skew

Min

Skew

Ideal Data Placement

T0510-01

Figure 17. TX LVDS Timing Specifications (TXA and TXB) (DACCLK Centered Over Data)

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DAC Data, DAC Frame

DAC Data Clock

Min

Skew

Max

Skew

Min

Skew

Max

Skew

Ideal

Data

Placement

Ideal

Data

Placement

T0511-01

Figure 18. TX LVDS Timing Specifications (TXA and TXB) (DACCLK Aligned With Data)

The ADC output interface has two types of timing, based on the clock centered over the data, or clock

edge-aligned with the data. The GC6016 only processes clock centered over the data. Each ADC type is

characterized by the data and clock alignment, in Table 17, from which the proper table and timing diagram can

be determined as follows: ADC W7 in Table 18 and Figure 19; ADC W14 in Table 19 and Figure 20; and ADC

B7 in Table 20 and Figure 19. Note: The general ADC routing is to align the clock and data traces with a

common routing delay. For the ADS5463 and ADS5474 the clock trace must be adjusted in length to meet the

system timing design.

Note: when RXA is used as a baseband interface, the specification is shown in table Table 17. The table shows

a sampling of ADCs released at publication time. If the clock is not centered, the pc board may require added

routing delay to the clock out to satisfy the setup time requirements. See (*) in Table 17.

W7 – word-wide ADC interface, clock on bit 7

W14 – word-wide ADC interface, clock on bit 14

B7 – byte-wide ADC interface, clock on bit 7

B14 – byte-wide ADC interface, clock on bit 14

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Table 17. General LVDS ADC Interface Table

Clock

Centered

ADC Type

ADS5400

Bits per Rail

ADC Format

ADC Input Timing Table

ADC Figure

1

Yes

No

W7

Table 18

Table 19

Figure 19

ADS54RF63 (*)

ADS5463 (*)

ADS5474 (*)

W14

RXA as baseband

TX input

2

Yes

Baseband format – W14

Table 21

Table 20

Figure 19

ADS61xx, ADS41xx,

ADS62pxx

B7

ADS55xx

2

Yes

B7, W7

Table 20Table 18

Figure 19

ADS58B18

ADS58B28,

ADS62c1x

2

Yes

B7, W7

Table 20Table 18

Figure 19

ADS64xx

ADS52xx

6 or 7

Yes

W7

Table 18

Figure 20

12 or 14

Table 18. RX ADC-W7 Switching Characteristics

PARAMETER

TEST CONDITIONS

MIN NOM

MAX UNIT

(1)

f_CLK(ADC)

t_su(ADC,A)

RX input clock frequency, ADCA7 Clk

See

620

MHz

Input data setup time on port A before ADCA7

Clk transition

(1)(2)

260

170

260

140

ps

Input data hold time on port A after ADCA7 Clk

transition

t_h(ADC,A)

t_su(ADC,B)

t_h(ADC,B)

See

ps

Input data setup time on port B before ADCB7

Clk transition

Input data hold time on port B after ADCB7 Clk

transition

(1) Chip specifications are production tested at 90°C case temperature for the given specification. Early production lots are sample tested

at –40°C.

(2) Setup and hold times apply to data and appropriate ADC Clk, respectively. Timing is measured from ADC Clk threshold crossing.

ADC Clock

ADC Data

t_su

t_h

t_su

T0512-01

Figure 19. RX ADC LVDS Timing Specifications (RXA and RXB)

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Table 19. RX ADC-W14 Switching Characteristics

PARAMETER

TEST CONDITIONS

MIN NOM

MAX UNIT

RX input clock frequency ADCA14 Clk,

ADCB14 Clk

(1)

f_CLK(ADC)

t_su(ADC,A)

See

620

MHz

ps

(1)(2)

Input data setup time on port A before

ADCA14 Clk transition

160

200

180

220

t_h(ADC,A)

t_su(ADC,B)

t_h(ADC,B)

Input data hold time on port A after

ADCA14 Clk transition

See

ps

Input data setup time on port B before

ADCB14 Clk transition

Input data hold time on port B after

ADCB14 Clk transition

(1) Chip specifications are production tested at 90°C case temperature for the given specification. Early production lots are sample tested

at –40°C.

(2) Setup and hold times apply to data and appropriate ADC Clk, respectively. Timing is measured from ADC Clk threshold crossing.

Table 20. RX ADC-B7, B14 Switching Characteristics

PARAMETER

TEST CONDITIONS

MIN NOM

MAX UNIT

(1)

f_CLK(ADC-AB)RX input clock frequency, ADCA7 Clk,

ADCB7 Clk

See

620

MHz

(1)

f_CLK(ADC-C)

RX input clock frequency, ADCC7 Clk

See

620

MHz

ps

Input data setup time on port A before

ADCA7 Clk transition

(1)(2)

t_su(ADC,A)

260

160

170

140

290

150

130

200

170

240

Input data hold time on port A after

ADCA7 Clk transition

(1)(2)

t_h(ADC,A)

t_su(ADC,B)

t_h(ADC,B)

t_su(ADC,C)

t_h(ADC,C)

t_su(ADC,A)

t_h(ADC,A)

t_su(ADC,B)

t_h(ADC,B)

See

ps

Input data setup time on port B before

ADCB7 Clk transition

Input data hold time on port B after

ADCB7 Clk transition

Input data setup time on port C before

ADCC7 Clk transition

Input data hold time on port C after

ADCC7 Clk transition

Input data setup time on port A before

ADCA14 Clk transition

Input data hold time on port A after

ADCA14 Clk transition

Input data setup time on port B before

ADCB14 Clk transition

Input data hold time on port B after

ADCB14 Clk transition

(1) Chip specifications are production tested at 90°C case temperature for the given specification. Early production lots are sample tested

at –40°C.

(2) Setup and hold times apply to data and appropriate ADC Clk, respectively. Timing is measured from ADC Clk threshold crossing.

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ADC Clock

ADC Frame Clock

ADC Data

t_su

t_h

t_su

T0513-01

Figure 20. RX ADC LVDS Timing Specifications (RXA and RXB)

Table 21. RXA-BB Switching Characteristics

PARAMETER

TEST CONDITIONS

MIN NOM

MAX UNIT

(1)

f_CLK(BB-A)

t_su(BB-A)

RX input clock frequency

See

250

MHz

Input data setup time on port A before

ADCA Clk transition

(1)(2)

160

200

ps

Input data hold time on port A after

ADCA Clk transition

t_h(BB-A)

See

ps

(1) Chip specifications are production tested at 90°C case temperature for the given specification. Early production lots are sample tested

at –40°C.

(2) Setup and hold times apply to data and appropriate ADC Clk, respectively. Timing is measured from ADC Clk threshold crossing.

Table 22. DPD Clock and Sync A,B Switching Characteristics⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN NOM

MAX UNIT

(2)

f_CLK(DPD)

f_CLK(BB)

DPD input clock frequency

BB internal clock frequency

DPD input clock duty cycle

See

310

250

MHz

(1)

(3)

(2)

t_DUTY-CYCLE

40%

60%

2.5%

f_{CLK (JITTERRMS-DPD)}DPD clock input jitter

t_su(SYNCA)

t_h(SYNCA)

t_su(SYNCB)

t_h(SYNCB)

Input data setup time before f_CLK

Input data hold time after f_CLK

Input data setup time before f_CLK

Input data hold time after f_CLK

↑

0.25

0.1

ns

↑

0.35

0.05

↑

(1) The PLL output ranges are 400–1000 MHz. These are configuration dependent but related to the DPDCLK frequency. The cmd5330

software automatically checks these limits when compiling a configuration.

(2) Chip specifications are production tested at 90°C case temperature for the given specification. Early production lots are sample tested

at –40°C.

(3) Specification is from the PLL specification and is not production tested.

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DPD Clock

SYNCA, SYNCB

t_su

t_h

T0514-01

4 cycles, min.

Figure 21. SYNCA, SYNCB Timing to DPD Clock

Table 23. DPD Clock and Sync Out Switching Characteristics

PARAMETER

TEST CONDITIONS

MIN NOM

MAX UNIT

(1)

t_d(SYNCOut)

Data valid after DPD clock

See

0.95

ns

(1)

t_HO(SYNCOut)Data held valid after next DPD clock

0.3

(1) Chip specifications are production tested at 90°C case temperature for the given specification. Early production lots are sample tested

at –40°C.

Sync Out

DPD Clock

t_d

t_HO

T0515-01

Figure 22. Sync Out Timing to DPD Clock

The JTAG test connections are used with the CMOS signals for board interconnection tests. The TRSTB pin

must be toggled low, or low initially. If JTAG is not used, the TRSTB signal should be GROUNDed or tied to

GND through < 1 kΩ resistance. TRSTB should be 0 for normal operation.

Table 24. JTAG Switching Characteristics

PARAMETER

JTAG clock frequency

TEST CONDITIONS

MIN

MAX

UNIT

MHz

ns

f_TCK

50

(1)

t_TCKL

JTAG clock low period

See

10

t_TCKH

JTAG clock high period

ns

t_su(TDI,TMS)

t_H(TDI,TMS)

t_d

Input data setup time before f_TCK

↑

7

ns

Input data hold time after f_TCK

Output data delay from f_TCK

Previous data valid from f_TCK

↑

1.5

↓

10

2

ns

t_OHD(TDO)

↓

(1) Chip specifications are production tested at 90°C case temperature for the given specification. Early production lots are sample tested

at –40°C.

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t

TCK

TDI

t_SU

t_H

TDO

t_d

t_OH

T0289-02

Figure 23. JTAG Timing Specifications

The SPI programming interface is active only when EMIFENA is 0. There are both three-wire and four-wire SPI

interfaces; the SPIDO(SPARE) is the fourth wire for SPI data output.

Table 25. SPI Switching Characteristics

PARAMETER

TEST CONDITIONS

Valid for SPIDENB, see⁽¹⁾

Valid for SPIDIO, see⁽¹⁾

Valid for SPIDIO, see⁽²⁾

Valid for SPIDO(SPARE), see⁽²⁾

See⁽¹⁾

MIN NOM

MAX UNIT

t_su(DENB)

t_su(DI)

Enable setup time before SPI CLK↑

Data setup time before SPI CLK↑

Input data hold time after CLK↑

5

ns

t_h(DI)

0.6

t_d(DO)

Output data delay from f_TCK

SPI clock frequency

↓

8

ns

t_d(DO1)

f_{clk SPI}

50

MHz

(1) Chip specifications are production tested at 90°C case temperature for the given specification. Early production lots are sample tested

at –40°C.

(2) The SPI data output in three-wire mode comes from SPIDIO; in four-wire mode the output is from SPIDO(SPARE).

SPI Clock

t_su(DENB)

t_h(DI)

SPIENB

t_su(DI)

SPIDIO-In

SPIDO(SPARE)

t_d(DO1)

t_h(DO)

T0516-01

Figure 24. SPI Timing Specifications

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Table 26. MPU Switching Characteristics (READ)

PARAMETER

TEST CONDITIONS

MIN MAX UNIT

t_su(RD)

t_dly(RD)

t_h(RD)

CEB and ADDR setup time to ↓OEB

Data valid time after ↓OEB

See⁽¹⁾

See⁽²⁾

See⁽¹⁾

1.5

ns

15

CEB and ADDR hold time to ↑OEB

Time OEB must remain HIGH between READs

Data goes to high-impedance state after ↑OEB or ↑CEB

Time between READs

2.5

6

t_HIGH(RD)

t_z(RD)

t_cycle(RD)

t_oh(RD)

5

21

(2)

Time after OEB↑ that data is valid

See

TBD

(1) Chip specifications are production tested at 90°C case temperature for the given specification. Early production lots are sample tested

at –40°C.

(2) Bench tested for output start changing after releasing strobe with a 50-Ω load on the output

CEB

t_su(RD)

t_h(RD)

Addr

WEB

OEB

Data

t_su(RD)

t_h(RD)

t_z(RD)

t_dly(RD)

t_oh(RD)

T0517-01

Figure 25. MPU READ Timing Specifications

Table 27. MPU Switching Characteristics (WRITE)

PARAMETER

TEST CONDITIONS

MIN MAX UNIT

t_su(WR)

CEB, DATA, and ADDR setup time to ↓WEB

CEB, DATA, and ADDR hold time after ↑WEB

Time WEB and CEB must remain simultaneously LOW

Time CEB or WRB must remain HIGH between WRITEs

Time between WRITEs

See⁽¹⁾

1.4

3

ns

t_h(WR)

t_low(WR)

t_high(WR)

t_cycle(WR)

4

7

11

(1) Chip specifications are production tested at 90°C case temperature for the given specification. Early production lots are sample tested

at –40°C.

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CEB

t_su(WR)

t_h(WR)

Addr

t_su(WR)

t_h(WR)

OEB

t_low(WR)

t_high(WR)

WEB

t_su(WR)

t_h(WR)

Data

T0518-01

Figure 26. MPU WRITE Timing Specifications

Power Sequencing Guideline

TI ASIC I/O design allows either the core supply (VDD) or the I/O supply (VDDS) to be powered up⁽²⁾for an

indefinite period of time while the other power supply is not powered up, if all of these constraints are met:

•

Chip is within all maximum ratings and recommended operating conditions.

Have followed all warnings about exposure to maximum rated and recommended conditions, particularly

junction temperature. These apply to power transitions as well as normal operation.

•

Bus contention while VDDS is powered up must be limited to 100 hours over the projected lifetime of the

device.

Bus contention while VDDS is powered down may violate the absolute maximum ratings.

However, it is generally good practice to power up VDD, VDDSHV, and VDDS all within 1 second of each other.

Application Information

The GC5330/GC6016 evaluation module includes the following additional transmit/receive signal chain

components:

•

TMS320C6748 digital signal processor (DSP)

DAC3283 16-bit 800-MSPS, dac348X, or DAC5682 16-bit, 1-GSPS DAC (transmit path)

CDCE72010 clock generator

TRF3720 300-MHz to 4.8-GHz quadrature modulator with integrated wideband PLL/VCO

TRF370317 0.4-GHz to 4-GHz quadrature modulator

ADS41B49 14-bit, 250-MSPS ADC (and other options; feedback path)

AMC7823 analog monitoring and control circuit with GPIO and SPI

PGA870 wideband programmable gain amplifier

ADS42b49 14-bit dual 250-MSPS receive or complex feedback ADC (and other options; RX path)

(2) A supply bus is powered up when the voltage is within the recommended operating range. It is powered down when it is below that

range, either stable or in transition.

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MPU Interface Guidelines

The following section describes the hardware interface between the recommended microprocessor and the

GC6016. The GC6016 interface is an EMIF asynchronous interface.

The TMS320C674x/OMAP-L1x Processor Peripherals Overview referencde guide (SPRUFK9) illustrates the

connections to the TMS320C6748 peripherals. The TMS320C674x/OMAP-L1x Processor External Memory

Interface A (EMIFA) user's guide (SPRUFL6) illustrates the connections to the EMIF A interface, and DSP timing.

It is recommended that if more than one EMIF-A load is connected to the DSP, buffering is used for the control

bus WE, RD, address bus, and data bus.


型号：	GC6016IZEV
厂家：	TEXAS INSTRUMENTS
描述：	Wideband Transmit-Receive Digital Signal Processors
文件：	总46页 (文件大小：510K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

GC6016IZEV [TI]

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