HD3SS213 [TI]
支持 DDC/AUX 开关的 5.4Gbps DisplayPort 1.2a 1:2/2:1 差动多路复用器;
| 型号： | HD3SS213 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 支持 DDC/AUX 开关的 5.4Gbps DisplayPort 1.2a 1:2/2:1 差动多路复用器 开关 复用器 |
| 文件： | 总25页 (文件大小：1823K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HD3SS213
ZHCSBL2C –DECEMBER 2016 –REVISED JANUARY 2021
HD3SS213 5.4Gbps DisplayPort 1.2a 2:1 和1:2 差动开关
1 特性
3 说明
• 符合DisplayPort 1.2 电气标准
• 2:1 和1:2 切换最高支持5.4Gbps 的数据速率
• 支持HPD 切换
• 支持AUX 和DDC 切换
• –3dB 差动带宽宽达5.4GHz 以上
• 出色的动态特性（2.7GHz 时）：
– 串扰= -50dB
HD3SS213 器件是一款高速无源开关，能够在一个应
用中将两个完整 DisplayPort 4 通道端口从两个源之一
切换到一个目标位置。它还将一个源切换到两个接收器
之一。对于 DisplayPort 应用，HD3SS213 支持 ZEQ
封装中辅助 (AUX)、显示数据通道 (DDC) 和热插拔检
测(HPD) 信号的切换。
一个典型应用是主板，该主板包含两个需要驱动一个
DisplayPort 接收器的 GPU。GPU 由 Dx_SEL 引脚选
择。另一个应用是一个源需要在两个接收器之间切换，
例如一个侧面连接器和一个扩展坞连接器。此切换操作
由 Dx_SEL 和 AUX_SEL 引脚控制。HD3SS213 在
-40°C 至 105°C 的完全工业温度范围内由一个电压为
3.3 V 的单电源供电运行。
– 隔离= -25dB
– 插入损耗= -1.5dB
– 回损= -13dB
– 最大位间偏差= 5ps
• VDD 工作范围：3.3V±10%
• 封装选项：
– 5mm × 5mm，50 引脚nFBGA
• 输出使能(OE) 引脚禁用开关以省电
• HD3SS213 < 10mW（待机功耗< 30µW
此时，OE = L）
器件信息(1)
封装尺寸（标称值）
器件型号
HD3SS213
封装
nFBGA (50)
5.00mm x 5.00mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
2 应用
DAx(p)
• PC 和笔记本电脑
• 平板电脑
• 联网外设和打印机
DCx(p)
DAx(n)
DCx(n)
AUXAx
Source A
DDCA
DDCC
DP Sink
HPDA
AUXCx
HPDC
AUXBx
DDCB
HPDB
OE
Source B
Dx_SEL
AUX_SEL
Control
DBx(p)
DBx(n)
HD3SS213 2:1
DAx(p)
DAx(n)
DCx(p)
DCx(n)
AUXAx
DP Sink A
DDCA
HPDA
DP Source
DDCC
AUXCx
HPDC
AUXBx
DDCB
HPDB
OE
DP Sink B
Dx_SEL
AUX_SEL
Control
DBx(p)
DBx(n)
HD3SS213 1:2
Copyright © 2016, Texas Instruments Incorporated
HD3SS213 应用方框图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLAS901
HD3SS213
www.ti.com.cn
ZHCSBL2C –DECEMBER 2016 –REVISED JANUARY 2021
Table of Contents
7.3 Feature Description...................................................11
7.4 Device Functional Modes..........................................11
8 Application and Implementation..................................12
8.1 Application Information............................................. 12
8.2 Typical Applications.................................................. 13
9 Layout.............................................................................16
9.1 Layout Guidelines..................................................... 16
9.2 Layout Example........................................................ 17
10 Device and Documentation Support..........................18
10.1 接收文档更新通知................................................... 18
10.2 支持资源..................................................................18
10.3 Trademarks.............................................................18
10.4 静电放电警告.......................................................... 18
10.5 术语表..................................................................... 18
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................6
6.6 Timing Requirements..................................................7
6.7 Typical Characteristics................................................9
7 Detailed Description......................................................10
7.1 Overview...................................................................10
7.2 Functional Block Diagram.........................................10
Information.................................................................... 18
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision B (December 2016) to Revision C (January 2021)
Page
• 注：采用MicroStar Jr. BGA 封装的器件采用层压nFBGA 封装进行了重新设计。这种nFBGA 封装提供了类似
于数据表中的电气性能。该封装占用空间也类似于MicroStar Jr. BGA。将在整个数据表中更新全新封装标识符
来代替已停止使用的封装标识符。......................................................................................................................1
• 将u*jr BGA 更改为nFBGA.................................................................................................................................1
• Changed ZQE to ZXH.........................................................................................................................................3
• Changed u*jr ZQE to nFBGA ZXH. Updated thermal data.................................................................................6
• Changed u*jr BGA to nFBGA........................................................................................................................... 10
Changes from Revision A (September 2013) to Revision B (December 2016)
Page
• 添加了器件信息表、ESD 等级表、特性说明部分、器件功能模式部分、应用和实施部分、电源相关建议部
分、布局部分、器件和文档支持部分以及机械、封装和可订购信息部分......................................................... 1
• Added A2 to J4 row in Pin Functions table.........................................................................................................3
Changes from Revision * (September 2013) to Revision A (September 2013)
Page
• Deleted Ordering Information............................................................................................................................. 3
Copyright © 2023 Texas Instruments Incorporated
2
Submit Document Feedback
Product Folder Links: HD3SS213
HD3SS213
www.ti.com.cn
ZHCSBL2C –DECEMBER 2016 –REVISED JANUARY 2021
5 Pin Configuration and Functions
1
2
3
4
5
6
7
8
9
Dx_SEL
VDD
DA0(n)
DA1(n)
DA2(n)
DA3(p)
DA3(n)
A
B
C
D
E
F
DC0(n)
DC0(p)
AUX_SEL
DC1(p)
GND
DA0(p)
DA1(p)
DA2(p)
OE
DB0(p)
GND
DB0(n)
DC1(n)
DC2(n)
DC3(n)
DB1(p)
DB2(p)
DB3(p)
DB1(n)
DB2(n)
DB3(n)
DC2(p)
DC3(p)
GND
AUXC(p)
HPDA
GND
G
H
AUXC(n)
HPDC
HPDB
GND
VDD
DDCCLK_B AUXB(p)
GND
DDCCLK_A AUXA(p)
DDCCLK_C
DDCDAT_B AUXB(n) DDCDAT_C DDCDAT_A AUXA(n)
J
nFBGA 50-Pin ZXH Package Top View
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION(2)
NO.
NAME
H9,
J9
AUXA(p),
AUXA(n)
Port A AUX positive signal
Port A AUX negative signal
I/O
I/O
H6,
J6
AUXB(p),
AUXB(n)
Port B AUX positive signal
Port B AUX negative signal
H2,
H1
AUXC(p),
AUXC(n)
Port C AUX positive signal
Port C AUX negative signal
I/O
I
C2
AUX_SEL
AUX/DDC selection control pin in conjunction with Dx_SEL Pin
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: HD3SS213
HD3SS213
www.ti.com.cn
ZHCSBL2C –DECEMBER 2016 –REVISED JANUARY 2021
表5-1. Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION(2)
NO.
NAME
NA
CADA/B/C
I/O
I/O
Port A/B/C cable activity detect
B4,
A4
DA0(p),
DA0(n)
Port A, Channel 0, High speed positive signal
Port A, Channel 0, High speed negative signal
B5,
A5
DA1(p),
DA1(n)
Port A, Channel 1, High speed positive signal
Port A, Channel 1, High speed negative signal
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
B6,
A6
DA2(p),
DA2(n)
Port A, Channel 2, High speed positive signal
Port A, Channel 2, High speed negative signal
A8,
A9
DA3(p),
DA3(n)
Port A, Channel 3, High speed positive signal
Port A, Channel 3, High speed negative signal
B8,
B9
DB0(p),
DB0(n)
Port B, Channel 0, High speed positive signal
Port B, Channel 0, High speed negative signal
D8,
D9
DB1(p),
DB1(n)
Port B, Channel 1, High speed positive signal
Port B, Channel 1, High speed negative signal
E8,
E9
DB2(p),
DB2(n)
Port B, Channel 2, High speed positive signal
Port B, Channel 2, High speed negative signal
F8,
F9
DB3(p),
DB3(n)
Port B, Channel 3, High speed positive signal
Port B, Channel 3, High speed negative signal
B2,
B1
DC0(p),
DC0(n)
Port C, Channel 0, High speed positive signal
Port C, Channel 0, High speed negative signal
D2,
D1
DC1(p),
DC1(n)
Port C, Channel 1, High speed positive signal
Port C, Channel 1, High speed negative signal
E2,
E1
DC2(p),
DC2(n)
Port C, Channel 2, High speed positive signal
Port C, Channel 2, High speed negative signal
F2,
F1
DC3(p),
DC3(n)
Port C, Channel 3, High speed positive signal
Port C, Channel 3, High speed negative signal
H8,
J8
DDCCLK_A,
DDCDAT_A
Port A DDC clock signal
Port A DDC data signal
H5,
J5
DDCCLK_B,
DDCDAT_B
Port B DDC clock signal
Port B DDC data signal
J3,
J7
DDCCLK_C,
DDCDAT_C
Port C DDC clock signal
Port C DDC data signal
I/O
I
A1
Dx_SEL
GND
High speed port selection control pins
Ground
B3, C8, G2,
G8, H4, H7
S
J2
H3
J1
HPDA
HPDB
HPDC
I/O
I/O
I/O
Port A hot plug detect
Port B hot plug detect
Port C hot plug detect
Output enable:
B7
OE
I
OE = VIH: Normal operation
OE = VIL: Standby mode
A2,
J4
VDD
S
3.3-V positive power supply voltage
(1) I = Input, O = Output, S = Supply
(2) The high speed data ports incorporate 20-kΩpulldown resistors that are switched in when a port is not selected and switched out
when the port is selected.
Copyright © 2023 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: HD3SS213
HD3SS213
www.ti.com.cn
ZHCSBL2C –DECEMBER 2016 –REVISED JANUARY 2021
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
–0.5
–0.5
–0.5
MAX
UNIT
(2)
Supply voltage, VDD
4
4
V
Differential I/O
Voltage
V
Control pin
VDD + 0.5
Continuous power dissipation
Operating free-air temperature, TA
Storage temperature, Tstg
See 节6.4
105
150
°C
°C
–40
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values, except differential voltages, are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD) Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Typical values for all parameters are at VCC = 3.3 V and TA = 25°C (unless otherwise noted). All temperature limits are
specified by design.
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX UNIT
VDD
VIH
Supply voltage
3
3.3
3.6
V
V
Control pins and signal pins (Dx_SEL,
AUX_SEL, OE, HPDx)
Input high voltage
Input mid level voltage
Input low voltage
2
VDD
VDD/2
–300 mV
VDD/2
+ 300 mV
VIM
AUX_SEL pin
VDD/2
V
V
Control pins and signal pins (Dx_SEL,
AUX_SEL, OE, HPDx)
VIL
0.8
1.8
2
–0.1
Differential voltage
(Dx, AUXx)
VI/O_Diff
Switch I/O differential voltage
Switch I/O common-mode voltage
Switch I/O common-mode voltage
VDD = 3.6 V, VIN = VDD
0
0
0
VPP
V
Dx switching I/O common-
mode voltage
VI/O_CM
AUXx switching I/O common-
mode voltage
3.6
1
V
Input high current
(Dx_SEL, AUX_SEL)
IIH
IIM
IIL
µA
µA
µA
µA
Input mid level current
(AUX_SEL)
VDD = 3.6V, VIN = VDD/2
1
Input low current
(Dx_SEL, AUX_SEL)
VDD = 3.6 V, VIN = GND
1
Leakage current
(Dx_SEL, AUX_SEL)
VDD = 3.3 V, VI = 2 V, OE = 3.3 V
1
VDD = 3.3 V, VI = 2 V, OE = 3.3 V,
Dx_SEL = 3.3 V
ILK
1
Leakage current (HPDx)
µA
VDD = 3.3 V, VI = 2 V, OE = 3.3 V,
Dx_SEL = GND
1
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: HD3SS213
HD3SS213
www.ti.com.cn
ZHCSBL2C –DECEMBER 2016 –REVISED JANUARY 2021
Typical values for all parameters are at VCC = 3.3 V and TA = 25°C (unless otherwise noted). All temperature limits are
specified by design.
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX UNIT
Ioff
Device shut down current
VDD = 3.6 V, OE = GND
2.5
1
µA
VDD = 3.6 V,
Dx_SEL or AUX_SEL = VDD or GND
IDD
Supply current
0.6
mA
DA, DB, DC HIGH SPEED SIGNAL PATH
CON
Outputs ON capacitance
Outputs OFF capacitance
VI = 0 V, outputs open, switch ON
VI = 0 V, outputs open, switch OFF
1.5
1
pF
pF
COFF
VDD = 3.3 V, VCM = 0.5 V to 1.5 V,
IO = –40 mA
RON
ON resistance
8
12
Ω
Ω
Ω
ON resistance match between VDD = 3.3 V, 0.5 V ≤VI ≤1.2V,
1.5
ΔRON
RFLAT_ON
pairs of the same channel
IO = –40 mA
ON resistance flatness,
1.3
VDD = 3.3 V, 0.5 V ≤VI ≤1.2 V
RON(max) –RON(min)
AUXx, DDC SIGNAL PATH
CON
Outputs ON capacitance
Outputs OFF capacitance
VI = 0 V, outputs open, switch ON
VI = 0 V, outputs open, switch OFF
9
3
pF
pF
COFF
VDD = 3.3 V, VCM = 0 V –VDD, IO = –8
mA
RON(AUX) ON resistance
6
10
30
Ω
Ω
RON(DDC) ON resistance on DDC channel
20
VDD = 3.3 V, VCM = 0.4 V, IO = –3 mA
6.4 Thermal Information
HD3SS213
nFBGA (ZXH)
50 PIN
72.9
THERMAL METRIC
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
35.9
43.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.6
ψJT
42.9
ψJB
RθJC(bot)
—
6.5 Electrical Characteristics
over recommended operating conditions; RL and RSC = 50 Ω(unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
–17
–13
–50
–25
–1
MAX UNIT
1.35 GHz
2.7 GHz
RL
Dx differential return loss
dB
XTALK
OIRR
Dx differential crosstalk
2.7 GHz
dB
dB
Dx differential off-isolation
2.7 GHz
f = 1.35 GHz
f = 2.7 GHz
IL
Dx differential insertion loss
dB
–1.5
360
MHz
AUX –3-dB bandwidth
(1) For return loss, crosstalk, off-isolation, and insertion loss values, the data was collected on a Rogers material board with minimum
length traces on the input and output of the device under test.
Copyright © 2023 Texas Instruments Incorporated
6
Submit Document Feedback
Product Folder Links: HD3SS213
HD3SS213
www.ti.com.cn
ZHCSBL2C –DECEMBER 2016 –REVISED JANUARY 2021
6.6 Timing Requirements
over recommended operating conditions; RL and RSC = 50 Ω(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
tPD
Ton
Switch propagation delay
100
1
ps
µs
RSC and RL = 50 Ω, see 图6-2
Dx_SEL/AUX_SEL-to-switch Ton
(Data, AUX and DDC)
0.7
0.7
RSC and RL = 50 Ω, see 图6-1
RSC and RL = 50 Ω, see 图6-1
Dx_SEL/AUX_SEL-to-switch Toff
(Data, AUX and DDC)
Toff
1
µs
Ton
Dx_SEL/AUX_SEL-to-switch Ton (HPD)
Dx_SEL/AUX_SEL-to-switch Toff (HPD)
Inter-pair output skew (CH-CH)
0.7
0.7
1
1
µs
µs
ps
ps
RL = 50 Ω, see 图6-1
Toff
RL = 50 Ω, see 图6-1
TSK(O)
TSK(b-b)
50
5
RSC and RL = 1 kΩ, see 图6-2
RSC and RL = 1 kΩ, see 图6-2
Intra-pair output skew (bit-bit)
1
50%
Dx_SEL
90%
VOUT
10%
Toff
Ton
图6-1. Select to Switch Ton and Toff
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: HD3SS213
HD3SS213
www.ti.com.cn
ZHCSBL2C –DECEMBER 2016 –REVISED JANUARY 2021
Vcc
Rsc = 50 ꢀ
DAx/DBx(p)
DCx(p)
RLoad = 50 ꢀ
Rsc = 50 ꢀ
DCx(n)
DAx/DBx(n)
RLoad = 50 ꢀ
SEL
DAx/DBx(p)
50%
50%
DAx/DBx(n)
DCx(p)
50%
50%
DCx(n)
tP1
tP2
t4
t1
t2
t3
DCx(p)
50%
DCx(n)
DCy(p)
tSK(O)
DCy(n)
tPD = Max(tp1, tp2
)
tSK(O) = Difference between tPD for any two pairs of outputs
tSK(b-b) = 0.5 X |(t4 œ t3) + (t1 œ t2)|
Copyright © 2016, Texas Instruments Incorporated
图6-2. Propagation Delay and Skew
Copyright © 2023 Texas Instruments Incorporated
8
Submit Document Feedback
Product Folder Links: HD3SS213
HD3SS213
www.ti.com.cn
ZHCSBL2C –DECEMBER 2016 –REVISED JANUARY 2021
6.7 Typical Characteristics
-3
0.0145
# 10
7.8
7.6
7.4
7.2
7
0.014
0.0135
0.013
0.0125
0.012
0.0115
0.011
6.8
6.6
6.4
V = 3.6 V; AUXc to AUXa
V = 3.0 V; AUXc to AUXa
V = 3.6 V; AUXc to AUXb
V = 3.0 V; AUXc to AUXb
V = 3.6 V; AUXc to AUXa
V = 3.0 V; AUXc to AUXa
V = 3.6 V; AUXc to AUXb
V = 3.0 V; AUXc to AUXb
0.0105
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
Temperature (ºC)
Temperature (ºC)
图6-3. DxSEL to Switch Toff
图6-4. DxSEL to Switch Ton
0.0135
0.3
0.28
0.26
0.24
0.22
0.2
V = 3.6 V; AUXc to AUXa
V = 3.0 V; AUXc to AUXa
V = 3.6 V; AUXc to AUXb
V = 3.0 V; AUXc to AUXb
V = 3.6 V; AUXc to AUXa
V = 3.0 V; AUXc to AUXa
V = 3.6 V; AUXc to AUXb
V = 3.0 V; AUXc to AUXb
0.013
0.0125
0.012
0.0115
0.011
0.0105
0.01
0.0095
0.18
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
Temperature (ºC)
Temperature (ºC)
图6-5. OUTEN to Switch Toff
图6-6. OUTEN to Switch Ton
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: HD3SS213
HD3SS213
www.ti.com.cn
ZHCSBL2C –DECEMBER 2016 –REVISED JANUARY 2021
7 Detailed Description
7.1 Overview
The HD3SS213 device is a high-speed passive switch offered in an industry standard 50-pin nFBGA package.
The device is specified to operate from a single supply voltage of 3.3 V over the industrial temperature range of
–40°C to 105°C. The HD3SS213 is a generic 4-CH high-speed mux/demux type of switch that can be used for
routing high-speed signals between two different locations on a circuit board. The HD3SS213 also supports
several other high speed data protocols with a differential amplitude of < 1800 mVPP and a common-mode
voltage of < 2 V, as with USB 3.0 and DisplayPort 1.2. For display port applications, the HD3SS213 also
supports switching of both the auxiliary and hot plug detect signals.
The high speed port selection control inputs of the device, Dx_SEL and AUX_SEL pins can easily be controlled
by available GPIO pins within a system.
7.2 Functional Block Diagram
VDD
4
DAz(p)
SEL=0
4
DAz(n)
4
DCz(p)
(z = 0, 1, 2 or 3)
4
DCz(n)
4
DBz(p)
SEL=1
4
DBz(n)
SEL
Dx_SEL
SEL
SEL=0
SEL=1
HPDA
HPDB
HPDC
AUX_SEL
AUXA(p)
AUXA(n)
SEL2
SEL
AUXx(P) or DDCCLK_x
AUXx(n) or DDCDAT_x
AUXB(p)
AUXB(n)
AUXC(p)
AUXC(n)
DDCCLK_C
DDCDAT_C
DDCCLK_A
DDCDAT_A
DDCCLK_B
DDCDAT_B
OE
HD3SS213
GND
Copyright © 2016, Texas Instruments Incorporated
Copyright © 2023 Texas Instruments Incorporated
10
Submit Document Feedback
Product Folder Links: HD3SS213
HD3SS213
www.ti.com.cn
ZHCSBL2C –DECEMBER 2016 –REVISED JANUARY 2021
7.3 Feature Description
The HD3SS213 behaves as a two to one or one to two using high bandwidth pass gates (see 节 7.2). The input
ports are selected using the AUX_SEL and Dx_SEL pins which are shown in 表7-1.
表7-1. AUX/DDC Switch Control Logic
CONTROL LINES
SWITCHED I/O PINS
AUX_SEL
Dx_SEL
AUXA
To/From AUXC
AUXB
AUXC
DDCA
DDCB
DDCC
L
L
L
H
L
Z
To/From AUXA
Z
Z
Z
Z
Z
Z
Z
Z
Z
To/From AUXC
To/From AUXB
To/From DDCA
To/From DDCB
To/From AUXA
To/From AUXB
Z
H
H
M
M
Z
Z
To/From AUXC
H
L
Z
Z
Z
To/From AUXC
Z
To/From AUXC
Z
Z
To/From DDCC
Z
To/From DDCA
To/From DDCB
H
To/From AUXC
To/From DDCC
7.4 Device Functional Modes
The HD3SS213 can be operated in normal operation mode or in shut down mode. In normal operation, the
inputs ports of the HD3SS213 are routed to the output ports according to 表 7-1. In standby mode, the
HD3SS213 is disabled to enable power savings with a typical current consumption of 2.5 µA. The functional
mode is selected through the OE input pin with HIGH for normal operation and LOW for standby.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: HD3SS213
HD3SS213
www.ti.com.cn
ZHCSBL2C –DECEMBER 2016 –REVISED JANUARY 2021
8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
Many interfaces require AC coupling between the source and sink. The 0402 capacitors are the preferred option
to provide AC coupling, and the 0603 size capacitors also work. The 0805 size capacitors and C-packs must be
avoided. When placing AC coupling capacitors symmetric placement is best. A capacitor value of 0.1 µF is best
and the value must be match for the ± signal pair. There are several placement options for the AC coupling
capacitors. Because the switch requires a bias voltage, the capacitors must only be placed on one side of the
switch. If they are placed on both sides of the switch, a biasing voltage must be provided. A few placement
options are shown below.
In 图8-1, the coupling capacitors are placed on the source pair. In this situation, the switch is biased by the sink.
DAx(p)
DCx(p)
DAx(n)
GPU/
Source A
DCx(n)
Sink
Dx_SEL
Control
AUX_SEL
DBx(p)
DBx(n)
GPU/
Source B
HD3SS213
Copyright © 2016, Texas Instruments Incorporated
图8-1. Source Biased by the Sink
In 图 8-2, the coupling capacitors are placed between the switch and Sink. In this situation, the switch is biased
by the Source
Copyright © 2023 Texas Instruments Incorporated
12
Submit Document Feedback
Product Folder Links: HD3SS213
HD3SS213
www.ti.com.cn
ZHCSBL2C –DECEMBER 2016 –REVISED JANUARY 2021
DAx(p)
DAx(n)
DCx(p)
DCx(n)
Sink
Source
Dx_SEL
Control
AUX_SEL
DBx(n)
Sink
HD3SS213
Copyright © 2016, Texas Instruments Incorporated
图8-2. Switch Biased by the Source
8.2 Typical Applications
8.2.1 HD3SS213 AUX Channel in 2:1 Application
Vdd
100 K
Vbias
50 Ω
AUXa(n)
AUXa(p)
AUXc(n)
AUXc(p)
Source A
50 Ω
Vbias
Sink connector
100 K
Vbias
50 Ω
AUXb(n)
AUXb(p)
Source B
OE
50 Ω
Vbias
Dx_SEL
AUX_SEL
Control
HD3SS213 2:1
Copyright © 2016, Texas Instruments Incorporated
图8-3. HD3SS213 AUX Channel in 2:1 Application Schematic
8.2.1.1 Design Requirements
表8-1 lists the design parameters.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: HD3SS213
HD3SS213
www.ti.com.cn
ZHCSBL2C –DECEMBER 2016 –REVISED JANUARY 2021
表8-1. Design Parameters
PARAMETERS
Input voltage
VALUE
3.3 V
0.1 µF
Decoupling capacitors
AC capacitors(1)
75 nF to 200 nF AC capacitors
(1) DAx, AUXAx, AUXBx and DBx require AC capacitors. N lines require AC capacitors. Alternate
mode signals may or may not require AC capacitors.
8.2.1.2 Detailed Design Procedure
• Connect VDD and GND pins to the power and ground planes of the printed-circuit board with 0.1-µF bypass
capacitor
• Use VDD/2 logic level at AUX_SEL pin
• Use 3.3-V TTL/CMOS logic level at Dx_SEL to connect DAx to DCx
• Use GND logic level at Dx_SEL to connect DBx to DCx
• Use controlled-impedance transmission media for all the differential signals
• Ensure the received complimentary signals are with a differential amplitude of <1800 mVPP and a common-
mode voltage of <2 V
8.2.1.3 Application Curves
3.94
3.92
3.9
3.54
3.52
3.5
3.88
3.86
3.84
3.82
3.8
3.48
3.46
3.44
3.42
3.4
3.78
3.76
3.74
V = 3 V
V = 3 V
V = 3.6 V
V = 3.6 V
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
Temperature (ºC)
图8-5. Intra-Pair Skew Ports C to B (µs)
图8-4. Intra-Pair Skew Ports C to A (µs)
8
8
# 10
# 10
7.4
7.3
7.2
7.1
7
7.1
7
V = 3.6 V
V = 3 V
V = 3.6 V
V = 3 V
6.9
6.8
6.7
6.6
6.5
6.4
6.3
6.9
6.8
6.7
6.6
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
Temperature (ºC)
Temperature (ºC)
图8-7. Bandwidth Ports AUXc to AUXb
图8-6. Bandwidth Ports AUXc to AUXa
Copyright © 2023 Texas Instruments Incorporated
14
Submit Document Feedback
Product Folder Links: HD3SS213
HD3SS213
www.ti.com.cn
ZHCSBL2C –DECEMBER 2016 –REVISED JANUARY 2021
8.2.2 HD3SS213 AUX Channel in 1:2 Application
AUX channel is controlled by AUX_SEL. This pin configures the switch to route the incoming AUX signal to the
outgoing AUX path, when AUX_SEL = 0 the AUXA channel is routed to AUXC, when AUX_SEL = 1 the AUXB
channel is routed to AUXC.
Vdd
100 K
AUXa(n)
AUXc(n)
AUXa(p)
AUXc(p)
Sink connector A
100 K
Source
Vdd
100 K
AUXb(n)
AUXb(p)
Sink connector B
OE
100 K
Dx_SEL
AUX_SEL
Control
HD3SS213 1:2
Copyright © 2016, Texas Instruments Incorporated
图8-8. HD3SS213 AUX Channel in 1:2 Application Schematic
Power Supply Recommendations
The HD3SS213 requires 3.3 V power sources. 3.3-V supply (VDD) must have 0.1-µF bypass capacitors to VSS
(ground) for proper operation. TI recommends one capacitor for each power terminal. Place the capacitor as
close as possible to the terminal on the device and keep trace length to a minimum. Smaller value capacitors like
0.01 µF are also recommended on the supply terminals.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: HD3SS213
HD3SS213
www.ti.com.cn
ZHCSBL2C –DECEMBER 2016 –REVISED JANUARY 2021
9 Layout
9.1 Layout Guidelines
• Routing the high-speed differential signal traces on the top layer avoids the use of vias (and the introduction
of their inductances) and allows for clean interconnects from the DisplayPort connectors to the repeater
inputs and from the repeater output to the subsequent receiver circuit.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Decoupling capacitors must be placed next to each power terminal on the HD3SS213. Take care to minimize
the stub length of the race connecting the capacitor to the power pin.
• Avoid sharing vias between multiple decoupling capacitors.
• Place vias as close as possible to the decoupling capacitor solder pad.
• Widen VDD and/or GND planes to reduce effect if static and dynamic IR drop.
9.1.1 Differential Traces
Guidelines for routing PCB traces are necessary when trying to maintain signal integrity and lower EMI. Although
there seems to be an endless number of precautions, this section provides only a few main recommendations as
layout guidance.
1. Reduce intra-pair skew in a differential trace by introducing small meandering corrections at the point of
mismatch.
2. Reduce inter-pair skew, caused by component placement and IC pinouts, by making larger meandering
correction along the signal path. Use chamfered corners with a length-to-trace width ratio of between 3 and
5. The distance between bends must be 8 to 10 times the trace width
3. Use 45° bends instead of right-angle (90°) bends. Right-angle bends increase the effective trace width,
which changes the differential trace impedance creating large discontinuities. A 45° bends is seen as a
smaller discontinuity.
4. When routing around an object, route both trace of a pair in parallel. Splitting the traces changes the line-to-
line spacing, thus causing the differential impedance to change and discontinuities to occur
5. Place passive components within the signal path, such as source-matching resistors or AC coupling
capacitors, next to each other. Routing as in case a) creates wider trace spacing than in b). However, the
resulting discontinuity is limited to a far narrower area.
6. When routing traces next to a via or between an array of vias, make sure that the via clearance section does
not interrupt the path of the return current on the ground plane below
7. Avoid metal layers and traces underneath or between the pads off the DisplayPort connectors for better
impedance matching. Otherwise, they cause the differential impedance to drop below 75 Ωand fail the
board during TDR testing.
8. Use the smallest size possible for signal trace vias and DisplayPort connector pads as they have less impact
on the 100 Ωdifferential impedance. Large vias and pads can cause the impedance to drop below 85 Ω.
9. Use solid power and ground planes for 100 Ωimpedance control and minimum power noise.
10. For 100 Ωdifferential impedance use the smallest trace spacing possible, which is usually specified by the
PCB vendor.
11. Keep the trace length between the DisplayPort connector and the DisplayPort device as short as possible to
minimize attenuation.
12. Use good DisplayPort connectors whose impedances meet the specifications.
13. Place bulk capacitors (for example, 10 µF) close to power sources, such as voltage regulators or where the
power is supplied to the PCB.
14. Place smaller 0.1-µF or 0.01-µF capacitors at the device.
Copyright © 2023 Texas Instruments Incorporated
16
Submit Document Feedback
Product Folder Links: HD3SS213
HD3SS213
www.ti.com.cn
ZHCSBL2C –DECEMBER 2016 –REVISED JANUARY 2021
9.2 Layout Example
Copyright © 2016, Texas Instruments Incorporated
图9-1. HD3SS213 Layout Example
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: HD3SS213
HD3SS213
www.ti.com.cn
ZHCSBL2C –DECEMBER 2016 –REVISED JANUARY 2021
10 Device and Documentation Support
10.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.4 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
18
Submit Document Feedback
Product Folder Links: HD3SS213
PACKAGE OPTION ADDENDUM
www.ti.com
8-Apr-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
HD3SS213ZXHR
ACTIVE
NFBGA
ZXH
50
2500 RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 105
HD3SS213
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Mar-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
HD3SS213ZXHR
NFBGA
ZXH
50
2500
330.0
12.4
5.3
5.3
1.5
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Mar-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
NFBGA ZXH 50
SPQ
Length (mm) Width (mm) Height (mm)
336.6 336.6 31.8
HD3SS213ZXHR
2500
Pack Materials-Page 2
PACKAGE OUTLINE
NFBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
ZXH0050A
A
5.1
4.9
B
BALL A1 CORNER
5.1
4.9
C
1 MAX
SEATING PLANE
0.08 C
0.25
0.15
BALL TYP
(0.5) TYP
4 TYP
J
(0.5) TYP
H
G
F
SYMM
4
TYP
E
D
C
0.35
50X Ø
B
A
0.25
0.15
0.05
C A B
C
0.5 TYP
1
2
3
4
5
6
7
8
9
0.5 TYP
SYMM
4225134/A 08/2019
NOTES:
NanoFree is a trademark of Texas Instruments.
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
NFBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
ZXH0050A
(0.5) TYP
3
1
2
4
5
6
7
8
9
A
B
(0.5) TYP
C
D
E
F
SYMM
50X (Ø0.25)
G
H
J
SYMM
LAND PATTERN EXAMPLE
SCALE: 20X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
EXPOSED
METAL
(Ø 0.25)
SOLDER MASK
OPENING
EXPOSED
METAL
(Ø 0.25)
METAL
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON- SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4225134/A 08/2019
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. Refer to Texas Instruments
Literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
NFBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
ZXH0050A
(0.5) TYP
3
1
2
4
5
6
7
8
9
A
B
(0.5) TYP
C
D
E
F
METAL
TYP
SYMM
(R0.05) TYP
G
H
J
50X ( 0.25)
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.100 mm THICK STENCIL
SCALE: 20X
4225134/A 08/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
相关型号：
HD3SS215IRTQR
支持 DDC/AUX 开关的 6Gbps HDMI 2.0/5.4Gbps DisplayPort 1.2a 1:2/2:1 差动多路复用器 | RTQ | 56 | -40 to 85
TI
HD3SS215IRTQT
支持 DDC/AUX 开关的 6Gbps HDMI 2.0/5.4Gbps DisplayPort 1.2a 1:2/2:1 差动多路复用器 | RTQ | 56 | -40 to 85
TI
©2020 ICPDF网 联系我们和版权申明