HD3SS214_V01 [TI]
HD3SS214 8.1 Gbps DisplayPort 1.4 2:1/1:2 Differential Switch;
| 型号： | HD3SS214_V01 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HD3SS214 8.1 Gbps DisplayPort 1.4 2:1/1:2 Differential Switch |
| 文件： | 总32页 (文件大小：1967K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HD3SS214
SLAS907C – DECEMBER 2015 – REVISED DECEMBER 2020
HD3SS214 8.1 Gbps DisplayPort 1.4 2:1/1:2 Differential Switch
1 Features
3 Description
•
•
Compatible with DisplayPort 1.4 electrical standard
2:1 and 1:2 switching supporting data rates up to
8.1 Gbps
HD3SS214 is a high-speed passive switch capable of
switching two full DisplayPort 4 lane ports from one of
two sources to one target location in an application. It
will also switch one source to one of two sinks. For
DisplayPort Applications, the HD3SS214 supports
switching of the Auxiliary (AUX), Display Data
Channel (DDC) and Hot Plug Detect (HPD) signals in
the nFBGA ZXH package.
•
•
•
•
•
Supports HPD, AUX and DDC switching
Wide differential BW of 8 GHz
Excellent dynamic electrical characteristics
VDD operating range 3.3 V ±10%
Extended industrial temperature range of
-40°C to 105°C
5 mm x 5 mm, 50-ball nFBGA package
Output enable (OE) pin disables switch to save
power
One typical application would be a mother board that
includes two GPUs that need to drive one DisplayPort
sink. The GPU is selected by the Dx_SEL pin.
Another application is when one source needs to
switch between one of two sinks, example would be a
side connector and a docking station connector. The
switching is controlled using the Dx_SEL and
AUX_SEL pins. The HD3SS214 operates from a
single supply voltage of 3.3 V over extended industrial
temperature range -40°C to 105°C.
•
•
•
Power consumption
– Active < 2 mW typical
– Standby < 10 µW typical (when OE = L)
2 Applications
•
•
•
PC & notebooks
Tablets
Connected peripherals & printers
Device Information (1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
HD3SS214
nFBGA (50)
5.00 mm x 5.00 mm
HD3SS214I
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
DAx(p)
DCx(p)
DAx(n)
DCx(n)
AUXAx
Source A
DDCA
DP Sink
DDCC
HPDA
AUXCx
HPDC
AUXBx
DDCB
HPDB
OE
Dx_SEL
Source B
Control
AUX_SEL
DBx(p)
DBx(n)
HD3SS214 2:1
Copyright © 2016, Texas Instruments Incorporated
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
HD3SS214
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SLAS907C – DECEMBER 2015 – REVISED DECEMBER 2020
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings (1) (2) ...............................5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................7
6.6 Electrical Characteristics, Device Parameters............7
6.7 Timing Requirements..................................................8
6.8 Typical Characteristics................................................8
7 Detailed Description........................................................9
7.1 Overview.....................................................................9
7.2 Functional Block Diagram.........................................10
7.3 Feature Description...................................................10
7.4 Device Functional Modes..........................................11
8 Application and Implementation..................................12
8.1 Application Information............................................. 12
8.2 Typical Application.................................................... 12
9 Power Supply Recommendations................................17
10 Layout...........................................................................18
10.1 Layout Guidelines................................................... 18
10.2 Layout Example...................................................... 19
11 Device and Documentation Support..........................21
11.1 Device Support........................................................21
11.2 Receiving Notification of Documentation Updates..21
11.3 Community Resources............................................21
11.4 Trademarks............................................................. 21
12 Mechanical, Packaging, and Orderable
Information.................................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from , to , (from Revision B (June 2017) to Revision C (December 2020))
Page
•
•
Changed Title and Feature From: DisplayPort 1.3 To: DisplayPort 1.4..............................................................1
NOTE: The device in the MicroStar Jr. BGA packaging were redesigned using a laminate nFBGA package.
This nFBGA package offers datasheet-equivalent electrical performance. It is also footprint equivalent to the
MicroStar Jr. BGA. The new package designator in place of the discontinued package designator will be
updated throughout the datasheet......................................................................................................................1
Changed u*jr BGA to nFBGA............................................................................................................................. 1
Changed u*jr ZQE to nFBGA ZXH..................................................................................................................... 3
Changed DC2(p) to DC2(n) in Pin Functions..................................................................................................... 3
Changed DC2(n) to DC2(p) in Pin Functions..................................................................................................... 3
Changed u*jr ZQE to nFBGA ZXH. Updated thermal data.................................................................................5
•
•
•
•
•
Changes from Revision A (July 2016) to Revision B (June 2017)
Page
•
Changed Title and Feature From: DisplayPort 1.3 To: DisplayPort 1.4..............................................................1
Changes from Revision * (December 2015) to Revision A (July 2016)
Page
•
•
Changed DC2(p) to DC2(n) in Pin Functions..................................................................................................... 3
Changed DC2(n) to DC2(p) in Pin Functions..................................................................................................... 3
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5 Pin Configuration and Functions
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Dx_SEL
VDD
DA0(n)
DA1(n)
DA2(n)
DA3(p)
DA3(n)
DC0(n)
DC0(p)
AUX_SEL
DC1(p)
DC2(p)
DC3(p)
GND
GND
DA0(p)
DA1(p)
DA2(p)
OE
DB0(p)
GND
DB0(n)
DC1(n)
DC2(n)
DC3(n)
DB1(p)
DB1(n)
DB2(n)
DB3(n)
DB2(p)
DB3(p)
G
H
J
GND
AUXC(n)
HPDC
AUXC(p)
HPDA
HPDB
GND
VDD
DDCCLK_B
DDCDAT_B
AUXB(p)
AUXB(n)
GND
DDCCLK_A
DDCDAT_A
AUXA(p)
DDCCLK_C
DDCDAT_C
AUXA(n)
Not to scale
Figure 5-1. ZXH Package 50-ball (nFBGA) Top View
Pin Functions
PIN
I/O
DESCRIPTION(1)
NO.
A1
NAME
Dx_SEL
VDD
Control I
Supply
I/O
High Speed Port Selection Control Pins
A2,J4
A4
3.3 V Positive power supply voltage
DA0(n)
DA1(n)
DA2(n)
DA3(p)
DA3(n)
DC0(n)
Port A, Channel 0, High Speed Negative Signal
Port A, Channel 1, High Speed Negative Signal
Port A, Channel 2, High Speed Negative Signal
Port A, Channel 3, High Speed Positive Signal
Port A, Channel 3, High Speed Negative Signal
Port C, Channel 0, High Speed Negative Signal
A5
I/O
A6
I/O
A8
I/O
A9
I/O
B1
I/O
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Pin Functions (continued)
PIN
I/O
DESCRIPTION(1)
NO.
NAME
B2
DC0(p)
I/O
Port C, Channel 0, High Speed Positive Signal
B3,C8,G2,G
8,H4,H7
GND
Supply
Ground
B4
B5
B6
DA0(p)
DA1(p)
DA2(p)
I/O
I/O
I/O
Port A, Channel 0, High Speed Positive Signal
Port A, Channel 1, High Speed Positive Signal
Port A, Channel 2, High Speed Positive Signal
Output Enable:
B7
OE
I
OE = VIH: Normal Operation
OE = VIL: Standby Mode
B8
B9
C2
D1
D2
D8
D9
E1
E2
E8
E9
F1
F2
F8
F9
H1
H2
H3
H6
H5
H8
H9
J1
DB0(p)
DB0(n)
AUX_SEL
DC1(n)
DC1(p)
DB1(p)
DB1(n)
DC2(n)
DC2(p)
DB2(p)
DB2(n)
DC3(n)
DC3(p)
DB3(p)
DB3(n)
AUXC(n)
AUXC(p)
HPDB
I/O
I/O
Control I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Port B, Channel 0, High Speed Positive Signal
Port B, Channel 0, High Speed Negative Signal
AUX/DDC Selection Control Pin in Conjunction with Dx_SEL Pin
Port C, Channel 1, High Speed Negative Signal
Port C, Channel 1, High Speed Positive Signal
Port B, Channel 1, High Speed Positive Signal
Port B, Channel 1, High Speed Negative Signal
Port C, Channel 2, High Speed Negative Signal
Port C, Channel 2, High Speed Positive Signal
Port B, Channel 2, High Speed Positive Signal
Port B, Channel 2, High Speed Negative Signal
Port C, Channel 3, High Speed Negative Signal
Port C, Channel 3, High Speed Positive Signal
Port B, Channel 3, High Speed Positive Signal
Port B, Channel 3, High Speed Negative Signal
Port C AUX Negative Signal
Port C AUX Positive Signal
Port B Hot Plug Detect
AUXB(p)
Port B AUX Positive Signal
DDCCLK_B
DDCCLK_A
AUXA(p)
Port B DDC Clock Signal
Port A DDC Clock Signal
Port A AUX Positive Signal
HPDC
Port C Hot Plug Detect
J2
HPDA
Port A Hot Plug Detect
J3
DDCCLK_C
DDCDAT_B
AUXB(n)
Port C DDC Clock Signal
J5
Port B DDC Data Signal
J6
Port B AUX Negative Signal
J7
DDCDAT_C
DDCDAT_A
AUXA(n)
Port C DDC Data Signal
J8
Port A DDC Data Signal
J9
Port A AUX Negative Signal
(1) The high speed data ports incorporate 20-kΩ pull down resistors that are switched in when a port is not selected and switched out
when the port is selected.
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6 Specifications
6.1 Absolute Maximum Ratings (1) (2)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX
UNIT
Supply voltage range(3)
Voltage range
VDD
4
4
V
Differential I/O
Control pin
V
VDD + 0.5
See Section 6.4
Continuous power dissipation
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-B
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Typical values for all parameters are at VCC = 3.3 V and TA = 25°C. All temperature limits are specified by design.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD
VIH
Supply voltage
3
3.3
3.6
V
V
Control Pins, Signal Pins
(Dx_SEL, AUX_SEL, MODE, OE)
Input high voltage
Input mid level voltage
Input low voltage
2
VDD
VDD/2 -300
mV
VDD/2 -300
mV
VIM
AUX_SEL Pin
VDD/2
V
V
Control Pins, Signal Pins
(Dx_SEL, AUX_SEL, MODE, OE)
VIL
-0.1
0.8
VI/O_Diff
Differential voltage (Dx, AUXx)
Switch I/O diff voltage
0
0
1.8
2
Vpp
V
Dx switching I/O Common mode voltage
VI/O_CM
Switch I/O common mode voltage
AUXx (1) switching I/O Common mode
voltage
0
3.6
HD3SS214
HD3SS214I
0
70
°C
°C
Operating free-air temperature
–40
105
6.4 Thermal Information
HD3SS214
ZXH (nFBGA)
50 PINS
72.9
THERMAL METRIC(1)
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
35.9
43.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
1.6
ψJB
42.9
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HD3SS214
ZXH (nFBGA)
50 PINS
THERMAL METRIC(1)
UNIT
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
µA
IIH
IIM
IIL
Input High Current (Dx_SEL, AUX_SEL)
Input Mid Current (AUX_SEL)
VDD = 3.6 V, VIN = VDD
1
1
1
1
VDD = 3.6 V, VIN = VDD/2
VDD = 3.6 V, VIN =GND
µA
Input Low Current (Dx_SEL, AUX_SEL)
Leakage Current (Dx_SEL, AUX_SEL)
µA
VDD = 3.3 V, VIN = 2 V, OE = 3.3 V
µA
VDD = 3.3 V, VIN = 2 V, OE = 3.3 V;
Dx_SEL = 3.3 V
Leakage Current (HPDx)
Leakage Current (HPDx)
1
1
µA
µA
ILKG
VDD = 3.3 V, VIN = 2 V, OE = 3.3 V;
Dx_SEL = GND
IOFF
IDD
Device Shut Down Current
Supply Current
VDD = 3.6 V, OE = GND
2.5
1
µA
VDD = 3.6 V, Dx_SEL/AUX_SEL = VDD/GND
0.6
mA
DA, DB, DC HIGH SPEED SIGNAL PATH
CON
COFF
RON
Outputs ON Capacitance
Outputs OFF Capacitance
ON resistance
VIN = 0 V, Outputs Open, Switch ON
VIN = 0 V, Outputs Open, Switch OFF
VDD = 3.3 V, VCM = 0.5 V – 1.5 V, IO = -40 mA
0.6
0.8
8
pF
pF
Ω
12
On resistance match between pairs of the
same channel
VDD = 3.3 V, VCM = 0.5 V ≤ VIN ≤ 1.2 V,
IO = -40 mA
ΔRON
1.5
Ω
Ω
On resistance flatness
(RON(MAX) – RON(MAIN)
R(FLAT_ON)
VDD = 3.3 V, VCM = 0.5 V ≤ VIN ≤ 1.2 V
1.3
AUXX, DDC, SIGNAL PATH
RON(AUX) ON resistance on AUX channel
RON(DDC) ON resistance on DDC channel
VDD = 3.3 V, VCM = 0 V – VDD, IO = -8 mA
VDD = 3.3 V, VCM = 0.4 V, IO = -3 mA
6
10
30
Ω
Ω
20
6.6 Electrical Characteristics, Device Parameters
over operating free-air temperature range (unless otherwise noted)
PARAMETER(1)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
dB
1.35 GHz
2.7 GHz
–0.9
–1.4
–1.6
–17
–13
–11
IL
Dx Differential Insertion Loss
dB
4.05 GHz
1.35 GHz
2.7 GHz
dB
dB
RL
Dx Differential Return Loss
Dx Differential Crosstalk
dB
4.05 GHz
1.35 GHz
2.7 GHz
dB
dB
XTALK
–53
–47
dB
4.05 GHz
1.35 GHz
2.7 GHz
dB
dB
OIRR
Dx Differential Off-Isolation
AUX Bandwidth
–26
–24
500
dB
4.05 GHz
dB
MHz
(1) For Return Loss, Crosstalk, Off-Isolation, and Insertion Loss values the data was collected on a Rogers material board with minimum
length traces on the input and output of the device under test.
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6.7 Timing Requirements
PARAMETER
TEST CONDITIONS
RSC and RL = 50 Ω
MIN
TYP MAX UNIT
tPD
ton
Switch propagation delay
100
1
ps
Dx_SEL/AUX_SEL–to-Switch ton (Data and AUX
and DDC)
0.7
0.7
RSC and RL = 50 Ω
µs
Dx_SEL/AUX_SEL–to-Switch toff (Data and AUX
and DDC)
toff
1
ton
Dx_SEL/AUX_SEL –to-Switch ton (HPD)
Dx_SEL/AUX_SEL –to-Switch toff (HPD)
Inter-Pair Output Skew (CH-CH)
0.7
0.7
1
1
RL = 1 kΩ
µs
toff
tSK(O)
tSK(b-b)
30
5
ps
ps
RSC and RL = 50 kΩ
Intra-Pair Skew added (Bit-Bit)
1
6.8 Typical Characteristics
0
-5
0
-5
-10
-15
-20
-25
-30
-10
-15
-20
-25
-30
1E+8
1E+9
Frequency (Hz)
1E+10
1E+8
1E+9
Frequency (Hz)
1E+10
D002
D001
Figure 6-2. Return Loss
Figure 6-1. Insertion Loss and –3 dB Bandwidth
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
1E+8
1E+9
Frequency (Hz)
1E+10
D003
Figure 6-3. Off Isolation
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7 Detailed Description
7.1 Overview
The HD3SS214 is an analog, differential passive switch that can work for any high speed interface applications,
as long as it is biased at a common mode voltage range of 0 V to 2 V and has differential signaling with
differential amplitude up to 1800 mVpp.
Note
HD3SS214 MUX does not provide common mode biasing for the channel. Therefore, it is required that
the device is biased from either side for all active channels.
In high-speed applications and data paths, signal integrity is an important concern. The switch offers excellent
dynamic performance such as high isolation, crosstalk immunity, and minimal bit-bit skew. These characteristics
allow the device to function seamlessly in the system without compromising signal integrity. The 2:1/1:2, mux/de-
mux device operates with ports A or B switched to port C, or port C switched to either port A or B. This flexibility
allows an application to select between one of two Sources on ports A and B and send the output to the sink on
port C. Similarly, a Source on port C can select between one of two Sink devices on ports A and B to send the
data.
The HPD and data signals are both switched through the Dx_SEL pin. AUX and DDC are controlled with
AUX_SEL and Dx_SEL.
With an OE control pin, the HD3SS214 is operational, with low active current, when this pin is high. When OE is
pulled low, the device goes into standby mode and draws very little current in order to save power consumption
in the application.
HD3SS214 high speed MUX channels have independent adaptive common mode tracking allowing four data
paths to have different common mode voltage, simplifying system implementation and avoid inter-op issues.
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7.2 Functional Block Diagram
VDD
4
4
DAz(p)
DAz(n)
SEL=0
4
4
DCz(p)
DCz(n)
(z = 0, 1, 2 or 3)
4
4
DBz(p)
DBz(n)
SEL=1
SEL
Dx_SEL
SEL
HPDA
HPDB
SEL=0
SEL=1
HPDC
AUX_SEL
SEL2
AUXA(p)
AUXA(n)
SEL
AUXx(P) or DDCCLK_x
AUXx(n) or DDCDAT_x
AUXB(p)
AUXB(n)
AUXC(p)
AUXC(n)
DDCCLK_C
DDCDAT_C
DDCCLK_A
DDCDAT_A
DDCCLK_B
DDCDAT_B
OE
HD3SS214
GND
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7.3 Feature Description
7.3.1 High Speed Switching
The HD3SS214 supports switching of 8.1 Gbps data rates. The high speed mux is designed with a wide –3dB
differential bandwidth of 8 GHz and industry leading dynamic characteristics. All of these attributes help maintain
signal integrity in the application. Each high speed port incorporates 20-kΩ pull down resistors that are switched
in when the port is not selected and switched out when the port is selected. Additionally, high speed differential
pairs at port C have internal 20-kΩ resistor between positive and negative pins
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7.3.2 HPD, AUX, and DDC Switching
HPD, AUX, and DDC switching is supported through the HD3SS214. This enables the device to work in multiple
application scenarios within multiple electrical standards. The AUXA/B and DDCA/B lines can both be switched
to the AUXC port. This feature supports DP++ or AUX only adapters. For HDMI applications, the DDC channels
are switched to the DDC_C port only and the AUX channel can remain active or the end user can make it float.
7.3.3 Output Enable and Power Savings
The HD3SS214 has two power modes, active/normal operating mode, and standby mode. During standby mode,
the device consumes very little current to save the maximum power. To enter standby mode, the OE control pin
is pulled low and must remain low. For active/normal operation, the OE control pin should be pulled high to VDD
through a resistor.
7.4 Device Functional Modes
The HD3SS214 behaves as a two to one or one to two using high bandwidth pass gates. The input ports are
selected using the Dx_SEL pin and Dx_SEL pin which are shown in Table 7-1.
Table 7-1. AUX/DDC Switch Control Logic (2)
CONTROL LINES
SWITCHED I/O PINS(1)
AUX_SE
Dx_SEL
L
DCz(p) Pin
z = 0, 1 ,2 or 3
DCz(n) Pin
z = 0, 1 ,2 or 3
HPDC Pin
HPDA
HPDB
HPDA
HPDB
HPDA
HPDB
AUXA
AUXB
AUXC
DDCA
DDCB
DDCC
To/From
AUXA
L
L
L
H
L
DAz(p)
DBz(p)
DAz(p)
DBz(p)
DAz(p)
DBz(p)
DAz(n)
DBz(n)
DAz(n)
DBz(n)
DAz(n)
DBz(p)
To/From AUXC
Z
Z
Z
Z
Z
To/From
AUXB
Z
To/From AUXC
Z
Z
To/From
DDCA
To/From
AUXC
H
Z
Z
Z
Z
To/From
DDCB
H
H
L
Z
Z
Z
To/From AUXC
Z
Z
To/From
AUXA
To/From
DDCC
M(1)
M(1)
To/From AUXC
Z
Z
To/From DDCA
To/From
AUXB
H
To/From AUXC
Z
To/From DDCC To/From DDCB
(1) Z = High Impedance
(2) OE pin - For normal operation, drive OE high. Driving the OE pin low will disable the switch. Note: The ports which are not selected by
the control lines will be in high impedance status.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The HD3SS214 is a 1:2/2:1 DP switch that supports 8.1 Gbps data rates and DP++. This switch is bi-directional,
so it can be used to switch two inputs to one output or one input to one of two outputs. In addition to main link
switching, this switch also supports AUX and DDC switching, which simplifies DP++ implementation. 3.3 V is
used to supply power to the switch.
8.2 Typical Application
8.2.1 Dual GPU With Docking Station Support
Many consumer devices require multiple video sources to be routed to multiple output sinks. One example of
these devices is a dual-GPU laptop with docking station support. The laptop has two video sources that can be
chosen: one low-power integrated GPU and one high-power discrete GPU. The video stream from one of these
sources needs to be routed to one of two outputs: the docking station port or the laptop DisplayPort video port.
In order to support this functionality, a high data rate, multi-input/multi-output switch system is required.
Figure 8-1. Dual GPU with Docking Station Support
8.2.2 Design Requirements
For this design example, use the parameters shown in Table 8-1.
Table 8-1. Design Parameters
PARAMETER
VDD
VALUE
3.3 V
DP x1
DP x2
M
Source
Sink
AUX_SEL Level
DP++ Support
No
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8.2.3 Detailed Design Procedure
8.2.3.1 DP Inputs
The HD3SS214 is used as a 1:2 DP switch, the DCx[p/n] are connected to the GPU; the outputs (DAx[p/n] and
DBx[p/n] ) are routed to the ++DP connectors of the platform.
Note
This application information is only to show the principles of operation of the HD3SS214 and not the
requirements of all the implementation. Many implementations will require external circuitry to
compensate for signal loss (like a DP re-driver).
8.2.3.2 Source Selection Interface
Two control pins on the HD3SS214 are responsible for selecting the incoming DP signal: Dx_SEL and
AUX_SEL. Dx_SEL controls which high speed ports are selected. A low signal on Dx_SEL corresponds to Port
A routed to Port C and a high signal corresponds to Port B routed to Port C. A slide switch is used to select the
level for this signal. In an embedded application, this switch can be replaced by a GPIO signal from a
microcontroller.
AUX channel is controlled by AUX_SEL. This pin configures the switch to route the incoming AUX signal to the
outgoing AUX path, when AUX_SEL = 0 the AUXA channel will be routed to AUXC, when AUX_SEL = 1 the
AUXB channel will be routed to AUXC. Figure 8-2 shows the selection circuitry.
Figure 8-2. AUX_SEL Schematic
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8.2.4 DP++ Support
The HD3SS214 supports DP++ implementations.
Figure 8-3. DP++ Docking Station Support
8.2.4.1 Design Requirements
For this example, use the parameters shown in Table 8-2
Table 8-2. Design Parameters
PARAMETER
VALUE
3.3 V
DP x1
DP x2
M
VDD
Source
Sink
AUX_SEL Level
DP++ Support
Yes
8.2.4.2 Detailed Design Procedure
For applications involving DP++ support, following design procedures must be followed.
8.2.4.2.1 AUX and DDC Switching
The HD3SS214 supports DP++ implementations.
According to the DP++ standard, the DP AUX line is repurposed as the DDC line when HDMI signals are being
transmitted. Unfortunately, the AUX and DDC signals have very different electrical requirements. AUX is a
differential signal that requires AC coupling, while DDC uses I2C protocol, which needs pull-up resistors. As a
result, these signals are electrically incompatible if extra circuitry is not designed to accommodate the signals.
The source selection design block uses conditional pull-up resistors to support AUX and DDC signals on a
unified line.Figure 8-4 illustrates the circuit that was used to enable the signal.
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Figure 8-4. Combined AUX/DDC Circuitry
In this circuit, the unified AUX/DDC lines are split into two branches prior to entering the HD3SS214. One branch
is AC coupled and is connected to the AUX inputs of the HD3SS214. The other is connected to the DDC inputs.
AUX_SEL is configured so that the HD3SS214 transmits both of these through the switch. A conditional pull-up
resistor system is connected to the DDC branch of the line. This resistor system will enable the pull-up resistors
on the line only when HDMI/DVI signals are being transmitted, that is, when AUX is transmitting DDC signals.
This prevents the AUX signal from being interfered with during standard DP mode and enables I2C DDC
signaling during HDMI/DVI mode
The control input for the conditional pull-up circuit is the Cable Adaptor Detect (CAD) signal. When an HDMI or
DVI sink is being used, this signal goes high, which indicates that the AUX line must transmit the DDC signal.
When a standard DP sink is being used, the CAD signal goes low, indicating that the AUX line is transmitting its
normal AUX signal. In this way, the CAD signal indicates when the AUX/DDC lines need pull-up resistors and
when they do not.
The conditional pull-up circuit consists of an inverter, a p-type MOSFET, and two pull-up resistors. The FET acts
as a switch between the pull-up resistors. When CAD is high (indicating that pull-up resistors are needed), the
inverter outputs a low signal, which brings the Vgs of the FET below the FET’s threshold voltage. Pulling Vgs
below the threshold voltage turns the p-type FET on. When the FET turns on, it connects the AUX line’s pull-up
resistors to VCC, which enables them.
The chosen inverter is a Texas Instruments SN74AHC1G04 inverter, which has very fast response times and
very good electrical characteristics for VOH and VOL. The MOSFET chosen is a Texas Instruments TPS1120
(SLVS080). This device has a convenient dual transistor package, an ideal threshold voltage and very low drain-
to-source resistance when on. Together, these two devices have a desirable noise margin of 0.9 V.
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8.2.4.2.2 CONFIG1 and CONFIG2 Routing
The HD3SS214 only routes the high speed main link, AUX, and Hot Plug Detect (HPD) lines, which means
CONFIG1 and CONFIG2 lines need to be routed externally. This is necessary because these lines are important
for DP++ as CONFIG1 carries the CAD signal.
A Texas Instruments TS3USB221 (SCDS263) is used to route these signals. It is a 2:1/1:2 USB switch that
operates similarly to the HD3SS214. Each port has two inputs, so it is ideal for the CONFIG signals. SRC_SEL
is used to select which source the CONFIG signals are from. The circuit for routing these signals can be seen in
Figure 8-5.
Figure 8-5. CONFIG Signal Routing
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9 Power Supply Recommendations
There is no power supply sequence required for HD3SS214. However, it is recommended that OE is asserted
high after device supply VDD is stable and in spec. It is also recommended that ample decoupling capacitors are
placed at the device VCC near the pin.
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10 Layout
10.1 Layout Guidelines
10.1.1 Layer Stack
Routing the high-speed differential signal traces on the top layer avoids the use of vias (and the introduction of
their inductances) and allows for clean interconnects from the DisplayPort connectors to the repeater inputs and
from the repeater output to the subsequent receiver circuit.
Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance.
Routing the fast-edged control signals on the bottom layer by prevents them from cross-talking into the high-
speed signal traces and minimizes EMI.
If the receiver requires a supply voltage different from the one of the repeater, add a second power/ground plane
system to the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from
warping. Also, the power and ground plane of each power system can be placed closer together, thus increasing
the high-frequency bypass capacitance significantly. Finally, a second power/ground system provides added
isolation between the signal layers.
Layer 1:
High-speed, differential
signal traces
Layer 1:
High-speed, differential
signal traces
5 to 10 mils
20 to 40 mils
5 to 10 mils
Layer 2:
Layer 3:
Ground
Layer 2:
Ground plane
V
V
CC1
CC2
Layer 4:
Layer 5:
Layer 3: Power plane
Ground
Layer 4:
Low-frequency,
single-ended traces
Layer 6:
Low-frequency,
single-ended traces
Figure 10-1. Recommended 4- or 6- Layer (0.062") Stack for a Receiver PCB Design
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10.1.2 Differential Traces
Guidelines for routing PCB traces are necessary when trying to maintain signal integrity and lower EMI. Although
there seems to be an endless number of precautions to be taken, this section provides only a few main
recommendations as layout guidance.
1. Reduce intra-pair skew in a differential trace by introducing small meandering corrections at the point of
mismatch.
2. Reduce inter-pair skew, caused by component placement and IC pinouts, by making larger meandering
correction along the signal path. Use chamfered corners with a length-to-trace width ratio of between 3 and 5.
The distance between bends should be 8 to 10 times the trace width.
3. Use 45 degree bends (chamfered corners), instead of right-angle (90°) bends. Right-angle bends increase
the effective trace width, which changes the differential trace impedance creating large discontinuities. A 45o
bends is seen as a smaller discontinuity.
4. When routing around an object, route both trace of a pair in parallel. Splitting the traces changes the line-to-
line spacing, thus causing the differential impedance to change and discontinuities to occur.
5. Place passive components within the signal path, such as source-matching resistors or ac-coupling
capacitors, next to each other. Routing as in case a) creates wider trace spacing than in b), the resulting
discontinuity, however, is limited to a far narrower area.
6. When routing traces next to a via or between an array of vias, make sure that the via clearance section does
not interrupt the path of the return current on the ground plane below.
7. Avoid metal layers and traces underneath or between the pads off the DisplayPort connectors for better
impedance matching. Otherwise they will cause the differential impedance to drop below 75 Ω and fail the
board during TDR testing.
8. Use the smallest size possible for signal trace vias and DisplayPort connector pads as they have less impact
on the 100 Ω differential impedance. Large vias and pads can cause the impedance to drop below 85 Ω.
9. Use solid power and ground planes for 100 Ω impedance control and minimum power noise.
10.For 100 Ω differential impedance, use the smallest trace spacing possible, which is usually specified by the
PCB vendor.
11.Keep the trace length between the DisplayPort connector and the DisplayPort device as short as possible to
minimize attenuation.
12.Use good DisplayPort connectors whose impedances meet the specifications.
13.Place bulk capacitors (for example, 10 μF) close to power sources, such as voltage regulators or where the
power is supplied to the PCB.
14.Place smaller 0.1 μF or 0.01 μF capacitors at the device.
10.2 Layout Example
Figure 10-2. Skew Seduction via Meandering Using Chamfered Corners
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Figure 10-3. Routing Around an Object
Figure 10-4. Lumping Discontinuities
Figure 10-5. Avoiding via Clearance Sections
Figure 10-6. Keeping Planes out of the Area Between Edge-fingers
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11 Device and Documentation Support
11.1 Device Support
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
11.4 Trademarks
All trademarks are the property of their respective owners.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
3-Mar-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
HD3SS214IZQER
LIFEBUY
BGA
ZQE
50
2500 RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 105
HD3SS214
MICROSTAR
JUNIOR
HD3SS214IZXHR
HD3SS214ZQER
ACTIVE
NFBGA
ZXH
ZQE
50
50
2500 RoHS & Green
2500 RoHS & Green
SNAGCU
SNAGCU
Level-3-260C-168 HR
Level-3-260C-168 HR
HD3SS214I
HD3SS214
LIFEBUY
BGA
0 to 70
MICROSTAR
JUNIOR
HD3SS214ZXHR
ACTIVE
NFBGA
ZXH
50
2500 RoHS & Green
SNAGCU
Level-3-260C-168 HR
HD3SS214
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
3-Mar-2021
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Mar-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
HD3SS214IZQER
BGA MI
CROSTA
R JUNI
OR
ZQE
50
2500
330.0
12.4
5.3
5.3
1.5
8.0
12.0
Q1
HD3SS214IZXHR
HD3SS214ZQER
NFBGA
ZXH
ZQE
50
50
2500
2500
330.0
330.0
12.4
12.4
5.3
5.3
5.3
5.3
1.5
1.5
8.0
8.0
12.0
12.0
Q1
Q1
BGA MI
CROSTA
R JUNI
OR
HD3SS214ZXHR
NFBGA
ZXH
50
2500
330.0
12.4
5.3
5.3
1.5
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Mar-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
HD3SS214IZQER
BGA MICROSTAR
JUNIOR
ZQE
50
2500
336.6
336.6
31.8
HD3SS214IZXHR
HD3SS214ZQER
NFBGA
ZXH
ZQE
50
50
2500
2500
336.6
336.6
336.6
336.6
31.8
31.8
BGA MICROSTAR
JUNIOR
HD3SS214ZXHR
NFBGA
ZXH
50
2500
336.6
336.6
31.8
Pack Materials-Page 2
PACKAGE OUTLINE
NFBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
ZXH0050A
A
5.1
4.9
B
BALL A1 CORNER
5.1
4.9
C
1 MAX
SEATING PLANE
0.08 C
0.25
0.15
BALL TYP
(0.5) TYP
4 TYP
J
(0.5) TYP
H
G
F
SYMM
4
TYP
E
D
C
0.35
50X Ø
B
A
0.25
0.15
0.05
C A B
C
0.5 TYP
1
2
3
4
5
6
7
8
9
0.5 TYP
SYMM
4225134/A 08/2019
NOTES:
NanoFree is a trademark of Texas Instruments.
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
NFBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
ZXH0050A
(0.5) TYP
3
1
2
4
5
6
7
8
9
A
B
(0.5) TYP
C
D
E
F
SYMM
50X (Ø0.25)
G
H
J
SYMM
LAND PATTERN EXAMPLE
SCALE: 20X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
EXPOSED
METAL
(Ø 0.25)
SOLDER MASK
OPENING
EXPOSED
METAL
(Ø 0.25)
METAL
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON- SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4225134/A 08/2019
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. Refer to Texas Instruments
Literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
NFBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
ZXH0050A
(0.5) TYP
3
1
2
4
5
6
7
8
9
A
B
(0.5) TYP
C
D
E
F
METAL
TYP
SYMM
(R0.05) TYP
G
H
J
50X ( 0.25)
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.100 mm THICK STENCIL
SCALE: 20X
4225134/A 08/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
PACKAGE OUTLINE
TM
ZQE0050A
BGA MicroStar Jr - 1 mm max height
SCALE 2.500
PLASTIC BALL GRID ARRAY
5.1
4.9
B
A
BALL A1 CORNER
INDEX AREA
5.1
4.9
(0.74)
C
1 MAX
SEATING PLANE
0.08 C
0.25
TYP
0.15
BALL TYP
4 TYP
SYMM
(0.5) TYP
J
H
G
F
(0.5) TYP
SYMM
4
E
D
C
TYP
0.35
50X
0.25
0.15
0.05
C A
C
B
B
A
0.5 TYP
1
2
3
4
5
6
7
8
9
0.5 TYP
4221625/A 02/2015
MicroStar Junior is trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration MO-225.
www.ti.com
EXAMPLE BOARD LAYOUT
TM
ZQE0050A
BGA MicroStar Jr - 1 mm max height
PLASTIC BALL GRID ARRAY
50X ( 0.28)
(0.5) TYP
3
4
5
6
7
8
9
1
2
A
B
C
(0.5) TYP
D
E
F
G
H
J
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:15X
0.05 MAX
0.05 MIN
METAL UNDER
SOLDER MASK
(
0.28)
METAL
(
0.28)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4221625/A 02/2015
NOTES: (continued)
4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SSYZ015 (www.ti.com/lit/ssyz015).
www.ti.com
EXAMPLE STENCIL DESIGN
TM
ZQE0050A
BGA MicroStar Jr - 1 mm max height
PLASTIC BALL GRID ARRAY
50X ( 0.28)
(R0.05) TYP
(0.5) TYP
A
1
2
4
5
6
8
9
3
7
(0.5) TYP
B
C
D
E
F
G
H
J
METAL
TYP
SYMM
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:20X
4221625/A 02/2015
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
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Copyright © 2021, Texas Instruments Incorporated
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TI
HD3SS215RTQR
支持 DDC/AUX 开关的 6Gbps HDMI 2.0/5.4Gbps DisplayPort 1.2a 1:2/2:1 差动多路复用器 | RTQ | 56 | 0 to 70
TI
HD3SS215RTQT
支持 DDC/AUX 开关的 6Gbps HDMI 2.0/5.4Gbps DisplayPort 1.2a 1:2/2:1 差动多路复用器 | RTQ | 56 | 0 to 70
TI
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