HD3SS215_V01 [TI]
HD3SS215 6.0 Gbps HDMI DisplayPort 2:1/1:2 Differential Switch;
| 型号： | HD3SS215_V01 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HD3SS215 6.0 Gbps HDMI DisplayPort 2:1/1:2 Differential Switch |
| 文件： | 总39页 (文件大小：2809K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HD3SS215,HD3SS215I
SLAS971E – MAY 2014 – REVISED DECEMBER 2020
HD3SS215 6.0 Gbps HDMI DisplayPort 2:1/1:2 Differential Switch
1 Features
3 Description
•
•
•
•
General purpose 2:1/1:2 differential switch
HD3SS215 is a high-speed wide common mode
passive switch capable of supporting DisplayPort
HBR2 and high definition multimedia interface (HDMI)
applications requiring 4k2k 60Hz refresh rates. The
HD3SS215 can be configured to support two sources
to one sink or one source to two sinks. To support
these video standards the HD3SS215 also switches
the display data channel (DDC) and hot plug detect
(HPD) signals for HDMI or digital video interface (DVI)
applications. It also switches the auxiliary (AUX) and
hot plug detect (HPD) signals for DisplayPort
applications. The flexibility the HD3SS215 provides by
supporting both wide common mode and AC or DC
coupled links makes it ideal for many applications.
Compatible with displayport electrical standard
Compatible with hdmi electrical standards
2:1 and 1:2 switching supporting data rates up to 6
Gbps
•
•
•
•
Supports HPD switching
Supports AUX and DDC switching
Wide –3-dB differential bandwidth of 7 GHz
Excellent dynamic characteristics (at 3 GHz)
– Crosstalk = –35 dB
– Isolation = –21 dB
– Insertion Loss = –1.6 dB
– Return Loss = –12 dB
– Max Bit-Bit Skew = 5 ps
Device Information (1)
PART NUMBER
PACKAGE
nFBGA (50)
QFN (56)
BODY SIZE (NOM)
5.00 mm x 5.00 mm
8.00 mm × 8.00 mm
•
•
VDD operating range 3.3 V ±10%
Commercial temperature range: 0°C to 70°C
(HD3SS215)
HD3SS215,
HD3SS215I
•
•
Industrial temperature range: –40°C to 85°C
(HD3SS215I)
Package options:
– 5 mm x 5 mm, 50-ball ZXH
– 8 mm × 8 mm, 56-pin RTQ
Output enable (OE) pin disables switch to save
power
Power consumption:
– Active < 9 mW typical
– Standby < 30 µW maximum (when OE = L)
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
DAx(p)
DAx(n)
4
4
DCx(p)
DCx(n)
4
4
AUXAx
Source A
2
•
•
2
DDCA
HPDA
DP/DP++
HDMI sink
DDCC
2
2
AUXCx
HPDC
AUXBx
2
2
DDCB
HPDB
OE
Dx_SEL
AUX_SEL
Source B
Control
DBx(p)
DBx(n)
4
4
2 Applications
HD3SS215 2:1
•
Desktop and Notebook Applications:
– PCI Express Gen 1, Gen 2 Switching
– DP Switching
DAx(p)
4
4
DCx(p)
DCx(n)
4
4
DAx(n)
DP/DP++
HDMI Sink A
AUXAx
2
– HDMI Switching
– LVDS Switching
DDCA
HPDA
2
Source
DDCC
2
AUXCx
2
•
•
•
•
•
Connected peripherals & printers
Home theater & entertainment
TV
Gaming
Pro audio, video & signage
AUXBx
HPDC
2
2
DDCB
HPDB
OE
DP/DP++
HDMI Sink B
Dx_SEL
AUX_SEL
Control
DBx(p)
DBx(n)
4
4
HD3SS215 1:2
Application Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
HD3SS215, HD3SS215I
SLAS971E – MAY 2014 – REVISED DECEMBER 2020
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 4
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 9
7.1 Absolute Maximum Ratings (1) (2) ...............................9
7.2 ESD Ratings............................................................... 9
7.3 Recommended Operating Conditions.........................9
7.4 Thermal Information....................................................9
7.5 Electrical Characteristics...........................................10
7.6 Electrical Characteristics, Device Parameters (1) .....11
7.7 Switching Characteristics..........................................11
7.8 Timing Diagrams....................................................... 11
8 Detailed Description......................................................13
8.1 Overview...................................................................13
8.2 Functional Block Diagram.........................................14
8.3 Feature Description...................................................15
8.4 Device Functional Modes..........................................15
9 Applications and Implementation................................16
9.1 Application Information............................................. 16
9.2 Typical Applications.................................................. 16
10 Layout...........................................................................21
10.1 Layout Guidelines................................................... 21
10.2 Layout Example...................................................... 22
11 Device and Documentation Support..........................24
11.1 Community Resources............................................24
11.2 Trademarks............................................................. 24
12 Mechanical, Packaging, and Orderable
Information.................................................................... 24
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (September 2015) to Revision E (December 2020)
Page
•
NOTE: The device in the MicroStar Jr. BGA packaging were redesigned using a laminate nFBGA package.
This nFBGA package offers datasheet-equivalent electrical performance. It is also footprint equivalent to the
MicroStar Jr. BGA. The new package designator in place of the discontinued package designator will be
updated throughout the datasheet......................................................................................................................1
Changed u*jr ZQE to nFBGA ZXH..................................................................................................................... 1
Changed u*jr ZQE to nFBGA ZXH..................................................................................................................... 4
Changed u*jr ZQE to nFBGA ZXH..................................................................................................................... 4
Changed u*jr ZQE to nFBGA ZXH..................................................................................................................... 4
Changed u*jr ZQE to nFBGA ZXH..................................................................................................................... 7
Changed u*jr ZQE to nFBGA ZXH. Updated thermal data.................................................................................9
Changed u*jr ZQE to nFBGA ZXH....................................................................................................................11
Changed u*jr ZQE to nFBGA ZXH................................................................................................................... 16
•
•
•
•
•
•
•
•
Changes from Revision C (August 2015) to Revision D (September 2015)
Page
•
Changed Section 3 text string from "....DisplayPort 1.2a..." to "...DisplayPort HBR2..." and from "..HDMI2.0.."
to "...HDMI..." .....................................................................................................................................................1
Deleted RθJC(bot) spec from Thermal Information table as N/A...........................................................................9
Deleted "Operating free air temperature" spec from Electrical Characteristics table....................................... 10
Changed Figure 9-5 .........................................................................................................................................20
Changed Section Power Supply Recommendations text string from "Decoupling capacitors may be used to
reduce noise and improve power supply integrity" to "Decoupling capacitors must be used to reduce power
supply noise"...................................................................................................................................................0
•
•
•
•
Changes from Revision B (July 2015) to Revision C (July 2015)
Page
•
Added ton(OE_L-H), toff(OE_H-L), and tSWITCH_OVER to the Section 7.7 ..................................................................11
Changes from Revision A (May 2014) to Revision B (July 2015)
Page
•
Changed the title From: "2.0/DisplayPort 1.2A" To: "DisplayPort"...................................................................... 1
Copyright © 2020 Texas Instruments Incorporated
2
Submit Document Feedback
Product Folder Links: HD3SS215 HD3SS215I
HD3SS215, HD3SS215I
SLAS971E – MAY 2014 – REVISED DECEMBER 2020
www.ti.com
•
•
Changed Section 1 list item From: Compatible With DisplayPort 1.2a Electrical Standard To: Compatible With
DisplayPort Electrical Standard.......................................................................................................................... 1
Changed Section 1 list item From: Compatible With HDMI 1.4b and HDMI 2.0 Electrical Standards To:
Compatible With HDMI Electrical Standards...................................................................................................... 1
Added Section 1 item: Commercial Temperature Range: –40°C to 70°C (HD3SS215)..................................... 1
Added Section 1 item: Inductrial Temperature Range: –40°C to 85°C (HD3SS215I).........................................1
Added Section 1, Package Options: 8 mm × 8 mm, 56-Pin RTQ.......................................................................1
Changed the Section 2 list item From: TV and Monitors To: UHDTV, HDTV and Monitors................................1
Added Section 5 paragraph. ..............................................................................................................................4
Added the 56-Pin QFN image.............................................................................................................................4
Added RTQ column to the Pin Functions table ..................................................................................................4
Added RTQ column to the Pin Functions table ..................................................................................................7
Moved Tstg From: Section 7.2 To: Section 7.1 ...................................................................................................9
Changed the Handling Ratings table to Section 7.2 table ................................................................................. 9
Added HD3SS2151I, Operating free-air temperature Section 7.3 .....................................................................9
Added RTQ 56 PIN values to the Section 7.4 ....................................................................................................9
Added table Note " This pin can be driven.." to the Section 7.5 table.............................................................. 10
Changed the Section 7.6 table to include ZQE and RTQ package values....................................................... 11
Added the Section 7.7 table .............................................................................................................................11
Added section: Section 9.2.4 ...........................................................................................................................20
Added Figure 10-3 ...........................................................................................................................................22
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Changes from Revision * (May 2014) to Revision A (May 2014)
Page
Changed Section 3 section ................................................................................................................................1
Changed Figure 9-1 .........................................................................................................................................16
•
•
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: HD3SS215 HD3SS215I
HD3SS215, HD3SS215I
SLAS971E – MAY 2014 – REVISED DECEMBER 2020
www.ti.com
5 Description (continued)
One typical application would be a mother board that includes two GPUs that need to drive one DisplayPort sink.
The GPU is selected by the Dx_SEL pin. Another application is when one source needs to switch between one
of two sinks, such as a side connector an a docking station connector. The switching is controlled using the
Dx_SEL and AUX_SEL pins. The HD3SS215I operates from a single supply voltage of 3.3 V, over full industrial
temperature range –40°C to 85°C, in the ZXH package and 56 pin RTQ package.
6 Pin Configuration and Functions
1
2
3
4
5
6
7
8
9
Dx_SEL
VDD
DA0(n)
DA1(n)
DA2(n)
DA3(p)
DA3(n)
A
B
C
D
E
F
DC0(n)
DC0(p)
AUX_SEL
DC1(p)
GND
DA0(p)
DA1(p)
DA2(p)
OE
DB0(p)
GND
DB0(n)
DC1(n)
DC2(n)
DC3(n)
DB1(p)
DB2(p)
DB3(p)
DB1(n)
DB2(n)
DB3(n)
DC2(p)
DC3(p)
GND
AUXC(p)
HPDA
GND
G
H
AUXC(n)
HPDC
HPDB
GND
VDD
DDCCLK_B AUXB(p)
GND
DDCCLK_A AUXA(p)
DDCCLK_C
DDCDAT_B AUXB(n) DDCDAT_C DDCDAT_A AUXA(n)
J
Figure 6-1. 50-Pin µBGA ZXH Package (Top View)
Copyright © 2020 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: HD3SS215 HD3SS215I
HD3SS215, HD3SS215I
SLAS971E – MAY 2014 – REVISED DECEMBER 2020
www.ti.com
42
41
40
39
38
37
36
35
34
33
32
31
NC
AUX_SEL
1
2
DB0(P)
DB0(N)
DC0(P)
DC0(N)
3
GND
GND
DC1(P)
DC1(N)
4
DB1(P)
DB1(N)
5
6
HD3SS215 RTQ
GND
GND
DC2(P)
DC2(N)
7
DB2(P)
DB2(N)
8
GND
9
GND
GND
DC3(P)
DC3(N)
10
11
12
DB3(P)
DB3(N)
AUXA(P)
AUXA(N)
30
29
AUXC(P)
AUXC(N)
13
14
Figure 6-2. 56-Pin QFN RTQ Package (Top View)
Table 6-1. Pin Functions
PIN
NO.
I/O
DESCRIPTION(1)
NAME
ZXH
RTQ
56
1
Dx_SEL
AUX_SEL
DA0(p)
DA0(n)
DA1(p)
DA1(n)
DA2(p)
DA2(n)
A1
C2
B4
A4
B5
A5
B6
A6
2 Level Control I
3 Level Control I
High Speed Port Selection Control Pins
AUX/DDC Selection Control Pin in Conjunction with Dx_SEL Pin
Port A, Channel 0, High Speed Positive Signal
Port A, Channel 0, High Speed Negative Signal
Port A, Channel 1, High Speed Positive Signal
Port A, Channel 1, High Speed Negative Signal
Port A, Channel 2, High Speed Positive Signal
Port A, Channel 2, High Speed Negative Signal
54
53
51
50
48
47
I/O
I/O
I/O
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: HD3SS215 HD3SS215I
HD3SS215, HD3SS215I
SLAS971E – MAY 2014 – REVISED DECEMBER 2020
www.ti.com
Table 6-1. Pin Functions (continued)
PIN
NO.
I/O
DESCRIPTION(1)
NAME
ZXH
A8
RTQ
45
44
41
40
38
37
35
34
32
31
2
DA3(p)
DA3(n)
Port A, Channel 3, High Speed Positive Signal
Port A, Channel 3, High Speed Negative Signal
Port B, Channel 0, High Speed Positive Signal
Port B, Channel 0, High Speed Negative Signal
Port B, Channel 1, High Speed Positive Signal
Port B, Channel 1, High Speed Negative Signal
Port B, Channel 2, High Speed Positive Signal
Port B, Channel 2, High Speed Negative Signal
Port B, Channel 3, High Speed Positive Signal
Port B, Channel 3, High Speed Negative Signal
Port C, Channel 0, High Speed Positive Signal
Port C, Channel 0, High Speed Negative Signal
Port C, Channel 1, High Speed Positive Signal
Port C, Channel 1, High Speed Negative Signal
Port C, Channel 2, High Speed Positive Signal
Port C, Channel 2, High Speed Negative Signal
Port C, Channel 3, High Speed Positive Signal
Port C, Channel 3, High Speed Negative Signal
Port A AUX Positive Signal
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A9
DB0(p)
B8
DB0(n)
B9
DB1(p)
D8
D9
E8
DB1(n)
DB2(p)
DB2(n)
E9
DB3(p)
F8
DB3(n)
F9
DC0(p)
B2
DC0(n)
B1
3
DC1(p)
D2
D1
E2
5
DC1(n)
6
DC2(p)
8
DC2(n)
E1
9
DC3(p)
F2
11
DC3(n)
F1
12
30
29
24
25
13
14
27
28
22
23
18
26
16, 17, 15
AUXA(p)
AUXA(n)
AUXB(p)
AUXB(n)
AUXC(p)
AUXC(n)
DDCCLK_A
DDCDAT_A
DDCCLK_B
DDCDAT_B
DDCCLK_C
DDCDAT_C
HPDA/B/C
H9
J9
Port A AUX Negative Signal
H6
J6
Port B AUX Positive Signal
Port B AUX Negative Signal
H2
H1
H8
J8
Port C AUX Positive Signal
Port C AUX Negative Signal
Port A DDC Clock Signal
Port A DDC Data Signal
H5
J5
Port B DDC Clock Signal
Port B DDC Data Signal
J3
Port C DDC Clock Signal
I/O
I/O
J7
Port C DDC Data Signal
J2, H3, J1
Port A/B/C Hot Plug Detect
Output Enable:
OE
B7
43
I
OE = VIH: Normal Operation
OE = VIL: Standby Mode
VDD
GND
A2, J4
19, 55
Supply
Supply
3.3 V Positive power supply voltage
4, 7, 10, 33,
36, 39, 46,
49, 52
B3, C8, G2,
G8 H4, H7
Ground
NC
20, 21, 42
–
Not connected
Supply Ground
Thermal Pad
–
GND
(1) Only the high speed data DAz/DBz ports incorporate 20kΩ pull down resistors that are switched in when a port is not selected and
switched out when the port is selected.
Copyright © 2020 Texas Instruments Incorporated
6
Submit Document Feedback
Product Folder Links: HD3SS215 HD3SS215I
HD3SS215, HD3SS215I
SLAS971E – MAY 2014 – REVISED DECEMBER 2020
www.ti.com
Pin Functions
PIN
NO.
I/O
DESCRIPTION(1)
NAME
ZXH
A1
C2
B4
A4
B5
A5
B6
A6
A8
A9
B8
B9
D8
D9
E8
E9
F8
RTQ
56
1
Dx_SEL
AUX_SEL
DA0(p)
2 Level Control I
3 Level Control I
High Speed Port Selection Control Pins
AUX/DDC Selection Control Pin in Conjunction with Dx_SEL Pin
Port A, Channel 0, High Speed Positive Signal
Port A, Channel 0, High Speed Negative Signal
Port A, Channel 1, High Speed Positive Signal
Port A, Channel 1, High Speed Negative Signal
Port A, Channel 2, High Speed Positive Signal
Port A, Channel 2, High Speed Negative Signal
Port A, Channel 3, High Speed Positive Signal
Port A, Channel 3, High Speed Negative Signal
Port B, Channel 0, High Speed Positive Signal
Port B, Channel 0, High Speed Negative Signal
Port B, Channel 1, High Speed Positive Signal
Port B, Channel 1, High Speed Negative Signal
Port B, Channel 2, High Speed Positive Signal
Port B, Channel 2, High Speed Negative Signal
Port B, Channel 3, High Speed Positive Signal
Port B, Channel 3, High Speed Negative Signal
Port C, Channel 0, High Speed Positive Signal
Port C, Channel 0, High Speed Negative Signal
Port C, Channel 1, High Speed Positive Signal
Port C, Channel 1, High Speed Negative Signal
Port C, Channel 2, High Speed Positive Signal
Port C, Channel 2, High Speed Negative Signal
Port C, Channel 3, High Speed Positive Signal
Port C, Channel 3, High Speed Negative Signal
Port A AUX Positive Signal
54
53
51
50
48
47
45
44
41
40
38
37
35
34
32
31
2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DA0(n)
DA1(p)
DA1(n)
DA2(p)
DA2(n)
DA3(p)
DA3(n)
DB0(p)
DB0(n)
DB1(p)
DB1(n)
DB2(p)
DB2(n)
DB3(p)
DB3(n)
F9
DC0(p)
B2
B1
D2
D1
E2
E1
F2
DC0(n)
3
DC1(p)
5
DC1(n)
6
DC2(p)
8
DC2(n)
9
DC3(p)
11
DC3(n)
F1
12
30
29
24
25
13
14
27
28
22
23
18
26
16, 17, 15
AUXA(p)
AUXA(n)
AUXB(p)
AUXB(n)
AUXC(p)
AUXC(n)
DDCCLK_A
DDCDAT_A
DDCCLK_B
DDCDAT_B
DDCCLK_C
DDCDAT_C
HPDA/B/C
H9
J9
Port A AUX Negative Signal
H6
J6
Port B AUX Positive Signal
Port B AUX Negative Signal
H2
H1
H8
J8
Port C AUX Positive Signal
Port C AUX Negative Signal
Port A DDC Clock Signal
Port A DDC Data Signal
H5
J5
Port B DDC Clock Signal
Port B DDC Data Signal
J3
Port C DDC Clock Signal
I/O
I/O
J7
Port C DDC Data Signal
J2, H3, J1
Port A/B/C Hot Plug Detect
Output Enable:
OE
VDD
GND
NC
B7
43
I
OE = VIH: Normal Operation
OE = VIL: Standby Mode
A2, J4
19, 55
Supply
Supply
3.3 V Positive power supply voltage
4, 7, 10, 33,
36, 39, 46,
49, 52
B3, C8, G2,
G8 H4, H7
Ground
20, 21, 42
Not connected
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: HD3SS215 HD3SS215I
HD3SS215, HD3SS215I
SLAS971E – MAY 2014 – REVISED DECEMBER 2020
www.ti.com
PIN
NO.
I/O
DESCRIPTION(1)
NAME
ZXH
RTQ
Thermal Pad
–
–
GND
Supply Ground
(1) Only the high speed data DAz/DBz ports incorporate 20kΩ pull down resistors that are switched in when a port is not selected and
switched out when the port is selected.
Copyright © 2020 Texas Instruments Incorporated
8
Submit Document Feedback
Product Folder Links: HD3SS215 HD3SS215I
HD3SS215, HD3SS215I
SLAS971E – MAY 2014 – REVISED DECEMBER 2020
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings (1) (2)
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
MIN
–0.5
–0.5
–0.5
–0.5
–65
MAX
Supply voltage VDD
Differential I/O
4
4
V
V
Voltage
AUX_SEL, Dx_SEL
4
HPDx, DDCCLK_X, DDCDAT_X
Storage temperature
6
Tstg
150
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to network ground pin.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±1500
V
V(ESD)
Electrostatic discharge
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins(2)
±1250
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3
NOM
MAX
3.6
70
UNIT
V
VDD
TA
Main power supply
3.3
HD3SS215
HD3SS215I
0
°C
Operating free-air temperature
AC coupling capacitor
–40
75
85
°C
CAC
100
200
nF
7.4 Thermal Information
HD3SS215
THERMAL METRIC(1)
UNIT
RTQ (56 PIN)
90.5
ZXH (50 PIN)
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
69.9
35.1
40.4
1.6
°C/W
°C/W
°C/W
°C/W
°C/W
41.9
53.9
1.8
ψJB
Junction-to-board characterization parameter
53.4
40.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: HD3SS215 HD3SS215I
HD3SS215, HD3SS215I
SLAS971E – MAY 2014 – REVISED DECEMBER 2020
www.ti.com
7.5 Electrical Characteristics
Typical values for all parameters are at VDD = 3.3 V and TA = 25°C. All temperature limits are specified by design.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VDD
Supply voltage
3
3.3
3.6
VDD
5.5
V
Control Pins, Signal Pins
(Dx_SEL, AUX_SEL, OE)
2
2
VIH
Input high voltage
V
HPD and DDC
VDD/2
– 300mV
VDD/2
+ 300mV
VIM
VIL
Input mid level voltage
Input low voltage
AUX_SEL Pin (1)
VDD/2
V
V
Control Pins, Signal Pins
(Dx_SEL, AUX_SEL, OE)
–0.1
0.8
VI/O_Diff
VCM
Differential voltage (Dx, AUXx)
Common voltage (Dx, AUXx)
Switch I/O diff voltage
0
0
1.8
3.3
Vpp
V
Switch common mode voltage
Input high current (Dx_SEL,
AUX_SEL)
IIH
IIM
IIL
VDD = 3.6 V, VIN = VDD
VDD = 3.6 V, VIN = VDD/2
VDD = 3.6 V, VIN = GND
1
1
1
Input mid current (AUX_SEL)
Input low current (Dx_SEL,
AUX_SEL)
0.01
VDD = 3.6 V, VIN = 2 V, OE = 3.3 V
VDD = 3.6 V, VIN = 2 V, OE = 0 V
0.01
0.01
2
2
Leakage current
(Dx_SEL, AUX_SEL)
µA
VDD = 3.6 V, VIN = 2 V, OE = 0 V;
Dx_SEL = 3.3 V
ILK
0.01
0.01
5
Leakage current (HPDx/DDCx)
VDD = 3.6 V, VIN = 2 V, OE = 3.3 V;
Dx_SEL = GND
5
8
IOFF
IDD
Device shut down current
Supply current
VDD = 3.6 V, OE = GND
VDD = 3.6 V,
Dx_SEL= VDD; AUX_SEL = GND;
Outputs Floating
2.5
8
3.2
mA
DA, DB, DC HIGH SPEED SIGNAL PATH
VCM = 0 V–3.3 V,
IO = –1mA
RON
ON resistance
14
Ω
Ω
Ω
On resistance match between pairs of VCM = 0 V–3. 3V,
ΔRON
1.5
the same channel
IO = –1 mA
On resistance flatness (RON(MAX)
–
RFLAT_ON
VCM = 0 V–3.3 V
1.3
RON(MAIN)
)
AUXx, DDC, SIGNAL PATH
VCM = 0 V–3.3 V,
IO = –8 mA
RON(AUX)
ON resistance on AUX channel
5
8
Ω
Ω
RON(DDC) ON resistance on DDC channel
VCM = 0.4 V, IO = -3 mA
30
40
(1) This pin can be driven to the specified level or 10 kΩ. Pull up and pull downs can be used. It cannot be left floating.
Copyright © 2020 Texas Instruments Incorporated
10
Submit Document Feedback
Product Folder Links: HD3SS215 HD3SS215I
HD3SS215, HD3SS215I
SLAS971E – MAY 2014 – REVISED DECEMBER 2020
www.ti.com
7.6 Electrical Characteristics, Device Parameters (1)
Under recommended operating conditions; RLOAD, RSC = 50 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
–15
–12
–17
–13
–35
–35
–21
–16
–1.2
–1.6
–2
MAX UNIT
1.35 GHz
ZXH package
RTQ package
3 GHz
RL
Dx Differential return loss
dB
1.35 GHz
3 GHz
ZXH package
RTQ package
ZXH package
RTQ package
XTALK
Dx Differential crosstalk
2.7 GHz
3 GHz
dB
dB
dB
dB
OIRR
Dx Differential off-isolation
f = 1.35 GHz
f = 3 GHz
ZXH package
RTQ package
IL
Dx Differential insertion loss
f = 1.35 GHz
f = 3 GHz
–2.4
7
ZXH package
RTQ package
BWDx
Dx Differential -3-dB bandwidth
AUX –3-dB bandwidth
GHz
MHz
5
BWAUX
720
(1) For Return Loss, Crosstalk, Off-Isolation, and Insertion Loss values the data was collected on a Rogers material board with minimum
length traces on the input and output of the device under test.
7.7 Switching Characteristics
Under recommended operating conditions; RLOAD, RSC = 50 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPD
Switch propagation delay
RSC and RLOAD = 50 Ω,
200
ps
See Figure 7-2
ton(OE_L-H)
toff(OE_H-L)
tSWITCH_OVER
Time from OE toggling High and valid data at the RSC and RLOAD = 50 Ω,
1
15
2
50
1
µs
µs
outputs
VCM = 3 V - 3.3 V
Time from OE toggling Low and outputs are in Z-
state
Time to switch between ports when DX_SEL or
AUX_SEL state is changed for Data, AUX, DDC
signals
RSC and RLOAD = 50 Ω,
See Figure 7-1
0.7
ton
Dx_SEL/AUX_SEL-to-Switch ton (HPD)
Dx_SEL/AUX_SEL-to-Switch toff (HPD)
Inter-Pair output skew (CH-CH)
RLOAD = 125k Ω, See Figure 7-1
0.7
0.7
1
20
30
5
µs
ps
toff
tSK(O)
tSK(b-b)
RSC and RLOAD = 50 Ω,
See Figure 7-2
Intra-Pair output skew (bit-bit)
1
7.8 Timing Diagrams
50%
Dx_SEL
90%
10%
VOUT
Ton
Toff
Figure 7-1. Select to Switch ton and toff
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: HD3SS215 HD3SS215I
HD3SS215, HD3SS215I
SLAS971E – MAY 2014 – REVISED DECEMBER 2020
www.ti.com
Vcc
Rsc = 50 Ω
DAx/DBx(p)
DCx(p)
RLoad = 50 Ω
Rsc = 50 Ω
DAx/DBx(n)
DCx(n)
RLoad = 50 Ω
SEL
DAx/DBx(p)
50%
50%
DAx/DBx(n)
DCx(p)
50%
50%
DCx(n)
tP1
t2
tP2
t4
t1
t3
DCx(p)
50%
DCx(n)
DCy(p)
t
SK(O)
DCy(n)
tPD = Max(tp1, tp2
)
tSK(O) = Difference between tPD for any
two pairs of outputs
tSK(b-b) = 0.5 X |(t4 – t3) + (t1 – t2)|
Figure 7-2. Propagation Delay and Skew
Copyright © 2020 Texas Instruments Incorporated
12
Submit Document Feedback
Product Folder Links: HD3SS215 HD3SS215I
HD3SS215, HD3SS215I
SLAS971E – MAY 2014 – REVISED DECEMBER 2020
www.ti.com
8 Detailed Description
8.1 Overview
The HD3SS215 is a generic analog, differential passive switch that can work for any high speed interface
applications, as long as it is biased at a common mode voltage range of 0 V to 3.3 V and has differential
signaling with differential amplitude up to 1800 mVpp. It employs adaptive tracking that maintains the high speed
channel impedance over the entire common mode voltage range. In high-speed applications and data paths,
signal integrity is an important concern. The switch offers excellent dynamic performance such as high isolation,
crosstalk immunity, and minimal bit-bit skew. These characteristics allow the device to function seamlessly in the
system without compromising signal integrity. The 2:1/1:2, mux/de-mux device operates with ports A or B
switched to port C, or port C switched to either port A or B. This flexibility allows an application to select between
one of two Sources on ports A and B and send the output to the sink on port C. Similarly, a Source on port C can
select between one of two Sink devices on ports A and B to send the data. To comply with DisplayPort, DP++
and HDMI applications, the HD3SS215 also switches AUX, HPD, and DDC along with the high-speed differential
signals. The HPD and data signals are both switched through the Dx_SEL pin. AUX and DDC are controlled with
AUX_SEL and Dx_SEL. The Functional Modes section contains information on how to set the control pins.
With an OE control pin, the HD3SS215 is operational, with low active current, when this pin is high. When OE is
pulled lowed, the device goes into standby mode and draws very little current in order to save power
consumption in the application.
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: HD3SS215 HD3SS215I
HD3SS215, HD3SS215I
SLAS971E – MAY 2014 – REVISED DECEMBER 2020
www.ti.com
8.2 Functional Block Diagram
VDD
4
4
DAz(p)
DAz(n)
SEL=0
4
4
DCz(p)
DCz(n)
(z = 0, 1, 2 or 3)
4
4
DBz(p)
DBz(n)
SEL=1
SEL
Dx_SEL
SEL
HPDA
HPDB
SEL=0
SEL=1
HPDC
AUX_SEL
SEL2
AUXA(p)
AUXA(n)
SEL
AUXx(P) or DDCCLK_x
AUXx(n) or DDCDAT_
AUXB(p)
AUXB(n)
AUXC(p)
x
AUXC(n)
DDCCLK_C
DDCDAT_C
DDCCLK_A
DDCDAT_A
DDCCLK_B
DDCDAT_B
OE
HD3SS215
GND
The high speed data ports incorporate 20kΩ pull down resistors that are switched in when a port is not selected and switched out when
the port is selected.
Figure 8-1. Functional Block Diagram
Copyright © 2020 Texas Instruments Incorporated
14
Submit Document Feedback
Product Folder Links: HD3SS215 HD3SS215I
HD3SS215, HD3SS215I
SLAS971E – MAY 2014 – REVISED DECEMBER 2020
www.ti.com
8.3 Feature Description
8.3.1 High Speed Switching
The HD3SS215 supports switching of 6 Gbps data rates. The wide common mode of the device enables it to
support TMDS signal levels and DisplayPort signals. The high speed muxing is designed with a wide –3dB
differential bandwidth of 7 GHz and industry leading dynamic characteristics. All of these attributes help maintain
signal integrity in the application. Each high speed port incorporates 20kΩ pull down resistors that are switched
in when the port is not selected and switched out when the port is selected.
8.3.2 HPD, AUX, and DDC Switching
HPD, AUX and DDC switching is supported through the HD3SS215. This enables the device to work in multiple
application scenarios within multiple electrical standards. The AUXA/B and DDCA/B lines can both be switched
to the AUXC port. This feature supports DP++ or AUX only adapters. For HDMI applications, the DDC channels
are switched to the DDC_C port only and the AUX channel can remain active or the end user can make it float.
8.3.3 Output Enable and Power Savings
The HD3SS215 has two power modes, active/normal operating mode, and standby mode. During standby mode,
the device consumes very little current to save the maximum power. To enter standby mode, the OE control pin
is pulled low and must remain low. For active/normal operation, the OE control pin should be pulled high to VDD
through a resistor.
8.4 Device Functional Modes
8.4.1 Switch Control Modes
Refer to the Section 8.2.
The HD3SS215 behaves as a two to one or one to two differential switch using high bandwidth pass gates. The
input ports are selected using the AUX_SEL pin and Dx_SEL pin which are shown in Table 8-1.
Table 8-1. Switch Control Logic (1) (2) (3)
CONTROL LINES(4)
AUX_SEL Dx_SEL
SWITCHED I/O PINS
DCz(p) Pin
DCz(n) Pin
z = 0, 1, 2 or 3 z = 0, 1, 2 or 3
HPDC Pin
AUXA
AUXB
AUXC
DDCA
DDCB
DDCC
L
L
L
H
L
DAz(p)
DBz(p)
DAz(p)
DBz(p)
DAz(p)
DBz(p)
DAz(n)
DBz(n)
DAz(n)
DBz(n)
DAz(n)
DBz(n)
HPDA
To/From
AUXC
Z
To/From
AUXA
Z
Z
Z
Z
Z
Z
HPDB
HPDA
HPDB
HPDA
HPDB
Z
Z
Z
To/From
AUXC
To/From
AUXB
Z
Z
Z
H
Z
To/From
DDCA
To/From
AUXC
H
H
L
Z
Z
To/From
DDCB
Z
To/From
AUXC
M(4)
M(4)
To/From
AUXC
To/From
AUXA
To/From
DDCC
Z
To/From
DDCA
H
Z
To/From
AUXC
To/From
AUXB
Z
To/From
DDCC
To/From
DDCB
(1) Z = High Impedance
(2) OE pin - For normal operation, drive OE high. Driving the OE pin low will disable the switch.
(3) The ports which are not selected by the control lines will be in high impedance status.
(4) For HDMI application, keep the AUX_SEL at middle level voltage. The AUX channel is still active, and the end user can make the lines
float.
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: HD3SS215 HD3SS215I
HD3SS215, HD3SS215I
SLAS971E – MAY 2014 – REVISED DECEMBER 2020
www.ti.com
9 Applications and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The HD3SS215 can be used in a variety of applications. This section shows the typical applications for
DisplayPort , DP++, and HDMI. The example diagrams illustrate using the HD3SS215 in a two source to one
sink application and a one source to two sinks application. All schematics are using the ZXH pin-out.
9.2 Typical Applications
9.2.1 DisplayPort and Dual Mode Adapter with Two Sources
The application schematic below shows the HD3SS215 in the 2:1 configuration for DisplayPort switching. The
HD3SS215 receives inputs from DP Source A and DP Source B. The control pins of the device can be set to
select Source A/B inputs and transfer them to port C through the Dx_SEL control pin. The schematic also shows
the CONFIG1 and AUX_SEL settings to configure the HD3SS215 to work with DP++ Type 2 and Type1
adapters. For this specific schematic, the AC capacitors needed on the MainLink signal lines are shown on the
Sink side of the HD3SS215. This is done to decrease the BOM. If desired the AC capacitors maybe placed in the
signal path on the Source A/B side of HD3SS215. Additional diagrams are provided to show the configuration of
the AUX channel for 2:1 and 1:2 DisplayPort only applications.
Figure 9-1. HD3SS215 Application Diagram for DisplayPort or Dual Mode Adapter Configuration
Copyright © 2020 Texas Instruments Incorporated
16
Submit Document Feedback
Product Folder Links: HD3SS215 HD3SS215I
HD3SS215, HD3SS215I
SLAS971E – MAY 2014 – REVISED DECEMBER 2020
www.ti.com
Figure 9-2. HD3SS215 AUX Channel in 2:1 DisplayPort Application
Figure 9-3. HD3SS215 AUX Channel in 1:2 DisplayPort Application
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: HD3SS215 HD3SS215I
HD3SS215, HD3SS215I
SLAS971E – MAY 2014 – REVISED DECEMBER 2020
www.ti.com
9.2.1.1 Design Requirements
Table 9-1. Design Parameters
DESIGN PARAMETER
VDD
EXAMPLE VALUE
3.3 V
Decoupling Capacitors
0.1 µF
AC Capacitors
75 nF to 200 nF (100 nF shown)
10 kΩ to105 kΩ (100 kΩ shown)
10 kΩ
AUX Pull-Up/Pull-Down Resistors
Pull-Up/Pull-Down Resistors for Control Pins
CONFIG1/CONFIG2 Pull-Down Resistors
1 MΩ and 5 MΩ
9.2.1.2 Detailed Design Procedure
The HD3SS215 is designed to operate with a 3.3 V power supply. Levels above those listed in the Absolute
Ratings table should not be used. If using a higher voltage system power supply, a voltage regulator can be used
to step down to 3.3 V. Decoupling capacitors may be used to reduce noise and improve power supply integrity.
AC capacitors must be placed on the MainLink lines. Additionally, AC capacitors are placed on the AUXC lines.
After the blocking capacitors, the AUXCp line must be pulled down weakly through a resistor to ground, and the
AUXCn line must be pulled up weakly through a resistor to VDD. The voltage level of the control pins, AUX_SEL
and Dx_SEL should be set according to the application and muxing desired. For a DisplayPort connector, the
CONFIG1 and CONFIG2 pins should be pulled to ground through resistors. For Dual Mode adapter
implementation, the CONFIG1 line may be used to perform cable adapter detection. The CONFIG2 line can be
configured for an HDMI adaptor or left as a no connect for a DVI adapter. The CONFIG2 pin on the connector
should be pulled up or left floating accordingly for Dual Mode adapter configuration.
Copyright © 2020 Texas Instruments Incorporated
18
Submit Document Feedback
Product Folder Links: HD3SS215 HD3SS215I
HD3SS215, HD3SS215I
SLAS971E – MAY 2014 – REVISED DECEMBER 2020
www.ti.com
9.2.2 HDMI Application with Two Sinks
The HD3SS215 can be placed in applications needing to switch between two sinks. In this example, the HDMI
source selects between Sink A or Sink B in the 1:2 configuration.
Figure 9-4. Application Diagram for a 1:2 Configuration with HDMI Source and Connectors
9.2.2.1 Design Requirements
Table 9-2. Design Parameters
DESIGN PARAMETER
VDD
EXAMPLE VALUE
3.3 V
Decoupling Capacitors
0.1 µF
DDC Pull-Up Resistors
1.5 kΩ to 2 kΩ to 5 V (2 kΩ shown)
Pull-Up/Pull-Down Resistors for Control Pins
HPD Pull-Down Resistor
10 kΩ
100 kΩ
9.2.2.2 Detailed Design Procedure
The HD3SS215 is designed to operate with a 3.3 V power supply. Levels above those listed in the Absolute
Ratings table should not be used. If using a higher voltage system power supply, a voltage regulator can be used
to step down to 3.3 V. Decoupling capacitors may be used to reduce noise and improve power supply integrity.
Pull-up resistors to 5 V must be placed on the source side DDC clock and data lines according to the HDMI2.0
Standard. A weak pull down resistor should be placed on the source side HPD line. This is to ensure the source
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
19
Product Folder Links: HD3SS215 HD3SS215I
HD3SS215, HD3SS215I
SLAS971E – MAY 2014 – REVISED DECEMBER 2020
www.ti.com
can differentiate between when HPD is disconnected or at a high voltage level. The AUX_SEL and Dx_SEL
control pins should be set according to the application and desired muxing.
9.2.3
9.2.4 HDMI 2:1 Sink Application Using the RTQ Package
The HD3SS215 can be placed in applications needing to switch between two HDMI connectors and one Generic
HDMI sink.
3.3V
0.1uF
0.1uF
5V
Source A
D0p
D0n
DA0p
DA0n
5V
GND1
D1p
D1n
DA1p
DA1n
Sink
47kΩ
47kΩ
GND2
D2p
D2n
DA2p
DA2n
GND3
5V
DC0p
DC0n
D0p
D0n
GND4
D3p
D3n
DA3p
DA3n
GND1
GND2
Utility
DC1p
DC1n
D1p
D1n
DDC_SCL
DDC_SDA
AUXAp
AUXAn
DDC_GND
DC2p
DC2n
D2p
D2n
HPD
DDCCLK_A
DDCDAT_A
GND3
GND4
DC3p
DC3n
D3p
D3n
HPDA
HDMI Connector
Utility
AUXCp
AUXCn
DDC_SCL
DDC_SDA
100kΩ
DDC_GND
Source B
DDCCLK_C
DDCDAT_C
HPD
D0p
D0n
DB0p
DB0n
GND1
HPDC
D1p
D1n
DB1p
DB1n
HDMI SINK Device
GND2
3.3V
5V
D2p
D2n
DB2p
DB2n
GND3
10kΩ
GND4
D3p
D3n
DB3p
DB3n
OE
AUX_SEL
Dx_SEL
Utility
DDC_SCL
DDC_SDA
AUXBp
AUXBn
DDC_GND
10kΩ
HPD
DDCCLK_B
DDCDAT_B
10kΩ
HPDB
HDMI Connector
100kΩ
HD3SS215
AUX_SEL and Dx_SEL configured for A to C
Figure 9-5. HDMI 2:1 Sink Application Using the RTQ Package
Note
According to the HDMI specification the DDC 2-kΩ pullup resistors can be replaced by
47-kΩ pullups. Figure 9-5 schematic and Figure 10-3 PCB layout example shows 47-kΩ pullup
resistors.
Power Supply Recommendations
The HD3SS215 is designed to operate with a 3.3-V power supply. Levels above those listed in the Absolute
Ratings table should not be used. If using a higher voltage system power supply, a voltage regulator can be used
to step down to 3.3 V. Decoupling capacitors must be used to reduce power supply noise.
Copyright © 2020 Texas Instruments Incorporated
20
Submit Document Feedback
Product Folder Links: HD3SS215 HD3SS215I
HD3SS215, HD3SS215I
SLAS971E – MAY 2014 – REVISED DECEMBER 2020
www.ti.com
10 Layout
10.1 Layout Guidelines
•
•
•
The ESD and EMI protection devices (if used) should be placed as close as possible to the connector.
Place voltage regulators as far away as possible from the high-speed differential pairs.
It is recommended that small decoupling capacitors for the HD3SS215 power rail be placed close to the
device.
•
•
•
•
•
The high-speed differential signal traces should be routed on the top layer to avoid the use of vias and allow
clean interconnects to the mux.
The high speed differential signal traces should be routed parallel to each other as much as possible. It is
recommended the traces be symmetrical.
In order to control impedance for transmission lines, a solid ground plane should be placed next to the high-
speed signal layer. This also provides an excellent low-inductance path for the return current flow.
The power plane should be placed next to the ground plane to create additional high-frequency bypass
capacitance.
Adding test points will cause impedance discontinuity and will therefore negatively impact signal
performance. If test points are used, they should be placed in series and symmetrically. They must not be
placed in a manner that causes stubs on the differential pair.
•
Avoid 90 degree turns in traces. The use of bends in differential traces should be kept to a minimum. When
bends are used, the number of left and right bends should be as equal as possible and the angle of the bend
should be ≥135 degrees. This will minimize any length mismatch caused by the bends and therefore
minimize the impact bends have on EMI.
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: HD3SS215 HD3SS215I
HD3SS215, HD3SS215I
SLAS971E – MAY 2014 – REVISED DECEMBER 2020
www.ti.com
10.2 Layout Example
An example layout for the HD3SS215 shows the device implemented on a 4-layer board. The layout figures
follow the DisplayPort application schematic above. The top layer layout view shows the signal routing for two
sources and one sink. The bottom layer layout view shows the remaining signal routing and a copper pour
implemented for the decoupling capacitors.
Figure 10-1. Top Layer Layout View
Figure 10-2. Bottom Layer Layout View
Copyright © 2020 Texas Instruments Incorporated
22
Submit Document Feedback
Product Folder Links: HD3SS215 HD3SS215I
HD3SS215, HD3SS215I
SLAS971E – MAY 2014 – REVISED DECEMBER 2020
www.ti.com
Figure 10-3. RTQ Layout for 2:1 HDMI Sink Application
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
23
Product Folder Links: HD3SS215 HD3SS215I
HD3SS215, HD3SS215I
SLAS971E – MAY 2014 – REVISED DECEMBER 2020
www.ti.com
11 Device and Documentation Support
11.1 Community Resources
11.2 Trademarks
All trademarks are the property of their respective owners.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2020 Texas Instruments Incorporated
24
Submit Document Feedback
Product Folder Links: HD3SS215 HD3SS215I
PACKAGE OPTION ADDENDUM
www.ti.com
3-Mar-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
HD3SS215IRTQR
HD3SS215IRTQT
HD3SS215IZQER
ACTIVE
ACTIVE
LIFEBUY
QFN
QFN
RTQ
RTQ
ZQE
56
56
50
2000 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
Call TI | NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
HD3SS215I
NIPDAU
HD3SS215I
HD3SS215I
BGA
SNAGCU
MICROSTAR
JUNIOR
HD3SS215IZQET
LIFEBUY
BGA
ZQE
50
250
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
HD3SS215I
MICROSTAR
JUNIOR
HD3SS215IZXHR
HD3SS215IZXHT
HD3SS215RTQR
HD3SS215RTQT
HD3SS215ZQER
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LIFEBUY
NFBGA
NFBGA
QFN
ZXH
ZXH
RTQ
RTQ
ZQE
50
50
56
56
50
2500 RoHS & Green
250 RoHS & Green
2000 RoHS & Green
250 RoHS & Green
SNAGCU
SNAGCU
NIPDAU
NIPDAU
SNAGCU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
HD3SS215I
HD3SS215I
HD3SS215
HD3SS215
HD3SS215
0 to 70
0 to 70
0 to 70
QFN
BGA
2500 RoHS & Green
MICROSTAR
JUNIOR
HD3SS215ZXHR
ACTIVE
NFBGA
ZXH
50
2500 RoHS & Green
SNAGCU
Level-3-260C-168 HR
HD3SS215
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
3-Mar-2021
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Mar-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
HD3SS215IRTQR
HD3SS215IRTQT
HD3SS215IZQER
QFN
QFN
RTQ
RTQ
ZQE
56
56
50
2000
250
330.0
180.0
330.0
16.4
16.4
12.4
8.3
8.3
5.3
8.3
8.3
5.3
1.1
1.1
1.5
12.0
12.0
8.0
16.0
16.0
12.0
Q2
Q2
Q1
BGA MI
CROSTA
R JUNI
OR
2500
HD3SS215IZQET
BGA MI
CROSTA
R JUNI
OR
ZQE
50
250
330.0
12.4
5.3
5.3
1.5
8.0
12.0
Q1
HD3SS215IZXHR
HD3SS215IZXHT
HD3SS215RTQR
HD3SS215RTQT
HD3SS215ZQER
NFBGA
NFBGA
QFN
ZXH
ZXH
RTQ
RTQ
ZQE
50
50
56
56
50
2500
250
330.0
330.0
330.0
180.0
330.0
12.4
12.4
16.4
16.4
12.4
5.3
5.3
8.3
8.3
5.3
5.3
5.3
8.3
8.3
5.3
1.5
1.5
1.1
1.1
1.5
8.0
8.0
12.0
12.0
16.0
16.0
12.0
Q1
Q1
Q2
Q2
Q1
2000
250
12.0
12.0
8.0
QFN
BGA MI
CROSTA
R JUNI
OR
2500
HD3SS215ZXHR
NFBGA
ZXH
50
2500
330.0
12.4
5.3
5.3
1.5
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Mar-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
HD3SS215IRTQR
HD3SS215IRTQT
HD3SS215IZQER
QFN
QFN
RTQ
RTQ
ZQE
56
56
50
2000
250
367.0
210.0
336.6
367.0
185.0
336.6
38.0
35.0
31.8
BGA MICROSTAR
JUNIOR
2500
HD3SS215IZQET
BGA MICROSTAR
JUNIOR
ZQE
50
250
336.6
336.6
31.8
HD3SS215IZXHR
HD3SS215IZXHT
HD3SS215RTQR
HD3SS215RTQT
HD3SS215ZQER
NFBGA
NFBGA
QFN
ZXH
ZXH
RTQ
RTQ
ZQE
50
50
56
56
50
2500
250
336.6
336.6
367.0
210.0
336.6
336.6
336.6
367.0
185.0
336.6
31.8
31.8
38.0
35.0
31.8
2000
250
QFN
BGA MICROSTAR
JUNIOR
2500
HD3SS215ZXHR
NFBGA
ZXH
50
2500
336.6
336.6
31.8
Pack Materials-Page 2
PACKAGE OUTLINE
TM
ZQE0050A
BGA MicroStar Jr - 1 mm max height
SCALE 2.500
PLASTIC BALL GRID ARRAY
5.1
4.9
B
A
BALL A1 CORNER
INDEX AREA
5.1
4.9
(0.74)
C
1 MAX
SEATING PLANE
0.08 C
0.25
TYP
0.15
BALL TYP
4 TYP
SYMM
(0.5) TYP
J
H
G
F
(0.5) TYP
SYMM
4
E
D
C
TYP
0.35
50X
0.25
0.15
0.05
C A
C
B
B
A
0.5 TYP
1
2
3
4
5
6
7
8
9
0.5 TYP
4221625/A 02/2015
MicroStar Junior is trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration MO-225.
www.ti.com
EXAMPLE BOARD LAYOUT
TM
ZQE0050A
BGA MicroStar Jr - 1 mm max height
PLASTIC BALL GRID ARRAY
50X ( 0.28)
(0.5) TYP
3
4
5
6
7
8
9
1
2
A
B
C
(0.5) TYP
D
E
F
G
H
J
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:15X
0.05 MAX
0.05 MIN
METAL UNDER
SOLDER MASK
(
0.28)
METAL
(
0.28)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4221625/A 02/2015
NOTES: (continued)
4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SSYZ015 (www.ti.com/lit/ssyz015).
www.ti.com
EXAMPLE STENCIL DESIGN
TM
ZQE0050A
BGA MicroStar Jr - 1 mm max height
PLASTIC BALL GRID ARRAY
50X ( 0.28)
(R0.05) TYP
(0.5) TYP
A
1
2
4
5
6
8
9
3
7
(0.5) TYP
B
C
D
E
F
G
H
J
METAL
TYP
SYMM
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:20X
4221625/A 02/2015
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
PACKAGE OUTLINE
NFBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
ZXH0050A
A
5.1
4.9
B
BALL A1 CORNER
5.1
4.9
C
1 MAX
SEATING PLANE
0.08 C
0.25
0.15
BALL TYP
(0.5) TYP
4 TYP
J
(0.5) TYP
H
G
F
SYMM
4
TYP
E
D
C
0.35
50X Ø
B
A
0.25
0.15
0.05
C A B
C
0.5 TYP
1
2
3
4
5
6
7
8
9
0.5 TYP
SYMM
4225134/A 08/2019
NOTES:
NanoFree is a trademark of Texas Instruments.
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
NFBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
ZXH0050A
(0.5) TYP
3
1
2
4
5
6
7
8
9
A
B
(0.5) TYP
C
D
E
F
SYMM
50X (Ø0.25)
G
H
J
SYMM
LAND PATTERN EXAMPLE
SCALE: 20X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
EXPOSED
METAL
(Ø 0.25)
SOLDER MASK
OPENING
EXPOSED
METAL
(Ø 0.25)
METAL
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON- SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4225134/A 08/2019
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. Refer to Texas Instruments
Literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
NFBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
ZXH0050A
(0.5) TYP
3
1
2
4
5
6
7
8
9
A
B
(0.5) TYP
C
D
E
F
METAL
TYP
SYMM
(R0.05) TYP
G
H
J
50X ( 0.25)
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.100 mm THICK STENCIL
SCALE: 20X
4225134/A 08/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
GENERIC PACKAGE VIEW
RTQ 56
8 x 8, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224653/A
www.ti.com
PACKAGE OUTLINE
RTQ0056B
VQFN - 1 mm max height
S
C
A
L
E
1
.
5
0
0
PLASTIC QUAD FLATPACK - NO LEAD
8.15
7.85
A
B
PIN 1 INDEX AREA
8.15
7.85
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
2X 6.5
4.5 0.1
SYMM
(0.2) TYP
EXPOSED
THERMAL PAD
28
15
14
29
SYMM
57
2X 6.5
5.2 0.1
1
42
52X 0.5
PIN 1 ID
0.30
0.18
56
43
56X
0.5
0.3
0.1
C A B
56X
0.05
4219130/B 11/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RTQ0056B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(4.5)
(0.73) TYP
(1.27) TYP
SEE SOLDER MASK
56X (0.6)
56X (0.24)
DETAIL
56
43
1
42
52X (0.5)
(1.08) TYP
(R0.05) TYP
(1.27) TYP
(7.8)
57
SYMM
(5.2)
(
0.2) TYP
VIA
14
29
28
15
SYMM
(7.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219130/B 11/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RTQ0056B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.46) TYP
56X (0.6)
56X (0.24)
43
56
1
42
52X (0.5)
(R0.05) TYP
(1.27) TYP
57
(0.635) TYP
(7.8)
SYMM
12X (1.07)
METAL
TYP
14
29
15
28
SYMM
12X (1.26)
(7.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 10X
EXPOSED PAD 57
69% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4219130/B 11/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,
costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either
on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s
applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明