HD3SS3212IRKSR [TI]
USB 3.1 两通道差分 2:1/1:2 10Gbps 多路复用器/多路信号分离器 | RKS | 20 | -40 to 85;
| 型号： | HD3SS3212IRKSR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | USB 3.1 两通道差分 2:1/1:2 10Gbps 多路复用器/多路信号分离器 | RKS | 20 | -40 to 85 复用器 |
| 文件： | 总25页 (文件大小：1358K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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HD3SS3212, HD3SS3212I
ZHCSDQ7 –MAY 2015
HD3SS3212x 双通道差分 2:1/1:2 USB3.1 复用器/解复用器
1 特性
3 说明
1
•
提供面向支持 USB3.1 第 1 代和第 2 代数据传输速
率的 USB Type-C™ 生态系统的复用器/解复用器
解决方案
HD3SS3212 是一款高速双向无源开关，可采用复用或
解复用两种配置，适用于支持 USB3.1 第 1 代和第 2
代数据传输速率的 USB Type-C™ 应用。 该器件可通
过控制引脚 SEL 在两个差分通道（端口 B 到端口 A，
或者端口 C 到端口 A）间切换。
•
兼容 MIPI DSI/CSI、FPDLinkIII、LVDS 和 PCIE
的第 II 代和第 III 代
•
•
•
运行速率高达 10Gbps
HD3SS3212 是一款通用模拟差分无源开关，可满足任
何高速接口应用对于 0-2V 共模电压范围和差分幅值高
达 1800mVpp 的差分信令的需求。 该器件采用自适应
跟踪，可确保信道在整个共模电压范围内保持不变。
-3dB 差分带宽宽达 8GHz 以上
出色动态特性（5GHz 时）
–
–
–
–
串扰 = –32dB
断开隔离 = –19dB
插入损耗 = –1.6dB
回波损耗 = –12dB
该器件具有出色的动态特性，可在信号眼图衰减最小的
情况下实现高速转换，并且附加抖动极少。 该器件在
工作模式下的功耗 < 2mW，关断模式下的功耗
< 20µW（可通过 OEn 引脚切换模式）。
•
•
•
•
•
双向“复用/解复用”差分开关
支持 0 到 2V 共模电压
单电源电压 VCC：3.3V±10%
器件信息(1)
0°C 至 70°C 的商用温度范围 (HD3SS3212RKS)
器件型号
HD3SS3212
HD3SS3212I
封装
封装尺寸（标称值）
-40°C 至 85°C 的工业温度范围
(HD3SS3212IRKS)
2.50mm × 4.50mm ×
0.5mm 间距
VQFN (20)
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
2 应用
•
•
•
•
•
•
USB Type-C™ 生态系统
台式机和笔记本个人电脑 (PC)
服务器/储存区网络
PCI EXPress 背板
共享 I/O 端口
FPDLinkII 和 FPDLinkIII 开关
4 简化电路原理图
1
20
2
3
4
5
6
7
8
9
19
OEn
A0p
A0n
B0p
B0n
B1p
18
17
16
15
14
13
12
GND
B1n
C0p
C0n
VCC
A1p
A1n
SEL
C1p
C1n
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLASE74
HD3SS3212, HD3SS3212I
ZHCSDQ7 –MAY 2015
www.ti.com.cn
目录
10.1 Overview ................................................................. 8
10.2 Functional Block Diagram ....................................... 8
10.3 Feature Description................................................. 8
10.4 Device Functional Modes........................................ 9
11 Application and Implementation........................ 10
11.1 Application Information.......................................... 10
11.2 Typical Applications .............................................. 13
12 Power Supply Recommendations ..................... 17
13 Layout................................................................... 17
13.1 Layout Guidelines ................................................. 17
13.2 Layout Example .................................................... 17
14 器件和文档支持 ..................................................... 18
14.1 相关链接................................................................ 18
14.2 社区资源................................................................ 18
14.3 商标....................................................................... 18
14.4 静电放电警告......................................................... 18
14.5 术语表 ................................................................... 18
15 机械、封装和可订购信息....................................... 18
1
2
3
4
5
6
7
8
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
简化电路原理图........................................................ 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
8.1 Absolute Maximum Ratings ...................................... 4
8.2 ESD Ratings.............................................................. 4
8.3 Recommended Operating Conditions....................... 4
8.4 Thermal Information.................................................. 4
8.5 Electrical Characteristics........................................... 5
8.6 High-Speed Performance Parameters...................... 5
8.7 Switching Characteristics.......................................... 6
Parameter Measurement Information .................. 6
9
10 Detailed Description ............................................. 8
5 修订历史记录
日期
修订版本
注释
2015 年 5 月
*
首次发布。
2
Copyright © 2015, Texas Instruments Incorporated
HD3SS3212, HD3SS3212I
www.ti.com.cn
ZHCSDQ7 –MAY 2015
6 Device Comparison Table
OPERATING TEMPERATURE (°C)
PACKAGE(1)(2)
ORDERABLE PART NUMBER
0 to 70
RKS
RKS
20 pins
20 pins
HD3SS3212RKSR
HD3SS3212IRKSR
–40 to 85
(1) For the most current package and ordering information, see 机械、封装和可订购信息.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
7 Pin Configuration and Functions
RKS Package
20-Pin VQFN
Top View
1
20
2
3
4
5
6
7
8
9
19
OEn
A0p
A0n
B0p
B0n
B1p
18
17
16
15
14
13
12
GND
B1n
C0p
C0n
VCC
A1p
A1n
SEL
C1p
C1n
Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
VCC
6
P
3.3-V power
Active-low chip enable
L: Normal operation
H: Shutdown
OEn
2
I
A0p
A0n
3
I/O
I/O
G
Port A, channel 0, high-speed positive signal
Port A, channel 0, high-speed negative signal
Ground
4
GND
A1p
A1n
5, 11, 20
7
8
I/O
I/O
Port A, channel 1, high-speed positive signal
Port A, channel 1, high-speed negative signal
Port select pin. Internally tied to GND via 100-kΩ resistor.
L: Port A to Port B
SEL
9
I
H: Port A to Port C
C1n
C1p
C0n
C0p
B1n
B1p
B0n
B0p
NC
12
13
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
Port C, channel 1, high-speed negative signal (connector side)
Port C, channel 1, high-speed positive signal (connector side)
Port C, channel 0, high-speed negative signal (connector side)
Port C, channel 0, high-speed positive signal (connector side)
Port B, channel 1, high-speed negative signal (connector side)
Port B, channel 1, high-speed positive signal (connector side)
Port B, channel 0, high-speed negative signal (connector side)
Port B, channel 0, high-speed positive signal (connector side)
These are no connect pins but can be tied to VCC or GND
14
15
16
17
18
19
1, 10
(1) The high-speed data ports incorporate 20-kΩ pulldown resistors that are switched in when a port is not selected and switched out when
the port is selected.
Copyright © 2015, Texas Instruments Incorporated
3
HD3SS3212, HD3SS3212I
ZHCSDQ7 –MAY 2015
www.ti.com.cn
8 Specifications
8.1 Absolute Maximum Ratings
(1)
see
MIN
–0.5
–0.5
–0.5
–65
MAX
4
UNIT
V
VCC
Supply voltage
Voltage
Differential I/O
Control pins
2.5
VCC+ 0.5
150
Tstg
Storage temperature
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
8.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
3.6
VCC
0.8
1.8
2
UNIT
V
VCC
Vih
Supply voltage
3
2
Input high voltage (SEL, OEn pins)
Input low voltage (SEL, OEn pins)
High-speed signal pins differential voltage
High speed signal pins common mode voltage
V
Vil
–0.1
0
V
Vdiff
Vcm
Vpp
V
0
HD3SS3212RKS
HD3SS3212IRKS
0
70
TA
Operating free-air/ambient temperature
°C
–40
85
8.4 Thermal Information
HD3SS3212
RKS (VQFN)
20 PINS
46.6
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
41.8
4.4
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
17.6
ψJB
1.6
RθJC(bot)
17.6
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
Copyright © 2015, Texas Instruments Incorporated
HD3SS3212, HD3SS3212I
www.ti.com.cn
ZHCSDQ7 –MAY 2015
8.5 Electrical Characteristics
PARAMETER
TEST CONDITIONS
VCC = 3.3 V, OEn = 0
MIN
TYP
0.6
5
MAX
0.8
UNIT
mA
µA
pF
ICC
Device active current
Device shutdown current
Output ON capacitance
Output OFF capacitance
Output ON resistance
ISTDN
CON
COFF
RON
VCC = 3.3 V, OEn = VCC
20
0.6
0.8
5
pF
VCC = 3.3 V; VCM = 0 to 2 V; IO = –8
mA
8
0.5
1
Ω
ΔRON
On-resistance match between pairs of the
same channel
VCC = 3.3 V; –0.35 V ≤ VIN ≤ 2.35 V;
IO = –8 mA
Ω
Ω
RFLAT_ON
On-resistance flatness RON(MAX) –
RON(MAIN)
VCC = 3.3 V; –0.35 V ≤ VIN ≤ 2.35 V
IIH,CTRL
IIL,CTRL
IIH,HS
Input high current, control pins (SEL, OEn)
Input low current, control pins (SEL, OEn)
1
1
1
µA
µA
µA
Input high current, high-speed pins
[Ax/Bx/Cx][p/n]
VIN = 2 V for selected port, A and B
with SEL = 0, and A and C with SEL
= VCC
IIH,HS
Input high current, high-speed pins
[Ax/Bx/Cx][p/n]
VIN = 2 V for non-selected port, C
with SEL = 0, and B with SEL =
VCC
100
140
1
µA
µA
(1)
IIL,HS
Input low current, high-speed pins
[Ax/Bx/Cx][p/n]
(1) There is a 20-kΩ pull-down in non-selected port.
8.6 High-Speed Performance Parameters
PARAMETER
TEST CONDITION
MIN
TYP
–0.5
-0.55
–0.8
–1.4
–1.6
8
MAX
UNIT
ƒ = 0.3 MHz
f = 0.625 MHz
IL
Differential insertion loss
ƒ = 2.5 GHz
ƒ = 4 GHz
ƒ = 5 GHz
dB
BW
RL
–3-dB bandwidth
GHz
dB
ƒ = 0.3 MHz
ƒ = 2.5 GHz
ƒ = 4 GHz
ƒ = 5 GHz
ƒ = 0.3 MHz
ƒ = 2.5 GHz
ƒ = 4 GHz
ƒ = 5 GHz
ƒ = 0.3 MHz
ƒ = 2.5 GHz
ƒ = 4 GHz
ƒ = 5 GHz
–25
–13
–13
– 12
–75
–23
–19
–19
–90
–35
–32.5
–32
Differential return loss
OIRR
Differential OFF isolation
Differential crosstalk
dB
dB
XTALK
Copyright © 2015, Texas Instruments Incorporated
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HD3SS3212, HD3SS3212I
ZHCSDQ7 –MAY 2015
www.ti.com.cn
8.7 Switching Characteristics
PARAMETER
MIN
TYP
MAX
UNIT
ps
tPD
Switch propagation delay (see Figure 3)
80
0.5
0.5
6
tSW_ON
tSW_OFF
tSK_INTRA
tSK_INTER
Switching time SEL-to-Switch ON (see Figure 2)
Switching time SEL-to-Switch OFF (see Figure 2)
Intra-pair output skew (see Figure 3)
µs
µs
ps
Inter-pair output skew (see Figure 3)
20
ps
9 Parameter Measurement Information
VCC
RSC = 50
Bxp/Cxp
Bxn/Cxn
Axp
RL = 50
RL = 50
RSC = 50
Axn
Figure 1. Test Setup
50%
50%
SEL
90%
10%
VOUT
tSW_ON
tSW_OFF
Figure 2. Switch On and Off Timing Diagram
6
Copyright © 2015, Texas Instruments Incorporated
HD3SS3212, HD3SS3212I
www.ti.com.cn
ZHCSDQ7 –MAY 2015
Parameter Measurement Information (continued)
2.6-V Max
50%
50%
VIN
0 V
2.6-V Max
50%
50%
VOUT
0 V
tPD
VOUTp
VOUTn
50%
TSK_INTRA
B0/C0
VOUT
50%
50%
50%
50%
B1/C1
VOUT
tSK_INTER
Figure 3. Timing Diagrams and Test Setup
Copyright © 2015, Texas Instruments Incorporated
7
HD3SS3212, HD3SS3212I
ZHCSDQ7 –MAY 2015
www.ti.com.cn
10 Detailed Description
10.1 Overview
The HD3SS3212 is a generic analog differential passive switch that can work for any high-speed interface
applications requiring a common mode voltage range of 0 to 2 V and differential signaling with differential
amplitude up to 1800 mVpp. It employs adaptive tracking that ensures the channel remains unchanged for the
entire common mode voltage range.
Excellent dynamic characteristics of the device allow high-speed switching with minimum attenuation to the
signal eye diagram with very little added jitter. It consumes <2 mW of power when operational and has a
shutdown mode exercisable by OEn pin resulting <20 µW.
10.2 Functional Block Diagram
10.3 Feature Description
10.3.1 Output Enable and Power Savings
The HD3SS3212 has two power modes, active/normal operating mode and standby/shutdown mode. During
standby mode, the device consumes very-little current to save the maximum power. To enter standby mode, the
OEn control pin is pulled high through a resistor and must remain high. For active/normal operation, the OEn
control pin should be pulled low to GND or dynamically controlled to switch between H or L.
HD3SS3212 consumes <2 mW of power when operational and has a shutdown mode exercisable by the EN pin
resulting <20 µW.
8
Copyright © 2015, Texas Instruments Incorporated
HD3SS3212, HD3SS3212I
www.ti.com.cn
ZHCSDQ7 –MAY 2015
10.4 Device Functional Modes
Table 1. Port Select Control Logic(1)
Port B or Port C Channel Connected to Port A Channel
Port A Channel
SEL = L
B0p
SEL = H
C0p
A0p
A0n
A1p
A1n
B0n
C0n
B1p
C1p
B1n
C1n
(1) The HD3SS3212 can tolerate polarity inversions for all differential signals on Ports A, B, and C. Take
care to ensure the same polarity is maintained on Port A versus Ports B/C.
Copyright © 2015, Texas Instruments Incorporated
9
HD3SS3212, HD3SS3212I
ZHCSDQ7 –MAY 2015
www.ti.com.cn
11 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
11.1 Application Information
The HD3SS3212 is a generic 2-channel high-speed mux/demux type of switch that can be used for routing high-
speed signals between two different locations on a circuit board. The HD3SS3212 supports several high-speed
data protocols with a differential amplitude of <1800 mVpp and a common mode voltage of <2.0 V, as with USB
3.0 and DisplayPort 1.2. The device’s one select input (SEL) pin can easily be controlled by an available GPIO
pin within a system or from a microcontroller.
The HD3SS3212 with its adaptive common mode tracking technology can support applications where the
common mode is different between the RX and TX pair. The two USB3.1 Type C connector applications show
both a host and device side. The cable between the two connectors swivels the pairs to properly route the
signals to the correct pin. The other applications are more generic because different connectors can be used.
Many interfaces require AC coupling between the transmitter and receiver. The 0402 capacitors are the preferred
option to provide AC coupling; 0603 size capacitors also work. Avoid the 0805 size capacitors and C-packs.
When placing AC coupling capacitors, symmetric placement is best. A capacitor value of 0.1 µF is best, and the
value should match for the ±signal pair. The designer should place them along the TX pairs on the system board,
which are usually routed on the top layer of the board.
The AC coupling capacitors have several placement options. Because the switch requires a bias voltage, the
designer must place the capacitors on one side of the switch. If they are placed on both sides of the switch, a
biasing voltage should be provided. Figure 4 shows a few placement options. The coupling capacitors are placed
between the switch and endpoint. In this situation, the switch is biased by the system/host controller.
0.1uF
RX
Port B
Device/
TX
Endpoint
Port C
System/Host
controller
TX
0.1uF
Port B
RX
RX
Device/
Endpoint
0.1uF
Port C
TX
0.1uF
Figure 4. AC Coupling Capacitors between Switch TX and Endpoint TX
In Figure 5, the coupling capacitors are placed on the host transmit pair and endpoint transmit pair. In this
situation, the switch on top is biased by the endpoint and the lower switch is biased by the host controller.
10
Copyright © 2015, Texas Instruments Incorporated
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www.ti.com.cn
ZHCSDQ7 –MAY 2015
Application Information (continued)
RX
0.1uF
Port B
Device/
Endpoint
TX
Port C
Port B
System/Host
controller
TX
0.1uF
RX
RX
Device/
Endpoint
Port C
TX
0.1uF
Figure 5. AC Coupling Capacitors on Host TX and Endpoint TX
In the case where the common mode voltage in the system is higher than 2 V, the coupling capacitors are placed
on both sides of the switch (shown in Figure 6). A biasing voltage of <2 V is required in this case.
VBIAS
RX
Port B
Device/
TX
Endpoint
VBIAS
Port C
System/Host
TX
controller
Port B
RX
RX
Device/
Endpoint
Port C
VBIAS can be GND
Capacitor and Resistor values depend upon application
TX
Figure 6. AC Coupling Capacitors on Both Sides of Switch
The HD3SS3212 can be used with the USB Type C connector to support the connector’s flip ability. Figure 7
provides the generic location for the AC coupling capacitors for this application.
Copyright © 2015, Texas Instruments Incorporated
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HD3SS3212, HD3SS3212I
ZHCSDQ7 –MAY 2015
www.ti.com.cn
Application Information (continued)
Down Facing Port
Up Facing Port
TX1+
RX1+
TX1±
RX1±
RX+
TX+
RX1+ 0.1 µF
TX1+
RX±
TX
RX
TX±
RX1±
TX1±
System/Host
Controller
Hub
0.1 µF
TX2+
RX2+
TX+
RX+
TX2±
RX2±
TX
TX±
RX
RX±
0.1 µF
RX2+
TX2+
RX2±
TX2±
0.1 µF
Figure 7. AC Coupling Capacitors for USB Type C
12
Copyright © 2015, Texas Instruments Incorporated
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www.ti.com.cn
ZHCSDQ7 –MAY 2015
11.2 Typical Applications
11.2.1 Down Facing Port for USB3.1 Type C
HD3SS3212
19
A2
A3
B0+
SSTXp1
A1
GND
GND
GND
GND
18
SSTXn1
B0±
B12
0.1 µF
SSTXp
3
A0+
15
14
17
16
13
B2
C0+
C0±
B1+
B1±
C1+
A12
B1
SSTXp2
SSTXn2
0.1 µF
SSTXn
4
7
A0-
B3
SSRXp
A1+
B11
B10
A11
A10
A5
SSRXp1
SSRXn1
SSRXp2
SSRXn2
CC1
8
2
SSRXn
A1-
USB Host
OEn
Optional
Controller
9
1
SEL
NC
12
5
10 N
C1±
GND
10 NC
VCC
11
20
GND
GND
B5
CC2
10 µF
0.1 µF
0.01 µF
6
VCC
USB C
CC
Controller
Figure 8. Down Facing Port for USB3.1 Type C Connector
11.2.1.1 Design Requirements
The HD3SS3212 can be designed into many different applications. All the applications have certain requirements
for the system to work properly. The HD3SS3212 requires 3.3-V ±10% VCC rail. The OEn pin must be low for
device to work otherwise it disables the outputs. This pin can be driven by a processor. The expectation is that
one side of the device has AC coupling capacitors. Table 2 provides information on expected values to perform
properly.
Table 2. Design Parameters
DESIGN PARAMETER
VALUE
3.3 V
VCC
AXp/n, BXp/n, CXp/n CM input voltage
Control/OEn pin max voltage for low
Control/OEn pin min voltage for high
AC coupling capacitor
0 to 2 V
0.8 V
2.0 V
100 nF
1 kΩ
RBIAS (Figure 8) when needed
11.2.1.2 Detailed Design Procedure
The HD3SS3212 is a high-speed passive switch device that can behave as a mux or demux. Because this is a
passive switch, signal integrity is important because the device provides no signal conditioning capability. The
device can support 2 to 3 inches of board trace and a connector on either end.
To design in the HD3SS3212, the designer needs to understand the following.
•
•
•
•
•
Determine the loss profile between circuits that are to be muxed or demuxed.
Provide clean impedance and electrical length matched board traces.
Depending upon the application, determine the best place to put the 100-nF coupling capacitor.
Provide a control signal for the SEL and OEn pins.
The thermal pad must be connected to ground.
Copyright © 2015, Texas Instruments Incorporated
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HD3SS3212, HD3SS3212I
ZHCSDQ7 –MAY 2015
www.ti.com.cn
•
See the application schematics on recommended decouple capacitors from VCC pins to ground
11.2.1.3 Application Curves
Figure 9. 10 Gbps Source Eye Diagram
Figure 10. 10 Gbps Output Eye Diagram
11.2.2 Up Facing Port for USB3.1 Type C
HD3SS3212
19
A2
A3
SSTXp1
SSTXn1
B0+
A1
GND
GND
GND
GND
18
15
14
17
16
13
B0±
A0+
C0+
B12
3
SSRXp
B2
A12
B1
SSTXp2
SSTXn2
4
7
A0±
SSRXn
SSTXp
B3
C0±
A1+
B1+
0.1 µF
0.1 µF
B11
B10
A11
A10
A5
SSRXp1
SSRXn1
SSRXp2
SSRXn2
CC1
8
2
9
A1±
SSTXn
B1±
OEn
C1+
SEL
USB Device
Optional
Controller
12
5
C1±
GND
NC
NC
1
10
10 N
11
20
VCC
GND
B5
GND
CC2
10 µF
6
0.1 µF
USB C
0.01 µF
VCC
CC
Controller
Figure 11. Up Facing Port for USB3.1 USB Type-C Connector
14
Copyright © 2015, Texas Instruments Incorporated
HD3SS3212, HD3SS3212I
www.ti.com.cn
ZHCSDQ7 –MAY 2015
11.2.3 PCIE/SATA/USB
HD3SS3212
19
B0+
B0±
B1+
B1±
TXp1
18
17
16
TXn1
RXp1
RXn1
0.1 µF
0.1 µF
3
TXp
A0+
4
7
A0±
TXn
RXp
Con
Con
A1+
15
14
13
12
C0+
C0±
C1+
8
2
9
TXp2
TXn2
RXp2
RXn2
RXn
A1±
OEn
SEL
PCIE/USB/
SATA
Optional
C1±
GND
GND
GND
Controller
5
10 N
11
20
VCC
6
1
10
10 µF
0.1 µF
0.1 µF
0.01 µF
VCC
Figure 12. PCIE Motherboard
11.2.4 PCIE/eSATA
HD3SS3212
PCIE Controller
RXp1
19
B0+
18
B0±
RXn1
TXp1
TXn1
3
TXp
A0+
0.1 µF
15
14
B1+
4
7
TXn
RXp
0.1 µF
A0±
B1±
A1+
17
16
13
12
8
2
9
1
RXp2
RXn2
TXp2
TXn2
C0+
RXn
A1±
MINI CARD
mSATA Con
Optional
C0±
OEn
0.1 µF
0.1 µF
C1+
SEL
NC
C1±
GND
GND
GND
Controller
5
10 NC
eSATA Controller
10 N
11
20
VCC
6
VCC
10 µF
0.1 µF
0.01 µF
Figure 13. PCIE and eSATA Combo
Copyright © 2015, Texas Instruments Incorporated
15
HD3SS3212, HD3SS3212I
ZHCSDQ7 –MAY 2015
www.ti.com.cn
11.2.5 USB/eSATA
HD3SS3212
USB Controller
RXp1
19
B0+
18
15
14
B0±
RXn1
TXp1
TXn1
3
TXp
A0+
0.1 µF
0.1 µF
B1+
4
7
TXn
RXp
A0±
B1±
A1+
17
16
13
12
8
2
9
1
RXp2
RXn2
TXp2
TXn2
C0+
RXn
A1±
USB/eSATA
C0±
OEn
Con
0.1 µF
0.1 µF
C1+
SEL
NC
Optional
C1±
GND
GND
GND
Controller
5
10 NC
10 N
eSATA Controller
11
20
VCC
6
VCC
10 µF
0.1 µF
0.01 µF
Figure 14. eSATA and USB 3.0 Combo Connector
11.2.6 MIPI Camera Serial Interface
HD3SS3212
CSI Camera
19
B0+
B0±
B1+
B1±
D0p
18
15
14
D0n
3
D0p
A0+
CLKp
CLKn
4
7
D0n
A0±
CLKp
A1+
17
16
13
12
C0+
8
2
9
1
D0p
CLKn
CSI RX
Chipset
A1±
C0±
D0n
OEn
C1+
CLKp
CLKn
Optional
SEL
NC
Controller
C1±
GND
GND
GND
5
10 NC
10 N
CSI Camera
11
20
VCC
6
VCC
10 µF
0.1 µF
0.01 µF
Figure 15. CSI Camera Array
16
Copyright © 2015, Texas Instruments Incorporated
HD3SS3212, HD3SS3212I
www.ti.com.cn
ZHCSDQ7 –MAY 2015
12 Power Supply Recommendations
The HD3SS3212 does not require a power supply sequence. However, TI recommends that OEn is asserted low
after device supply VCC is stable and in specification. TI also recommends to place ample decoupling capacitors
at the device VCC near the pin.
13 Layout
13.1 Layout Guidelines
On a high-K board, TI always recommends to solder the PowerPAD™ onto the thermal land. A thermal land is
the area of solder-tinned-copper underneath the PowerPAD package. On a high-K board, the HD3SS3212 can
operate over the full temperature range by soldering the PowerPAD onto the thermal land without vias.
On a low-K board, for the device to operate across the temperature range, the designer must use a 1-oz Cu
trace connecting the GND pins to the thermal land. A general PCB design guide for PowerPAD packages is
provided in PowerPAD Thermally-Enhanced Package, SLMA002.
13.2 Layout Example
Match High Speed traces
length as close as possible to
minimize Skew
OEn and SEL can be controlled
by the microcontroller. OEn
can also be tied to Vcc with
resistor
OEn
B0p
B0n
100nF
A0p
A0n
100nF
B1p
B1n
C0p
C0n
GND
VCC
A1p
A1n
SEL
C1p
C1n
Match High Speed traces
length as close as possible to
minimize Skew
Place VCC decoupling caps as
close to VCC pins as possible
Figure 16. HD3SS3212 Basic Layout Example for Application Shown
in Down Facing Port for USB3.1 Type C
版权 © 2015, Texas Instruments Incorporated
17
HD3SS3212, HD3SS3212I
ZHCSDQ7 –MAY 2015
www.ti.com.cn
14 器件和文档支持
14.1 相关链接
以下表格列出了快速访问链接。 范围包括技术文档、支持与社区资源、工具和软件，并且可以快速访问样片或购买
链接。
表 3. 相关链接
器件
产品文件夹
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
支持与社区
请单击此处
请单击此处
HD3SS3212
HD3SS3212I
14.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
14.3 商标
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
14.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
14.5 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
15 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不
对本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
18
版权 © 2015, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
HD3SS3212IRKSR
HD3SS3212IRKST
HD3SS3212RKSR
HD3SS3212RKST
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VQFN
VQFN
VQFN
VQFN
RKS
RKS
RKS
RKS
20
20
20
20
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
0 to 70
HD3212I
NIPDAU
NIPDAU
NIPDAU
HD3212I
HDS3212
HDS3212
0 to 70
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
GENERIC PACKAGE VIEW
RKS 20
2.5 x 4.5, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226872/A
www.ti.com
PACKAGE OUTLINE
RKS0020A
VQFN - 1 mm max height
S
C
A
L
E
3
.
3
0
0
PLASTIC QUAD FLATPACK - NO LEAD
2.6
2.4
B
A
PIN 1 INDEX AREA
4.6
4.4
0.1 C
C
1.0
0.8
SEATING PLANE
0.08 C
0.05
0.00
1
0.1
2X 0.5
(0.2) TYP
11
10
14X 0.5
EXPOSED
THERMAL PAD
9
12
2X
3.5
3
0.1
2
19
0.30
0.18
20X
1
20
PIN 1 ID
(OPTIONAL)
0.1
C A B
0.5
0.3
20X
0.05
4222490/B 02/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RKS0020A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1)
SYMM
1
20
20X (0.6)
2
19
20X (0.24)
(1.25)
SYMM
(3)
(4.3)
16X (0.5)
(R0.05) TYP
12
9
(
0.2) VIA
TYP
10
11
(2.3)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222490/B 02/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
www.ti.com
EXAMPLE STENCIL DESIGN
RKS0020A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
2X (0.95)
20
1
20X (0.6)
2
19
20X (0.24)
2X (1.31)
16X (0.5)
SYMM
(4.3)
(0.76)
METAL
TYP
9
12
(R0.05) TYP
11
10
SYMM
(2.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
83% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4222490/B 02/2021
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
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