HD3SS3411TRWARQ1 [TI]
3.3V 汽车级 PCI Express 3.0 单通道模拟差动开关 | RWA | 14 | -40 to 105;
| 型号： | HD3SS3411TRWARQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3V 汽车级 PCI Express 3.0 单通道模拟差动开关 | RWA | 14 | -40 to 105 开关 PC |
| 文件： | 总23页 (文件大小：1119K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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HD3SS3411-Q1
ZHCSE09A –JUNE 2015–REVISED JULY 2015
HD3SS3411-Q1 单通道差分 2:1 复用器/解复用器
1 特性
3 说明
1
•
•
符合汽车级 Q100 标准
HD3SS3411-Q1 是一款高速双向无源开关，可采用复
用器或解复用器两种配置。 该器件可通过控制引脚
SEL 在两个差分通道（端口 B 到端口 A，或者端口 C
到端口 A）间切换。
兼容多种接口标准，包括 FPD-Link、LVDS、PCIE
第 II 代和第 III 代、XAUI 以及 USB3.1
•
•
•
运行速率高达 10Gbps
-3dB 差分带宽宽达 7.5GHz 左右
出色动态特性（4GHz 时）
HD3SS3411-Q1 是一款通用模拟差动无源开关，只要
在 0V 至 2V 的共模电压范围内偏置，并且具有差分幅
值高达 1800mVpp 的差分信令，即可用于任何高速接
口应用。 该器件采用自适应跟踪，可确保信道在整个
共模电压范围内保持不变。
–
–
–
插入损耗 = -1.1dB
回波损耗 = -11.3dB
断开隔离 = –19dB
•
•
•
•
双向“复用/解复用”差分开关
支持 0V 到 2V 共模电压
该器件具有出色的动态特性，可在信号眼图衰减最小的
情况下实现高速转换，并且附加抖动极少。 该器件在
工作模式下的功耗 < 2mW；在关断模式下的功耗
< 2µW（可通过 OEn 引脚切换模式）。
单电源电压 VCC：3.3V±10%
-40°C 至 105°C 的工业温度范围
2 应用
器件信息(1)
•
•
•
•
•
•
车用信息娱乐
器件型号
HD3SS3411-Q1
HD3SS3411I
HD3SS3411
封装
封装尺寸（标称值）
工业数据交换
台式机和笔记本个人电脑 (PC)
服务器/储存区网络
PCI EXPress 背板
共享 I/O 端口
WQFN (14)
3.50mm x 3.50mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
4 简化电路原理图
VCC
Bp
Bn
Ap
An
Cp
Cn
SEL
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLASE82
HD3SS3411-Q1
ZHCSE09A –JUNE 2015–REVISED JULY 2015
www.ti.com.cn
目录
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
简化电路原理图........................................................ 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics........................................... 5
7.6 Timing Requirements................................................ 5
7.7 Typical Characteristics.............................................. 6
Detailed Description .............................................. 7
8.1 Overview ................................................................... 7
8.2 Functional Block Diagram ......................................... 7
8.3 Feature Description................................................... 7
8.4 Device Functional Modes.......................................... 8
9
Application Information and Implementation ..... 9
9.1 Application Information.............................................. 9
9.2 Typical Application .................................................... 9
9.3 Design Requirements.............................................. 10
9.4 Detailed Design Procedure ..................................... 10
9.5 Application Curves .................................................. 12
10 Power Supply Recommendations ..................... 12
11 Layout................................................................... 13
11.1 Layout Guidelines ................................................. 13
11.2 Layout Example .................................................... 14
12 器件和文档支持 ..................................................... 15
12.1 文档支持 ............................................................... 15
12.2 社区资源................................................................ 15
12.3 商标....................................................................... 15
12.4 静电放电警告......................................................... 15
12.5 出口管制提示......................................................... 15
12.6 Glossary................................................................ 15
13 机械、封装和可订购信息....................................... 15
8
5 修订历史记录
Changes from Original (June 2015) to Revision A
Page
•
•
Changed the "Operating free-air Temperature" MAX value From: 85°C To: 105°C in Recommended Operating
Conditions .............................................................................................................................................................................. 4
Changed the MAX value of R(FLAT_ON) From: 0.5 Ω To: 1 Ω in the Electrical Characteristics ............................................... 5
2
Copyright © 2015, Texas Instruments Incorporated
HD3SS3411-Q1
www.ti.com.cn
ZHCSE09A –JUNE 2015–REVISED JULY 2015
6 Pin Configuration and Functions
RWA Package
Top View
OEn
GND
14
1
2
3
4
5
6
Ap
An
13 Bp
12 Bn
11 GND
VCC
GND
RSVD
10 Cp
Cn
9
7
8
SEL
GND
Pin Functions
NAME
Ap
NO
2
TYPE
I/O
DESCRIPTION
Port A, High Speed Positive Signal
Port A, High Speed Negative Signal
Port B, High Speed Positive Signal
Port B, High Speed Negative Signal
Port C, High Speed Positive Signal
Port C, High Speed Negative Signal
An
3
I/O
Bp
13
12
10
9
I/O
Bn
I/O
Cp
I/O
Cn
I/O
5,8,11,14,
Pad
GND
G
Ground
Active Low Chip Enable
L: Normal operation
H: Shutdown
OEn
RSVD
SEL
1
6
7
4
I
I/O
I
Reserved Pin – connect or pull-down to GND
Port select pin
L: Port A to Port B
H: Port A to Port C
VCC
P
3.3 V power
Copyright © 2015, Texas Instruments Incorporated
3
HD3SS3411-Q1
ZHCSE09A –JUNE 2015–REVISED JULY 2015
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings(1)
Over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX
UNIT
Supply voltage range (VCC
)
Absolute minimum/maximum supply voltage range
4
V
Differential I/O
Control pin
2.5
Voltage range
V
VDD + 0.5
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3
NOM
MAX
3.6
VCC
0.8
1.8
2
UNIT
V
VCC
VIH
VIL
Supply voltage
Input high voltage (SEL, OEn Pin)
Input low voltage (SEL OEn Pin)
High speed signal pins differential voltage
Common mode voltage (differential pins)
Operating free-air temperature
2
V
–0.1
0
V
VDiff
VCM
TA
VPP
V
0
–40
105
°C
7.4 Thermal Information
RWA
14 PINS
50.5
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
63.1
26.4
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
2.2
ψJB
26.5
RθJC(bot)
7.3
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
Copyright © 2015, Texas Instruments Incorporated
HD3SS3411-Q1
www.ti.com.cn
ZHCSE09A –JUNE 2015–REVISED JULY 2015
7.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
0.6
0.3
0.6
MAX
0.8
UNITS
mA
ICC
Device active Current
Device shutdown Current
Outputs ON Capacitance
VCC = 3.3 V, OEn = 0
VCC = 3.3 V, OEn = 0
ISTDN
CON
0.6
µA
pF
VCC = 3.3 V; VCM = 0 V to 2 V ;
IO = –8 mA
RON
Output ON resistance
5
8
0.5
1
Ω
Ω
On resistance match between pairs of
the same channel
VCC = 3.3 V ; –0.35 V ≤ VIN ≤ 2.35 V;
IO = –8 mA
ΔRON
On resistance flatness
(RON(MAX) – RON(MAIN)
R(FLAT_ON)
IIH(CTRL)
IIL(CTRL)
VDD = 3.3 V; –0.35 V ≤ VIN ≤ 2.35 V
Ω
Input high current, control pins
(SEL, OEn)
1
µA
µA
Input low current, control pins
(SEL, OEn)
1
[A/B/C][p/n] VIN = 2 V for selected port,
A and B with SEL= 0, and A and C with
SEL = VCC
1
µA
[A/B/C][p/n] VIN = 2 V for non-selected
port, C with SEL= 0, and B with
SEL = VCC
(Note there is a 20 KΩ pull-down in non-
selected port)
IIH(HS)
Input high current, high speed pins
Input low current, high speed pins
100
140
1
µA
µA
IIL(HS)
[A/B/C][p/n]
High Speed Performance
f = 0.3 MHz
f = 2.5 GHz
f = 4 GHz
–0.5
–0.7
–1.1
7.5
IL
Differential Insertion Loss
dB
GHz
dB
BW
RL
-3 dB Bandwidth
f = 0.3 MHz
f = 2.5 GHz
f = 4 GHz
–26.4
–16.6
–11.3
–75
Differential return loss
f = 0.3 MHz
f = 2.5 GHz
f = 4 GHz
OI
Differential OFF isolation
Differential Crosstalk
–22
dB
dB
–19
Xtalk
f = 4 GHz
–35
7.6 Timing Requirements
MIN
NOM
MAX
UNIT
ps
tPD
Switch propagation delay
Switching time
80
0.5
5
tSW
ns
tSK_INTRA
Intra-pair output skew
ps
Copyright © 2015, Texas Instruments Incorporated
5
HD3SS3411-Q1
ZHCSE09A –JUNE 2015–REVISED JULY 2015
www.ti.com.cn
7.7 Typical Characteristics
0
-5
2
0
-2
-10
-15
-20
-25
-30
-4
-6
-8
-10
-12
0
2
4
6
8
10
0
2
4
6
8
10
Frequency (GHz)
Frequency (GHz)
D001
D002
Figure 1. Return Loss vs Frequency
Figure 2. Insertion Loss vs Frequency
6
Copyright © 2015, Texas Instruments Incorporated
HD3SS3411-Q1
www.ti.com.cn
ZHCSE09A –JUNE 2015–REVISED JULY 2015
8 Detailed Description
8.1 Overview
The HD3SS3411-Q1 is a high-speed bi-directional passive switch in mux or demux configurations. Based on
control pin SEL, the device switches one differential channels between Port B or Port C to Port A.
The HD3SS3411-Q1 is a generic analog differential passive switch that can work for any high speed interface
applications as long as it is biased at a common mode voltage range of 0 V to 2 V and has differential signaling
with differential amplitude up to 1800 mVpp. The device employs an adaptive tracking that ensures the channel
remains unchanged for entire common mode voltage range.
Table 1. MUX Pin Connections(1)
PORT B OR PORT C CHANNEL CONNECTED TO PORT A
CHANNEL
PORT A CHANNEL
SEL = L
Bp
SEL = H
Cp
Ap
An
Bn
Cn
(1) The HD3SS3411-Q1 can tolerate polarity inversions for all differential signals on Ports A, B and C.
Care should be taken to ensure the same polarity is maintained on Port A vs. Port B/C.
8.2 Functional Block Diagram
VCC
Bp
Bn
Ap
An
Cp
Cn
SEL
GND
8.3 Feature Description
8.3.1 Output Enable and Power Savings
The HD3SS3411-Q1 has two power modes, normal operating mode and shutdown mode. During shutdown
mode, the device consumes very-little current to save the maximum power. The OEn control pin is used to toggle
between the two modes.
HD3SS3411-Q1 consumes < 2 mW of power when operational and has a shutdown mode exercisable by the
OEn pin resulting < 20 µW.
Copyright © 2015, Texas Instruments Incorporated
7
HD3SS3411-Q1
ZHCSE09A –JUNE 2015–REVISED JULY 2015
www.ti.com.cn
8.4 Device Functional Modes
The OEn control pin selects the functional mode of HD3SS3411-Q1. To enter standby/shutdown mode, the OEn
control pin is pulled high through a resistor and must remain high. For active/normal operation, the OEn control
pin should be pulled low to GND or dynamically controlled to switch between H or L.
Table 2. Device Power Modes
OEn
L
Device State
Normal
Signal Pins
Normal
H
Shutdown
Tri-stated
8
Copyright © 2015, Texas Instruments Incorporated
HD3SS3411-Q1
www.ti.com.cn
ZHCSE09A –JUNE 2015–REVISED JULY 2015
9 Application Information and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
HD3SS3411-Q1 mux channels have independent adaptive common mode tracking allowing RX and TX paths to
have different common mode voltage simplifying system implementation and avoiding inter-operational issues.
HD3SS3411-Q1 mux does not provide common mode biasing for the channel. Therefore, it is required that the
device is biased from either side for all active channels.
The HD3SS3411 supports several high-speed data protocols with a differential amplitude of < 1800 mVpp and a
common mode voltage of < 2 V, as with USB 3.1 and DisplayPort 1.3. The one select input (SEL) pin can be
controlled by an available GPIO pin within a system or from a microcontroller.
9.2 Typical Application
Serializer A
Camera A
VDD33
(3.3V) (1.8V or 3.3V)
VDDIO
DATA
PCLK
Image
Sensor
R(7;0)
G(7;0)
B(7;0)
HS
VS
DE
RGB Display
720p
24-bit color
depth
FSYNC
RIN+
RIN-
I2C
100 ohm STP Cable
PCLK
PDB
OSS_SEL
OEN
LOCK
PASS
I2S AUDIO
(STEREO)
MCLK
Deserializer
DATA
PCLK
MODE_SEL
INTB_IN
Video
Source
SCL
SDA
IDX
DAP
I2C
Serializer B
Figure 3. FPD Link III Application
Copyright © 2015, Texas Instruments Incorporated
9
HD3SS3411-Q1
ZHCSE09A –JUNE 2015–REVISED JULY 2015
www.ti.com.cn
9.3 Design Requirements
For this design example, use the values shown in Table 3.
Table 3. Design Paramerters
PARAMETER
VALUE
3.3 V
VCC voltage
Ap/n, Bp/n, Cp/n CM input voltage
SEL/OEn pin max voltage for low
SEL/OEn pin min voltage for high
0 V to 2 V
0 V
3.3 V
9.4 Detailed Design Procedure
9.4.1 AC Coupling Capacitors
Many interfaces require AC coupling between the transmitter and receiver. The 0402 capacitors are the preferred
option to provide AC coupling, and the 0603 size capacitors will also work. The 0805 size capacitors and C-
packs should be avoided. When placing AC coupling capacitors symmetric placement is best. A capacitor value
of 0.1 µF is best and the value should be match for the ± signal pair. The placement should be along the TX
pairs on the system board, which are usually routed on the top layer of the board.
There are several placement options for the AC coupling capacitors. Because the switch requires a bias voltage,
the capacitors must only be placed on one side of the switch. If they are placed on both sides of the switch, a
biasing voltage should be provided. A few placement options are shown below. In Figure 4, the coupling
capacitors are placed between the switch and endpoint. In this situation, the switch is biased by the system/host
controller.
Figure 4. AC Coupling Capacitors Between Switch TX and Endpoint TX
10
Copyright © 2015, Texas Instruments Incorporated
HD3SS3411-Q1
www.ti.com.cn
ZHCSE09A –JUNE 2015–REVISED JULY 2015
Detailed Design Procedure (continued)
In Figure 5, the coupling capacitors are placed on the host transmit pair and endpoint transmit pair. In this
situation, the switch on the top is biased by the endpoint and the lower switch is biased by the host controller.
Figure 5. AC Coupling Capacitors on Host TX and Endpoint TX
If the common mode voltage in the system is higher than 2 V, the coupling capacitors are placed on both sides of
the switch (shown in Figure 6). A biasing voltage of less than 2 V is required in this case.
Figure 6. AC Coupling Capacitors on Both Sides of Switch
Copyright © 2015, Texas Instruments Incorporated
11
HD3SS3411-Q1
ZHCSE09A –JUNE 2015–REVISED JULY 2015
www.ti.com.cn
9.5 Application Curves
Figure 7. 6 Gbps Source Eye Diagram
Figure 8. 6 Gbps Output Eye Diagram
10 Power Supply Recommendations
There is no power supply sequence required for HD3SS3411-Q1. However, it is recommended that OEn is
asserted low after device supply VCC is stable and in specifications. It is also recommended that ample
decoupling capacitors are placed at the device VCC near the pin.
12
Copyright © 2015, Texas Instruments Incorporated
HD3SS3411-Q1
www.ti.com.cn
ZHCSE09A –JUNE 2015–REVISED JULY 2015
11 Layout
11.1 Layout Guidelines
11.1.1 Critical Routes
•
The high speed differential signals must be routed with great care to minimize signal quality degradation
between the connector and the source or sink of the high speed signals by following the guidelines provided
in this document. Depending on the configuration schemes, the speed of each differential pair can reach a
maximum speed of 10 Gbps. These signals are to be routed first before other signals with highest priority.
•
Each differential pair should be routed together with controlled differential impedance of 85-Ω to 90-Ω and 50-
Ω common mode impedance. Keep away from other high speed signals. The number of vias should be kept
to minimum. Each pair should be separated from adjacent pairs by at least 3 times the signal trace width.
Route all differential pairs on the same group of layers (Outer layers or inner layers) if not on the same layer.
No 90 degree turns on any of the differential pairs. If bends are used on high speed differential pairs, the
angle of the bend should be greater than 135 degrees.
•
Length matching:
–
Keep high speed differential pairs lengths within 5 mil of each other to keep the intra-pair skew minimum.
The inter-pair matching of the differential pairs is not as critical as intra-pair matching.
•
•
•
Keep high speed differential pair traces adjacent to ground plane.
Do not route differential pairs over any plane split.
ESD components on the high speed differential lanes should be placed nearest to the connector in a pass
through manner without stubs on the differential path.
•
For ease of routing, the P and N connection of the USB3.1 differential pairs to the HD3SS3411-Q1 pins can
be swapped.
11.1.2 General Routing/Placement Rules
•
Follow 20H rule (H is the distance to ref-plane) for separation of the high speed trace from the edge of the
plane.
•
•
Minimize parallelism of high speed clocks and other periodic signal traces to high speed lines.
All differential pairs should be routed on the top or bottom layer (microstrip traces) if possible or on the same
group of layers. Vias should only be used in the breakout region of the device to route from the top to bottom
layer when necessary. Avoid using vias in the main region of the board at all cost. Use a ground reference via
next to signal via. Distance between ground reference via and signal need to be calculated to have similar
impedance as traces.
•
•
All differential signals should not be routed over plane split. Changing signal layers is preferable to crossing
plane splits.
Use of and proper placement of stitching caps when split plane crossing is unavoidable to account for high
frequency return current path.
•
•
Route differential traces over a continuous plane with no interruptions.
Do not route differential traces under power connectors or other interface connectors, crystals, oscillators, or
any magnetic source.
•
•
Route traces away from etching areas like pads, vias, and other signal traces. Try to maintain a 20 mil keep
out distance where possible.
Decoupling caps should be placed next to each power terminal on the HD3SS3411-Q1. Care should be taken
to minimize the stub length of the trace connecting the capacitor to the power pin.
•
•
•
Avoid sharing vias between multiple decoupling caps.
Place vias as close as possible to the decoupling cap solder pad.
Widen VCC/GND planes to reduce effect of static and dynamic IR drop.
Copyright © 2015, Texas Instruments Incorporated
13
HD3SS3411-Q1
ZHCSE09A –JUNE 2015–REVISED JULY 2015
www.ti.com.cn
11.2 Layout Example
OEn and SEL can be controlled
by µC. OEn can also be tied
to Vcc with resistor
Match High Speed traces
length as close as possible to
minimize Skew
Match High Speed traces
length as close as possible to
minimize Skew
OEn
100nF
100nF
Ap
An
Bp
Bn
VCC
GND
Place VCC decoupling caps as
close to VCC pins as possible
Cp
Cn
GND
RSVD
GND
Figure 9. Layout
14
版权 © 2015, Texas Instruments Incorporated
HD3SS3411-Q1
www.ti.com.cn
ZHCSE09A –JUNE 2015–REVISED JULY 2015
12 器件和文档支持
12.1 文档支持
12.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.5 出口管制提示
接收方同意：如果美国或其他适用法律限制或禁止将通过非披露义务的披露方获得的任何产品或技术数据（其中包
括软件）（见美国、欧盟和其他出口管理条例之定义）、或者其他适用国家条例限制的任何受管制产品或此项技术
的任何直接产品出口或再出口至任何目的地，那么在没有事先获得美国商务部和其他相关政府机构授权的情况下，
接收方不得在知情的情况下，以直接或间接的方式将其出口。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不
对本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2015, Texas Instruments Incorporated
15
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
HD3SS3411RWARQ1
HD3SS3411TRWARQ1
PREVIEW
ACTIVE
WQFN
WQFN
RWA
RWA
14
14
3000
TBD
Call TI
NIPDAU
Call TI
-40 to 105
-40 to 105
3000 RoHS & Green
Level-2-260C-1 YEAR
3411Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2021
OTHER QUALIFIED VERSIONS OF HD3SS3411-Q1 :
Catalog : HD3SS3411
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
HD3SS3411TRWARQ1
WQFN
RWA
14
3000
330.0
12.4
3.75
3.75
1.15
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
WQFN RWA 14
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 33.0
HD3SS3411TRWARQ1
3000
Pack Materials-Page 2
PACKAGE OUTLINE
RWA0014A
WQFN - 0.8 mm max height
S
C
A
L
E
3
.
2
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.65
3.35
B
A
PIN 1 INDEX AREA
3.65
3.35
C
0.8 MAX
SEATING PLANE
0.08
0.05
0.00
2.05 0.1
2X 1.5
(0.2) TYP
7
8
6
9
2X
2
8X 0.5
2
13
0.30
0.18
14X
1
14
0.1
C A
B
PIN 1 ID
(OPTIONAL)
0.05
0.5
0.3
14X
4221612/B 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RWA0014A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.05)
2X (1.5)
SYMM
1
14
14X (0.6)
2
13
14X (0.24)
SYMM
(3.3)
(0.775)
8X (0.5)
9
6
(
0.2) VIA
TYP
7
8
(0.775)
(R0.05) TYP
(3.3)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4221612/B 02/2015
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RWA0014A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
2X (1.5)
4X ( 0.92)
1
14
14X (0.6)
2
13
14X (0.24)
(3.3)
SYMM
(0.56)
8X (0.5)
9
6
METAL
TYP
7
SYMM
(3.3)
8
(R0.05) TYP
(0.56)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
4221612/B 02/2015
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
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