HD3SS3412A [TI]
4 通道高性能差动开关;
| 型号： | HD3SS3412A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 4 通道高性能差动开关 开关 |
| 文件： | 总27页 (文件大小：1963K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Support &
Community
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
HD3SS3412A
ZHCSH49 –DECEMBER 2017
HD3SS3412A 4 通道高性能差动开关
1 特性
3 说明
1
•
兼容运行速率高达 12Gbps 的多种接口标准，包括
HD3SS3412A 器件是一款高速无源开关，能够切换四
条差分通道， 包括 在电脑或服务器应用中从一个源分
别到两个目标位置的两条完整 PCI Express x1 通道等
应用。具有双向功能的 HD3SS3412A 还 支持 一个目
标设备与两个源设备相连，例如两个平台共享一个外
设。HD3SS3412A 具有单个控制线（SEL 引脚），可
用于控制端口 A 与端口 B 或端口 C 间的信号路径。
PCI Express GEN III 和 USB 3.0
超过 8 GHz 的 –3dB 宽差动带宽
出色动态特性（4GHz 时）
•
•
–
–
–
–
串扰 = -35dB
断开隔离 = –19dB
插入损耗 = –1.5dB
回波损耗 = –11dB
HD3SS3412A 采用行业标准的 42 引脚 WQFN 封装，
采用多家供应商通用的尺寸。该器件需要在 0°C 至
70ºC 的完整温度范围内由电压为 3.3V 的单电源供电
运行。
•
•
•
•
•
双向“多路复用器/多路信号分离器”类型差动开关
VDD 运行电压范围 3.3V ± 10%
小型 3.5mm × 9.0mm 42 引脚 WQFN 封装
通用行业标准引脚
器件信息(1)
支持 XAUI 和 SGMII
器件型号
封装
封装尺寸（标称值）
2 应用
HD3SS3412A
WQFN (42)
9.00mm x 3.50mm
•
•
•
•
台式机和笔记本电脑
(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。
服务器和存储局域网络
PCI EXPress 背板
共享 I/O 端口
HD3SS3412A 引脚
HD3SS3412A 开关直通布线
GND
A0+
A0-
B0+
B0-
B1+
B1-
Top View
RUA
Package
GND
VDD
A1+
A1-
C0+
C0-
C1+
NC
C1-
VDD
SEL
GND
A2+
B2+
B2-
B3+
B3-
C2+
C2-
A2-
VDD
GND
A3+
GND
Pad
A3-
C3+
C3-
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLAS974
HD3SS3412A
ZHCSH49 –DECEMBER 2017
www.ti.com.cn
目录
9.2 Functional Block Diagram ....................................... 12
9.3 Feature Description................................................. 13
9.4 Device Functional Modes........................................ 13
10 Application and Implementation........................ 14
10.1 Application Information.......................................... 14
10.2 Typical Application ................................................ 15
11 Power Supply Recommendations ..................... 17
12 Layout................................................................... 17
12.1 Layout Guidelines ................................................. 17
12.2 Layout Example .................................................... 17
13 器件和文档支持 ..................................................... 18
13.1 接收文档更新通知 ................................................. 18
13.2 社区资源................................................................ 18
13.3 商标....................................................................... 18
13.4 静电放电警告......................................................... 18
13.5 Glossary................................................................ 18
14 机械、封装和可订购信息....................................... 18
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
说明 （续）.............................................................. 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 6
7.1 Absolute Maximum Ratings ...................................... 6
7.2 ESD Ratings.............................................................. 6
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information.................................................. 6
7.5 Electrical Characteristics........................................... 7
7.6 Dissipation Ratings ................................................... 7
7.7 Typical Characteristics.............................................. 9
Parameter Measurement Information ................ 10
Detailed Description ............................................ 12
9.1 Overview ................................................................. 12
8
9
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
日期
修订版本
说明
2017 年 12 月
*
初始发行版
2
版权 © 2017, Texas Instruments Incorporated
HD3SS3412A
www.ti.com.cn
ZHCSH49 –DECEMBER 2017
5 说明 （续）
HD3SS3412A 是通用的 4 通道高速多路复用器/多路信号分离器开关类型，可用于电路板上两个不同位置间的高速
信号路由。虽然 HD3SS3412A 专为 PCI Express Gen III 应用而设计，但也支持其它多种差模电压＜1800mVpp、
共模电压＜2.0V 的高速数据协议，与 USB 3.0 和 DisplayPort 1.2 相同。该器件的一个选择输入 (SEL) 引脚可通过
系统内或微控制器提供的一个 GPIO 引脚轻松控制。
6 Pin Configuration and Functions
RUA Package
42-Pin WQFN
Top View
GND
A0+
A0-
B0+
B0-
B1+
B1-
Top View
RUA
Package
GND
VDD
A1+
A1-
C0+
C0-
C1+
NC
C1-
VDD
SEL
GND
A2+
B2+
B2-
B3+
B3-
C2+
C2-
A2-
VDD
GND
A3+
GND
Pad
A3-
C3+
C3-
GND
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
SWITCH PORT A
A0+
2
3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Port A, Channel 0, High-Speed Positive Signal
Port A, Channel 0, High-Speed Negative Signal
Port A, Channel 1, High-Speed Positive Signal
Port A, Channel 1, High-Speed Negative Signal
Port A, Channel 2, High-Speed Positive Signal
Port A, Channel 2, High-Speed Negative Signal
Port A, Channel 3, High-Speed Positive Signal
Port A, Channel 3, High-Speed Negative Signal
A0–
A1+
6
A1–
7
A2+
11
12
15
16
A2–
A3+
A3–
SWITCH PORT B
B0+
B0–
B1+
38
37
36
I/O
I/O
I/O
Port B, Channel 0, High-Speed Positive Signal
lPort B, Channel 0, High-Speed Negative Signal
Port B, Channel 1, High-Speed Positive Signal
Copyright © 2017, Texas Instruments Incorporated
3
HD3SS3412A
ZHCSH49 –DECEMBER 2017
www.ti.com.cn
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
B1–
NO.
35
29
28
27
26
I/O
I/O
I/O
I/O
I/O
Port B, Channel 1, High-Speed Negative Signal
Port B, Channel 2, High-Speed Positive Signal
Port B, Channel 2, High-Speed Negative Signal
Port B, Channel 3, High-Speed Positive Signal
Port B, Channel 3, High-Speed Negative Signal
B2+
B2–
B3+
B3–
4
Copyright © 2017, Texas Instruments Incorporated
HD3SS3412A
www.ti.com.cn
ZHCSH49 –DECEMBER 2017
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
SWITCH PORT C
C0+
C0–
C1+
C1–
C2+
C2–
C3+
C3–
34
33
32
31
25
24
23
22
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Port C, Channel 0, High-Speed Positive Signal
Port C, Channel 0, High-Speed Negative Signal
Port C, Channel 1, High-Speed Positive Signal
Port C, Channel 1, High-Speed Negative Signal
Port C, Channel 2, High-Speed Positive Signal
Port C, Channel 2, High-Speed Negative Signal
Port C, Channel 3, High-Speed Positive Signal
Port C, Channel 3, High-Speed Negative Signal
CONTROL, SUPPLY, AND NO CONNECT
8
NC
18
—
Electrically not connected. May connect to VDD or GND, or leave unconnected.
42
1
4
10
14
17
GND
Supply Negative power supply voltage
19
21
39
41
Center Pad
SEL
9
I
Select between port B or port C. Internally tied to GND through a 100-kΩ resistor
5
13
20
30
40
VDD
Supply Positive power supply voltage
Copyright © 2017, Texas Instruments Incorporated
5
HD3SS3412A
ZHCSH49 –DECEMBER 2017
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN
–0.5
–0.5
–0.5
–65
MAX
UNIT
Supply voltage (VDD
)
Absolute minimum/maximum supply voltage
Differential I/O
4
4
V
Voltage
V
Control pin (SEL)
VDD + 0.5
150
Storage temperature, Tstg
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to network ground terminal.
7.2 ESD Ratings
VALUE
±4000
±1500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Typical values for all parameters are at VDD = 3.3 V and TA = 25°C. (Temperature limits are specified by design)
MIN NOM
MAX
UNIT
V
VDD
Supply voltage
3.0
2.0
–0.1
0
3.3
3.6
VDD
0.8
VIH
Input high voltage (SEL pin)
Input low voltage (SEL pin)
Differential voltage (differential pins)
Common voltage (differential pins)
Operating free-air temperature
V
VIL
V
VI/O_Diff
VI/O_CM
TA
Switch I/O diff voltage
1.8
VPP
V
Switch I/O common-mode voltage
Ambient temperature
0
2.0
0
70
oC
7.4 Thermal Information
HD3SS3412A
RUA (WQFN)
42 PINS
53.8
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
38.2
21.9
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
27.4
ψJB
5.6
RθJC(bot)
27.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6
Copyright © 2017, Texas Instruments Incorporated
HD3SS3412A
www.ti.com.cn
ZHCSH49 –DECEMBER 2017
7.5 Electrical Characteristics
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
DEVICE PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IIH
IIL
Input High Voltage (SEL)
Input Low Voltage (SEL)
VDD = 3.6 V; VIN = VDD
VDD = 3.6 V; VIN = GND
95
1
µA
µA
VDD = 3.6 V; VIN = 0 V; VOUT = 2 V
(ILK On OPEN outputs) [Ports B and C]
130
Leakage Current (Differential
I/O pins)
ILK
µA
VDD = 3.6 V, VIN = 2 V; VOUT = 0 V
(ILK On OPEN outputs) [Port A]
4
6
IDD
Supply Current
VDD = 3.6 V; SEL = VDD/GND; Outputs Floating
VIN = 0 V; Outputs Open; Switch ON
4.7
1.5
1
mA
pF
pF
Ω
CON
COFF
RON
Outputs ON Capacitance
Outputs OFF Capacitance
Output ON resistance
VIN = 0 V; Outputs Open, Switch OFF
VDD = 3.3 V; VCM = 0.5 V to 1.5 V ; IO = –8 mA
5
8
2
ON-resistance match between
channels
VDD = 3.3 V ; –0.35 V ≤ VIN ≤ 1.2 V; IO = –8 mA
VDD = 3.3 V; –0.35 V ≤ VIN ≤ 1.2 V; IO = –8 mA
Ω
Ω
ΔRON
ON-resistance match between
pairs of the same channel
0.7
ON-resistance flatness
(RON(MAX) – RON(MAIN)
RFLAT_ON
tPD
VDD = 3.3 V; –0.35 V ≤ VIN ≤ 1.2 V
Rsc and RLOAD = 50 Ω
1.15
Ω
Switch propagation delay
SEL-to-switch TON
85
250
250
ps
70
70
Rsc and RLOAD = 50 Ω
Rsc and RLOAD = 50 Ω
ns
SEL-to-switch TOFF
Inter-pair output skew (CH-
CH)
TSKEW_Inter
20
8
ps
ps
TSKEW_Intra Intra-pair output skew (bit-bit) Rsc and RLOAD = 50 Ω
Differential return loss (VCM = f = 0.3 MHz
0 V)
Also see Typical
–28
–12
–11
–90
–39
–35
–75
–22
–19
–0.5
–1.1
–1.5
8
f = 2500 MHz
f = 4000 MHz
RL
dB
dB
dB
Characteristics
Differential Crosstalk(VCM = 0 f = 0.3 MHz
V)
f = 2500 MHz
XTALK
Also see Typical
Characteristics
f = 4000 MHz
Differential Off-Isolation(VCM f = 0.3 MHz
= 0 V)
Also see Typical
f = 2500 MHz
OIRR
f = 4000 MHz
f = 0.3 MHz
f = 2500 MHz
f = 4000 MHz
At –3 dB
Characteristics
Differential Insertion Loss
(VCM = 0 V)
Also see Typical
Characteristics
IL
dB
BW
Bandwidth
GHz
7.6 Dissipation Ratings
MIN
MAX
21.6
UNIT
mW
PD
Power Dissipation
15.5
Copyright © 2017, Texas Instruments Incorporated
7
HD3SS3412A
ZHCSH49 –DECEMBER 2017
www.ti.com.cn
50%
SEL
90%
V
10%
OUT
Toff
Ton
Figure 1. Switch ON and OFF Timing Diagram
V
DD
R
= 50W
SC
An+
An-
Bn+/Cn+
Bn-/Cn-
R
= 50W
L
R
= 50W
SC
R
= 50W
L
SEL
V
DD
V
+
IN
50%
50%
0V
V
DD
50%
50%
V
IN
-
0V
V
DD
50%
50%
V
V
+
OUT
0V
V
DD
50%
50%
+
0V
OUT
t
t
P1
P1
TSKEWInter = Difference between tPD for any two pairs of outputs
TSKEWIntra = Difference between tP1 and tP2 of same pair
Figure 2. Propagation Delay Timing Diagram and Test Setup
8
Copyright © 2017, Texas Instruments Incorporated
HD3SS3412A
www.ti.com.cn
ZHCSH49 –DECEMBER 2017
7.7 Typical Characteristics
5
0
m1
0
m2
m5
freq=329.0kHz
dB(SDD11)=-28.545
m3
m1
freq=300.0kHz
dB(SDD21)=-0.491
-2
-4
m4
-5
m6
freq=2.514GHz
dB(SDD11)=-13.842
m7
m6
m2
freq=2.514GHz
dB(SDD21)=-1.221
-10
-15
-20
-25
-30
-6
-8
m7
freq=3.985GHz
dB(SDD11)=-11.177
m3
freq=3.985GHz
dB(SDD21)=-1.536
-10
-12
-14
m5
m4
freq=8.331GHz
dB(SDD21)=-2.998
freq, Hz
freq, Hz
Figure 3. Differential Insertion Loss
Figure 4. Differential Return Loss
0
-20
m1
freq=300.0kHz
dB(SDD21)=-74.449
m1
m3
m3
freq=300.0kHz
dB(SDD21)=-97.081
m2
m2
-20
-40
-40
-60
m2
freq=2.514GHz
dB(SDD21)=-22.000
m2
freq=2.514GHz
dB(SDD21)=-39.567
-60
-80
m1
m3
freq=3.985GHz
dB(SDD21)=-18.935
m3
freq=3.985GHz
dB(SDD21)=-34.786
m1
-80
-100
-120
-100
freq, Hz
freq, Hz
Figure 6. Differential Off Isolation
Figure 5. Differential Crosstalk
Copyright © 2017, Texas Instruments Incorporated
9
HD3SS3412A
ZHCSH49 –DECEMBER 2017
www.ti.com.cn
8 Parameter Measurement Information
Network
Analyzer
P2
P1
VDD
B0+
A0+
A0-
100 W
B0-
HD3SS3412
SEL
A1+
A1-
B1+
B1-
100 W
Figure 7. Cross Talk Measurement Setup
Network
Analyzer
P2
P1
VDD
B0+
A0+
A0-
100 W
B0-
HD3SS3412
SEL
B1+
B1-
Figure 8. Off Isolation Measurement Setup
10
Copyright © 2017, Texas Instruments Incorporated
HD3SS3412A
www.ti.com.cn
ZHCSH49 –DECEMBER 2017
Parameter Measurement Information (continued)
A
3.1 Inches Rogers
Microstrip
10Gbps PRBS 27-1
Oscilloscope
Vi=0.8Vpp; Vcm =0V
Figure 9. Source Eye Diagram Test Setup
A
1.4 Inches
Rogers
1.7 Inches
Rogers
Microstrip
Microstrip
10Gbps PRBS 27-1
Vi=0.8Vpp; Vcm =0V
Oscilloscope
Figure 10. Output Eye Diagram Test Setup
Copyright © 2017, Texas Instruments Incorporated
11
HD3SS3412A
ZHCSH49 –DECEMBER 2017
www.ti.com.cn
9 Detailed Description
9.1 Overview
The HD3SS3412A is a high-speed passive switch offered in an industry standard 42-pin WQFN package
available in a common footprint shared by several other vendors. The device is specified to operate from a single
supply voltage of 3.3 V over the commercial temperature range of 0°C to 70°C. The HD3SS3412A is a generic 4-
CH high-speed mux/demux type of switch that can be used for routing high-speed signals between two different
locations on a circuit board. Although it was designed specifically to address PCI Express Gen III applications,
the HD3SS3412A will also support several other high-speed data protocols with a differential amplitude of < 1800
mVpp and a common-mode voltage of < 2.0 V, as with USB 3.0 and DisplayPort 1.2. The device’s one select
input (SEL) pin can easily be controlled by an available GPIO pin within a system or from a microcontroller.
9.2 Functional Block Diagram
VDD
B0+
B0-
A0+
A0-
C0+
C0-
SEL
SEL
100kO
SEL
B1+
B1-
A1+
A1-
C1+
C1-
SEL
B2+
B2-
A2+
A2-
C2+
C2-
SEL
B3+
B3-
A3+
A3-
C3+
C3-
GND
12
Copyright © 2017, Texas Instruments Incorporated
HD3SS3412A
www.ti.com.cn
ZHCSH49 –DECEMBER 2017
9.3 Feature Description
The HD3SS3412A has a single control line (SEL Pin) which can be used to control the signal path between Port
A and either Port B or Port C. The one select input (SEL) pin of the device can easily be controlled by an
available GPIO pin within a system or from a microcontroller. The input signal is selected using the SEL pin.
Table 1. Mux Pin Connections(1)
PORT B OR PORT C CHANNEL
CONNECTED TO PORT A CHANNEL
PORT A CHANNEL
SEL = L
B0+
SEL = H
C0+
A0+
A0–
A1+
A1–
A2+
A2–
A3+
A3–
B0–
C0–
B1+
C1+
B1–
C1–
B2+
C2+
B2–
C2–
B3+
C3+
B3–
C3–
(1) The HD3SS3412A can tolerate polarity inversions for all differential signals on Ports A, B, and C. Take care to ensure the same polarity
is maintained on Port A versus Port B/C.
9.4 Device Functional Modes
Table 2 lists the functional modes for the HD3SS3412A.
Table 2. HD3SS3412A Control Logic
PORT A TO PORT B
CONNECTION STATUS
PORT A TO PORT C
CONNECTION STATUS
CONTROL PIN (SEL)
L (Default State)
H
Connected
Disconnected
Connected
Disconnected
Copyright © 2017, Texas Instruments Incorporated
13
HD3SS3412A
ZHCSH49 –DECEMBER 2017
www.ti.com.cn
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
10.1.1 AC Coupling Caps
Many interfaces require AC coupling between the transmitter and receiver. The 0402 capacitors are the preferred
option to provide AC coupling, and the 0603 size capacitors also work. The 0805 size capacitors and C-packs
should be avoided. When placing AC coupling capacitors symmetric placement is best. A capacitor value of 0.1
µF is best and the value should be match for the ± signal pair. The placement should be along the TX pairs on
the system board, which are usually routed on the top layer of the board.
There are several placement options for the AC coupling capacitors. Because the switch requires a bias voltage,
the capacitors must only be placed on one side of the switch. If they are placed on both sides of the switch, a
biasing voltage should be provided. A few placement options are shown below. In Figure 11, the coupling
capacitors are placed between the switch and endpoint. In this situation, the switch is biased by the system/host
controller.
Figure 11. AC Coupling Capacitors Between Switch Tx and Endpoint Tx
In Figure 12, the coupling capacitors are placed on the host transmit pair and endpoint transmit pair. In this
situation, the switch on the top is biased by the endpoint and the lower switch is biased by the host controller.
Figure 12. AC Coupling Capacitors on Host Tx and Endpoint Tx
14
Copyright © 2017, Texas Instruments Incorporated
HD3SS3412A
www.ti.com.cn
ZHCSH49 –DECEMBER 2017
Application Information (continued)
If the common-mode voltage in the system is higher than 2 V, the coupling capacitors are placed on both sides
of the switch (shown in Figure 13). A biasing voltage of less than 2 V is required in this case.
Figure 13. AC Coupling Capacitors on Both Sides of Switch
10.2 Typical Application
Microprocessor
Port A
x2
Port B
x2
Port C
x2
Port B
x2
Chipset
Memory/GPU
Hub
Port C
x2
x8
iGPU
Port B
x2
x16
Port C
x2
Chipset
I/O Hub
Port B
x2
GPIO
Port C
x2
SEL Pins
Figure 14. Typical Application Block Diagram
Copyright © 2017, Texas Instruments Incorporated
15
HD3SS3412A
ZHCSH49 –DECEMBER 2017
www.ti.com.cn
Typical Application (continued)
10.2.1 Design Requirements
Table 3 lists the design parameters of this example.
Table 3. Design Parameters
DESIGN PARAMETERS
Input voltage range
EXAMPLE VALUE
3.3 V
Decoupling capacitors
0.1 µF
75 nF – 200 nF (100 nF shown) USBAA TX p and
n lines require AC capacitors. Alternate mode
signals may or may not require AC capacitors
AC capacitors
10.2.2 Detailed Design Procedure
•
Connect VDD and GND pins to the power and ground planes of the printed circuit board, with 0.1-uF bypass
capacitor
•
•
•
Use +3.3-V TTL/CMOS logic level at SEL
Use controlled-impedance transmission media for all the differential signals
Ensure the received complimentary signals are with a differential amplitude of <1800 mVpp and a common-
mode voltage of <2 V
10.2.3 Application Curves
Figure 16. 10-gbps Output Eye Diagram at a: VID = 800
Mvpp; 27–1 Prbs; VCM= 0v; VDD= 3.3 V; Sel= 0 V
Figure 15. 10-gbps Source Eye Diagram at a: VID = 800
Mvpp; 27–1 Prbs; VCM= 0 V
16
Copyright © 2017, Texas Instruments Incorporated
HD3SS3412A
www.ti.com.cn
ZHCSH49 –DECEMBER 2017
11 Power Supply Recommendations
The HD3SS3412A requires +3.3-V digital power sources. VDD 3.3 supply must have 0.1-μF bypass capacitors to
VSS (ground) in order for proper operation. The recommendation is one capacitor for each power terminal. Place
the capacitor as close as possible to the terminal on the device and keep trace length to a minimum. Smaller
value capacitors like 0.01-μF are also recommended on the digital supply terminals.
12 Layout
12.1 Layout Guidelines
•
Decoupling caps should be placed next to each power terminal on the HD3SS3412A. Take care to minimize
the stub length of the race connecting the capacitor to the power pin.
•
•
•
•
Avoid sharing vias between multiple decoupling caps
Place vias as close as possible to the decoupling cop solder pad
Widen VDD/GND planes to reduce effect if static and dynamic IR drop
The VBUS traces/planes must be wide enough to carry maximum of 2-A current
12.2 Layout Example
Use controlled-impedance
Transmission media for all
Differential signals
VIA to SW Cooper Pour
VDD3P3
VDD3P3
AX+
AX-
BX+
BX-
CX+
CX-
VSS
SEL
VBUS
GND
Exposed Thermal
Pad Are
3.3V Logic level
VBUS traces wide
enough to carry 2A
current
Figure 17. Layout Example
版权 © 2017, Texas Instruments Incorporated
17
HD3SS3412A
ZHCSH49 –DECEMBER 2017
www.ti.com.cn
13 器件和文档支持
13.1 接收文档更新通知
要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.2 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
13.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知和修
订此文档。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航。
18
版权 © 2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
HD3SS3412ARUAR
HD3SS3412ARUAT
ACTIVE
ACTIVE
WQFN
WQFN
RUA
RUA
42
42
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
0 to 70
0 to 70
HD3SS3412
HD3SS3412
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-May-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
HD3SS3412ARUAR
HD3SS3412ARUAT
WQFN
WQFN
RUA
RUA
42
42
3000
250
330.0
180.0
24.4
24.4
3.9
3.9
9.4
9.4
1.0
1.0
8.0
8.0
24.0
24.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-May-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
HD3SS3412ARUAR
HD3SS3412ARUAT
WQFN
WQFN
RUA
RUA
42
42
3000
250
367.0
211.0
367.0
193.0
45.0
46.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RUA 42
9 x 3.5, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226504/A
www.ti.com
PACKAGE OUTLINE
RUA0042A
WQFN - 0.8 mm max height
S
C
A
L
E
1
.
8
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.6
3.4
A
B
PIN 1 INDEX AREA
9.1
8.9
0.8
0.6
C
SEATING PLANE
0.08 C
0.05
0.00
2.05 0.1
2X 1.5
SYMM
(0.1) TYP
EXPOSED
THERMAL PAD
21
18
17
22
SYMM
43
2X 8
7.55 0.1
0.3
0.2
1
38
42X
42
39
38X 0.5
0.1
C A B
0.5
0.3
42X
PIN 1 ID
0.05
4219139/A 03/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RUA0042A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2.05)
SYMM
SEE SOLDER MASK
DETAIL
42X (0.6)
42X (0.25)
42
39
1
38X (0.5)
38
(3.525) TYP
(R0.05) TYP
(
0.2) TYP
VIA
1.17 TYP
SYMM
43
(7.55) (8.8)
17
22
18
21
(0.775)
TYP
(3.3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219139/A 03/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RUA0042A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.56) TYP
42X (0.6)
42X (0.25)
42
39
1
38X (0.5)
38
(R0.05) TYP
(0.585)
TYP
43
SYMM
(8.8)
12X (0.97)
22
17
21
18
12X (0.92)
SYMM
(3.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 12X
EXPOSED PAD 43
69% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4219139/A 03/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他 TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款 (https:www.ti.com.cn/zh-cn/legal/termsofsale.html) 或 ti.com.cn 上其他适用条款/TI 产品随附的其他适用条款
的约束。TI 提供这些资源并不会扩展或以其他方式更改 TI 针对 TI 产品发布的适用的担保或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2021 德州仪器半导体技术（上海）有限公司
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明