HPA02218RTERQ1 [TI]
2.95-V to 6-V Input, 6-A Output, 2-MHz, Synchronous Step-Down SWIFT Switcher;
| 型号： | HPA02218RTERQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2.95-V to 6-V Input, 6-A Output, 2-MHz, Synchronous Step-Down SWIFT Switcher 开关 |
| 文件： | 总38页 (文件大小：1675K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS54618-Q1
www.ti.com
SLVSBY9C –AUGUST 2013–REVISED DECEMBER 2013
2.95-V to 6-V Input, 6-A Output, 2-MHz, Synchronous Step-Down SWIFT™ Switcher
Check for Samples: TPS54618-Q1
1
FEATURES
DESCRIPTION
The TPS54618RTE-Q1 SWIFT integrated circuit is a
full-featured 6-V, 6-A, synchronous step-down
2
•
Qualified for Automotive Applications
•
AEC-Q100 Qualified With the Following
Results:
current-mode
MOSFETs.
converter
with
two
integrated
–
Device Temperature Grade 1: –40°C to
125°C Ambient Operating Temperature
Range
The TPS54618RTE-Q1 enables small designs by
integrating the MOSFETs, implementing current-
mode control to reduce external component count,
reducing inductor size by enabling up to 2-MHz
switching frequency, and minimizing the IC footprint
with a small 3-mm × 3-mm thermally enhanced QFN
package.
–
–
Device HBM ESD Classification Level H2
Device CDM ESD Classification Level C4B
•
Two 12-mΩ (Typical) MOSFETs for High
Efficiency at 6-A Loads
The TPS54618RTE-Q1 provides accurate regulation
for a variety of loads with an accurate ±1% voltage
reference (VREF) overtemperature.
•
•
300-kHz to 2-MHz Switching Frequency
0.8-V ±1% Voltage Reference Overtemperature
(–40°C to 150°C)
The integrated 12-mΩ MOSFETs and 515-μA typical
supply current maximize efficiency. Using the enable
pin reduces the shutdown supply current to 5.5 µA
when the device enters shutdown mode.
•
•
•
•
Synchronizes to External Clock
Adjustable Slow Start and Sequencing
UV and OV Power-Good Output
Thermally Enhanced 3-mm × 3-mm 16-pin QFN
The undervoltage lockout internal setting is 2.6 V, but
can be increased by programming the threshold with
a resistor network on the enable pin. The slow-start
pin controls the output-voltage start-up ramp. An
open-drain power-good signal indicates when the
output is within 93% to 107% of its nominal voltage.
APPLICATIONS
•
•
Low-Voltage, High-Density Power Systems
Point-of-Load Regulation for High-
Performance DSPs, FPGAs, ASICs, and
Microprocessors
Frequency foldback and thermal shutdown protect the
device during an overcurrent condition.
•
Broadband, Networking, and Optical
Communications Infrastructure
The SwitcherPro™ software tool, available at
www.ti.com/switcherpro, supports the TPS54618RTE-
Q1.
For more SWIFTTM integrated-circuit documentation,
see the TI Web site at www.ti.com/swift.
Figure 1. SIMPLIFIED SCHEMATIC
VIN
C
BOOT
VIN
BOOT
C
I
R
R
4
5
100
TPS54618-Q1
EN
L
O
VOUT
3 Vin
95
PH
C
O
5 Vin
90
R
1
2
PWRGD
85
VSENSE
80
75
R
SS/TR
RT /CLK
COMP
70
65
60
GND
AGND
C
POWERPAD
ss
R
R
T
3
f
= 500kHz
s
55
50
Vout = 1.8V
C
1
0
1
2
3
4
5
6
I
- Output Current - A
O
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
SWIFT, SwitcherPro are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
TPS54618-Q1
SLVSBY9C –AUGUST 2013–REVISED DECEMBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DEVICE INFORMATION(1)(2)
TA
P/N
PACKAGE
TOP-SIDE MARKING
–40ºC to 125ºC
TPS54618QRTERQ1
QFN, 3x3
618Q1
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
ABSOLUTE MAXIMUM RATINGS(1)
VALUE
–0.3 to 7
–0.3 to 4
PH + 7
–0.3 to 3
–0.3 to 3
–0.3 to 7
–0.3 to 3
–0.3 to 4
7
UNIT
VIN
EN
BOOT
VSENSE
COMP
PWRGD
SS/TR
Input voltage
V
RT/CLK
BOOT-PH
PH
Output voltage
Source current
Sink current
–0.6 to 7
–2 to 10
100
V
PH, 10-ns transient
EN
µA
RT/CLK
COMP
PWRGD
SS/TR
100
100
µA
mA
µA
kV
V
10
100
Electrostatic discharge Human-body model, (HBM) AEC-Q100 Classification Level H2
2
(ESD) ratings
Charged-device model, (CDM) AEC-Q100 Classification Level C4B
750
TJ
–40 to 150
–65 to 150
°C
°C
Temperature
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2
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SLVSBY9C –AUGUST 2013–REVISED DECEMBER 2013
THERMAL INFORMATION
TPS54618-Q1
THERMAL METRIC(1)
RTE
16 PINS
44.38
46.09
15.96
0.69
UNIT
θJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
θJCtop
θJB
ψJT
ψJB
15.91
4.55
θJCbot
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
ELECTRICAL CHARACTERISTICS
TA = –40°C to 125°C, VIN = 2.95 to 6 V (unless otherwise noted)
DESCRIPTION
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage
CONDITIONS
MIN
TYP
MAX
UNIT
2.95
6
2.5
2.6
15
V
V
VIN UVLO STOP
VIN UVLO START
2.28
2.45
5.5
Internal undervoltage lockout threshold
Shutdown supply current
Quiescent current - Iq
EN = 0 V, 25°C, 2.95 V ≤ VIN ≤ 6 V
μA
μA
VSENSE = 0.9 V, VIN = 5 V, 25°C, RT = 400 kΩ
515
650
ENABLE AND UVLO (EN PIN)
Rising
1.25
1.18
–3.5
–1.9
Enable threshold
Input current
V
Falling
Enable threshold + 50 mV
Enable threshold – 50 mV
μA
VOLTAGE REFERENCE (VSENSE PIN)
Voltage reference
2.95 V ≤ VIN ≤ 6 V, –40°C <TJ < 150°C
0.791 0.799 0.807
V
MOSFET
BOOT-PH = 5 V
BOOT-PH = 2.95 V
VIN = 5 V
12
16
13
17
25
33
25
33
High-side switch resistance
Low-side switch resistance
mΩ
mΩ
VIN = 2.95 V
ERROR AMPLIFIER
Input current
2
nA
Error amplifier transconductance (gm)
–2 μA < I(COMP) < 2 μA, V(COMP) = 1 V
245
μmhos
μmhos
Error amplifier transconductance (gm) during –2 μA < I(COMP) < 2 μA, V(COMP) = 1 V,
slow start
79
VSENSE = 0.4 V
Error amplifier source or sink
COMP to Iswitch gm
V(COMP) = 1 V, 100-mV overdrive
±20
25
μA
A/V
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ELECTRICAL CHARACTERISTICS (continued)
TA = –40°C to 125°C, VIN = 2.95 to 6 V (unless otherwise noted)
DESCRIPTION
CURRENT LIMIT
CONDITIONS
MIN
TYP
MAX
UNIT
VIN = 6 V, 25°C < TJ < 150°C
7.46
7.68
10.6
10.2
15.3
13.5
Current-limit threshold
A
VIN = 2.95 V, 25°C < TJ < 150°C
THERMAL SHUTDOWN
Thermal shutdown
Hysteresis
168
20
°C
°C
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Switching-frequency range using RT mode
200
400
300
75
2000
600
kHz
kHz
kHz
ns
V
Switching frequency
RT = 400 kΩ
500
Switching-frequency range using CLK mode
Minimum CLK pulse duration
RT/CLK voltage
2000
R(RT/CLK) = 400 kΩ
0.5
1.6
0.6
90
RT/CLK high threshold
2.2
V
RT/CLK low threshold
0.4
V
RT/CLK falling edge to PH rising-edge delay
PLL lock-in time
Measure at 500 kHz with RT resistor in series
Measure at 500 kHz
ns
μs
42
PH (PH PIN)
Measured at 50% points on PH, IOUT = 3 A
75
Minimum on-time
ns
ns
Measured at 50% points on PH, VIN = 6 V,
IOUT = 0 A
120
Prior to skipping off-pulses, BOOT-PH = 2.95 V,
IOUT = 3 A
Minimum off-time
60
Rise time
2.25
2
V/ns
V/ns
VIN = 6 V, 6 A
Fall time
BOOT (BOOT PIN)
BOOT charge resistance
BOOT-PH UVLO
VIN = 5 V
16
Ω
VIN = 2.95 V
2.1
V
SLOW-START AND TRACKING (SS/TR PIN)
Charge current
V(SS/TR) = 0.4 V
2
54
μA
mV
V
SS/TR to VSENSE matching
SS/TR to reference crossover
SS/TR discharge voltage (overload)
SS/TR discharge current (overload)
V(SS/TR) = 0.4 V
98% normal
1.1
61
VSENSE = 0 V
mV
µA
VSENSE = 0 V, V(SS/TR) = 0.4 V
350
SS discharge current (UVLO, EN, thermal
fault)
VIN = 5 V, V(SS) = 0.5 V
1.9
mA
POWER GOOD (PWRGD PIN)
VSENSE falling (fault)
VSENSE rising (good)
VSENSE rising (fault)
VSENSE falling (good)
VSENSE falling
91
93
VSENSE threshold
% Vre
109
107
2
Hysteresis
% Vref
Output high leakage
On-resistance
VSENSE = VREF, V(PWRGD) = 5.5 V
7
nA
Ω
V
56
100
0.3
1.5
Output low
I(PWRGD) = 3 mA
0.2
0.65
Minimum VIN for valid output
V(PWRGD) < 0.5 V at 100 μA
V
4
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SLVSBY9C –AUGUST 2013–REVISED DECEMBER 2013
DEVICE INFORMATION
PIN CONFIGURATION
QFN16
RTE Package
(Top View)
16
15
14
13
VIN
VIN
1
2
3
4
12
PH
11 PH
Exposed Thermal Pad
GND
GND
10
9
PH
SS/TR
5
6
7
8
PIN FUNCTIONS
PIN
DESCRIPTION
NAME
AGND
BOOT
NO.
5
Connect analog ground electrically to GND close to the device.
13
The device requires a bootstrap capacitor between BOOT and PH. A voltage on this capacitor below the minimum
required by the BOOT UVLO forces the output to switch off until the capacitor recharges.
COMP
EN
7
Error amplifier output, and input to the output-switch current comparator. Connect frequency compensation
components to this pin.
15
Enable pin, internal pull-up current source. Pull below 1.2 V to disable. Float to enable. Use of two additional
resistors can set the on-and-off threshold (adjust UVLO).
GND
PH
3, 4
Directly connect this power-ground pin electrically to the thermal pad under the IC.
10, 11, The source of the internal high-side power MOSFET, and drain of the internal low-side (synchronous) rectifier
12
MOSFET.
PWRGD
14
An open-drain output; asserts low if output voltage is low due to thermal shutdown, overcurrent, over or
undervoltage, or EN shutdown.
RT/CLK
SS/TR
8
9
Resistor timing or external clock input pin
Slow-start and tracking. An external capacitor connected to this pin sets the output-voltage rise time.
Another use of this pin can be for tracking.
VIN
1, 2, 16 Input supply voltage, 2.95 to 6 V.
VSENSE
6
Inverting node of the transconductance (gm) error amplifier
Thermal
pad
Connect the GND pin to the exposed thermal pad for proper operation. Connect this thermal pad to any internal
PCB ground plane using multiple vias for good thermal performance.
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FUNCTIONAL BLOCK DIAGRAM
PWRGD
EN
VIN
ihys
i1
Shutdown
Thermal
Shutdown
UVLO
Enable
Comparator
93%
Logic
Shutdown
Shutdown
Logic
109%
Enable
Threshold
Boot
Charge
Voltage
Reference
Boot
UVLO
Minimum
COMP Clamp
Current
Sense
ERROR
AMPLIFIER
PWM
Comparator
VSENSE
SS/TR
BOOT
Logic and PWM
Latch
Shutdown
Logic
Slope
Compensation
S
COMP
PH
Frequency
Shift
Maximum
Clamp
Overload
Recovery
Oscillator
With PLL
GND
TPS54618-Q1 Block Diagram
RT/CLK
AGND
POWERPAD
6
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SLVSBY9C –AUGUST 2013–REVISED DECEMBER 2013
TYPICAL CHARACTERISTICS CURVES
HIGH-SIDE AND LOW-SIDE rDS(on) versus TEMPERATURE
FREQUENCY versus TEMPERATURE
0.025
0.023
0.021
0.019
0.017
0.015
0.013
0.011
0.009
0.007
0.005
525
520
RT = 400 kW,
Vin = 5 V
High Side Rdson Vin = 3.3 V
515
510
505
500
495
490
485
Low Side Rdson Vin = 3.3 V
High Side Rdson Vin = 5 V
Low Side Rdson Vin = 5 V
480
475
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
T - Junction Temperature - °C
J
T
- Junction Temperature - °C
J
Figure 2.
Figure 3.
HIGH-SIDE CURRENT LIMIT versus TEMPERATURE
VOLTAGE REFERENCE versus TEMPERATURE
12
11.5
11
0.807
0.805
0.803
0.801
0.799
0.797
0.795
0.793
0.791
Vin = 3.3 V
Vin = 6 V
10.5
10
Vin = 2.95 V
9.5
9
8.5
8
25
75
50
100
125
150
-50
-25
0
25
50
75
100
125
150
T
- Junction Temperature - °C
J
T
- Junction Temperature - °C
J
Figure 4.
Figure 5.
SWITCHING FREQUENCY versus
RT RESISTANCE LOW-FREQUENCY RANGE
2000
SWITCHING FREQUENCY versus VSENSE
100
75
1800
1600
1400
1200
1000
800
Vsense Falling
Vsense Rising
50
600
25
0
400
200
100 200 300 400 500 600 700 800
Resistance (kΩ)
G000
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
Vsense - V
Figure 7.
Figure 6.
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TYPICAL CHARACTERISTICS CURVES (continued)
TRANSCONDUCTANCE (SLOW START) versus
JUNCTION TEMPERATURE
TRANSCONDUCTANCE versus TEMPERATURE
105
100
95
310
290
270
250
230
210
Vin = 3.3 V
Vin = 3.3 V
90
85
80
75
70
65
190
170
60
55
-50
-25
0
25
50
75
100
125
150
150
150
-50
-25
0
25
50
75
100
125
150
T
- Junction Temperature - °C
T
- Junction Temperature - °C
J
J
Figure 8.
Figure 9.
EN PIN VOLTAGE versus TEMPERATURE
EN PIN CURRENT versus TEMPERATURE
-3
1.3
1.29
1.28
1.27
1.26
1.25
1.24
1.23
1.22
1.21
1.2
Vin = 5 V,
Ven = Threshold +50 mV
-3.1
Vin = 3.3 V, rising
-3.2
-3.3
-3.4
-3.5
-3.6
-3.7
-3.8
Vin = 3.3 V, falling
1.19
1.18
1.17
-3.9
-4
1.16
1.15
-50
-50
-25
0
25
50
75
100
125
150
-25
0
25
50
75
100
125
T - Junction Temperature - °C
J
T
- Junction Temperature - °C
J
Figure 10.
Figure 11.
EN PIN CURRENT versus TEMPERATURE
CHARGE CURRENT versus TEMPERATURE
-1
-1.2
-1.4
-1.6
-1.8
-2
-1.4
-1.6
-1.8
-2
Vin = 5 V
Vin = 5 V,
Ven = Threshold -50 mV
-2.2
-2.4
-2.6
-2.2
-2.4
-2.6
-2.8
-3
-2.8
-3
-50
-30
-10
10
30
50
70
90
110
130
150
-50
-25
0
25
50
75
100
125
T
- Junction Temperature - °C
T
- Junction Temperature - °C
J
J
Figure 12.
Figure 13.
8
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TYPICAL CHARACTERISTICS CURVES (continued)
INPUT VOLTAGE versus TEMPERATURE
SHUTDOWN SUPPLY CURRENT versus TEMPERATURE
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
8
Vin = 3.3 V
7
6
5
4
3
2
UVLO Stop Switching
UVLO Start Switching
1
0
2
-50
-50
-25
0
25
50
75
100
125
150
-25
0
25
50
75
100
125
150
T
- Junction Temperature - °C
T
- Junction Temperature - °C
J
J
Figure 14.
Figure 15.
SHUTDOWN SUPPLY CURRENT versus INPUT VOLTAGE
8
VIN SUPPLY CURRENT versus JUNCTION TEMPERATURE
800
T
= 25°C
Vin = 3.3 V
J
7
6
5
4
3
2
700
600
500
400
300
200
1
0
3
3.5
4
4.5
V - Input Voltage - V
I
5
5.5
6
-50
-25
0
25
50
75
100
125
150
T
- Junction Temperature - °C
J
Figure 16.
Figure 17.
VIN SUPPLY CURRENT versus INPUT VOLTAGE
PWRGD THRESHOLD versus TEMPERATURE
800
700
600
500
400
110
T
= 25°C
J
108
106
104
102
100
98
Vsense Rising, Vin = 5 V
Vsense Falling
96
Vsense Rising
Vsense Falling
94
92
300
200
90
88
-50
-25
0
25
50
75
100
125
150
3
3.5
4
4.5
V - Input Voltage - V
I
5
5.5
6
T
- Junction Temperature - °C
J
Figure 18.
Figure 19.
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TYPICAL CHARACTERISTICS CURVES (continued)
PWRGD ON-RESISTANCE versus TEMPERATURE
SS/TR-TO-VSENSE OFFSET versus TEMPERATURE
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
20
Vin = 5 V,
SS = 0.4 V
Vin = 3.3 V
10
0
10
0
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
T
- Junction Temperature - °C
T
- Junction Temperature - °C
J
J
Figure 20.
Figure 21.
EFFICIENCY versus LOAD CURRENT
EFFICIENCY versus LOAD CURRENT
100
100
95
90
85
80
75
70
65
60
95
90
85
80
75
70
65
60
Vout = 3.3 V
Vout = 1.8 V
Vout = 1.8 V
Vout = 1.05 V
Vout = 1.05 V
Vin = 5 V,
f
Vin = 3.5 V,
= 1 MHz,
f
= 1 MHz,
T = 25°C
J
s
s
55
50
55
50
T
= 25°C
J
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Output Current - A
Figure 22.
Output Current - A
Figure 23.
EFFICIENCY versus LOAD CURRENT
EFFICIENCY versus LOAD CURRENT
100
95
90
85
80
75
70
65
60
100
95
90
85
80
75
70
65
60
Vout = 3.3 V
Vout = 1.8 V
Vout = 1.8 V
Vout = 1.05 V
Vout = 1.05 V
Vin = 5 V,
f
Vin = 3.5 V,
= 500 kHz,
f
= 500 kHz,
T = 25°C
J
s
s
55
50
55
50
T
= 25°C
J
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Output Current - A
Figure 24.
Output Current - A
Figure 25.
10
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OVERVIEW
The TPS54618RTE-Q1 is a 6-V, 6-A, synchronous step-down (buck) converter with two integrated n-channel
MOSFETs. To improve performance during line and load transients, the device implements a constant-
frequency, peak-current-mode control which reduces output capacitance and simplifies external frequency-
compensation design. The wide switching-frequency range of 200 to 2000 kHz allows for efficiency and size
optimization when selecting the output-filter components. A resistor to ground on the RT/CLK pin adjusts the
switching frequency. The device has an internal phase-lock loop (PLL) on the RT/CLK pin that synchronizes the
power switch turnon to the falling edge of an external system clock.
The TPS54618RTE-Q1 has a typical default start-up voltage of 2.45 V. The EN pin has an internal pullup current
source that is usable for adjusting the input voltage undervoltage lockout (UVLO) with two external resistors. In
addition, the pullup current provides a default condition for the device to operate when the EN pin is floating. The
total operating current for the TPS54618RTE-Q1 is typically 515 μA when not switching and under no load.
When the device is disabled, the supply current is less than 5.5 μA.
The integrated 12-mΩ MOSFETs allow for high-efficiency power-supply designs with continuous output currents
up to 6 amperes.
The TPS54618RTE-Q1 reduces the external component count by integrating the boot recharge diode. A
capacitor between the BOOT and PH pins supplies the bias voltage for the integrated high-side MOSFET. A
UVLO circuit monitors the boot capacitor voltage and turns off the high-side MOSFET when the voltage falls
below a preset threshold. This BOOT circuit allows the TPS54618RTE-Q1 to operate approaching 100%. The
device can step down the output voltage to as low as the 0.799-V reference.
The TPS54618RTE-Q1 has a power-good (PWRGD) comparator with 2% hysteresis.
The TPS54618RTE-Q1 minimizes excessive output overvoltage transients by taking advantage of the
overvoltage power-good comparator. The regulated output voltage rising above 109% of the nominal voltage
activates the overvoltage comparator, turning off the high-side MOSFET and masking it from turning back on
until the output voltage is lower than 107%.
A use of the SS/TR (slow start/tracking) pin is to minimize inrush currents or provide power-supply sequencing
during power up. Couple a small-value capacitor to the pin for slow start. Discharge of the SS/TR pin occurs
before the output power up to ensure a repeatable restart after an overtemperature fault, UVLO fault, or disabled
condition.
The use of a frequency fold-back circuit reduces the switching frequency during start-up and overcurrent fault
conditions to help limit the inductor current.
DETAILED DESCRIPTION
FIXED FREQUENCY PWM CONTROL
The TPS54618RTE-Q1 uses an adjustable fixed-frequency, peak-current-mode control. External resistors on the
VSENSE pin compare the output voltage to an internal voltage reference by an error amplifier which drives the
COMP pin. An internal oscillator initiates the turnon of the high-side power switch. The device compares the
error-amplifier output to the high-side power-switch current. When the power-switch current reaches the COMP
voltage level, the high-side power switch turns off and the low-side power switch turns on. The COMP pin voltage
increases and decreases as the output current increases and decreases. The device implements a current limit
by clamping the COMP pin voltage to a maximum level and also implements a minimum clamp for improved
transient response performance.
SLOPE COMPENSATION AND OUTPUT CURRENT
The TPS54618RTE-Q1 adds a compensating ramp to the switch-current signal. This slope compensation
prevents sub-harmonic oscillations as duty cycle increases. The available peak inductor current remains constant
over the full duty-cycle range.
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BOOTSTRAP VOLTAGE (BOOT) AND LOW-DROPOUT OPERATION
The TPS54618RTE-Q1 has an integrated boot regulator and requires a small ceramic capacitor between the
BOOT and PH pins to provide the gate-drive voltage for the high-side MOSFET. The value of the ceramic
capacitor should be 0.1 μF. TI recommends a ceramic capacitor with an X7R or X5R grade dielectric with a
voltage rating of 10 V or higher because of the stable characteristics over temperature and voltage.
To improve dropout, the TPS54618RTE-Q1 operates at 100% duty cycle as long as the BOOT to PH pin voltage
is greater than 2.2 V. The high-side MOSFET turns off using a UVLO circuit, allowing for the low-side MOSFET
to conduct when the voltage from BOOT to PH drops below 2.2 V. Because the supply current sourced from the
BOOT pin is very low, the high-side MOSFET can remain on for more switching cycles than are required to
refresh the capacitor. Thus, the effective duty cycle of the switching regulator is very high.
ERROR AMPLIFIER
The TPS54618RTE-Q1 has a transconductance amplifier. The error amplifier compares the VSENSE voltage to
the lower of the SS/TR pin voltage or the internal 0.799-V voltage reference. The transconductance of the error
amplifier is 245 μA/V during normal operation. When the voltage of VSENSE pin is below 0.799 V and the device
is regulating using the SS/TR voltage, the gm is typically greater than 79 μA/V, but less than 245 μA/V. The
placement of frequency-compensation components is between the COMP pin and ground.
VOLTAGE REFERENCE
The voltage-reference system produces a precise ±1% voltage reference over temperature by scaling the output
of a temperature-stable band-gap circuit. The band-gap and scaling circuits produce 0.799 V at the non-inverting
input of the error amplifier.
ADJUSTING THE OUTPUT VOLTAGE
A resistor divider from the output node to the VSENSE pin sets the output voltage. TI recommends using divider
resistors with 1% tolerance or better. Start with 100 kΩ for the R1 resistor and use Equation 1 to calculate R2. To
improve efficiency at very light loads, consider using larger-value resistors. If the values are too high, the
regulator is more susceptible to noise and voltage errors from the VSENSE input current are noticeable.
vertical spacer
vertical spacer
æ
ç
è
ö
÷
ø
0.799 V
R2 = R1 ´
VO - 0.799 V
(1)
TPS54618-Q1
V
O
R1
R2
VSENSE
–
+
0.799 V
Figure 26. Voltage-Divider Circuit
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ENABLE AND ADJUSTING UNDERVOLTAGE LOCKOUT
The VIN pin voltage falling below 2.28 Vdisables the TPS54618RTE-Q1. If an application requires a higher
undervoltage lockout (UVLO), use the EN pin as shown in Figure 27 to adjust the input-voltage UVLO by using
two external resistors. TI recommends using the EN resistors to set the UVLO falling threshold (VSTOP) above 2.6
V. Set the rising threshold (VSTART) to provide enough hysteresis to allow for any input supply variations. The EN
pin has an internal pullup current source that provides the default condition of the TPS54618RTE-Q1 operating
when the EN pin floats. Once the EN pin voltage exceeds 1.25 V, an additional 1.6 μA of hysteresis is added.
Pulling the EN pin below 1.18 V removes the 1.6 μA. This additional current facilitates input-voltage hysteresis.
TPS54618-Q1
i
hys
VIN
1.6 mA
i
1
R1
R2
1.9 mA
+
EN
–
Figure 27. Adjustable Undervoltage Lockout
æ
ç
è
ö
VENFALLING
VSTART
- VSTOP
÷
VENRISING
ø
R1 =
æ
ö
÷
ø
VENFALLING
I
1-
+I
p ç
h
VENRISING
è
(2)
(3)
vertical spacer
R1´ VENFALLING
R2 =
VSTOP - VENFALLING + R1(Ip + Ih )
where R1 and R2 are in ohms, Ih = 1.6 µA, Ip = 1.9 µA, VENRISING = 1.25 V, VENFALLING = 1.18 V
SLOW-START OR TRACKING PIN
The TPS54618RTE-Q1 regulates to the lower of the SS/TR pin and the internal reference voltage. A capacitor on
the SS/TR pin to ground implements a slow-start time. The TPS54618RTE-Q1 has an internal pullup current
source of 2 μA which charges the external slow-start capacitor. Equation 4 calculates the required slow-start
capacitor value, where tSS is the desired slow-start time in ms, ISS is the internal slow-start charging current of 2
μA, and VREF is the internal voltage reference of 0.799 V.
vertical spacer
Tss(mS) ´ Iss(mA)
Css(nF) =
Vref(V)
(4)
During normal operation, the VIN going below UVLO, the pulling of the EN pin voltage below 1.2 V, or the
occurrence of a thermal shutdown event stops the TPS54618RTE-Q1 from switching. On the VIN going above
UVLO, the release or pulling high of the EN pin, or exit of a thermal shutdown, SS/TR discharges to below 40
mV before reinitiating a power-up sequence. The VSENSE voltage follows the SS/TR pin voltage with a 54-mV
offset up to 85% of the internal voltage reference. When the SS/TR voltage is greater than 85% of the internal
reference voltage, the offset increases as the effective system reference transitions from the SS/TR voltage to
the internal voltage reference.
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SEQUENCING
One can implement many of the common power-supply sequencing methods using the SS/TR, EN, and PWRGD
pins. Implementation of the sequential method can be by using an open-drain or collector output of a power-on-
reset pin of another device. Figure 28 shows the sequential method. Coupling of the power-good signal to the EN
pin on the TPS54618RTE-Q1 enables the second power supply once the primary supply reaches regulation.
One can implement ratiometric start-up by connecting the SS/TR pins together. The regulator outputs ramp up
and reach regulation at the same time. Double the current source in Equation 4 when calculating the slow-start
time. Figure 30 illustrates the ratiometric method.
TPS54618-Q1
EN2
PWRGD1
EN1
EN1
SS1
SS2
EN2
PWRGD2
VO1
VO2
Figure 28. Sequential Start-Up Sequence
Figure 29. Sequential Startup using EN and
PWRGD
TPS54618-Q1
EN1
SS/TR1
EN
SS
PWRGD1
TPS54618-Q1
VO1
VO2
EN2
SS/TR2
PWRGD2
Figure 30. Schematic for Ratiometric Start-Up
Figure 31. Ratiometric Startup
Sequence
vertical spacer
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One can implement ratiometric and simultaneous power-supply sequencing by connecting the resistor network of
R1 and R2 shown in Figure 32 to the output of the power supply to be tracked or to another voltage reference
source. Using Equation 5 and Equation 6, calculate values of the tracking resistors to initiate the VOUT2 slightly
before, after, or at the same time as VOUT1. Equation 7 is the voltage difference between VOUT1 and VOUT2.
The ΔV variable is zero volts for simultaneous sequencing. Including VSSOFFSET and ISS are included as variables
in the equations minimizes the effect of the inherent SS/TR to VSENSE offset (VSSOFFSET) in the slow-start circuit
and the offset created by the pullup current source (ISS) and tracking resistors. To design a ratiometric start-up in
which the VOUT2 voltage is slightly greater than the VOUT1 voltage when VOUT2 reaches regulation, use a
negative number in Equation 5 through Equation 7 for ΔV. Equation 7 results in a positive number for
applications in which the VOUT2 is slightly lower than VOUT1 when VOUT2 regulation is achieved. The
requirement for pulling the SS/TR pin below 40 mV before starting after an EN, UVLO, or thermal-shutdown fault
necessitates careful selection of the tracking resistors to ensure the device restarts after a fault. Make sure the
calculated R1 value from Equation 5 is greater than the value calculated in Equation 8 to ensure the device can
recover from a fault. As the SS/TR voltage becomes more than 85% of the nominal reference voltage, the
VSSOFFSET becomes larger as the slow-start circuits gradually hand off the regulation reference to the internal
voltage reference. The SS/TR pin voltage must be greater than 1.1 V for a complete handoff to the internal
voltage reference as shown in Figure 31.
vertical spacer
Vout2 + DV
Vssoffset
Iss
R1 =
´
Vref
(5)
vertical spacer
Vref ´ R1
R2 =
Vout2 + DV - Vref
(6)
(7)
(8)
vertical spacer
DV = Vout1 - Vout2
vertical spacer
R1> 2930´ Vout1-145´DV
vertical spacer
TPS54618-Q1
EN1
VOUT1
EN1
SS/TR1
PWRGD1
SS2
Vout1
Vout2
TPS54618-Q1
VOUT2
EN2
R1
R2
SS/TR2
PWRGD2
Figure 32. Ratiometric and Simultaneous Start-Up
Sequence
Figure 33. Ratiometric Start-Up Using Coupled
SS/TR Pins
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CONSTANT SWITCHING FREQUENCY and TIMING RESISTOR (RT/CLK Pin)
The switching frequency of the TPS54618RTE-Q1 is adjustable over a wide range from 300 kHz to 2000 kHz by
placing a maximum of 700 kΩ and minimum of 85 kΩ, respectively, on the RT/CLK pin. An internal amplifier
holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. RT/CLK
is typically 0.5 V. To determine the timing resistance for a given switching frequency, use the curve in Figure 6 or
Equation 9.
235892
RT kW =
( )
1.027
fSW kHz
(
)
(9)
vertical spacer
kHz =
171032
f
(
)
SW
0.974
RT kW
( )
(10)
To reduce the solution size, one would typically set the switching frequency as high as possible, but consider
tradeoffs of the efficiency, maximum input voltage, and minimum controllable on-time.
The minimum controllable on time is typically 75 ns at full-current load and 120 ns at no load, and limits the
maximum operating input voltage or output voltage.
OVERCURRENT PROTECTION
The TPS54618RTE-Q1 implements a cycle-by-cycle current limit. During each switching cycle, there is a
comparison of the high-side switch current to the voltage on the COMP pin. When the instantaneous switch
current intersects the COMP voltage, the high-side switch turns off. During overcurrent conditions that pull the
output voltage low, the error amplifier responds by driving the COMP pin high, increasing the switch current. An
internal clamp on the error amplifier output functions as a switch-current limit.
FREQUENCY SHIFT
To operate at high switching frequencies and provide protection during overcurrent conditions, the
TPS54618RTE-Q1 implements a frequency shift. Without implementation of the frequency shift, during an
overcurrent condition the low-side MOSFET may not be turn off long enough to reduce the current in the
inductor, causing a current runaway. With frequency shift, during an overcurrent condition the switching
frequency is reduced from 100%, then 50%, then 25%, as the voltage decreases from 0.799 to 0 volts on the
VSENSE pin, to allow the low-side MOSFET to be off long enough to decrease the current in the inductor. During
start-up, the switching frequency increases as the voltage on VSENSE increases from 0 to 0.799 volts. See
Figure 7 for details.
REVERSE OVERCURRENT PROTECTION
The TPS54618RTE-Q1 implements low-side current protection by detecting the voltage across the low-side
MOSFET. When the converter sinks current through its low-side FET, the control circuit turns off the low-side
MOSFET if the reverse current is typically more than 4.5 A. By implementing this additional protection scheme,
the converter is able to protect itself from excessive current during power cycling and start-up into pre-biased
outputs.
SYNCHRONIZE USING THE RT/CLK PIN
A use of the RT/CLK pin is to synchronize the converter to an external system clock. See Figure 34. To
implement the synchronization feature in a system, connect a square wave to the RT/CLK pin with an on-time of
at least 75 ns. Pulling the pin above the PLL upper threshold initiates a mode change, and the pin becomes a
synchronization input. The device disables the internal amplifier, and the pin is a high-impedance clock input to
the internal PLL. Cessation of clocking edges re-enables the internal amplifier and the mode returns to the
frequency set by the resistor. The square-wave amplitude at this pin must transition lower than 0.6 V and higher
than 1.6 V, typically. The synchronization frequency range is 300 kHz to 2000 kHz. The rising edge of the PH
synchronizes to the falling edge of the RT/CLK pin.
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TPS54618-Q1
SYNC Clock
PLL
RT/CLK
Clock
RT
Source
PH
Figure 34. Synchronizing to a System Clock
Figure 35. Plot of Synchronizing to System Clock
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POWER GOOD (PWRGD PIN)
The PWRGD pin output is an open-drain MOSFET. The VSENSE voltage entering the fault condition by falling
below 91% or rising above 109% of the nominal internal reference voltage pulls the output low. There is a 2%
hysteresis on the threshold voltage, so when the VSENSE voltage rises to the good condition above 93% or falls
below 107% of the internal voltage reference, the PWRGD output MOSFET turns off. TI recommends use of a
pullup resistor between the values of 1 kΩ and 100 kΩ to a voltage source that is 6 V or less. PWRGD is in a
valid state once the VIN input voltage is greater than 1.5 V.
OVERVOLTAGE TRANSIENT PROTECTION
The TPS54618RTE-Q1 incorporates an overvoltage-transient-protection (OVTP) circuit to minimize voltage
overshoot when recovering from output fault conditions or strong unload transients. The OVTP feature minimizes
the output overshoot by implementing a circuit to compare the VSENSE pin voltage to the OVTP threshold,
which is 109% of the internal voltage reference. The VSENSE pin voltage going greater than the OVTP threshold
disables the high-side MOSFET, preventing current from flowing to the output and minimizing output overshoot.
The VSENSE voltage dropping lower than the OVTP threshold allows the high-side MOSFET to turn on during
the next clock cycle.
THERMAL SHUTDOWN
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 168°C.
The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal
trip threshold. Once the die temperature decreases below 150°C, the device reinitiates the power-up sequence
by discharging the SS pin to below 40 mV. The thermal shutdown hysteresis is 20°C.
SMALL-SIGNAL MODEL FOR LOOP RESPONSE
Figure 36 shows for the TPS54618RTE-Q1 control loop an equivalent model which one can modeled in a circuit-
simulation program to check frequency response and dynamic load response. The error amplifier is a
transconductance amplifier with a gm of 245 μA/V. One can model the error amplifier using an ideal voltage-
controlled current source. Resistor R0 and capacitor C0 model the open-loop gain and frequency response of the
amplifier. The 1-mV ac voltage source between nodes a and b effectively breaks the control loop for the
frequency-response measurements. Plotting a / c shows the small-signal response of the frequency
compensation. Plotting a / b shows the small-signal response of the overall loop. One can check the dynamic
loop response by replacing the RL with a current source with the appropriate load-step amplitude and step rate in
a time-domain analysis.
PH
VO
Power Stage
25 A/V
a
b
R1
RESR
RL
COMP
c
COUT
VSENSE
R2
0.799 V
C0 R0
R3
C1
gm
245 µA/V
C2
Figure 36. Small-Signal Model for Loop Response
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SIMPLE SMALL-SIGNAL MODEL FOR PEAK CURRENT MODE CONTROL
Figure 36 is a simple small-signal model that one can use to understand how to design the frequency
compensation. A voltage-controlled current source (duty cycle modulator) supplying current to the output
capacitor and load resistor an approximate the TPS54618RTE-Q1 power stage. The control to output transfer
function, shown in Equation 11, consists of a dc gain, one dominant pole, and one ESR zero. The quotient of the
change in switch current and the change in COMP pin voltage (node c in Figure 36) is the power-stage
transconductance. The gm for the TPS54618RTE-Q1 is 25 A/V. The low-frequency gain of the power-stage
frequency response is the product of the transconductance and the load resistance, as shown in Equation 12. As
the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This
variation with load may seem problematic at first glance, but the dominant pole moves with load current (see
Equation 13). The combined effect is highlighted by the dashed line in the right half of Figure 37. As the load
current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the
same for the varying load conditions, which makes it easier to design the frequency compensation.
vertical spacer
vertical spacer
VO
Adc
VC
R
ESR
fp
R
L
gm
ps
C
OUT
fz
Figure 37. Simple Small-Signal Model and Frequency Response for Peak-Current-Mode Control
æ
ç
è
æ
ç
è
s
ö
÷
ø
ö
÷
ø
1+
1+
2p × ¦z
vo
vc
= Adc ´
s
2p × ¦p
(11)
(12)
Adc = gmps ´ RL
1
¦p =
COUT ´ RL ´ 2p
(13)
vertical spacer
¦z =
1
COUT ´ RESR ´ 2p
(14)
SMALL-SIGNAL MODEL FOR FREQUENCY COMPENSATION
The TPS54618RTE-Q1 uses a transconductance amplifier for the error amplifier and readily supports two of the
commonly used frequency-compensation circuits. Figure 38 shows the compensation circuits. High-bandwidth
power-supply designs using low-ESR output capacitors most likely implement Type 2 circuits. Type 2A adds one
additional high-frequency pole to attenuate high-frequency noise.
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VO
R1
VSENSE
Type 2A
Type 2B
COMP
gm
ea
CO
Vref
R2
R3
C1
C2
R3
RO
5pF
C1
Figure 38. Types of Frequency Compensation
The design guidelines for TPS54618RTE-Q1 loop compensation are as follows:
1. Calculate the modulator pole, ƒpmod, and the ESR zero, ƒz1, using Equation 15 and Equation 16. The output
capacitor (COUT) may require derating if the output voltage is a high percentage of the capacitor rating. Use
the capacitor manufacturer information to derate the capacitor value. Use Equation 17 and Equation 18 to
estimate a starting point for the crossover frequency, ƒc. Equation 17 is the geometric mean of the modulator
pole and the ESR zero, and Equation 18 is the mean of the modulator pole and the switching frequency. Use
the lower value of Equation 17 or Equation 18 as the maximum crossover frequency.
Ioutmax
¦p mod =
2p ´ Vout ´ Cout
(15)
vertical spacer
1
¦z mod =
2p ´ Resr ´ Cout
(16)
vertical spacer
¦
=
¦p mod´ ¦z mod
vertical spacer
¦p mod´
C
(17)
(18)
¦sw
¦
=
C
2
vertical spacer
2. Determine R3 by
2p × ¦c ´ Vo ´ COUT
R3 =
gmea ´ Vref ´ gmps
(19)
vertical spacer
where is the gmea amplifier gain (245 μA/V) and gmps is the power stage gain (25 A/V).
1
¦p =
COUT ´ RL ´ 2p
3. Place a compensation zero at the dominant pole.
4. Determine C1 by:
RL ´ COUT
C1 =
R3
(20)
(21)
5. C2 is optional. One can use C2 to cancel the zero from the ESR of C0.
Resr ´ COUT
C2 =
R3
20
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APPLICATION INFORMATION
DESIGN GUIDE – STEP-BY-STEP DESIGN PROCEDURE
This example details the design of a high-frequency switching-regulator design using ceramic output capacitors.
This design is available as the HPA606 evaluation module (EVM). One must know a few parameters in order to
start the design process. Determination of these parameters is typically at the system level. For this example, we
start with the following known parameters:
Output voltage
1.8 V
Transient response 1.5-A to 4.5-A load step
Maximum Output Current
Input voltage
ΔVOUT = 4%
6 A
3 V to 6 V, 5-V nominal
< 30 mV p-p
1000 kHz
Output-voltage ripple
Switching frequency (fsw
)
SELECTING THE SWITCHING FREQUENCY
The first step is to decide on a switching frequency for the regulator. Typically, one wants to choose the highest
switching frequency possible, because this produces the smallest solution size. The high switching frequency
allows for lower-valued inductors and smaller output capacitors, compared to a power supply that switches at a
lower frequency. However, the highest switching frequency causes extra switching losses, which hurt the
converter’s performance. The converter is capable of running from 300 kHz to 2 MHz. Unless a small solution
size is an ultimate goal, select a moderate switching frequency of 1 MHz to achieve both a small solution size
and high-efficiency operation. Using Equation 9, the calculated value of R4 is 180 kΩ. Choose a standard 1%
182-kΩ value for the design.
-Q1
Figure 39. High Frequency, 1.8-V Output Power-Supply Design With Adjusted UVLO
OUTPUT-INDUCTOR SELECTION
The inductor selected works for the entire TPS54618RTE-Q1 input voltage range. To calculate the value of the
output inductor, use Equation 22. KIND is a coefficient that represents the amount of inductor ripple current
relative to the maximum output current. The output capacitor filters the inductor ripple current. Therefore,
choosing high inductor ripple currents impacts the selection of the output capacitor, because the output capacitor
must have a ripple-current rating equal to or greater than the inductor ripple current. In general, the inductor
ripple value is at the discretion of the designer; however, KIND is normally from 0.1 to 0.3 for the majority of
applications.
For this design example, use KIND = 0.3 and calculate the inductor value to be 0.7 μH. For this design, choose a
nearest standard value: 0.75 μH. For the output filter inductor, it is important that the rms-current and saturation-
current ratings not be exceeded. The rms and peak inductor current can be found from Equation 24 and
Equation 25.
For this design, the rms inductor current is 6.01 A and the peak inductor current is 6.84 A. The chosen inductor is
a Toko FDV0630-R75M. It has a saturation-current rating 0f 10 A and an rms-current rating of 8.9 A.
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The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults, or transient-load conditions, the inductor current can increase above the peak inductor current level
calculated previously. In transient conditions, the inductor current can increase up to the switch-current limit of
the device. For this reason, the most conservative approach is to specify an inductor with a saturation current
rating equal to or greater than the switch-current limit rather than the peak inductor current.
Vinmax - Vout
Vout
L1 =
´
Io ´ Kind
Vinmax ´ ¦sw
(22)
vertical spacer
Vinmax - Vout
Vout
Iripple =
´
L1
Vinmax ´ ¦sw
(23)
vertical spacer
æ
ö2
÷
1
Vo ´ (Vinmax - Vo)
Vinmax ´ L1 ´ ¦sw
ILrms = Io2
+
´
ç
12
è
ø
(24)
(25)
vertical spacer
ILpeak = Iout +
Iripple
2
OUTPUT CAPACITOR
There are three primary considerations for selecting the value of the output capacitor. The output capacitor
determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in
load current. The basis of the output capacitance selection must be the most-stringent of these three criteria.
The desired response to a large change in the load current is the first criterion. The output capacitor must supply
the load with current when the regulator cannot. This situation would occur if there are desired hold-up times for
the regulator where the output capacitor must hold the output voltage above a certain level for a specified
amount of time after the input power is removed. The regulator is temporarily not able to supply sufficient output
current if there is a large, fast increase in the current needs of the load such as transitioning from no load to a full
load. The regulator usually requires two or more clock cycles for the control loop to see the change in load
current and output voltage and adjust the duty cycle to react to the change. The output capacitor size must be
able to supply the extra current to the load until the control loop responds to the load change. The output
capacitance must be large enough to supply the difference in current for two clock cycles while only allowing a
tolerable amount of droop in the output voltage. Equation 26 shows the minimum output capacitance necessary
to accomplish this.
For this example, the transient load response specification is a 3% change in Vout for a load step from 1.5 A
(25% load) to 4.5 A (75% load). For this example, ΔIout = 4.5 – 1.5 = 3.0 A and ΔVout = 0.04 × 1.8 = 0.072 V.
Using these numbers gives a minimum capacitance of 83 μF. This value does not take the ESR of the output
capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to
ignore in this calculation.
Equation 27 calculates the minimum output capacitance needed to meet the output-voltage ripple specification,
where fsw is the switching frequency, Vripple is the maximum allowable output voltage ripple, and Iripple is the
inductor ripple current. In this case, the maximum output-voltage ripple is 30 mV. Under this requirement,
Equation 27 yields 7 uF.
vertical spacer
2 ´ DIout
Co >
¦sw ´ DVout
(26)
vertical spacer
1
1
Co >
´
Voripple
8 ´ ¦sw
Iripple
(27)
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where ΔIout is the change in output current, fsw is the regulators switching frequency, and ΔVout is the allowable
change in the output voltage.
vertical spacer
Equation 28 calculates the maximum ESR an output capacitor can have to meet the output-voltage ripple
specification. Equation 28 indicates the ESR should be less than 18 mΩ. In this case, the ESR of the ceramic
capacitor is much less than 18 mΩ.
Factoring in additional capacitance de-ratings for aging, temperature, and dc bias increases this minimum value.
For this example, use five 22-μF, 10-V X5R ceramic capacitors with 3 mΩ of ESR. The estimated capacitance
after derating by a factor of 0.75 is 82.5 µF.
Capacitors generally have limits to the amount of ripple current they can handle without failing or producing
excess heat. One must select an output capacitor that can support the inductor ripple current. Some capacitor
data sheets specify the rms (root mean square) value of the maximum ripple current. Use Equation 29 to
calculate the rms ripple current that the output capacitor must support. For this application, Equation 29 yields
520 mA.
Voripple
Resr <
Iripple
(28)
vertical spacer
Vout ´ (Vinmax - Vout)
Icorms =
12 ´ Vinmax ´ L1 ´ ¦sw
(29)
INPUT CAPACITOR
The TPS54618RTE-Q1 requires a high-quality ceramic, type X5R or X7R, input decoupling capacitor of at least
10 μF of effective capacitance, and in some applications, a bulk capacitance. The effective capacitance includes
any dc bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage.
The capacitor must also have a ripple-current rating greater than the maximum input-current ripple of the
TPS54618RTE-Q1. Calculate the input-current ripple using Equation 30.
The value of a ceramic capacitor varies significantly over temperature and the amount of dc bias applied to the
capacitor. One can minimize the capacitance variations due to temperature by selecting a dielectric material that
is stable over temperature. Designers usually select X5R and X7R ceramic dielectrics for power regulator
capacitors because they have a high capacitance-to-volume ratio and are fairly stable over temperature. One
must also select the output capacitor with the dc bias taken into account. The capacitance value of a capacitor
decreases as the dc bias across a capacitor increases.
This example design requiresa ceramic capacitor with at least a 10-V voltage rating to support the maximum
input voltage. The selection for this example is two 10-μF and one 0.1-μF 10-V capacitors in parallel. The input
capacitance value determines the input ripple voltage of the regulator. Calculate the input-voltage ripple using
Equation 31. Using the design example values, Ioutmax = 6 A, Cin = 20 μF, and Fsw = 1 MHz, yields an input
voltage ripple of 149 mV and an rms input ripple current of 2.94 A.
Vinmin - Vout
(
)
Vout
Icirms = Iout ´
´
Vinmin
Vinmin
(30)
(31)
vertical spacer
Ioutmax ´ 0.25
Cin ´ ¦sw
DVin =
SLOW-START CAPACITOR
The slow-start capacitor determines the minimum amount of time it takes for the output voltage to reach its
nominal programmed value during power up. This is useful if a load requires a controlled voltage-slew rate. This
is also useful if the output capacitance is very large and would require large amounts of current to charge the
capacitor quickly to the output-voltage level. The large currents necessary to charge the capacitor may make the
TPS54618RTE-Q1 reach the current limit, or excessive current draw from the input power supply may cause the
input voltage rail to sag. Limiting the output-voltage slew rate solves both of these problems.
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One can calculate the slow-start capacitor value using Equation 32. For the example circuit, the slow-start time is
not too critical because the output-capacitor value is 110 μF, which does not require much current to charge to
1.8 V. The example circuit has the slow-start time set to an arbitrary value of 4 ms, which requires a 10-nF
capacitor. In TPS54618RTE-Q1, Iss is 2.2 μA and Vref is 0.799 V.
Tss(ms) ´ Iss(mA)
Css(nF) =
Vref(V)
(32)
BOOTSTRAP CAPACITOR SELECTION
Connect a 0.1-μF ceramic capacitor between the BOOT to PH pin for proper operation. TI recommends using a
ceramic capacitor with X5R or better-grade dielectric. The capacitor should have a 10-V or higher voltage rating.
OUTPUT-VOLTAGE AND FEEDBACK RESISTOR SELECTION
For the example design, the R6 selection was 100 kΩ. Calculating with Equation 33, R7 is 80 kΩ. The nearest
standard 1% resistor is 80.6 kΩ.
Vref
R7 =
R6
Vo - Vref
(33)
Due to the internal design of the TPS54618RTE-Q1, there is a minimum output voltage limit for any given input
voltage. The output voltage can never be lower than the internal voltage reference of 0.799 V. Above 0.799 V,
the minimum controllable on-time may limit the output voltage. In this case, Equation 34 gives the minimum
output voltage.
Voutmin = Ontimemin´Fsmax ´ Vinmax - loutmin´RDSmin -Ioutmin´ RL + RDSmin
(
(
)
)
where:
Voutmin = minimum achievable output voltage
Ontimemin = minimum controllable on-time (75 ns typical. 120 ns no load)
Fsmax = maximum switching frequency, including tolerance
Vinmax = maximum input voltage
Ioutmin = minimum load current
RDSmin = minimum high-side MOSFET on-resistance (See Electrical Characteristics)
RL = series resistance of output inductor
(34)
There is also a maximum achievable output voltage, which is limited by the minimum off-time. Equation 35 gives
the maximum output voltage.
Offtimemax
ts
tdead
ts
æ
ö
æ
ö
Voutmax = Vin´ 1-
-Ioutmax ´ RDSmax + RI - 0.7 -Ioutmax ´RDSmax ´
(
) (
)
ç
÷
ç
÷
è
ø
è
ø
where:
Voutmax = maximum achievable output voltage
Vin = minimum input voltage
Offtimemax = maximum off-time (90 ns typical for adequate margin)
ts = 1/Fs
Ioutmax = maximum current
RDSmax = maximum high-side MOSFET on-resistance (See Electrical Characteristics)
RI = DCR of the inductor
tdead = dead time (60 ns)
(35)
COMPENSATION
There are several industry techniques used to compensate dc-dc regulators. The method presented here is easy
to calculate and yields high phase margins. For most conditions, the regulator has a phase margin between 60
and 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to the
TPS54618RTE-Q1. Ignoring the slope compensation usually results in the actual crossover frequency being
lower than the crossover frequency used in the calculations. Use SwitcherPro software for a more accurate
design.
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To get started, calculate the modulator pole, fpmod, and the ESR zero, fz1 using Equation 36 and Equation 37.
For Cout, the derated capacitance value is 82.5 µF. Use Equation 38 and Equation 39 to estimate a starting
point for the crossover frequency, fc. For the example design, fpmod is 6.43 kHz and fzmod is 643 kHz.
Equation 38 is the geometric mean of the modulator pole and the ESR zero, and Equation 39 is the mean of
modulator pole and the switching frequency. Equation 38 yields 64.3 kHz and Equation 39 gives 56.7 kHz. The
lower value of Equation 38 or Equation 39 is the maximum recommended crossover frequency. For this example,
specify a lower fc value of 40 kHz. Next, calculate the compensation components. Use a resistor in series with a
capacitor to create a compensating zero. A capacitor in parallel with these two components forms the
compensating pole (if needed).
Ioutmax
¦p mod =
2p ´ Vout ´ Cout
(36)
vertical spacer
1
¦z mod =
2p ´ Resr ´ Cout
(37)
vertical spacer
¦
=
¦p mod´ ¦z mod
vertical spacer
¦p mod´
C
(38)
(39)
¦sw
¦
=
C
2
vertical spacer
The compensation design takes the following steps:
1. Set up the anticipated crossover frequency. Use Equation 40 to calculate the resistor value for
thecompensation network. In this example, the anticipated crossover frequency (fc) is 40 kHz. The power-
stage gain (gmps) is 25 A/V and the error-amplifier gain (gmea) is 245 μA/V.
2p × ¦c ´ Vo ´ Co
R3 =
Gm ´ Vref ´ VIgm
(40)
2. Place the compensation zero at the pole formed by the load resistor and the output capacitor. Calculate the
compensation-network capacitor with Equation 41.
Ro ´ Co
C4 =
R3
(41)
3. One can add an additional pole to attenuate high-frequency noise. In this application, it is not necessary to
add such a pole.
From the procedures above, the compensation network includes a 7.50-kΩ resistor and a 3300-pF capacitor.
APPLICATION CURVES
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EFFICIENCY
versus
LOAD CURRENT
EFFICIENCY
versus
LOAD CURRENT
100
90
100
90
Vin = 3.3 V
80
70
60
50
40
30
20
10
0
Vin = 5 V
80
Vin = 3 V
70
60
50
40
30
20
Vin = 5 V
10
0
0.01
0.1
1
10
0
1
2
3
4
5
6
Output Current - A
Output Current - A
Figure 40.
Figure 41.
TRANSIENT RESPONSE, 1.5-A STEP
POWER-UP VOUT, VIN
Vout = 50 mV / div (ac coupled)
Vin = 2 V / div
Iout = 2 A / div (1.5 A to 4.5 A load step)
Vout = 1 V / div
PWRGD = 2 V / div
Time = 2 msec / div
Time = 200 usec / div
Figure 42.
Figure 43.
POWER-UP VOUT, EN
OUTPUT RIPPLE, 3 A
Vout = 10 mV / div (ac coupled)
EN = 2 V / div
Vout = 1 V / div
PH = 2 V / div
PWRGD = 2 V / div
Time = 2 msec / div
Figure 44.
Time = 500 nsec / div
Figure 45.
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INPUT RIPPLE, 3 A
CLOSED LOOP RESPONSE, VIN (5 V), 3 A
60
50
40
180
150
120
Vin = 100 mV / div (ac coupled)
30
20
90
60
10
30
0
0
PH = 2 V / div
–10
–30
–20
–30
–40
–50
–60
–60
–90
–120
–150
Gain
Phase
–180
100
1000
10k
Frequency - Hz
100k
1M
Time = 500 nsec / div
Figure 46.
Figure 47.
LOAD REGULATION
versus
LOAD CURRENT
REGULATION
versus
INPUT VOLTAGE
0.4
0.3
0.4
0.3
Iout = 3 A
Vin = 5 V
0.2
0.1
0.2
0.1
Vin = 3.3 V
0
0
-0.1
-0.2
-0.3
-0.4
-0.1
-0.2
-0.3
-0.4
3
3.5
4
4.5
5
5.5
6
0
1
2
3
4
5
6
Input Voltage-V
Output Current - A
Figure 48.
Figure 49.
POWER-DISSIPATION ESTIMATE
The following formulas show how to estimate the IC power dissipation under continuous-conduction-mode (CCM)
operation. The power dissipation of the IC (Ptot) includes conduction loss (Pcon), dead time loss (Pd), switching
loss (Psw), gate-drive loss (Pgd), and supply-current loss (Pq).
Pcon = Io2 × RDS_on_Temp
Pd = ƒsw × Io × 0.7 × 40 × 10–9
Psw = 1/2 × Vin × Io × ƒsw× 13 × 10–9
Pgd = 2 × Vin × ƒsw× 10 × 10–9
Pq = Vin × 515 × 10–6
where:
IO is the output current (A).
RDS_on_Temp is the on-resistance of the high-side MOSFET with given temperature (Ω).
Vin is the input voltage (V).
ƒsw is the switching frequency (Hz).
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So
Ptot = Pcon + Pd + Psw + Pgd + Pq
For given TA,
TJ = TA + Rth × Ptot
For given TJMAX = 150°C
TAmax = TJ max – Rth × Ptot
where:
Ptot is the total device power dissipation (W).
TA is the ambient temperature (°C).
TJ is the junction temperature (°C).
Rth is the thermal resistance of the package (°C/W).
TJMAX is maximum junction temperature (°C).
TAMAX is maximum ambient temperature (°C).
There are additional power losses in the regulator circuit due to the inductor ac and dc losses and trace
resistance that impact the overall efficiency of the regulator.
LAYOUT
Layout is a critical portion of good power-supply design. There are several signal paths that conduct fast-
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade the power-supply performance. Take care to minimize the loop area formed by the bypass capacitor
connections and the VIN pins. See Figure 50 for a PCB layout example. Tie the GND pins and AGND pin directly
to the power pad under the IC. Connect the power pad to any internal PCB ground planes using multiple vias
directly under the IC. One can use additional vias to connect the top-side ground area to the internal planes near
the input and output capacitors. For operation at full-rated load, the top-side ground area along with any
additional internal ground planes must provide adequate heat-dissipating area.
Locate the input bypass capacitor as close to the IC as possible. Route the PH pin to the output inductor.
Because the PH connection is the switching node, the location of the output inductor should be very close to the
PH pin, and minimize the area of the PCB conductor to prevent excessive capacitive coupling. Locate the boot
capacitor close to the device. The sensitive analog ground connections for the feedback-voltage divider,
compensation components, slow-start capacitor, and connect the frequency-setting resistor to a separate analog
ground trace as shown. The RT/CLK pin is particularly sensitive to noise, so locate the RT resistor as close as
possible to the IC and route with minimal lengths of trace. Place the additional external components
approximately as shown. It may be possible to obtain acceptable performance with alternate PCB layouts.
However this layout, meant as a guideline, produces demonstrably good results.
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VIA to
Ground
Plane
UVLO SET
RESISTORS
VIN
BOOT
CAPACITOR
VIN
INPUT
OUTPUT
VIN
VIN
PH
PH
PH
SS
VOUT
BYPASS
CAPACITOR
INDUCTOR
OUTPUT
FILTER
EXPOSED
POWERPAD
AREA
CAPACITOR
GND
GND
PH
SLOW START
CAPACITOR
FEEDBACK
RESISTORS
ANALOG
GROUND
TRACE
FREQUENCY
SET
RESISTOR
COMPENSATION
NETWORK
TOPSIDE
GROUND
AREA
VIA to Ground Plane
Figure 50. PCB Layout Example
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REVISION HISTORY
Changes from Revision B (November 2013) to Revision C
Page
•
•
•
Changed title of data sheet ................................................................................................................................................... 1
Changed absolute maximum voltage for RT/CLK pin from 3.3 V to 4 V .............................................................................. 2
Changed high threshold for RT/CLK pin from 2.5 V to 2.2 V ............................................................................................... 4
Changes from Revision A (September 2013) to Revision B
Page
•
Revised thermal data ............................................................................................................................................................ 3
Changes from Original (August 2013) to Revision A
Page
•
•
Revised the absolute maximum EN voltage input from 3.3 V maximum to a 4 V maximum ............................................... 2
Changed Changed graph title from "SWITCHING FREQUENCY vs RT RESISTANCE LOW FREQUENCY RANGE
Typical Characteristics curve" to "SWITCHING FREQUENCY versus VSENSE." .............................................................. 7
•
•
Changed first equation for Constant Switching Frequency and Timing Resistor ............................................................... 16
Changed second equation for Constant Switching Frequency and Timing Resistor ......................................................... 16
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PACKAGE OPTION ADDENDUM
www.ti.com
22-Nov-2013
PACKAGING INFORMATION
Orderable Device
HPA02246QRTERQ1
TPS54618QRTERQ1
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
WQFN
WQFN
RTE
16
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
618Q1
618Q1
ACTIVE
RTE
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
22-Nov-2013
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS54618-Q1 :
Catalog: TPS54618
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Nov-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS54618QRTERQ1
WQFN
RTE
16
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Nov-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
WQFN RTE 16
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
TPS54618QRTERQ1
3000
Pack Materials-Page 2
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TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
Automotive and Transportation www.ti.com/automotive
Communications and Telecom www.ti.com/communications
Amplifiers
Data Converters
DLP® Products
DSP
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
www.ti.com/computers
www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/industrial
www.ti.com/medical
Medical
Logic
Security
www.ti.com/security
Power Mgmt
Microcontrollers
RFID
power.ti.com
Space, Avionics and Defense
Video and Imaging
www.ti.com/space-avionics-defense
www.ti.com/video
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/omap
OMAP Applications Processors
Wireless Connectivity
TI E2E Community
e2e.ti.com
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated
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