INA114BP [TI]
Precision INSTRUMENTATION AMPLIFIER;
| 型号： | INA114BP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Precision INSTRUMENTATION AMPLIFIER 放大器 光电二极管 |
| 文件： | 总17页 (文件大小：377K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INA114
®
INA114
INA114
Precision
INSTRUMENTATION AMPLIFIER
DESCRIPTION
FEATURES
The INA114 is a low cost, general purpose instrumen-
tation amplifier offering excellent accuracy. Its versa-
tile 3-op amp design and small size make it ideal for a
wide range of applications.
● LOW OFFSET VOLTAGE: 50µV max
● LOW DRIFT: 0.25µV/°C max
● LOW INPUT BIAS CURRENT: 2nA max
● HIGH COMMON-MODE REJECTION:
Asingleexternalresistorsetsanygainfrom1to10,000.
Internal input protection can withstand up to ±40V
without damage.
115dB min
● INPUT OVER-VOLTAGE PROTECTION:
±40V
TheINA114islasertrimmedforverylowoffsetvoltage
(50µV), drift (0.25µV/°C) and high common-mode
rejection (115dB at G = 1000). It operates with power
supplies as low as ±2.25V, allowing use in battery
operated and single 5V supply systems. Quiescent cur-
rent is 3mA maximum.
● WIDE SUPPLY RANGE: ±2.25 to ±18V
● LOW QUIESCENT CURRENT: 3mA max
● 8-PIN PLASTIC AND SOL-16
The INA114 is available in 8-pin plastic and SOL-16
surface-mount packages. Both are specified for the
–40°C to +85°C temperature range.
APPLICATIONS
● BRIDGE AMPLIFIER
● THERMOCOUPLE AMPLIFIER
● RTD SENSOR AMPLIFIER
● MEDICAL INSTRUMENTATION
● DATA ACQUISITION
V+
(13)
7
–
VIN
INA114
2
Over-Voltage
Protection
Feedback
(12)
(4)
A1
25kΩ
25kΩ
DIP Connected
Internally
1
25kΩ
25kΩ
(2)
6
A3
VO
RG
(11)
8
50kΩ
RG
G = 1 +
(15)
5
A2
Ref
+
VIN
3
Over-Voltage
Protection
(10)
25kΩ
25kΩ
(5)
4
(7)
DIP
(SOIC)
V–
International Airport Industrial Park
•
Mailing Address: PO Box 11400, Tucson, AZ 85734
FAXLine: (800) 548-6133 (US/Canada Only)
• Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/
•
•
Cable: BBRCORP
•
Telex: 066-6491
•
FAX: (520) 889-1510
•
Immediate Product Info: (800) 548-6132
©1992 Burr-Brown Corporation
PDS-1142D
Printed in U.S.A. March, 1998
SBOS014
SPECIFICATIONS
ELECTRICAL
At TA = +25°C, VS = ±15V, RL = 2kΩ, unless otherwise noted.
INA114BP, BU
TYP
INA114AP, AU
TYP
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
INPUT
Offset Voltage, RTI
Initial
vs Temperature
TA = +25°C
TA = TMIN to TMAX
VS = ±2.25V to ±18V
±10 + 20/G ±50 + 100/G
±0.1 + 0.5/G ±0.25 + 5/G
±25 + 30/G ±125 + 500/G
µV
µV/°C
µV/V
µV/mo
Ω || pF
Ω || pF
V
±0.25 + 5/G
±1 + 10/G
vs Power Supply
Long-Term Stability
Impedance, Differential
Common-Mode
Input Common-Mode Range
Safe Input Voltage
Common-Mode Rejection
0.5 + 2/G
±0.2 + 0.5/G
1010 || 6
3 + 10/G
✻
✻
✻
✻
✻
✻
1010 || 6
±11
±13.5
✻
±40
✻
V
VCM = ±10V, ∆RS = 1kΩ
G = 1
80
96
110
115
96
75
90
106
106
90
dB
dB
dB
dB
G = 10
G = 100
G = 1000
115
120
120
106
110
110
BIAS CURRENT
vs Temperature
±0.5
±8
±2
±2
✻
✻
±5
±5
nA
pA/°C
OFFSET CURRENT
vs Temperature
±0.5
±8
✻
✻
nA
pA/°C
NOISE VOLTAGE, RTI
f = 10Hz
f = 100Hz
G = 1000, RS = 0Ω
15
11
11
0.4
✻
✻
✻
✻
nV/√Hz
nV/√Hz
nV/√Hz
µVp-p
f = 1kHz
fB = 0.1Hz to 10Hz
Noise Current
f=10Hz
f=1kHz
fB = 0.1Hz to 10Hz
0.4
0.2
18
✻
✻
✻
pA/√Hz
pA/√Hz
pAp-p
GAIN
Gain Equation
Range of Gain
Gain Error
1 + (50kΩ/RG)
✻
V/V
V/V
%
%
%
1
10000
±0.05
±0.4
±0.5
±1
✻
✻
✻
±0.5
±0.7
±2
±10
✻
±0.002
±0.004
±0.004
±0.02
G = 1
G = 10
G = 100
G = 1000
G = 1
±0.01
±0.02
±0.05
±0.5
±2
±25
±0.0001
±0.0005
±0.0005
±0.002
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
%
Gain vs Temperature
50kΩ Resistance(1)
Nonlinearity
±10
ppm/°C
ppm/°C
% of FSR
% of FSR
% of FSR
% of FSR
±100
±0.001
±0.002
±0.002
±0.01
G = 1
G = 10
G = 100
G = 1000
OUTPUT
Voltage
IO = 5mA, TMIN to TMAX
VS = ±11.4V, RL = 2kΩ
VS = ±2.25V, RL = 2kΩ
±13.5
±10
±1
±13.7
±10.5
±1.5
1000
+20/–15
✻
✻
✻
✻
✻
✻
✻
✻
V
V
V
pF
mA
Load Capacitance Stability
Short Circuit Current
FREQUENCY RESPONSE
Bandwidth, –3dB
G = 1
G = 10
G = 100
1
100
10
1
0.6
18
20
120
1100
20
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
MHz
kHz
kHz
kHz
V/µs
µs
µs
µs
µs
µs
G = 1000
VO = ±10V, G = 10
G = 1
G = 10
G = 100
G = 1000
50% Overdrive
Slew Rate
Settling Time, 0.01%
0.3
✻
✻
Overload Recovery
POWER SUPPLY
Voltage Range
Current
±2.25
±15
±2.2
±18
±3
✻
✻
✻
✻
V
mA
VIN = 0V
TEMPERATURE RANGE
Specification
Operating
–40
–40
85
125
✻
✻
✻
✻
°C
°C
θJA
80
✻
°C/W
✻ Specification same as INA114BP/BU.
NOTE: (1) Temperature coefficient of the “50kΩ” term in the gain equation.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
2
INA114
PIN CONFIGURATIONS
ELECTROSTATIC
DISCHARGE SENSITIVITY
P Package
8-Pin DIP
Top View
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with ap-
propriate precautions. Failure to observe proper handling and
installation procedures can cause damage.
RG
1
2
3
4
8
7
6
5
RG
V+
VO
Ref
V–
IN
IN
V+
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
V–
U Package
SOL-16 Surface-Mount
Top View
NC
RG
NC
1
2
3
4
5
6
7
8
16 NC
PACKAGE/ORDERING INFORMATION
15 RG
PACKAGE
DRAWING TEMPERATURE
14 NC
PRODUCT
PACKAGE
NUMBER(1)
RANGE
V–
13 V+
IN
IN
INA114AP
INA114BP
INA114AU
INA114BU
8-Pin Plastic DIP
8-Pin Plastic DIP
SOL-16 Surface-Mount
SOL-16 Surface-Mount
006
006
211
211
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
V+
12 Feedback
11 VO
NC
V–
10 Ref
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
NC
9
NC
ABSOLUTE MAXIMUM RATINGS(1)
Supply Voltage .................................................................................. ±18V
Input Voltage Range .......................................................................... ±40V
Output Short-Circuit (to ground) .............................................. Continuous
Operating Temperature ................................................. –40°C to +125°C
Storage Temperature..................................................... –40°C to +125°C
Junction Temperature .................................................................... +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
NOTE: (1) Stresses above these ratings may cause permanent damage.
®
3
INA114
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VS = ±15V, unless otherwise noted.
COMMON-MODE REJECTION vs FREQUENCY
G = 100, 1k
G = 10
GAIN vs FREQUENCY
140
120
100
80
1k
100
10
G = 1k
G = 100
60
G = 10
G = 1
40
1
20
0
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
Frequency (Hz)
Frequency (Hz)
INPUT COMMON-MODE VOLTAGE RANGE
vs OUTPUT VOLTAGE
POSITIVE POWER SUPPLY REJECTION
vs FREQUENCY
15
10
5
140
120
100
80
–
VD/2
VO
+
–
G = 1000
VD/2
+
G = 100
G = 10
VCM
0
(Any Gain)
60
A3 – Output
Swing Limit
A3 + Output
Swing Limit
–5
–10
–15
G = 1
40
20
0
–15
–10
–5
0
5
10
15
10
100
1k
10k
100k
1M
Output Voltage (V)
Frequency (Hz)
NEGATIVE POWER SUPPLY REJECTION
vs FREQUENCY
INPUT-REFERRED NOISE VOLTAGE
vs FREQUENCY
140
1k
100
10
120
100
80
60
40
20
0
G = 100
G = 1000
G = 1
G = 10
G = 1
G = 10
G = 100, 1000
G = 1000
BW Limit
1
10
100
1k
10k
100k
1M
1
10
100
1k
10k
Frequency (Hz)
Frequency (Hz)
®
4
INA114
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = ±15V, unless otherwise noted.
SETTLING TIME vs GAIN
OFFSET VOLTAGE WARM-UP vs TIME
1200
1000
800
600
400
200
0
6
4
G ≥ 100
2
0
0.01%
–2
–4
–6
0.1%
1
10
100
1000
0
15
30
45
60
75
90
105
120
Gain (V/V)
Time from Power Supply Turn-on (s)
INPUT BIAS AND INPUT OFFSET CURRENT
vs TEMPERATURE
INPUT BIAS CURRENT
vs DIFFERENTIAL INPUT VOLTAGE
2
1
3
2
1
±IB
0
0
IOS
–1
–2
–3
G = 1
–1
–2
G = 10
G = 100
G = 1000
–15
–40
–15
10
35
60
85
–45
–30
0
15
30
45
Temperature (°C)
Differential Overload Voltage (V)
INPUT BIAS CURRENT
vs COMMON-MODE INPUT VOLTAGE
MAXIMUM OUTPUT SWING vs FREQUENCY
3
32
Both Inputs
28
24
20
16
12
8
2
1
|Ib1| + |Ib2
|
G = 1, 10
G = 100
One Input
Over-Voltage
Protection
0
Over-Voltage
Protection
Normal
Operation
G = 1000
–1
–2
–3
One Input
4
Both Inputs
–30 –15
0
–45
0
15
30
45
10
100
1k
10k
100k
1M
Frequency (Hz)
Common-Mode Voltage (V)
®
5
INA114
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = ±15V, unless otherwise noted.
SLEW RATE vs TEMPERATURE
OUTPUT CURRENT LIMIT vs TEMPERATURE
1.0
0.8
0.6
0.4
0.2
0
30
25
20
15
10
+|ICL
|
–|ICL
|
–75
–50
–25
0
25
50
75
100
125
–40
–15
10
35
60
85
Temperature (°C)
Temperature (°C)
QUIESCENT CURRENT AND POWER DISSIPATION
vs POWER SUPPLY VOLTAGE
QUIESCENT CURRENT vs TEMPERATURE
2.6
2.5
2.4
2.3
2.2
2.1
2.0
120
2.8
2.6
2.4
2.2
2.0
1.8
100
80
60
40
20
0
Power Dissipation
Quiescent Current
0
±3
±6
±9
±12
±15
±18
–75
–50
–25
0
25
50
75
100
125
Power Supply Voltage (V)
Temperature (°C)
POSITIVE SIGNAL SWING vs TEMPERATUE (RL = 2kΩ)
NEGATIVE SIGNAL SWING vs TEMPERATUE (RL = 2kΩ)
16
14
12
10
8
–16
–14
–12
–10
–8
VS = ±15V
VS = ±15V
VS = ±11.4V
VS = ±11.4V
6
–6
4
–4
VS = ±2.25V
VS = ±2.25V
2
–2
0
0
–75
–50
–25
0
25
50
75
100
125
–75
–50
–25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
®
6
INA114
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = ±15V, unless otherwise noted.
LARGE SIGNAL RESPONSE, G = 1
SMALL SIGNAL RESPONSE, G = 1
+10V
0
+100mV
0
–10V
–200mV
LARGE SIGNAL RESPONSE, G = 1000
SMALL SIGNAL RESPONSE, G = 1000
+200mV
0
+10V
0
–200mV
–10V
INPUT-REFERRED NOISE, 0.1 to 10Hz
0.1µV/div
1 s/div
®
7
INA114
APPLICATION INFORMATION
Figure 1 shows the basic connections required for operation
of the INA114. Applications with noisy or high impedance
power supplies may require decoupling capacitors close to
the device pins as shown.
ues. The accuracy and temperature coefficient of these
resistors are included in the gain accuracy and drift specifi-
cations of the INA114.
The stability and temperature drift of the external gain
setting resistor, RG, also affects gain. RG’s contribution to
gain accuracy and drift can be directly inferred from the gain
equation (1). Low resistor values required for high gain can
make wiring resistance important. Sockets add to the wiring
resistance which will contribute additional gain error (possi-
bly an unstable gain error) in gains of approximately 100 or
greater.
The output is referred to the output reference (Ref) terminal
which is normally grounded. This must be a low-impedance
connection to assure good common-mode rejection. A resis-
tance of 5Ω in series with the Ref pin will cause a typical
device to degrade to approximately 80dB CMR (G = 1).
SETTING THE GAIN
Gain of the INA114 is set by connecting a single external
resistor, RG:
NOISE PERFORMANCE
The INA114 provides very low noise in most applications.
For differential source impedances less than 1kΩ, the INA103
may provide lower noise. For source impedances greater
than 50kΩ, the INA111 FET-input instrumentation ampli-
fier may provide lower noise.
50 kΩ
R G
G = 1 +
(1)
Commonly used gains and resistor values are shown in
Figure 1.
Low frequency noise of the INA114 is approximately
0.4µVp-p measured from 0.1 to 10Hz. This is approximately
one-tenth the noise of “low noise” chopper-stabilized ampli-
fiers.
The 50kΩ term in equation (1) comes from the sum of the
two internal feedback resistors. These are on-chip metal film
resistors which are laser trimmed to accurate absolute val-
V+
0.1µF
Pin numbers are
for DIP packages.
7
–
VIN
INA114
2
1
Over-Voltage
Protection
A1
VO = G • (VI+N – VI–N
)
25kΩ
25kΩ
50kΩ
RG
25kΩ
25kΩ
G = 1 +
6
5
A3
RG
+
8
3
VO
Load
–
A2
+
VIN
Over-Voltage
Protection
25kΩ
25kΩ
4
0.1µF
DESIRED
GAIN
RG
(Ω)
NEAREST 1% RG
(Ω)
Also drawn in simplified form:
V–
1
2
5
10
20
50
100
200
500
1000
2000
5000
10000
No Connection
50.00k
12.50k
5.556k
2.632k
1.02k
No Connection
49.9k
12.4k
5.62k
2.61k
1.02k
511
–
VIN
INA114
Ref
VO
RG
+
VIN
505.1
251.3
100.2
50.05
25.01
10.00
5.001
249
100
49.9
24.9
10
4.99
FIGURE 1. Basic Connections.
®
8
INA114
OFFSET TRIMMING
The INA114 is laser trimmed for very low offset voltage and
drift. Most applications require no external offset adjust-
ment. Figure 2 shows an optional circuit for trimming the
output offset voltage. The voltage applied to Ref terminal is
summed at the output. Low impedance must be maintained
at this node to assure good common-mode rejection. This is
achieved by buffering trim voltage with an op amp as
shown.
Microphone,
Hydrophone
etc.
INA114
47kΩ
47kΩ
Thermocouple
INA114
–
VIN
V+
VO
INA114
RG
100µA
+
1/2 REF200
Ref
10kΩ
VIN
100Ω
100Ω
OPA177
±10mV
Adjustment Range
10kΩ
INA114
Center-tap provides
bias current return.
100µA
1/2 REF200
V–
FIGURE 3. Providing an Input Common-Mode Current Path.
FIGURE 2. Optional Trimming of Output Offset Voltage.
A combination of common-mode and differential input
signals can cause the output of A1 or A2 to saturate. Figure
4 shows the output voltage swing of A1 and A2 expressed in
terms of a common-mode and differential input voltages.
Output swing capability of these internal amplifiers is the
same as the output amplifier, A3. For applications where
input common-mode range must be maximized, limit the
output voltage swing by connecting the INA114 in a lower
gain (see performance curve “Input Common-Mode Voltage
Range vs Output Voltage”). If necessary, add gain after the
INA114 to increase the voltage swing.
INPUT BIAS CURRENT RETURN PATH
The input impedance of the INA114 is extremely high—
approximately 1010Ω. However, a path must be provided for
the input bias current of both inputs. This input bias current
is typically less than ±1nA (it can be either polarity due to
cancellation circuitry). High input impedance means that
this input bias current changes very little with varying input
voltage.
Input circuitry must provide a path for this input bias current
if the INA114 is to operate properly. Figure 3 shows various
provisions for an input bias current path. Without a bias
current return path, the inputs will float to a potential which
exceeds the common-mode range of the INA114 and the
input amplifiers will saturate. If the differential source resis-
tance is low, bias current return path can be connected to one
input (see thermocouple example in Figure 3). With higher
source impedance, using two resistors provides a balanced
input with possible advantages of lower input offset voltage
due to bias current and better common-mode rejection.
Input-overload often produces an output voltage that appears
normal. For example, an input voltage of +20V on one input
and +40V on the other input will obviously exceed the linear
common-mode range of both input amplifiers. Since both
input amplifiers are saturated to nearly the same output
voltage limit, the difference voltage measured by the output
amplifier will be near zero. The output of the INA114 will
be near 0V even though both inputs are overloaded.
INPUT PROTECTION
The inputs of the INA114 are individually protected for
voltages up to ±40V. For example, a condition of –40V on
one input and +40V on the other input will not cause
damage. Internal circuitry on each input provides low series
impedance under normal signal conditions. To provide
equivalent protection, series input resistors would contribute
excessive noise. If the input is overloaded, the protection
circuitry limits the input current to a safe value (approxi-
mately 1.5mA). The typical performance curve “Input Bias
Current vs Common-Mode Input Voltage” shows this input
INPUT COMMON-MODE RANGE
The linear common-mode range of the input op amps of the
INA114 is approximately ±13.75V (or 1.25V from the
power supplies). As the output voltage increases, however,
the linear input range will be limited by the output voltage
swing of the input amplifiers, A1 and A2. The common-
mode range is related to the output voltage of the complete
amplifier—see performance curve “Input Common-Mode
Range vs Output Voltage.”
®
9
INA114
current limit behavior. The inputs are protected even if no
power supply voltage is present.
The output sense connection can be used to sense the output
voltage directly at the load for best accuracy. Figure 5 shows
how to drive a load through series interconnection resis-
tance. Remotely located feedback paths may cause instabil-
ity. This can be generally be eliminated with a high
frequency feedback path through C1. Heavy loads or long
lines can be driven by connecting a buffer inside the feed-
back path (Figure 6).
OUTPUT VOLTAGE SENSE (SOL-16 package only)
The surface-mount version of the INA114 has a separate
output sense feedback connection (pin 12). Pin 12 must be
connected to the output terminal (pin 11) for proper opera-
tion. (This connection is made internally on the DIP version
of the INA114.)
V+
G • VD
2
VCM
–
INA114
Over-Voltage
Protection
A1
25kΩ
25kΩ
VD
50kΩ
RG
G = 1 +
2
25kΩ
25kΩ
A3
V
O = G • VD
RG
VD
2
A2
Over-Voltage
Protection
25kΩ
25kΩ
VCM
G • VD
2
VCM
+
V–
FIGURE 4. Voltage Swing of A1 and A2.
Surface-mount package
version only.
Surface-mount package
version only.
Output
Sense
VI–N
VI–N
C1
1000pF
Output
Sense
OPA633
RG
IL: ±100mA
RL
INA114
RG
INA114
180Ω
VI+N
Ref
Ref
VI+N
Load
Equal resistance here preserves
good common-mode rejection.
FIGURE 5. Remote Load and Ground Sensing.
FIGURE 6. Buffered Output for Heavy Loads.
VI–N
VI+N
VO
22.1kΩ
22.1kΩ
511Ω
INA114
Ref
Shield is driven at the
common-mode potential.
100Ω
For G = 100
RG = 511Ω // 2(22.1kΩ)
effective RG = 505Ω
OPA602
FIGURE 7. Shield Driver Circuit.
®
10
INA114
V+
V+
REF200
100µA
Equal line resistance here creates
a small common-mode voltage
which is rejected by INA114.
1
VO
RTD
RG
INA114
Ref
2
RZ
3
VO = 0V at RRTD = RZ
Resistance in this line causes
a small common-mode voltage
which is rejected by INA114.
FIGURE 8. RTD Temperature Measurement Circuit.
V+
2
10.0V
6
REF102
R1
R4
27kΩ
80.6kΩ
4
R(72)
1N4148
R2
(1)
1MΩ
5.23k
Ω
VO
Cu
Cu
INA114
Ref
K
R5
R3
50Ω
100Ω
R6
100Ω
Zero Adj
SEEBECK
ISA
COEFFICIENT
R2
R4
TYPE
MATERIAL
(µV/°C)
(R3 = 100Ω)
(R5 + R6 = 100Ω)
E
J
Chromel
Constantan
58.5
50.2
39.4
38.0
3.48kΩ
56.2kΩ
Iron
Constantan
4.12kΩ
5.23kΩ
5.49kΩ
64.9kΩ
80.6kΩ
84.5kΩ
K
T
Chromel
Alumel
Copper
Constantan
NOTES: (1) –2.1mV/°C at 200µA. (2) R7 provides down-scale burn-out indication.
FIGURE 9. Thermocouple Amplifier With Cold Junction Compensation.
®
11
INA114
2.8kΩ
VO
LA
RG/2
INA114
Ref
RA
2.8kΩ
G = 10
390kΩ
1/2
OPA2604
1/2
OPA2604
10kΩ
RL
390kΩ
FIGURE 10. ECG Amplifier With Right-Leg Drive.
–
VO
+10V
VIN
+
RG
INA114
Ref
R1
1MΩ
C1
0.1µF
G = 500
Bridge
VO
RG
100Ω
INA114
Ref
1
f–3dB
=
2πR1C1
OPA602
= 1.59Hz
FIGURE 11. Bridge Transducer Amplifier.
FIGURE 12. AC-Coupled Instrumentation Amplifier.
VIN
R
–
R1
IO
=
• G
VIN
+
RG
INA114
Ref
IB
A1
IO
Load
A1
IB Error
OPA177
OPA602
OPA128
±1.5nA
1pA
75fA
FIGURE 13. Differential Voltage-to-Current Converter.
®
12
INA114
PACKAGE OPTION ADDENDUM
www.ti.com
16-Feb-2009
PACKAGING INFORMATION
Orderable Device
INA114AP
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
PDIP
P
8
50 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
INA114APG4
INA114AU
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
P
8
50 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
DW
DW
DW
DW
DW
P
16
16
16
16
16
8
40 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
INA114AU/1K
INA114AU/1KE4
INA114AUE4
INA114AUG4
INA114BP
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
50 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
INA114BPG4
INA114BU
P
8
50 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
DW
DW
DW
DW
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
INA114BU/1K
INA114BU/1KE4
INA114BUE4
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Feb-2009
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
INA114AU/1K
INA114BU/1K
SOIC
SOIC
DW
DW
16
16
1000
1000
330.0
330.0
16.4
16.4
10.85
10.85
10.8
10.8
2.7
2.7
12.0
12.0
16.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
INA114AU/1K
INA114BU/1K
SOIC
SOIC
DW
DW
16
16
1000
1000
346.0
346.0
346.0
346.0
33.0
33.0
Pack Materials-Page 2
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