INA115AU [TI]
Precision INSTRUMENTATION AMPLIFIER;
| 型号： | INA115AU |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Precision INSTRUMENTATION AMPLIFIER 放大器 光电二极管 |
| 文件： | 总16页 (文件大小：736K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
INA115
INA115
Precision
INSTRUMENTATION AMPLIFIER
FEATURES
DESCRIPTION
● LOW OFFSET VOLTAGE: 50µV max
The INA115 is a low cost, general purpose instrumen-
tation amplifier offering excellent accuracy. Its versa-
tile three-op amp design and small size make it ideal
for a wide range of applications. Similar to the model
INA114, the INA115 provides additional connections
to the input op amps, A1 and A2, which improve gain
accuracy in high gains and are useful in forming
switched-gain amplifiers.
● LOW DRIFT: 0.25µV/°C max
● LOW INPUT BIAS CURRENT: 2nA max
● HIGH COMMON-MODE REJECTION:
115dB min
● INPUT OVER-VOLTAGE PROTECTION:
±40V
● WIDE SUPPLY RANGE: ±2.25 TO ±18V
● LOW QUIESCENT CURRENT: 3mA max
● SOL-16 SURFACE-MOUNT PACKAGE
A single external resistor sets any gain from 1 to
10,000. Internal input protection can withstand up to
±40V without damage.
The INA115 is laser trimmed for very low offset
voltage (50µV), drift (0.25µV/˚C) and high common-
mode rejection (115dB at G=1000). It operates with
power supplies as low as ±2.25V, allowing use in
battery operated and single 5V supply systems. Quies-
cent current is 3mA maximum.
APPLICATIONS
● SWITCHED-GAIN AMPLIFIER
● BRIDGE AMPLIFIER
● THERMOCOUPLE AMPLIFIER
● RTD SENSOR AMPLIFIER
● MEDICAL INSTRUMENTATION
● DATA ACQUISITION
The INA115 is available in the SOL-16 surface-mount
package, specified for the –40°C to +85°C tempera-
ture range.
VO1
1
V+
13
–
VIN
INA115
4
Over-Voltage
Protection
Feedback
A1
2
3
12
25kΩ
25kΩ
25kΩ
25kΩ
A3
VO
RG
11
10
14
15
50kΩ
RG
G = 1 +
A2
Ref
+
VIN
5
Over-Voltage
Protection
25kΩ
25kΩ
8
7
VO2
V–
International Airport Industrial Park
•
Mailing Address: PO Box 11400, Tucson, AZ 85734
FAXLine: (800) 548-6133 (US/Canada Only)
•
Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706
•
Tel: (520) 746-1111
•
Twx: 910-952-1111
Internet: http://www.burr-brown.com/
•
•
Cable: BBRCORP
•
Telex: 066-6491
•
FAX: (520) 889-1510
•
Immediate Product Info: (800) 548-6132
©1992 Burr-Brown Corporation
PDS-1169B
Printed in U.S.A. October, 1993
SBOS021
SPECIFICATIONS
ELECTRICAL
At TA = +25°C, VS = ±15V, RL = 2kΩ unless otherwise noted.
INA115BU
TYP
INA115AU
TYP
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
INPUT
Offset Voltage, RTI
Initial
vs Temperature
TA = +25°C
TA = TMIN to TMAX
VS = ±2.25V to ±18V
±10 + 20/G ±50 + 100/G
±0.1 + 0.5/G ±0.25 + 5/G
±25 + 30/G ±125 + 500/G
µV
µV/°C
µV/V
µV/mo
Ω || pF
Ω || pF
V
±0.25 + 5/G
±1 + 10/G
vs Power Supply
Long-Term Stability
Impedance, Differential
Common-Mode
Input Common-Mode Range
Safe Input Voltage
Common-Mode Rejection
0.5 + 2/G
±0.2 + 0.5/G
1010 || 6
3 + 10/G
✻
✻
✻
✻
✻
✻
1010 || 6
±11
±13.5
✻
±40
✻
V
VCM = ±10V, ∆RS = 1kΩ
G = 1
80
96
110
96
75
90
106
90
dB
dB
dB
dB
G = 10
G = 100
G = 1000
115
120
120
106
110
110
115
106
BIAS CURRENT
vs Temperature
±0.5
±8
±2
±2
✻
✻
±5
±5
nA
pA/°C
OFFSET CURRENT
vs Temperature
±0.5
±8
✻
✻
nA
pA/°C
NOISE VOLTAGE, RTI
f = 10Hz
f = 100Hz
G = 1000, RS = 0Ω
15
11
11
0.4
✻
✻
✻
✻
nV/√Hz
nV/√Hz
nV/√Hz
µVp-p
f = 1kHz
fB = 0.1Hz to 10Hz
Noise Current
f=10Hz
f=1kHz
fB = 0.1Hz to 10Hz
0.4
0.2
18
✻
✻
✻
pA/√Hz
pA/√Hz
pAp-p
GAIN
Gain Equation
Range of Gain
Gain Error
1 + (50kΩ/RG)
✻
V/V
V/V
%
%
%
1
10000
±0.05
±0.4
±0.5
±1
✻
✻
✻
±0.5
±0.7
±2
±10
✻
±0.002
±0.004
±0.004
±0.02
G = 1
G = 10
G = 100
G = 1000
G = 1
±0.01
±0.02
±0.05
±0.5
±2
±25
±0.0001
±0.0005
±0.0005
±0.002
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
%
Gain vs Temperature
50kΩ Resistance(1)
Nonlinearity
±10
ppm/°C
ppm/°C
% of FSR
% of FSR
% of FSR
% of FSR
±100
±0.001
±0.002
±0.002
±0.01
G = 1
G = 10
G = 100
G = 1000
OUTPUT(2)
Voltage
IO = 5mA, TMIN to TMAX
VS = ±11.4V, RL = 2kΩ
VS = ±2.25V, RL = 2kΩ
±13.5
±10
±1
±13.7
±10.5
±1.5
1000
+20/–15
✻
✻
✻
✻
✻
✻
✻
✻
V
V
V
pF
mA
Load Capacitance Stability
Short Circuit Current
FREQUENCY RESPONSE
Bandwidth, –3dB
G = 1
G = 10
G = 100
1
100
10
1
0.6
18
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
MHz
kHz
kHz
kHz
V/µs
µs
µs
µs
µs
µs
G = 1000
VO = ±10V, G = 10
G = 1
G = 10
G = 100
G = 1000
50% Overdrive
Slew Rate
Settling Time, 0.01%
0.3
✻
✻
20
120
1100
20
Overload Recovery
POWER SUPPLY
Voltage Range
Current
±2.25
±15
±2.2
±18
±3
✻
✻
✻
✻
V
mA
VIN = 0V
TEMPERATURE RANGE
Specification
Operating
–40
–40
+85
+125
✻
✻
✻
✻
°C
°C
θJA
80
✻
°C/W
✻ Specification same as INA115BU.
NOTE: (1) Temperature coefficient of the “50kΩ” term in the gain equation. (2) Output specifications are for output amplifier, A3. A1 and A2 provide the same output
voltage swing but have less output current drive. A1 and A2 can drive external loads of 25kΩ || 200pF.
®
2
INA115
PIN CONFIGURATIONS
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with ap-
propriate precautions. Failure to observe proper handling and
installation procedures can cause damage.
U Package
SOL-16 Surface-Mount
Top View
VO1
Gain Sense1
RG
1
2
3
4
5
6
7
8
16 NC
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
15 Gain Sense2
14 RG
V–
13 V+
IN
V+
12 Feedback
11 VO
IN
NC
V–
ABSOLUTE MAXIMUM RATINGS
10 Ref
Supply Voltage .................................................................................. ±18V
Input Voltage Range.......................................................................... ±40V
Output Short-Circuit (to ground) .............................................. Continuous
Operating Temperature ................................................. –40°C to +125°C
Storage Temperature..................................................... –40°C to +125°C
Junction Temperature .................................................................... +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
VO2
9
NC
PACKAGE/ORDERING INFORMATION
PACKAGE
DRAWING TEMPERATURE
PRODUCT
PACKAGE
NUMBER(1)
RANGE
INA115AU
INA115BU
SOL-16 Surface-Mount
SOL-16 Surface-Mount
211
211
–40°C to +85°C
–40°C to +85°C
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
INA115
3
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VS = ±15V, unless otherwise noted.
GAIN vs FREQUENCY
COMMON-MODE REJECTION vs FREQUENCY
G = 100, 1k
G = 10
140
120
100
80
1k
100
10
G = 1k
G = 100
60
G = 10
G = 1
40
1
VO1 connected to Gain Sense1 and
20
VO2 connected to Gain Sense2 . See text.
0
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
Frequency (Hz)
Frequency (Hz)
INPUT COMMON-MODE VOLTAGE RANGE
vs OUTPUT VOLTAGE
POSITIVE POWER SUPPLY REJECTION
vs FREQUENCY
15
140
120
100
80
10
5
–
VD/2
VO
+
–
G = 1000
VD/2
+
G = 100
G = 10
VCM
0
(Any Gain)
60
A3 – Output
Swing Limit
A3 + Output
Swing Limit
–5
–10
–15
G = 1
40
20
0
–15
–10
–5
0
5
10
15
10
100
1k
10k
100k
1M
Output Voltage (V)
Frequency (Hz)
INPUT- REFERRED NOISE VOLTAGE
vs FREQUENCY
NEGATIVE POWER SUPPLY REJECTION
vs FREQUENCY
1k
100
10
140
120
100
80
G = 100
G = 1000
G = 1
G = 10
G = 1
G = 10
60
G = 100, 1000
40
G = 1000
BW Limit
20
1
0
1
10
100
1k
10k
10
100
1k
10k
100k
1M
Frequency (Hz)
Frequency (Hz)
®
4
INA115
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = ±15V, unless otherwise noted.
SETTLING TIME vs GAIN
OFFSET VOLTAGE WARM-UP vs TIME
1200
1000
800
600
400
200
0
6
4
>
G
100
2
0
0.01%
–2
–4
–6
0.1%
1
10
100
1000
0
15
30
45
60
75
90
105
120
Gain (V/V)
Time from Power Supply Turn-on (s)
INPUT BIAS AND INPUT OFFSET CURRENT
vs TEMPERATURE
INPUT BIAS CURRENT
vs DIFFERENTIAL INPUT VOLTAGE
2
1
3
2
1
±IB
0
0
IOS
–1
–2
–3
G = 1
–1
–2
G = 10
G = 100
G = 1000
–15
–40
–15
10
35
60
85
–45
–30
0
15
30
45
Temperature (°C)
Differential Overload Voltage (V)
INPUT BIAS CURRENT
vs COMMON-MODE INPUT VOLTAGE
MAXIMUM OUTPUT SWING vs FREQUENCY
3
2
32
Both Inputs
28
24
20
16
12
8
|Ib1| + |Ib2
|
G = 1, 10
G = 100
One Input
1
Over-Voltage
Protection
0
Over-Voltage
Protection
Normal
Operation
G = 1000
–1
–2
–3
One Input
4
Both Inputs
–30 –15
0
–45
0
15
30
45
10
100
1k
10k
100k
1M
Common-Mode Voltage (V)
Frequency (Hz)
®
INA115
5
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = ±15V, unless otherwise noted.
SLEW RATE vs TEMPERATURE
OUTPUT CURRENT LIMIT vs TEMPERATURE
1.0
0.8
0.6
0.4
0.2
0
30
25
20
15
10
+|ICL
|
–|ICL
|
–75
–50
–25
0
25
50
75
100
125
125
125
–40
–15
10
35
60
85
Temperature (°C)
Temperature (°C)
QUIESCENT CURRENT AND POWER DISSIPATION
vs POWER SUPPLY VOLTAGE
QUIESCENT CURRENT vs TEMPERATURE
2.8
2.6
2.4
2.2
2.0
1.8
2.6
2.5
2.4
2.3
2.2
2.1
2.0
120
100
80
60
40
20
0
Power Dissipation
Quiescent Current
–75
–50
–25
0
25
50
75
100
0
±3
±6
±9
±12
±15
±18
Temperature (°C)
Power Supply Voltage (V)
POSITIVE SIGNAL SWING
vs TEMPERATURE (RL = 2kΩ)
NEGATIVE SIGNAL SWING
vs TEMPERATURE (RL = 2kΩ)
16
14
12
10
8
–16
–14
–12
–10
–8
VS = ±15V
VS = ±15V
VS = ±11.4V
VS = ±11.4V
6
–6
4
–4
VS = ±2.25V
VS = ±2.25V
2
–2
0
–75
0
–75
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
®
6
INA115
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = ±15V, unless otherwise noted.
LARGE SIGNAL RESPONSE, G = 1
SMALL SIGNAL RESPONSE, G = 1
+10V
0
+100mV
0
–10V
–200mV
VO1 connected to Gain Sense1 and
VO2 connected to Gain Sense2
LARGE SIGNAL RESPONSE, G = 1000
SMALL SIGNAL RESPONSE, G = 1000
+200mV
0
+10V
0
–10V
+200mV
INPUT-REFERRED NOISE, 0.1 to 10Hz
0.1µV/div
1 s/div
®
INA115
7
APPLICATION INFORMATION
Figure1showsthebasicconnectionsrequiredforoperationof
the INA115. Applications with noisy or high impedance
powersuppliesmayrequiredecouplingcapacitorsclosetothe
device pins as shown.
Commonly used gains and resistor values are shown in
Figure 1.
For G=1, no resistor is required, but connect pins 2-3 and
connect pins 14-15. Gain peaking in G=1 can be reduced by
shorting the internal 25kΩ feedback resistors (see typical
performance curve Gain vs Frequency). To do this, connect
pins 1-2-3 and connect pins 8-14-15.
The output is referred to the output reference (Ref) terminal
which is normally grounded. This must be a low-impedance
connection to assure good common-mode rejection. A resis-
tance of 5Ω in series with the Ref pin will cause a typical
device to degrade to approximately 80dB CMR (G=1).
The 50kΩ term in equation 1 comes from the sum of the two
internal feedback resistors. These are on-chip metal film
resistors which are laser trimmed to accurate absolute values.
The accuracy and temperature coefficient of these resistors
areincludedinthegainaccuracyanddriftspecificationsofthe
INA115.
The INA115 has a separate output sense feedback connection
(pin 12). Pin 12 must be connected (normally to the output
terminal, pin 11) for proper operation. The output sense
connection can be used to sense the output voltage directly at
the load for best accuracy.
The stability and temperature drift of the external gain setting
resistor, RG, also affects gain. RG’s contribution to gain error
and drift can be directly inferred from the gain equation (1).
Low resistor values required for high gain can make wiring
resistance important. The “force and sense” type connections
illustratedinFigure1helpreducetheeffectofinterconnection
resistance.
SETTING THE GAIN
Gain of the INA115 is set by connecting a single external
resistor, RG:
50 kΩ
R G
G = 1 +
(1)
V+
0.1µF
VO1
1
13
–
VIN
INA115
4
Over-Voltage
Protection
A1
2
3
12
11
10
VO = G • (VIN – VIN
)
25kΩ
25kΩ
25kΩ
25kΩ
50kΩ
RG
G = 1 +
A3
RG
+
14
15
VO
Load
–
A2
+
VIN
5
Over-Voltage
Protection
25kΩ
25kΩ
8
7
0.1µF
VO2
DESIRED
GAIN
RG
(Ω)
NEAREST 1% RG
(Ω)
Also drawn in simplified form:
VO1
1
2
5
10
20
50
100
200
500
1000
2000
5000
10000
No Connection
50.00k
12.50k
5.556k
2.632k
1.02k
No Connection
49.9k
12.4k
5.62k
2.61k
1.02k
511
V–
–
VIN
INA115
VO
RG
505.1
251.3
100.2
50.05
25.01
10.00
5.001
249
100
49.9
24.9
10
4.99
Ref
+
VIN
VO2
FIGURE 1. Basic Connections.
®
8
INA115
SWITCHED GAIN
OFFSET TRIMMING
Figure 2 shows a circuit for digital selection of four gains.
Multiplexer “on” resistance does not significantly affect gain.
The resistor values required for some commonly used gain
steps are shown. This circuit uses the internal 25kΩ feedback
resistors, so the resistor values shown cannot be scaled to a
different impedance level.
The INA115 is laser trimmed for very low offset voltage and
drift. Most applications require no external offset adjustment.
Figure 4 shows an optional circuit for trimming the output
offset voltage. The voltage applied to Ref terminal is summed
at the output. Low impedance must be maintained at this node
to assure good common-mode rejection. This is achieved by
buffering the trim voltage with an op amp as shown.
Figure 3 shows an alternative switchable gain configuration.
This circuit does not use the internal 25kΩ feedback resistors,
sothenominalvaluesshowncanbescaledtootherimpedance
levels. This circuit is ideal for use with a precision resistor
network to achieve excellent gain accuracy and lowest gain
drift.
INPUT BIAS CURRENT RETURN PATH
The input impedance of the INA115 is extremely high—
approximately 1010Ω. However, a path must be provided for
the input bias current of both inputs. This input bias current is
typically less than ±1nA (it can be either polarity due to
cancellation circuitry). High input impedance means that this
input bias current changes very little with varying input
voltage.
NOISE PERFORMANCE
TheINA115providesverylownoiseinmostapplications.For
differential source impedances less than 1kΩ, the INA103
may provide lower noise. For source impedances greater than
50kΩ,theINA111FET-InputInstrumentationAmplifiermay
provide lower noise.
Input circuitry must provide a path for this input bias current
if the INA115 is to operate properly. Figure 5 shows various
provisions for an input bias current path. Without a bias
current return path, the inputs will float to a potential which
exceedsthecommon-moderangeoftheINA115andtheinput
amplifiers will saturate. If the differential source resistance is
low, a bias current return path can be connected to one input
(see thermocouple example in Figure 5). With higher source
impedance, usingtworesistorsprovidesabalancedinputwith
possible advantages of lower input offset voltage due bias
current and better common-mode rejection.
Low frequency noise of the INA115 is approximately
0.4µVp-p measured from 0.1 to 10Hz. This is approximately
one-tenth the noise of “low noise” chopper-stabilized ampli-
fiers.
–
VIN
+15V
9
13
12
14
1
INA115
4
Over-Voltage
R1
R2
Feedback
12
Protection
11
10
A1
2
1
2
3
25kΩ
25kΩ
Enable
A0
25kΩ
25kΩ
A3
VO
7
6
11
10
R3
R4
16
15
14
15
A1
A2
5
Over-Voltage
Protection
5
4
25kΩ
25kΩ
3
8
HI-509
8
+
VIN
A0
A1
Gain
R1
(Ω)
R2
(Ω)
R3
(Ω)
R4
(Ω)
–15V
GAIN STEPS
L
H
L
L
L
H
H
1
1, 10, 100, 1000
1, 2, 4, 8
1, 2, 5, 10
2.5k
12.5k
15k
55.6
12.5k
10k
500
12.5k
10k
2.5k
12.5k
15k
H
Highest
0, +3, +6, +9dB
17.7k
60.3k
25k
17.7k
FIGURE 2. Switched-Gain Instrumentation Amplifier (minimum components).
9
®
INA115
–
VIN
+15V
9
13
12
14
R1
R2
R3
R4
R5
1
13
INA115
4
Over-Voltage
Protection
Feedback
12
11
10
7
A1
2
1
2
3
25kΩ
25kΩ
Enable
A0
25kΩ
25kΩ
NC
NC
A3
VO
11
10
16
15
14
15
A1
6
A2
R6
R7
5
Over-Voltage
Protection
5
4
25kΩ
25kΩ
3
8
7
HI-509
8
+
VIN
–15V
R1
R2
R3
R4
R5
R6
R7
A0
A1
Gain
GAIN STEPS
(Ω)
(Ω)
(Ω)
(Ω)
(Ω)
(Ω)
(Ω)
L
H
L
L
L
H
H
1
1, 10, 100, 1000V/V
1, 2, 4, 8V/V
1, 2, 5, 10V/V
18k
18k
18k
18k
1.8k
9k
10.8k
180
4.5k
3.6k
9.02k
40
9k
7.2k
43.7k
180
4.5k
3.6k
9.02k
1.8k
9k
10.8k
18k
18k
18k
18k
H
Highest
0, +3, +6, +9dB
12.74k
12.74k
FIGURE 3. Switched-Gain Instrumentation Amplifier (improved gain drift).
–
VIN
VO
V+
Microphone,
INA115
INA115
RG
Hydrophone
etc.
100µA
1/2 REF200
+
Ref
VIN
47kΩ
47kΩ
100Ω
100Ω
OPA177
±10mV
Adjustment Range
10kΩ
Thermocouple
INA115
100µA
1/2 REF200
V–
10kΩ
FIGURE 4. Optional Trimming of Output Offset Voltage.
INA115
Center-tap provides
bias current return.
FIGURE 5. Providing an Input Common-Mode Current Path.
®
10
INA115
INPUT COMMON-MODE RANGE
common-mode range of both input amplifiers. Since both
input amplifiers are saturated to the nearly the same output
voltage limit, the difference voltage measured by the output
amplifier will be near zero. The output of the INA115 will be
near 0V even though both inputs are overloaded.
The linear common-mode range of the input op amps of the
INA115 is approximately ±13.75V (or 1.25V from the power
supplies). As the output voltage increases, however, the linear
input range will be limited by the output voltage swing of the
input amplifiers, A1 and A2. The common-mode range is
related to the output voltage of the complete amplifier—see
performance curve “Input Common-Mode Range vs Output
Voltage.”
INPUT PROTECTION
The inputs of the INA115 are individually protected for
voltagesupto ±40V. Forexample, aconditionof–40Vonone
input and +40V on the other input will not cause damage.
Internalcircuitryoneachinputprovideslowseriesimpedance
undernormalsignalconditions.Toprovideequivalentprotec-
tion, seriesinputresistorswouldcontributeexcessivenoise. If
theinputisoverloaded,theprotectioncircuitrylimitstheinput
current to a safe value (approximately 1.5mA). The typical
performance curve “Input Bias Current vs Common-Mode
Input Voltage” shows this input current limit behavior. The
inputs are protected even if the power supply voltage is zero.
A combination of common-mode and differential input sig-
nals can cause the output of A1 or A2 to saturate. Figure 6
shows the output voltage swing of A1 and A2 expressed in
terms of a common-mode and differential input voltages.
Output swing capability of the input amplifiers, A1 and A2 is
the same as the output amplifier, A3. For applications where
input common-mode range must be maximized, limit the
output voltage swing by connecting the INA115 in a lower
gain (see performance curve “Input Common-Mode Voltage
Range vs Output Voltage”). If necessary, add gain after the
INA115 to increase the voltage swing.
OTHER APPLICATIONS
Input-overload often produces an output voltage that appears
normal. For example, an input voltage of +20V on one input
and +40V on the other input will obviously exceed the linear
See the INA114 data sheet for other applications circuits of
general interest.
V+
G • VD
VCM
–
2
INA115
Over-Voltage
Protection
A1
25kΩ
25kΩ
VD
50kΩ
RG
G = 1 +
25kΩ
25kΩ
2
A3
VO = G • VD
RG
VD
2
A2
Over-Voltage
Protection
25kΩ
25kΩ
VCM
G • VD
2
VCM
+
V–
FIGURE 6. Voltage Swing of A1 and A2.
VO1
INA115
VO
LA
RG
RA
VO2
390kΩ
24.9kΩ
RL
OPA177
24.9kΩ
390kΩ
FIGURE 7. ECG Amplifier with Right Leg Drive.
®
INA115
11
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
INA115AU
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SOIC
SOIC
SOIC
SOIC
DW
16
16
16
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
INA115AU
INA115AU/1K
INA115BU
ACTIVE
ACTIVE
ACTIVE
DW
DW
DW
1000
40
Green (RoHS
& no Sb/Br)
INA115AU
INA115BU
INA115BU
Green (RoHS
& no Sb/Br)
INA115BUG4
40
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
INA115AU/1K
SOIC
DW
16
1000
330.0
16.4
10.75 10.7
2.7
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC DW 16
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 38.0
INA115AU/1K
1000
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
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TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
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endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
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