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INA188

ZHCSE92 –SEPTEMBER 2015

INA188

精密零漂移、轨到轨输出、高压仪表放大器

1 特性

3 说明

1

•

出色的直流性能：

INA188 是一款精密的仪表放大器，其采用德州仪器

(TI) 专有的自动归零技术，可实现低偏移电压、近零偏

移和增益漂移、出色的线性度以及向下扩展至直流的超

低噪声密度 (12nV/√Hz)。

–

低输入偏移电压：55μV（最大值）

低输入偏移漂移：0.2μV/°C（最大值）

高共模抑制比 (CMRR)：104dB，增益 ≥ 10

（最小值）

INA188 经优化可提供超过 104dB 的出色共模抑制比

(G ≥ 10)。出色的共模和电源抑制性能可为高分辨率

的精密测量应用提供支持。这种通用型三运放设计可

提供轨到轨输出、由 4V 单电源或高达 ±18V 的双电源

供电的低电压运行以及一个高阻抗的宽输入范围。这

些规范值使得该器件成为通用信号测量和传感器调节应

用（如温度或桥式应用）的理想选择。

•

低输入噪声：

–

1kHz 时为 12nV/√Hz

0.25 μV_PP（0.1Hz 至 10Hz）

宽电源范围：

–

单电源：4V 至 36V

双电源：±2V 至 ±18V

通过单个外部电阻设置增益：

可通过单个外部电阻在 1 到 1000 范围内设置增益。

INA188 设计为采用符合行业标准的增益公式： G = 1

+ (50kΩ / R_G)。基准引脚可用于单电源运行过程中的

电平转换或者用于偏移校准。

–

增益公式：G = 1 + (50kΩ / R_G)

增益误差：0.007%，G = 1

增益漂移：5ppm/°C（最大值），G = 1

•

输入电压：(V–) + 0.1V 至 (V+) – 1.5V

已过滤射频干扰 (RFI) 的输入

轨到轨输出

INA188 的额定运行温度范围为 -40°C 至 +125°C。

器件信息

低静态电流：1.4mA

订货编号

INA188

封装

SOIC (8)

WSON (8)⁽²⁾

封装尺寸

工作温度范围：-55°C 至 +150°C

4.90mm x 3.91mm

4.00mm x 4.00mm

小外形尺寸集成电路 (SOIC)-8 和双边扁平无引线

(DFN)-8 封装

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

(2) DRJ 封装 (WSON-8) 是一款预览器件。

2 应用范围

•

桥式放大器

简化电路原理图

心电图 (ECG) 放大器

V+

压力传感器

RFI Filter Inputs

20 kꢀ

V_IN-

+

医疗仪表

A₁

RFI Filtered Inputs

便携式仪表

25 kꢀ

衡器

A₃

V_OUT

热电偶放大器

R_G

25 kꢀ

+

电阻式温度检测器 (RTD) 传感器放大器

数据采集

20 kꢀ

RFI Filtered Inputs

A₂

REF

RFI Filtered Inputs

V_IN+

+

V-

50 kW

R_G

G =1+

V_OUT= V_IN+- V

ìG+ V

REF

(

)

IN-

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION

DATA.

English Data Sheet: SBOS632

INA188

ZHCSE92 –SEPTEMBER 2015

www.ti.com.cn

7.3 Feature Description................................................. 18

7.4 Device Functional Modes........................................ 21

Application and Implementation ........................ 27

8.1 Application Information............................................ 27

8.2 Typical Application .................................................. 27

Power Supply Recommendations...................... 29

1

2

3

4

5

6

特性.......................................................................... 1

应用范围................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

8

9

10 Layout................................................................... 29

10.1 Layout Guidelines ................................................. 29

10.2 Layout Example .................................................... 30

11 器件和文档支持 ..................................................... 31

11.1 器件支持 ............................................................... 31

11.2 文档支持................................................................ 31

11.3 社区资源................................................................ 31

11.4 商标....................................................................... 31

11.5 静电放电警告......................................................... 31

11.6 Glossary................................................................ 31

12 机械、封装和可订购信息....................................... 32

6.5 Electrical Characteristics: V_S= ±4 V to ±18 V (V_S

8 V to 36 V)................................................................ 5

6.6 Electrical Characteristics: V_S= ±2 V to < ±4 V (V_S

=

4 V to < 8 V)............................................................... 7

6.7 Typical Characteristics.............................................. 9

Detailed Description ............................................ 17

7.1 Overview ................................................................. 17

7.2 Functional Block Diagram ....................................... 17

7

4 修订历史记录

日期

修订版本

注释

2015 年 9 月

*

最初发布。

2

INA188

www.ti.com.cn

ZHCSE92 –SEPTEMBER 2015

5 Pin Configuration and Functions

D Package

SOIC-8

Top View

DRJ Package

WSON-8

Top View

RG

8

7

6

RG

VIN-

VIN+

V-

1

2

3

1

8

7

6

RG

VIN-

VIN+

V-

RG

V+

Exposed

Thermal

Die Pad on

Underside

2

3

4

V+

VOUT

REF

4

5

REF

Pin Functions

I/O

DESCRIPTION

NO.

NAME

REF

RG

5

1, 8

4

I

Reference input. This pin must be driven by low impedance or connected to ground.

—

I

Gain setting pin. For gains greater than 1, place a gain resistor between pin 1 and pin 8.

V–

Negative supply

Positive supply

Negative input

Positive input

Output

V+

7

VIN–

VIN+

2

3

I

VOUT

6

O

3

INA188

ZHCSE92 –SEPTEMBER 2015

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

±20

UNIT

Supply

V

40 (single supply)

±10

Voltage

Current

Analog input range⁽²⁾

mA

V

(V–) – 0.5

–55

(V+) + 0.5

Output short-circuit⁽³⁾

Continuous

Operating range, T_A

150

Temperature

Junction, T_J

°C

Storage temperature, T_stg

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.3 V beyond the supply rails must be

current limited to 10 mA or less.

(3) Short-circuit to ground.

6.2 ESD Ratings

VALUE

±2500

±1000

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

4 (±2)

-40

NOM

MAX

UNIT

V_S

Supply voltage

36 (±18)

125

V

Specified temperature

°C

6.4 Thermal Information

INA188

THERMAL METRIC⁽¹⁾

D (SOIC)

8 PINS

125

DRG (WSON)

UNIT

8 PINS

145

75

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

80

68

39

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

32

14

ψ_JB

68

105

N/A

R_θJC(bot)

N/A

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

4

INA188

www.ti.com.cn

ZHCSE92 –SEPTEMBER 2015

6.5 Electrical Characteristics: V_S= ±4 V to ±18 V (V_S= 8 V to 36 V)

At T_A= 25°C, R_L= 10 kΩ, V_REF= V_S/ 2, and G = 1, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT⁽¹⁾

At RTI⁽²⁾

±25

±0.08

±60

±55

±0.2

μV

μV/°C

μV

V_OSI

Input stage offset voltage

Output stage offset voltage

Offset voltage

At RTI, T_A= –40°C to +125°C

At RTI

±170

±0.35

V_OSO

At RTI, T_A= –40°C to +125°C

At RTI

±0.2

μV/°C

μV

±25 ±60 / G ±55 ±170 / G

±0.2 ±0.35 / G

V_OS

At RTI, T_A= –40°C to +125°C

G = 1, V_S= 4 V to 36 V, V_CM= V_S/ 2

G = 10, V_S= 4 V to 36 V, V_CM= V_S/ 2

G = 100, V_S= 4 V to 36 V, V_CM= V_S/ 2

G = 1000, V_S= 4 V to 36 V, V_CM= V_S/ 2

μV/°C

±0.7

±0.6

±0.45

±0.3

1⁽³⁾

±2.25

PSRR

Power-supply rejection ratio

µV/V

µV

±0.8

Long-term stability

Turn-on time to specified V_OSI

Differential input impedance

Common-mode input impedance

See the Typical Characteristics

z_id

z_ic

100 || 6

GΩ || pF

100 || 9.5

The input signal common-mode range can be

calculated with this tool

V_CM

Common-mode voltage range

(V–) + 0.1

84

(V+) – 1.5

V

G = 1, at dc to 60 Hz, V_CM= (V–) + 1.0 V to

(V+) – 2.5 V

90

110

130

G = 10, at dc to 60 Hz, V_CM= (V–) + 1.0 V to

(V+) – 2.5 V

104

CMRR

Common-mode rejection ratio

dB

G = 100, at dc to 60 Hz, V_CM= (V–) + 1.0 V to

(V+) – 2.5 V

118

G = 1000, at dc to 60 Hz, V_CM= (V–) + 1.0 V to

(V+) – 2.5 V

118

INPUT BIAS CURRENT

±850

See Figure 10

±850

±2500

pA

pA/°C

pA

I_IB

Input bias current

T_A= –40°C to +125°C

I_OS

Input offset current

See Figure 11

pA/°C

INPUT VOLTAGE NOISE

f = 1 kHz, G = 100, R_S= 0 Ω

f = 0.1 Hz to 10 Hz, G = 100, R_S= 0 Ω

f = 1 kHz, G = 100, R_S= 0 Ω

f = 0.1 Hz to 10 Hz, G = 100, R_S= 0 Ω

f = 1 kHz

12.5

0.25

118

2.5

nV/√Hz

μV_PP

e_NI

e_NO

i_N

Input voltage noise

nV/√Hz

μV_PP

Output voltage noise

Input current noise

440

10

fA/√Hz

pA_PP

f = 0.1 Hz to 10 Hz

GAIN

G

Gain equation

Gain range

1 + (50 kΩ / R_G)

V/V

1

1000

±0.025%

±0.20%

±0.50%

5

G = 1, (V–) + 0.5 V ≤ V_O≤ (V+) – 1.5 V

G = 10, (V–) + 0.5 V ≤ V_O≤ (V+) – 1.5 V

G = 100, (V–) + 0.5 V ≤ V_O≤ (V+) – 1.5 V

G = 1000, (V–) + 0.5 V ≤ V_O≤ (V+) – 1.5 V

G = 1, T_A= –40°C to +125°C

±0.007%

±0.05%

±0.06%

±0.2%

1

E_G

Gain error

Gain versus temperature

Gain nonlinearity

ppm/°C

ppm

G > 1⁽⁴⁾, T_A= –40°C to +125°C

15

50

G = 1, V_O= –10 V to +10 V

3

8

G > 1, V_O= –10 V to +10 V

See Figure 42 to Figure 45

(1) Total V_OS, referred-to-input = (V_OSI) + (V_OSO/ G).

(2) RTI = Referred-to-input.

(3) 300-hour life test at 150°C demonstrated a randomly distributed variation of approximately 1 μV.

(4) Does not include effects of external resistor R_G.

5

INA188

ZHCSE92 –SEPTEMBER 2015

www.ti.com.cn

Electrical Characteristics: V_S= ±4 V to ±18 V (V_S= 8 V to 36 V) (continued)

At T_A= 25°C, R_L= 10 kΩ, V_REF= V_S/ 2, and G = 1, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OUTPUT

Output voltage swing from rail⁽⁵⁾

Capacitive load drive

R_L= 10 kΩ⁽⁵⁾

220

1

250

mV

nF

I_SC

Short-circuit current

Continuous to common

±18

mA

FREQUENCY RESPONSE

G = 1

600

95

G = 10

BW

SR

t_S

Bandwidth, –3 dB

Slew rate

kHz

G = 100

15

G = 1000

1.5

0.9

0.17

50

G = 1, V_S= ±18 V, V_O= 10-V step

G = 100, V_S= ±18 V, V_O= 10-V step

G = 1, V_S= ±18 V, V_STEP= 10 V

G = 100, V_S= ±18 V, V_STEP= 10 V

G = 1, V_S= ±18 V, V_STEP= 10 V

G = 100, V_S= ±18 V, V_STEP= 10 V

50% overdrive

V/μs

μs

To 0.1%

400

60

Settling time

To 0.01%

μs

500

75

Overload recovery

REFERENCE INPUT

R_INInput impedance

Voltage range

POWER SUPPLY

40

kΩ

V–

V+

V

Single

Dual

4

36

±18

1.6

1.8

Voltage range

V

±2

V_IN= V_S/ 2

1.4

I_Q

Quiescent current

mA

T_A= –40°C to +125°C

TEMPERATURE RANGE

Specified temperature range

Operating temperature range

–40

–55

125

150

°C

(5) See Typical Characteristics curves, Output Voltage Swing vs Output Current (Figure 19 to Figure 22).

6

INA188

www.ti.com.cn

ZHCSE92 –SEPTEMBER 2015

6.6 Electrical Characteristics: V_S= ±2 V to < ±4 V (V_S= 4 V to < 8 V)

At T_A= 25°C, R_L= 10 kΩ, V_REF= V_S/ 2, and G = 1, unless otherwise noted. Specifications not shown are identical to the

Electrical Characteristics table for V_S= ±2 V to ±18 V (V_S= 8 V to 36 V).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT⁽¹⁾

At RTI⁽²⁾

±25

±0.08

±60

±55

±0.2

μV

μV/°C

μV

V_OSI

Input stage offset voltage

Output stage offset voltage

At RTI, T_A= –40°C to +125°C

At RTI

±170

±0.35

V_OSO

At RTI, T_A= –40°C to +125°C

±0.2

μV/°C

±55 ±170 /

G

At RTI

±25 ±60 / G

μV

V_OS

Offset voltage

At RTI, T_A= –40°C to +125°C

±0.2 ±0.35 / G

μV/°C

Long-term stability

1⁽³⁾

µV

Turn-on time to specified V_OSI

Differential input impedance

Common-mode input impedance

See the Typical Characteristics

z_id

z_ic

100 || 6

GΩ || pF

100 || 9.5

V_O= 0 V, the input signal common-mode range can

be calculated with this tool

V_CM

Common-mode voltage range

(V–)

80

(V+) – 1.5

V

G = 1, at dc to 60 Hz, V_CM= (V–) + 1.0 V to

(V+) – 2.5 V

90

110

120

G = 10, at dc to 60 Hz, V_CM= (V–) + 1.0 V to

(V+) – 2.5 V

94

CMRR

Common-mode rejection ratio

dB

G = 100, at dc to 60 Hz, V_CM= (V–) + 1.0 V to

(V+) – 2.5 V

102

G = 1000, at dc to 60 Hz, V_CM= (V–) + 1.0 V to

(V+) – 2.5 V

INPUT BIAS CURRENT

±850

See Figure 10

±850

±2500

pA

pA/°C

pA

I_IB

Input bias current

T_A= –40°C to +125°C

I_OS

Input offset current

See Figure 11

pA/°C

INPUT VOLTAGE NOISE

f = 1 kHz, G = 100, R_S= 0 Ω

f = 0.1 Hz to 10 Hz, G = 100, R_S= 0 Ω

f = 1 kHz, G = 100, R_S= 0 Ω

f = 0.1 Hz to 10 Hz, G = 100, R_S= 0 Ω

f = 1 kHz

12.5

0.25

118

2.5

nV/√Hz

μV_PP

e_NI

e_NO

i_N

Input voltage noise

nV/√Hz

μV_PP

Output voltage noise

Input current noise

430

10

fA/√Hz

pA_PP

f = 0.1 Hz to 10 Hz

GAIN

G

Gain equation

Gain range

1 + (50 kΩ / R_G)

V/V

1

1000

±0.05%

±0.2%

±0.5%

5

G = 1, (V–) + 0.5 V ≤ V_O≤ (V+) – 1.5 V

G = 10, (V–) + 0.5 V ≤ V_O≤ (V+) – 1.5 V

G = 100, (V–) + 0.5 V ≤ V_O≤ (V+) – 1.5 V

G = 1000, (V–) + 0.5 V ≤ V_O≤ (V+) – 1.5 V

G = 1, T_A= –40°C to +125°C

±0.007%

±0.07%

±0.25%

1

E_G

Gain error

Gain versus temperature

Gain nonlinearity

ppm/°C

ppm

G > 1⁽⁴⁾, T_A= –40°C to +125°C

15

50

G = 1, V_O= (V–) + 0.5 V ≤ V_O≤ (V+) – 1.5 V

3

8

(1) Total V_OS, referred-to-input = (V_OSI) + (V_OSO/ G).

(2) RTI = Referred-to-input.

(3) 300-hour life test at 150°C demonstrated randomly distributed variation of approximately 1 μV.

(4) Does not include effects of external resistor R_G.

7

INA188

ZHCSE92 –SEPTEMBER 2015

www.ti.com.cn

Electrical Characteristics: V_S= ±2 V to < ±4 V (V_S= 4 V to < 8 V) (continued)

At T_A= 25°C, R_L= 10 kΩ, V_REF= V_S/ 2, and G = 1, unless otherwise noted. Specifications not shown are identical to the

Electrical Characteristics table for V_S= ±2 V to ±18 V (V_S= 8 V to 36 V).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OUTPUT

Output voltage swing from rail⁽⁵⁾

Capacitive load drive

R_L= 10 kΩ

220

1

250

mV

nF

I_SC

Short-circuit current

Continuous to common

±18

mA

FREQUENCY RESPONSE

G = 1

600

95

G = 10

BW

SR

t_S

Bandwidth, –3 dB

Slew rate

kHz

G = 100

15

G = 1000

1.5

0.9

0.17

50

G = 1, V_S= 5 V, V_O= 4-V step

G = 100, V_S= 5 V, V_O= 4-V step

G = 1, V_S= 5 V, V_STEP= 4 V

G = 100, V_S= 5 V, V_STEP= 4 V

G = 1, V_S= 5 V, V_STEP= 4 V

G = 100, V_S= 5 V, V_STEP= 4 V

50% overdrive

V/μs

μs

To 0.1%

400

60

Settling time

To 0.01%

μs

500

75

Overload recovery

REFERENCE INPUT

R_INInput impedance

Voltage range

POWER SUPPLY

40

kΩ

V–

V+

V

Single

Dual

4

36

±18

1.6

1.8

Voltage range

V

±2

V_IN= V_S/ 2

1.4

I_Q

Quiescent current

mA

T_A= –40°C to +125°C

TEMPERATURE RANGE

Specified temperature range

Operating temperature range

–40

–55

125

150

°C

(5) See Typical Characteristics curves, Output Voltage Swing vs Output Current (Figure 19 to Figure 22).

8

INA188

www.ti.com.cn

ZHCSE92 –SEPTEMBER 2015

6.7 Typical Characteristics

At T_A= 25°C, V_S= ±15 V, R_L= 10 kΩ, V_REF= midsupply, and G = 1, unless otherwise noted.

600

550

500

450

400

350

300

250

200

150

100

50

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

V_OSI(µV)

D001

Input Voltage Offset Drift (µV/°C)

–40°C to +125°C

Figure 1. Input Voltage Offset Distribution

Figure 2. Input Voltage Offset Drift Distribution

1000

900

800

700

600

500

400

300

200

100

0

45

40

35

30

25

20

15

10

5

0

V_OSO(µV)

D001

V_OSO(µV/°C)

–40°C to +125°C

Figure 3. Output Voltage Offset Distribution

Figure 4. Output Voltage Offset Drift Distribution

18

16

14

12

10

8

20

18

16

14

12

10

8

6

4

2

0

Input Bias Current (nA)

I_OS(nA)

Figure 5. Input Bias Current Distribution

Figure 6. Input Offset Current Distribution

9

INA188

ZHCSE92 –SEPTEMBER 2015

www.ti.com.cn

Typical Characteristics (continued)

At T_A= 25°C, V_S= ±15 V, R_L= 10 kΩ, V_REF= midsupply, and G = 1, unless otherwise noted.

27.5

25

45

40

35

30

25

20

15

10

5

22.5

20

17.5

15

12.5

10

7.5

5

2.5

0

Common-Mode Rejection (µV/V)

G = 1

G = 100

Figure 7. CMRR Distribution

Figure 8. CMRR Distribution

18000

16000

14000

12000

10000

8000

6000

4000

2000

0

0.95

0.9

0.85

0.8

0.75

0.7

0.65

0.6

0.55

0.5

0.45

0.4

I_IB±2 V

I_IB±15 V

0.35

0.3

-2000

-75 -50 -25

0

25

50

75 100 125 150 175

-15 -12

-9

-6

-3

0

3

6

9

12

15

Temperature (°C)

Common-Mode Voltage (V)

D001

Figure 9. Input Bias Current vs Common-Mode Voltage

Figure 10. Input Bias Current vs Temperature

6

4

700

650

600

550

500

450

400

350

300

2

0

-2

-4

-6

-75 -50 -25

0

25

50

75 100 125 150 175

0

10

20

30

40

50

60

70

80

90 100

Temperature (°C)

Time (s)

D001

Figure 11. Input Offset Current vs Temperature

Figure 12. Change in Input Offset Voltage vs Warm-Up Time

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ZHCSE92 –SEPTEMBER 2015

Typical Characteristics (continued)

At T_A= 25°C, V_S= ±15 V, R_L= 10 kΩ, V_REF= midsupply, and G = 1, unless otherwise noted.

150

130

110

90

150

130

110

90

G = 1

G = 10

G = 100

G = 1000

G = 10

G = 100

G = 1000

70

50

30

10

-10

10

100

1k

10k

100k

1M

10

100

1k

10k

100k

1M

Frequency (Hz)

At RTI

Figure 13. Positive PSRR vs Frequency

Figure 14. Negative PSRR vs Frequency

70

65

60

55

50

45

40

35

30

25

20

15

10

5

160

150

140

130

120

110

100

90

80

70

60

50

G=1

G=10

G=100

G=1000

40

30

G=1

G=10

G=100

G=1000

0

-5

20

10

-10

0

10

100

1k

10k

100k

1M

10M

10

100

1k

10k

100k

Frequency (Hz)

D001

At RTI

Figure 15. Gain vs Frequency

Figure 16. CMRR vs Frequency

160

150

140

130

120

110

100

90

50

40

G = 1

G > 1

30

20

10

80

0

70

60

50

40

30

20

10

0

-10

-20

-30

-40

-50

G=1

G=10

G=100

G=1000

10

100

1k

10k

100k

-75

-45

-15

15

45

75

105

135

Frequency (Hz)

Temperature (ºC)

D001

At RTI, 1-kΩ Source Imbalance

Figure 17. CMRR vs Frequency

Figure 18. Common-Mode Rejection Ratio vs Temperature

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ZHCSE92 –SEPTEMBER 2015

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Typical Characteristics (continued)

At T_A= 25°C, V_S= ±15 V, R_L= 10 kΩ, V_REF= midsupply, and G = 1, unless otherwise noted.

18

16

14

12

10

8

0

-40°C

125°C

25°C

-2

-4

-6

-8

-10

-12

-14

-16

-18

6

4

2

-40°C

125°C

25°C

0

-2

0

2.5

5

7.5 10 12.5 15 17.5 20 22.5 25

Output Current (mA)

0

3

6

9

12

15

18

21

24

27

30

Output Current (mA)

D001

V_S= ±18 V

Figure 19. Positive Output Voltage Swing vs

Output Current

Figure 20. Negative Output Voltage Swing vs

Output Current

2

0

-0.2

-0.4

-0.6

-0.8

-1

-40°C

125°C

25°C

1.8

1.6

1.4

1.2

1

0.8

0.6

0.4

0.2

0

-1.2

-1.4

-1.6

-1.8

-2

-40°C

125°C

25°C

0

2

4

6

8

10

12

14

16

18

20

0

2.5

5

7.5

10 12.5

15 17.5

20 22.5

Output Current (mA)

D001

V_S= ±2 V

Figure 21. Positive Output Voltage Swing vs

Output Current

Figure 22. Negative Output Voltage Swing vs

Output Current

2

100

50

1.6

1.2

0.8

0.4

0

20

10

5

2

1

-0.4

-0.8

-1.2

-1.6

-2

0.5

0.2

0.1

G = 1

G = 10

G = 100

G = 1000

0.05

0.02

1

10

100

1k

10k

100k

0

1

2

3

4

5

6

7

8

9

10

Frequency (Hz)

Time (s/div)

G = 1

Figure 23. Voltage Noise Spectral Density vs Frequency

Figure 24. 0.1-Hz to 10-Hz RTI Voltage Noise

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ZHCSE92 –SEPTEMBER 2015

Typical Characteristics (continued)

At T_A= 25°C, V_S= ±15 V, R_L= 10 kΩ, V_REF= midsupply, and G = 1, unless otherwise noted.

200

160

120

80

700

680

660

640

620

600

580

560

540

520

500

480

460

440

420

400

G = 1

G = 10

G = 100

G = 1000

40

0

-40

-80

-120

-160

-200

0

1

2

3

4

5

6

7

8

9

10

100

1k

10k

100k

Time (s/div)

Frequency (Hz)

G = 1000

Figure 25. 0.1-Hz to 10-Hz RTI Voltage Noise

Figure 26. Current Noise Spectral Density vs Frequency

35

10

8

V_S= 30 V

V_S= 4 V

32.5

30

6

27.5

25

4

22.5

20

2

0

17.5

15

-2

-4

-6

-8

-10

12.5

10

7.5

5

2.5

0

1

2

3

4

5

6

7

8

9

10

100

1k

10k

100k

Time (s/div)

Frequency (Hz)

D001

Figure 27. 0.1-Hz to 10-Hz RTI Current Noise

Figure 28. Large-Signal Response vs Frequency

6

4

6

4

2

0

-2

-4

-6

-2

-4

-6

0

50

100

150

200

250

300

350

400

0

50

100

150

200

250

300

350

400

Time (µs)

D001

R_L= 10 kΩ, C_L= 100 pF, G = 1

Figure 29. Large-Signal Pulse Response

R_L= 10 kΩ, C_L= 100 pF, G = 10

Figure 30. Large-Signal Pulse Response

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Typical Characteristics (continued)

At T_A= 25°C, V_S= ±15 V, R_L= 10 kΩ, V_REF= midsupply, and G = 1, unless otherwise noted.

6

4

2

0

-2

-4

-6

-2

-4

-6

0

50

100

150

200

250

300

350

400

0

0.5

1

1.5

2

2.5

3

3.5

4

Time (µs)

D001

R_L= 10 kΩ, C_L= 100 pF, G = 100

Figure 31. Large-Signal Pulse Response

R_L= 10 kΩ, C_L= 100 pF, G = 1000

Figure 32. Large-Signal Pulse Response

100

75

60

40

50

20

25

0

-25

-50

-75

-100

-20

-40

-60

0

50

100

150

200

250

300

350

400

0

50

100

150

200

250

300

350

400

Time (µs)

D001

R_L= 10 kΩ, C_L= 100 pF, G = 1

Figure 33. Small-Signal Pulse Response

R_L= 10 kΩ, C_L= 100 pF, G = 10

Figure 34. Small-Signal Pulse Response

60

40

60

40

20

0

-20

-40

-60

-20

-40

-60

0

50

100

150

200

250

300

350

400

0

0.5

1

1.5

2

2.5

3

3.5

4

Time (µs)

D001

R_L= 10 kΩ, C_L= 100 pF, G = 100

Figure 35. Small-Signal Pulse Response

R_L= 10 kΩ, C_L= 100 pF, G = 1000

Figure 36. Small-Signal Pulse Response

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ZHCSE92 –SEPTEMBER 2015

Typical Characteristics (continued)

At T_A= 25°C, V_S= ±15 V, R_L= 10 kΩ, V_REF= midsupply, and G = 1, unless otherwise noted.

150

100

50

1

0 pF

G = 1, 1-Vrms out, 2-kW load

G = 10, 1-Vrms out, 2-kW load

0.5

100 pF

220 pF

500 pF

1000 pF

0.3

0.2

0.1

0.05

0.03

0.02

0

0.01

0.005

-50

-100

0.003

0.002

0.001

0

20

40

60

80

100

120

100

1k

10k

Time (µs)

Frequency (Hz)

G = 1

Figure 37. Small-Signal Response vs Capacitive Load

Figure 38. Total Harmonic Distortion + Noise vs Frequency

1.5

1.38

1.36

1.34

1.32

1.3

1.45

1.4

1.35

1.3

1.28

1.26

1.24

1.22

1.2

1.25

1.2

1.15

1.1

-75

-50

-25

0

25

50

75

100 125 150

0

5

10

15

20

25

30

35

40

45

Temperature (°C)

Supply Voltage (V)

D001

Figure 39. Supply Current vs Temperature

Figure 40. Supply Current vs Supply Voltage

10k

4

3.2

2.4

1.6

0.8

0

1k

100

10

-0.8

-1.6

-2.4

-3.2

-4

1

0.1

1

10

100

1k

10k

100k

1M

10M

-10

-8

-6

-4

-2

0

2

4

6

8

10

Frequency (Hz)

Output Voltage (V)

D001

G = 1

Figure 41. Open-Loop Output Impedance

Figure 42. Gain Nonlinearity

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INA188

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Typical Characteristics (continued)

At T_A= 25°C, V_S= ±15 V, R_L= 10 kΩ, V_REF= midsupply, and G = 1, unless otherwise noted.

4

3.2

2.4

1.6

0.8

0

15

12

9

6

3

0

-0.8

-1.6

-2.4

-3.2

-4

-3

-6

-9

-12

-15

-10

-8

-6

-4

-2

0

2

4

6

8

10

-10

-8

-6

-4

-2

0

2

4

6

8

10

Output Voltage (V)

D001

G = 10

G = 100

Figure 43. Gain Nonlinearity

Figure 44. Gain Nonlinearity

180

160

140

120

100

80

10

8

Single-Ended Input

Common-Mode Input

6

4

2

0

-2

-4

-6

-8

-10

60

40

20

0

10M

100M

Frequency (Hz)

1G

10G

-10

-8

-6

-4

-2

0

2

4

6

8

10

Output Voltage (V)

D001

G = 1000

Figure 46. EMIRR

Figure 45. Gain Nonlinearity

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7 Detailed Description

7.1 Overview

The INA188 is a monolithic instrumentation amplifier (INA) based on the 36-V, precision zero-drift OPA188

(operational amplifier) core. The INA188 also integrates laser-trimmed resistors to ensure excellent common-

mode rejection and low gain error. The combination of the zero-drift amplifier core and the precision resistors

allows this device to achieve outstanding dc precision and makes the INA188 ideal for many high-voltage

industrial applications.

7.2 Functional Block Diagram

V₁= V_CMœ G₁(V_DIFF/ 2)

V+

V_IN-= V_CMœ V_DIFF/ 2

V+

V_DIFF/ 2

RFI Filter

V_IN-

A₁

+

Zero-Drift

Amp

-

V+

20 kꢀ

V-

V+

RFI Filter

25 kꢀ

20 kꢀ

A₃

V_OUT

-

V+

Zero-Drift

Amp

+

R_G

V-

+

V_CM

œ

+

V-

V_O= G₁x G₂(V_IN+- V_IN-

)

R_LOAD

V+

-

V+

20 kꢀ

V-

-

A₂

Zero-Drift

Amp

V_IN+

+

REF

RFI Filter

V_DIFF/ 2

G₁= 1 + 2R_F/ R_G

G₂= R₂/ R₁

V-

V_IN+= V_CM+ V_DIFF/ 2

V₂= V_CM+ G₁(V_DIFF/ 2)

V_IN-

INA188

Simplified

Form

V_OUT

R_G

+

V_IN+

REF

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ZHCSE92 –SEPTEMBER 2015

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7.3 Feature Description

7.3.1 Inside the INA188

The Functional Block Diagram section provides a detailed diagram for the INA188, including the ESD protection

and radio frequency interference (RFI) filtering. Instrumentation amplifiers are commonly represented in a

simplified form, as shown in Figure 47.

V_IN-

INA188

Simplified

Form

V_OUT

R_G

+

V_IN+

REF

Figure 47. INA Simplified Form

A brief description of the internal operation is as follows:

The differential input voltage applied across R_Gcauses a signal current to flow through the R_Gresistor and both

R_Fresistors. The output difference amplifier (A₃) removes the common-mode component of the input signal and

refers the output signal to the REF pin.

The equations shown in the Functional Block Diagram section describe the output voltages of A₁and A₂.

Understanding the internal node voltages is useful to avoid saturating the device and to ensure proper device

operation.

7.3.2 Setting the Gain

The gain of the INA188 is set by a single external resistor, R_G, connected between pins 1 and 8. The value of R_G

is selected according to Equation 1:

50 kW

R_G

G =1+

(1)

Table 1 lists several commonly-used gains and resistor values. The 50-kΩ term in Equation 1 comes from the

sum of the two internal 25-kΩ feedback resistors. These on-chip resistors are laser-trimmed to accurate absolute

values. The accuracy and temperature coefficients of these resistors are included in the gain accuracy and drift

specifications of the INA188.

Table 1. Commonly-Used Gains and Resistor Values

DESIRED GAIN

R_G(Ω)

NC⁽¹⁾

50k

NEAREST 1% R_G(Ω)

1

2

NC

49.9k

12.4k

5.49k

2.61k

1.02k

511

5

12.5k

5.556k

2.632k

1.02k

505.1

251.3

100.2

50.05

10

20

50

100

200

500

1000

249

100

49.9

(1) NC denotes no connection. When using the SPICE model, the simulation does not converge unless a resistor is connected to the R_G

pins; use a very large resistor value.

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ZHCSE92 –SEPTEMBER 2015

7.3.2.1 Gain Drift

The stability and temperature drift of the external gain setting resistor, R_G, also affects gain. The contribution of

R_Gto gain accuracy and drift can be determined from Equation 1.

The best gain drift of 5 ppm/℃ can be achieved when the INA188 uses G = 1 without R_Gconnected. In this case,

gain drift is limited only by the slight mismatch of the temperature coefficient of the integrated 20-kΩ resistors in

the differential amplifier (A₃). At gains greater than 1, gain drift increases as a result of the individual drift of the

25-kΩ resistors in the feedback of A₁and A₂, relative to the drift of the external gain resistor R_G. The low

temperature coefficient of the internal feedback resistors significantly improves the overall temperature stability of

applications using gains greater than 1 V/V over competing alternate solutions.

Low resistor values required for high gain can make wiring resistance important. Sockets add to the wiring

resistance and contribute additional gain error (such as a possible unstable gain error) at gains of approximately

100 or greater. To ensure stability, avoid parasitic capacitance of more than a few picofarads at R_Gconnections.

Careful matching of any parasitics on both R_Gpins maintains optimal CMRR over frequency; see Typical

Characteristics curve, Figure 17.

7.3.3 Zero Drift Topology

7.3.3.1 Internal Offset Correction

Figure 48 shows a simple representation of the proprietary zero-drift architecture for one of the three amplifiers

that comprise the INA188. These high-precision input amplifiers enable very low dc error and drift as a result of a

modern chopper technology with an embedded synchronous filter that removes nearly all chopping noise. The

chopping frequency is approximately 750 kHz. This amplifier is zero-corrected every 3 μs using a proprietary

technique. This design has no aliasing.

C2

Zero-Drift Amplifier Inside the INA188

Notch

Filter

GM1

CHOP1

CHOP2

GM2

GM3

+

-

+

-

OUT

+IN

-IN

-

+

-

C1

GM_FF

+

-

Figure 48. Zero-Drift Amplifier Functional Block Diagram

7.3.3.2 Noise Performance

This zero-drift architecture reduces flicker (1/f) noise to a minimum, and therefore enables the precise

measurement of small dc-signals with high resolution, accuracy, and repeatability. The auto-calibration technique

used by the INA188 results in reduced low-frequency noise, typically only 12 nV/√Hz (at G = 100). The spectral

noise density is detailed in Figure 53. Low-frequency noise of the INA188 is approximately 0.25 μV_PPmeasured

from 0.1 Hz to 10 Hz (at G = 100).

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7.3.3.3 Input Bias Current Clock Feedthrough

Zero-drift amplifiers, such as the INA188, use switching on their inputs to correct for the intrinsic offset and drift of

the amplifier. Charge injection from the integrated switches on the inputs can introduce very short transients in

the input bias current of the amplifier. The extremely short duration of these pulses prevents them from being

amplified; however, the pulses can be coupled to the output of the amplifier through the feedback network. The

most effective method to prevent transients in the input bias current from producing additional noise at the

amplifier output is to use a low-pass filter (such as an RC network).

7.3.4 EMI Rejection

The INA188 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from

sources (such as wireless communications) and densely-populated boards with a mix of analog signal-chain and

digital components. The INA188 is specifically designed to minimize susceptibility to EMI by incorporating an

internal low-pass filter. Depending on the end-system requirements, additional EMI filters may be required near

the signal inputs of the system, as well as incorporating known good practices such as using short traces, low-

pass filters, and damping resistors combined with parallel and shielded signal routing. Texas Instruments

developed a method to accurately measure the immunity of an amplifier over a broad frequency spectrum,

extending from 10 MHz to 6 GHz. This method uses an EMI rejection ratio (EMIRR) to quantify the INA188 ability

to reject EMI. Figure 49 and Figure 50 show the INA188 EMIRR graph for both differential and common-mode

EMI rejection across this frequency range. Table 2 shows the EMIRR values for the INA188 at frequencies

commonly encountered in real-world applications. Applications listed in Table 2 can be centered on or operated

near the particular frequency shown.

180

160

140

120

100

80

160

140

120

100

80

60

40

20

0

10M

100M

Frequency (Hz)

1G

10G

10M

100M

Frequency (Hz)

1G

10G

C035

C036

Figure 49. Common Mode EMIRR Testing

Figure 50. Differential Mode (VIN+) EMIRR Testing

Table 2. INA188 EMIRR for Frequencies of Interest

DIFFERENTIAL COMMON-MODE

FREQUENCY

APPLICATION OR ALLOCATION

(IN-P) EMIRR

EMIRR

Mobile radio, mobile satellite, space operation, weather, radar, ultrahigh-

frequency (UHF) applications

400 MHz

83 dB

101 dB

Global system for mobile communications (GSM) applications, radio

communication, navigation, GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF

applications

900 MHz

1.8 GHz

2.4 GHz

103 dB

112 dB

114 dB

118 dB

125 dB

123 dB

GSM applications, mobile personal communications, broadband, satellite,

L-band (1 GHz to 2 GHz)

802.11b, 802.11g, 802.11n, Bluetooth^®, mobile personal communications,

industrial, scientific and medical (ISM) radio band, amateur radio and satellite,

S-band (2 GHz to 4 GHz)

3.6 GHz

5.0 GHz

Radiolocation, aero communication and navigation, satellite, mobile, S-band

110 dB

119 dB

121 dB

123 dB

802.11a, 802.11n, aero communication and navigation, mobile communication,

space and satellite operation, C-band (4 GHz to 8 GHz)

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7.3.5 Input Protection and Electrical Overstress

Designers often ask questions about the capability of an amplifier to withstand electrical overstress. These

questions tend to focus on the device inputs, but can involve the supply voltage pins or even the output pin. Each

of these different pin functions have electrical stress limits determined by the voltage breakdown characteristics

of the particular semiconductor fabrication process and specific circuits connected to the pin. Additionally, internal

ESD protection is built into these circuits to protect them from accidental ESD events both before and during

product assembly.

Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is

helpful. The Functional Block Diagram section illustrates the ESD circuits contained in the INA188. The ESD

protection circuitry involves several current-steering diodes connected from the input and output pins and routed

back to the internal power-supply lines. This protection circuitry is intended to remain inactive during normal

circuit operation.

The input pins of the INA188 are protected with internal diodes connected to the power-supply rails. These

diodes clamp the applied signal to prevent the input circuitry from being damaged. If the input signal voltage can

exceed the power supplies by more than 0.3 V, limit the input signal current to less than 10 mA to protect the

internal clamp diodes. This current limiting can generally be done with a series input resistor. Some signal

sources are inherently current-limited and do not require limiting resistors.

7.3.6 Input Common-Mode Range

The linear input voltage range of the INA188 input circuitry extends from 100 mV inside the negative supply

voltage to 1.5 V below the positive supply, and maintains 84-dB (minimum) common-mode rejection throughout

this range. The common-mode range for most common operating conditions is best calculated using the INA

common-mode range calculating tool. The INA188 can operate over a wide range of power supplies and V_REF

configurations, thus providing a comprehensive guide to common-mode range limits for all possible conditions is

impractical.

The most commonly overlooked overload condition occurs when a circuit exceeds the output swing of A₁and A₂,

which are internal circuit nodes that cannot be measured. Calculating the expected voltages at the output of A₁

and A₂(see the Functional Block Diagram section) provides a check for the most common overload conditions.

The designs of A₁and A₂are identical and the outputs can swing to within approximately 250 mV of the power-

supply rails. For example, when the A₂output is saturated, A₁can continue to be in linear operation, responding

to changes in the noninverting input voltage. This difference can give the appearance of linear operation but the

output voltage is invalid.

7.4 Device Functional Modes

7.4.1 Single-Supply Operation

The INA188 can be used on single power supplies of 4 V to 36 V. Use the output REF pin to level shift the

internal output voltage into a linear operating condition. Ideally, connecting the REF oin to a potential that is mid-

supply avoids saturating the output of the input amplifiers (A₁and A₂). Actual output voltage swing is limited to

250 mV above ground when the load is referred to ground. The typical characteristic curves, Output Voltage

Swing vs Output Current (Figure 19 to Figure 22) illustrates how the output voltage swing varies with output

current. See the Driving the Reference Pin section for information on how to adequately drive the reference pin.

With single-supply operation, V_IN+and V_IN–must both be 0.1 V above ground for linear operation. For instance,

the inverting input cannot be connected to ground to measure a voltage connected to the noninverting input.

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ZHCSE92 –SEPTEMBER 2015

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Device Functional Modes (continued)

7.4.2 Offset Trimming

Most applications require no external offset adjustment; however, if necessary, adjustments can be made by

applying a voltage to the REF pin. Figure 51 shows an optional circuit for trimming the output offset voltage. The

voltage applied to the REF pin is summed at the output. The op amp buffer provides low impedance at the REF

pin to preserve good common-mode rejection.

V_IN-

-

V+

R_G

INA188

REF

100 µA

½ REF200

V_IN+

+

100 ꢀ

OPA333

+

10 kꢀ

±10 mV Adjustment

Range

100 ꢀ

100 µA

½ REF200

V-

Figure 51. Optional Trimming of the Output Offset Voltage

22

INA188

www.ti.com.cn

ZHCSE92 –SEPTEMBER 2015

Device Functional Modes (continued)

7.4.3 Input Bias Current Return Path

The input impedance of the INA188 is extremely high—approximately 20 GΩ. However, a path must be provided

for the input bias current of both inputs. This input bias current is typically 750 pA. High input impedance means

that this input bias current changes very little with varying input voltage.

Input circuitry must provide a path for this input bias current for proper operation. Figure 52 shows various

provisions for an input bias current path. Without a bias current path, the inputs float to a potential that exceeds

the common-mode range of the INA188, and the input amplifiers saturate. If the differential source resistance is

low, the bias current return path can be connected to one input (as shown in the thermocouple example in

Figure 52). With a higher source impedance, using two equal resistors provides a balanced input with possible

advantages of a lower input offset voltage as a result of bias current and better high-frequency common-mode

rejection.

-

Microphone,

hydrophone,

and so forth.

R_G

INA188

+

47 kꢀ

-

Thermocouple

+

10 kꢀ

-

+

Center tap provides

bias current return.

Figure 52. Providing an Input Common-Mode Current Path

23

INA188

ZHCSE92 –SEPTEMBER 2015

www.ti.com.cn

Device Functional Modes (continued)

7.4.4 Driving the Reference Pin

The output voltage of the INA188 is developed with respect to the voltage on the reference pin. Often, the

reference pin (pin 5) is connected to the low-impedance system ground in dual-supply operation. In single-supply

operation, offsetting the output signal to a precise mid-supply level (for example, 2.5 V in a 5-V supply

environment) can be useful. To accomplish this, a voltage source can be tied to the REF pin to level-shift the

output so that the INA188 can drive a single-supply analog-to-digital converter (ADC).

For best performance, keep the source impedance to the REF pin below 5 Ω. As illustrated in the Functional

Block Diagram section, the reference pin is internally connected to a 20-kΩ resistor. Additional impedance at the

REF pin adds to this 20-kΩ resistor. The imbalance in the resistor ratios results in degraded common-mode

rejection ratio (CMRR).

Figure 53 shows two different methods of driving the reference pin with low impedance. The OPA330 is a low-

power, chopper-stabilized amplifier, and therefore offers excellent stability over temperature. The OPA330 is

available in a space-saving SC70 and an even smaller chip-scale package. The REF3225 is a precision

reference in a small SOT23-6 package.

5 V

V_IN-

V_OUT

R_G

INA188

REF

V_IN+

+

5 V

2.5 V

REF3225

+

a) Level shifting using the OPA330 as a low-impedance buffer.

b) Level shifting using the low-impedance output of the REF3225.

Figure 53. Options for Low-Impedance Level Shifting

24

INA188

www.ti.com.cn

ZHCSE92 –SEPTEMBER 2015

Device Functional Modes (continued)

7.4.5 Error Sources Example

Most modern signal-conditioning systems calibrate errors at room temperature. However, calibration of errors

that result from a change in temperature is normally difficult and costly. Therefore, minimizing these errors is

important and can be done by choosing high-precision components (such as the INA188 that has improved

specifications in critical areas that impact the precision of the overall system). Figure 54 shows an example

application.

15 V

10 kꢀ

-

+

R_G

5.49 kꢀ

V_DIFF= 1 V

INA188

V_OUT

-

10 kꢀ

REF

+

V_CM= 10 V

Signal Bandwidth = 5 kHz

-15 V

Figure 54. Example Application with G = 10 V/V and a 1-V Differential Voltage

Resistor-adjustable INAs such as the INA188 show the lowest gain error in G = 1 because of the inherently well-

matched drift of the internal resistors of the differential amplifier. At gains greater than 1 (for instance, G = 10 V/V

or G = 100 V/V) the gain error becomes a significant error source because of the contribution of the resistor drift

of the 25-kΩ feedback resistors in conjunction with the external gain resistor. Except for very high-gain

applications, gain drift is by far the largest error contributor compared to other drift errors, such as offset drift. The

INA188 offers the lowest gain error over temperature in the marketplace for both G > 1 and G = 1 (no external

gain resistor). Table 3 summarizes the major error sources in common INA applications and compares the two

cases of G = 1 (no external resistor) and G = 10 (5.49-kΩ external resistor). As explained in Table 3, although

the static errors (absolute accuracy errors) in G = 1 are almost twice as great as compared to G = 10, there are

much fewer drift errors because of the much lower gain error drift. In most applications, these static errors can

readily be removed during calibration in production. All calculations refer the error to the input for easy

comparison and system evaluation.

25

INA188

ZHCSE92 –SEPTEMBER 2015

www.ti.com.cn

Device Functional Modes (continued)

Table 3. Error Calculation

G = 10 ERROR

(ppm)

G = 1 ERROR

(ppm)

SPECIFICATION

ERROR SOURCE

ABSOLUTE ACCURACY AT 25°C

Input offset voltage

ERROR CALCULATION

V_OSI/ V_DIFF

V_OSO/ (G × V_DIFF

I_OS× maximum (R_S+, R_S–) / V_DIFF

65 μV

180 μV

5 nA

65

18

50

65

180

50

Output offset voltage

)

Input offset current

104 dB (G = 10),

84 dB (G = 1)

V_CM/ (10^CMRR/20× V_DIFF

)

Common-mode rejection ratio

20

501

796

Total absolute accuracy error (ppm)

153

DRIFT TO 105°C

35 ppm/°C (G = 10),

1 ppm/°C (G = 1)

Gain drift

GTC × (T_A– 25)

2800

80

Input offset voltage drift

Output offset voltage drift

(V_{OSI_TC}/ V_DIFF) × (T_A– 25)

0.15 μV/°C

0.85 μV/°C

12

68

[V_{OSO_TC}/ ( G × V_DIFF)] × (T_A– 25)

6.8

I_{OS_TC}× maximum (R_S+, R_S–) ×

(T_A– 25) / V_DIFF

Offset current drift

60 pA/°C

48

Total drift error (ppm)

RESOLUTION

2867

208

Gain nonlinearity

5 ppm of FS

5

9

5

2

e_NO

6

e_NI= 18,

e_NO= 110

2

(e_NI

+

´

BW

Voltage noise (1 kHz)

47

G

V_DIFF

Total resolution error (ppm)

TOTAL ERROR

14

52

Total error (ppm)

Total error = sum of all error sources

3034

1056

26

INA188

www.ti.com.cn

ZHCSE92 –SEPTEMBER 2015

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The INA188 measures a small differential voltage with a high common-mode voltage developed between the

noninverting and inverting input. The low offset drift in conjunction with no 1/f noise makes the INA188 suitable

for a wide range of applications. The ability to set the reference pin to adjust the functionality of the output signal

offers additional flexibility that is practical for multiple configurations.

8.2 Typical Application

Figure 55 shows the basic connections required for operating the INA188. Applications with noisy or high-

impedance power supplies may require decoupling capacitors close to the device pins. The output is referred to

the output reference (REF) pin that is normally grounded. The reference pin must be a low-impedance

connection to assure good common-mode rejection.

15 V

±10 V

100 kꢀ

-

R_G

12.4 kꢀ

4.87 kꢀ

20 ꢀ

V_OUT= 2.5 V ± 2.3 V

INA188

4 mA to 20 mA

±20 mA

+

REF

2.5 V

REF3225

5 V

-15 V

10 ꢁF

Figure 55. PLC Input (±10 V, 4 mA to 20 mA)

8.2.1 Design Requirements

For this application, the design requirements are:

•

4-mA to 20-mA input with less than 20-Ω burden

±20-mA input with less than 20-Ω burden

±10-V input with impedance of approximately 100 kΩ

Maximum 4-mA to 20-mA or ±20mA burden voltage equal to ±0.4 V

Output range within 0 V to 5 V

27

INA188

ZHCSE92 –SEPTEMBER 2015

www.ti.com.cn

Typical Application (continued)

8.2.2 Detailed Design Procedure

The following steps must be applied for proper device functionality:

•

For a 4-mA to 20-mA input, the maximum burden of 0.4 V must have a burden resistor equal to 0.4 / 0.02 =

20 Ω.

•

To center the output within the 0-V to 5-V range, V_REFmust equal 2.5 V.

To keep the ±20-mA input linear within 0 V to 5 V, the gain resistor (R_G) must be 12.4 kΩ.

To keep the ±10-V input within the 0-V to 5-V range, attenuation must be greater than 0.05.

A 100-kΩ resistor in series with a 4.87-kΩ resistor provides 0.0466 attenuation of ±10 V, well within the ±2.5-

V linear limits.

8.2.3 Application Curve

5

4.5

4

3.5

3

2.5

2

1.5

1

0.5

0

-10

-8

-6

-4

-2

0

2

4

6

8

10

Input (V)

D001

Figure 56. Plot of PLC Input Transfer Function

28

INA188

www.ti.com.cn

ZHCSE92 –SEPTEMBER 2015

9 Power Supply Recommendations

The minimum power-supply voltage for the INA188 is ±2 V and the maximum power-supply voltage is ±18 V.

This minimum and maximum range covers a wide range of power supplies. However, for optimum performance,

±15 V is recommended. A 0.1-µF bypass capacitor is recommended to be added at the input to compensate for

the layout and power-supply source impedance.

10 Layout

10.1 Layout Guidelines

Attention to good layout practices is always recommended. For best operational performance of the device, use

good printed circuit board (PCB) layout practices, including:

•

Care must be taken to ensure that both input paths are well-matched for source impedance and capacitance

to avoid converting common-mode signals into differential signals. In addition, parasitic capacitance at the

gain-setting pins can also affect CMRR over frequency. For example, in applications that implement gain

switching using switches or PhotoMOS^®relays to change the value of R_G, select the component so that the

switch capacitance is as small as possible.

•

Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of the device

itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources

local to the analog circuitry.

–

Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as

close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-

supply applications.

•

Separate grounding for analog and digital portions of the circuitry is one of the simplest and most effective

methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.

A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital

and analog grounds, paying attention to the flow of the ground current. For more detailed information, see

SLOA089, Circuit Board Layout Techniques.

In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as

possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better

than in parallel with the noisy trace.

•

Place the external components as close to the device as possible. As illustrated in Figure 57, keeping R_G

close to the pins minimizes parasitic capacitance.

Keep the traces as short as possible.

29

INA188

ZHCSE92 –SEPTEMBER 2015

www.ti.com.cn

10.2 Layout Example

Gain Resistor

Bypass

Capacitor

R₆

V–_IH

V+_IH

V–

R₆

V+

–

V_IN

V_O

V_OUT

GND

+

REF

Bypass

Capacitor

V–

GND

Figure 57. PCB Layout Example

30

INA188

www.ti.com.cn

ZHCSE92 –SEPTEMBER 2015

11 器件和文档支持

11.1 器件支持

11.1.1 开发支持

表 4. 表 1.设计套件与评估模块

名称

部件号

类型

DIP 适配器评估模块

DIP-ADAPTER-EVM

评估模块和评估板

通用仪表放大器评估模块

INAEVM

表 5. 表 2.开发工具

名称

部件号

类型

计算仪表放大器的输入共模范围

基于 SPICE 的模拟仿真程序

INA-CMV-CALC

TINA-TI

计算工具

电路设计和仿真

11.2 文档支持

11.2.1 相关文档ꢀ

《OPA188 数据表》，SBOS642

《OPA330 数据表》，SBOS432

《REF3225 数据表》，SBVS058

《电路板布局布线技巧》，SLOA089

11.3 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.4 商标

E2E is a trademark of Texas Instruments.

Bluetooth is a registered trademark of Bluetooth SIG, Inc.

PhotoMOS is a registered trademark of Panasonic Electric Works Europe AG.

All other trademarks are the property of their respective owners.

11.5 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

11.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

31

INA188

ZHCSE92 –SEPTEMBER 2015

www.ti.com.cn

12 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不

对本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

32

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都遵循在订单确认时所提供的TI 销售条款与条件。

TI 保证其所销售的组件的性能符合产品销售时 TI 半导体产品销售条件与条款的适用规范。仅在 TI 保证的范围内，且 TI 认为有必要时才会使

用测试或其它质量控制技术。除非适用法律做出了硬性规定，否则没有必要对每种组件的所有参数进行测试。

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IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122

PACKAGE OUTLINE

D0008A

SOIC - 1.75 mm max height

SCALE 2.800

SMALL OUTLINE INTEGRATED CIRCUIT

C

SEATING PLANE

.228-.244 TYP

[5.80-6.19]

.004 [0.1] C

A

PIN 1 ID AREA

6X .050

[1.27]

8

1

2X

.189-.197

[4.81-5.00]

NOTE 3

.150

[3.81]

4X (0 -15 )

4

5

8X .012-.020

[0.31-0.51]

B

.150-.157

[3.81-3.98]

NOTE 4

.069 MAX

[1.75]

.010 [0.25]

C A B

.005-.010 TYP

[0.13-0.25]

4X (0 -15 )

SEE DETAIL A

.010

[0.25]

.004-.010

[0.11-0.25]

0 - 8

.016-.050

[0.41-1.27]

DETAIL A

TYPICAL

(.041)

[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

www.ti.com

EXAMPLE BOARD LAYOUT

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

SEE

DETAILS

1

8

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

5

4

6X (.050 )

[1.27]

(.213)

[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED

METAL

EXPOSED

METAL

.0028 MAX

[0.07]

.0028 MIN

[0.07]

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

1

8

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

5

4

6X (.050 )

[1.27]

(.213)

[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

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型号：	INA188IDR
厂家：	TEXAS INSTRUMENTS
描述：	36V、零漂移、轨到轨输出仪表放大器 \| D \| 8 \| -40 to 125 放大器仪表仪表放大器
文件：	总42页 (文件大小：1901K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

INA188IDR [TI]

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