INA203-Q1_16 [TI]
Low- or High-Side, High-Speed, Voltage Output Current Shunt Monitor;
| 型号： | INA203-Q1_16 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Low- or High-Side, High-Speed, Voltage Output Current Shunt Monitor |
| 文件： | 总23页 (文件大小：701K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INA203-Q1
www.ti.com
SBOS539 –DECEMBER 2010
Unidirectional Measurement
Current-Shunt Monitor with Dual Comparators
Check for Samples: INA203-Q1
1
FEATURES
DESCRIPTION
2
•
•
•
Qualified for Automotive Applications
Complete Current Sense Solution
Dual Comparators:
The INA203-Q1 is a unidirectional current-shunt
monitor with voltage output, dual comparators, and
voltage reference. The INA203-Q1 can sense drops
across shunts at common-mode voltages from –16V
to +80V. The INA203-Q1 is available with three
output voltage scales: 20V/V, 50V/V, and 100V/V,
with up to 500kHz bandwidth.
–
–
Comparator 1 with Latch
Comparator 2 with Optional Delay
•
•
•
•
•
Common-Mode Range: –16V to +80V
High Accuracy: 3.5% (max) Over Temperature
Bandwidth: 500kHz
The INA203-Q1also incorporates two open-drain
comparators with internal 0.6V references. On 14-pin
versions, the comparator references can be
overridden by external inputs. Comparator 1 includes
a latching capability, and Comparator 2 has a
user-programmable delay. 14-pin versions also
provide a 1.2V reference output.
Quiescent Current: 1.8mA
Latch-Up Performance Meets 100 mA Per
AEC-Q100, Level I
•
Packages: SO-14, TSSOP-14, MSOP-10
The INA203-Q1 operates from a single +2.7V to
+18V supply. It is specified over the extended
operating temperature range of –40°C to +125°C.
APPLICATIONS
•
•
•
Automotive
Power Management
Battery Chargers
VIN+
VS
OUT
1
2
3
4
5
10
9
VIN-
VIN+
VS
1
2
3
4
5
6
7
14
13
12
11
10
9
CMP1 OUT
CMP2 OUT
CMP1 RESET
CMP1 IN+
CMP2 IN+
GND
8
VIN-
OUT
7
1.2V REF
1.2V REF OUT
CMP1 OUT
CMP2 OUT
CMP2 DELAY
CMP1 RESET
CMP1 IN-/0.6V REF
CMP1 IN+
6
0.6V REF
CMP2 IN+
RELATED PRODUCTS
CMP2 IN-/0.6V REF
GND
FEATURES
PRODUCT
Variant of INA203-Q1–INA205 Comparator 2
polarity
INA206–INA208
8
Current-shunt monitor with single Comparator
and VREF
INA200–INA202
Current-shunt monitor only
INA193–INA198
INA270–INA271
Current-shunt monitor with split stages for filter
options
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
INA203-Q1
SBOS539 –DECEMBER 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Table 1. ORDERING INFORMATION(1)
ORDERABLE PART
TA
PACKAGE
NUMBER
TOP-SIDE MARKING
-40°C to 125°C
SOIC-8
Reel of 2000
INA203AQPWRQ1
I203AQ
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
VALUE
UNIT
V
Supply Voltage, V+
18
–18 to +18
Differential (VIN+) – (VIN–
)
V
Current-Shunt Monitor Analog
Inputs, VIN+and VIN–
Common-Mode
–16 to +80
V
Comparator Analog Input and Reset Pins
Analog Output, Out Pin
GND – 0.3 to (V+) + 0.3
GND – 0.3 to (V+) + 0.3
GND – 0.3 to 18
GND – 0.3 to 10
5
V
V
Comparator Output, Out Pin
VREF and CMP2 Delay Pin
Input Current Into Any Pin
Storage Temperature
V
V
mA
°C
°C
V
–65 to +150
+150
Junction Temperature
Human Body Model (HBM)
2000
ESD Ratings
Charged Device Model (CDM)
500
V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
2
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SBOS539 –DECEMBER 2010
ELECTRICAL CHARACTERISTICS: CURRENT-SHUNT MONITOR
Boldface limits apply over the specified temperature range: TA = –40°C to +125°C.
At TA = +25°C, VS = +12V, VCM = +12V, VSENSE = 100mV, RL = 10kΩ to GND, RPULL-UP = 5.1kΩ each connected from CMP1
OUT and CMP2 OUT to VS, and CMP1 IN+ = 1V and CMP2 IN– = GND, unless otherwise noted.
CURRENT-SHUNT MONITOR PARAMETERS
CONDITIONS
MIN
TYP
MAX
UNIT
INPUT
Full-Scale Sense Input Voltage
Common-Mode Input Range
Common-Mode Rejection Ratio
+25°C to +125°C
VSENSE
VCM
VSENSE = VIN+ – VIN–
0.15
(VS – 0.25)/Gain
V
V
–16
80
80
CMRR
VCM = –16V to +80V
VCM = +12V to +80V
100
123
100
±0.5
dB
100
90
dB
–40°C to +25°C
Offset Voltage, RTI(1)
dB
VOS
±2.5
±3
mV
mV
mV
mV/°C
mV/V
mA
+25°C to +125°C
–40°C to +25°C
±3.5
vs Temperature
dVOS/dT
PSR
IB
TMIN to TMAX
5
vs Power Supply
VOUT = 2V, VCM = +18V
2.5
±9
100
±16
Input Bias Current, VIN– Pin
OUTPUT (VSENSE ≥ 20mV)
Gain
G
20
V/V
%
Gain Error
VSENSE = 20mV to 100mV
VSENSE = 20mV to 100mV
VSENSE = 120mV, VS = +16V
VSENSE = 120mV, VS = +16V
VSENSE = 20mV to 100mV
±0.2
±1
±2
Over Temperature
Total Output Error(2)
Over Temperature
Nonlinearity Error(3)
Output Impedance, Pin 2
Maximum Capacitive Load
OUTPUT (VSENSE < 20mV)(4)
%
±0.75
±2.2
±3.5
%
%
±0.002
1.5
%
RO
Ω
No Sustained Oscillation
–16V ≤ VCM < 0V
10
nF
mV
V
300
0V ≤ VCM ≤ VS, VS = 5V
VS < VCM ≤ 80V
0.4
300
mV
VOLTAGE OUTPUT(5)
Output Swing to the Positive Rail
Output Swing to GND(6)
FREQUENCY RESPONSE
Bandwidth
VIN– = 11V, VIN+ = 12V
VIN– = 0V, VIN+ = –0.5V
(V+) – 0.15
(V+) – 0.25
V
V
(VGND) + 0.004
(VGND) + 0.05
BW
SR
CLOAD = 5pF
CLOAD < 10nF
500
40
1
kHz
Degrees
V/ms
Phase Margin
Slew Rate
VSENSE = 10mVPP to 100mVPP
CLOAD = 5pF
,
Settling Time (1%)
2
ms
NOISE, RTI
Output Voltage Noise Density
40
nV/√Hz
(1) Offset is extrapolated from measurements of the output at 20mV and 100mV VSENSE
.
(2) Total output error includes effects of gain error and VOS
(3) Linearity is best fit to a straight line.
.
(4) For details on this region of operation, see the Accuracy Variations section in the Applications Information.
(5) See Typical Characteristic curve Positive Output Voltage Swing vs Output Current (Figure 8).
(6) Specified by design; not production tested.
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ELECTRICAL CHARACTERISTICS: COMPARATOR
Boldface limits apply over the specified temperature range: TA = –40°C to +125°C.
At TA = +25°C, VS = +12V, VCM = +12V, VSENSE = 100mV, RL = 10kΩ to GND, and RPULL-UP = 5.1kΩ each connected from
CMP1 OUT and CMP2 OUT to VS, unless otherwise noted.
COMPARATOR PARAMETERS
CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
Offset Voltage
Comparator Common-Mode Voltage = Threshold Voltage
2
mV
mV/°C
mV/°C
mV
Offset Voltage Drift, Comparator 1
Offset Voltage Drift, Comparator 2
Threshold
±2
+5.4
608
Rising Edge on Non-Inverting input, TA = +25°C
590
620
Over Temperature
586
625
mV
Hysteresis(1), CMP1
Hysteresis(1), CMP2
TA = –40°C to +85°C
TA = –40°C to +85°C
–8
8
mV
mV
INPUT BIAS CURRENT(2)
CMP1 IN+, CMP2 IN+
vs Temperature
0.005
10
10
nA
15
nA
INPUT IMPEDANCE
Pins 3 and 6 (14-pin packages only)
INPUT RANGE
kΩ
CMP1 IN+ and CMP2 IN+
Pins 3 and 6 (14-pin packages only)(3)
OUTPUT
0V to VS – 1.5V
0V to VS – 1.5V
V
V
Large-Signal Differential Voltage Gain
High-Level Output Current
Low-Level Output Voltage
RESPONSE TIME(4)
CMP VOUT 1V to 4V, RL ≥ 15kΩ Connected to 5V
VID = 0.4V, VOH = VS
200
0.0001
220
V/mV
mA
1
VID = –0.6V, IOL = 2.35mA
300
mV
Comparator 1
RL to 5V, CL = 15pF, 100mV Input Step with 5mV Overdrive
1.3
1.3
ms
ms
RL to 5V, CL = 15pF, 100mV Input Step with 5mV Overdrive,
CDELAY Pin Open
Comparator 2
RESET
RESET Threshold(5)
1.1
V
MΩ
ms
ms
mF
s
Logic Input Impedance
Minimum RESET Pulse Width
RESET Propagation Delay
Comparator 2 Delay Equation(6)
Comparator 2 Delay
2
1.5
3
CDELAY = tD/5
0.5
tD
CDELAY = 0.1mF
(1) Hysteresis refers to the threshold (the threshold specification applies to a rising edge of a noninverting input) of a falling edge on the
noninverting input of the comparator; refer to Figure 1.
(2) Specified by design; not production tested.
(3) See the Comparator Maximum Input Voltage Range section in the Applications Information.
(4) The comparator response time specified is the interval between the input step function and the instant when the output crosses 1.4V.
(5) The CMP1 RESET input has an internal 2MΩ (typical) pull-down. Leaving the CMP1 RESET open results in a LOW state, with
transparent comparator operation.
(6) The Comparator 2 delay applies to both rising and falling edges of the comparator output.
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SBOS539 –DECEMBER 2010
VTHRESHOLD
0.592 0.6
VTHRESHOLD
0.6 0.608
Input Voltage
Input Voltage
Hysteresis = VTHRESHOLD - 8mV
a) CMP1
Hysteresis = VTHRESHOLD - 8mV
b) CMP2
Figure 1. Comparator Hysteresis
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ELECTRICAL CHARACTERISTICS: REFERENCE
Boldface limits apply over the specified temperature range: TA = –40°C to +125°C.
At TA = +25°C, VS = +12V, VCM = +12V, VSENSE = 100mV, RL = 10kΩ to GND, and RPULL-UP = 5.1kΩ each connected from
CMP1 OUT and CMP2 OUT to VS, unless otherwise noted.
REFERENCE PARAMETERS
CONDITIONS
MIN
TYP
MAX
UNIT
REFERENCE VOLTAGE
1.2VREFOUT Output Voltage
Reference Drift(1)
1.188
1.2
40
1.212
100
V
dVOUT/dT
TA = –40°C to +85°C
ppm/°C
V
0.6VREF Output Voltage (Pins 3 and 6 of 14-pin packages only)
0.6
40
Reference Drift(1)
dVOUT/dT
TA = –40°C to +85°C
VREFOUT – 1.2V
100
2
ppm/°C
LOAD REGULATION
Sourcing
dVOUT/dILOAD
0mA < ISOURCE < 0.5mA
0mA < ISINK < 0.5mA
0.4
0.4
1
mV/mA
mV/mA
mA
Sinking
LOAD CURRENT
ILOAD
LINE REGULATION
CAPACITIVE LOAD
Reference Output Maximum Capacitive Load
OUTPUT IMPEDANCE
Pins 3 and 6 of 14-Pin Packages Only
dVOUT/dVS
2.7V < VS < 18V
30
mV/V
No Sustained Oscillations
10
10
nF
kΩ
(1) Specified by design; not production tested.
ELECTRICAL CHARACTERISTICS: GENERAL
Boldface limits apply over the specified temperature range: TA = –40°C to +125°C.
All specifications at TA = +25°C, VS = +12V, VCM = +12V, VSENSE = 100mV, RL = 10kΩ to GND, RPULL-UP = 5.1kΩ each
connected from CMP1 OUT and CMP2 OUT to VS, and CMP1 IN+ = 1V and CMP2 IN– = GND, unless otherwise noted.
GENERAL PARAMETERS
CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
Operating Power Supply
Quiescent Current
VS
+2.7
+18
2.2
2.8
V
mA
mA
V
IQ
VOUT = 2V
1.8
1.5
Over Temperature
Comparator Power-On Reset Threshold(1)
VSENSE = 0mV
TEMPERATURE
Specified Temperature Range
Operating Temperature Range
Storage Temperature Range
Thermal Resistance
–40
–55
–65
+125
+150
+150
°C
°C
°C
qJA
MSOP-10 Surface-Mount
SO-14, TSSOP-14 Surface-Mount
200
150
°C/W
°C/W
(1) The INA203, INA204, and INA205 are designed to power-up with the comparator in a defined reset state as long as CMP1 RESET is
open or grounded. The comparator will be in reset as long as the power supply is below the voltage shown here. The comparator
assumes a state based on the comparator input above this supply voltage. If CMP1 RESET is high at power-up, the comparator output
comes up high and requires a reset to assume a low state, if appropriate.
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SBOS539 –DECEMBER 2010
TYPICAL CHARACTERISTICS
All specifications at TA = +25°C, VS = +12V, VCM = +12V, and VSENSE = 100mV, unless otherwise noted.
GAIN vs FREQUENCY
GAIN vs FREQUENCY
45
40
35
30
25
20
15
10
5
45
40
35
30
25
20
15
10
5
CLOAD = 1000pF
G = 100
G = 50
G = 100
G = 50
G = 20
G = 20
CLOAD = 0
10k
100k
1M
10k
100k
1M
Frequency (Hz)
Figure 2.
Frequency (Hz)
Figure 3.
COMMON-MODE AND POWER-SUPPLY REJECTION
vs FREQUENCY
GAIN PLOT
20
18
16
14
12
10
8
140
130
120
110
100
90
100V/V
CMR
50V/V
PSR
80
20V/V
70
6
60
4
50
2
40
0
20 100 200 300 400 500 600 700 800 900
10
100
1k
10k
100k
VSENSE (mV)
Frequency (Hz)
Figure 4.
Figure 5.
TOTAL OUTPUT ERROR vs VSENSE
TOTAL OUTPUT ERROR vs COMMON-MODE VOLTAGE
4.0
0.1
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
50
100 150 200
250 300
350 400 450
500
-8 -4
0
16 20
...
76
80
-16 -12
4
8
12
VSENSE (mV)
Common-Mode Voltage (V)
Figure 6.
Figure 7.
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TYPICAL CHARACTERISTICS (continued)
All specifications at TA = +25°C, VS = +12V, VCM = +12V, and VSENSE = 100mV, unless otherwise noted.
POSITIVE OUTPUT VOLTAGE SWING
vs OUTPUT CURRENT
QUIESCENT CURRENT vs OUTPUT VOLTAGE
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
12
11
10
9
VS = 12V
Sourcing Current
+25°C
8
-40°C
+125°C
7
6
VS = 3V
5
Sourcing Current
4
-40°C
+25°C
Output stage is designed
to source current. Current
sinking capability is
3
2
approximately 400mA.
1
+125°C
0
5
10
20
25
0
15
30
1
2
0
3
4
5
6
7
8
9
10
Output Current (mA)
Output Voltage (V)
Figure 8.
Figure 9.
QUIESCENT CURRENT
vs COMMON-MODE VOLTAGE
OUTPUT SHORT-CIRCUIT CURRENT
vs SUPPLY VOLTAGE
2.00
1.75
1.50
1.25
1.00
0.75
0.50
34
30
26
22
18
14
10
6
VSENSE = 100mV
-40°C
+25°C
VS = 2.7V
VS = 12V
+125°C
VS = 12V
VS = 2.7V
VSENSE = 0mV
-8 -4
0
4
20 24 28 32
-16 -12
8
12 16
36
2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.5 11.5 17 18
VCM (V)
Supply Voltage (V)
Figure 10.
STEP RESPONSE
Figure 11.
STEP RESPONSE
G = 20
G = 20
VSENSE = 10mV to 20mV
Time (2ms/div)
VSENSE = 10mV to 100mV
Time (2ms/div)
Figure 12.
Figure 13.
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TYPICAL CHARACTERISTICS (continued)
All specifications at TA = +25°C, VS = +12V, VCM = +12V, and VSENSE = 100mV, unless otherwise noted.
STEP RESPONSE
STEP RESPONSE
G = 20
G = 50
G = 100
G = 50
VSENSE = 90mV to 100mV
VSENSE = 10mV to 20mV
Time (5ms/div)
Time (2ms/div)
Figure 14.
Figure 15.
STEP RESPONSE
STEP RESPONSE
G = 50
VSENSE = 10mV to 100mV
VSENSE = 90mV to 100mV
Time (5ms/div)
Time (5ms/div)
Figure 16.
Figure 17.
STEP RESPONSE
COMPARATOR VOL vs ISINK
600
500
400
300
200
100
0
VSENSE = 10mV to 100mV
Time (10ms/div)
0
1
2
3
4
5
6
ISINK (mA)
Figure 19.
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
All specifications at TA = +25°C, VS = +12V, VCM = +12V, and VSENSE = 100mV, unless otherwise noted.
COMPARATOR TRIP POINT vs SUPPLY VOLTAGE
COMPARATOR TRIP POINT vs TEMPERATURE
600
602
601
600
599
598
597
596
599
598
597
596
595
594
593
592
591
590
2
4
6
8
10
12
14
16
18
-50
-25
0
25
50
75
100
125
Supply Voltage (V)
Temperature (°C)
Figure 20.
Figure 21.
COMPARATOR 1 PROPAGATION DELAY
vs OVERDRIVE VOLTAGE
COMPARATOR 2 PROPAGATION DELAY
vs OVERDRIVE VOLTAGE
200
175
150
125
100
75
14
13
12
11
10
50
0
20
40
60
80 100 120 140 160 180 200
0
20
40
60
80 100 120 140 160 180 200
Overdrive Voltage (mV)
Overdrive Voltage (mV)
Figure 22.
Figure 23.
COMPARATOR RESET VOLTAGE vs
SUPPLY VOLTAGE
COMPARATOR 1 PROPAGATION DELAY vs
TEMPERATURE
1.2
1.0
0.8
0.6
0.4
0.2
0
300
275
250
225
200
175
150
125
2
4
6
8
10
12
14
16
18
-50
-25
0
25
50
75
100
125
Supply Voltage (V)
Temperature (°C)
Figure 24.
Figure 25.
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TYPICAL CHARACTERISTICS (continued)
All specifications at TA = +25°C, VS = +12V, VCM = +12V, and VSENSE = 100mV, unless otherwise noted.
COMPARATOR 2 PROPAGATION DELAY
vs CAPACITANCE
COMPARATOR 1 PROPAGATION DELAY
1000
100
10
Input
200mV/div
1
Output
2V/div
0.1
0.01
VOD = 5mV
2ms/div
0.001
0.01
0.1
1
10
100
Delay Capacitance (nF)
Figure 26.
Figure 27.
COMPARATOR 2 PROPAGATION DELAY
REFERENCE VOLTAGE vs TEMPERATURE
1.22
1.21
1.20
1.19
1.18
Input
200mV/div
Output
2V/div
VOD = 5mV
5ms/div
-50
-25
0
25
50
75
100
125
Temperature (°C)
Figure 28.
Figure 29.
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APPLICATIONS INFORMATION
BASIC CONNECTIONS
This section addresses the accuracy of these specific
operating regions:
Figure 30 shows the basic connections of the
INA203-Q1. The input pins, VIN+ and VIN–, should be
connected as closely as possible to the shunt resistor
to minimize any resistance in series with the shunt
resistance.
•
•
•
Normal Case 1: VSENSE ≥ 20mV, VCM ≥ VS
Normal Case 2: VSENSE ≥ 20mV, VCM < VS
Low VSENSE Case 1: VSENSE < 20mV, –16V ≤ VCM
< 0
Power-supply bypass capacitors are required for
stability. Applications with noisy or high-impedance
power supplies may require additional decoupling
capacitors to reject power-supply noise. Connect
bypass capacitors close to the device pins.
•
•
Low VSENSE Case 2: VSENSE < 20mV, 0V ≤ VCM
VS
Low VSENSE Case 3: VSENSE < 20mV, VS < VCM
80V
≤
≤
Normal Case 1: VSENSE ≥ 20mV, VCM ≥ VS
POWER SUPPLY
This region of operation provides the highest
accuracy. Here, the input offset voltage is
The input circuitry of the INA203-Q1 can accurately
measure beyond the power-supply voltage, V+. For
example, the V+ power supply can be 5V, whereas
the load power-supply voltage is up to +80V. The
output voltage range of the OUT terminal, however, is
limited by the voltages on the power-supply pin.
characterized and measured using
a
two-step
method. First, the gain is determined by Equation 1.
VOUT1 - VOUT2
G =
100mV - 20mV
(1)
ACCURACY VARIATIONS AS A RESULT OF
VSENSE AND COMMON-MODE VOLTAGE
where:
VOUT1 = Output Voltage with VSENSE = 100mV
VOUT2 = Output Voltage with VSENSE = 20mV
Then the offset voltage is measured at VSENSE
100mV and referred to the input (RTI) of the current
shunt monitor, as shown in Equation 2.
The accuracy of the INA203-Q1 current shunt
monitors is a function of two main variables: VSENSE
(VIN+ – VIN–) and common-mode voltage, VCM, relative
=
to the supply voltage, VS. VCM is expressed as (VIN+
+
VIN–)/2; however, in practice, VCM is seen as the
voltage at VIN+ because the voltage drop across
VSENSE is usually small.
VOUT1
VOSRTI (Referred-To-Input) =
- 100mV
G
(2)
RSHUNT
3mW
Load Supply
-18V to +80V
Load
5V Supply
VS
VIN+
VIN-
INA203
RPULL-UP
4.7kW
RPULL-UP
4.7kW
x20
OUT
Current Shunt
Monitor Output
1.2V REF
CMP1 IN-/0.6 REF
1.2V REF OUT
CMP1 OUT
CMP1 IN+
CBYPASS
CMP2 IN+
CMP2 OUT
0.01mF
CMP2 IN-/0.6 REF
CMP2 DELAY
Optional Delay
Capacitor
0.2mF
GND
CMP1 RESET
Transparent/Reset
Latch
Figure 30. INA20x Basic Connection
12
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Low VSENSE Case 2: VSENSE < 20mV, 0V ≤ VCM ≤ VS
In the Typical Characteristics, the Output Error vs
Common-Mode Voltage curve (Figure 7) shows the
highest accuracy for this region of operation. In this
plot, VS = 12V; for VCM ≥ 12V, the output error is at its
minimum. This case is also used to create the
VSENSE ≥ 20mV output specifications in the Electrical
Characteristics table.
This region of operation is the least accurate for the
INA203-Q1. To achieve the wide input common-mode
voltage range, these devices use two op amp front
ends in parallel. One op amp front end operates in
the positive input common-mode voltage range, and
the other in the negative input region. For this case,
neither of these two internal amplifiers dominates and
overall loop gain is very low. Within this region, VOUT
approaches voltages close to linear operation levels
for Normal Case 2. This deviation from linear
operation becomes greatest the closer VSENSE
approaches 0V. Within this region, as VSENSE
approaches 20mV, device operation is closer to that
described by Normal Case 2. Figure 32 illustrates this
behavior. The VOUT maximum peak for this case is
Normal Case 2: VSENSE ≥ 20mV, VCM < VS
This region of operation has slightly less accuracy
than Normal Case 1 as a result of the common-mode
operating area in which the part functions, as seen in
the Output Error vs Common-Mode Voltage curve
(Figure 7). As noted, for this graph VS = 12V; for VCM
< 12V, the Output Error increases as VCM becomes
less than 12V, with a typical maximum error of
0.005% at the most negative VCM = –16V.
tested by maintaining a constant VS, setting VSENSE
=
0mV, and sweeping VCM from 0V to VS. The exact
VCM at which VOUT peaks during this test varies from
part to part, but the VOUT maximum peak is tested to
be less than the specified VOUT Tested Limit.
Low VSENSE Case 1:
VSENSE < 20mV, –16V ≤ VCM < 0; and
Low
VSENSE
Case
3:
VSENSE < 20mV, VS < VCM ≤ 80V
2.4
(1)
VOUT Tested Limit
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
Although the INA203-Q1 is not designed for accurate
operation in either of these regions, some
applications are exposed to these conditions; for
example, when monitoring power supplies that are
switched on and off while VS is still applied to the
INA203-Q1. It is important to know what the behavior
of the devices will be in these regions.
VCM1
Ideal
VCM2
VCM3
VOUT Tested Limit at
VCM4
VSENSE = 0mV, 0 £ VCM1 £ VS
.
As VSENSE approaches 0mV, in these VCM regions,
VCM2, VCM3, and VCM4 illustrate the variance
from part to part of the VCM that can cause
maximum VOUT with VSENSE < 20mV.
the
device
output
accuracy
degrades.
A
larger-than-normal offset can appear at the current
shunt monitor output with a typical maximum value of
VOUT = 300mV for VSENSE = 0mV. As VSENSE
approaches 20mV, VOUT returns to the expected
output value with accuracy as specified in the
Electrical Characteristics. Figure 31 illustrates this
effect (Gain = 100).
0
2
4
6
8
10 12 14 16 18 20 22 24
VSENSE (mV)
NOTE: (1) INA203-Q1 VOUT Tested Limit = 0.4V.
Figure 32. Example for Low VSENSE Case 2 (Gain
= 100)
2.0
1.8
1.6
1.4
SELECTING RSHUNT
The value chosen for the shunt resistor, RSHUNT
,
1.2
depends on the application and is a compromise
between small-signal accuracy and maximum
permissible voltage loss in the measurement line.
High values of RSHUNT provide better accuracy at
lower currents by minimizing the effects of offset,
while low values of RSHUNT minimize voltage loss in
the supply line. For most applications, best
performance is attained with an RSHUNT value that
provides a full-scale shunt voltage range of 50mV to
100mV. Maximum input voltage for accurate
measurements is (VSHUNT – 0.25)/Gain.
Actual
1.0
0.8
Ideal
0.6
0.4
0.2
0
0
2
4
6
8
10
12
14
16
18
20
VSENSE (mV)
Figure 31. Example for Low VSENSE Cases 1 and 3
(Gain = 100)
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TRANSIENT PROTECTION
OUTPUT VOLTAGE RANGE
The –16V to +80V common-mode range of the
INA203-Q1 is ideal for withstanding automotive fault
conditions ranging from 12V battery reversal up to
+80V transients, since no additional protective
components are needed up to those levels. In the
event that the INA203-Q1 is exposed to transients on
the inputs in excess of their ratings, then external
transient absorption with semiconductor transient
absorbers (zeners or Transzorbs) are necessary. Use
of metal oxide varistors (MOVs) or video disk
recorders (VDRs) is not recommended except when
they are used in addition to a semiconductor transient
absorber. Select the transient absorber such that it
will never allow the INA203-Q1 to be exposed to
transients greater than +80V (that is, allow for
transient absorber tolerance, as well as additional
voltage because of transient absorber dynamic
impedance). Despite the use of internal zener-type
ESD protection, the INA203-Q1 does not lend itself to
using external resistors in series with the inputs
because the internal gain resistors can vary up to
±30% but are closely matched. (If gain accuracy is
not important, then resistors can be added in series
with the INA203-Q1 inputs with two equal resistors on
each input.)
The output of the INA203-Q1 is accurate within the
output voltage swing range set by the power-supply
pin, V+. This performance is best illustrated when
using a gain of 100 , where a 100mV full-scale input
from the shunt resistor requires an output voltage
swing of +10V, and a power-supply voltage sufficient
to achieve +10V on the output.
INPUT FILTERING
An obvious and straightforward location for filtering is
at the output of the INA203-Q1 series; however, this
location negates the advantage of the low output
impedance of the internal buffer. The only other
option for filtering is at the input pins of the
INA203-Q1, which is complicated by the internal 5kΩ
+
30% input impedance; this configuration is
illustrated in Figure 33. Using the lowest possible
resistor values minimizes both the initial shift in gain
and effects of tolerance. The effect on initial gain is
given by Equation 3:
5kW
Gain Error % = 100 - 100 ´
5kW + RFILT
(3)
Total effect on gain error can be calculated by
replacing the 5kΩ term with 5kΩ – 30%, (or 3.5kΩ) or
5kΩ + 30% (or 6.5kΩ). The tolerance extremes of
RFILT can also be inserted into the equation. If a pair
of 100Ω 1% resistors are used on the inputs, the
initial gain error will be 1.96%. Worst-case tolerance
conditions will always occur at the lower excursion of
the internal 5kΩ resistor (3.5kΩ), and the higher
excursion of RFILT – 3% in this case.
RSHUNT << RFILTER
3mW
VSUPPLY
Load
RFILTER < 100W
RFILTER <100W
CFILTER
VIN+
VS
OUT
1
2
3
4
5
6
7
14
13
12
11
10
9
VIN-
1.2V REF
1.2V REF OUT
CMP1 OUT
CMP1 IN-/0.6V REF
CMP1 IN+
f
-3dB
CMP2 OUT
CMP2 IN+
1
f
=
-3dB
CMP2 DELAY
CMP1 RESET
2p(2RFILTER)CFILTER
CMP2 IN-/0.6V REF
GND
8
Figure 33. Input Filter (Gain Error: 1.5% to –2.2%)
14
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SBOS539 –DECEMBER 2010
Note that the specified accuracy of the INA203-Q1
must then be combined in addition to these
tolerances. While this discussion treated accuracy
worst-case conditions by combining the extremes of
the resistor values, it is appropriate to use geometric
mean or root sum square calculations to total the
effects of accuracy variations.
additional features for comparator functions. The
comparator reference voltage of both Comparator 1
and Comparator 2 can be overridden by external
inputs for increased design flexibility. Comparator 2
has a programmable delay.
COMPARATOR DELAY (14-Pin Version Only)
The Comparator 2 programmable delay is controlled
by a capacitor connected to the CMP2 Delay Pin; see
Figure 30. The capacitor value (in mF) is selected by
using Equation 4:
REFERENCE
The INA203-Q1 include an internal voltage reference
that has a load regulation of 0.4mV/mA (typical), and
not more than 100ppm/°C of drift. Only the 14-pin
package allows external access to reference
voltages, where voltages of 1.2V and 0.6V are both
available. Output current versus output voltage is
illustrated in the Typical Characteristics section.
tD
CDELAY (in mF) =
5
(4)
A
simplified version of the delay circuit for
Comparator 2 is shown in Figure 34. The delay
comparator consists of two comparator stages with
the delay between them. Note that I1 and I2 cannot
be turned on simultaneously; I1 corresponds to a U1
low output and I2 corresponds to a U1 high output.
Using an initial assumption that the U1 output is low,
I1 is on, then U2 +IN is zero. If U1 goes high, I2
supplies 120nA to CDELAY. The voltage at U2 +IN
begins to ramp toward a 0.6V threshold. When the
voltage crosses this threshold, the U2 output goes
high while the voltage at U2 +IN continues to ramp up
to a maximum of 1.2V when given sufficient time
(twice the value of the delay specified for CDELAY).
This entire sequence is reversed when the
comparator outputs go low, so that returning to low
exhibits the same delay.
COMPARATOR
The INA203-Q1 incorporates two open-drain
comparators. These comparators typically have 2mV
of offset and a 1.3ms (typical) response time. The
output of Comparator 1 latches and is reset through
the CMP1 RESET pin, as shown in Figure 35. This
configuration applies to both the 10- and 14-pin
versions. Figure 34 illustrates the comparator delay.
The 14-pin versions of the INA203-Q1 include
1.2V
I2
120nA
U1
U2
I1
120nA
0.6V
CDELAY
Figure 34. Simplified Model of the Comparator 2 Delay Circuit
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0.6V
VIN
0V
CMP Out
RESET
Figure 35. Comparator Latching Capability
It is important to note what will happen if events occur
more rapidly than the delay timeout; for example,
when the U1 output goes high (turning on I2), but
returns low (turning I1 back on) prior to reaching the
0.6V transition for U2. The voltage at U2 +IN ramps
back down at a rate determined by the value of
CDELAY, and only returns to zero if given sufficient
time.
whether either or both inputs are subject to the large
voltage. When making this determination, consider
the 20kΩ from each input back to the comparator.
Figure 37 shows the maximum input voltage that
avoids creating a reference error when driving both
inputs (an equivalent resistance back into the
reference of 10kΩ).
£ 1mA
In essence, when analyzing Comparator
2 for
1.2V
behavior with events more rapid than its delay
setting, use the model shown in Figure 34.
20kW
20kW
CMP1 IN-
COMPARATOR MAXIMUM INPUT VOLTAGE
RANGE
CMP2 IN+
The maximum voltage at the comparator input for
normal operation is up to (V+) – 1.5V. There are
special considerations when overdriving the reference
inputs (pins 3 and 6). Driving either or both inputs
high enough to drive 1mA back into the reference
introduces errors into the reference. Figure 36 shows
the basic input structure. A general guideline is to
limit the voltage on both inputs to a total of 20V. The
exact limit depends on the available voltage and
Figure 36. Limit Current Into Reference ≤ 1mA
RSHUNT
3mW
Load Supply
Load
-18V to +80V
5V Supply
VS
VIN+
INA203-Q1
x20
RPULL-UP
RPULL-UP
4.7kW
VIN-
OUT
4.7kW
Current Shunt Monitor Output
V < 11.2
1.2V REF
CMP1 IN-/0.6 REF
1.2V REF OUT
CMP1 OUT
CMP1 IN+
CBYPASS
0.01mF
CMP2 IN+
CMP2 OUT
CMP2 IN-
CMP2 DELAY
Optional Delay
Capacitor
0.2mF
GND
CMP1 RESET
Transparent/Reset
Latch
Figure 37. Overdriving Comparator Inputs Without Generating a Reference Error
16
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INA203-Q1
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SBOS539 –DECEMBER 2010
Raychem
Polyswitch
Load
< 18V
+5V Supply
Battery
3.3kW
Pull-Up
VS+
VIN+
VIN-
INA203-Q1
1.2V REF
x20
OUT
Resistors
CMP1 IN-
1.2V REF OUT
CMP1 OUT
CMP1 IN+
Overlimit(1)
Warning(1)
CMP2 IN+
CMP2 OUT
CMP2 IN-
CMP2 DELAY
GND
CMP1 RESET
CBYPASS
0.01mF
Reset
Latch
Optional
CDELAY
0.01mF
NOTE: (1) Warning at half current (with optional delay). Overlimit latches when Polyswitch opens.
Figure 38. Polyswitch Warning and Fault Detection Circuit
RSHUNT
0.02W
Load
Q2
NDS8434A
R1
100kW
+5V Supply
R7
1kW
Q1
2N3904
VS+
VIN+
VIN-
INA203-Q1
x20
OUT
R2
1kW
1.2V REF
CMP1 IN-
1.2V REF OUT
CMP1 OUT
R5
R3
CMP1 IN+
100kW
14kW
CMP2 IN+
CMP2 OUT
CMP2 IN-
CMP2 DELAY
R6
R4
GND
CMP1 RESET
Reset
6.04kW
6.04kW
CBYPASS
0.01mF
Latch
Figure 39. Lead-Acid Battery Protection Circuit
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Jan-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
INA203AQPWRQ1
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Purchase Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF INA203-Q1 :
Catalog: INA203
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
INA203AQPWRQ1
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP PW 14
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
INA203AQPWRQ1
2000
Pack Materials-Page 2
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