INA2126UA/2K5 [TI]
双路 36V 微功耗 (175µA)、250µV 失调电压、精密仪表放大器 | D | 16 | -40 to 85;
| 型号： | INA2126UA/2K5 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 双路 36V 微功耗 (175µA)、250µV 失调电压、精密仪表放大器 | D | 16 | -40 to 85 放大器 仪表 光电二极管 仪表放大器 |
| 文件： | 总37页 (文件大小：2285K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INA126, INA2126
ZHCSO32C –SEPTEMBER 2000 –REVISED JANUARY 2022
INAx126 MicroPower 仪表放大器
1 特性
3 说明
• 低静态电流：175 μA/channel
• 宽电源电压范围：±1.35V 至±18 V
• 低失调电压：250µA（最大值）
• 低温漂：3μV/°C（最大值）
• 低噪声：35nV/√Hz
• 低输入偏置电流：25nA（最大值）
• 温度范围：–40°C 至+85°C
• 多种封装选项：
INA126 和 INA2126 (INAx126) 是用于精确、低噪声、
差分信号采集的精密仪表放大器。这些器件均采用双运
算放大器设计，具有低静态电流（175μA/通道），可
提供出色的瞬态性能。由于这些特性再加上 ±1.35V 至
±18V 的宽工作电压范围，因此INAx126 非常适合便携
式仪表和数据采集系统。
可通过单个外部电阻器在 5V/V 到 10000V/V 范围内设
置增益。精密输入电路提供低失调电压（250μV，最
大值）、低失调电压漂移（3μV/°C，最大值）和出色
的共模抑制。
– 单通道：
• INA126P/PA 8 引脚PDIP (P)
• INA126U/UA 8 引脚SOIC (D)
• INA126E/EA 8 引脚VSSOP (DGK)
– 双通道：
所有版本的额定工作温度范围均为 –40°C 至 +85°C
工业温度范围。
器件信息
封装(1)
• INA2126P/PA 16 引脚PDIP (N)
• INA2126U/UA 16 引脚SOIC (D)
• INA2126E/EA 16 引脚SSOP (DBQ)
封装尺寸（标称值）
6.35mm × 9.81mm
3.91mm × 4.90mm
3.00mm × 3.00mm
6.35mm × 19.30mm
3.91mm × 9.90mm
3.90mm x 4.90mm
器件型号
PDIP (8)
INA126
SOIC (8)
2 应用
VSSOP (8)
PDIP (16)
SOIC (16)
SSOP (16)
• 液位变送器
• 流量变送器
• 多参数患者监护仪
• 混合模块（AI、AO、DI、DO）
• 交流充电（桩）站
• 输液泵
INA2126
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 心电图(ECG)
V+
V+
INA2126
7
9
2
3
+
VIN
INA126
6
7
+
–
3
8
+
V
O = (VIN – VIN) G
VIN
6
+
–
VO = (VIN – VIN) G
80kΩ
G = 5 +
RG
40kΩ
80kΩ
40kΩ
10kΩ
G = 5 +
10kΩ
RG
RG
10kΩ
RG
4
1
10kΩ
40kΩ
–
VIN
1
2
5
15
14
–
+
VIN
VIN
11
+
–
40kΩ
V
O = (VIN – VIN) G
5
40kΩ
80kΩ
G = 5 +
RG
4
10kΩ
10
V–
RG
简化版原理图：INA126
13
10kΩ
40kΩ
–
16
8
VIN
12
V–
简化版原理图：INA2126
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS062
INA126, INA2126
ZHCSO32C –SEPTEMBER 2000 –REVISED JANUARY 2022
www.ti.com.cn
Table of Contents
8 Application and Implementation..................................13
8.1 Application Information............................................. 13
8.2 Typical Application.................................................... 13
9 Power Supply Recommendations................................17
9.1 Low-Voltage Operation............................................. 17
10 Layout...........................................................................18
10.1 Layout Guidelines................................................... 18
10.2 Layout Example...................................................... 19
11 Device and Documentation Support..........................20
11.1 Device Support........................................................20
11.2 接收文档更新通知................................................... 20
11.3 支持资源..................................................................20
11.4 Trademarks............................................................. 20
11.5 Electrostatic Discharge Caution..............................20
11.6 术语表..................................................................... 20
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings .............................................................. 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information: INA126......................................6
6.5 Thermal Information: INA2126....................................6
6.6 Electrical Characteristics.............................................7
6.7 Typical Characteristics................................................9
7 Detailed Description......................................................12
7.1 Overview...................................................................12
7.2 Functional Block Diagram.........................................12
7.3 Feature Description...................................................12
7.4 Device Functional Modes..........................................12
Information.................................................................... 20
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision B (December 2015) to Revision C (December 2021)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• Added dual supply specification to Absolute Maximum Ratings ........................................................................5
• Deleted redundant operating temperature and input common mode voltage specifications in Recommended
Operating Conditions .........................................................................................................................................5
• Added dual supply and specified temperature specifications in Recommended Operating Conditions ............5
• Added proper signs for PSRR and input bias current specifications in Electrical Characteristics .....................7
• Deleted VO = 0 V test condition of common-mode voltage specification in Electrical Characteristics ...............7
• Changed common-mode voltage specification from ±11.25 V minimum, to –11.25 V minimum and 11.25 V
maximum, in Electrical Characteristics ..............................................................................................................7
• Changed minimum CMRR specification for INA126U/E, INA2126E from 83 dB to 80 dB in Electrical
Characteristics ...................................................................................................................................................7
• Added typical input bias current specification of ±10 nA for INA126PA/UA/EA and INA2126PA/UA/EA in
Electrical Characteristics ................................................................................................................................... 7
• Changed current noise specifications in Electrical Characteristics from 60 fA/√Hz to 160 fA/√Hz for f = 1
kHz, and from 2 pApp to 7.3 pApp for f = 0.1 Hz to 10 Hz..................................................................................7
• Changed test condition for short-circuit current specification in Electrical Characteristics from "Short circuit to
ground" to "Continuous to VS / 2" for clarity........................................................................................................7
• Changed short-circuit current specification in Electrical Characteristics from +10/-5 mA to ±5 mA................... 7
• Deleted redundant voltage range, operating temperature range, and specification temperature range
specifications from Electrical Characteristics .....................................................................................................7
• Changed Figures 6-7, 6-10, 6-13, 6-14, 6-15, 6-16, 6-17 ..................................................................................9
• Added Figure 6-11.............................................................................................................................................. 9
Changes from Revision A (August 2005) to Revision B (December 2015)
Page
• 添加了ESD 等级表、特性说明部分、器件功能模式、应用和实施部分、电源相关建议部分、布局部分、器
件和文档支持部分以及机械、封装和可订购信息部分.......................................................................................1
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5 Pin Configuration and Functions
RG
1
2
3
4
8
7
6
5
RG
V+
VO
Ref
V–
V+
IN
IN
V–
图5-1. INA126: P (8-Pin PDIP), D (8-Pin SOIC), and DGK (8-Pin VSSOP) Packages, Top View
表5-1. Pin Functions: INA126
PIN
I/O
DESCRIPTION
NO.
1, 8
2
NAME
RG
Gain setting pin. For gains greater than 5 place a gain resistor between pin 1 and pin 8.
—
I
I
Negative input
V–IN
V+IN
V–
Ref
3
Positive input
4
Negative supply
—
I
5
Reference input. This pin must be driven by a low impedance or connected to ground.
6
VO
O
Output
7
V+
Positive supply
—
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VI–NA
VI+NA
1
2
3
4
5
6
7
8
16 VI–NB
15 VI+NB
14 RGB
13 RGB
RGA
RGA
12
11
RefB
VOB
RefA
VOA
SenseA
V–
10 SenseB
V+
9
图5-2. INA2126: N (16-Pin PDIP), D (16-Pin SOIC), and DBQ (16-Pin SSOP) Packages, Top View
表5-2. Pin Functions: INA2126
PIN
I/O
DESCRIPTION
NO.
1
NAME
V–INA
V+INA
I
I
Negative input for amplifier A
Positive input for amplifier A
2
Gain setting pin for amplifier A. For gains greater than 5 place a gain resistor between pin 3 and
pin 4.
3, 4
5
RGA
—
Reference input for amplifier A. This pin must be driven by a low impedance or connected to
ground.
RefA
I
6
VOA
SenseA
V–
O
I
Output of amplifier A
7
Feedback for amplifier A. Connect to VOA, amplifier A output.
Negative supply
8
—
9
V+
Positive supply
—
I
10
11
SenseB
VOB
Feedback for amplifier B. Connect to VOB, amplifier B output.
Output of amplifier B
O
Reference input for amplifier B. This pin must be driven by a low impedance or connected to
ground.
12
RefB
RGB
I
Gain setting pin for amplifier B. For gains greater than 5 place a gain resistor between pin 13 and
pin 14.
13, 14
—
15
16
V+INB
I
I
Positive input for amplifier B
Negative input for amplifier B
V–INB
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
±18
UNIT
Supply voltage dual supply, VS = (V+) –(V–)
VS
V
36
Supply voltage single supply, VS = (V+) –(V–)
Input signal voltage(2)
Input signal current(2)
Output short-circuit(3)
(V+) + 0.7
10
V
(V–) –0.7
mA
Continuous
TA
Operating Temperature
125
300
125
°C
°C
°C
–55
Lead temperature (soldering, 10 s)
Storage Temperature
Tstg
–55
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) Input signal voltage is limited by internal diodes connected to power supplies. See Input Protection.
(3) Short-circuit to VS / 2.
6.2 ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±500
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.7
TYP
30
MAX
36
UNIT
Single-supply
Dual-supply
VS
TA
Supply voltage
V
±1.35
–40
±15
±18
85
Specified temperature
°C
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6.4 Thermal Information: INA126
INA126
SOIC
8 PINS
116.4
62.4
THERMAL METRIC(1)
PDIP
8 PINS
52.2
VSSOP
8 PINS
167.8
60.9
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
41.6
29.4
57.7
88.9
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
18.9
10.0
7.3
ψJT
29.2
57.1
87.3
ψJB
RθJC(bot)
N/A
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Thermal Information: INA2126
INA2126
THERMAL METRIC(1)
PDIP
16 PINS
39.3
SOIC
16 PINS
76.2
SSOP
16 PINS
115.8
67.0
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
26.2
37.8
20.1
33.5
58.3
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
10.7
7.5
19.9
ψJT
19.9
33.3
57.9
ψJB
RθJC(bot)
N/A
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.6 Electrical Characteristics
at TA = 25°C, VS = ±15 V, RL = 25 kΩ, VREF = 0 V, and VCM = VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT
INA126P/U/E
INA2126P/U/E
±100
±150
±0.5
±0.5
±5
±250
±500
±3
VOS
Offset voltage (RTI)
µV
INA126PA/UA/EA
INA2126PA/UA/EA
INA126P/U/E
INA2126P/U/E
Offset voltage drift (RTI)
µV/°C
uV/V
TA = –40°C to +85°C
INA126PA/UA/EA
INA2126PA/UA/EA
±5
INA126P/U/E
INA2126P/U/E
±15
±50
Power-supply rejection ratio
(RTI)
PSRR
VS = ±1.35 V to ±18 V
INA126PA/UA/EA
INA2126PA/UA/EA
±5
Input impedance
Safe input voltage
1 || 4
GΩ || pF
(V+) + 0.5
(V+) + 10
11.25
RS = 0 Ω
(V–) –0.5
(V–) –10
–11.25
V
RS = 1 kΩ
VCM
Common-mode voltage(1)
Channel seperation (dual)
±11.5
130
V
G = 5, dc
dB
INA126P
INA2126P
83
80
74
94
94
83
INA126U/E
INA2126U/E
CMRR
Common-mode rejection ratio
dB
RS = 0 Ω, VCM = ±11.25 V
INA126PA/UA/EA
INA2126PA/UA/EA
INPUT BIAS CURRENT
INA126P/U/E
INA2126P/U/E
±10
±25
±50
IB
Input bias current
nA
INA126PA/UA/EA
INA2126PA/UA/EA
±10
±30
Input bias current drift
Input offset current
TA = –40°C to +85°C
pA/℃
INA126P/U/E
INA2126P/U/E
±0.5
±2
±5
nA
IOS
INA126PA/UA/EA
INA2126PA/UA/EA
±0.5
±10
nA
Input offset current drift
TA = –40°C to +85°C
pA/℃
GAIN
Gain equation
Gain
V/V
V/V
5 + (80 kΩ / RG)
G
5
10000
±0.1
INA126P/U/E
INA2126P/U/E
±0.02
±0.02
±0.2
G = 5 , VO = ±14 V
INA126PA/UA/EA
INA2126PA/UA/EA
±0.18
±0.5
±1
GE
Gain error
%
INA126P/U/E
INA2126P/U/E
G = 100, VO = ±12 V
INA126PA/UA/EA
INA2126PA/UA/EA
±0.2
G = 5
±2
±25
±10
±100
Gain drift(2)
ppm/°C
%
TA = –40°C to +85°C
G = 100
Gain nonlinearity
G = 100, VO = ±14 V
±0.002
±0.012
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6.6 Electrical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 25 kΩ, VREF = 0 V, and VCM = VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
NOISE
f = 1 kHz
35
35
f = 100 Hz
nV/√Hz
eN
Voltage noise
fB = 10 Hz
45
fB = 0.1 Hz to 10 Hz
f = 1 kHz
0.7
160
7.3
µVPP
fA/√Hz
pAPP
In
Current noise
fB = 0.1Hz to 10Hz
OUTPUT
(V+) –
0.75
Positive output voltage swing
V
(V+) –0.9
Negative output voltage swing
Short-circuit current
V
(V–) + 0.95 (V–) + 0.8
ISC
CL
Continuous to VS / 2
Stable operation
±5
mA
pF
Load capacitance
1000
FREQUENCY RESPONSE
G = 5
200
9
BW
SR
tS
G = 100
kHz
V/µs
µs
Bandwidth, –3 dB
Slew rate
G = 500
1.8
0.4
30
G = 5, VO = ±10 V
G = 5
Settling time
To 0.01%, VSTEP = 10 V
50% input overload
G = 100
G = 500
160
1500
4
Overload recovery
µs
POWER SUPPLY
Quiescent current (per
IQ
IO = 0 mA
±175
±200
µA
channel)
(1) Input voltage range of the instrumentation amplifier input stage. The input range depends on the common-mode voltage, differential
voltage, gain, and reference voltage. See Typical Characteristic curves.
(2) The values specified for G > 5 do not include the effects of the external gain-setting resistor, RG.
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6.7 Typical Characteristics
at TA = 25°C, VS = ±15 V (unless otherwise noted)
70
110
100
90
80
70
60
50
40
30
20
10
0
G = 1000
60
50
G = 100
40
G = 1000
G = 100
G = 5
30
20
10
0
G = 20
G = 5
–10
100
1k
10k
Frequency (Hz)
100k
1M
10
100
1k
10k
100k
1M
Frequency (Hz)
图6-1. Gain vs Frequency
图6-2. Common-Mode Rejection vs Frequency
120
100
80
60
40
20
0
120
G = 1000
100
80
60
40
20
0
G = 100
G = 1000
G = 100
G = 5
G = 5
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
Frequency (Hz)
Frequency (Hz)
图6-3. Positive Power Supply Rejection vs Frequency
图6-4. Negative Power Supply Rejection vs Frequency
15
5
4
3
10
VS
=
5V
2
1
5
VS = +5V/0V
VREF = 2.5V
+15V
+
VD/2
–
VO
0
–5
+
0
VD/2
Ref
–
+
–1
–2
–3
–4
–5
VCM
–15V
–10
–15
–15
–10
–5
0
5
10
15
–5
–4 –3
–2
–1
0
1
2
3
4
5
Output Voltage (V)
Output Voltage (V)
VS = ±15 V
VS = ±5 V
图6-5. Input Common-Mode Voltage Range
图6-6. Input Common-Mode Voltage Range
vs Output Voltage
vs Output Voltage
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V (unless otherwise noted)
100
1000
1000
100
10
Voltage Noise
Current Noise
80
70
60
800
700
600
0.01%
50
40
500
0.1%
400
300
30
20
200
10
100
1
10
100
1k
1
10
100
1k
10k
Frequency (Hz)
Gain (V/V)
图6-7. Input-Referred Noise vs Frequency
图6-8. Settling Time vs Gain
250
200
150
100
50
10
8
6
4
2
(Noise)
0
–2
–4
–6
–8
–10
Vs = 1.35 V
Vs = 15 V
Vs = 18 V
0
-75
0
1
2
3
4
5
6
7
8
9
10
-50
-25
0
25
50
75
100 125 150
Time After Turn-On (ms)
Temperature (ꢀC)
图6-10. Quiescent Current vs Temperature
图6-9. Input-Referred Offset Voltage WarmUp
1.2
1
1
Rising, Unit 1
Rising, Unit 2
Falling, Unit 1
Falling, Unit 2
0.8
0.6
0.4
0.2
0
0.1
RL = 10kΩ
0.01
0.001
-0.2
-0.4
-0.6
-0.8
RL = 100kΩ
G = 5
10
100
1k
10k
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (ꢀC)
Frequency (Hz)
图6-11. Slew Rate vs Temperature
图6-12. Total Harmonic Distortion + Noise vs Frequency
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V (unless otherwise noted)
15
-12.5
-13
40
30
Sourcing, Unit 1
Sourcing, Unit 2
Sinking, Unit 1
14.5
Sinking, Unit 2
20
10
14
-13.5
-14
0
13.5
13
-10
-20
-30
-40
-14.5
-15
12.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
0
40
80
120
Time (ꢀs)
160
200
240
280
Output Current (mA)
G = 5
图6-14. Small-Signal Response
图6-13. Output Voltage Swing vs Output Current
40
15
10
5
30
20
10
0
0
-10
-20
-30
-40
-5
-10
-15
0
40
80
120
160
200
240
280
0
40
80
120
160
200
240
280
Time (ꢀs)
Time (ꢀs)
G = 100
G = 5
图6-15. Small-Signal Response
图6-16. Large-Signal Response
1
160
150
140
130
120
110
100
90
G = 1000
0.5
0
G = 100
G = 5
RL = 25kΩ
Measurement limited
by amplifier or
measurement noise.
80
-0.5
-1
70
60
100
1k
10k
100k
1M
Time (1 s/div)
Frequency (Hz)
图6-17. 0.1-Hz to 10-Hz Voltage Noise
图6-18. Channel Separation vs Frequency, RTI (Dual Version)
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7 Detailed Description
7.1 Overview
The INAx126 use only two, rather than three, operational amplifiers, providing savings in power consumption. In
addition, the input resistance is high and balanced, thus permitting the signal source to have an unbalanced
output impedance.
A minimum circuit gain of 5 permits an adequate dc common-mode input range, as well as sufficient bandwidth
for most applications.
7.2 Functional Block Diagram
RG (Optional)
REF
OUT
–IN
+
+
+IN
7.3 Feature Description
The INAx126 are low-power, general-purpose instrumentation amplifiers offering excellent accuracy. The
versatile two-operational-amplifier design and small size make the amplifiers an excellent choice for a wide
range of applications. The two-op-amp topology reduces power consumption. A single external resistor sets any
gain from 5 to 10,000. These devices operate with power supplies as low as ±1.35 V, and a quiescent current of
200 μA maximum.
7.4 Device Functional Modes
7.4.1 Single-Supply Operation
The INAx126 can be used on single power supplies from 2.7 V to 36 V. Use the output REF pin to level shift the
internal output voltage into a linear operating condition. Ideally, connect the REF pin to a potential that is
midsupply to avoid saturating the output of the amplifiers. See 节 8.1 for information on how to adequately drive
the reference pin.
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The INAx126 measures small differential voltage with high common-mode voltage developed between the
noninverting and inverting input. The high input impedance make the INAx126 an excellent choice for a wide
range of applications. The INAx126 can adjust the functionality of the output signals by setting the reference pin,
giving additional flexibility that is practical for multiple configurations.
8.2 Typical Application
图 8-1 shows the basic connections required for operation of the INA126. Applications with noisy or high
impedance power supplies may require decoupling capacitors close to the device pins as shown.
The output is referred to the output reference (Ref) pin, which is normally grounded. This connection must be
low-impedance to maintain good common-mode rejection. A resistance of 8 Ω in series with the Ref pin causes
a typical device to degrade to approximately 80-dB CMR.
图 8-4 depicts a desired differential signal from a sensor at 1 kHz and 5 mVPP superimposed on top of a 1-VPP
,
60-Hz common-mode signal (the 1-kHz signal can not be resolved in this scope trace). The FFT trace in 图 8-5
shows the two signals. 图 8-6 shows the clearly recovered differential signal at the output of the INA126
operating at a gain of 250. The FFT of 图8-7 shows the 60-Hz common-mode is no longer visible.
The dual version INA2126 has feedback-sense connections, SenseA and SenseB, that must be connected to the
respective output pins for proper operation. The sense connection can sense the output voltage directly at the
load for best accuracy.
V+
0.1µF
Pin numbers are
for single version
DESIRED GAIN
(V/V)
RG
NEAREST 1%
RG VALUE
7
(Ω)
INA126
3
8
+
5
10
NC
16k
NC
15.8k
5360
1780
845
VIN
6
A1
80kΩ
RG
20
5333
1779
842
410
162
80.4
40.1
16.0
8.0
G = 5 +
50
40kΩ
+
–
!
100
200
500
1000
2000
5000
10000
VO = (VIN – VIN) G
412
10kΩ
162
+
RG
80.6
40.2
15.8
7.87
10kΩ
Load
VO
–
1
2
NC: No Connection.
A2
–
VIN
40kΩ
0.1µF
5
Also drawn in simplified form:
Ref
+
VIN
4
VO
INA126
RG
!
–
VIN
V–
Ref
!Dual version has
external sense connection.
图8-1. Basic Connections
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8.2.1 Design Requirements
For the traces shown in 图8-2 and 图8-3:
• Common-mode rejection of at least 80 dB
• Gain of 250
8.2.2 Detailed Design Procedure
8.2.2.1 Setting the Gain
Gain is set by connecting an external resistor, RG:
g = 5 + 80 kΩ/ RG
(1)
Commonly used gains and RG resistor values are shown in 图8-1.
The 80-kΩ term in 方程式 1 comes from the internal metal-film resistors, which are laser-trimmed to accurate
absolute values. The accuracy and temperature coefficient of these resistors are included in the gain accuracy
and drift specifications.
The stability and temperature drift of the external gain setting resistor, RG, also affects gain. The RG contribution
to gain accuracy and drift can be directly inferred from 方程式 1. Low resistor values required for high gain can
make wiring resistance important. Sockets add to the wiring resistance, which contributes additional gain error in
gains of approximately 100 or greater.
8.2.2.2 Offset Trimming
The INAx126 family features low offset voltage and offset voltage drift. Most applications require no external
offset adjustment. 图 8-2 shows an optional circuit for trimming the output offset voltage. The voltage applied to
the Ref pin is added to the output signal. An operational amplifier buffer provides low impedance at the Ref pin to
preserve good common-mode rejection.
–
mIN
mO
RG
INA126
Ref
m+
!
+
mIN
100µA
1/2 REF200
100Ω
100Ω
10kΩ
OPA237
10ꢀm
Adjustꢀent Range
100µA
1/2 REF200
! Dual version has
external sense connection.
m–
图8-2. Optional Trimming of Output Offset Voltage
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8.2.2.3 Input Bias Current Return
The input impedance of the INAx126 is extremely high at approximately 109 Ω. However, a path must be
provided for the input bias current of both inputs. This input bias current is typically –10 nA (current flows out of
the input pins). High input impedance means that this input bias current changes very little with varying input
voltage.
Input circuitry must provide a path for this input bias current for proper operation. 图 8-3 shows various
provisions for an input bias current path. Without a bias current path, the inputs float to a potential that exceeds
the common-mode range, and the input amplifiers will saturate.
If the differential source resistance is low, the bias current return path can be connected to one input (see the
thermocouple example in 图 8-3). With higher source impedance, using two equal resistors provides a balanced
input with the advantages of lower input offset voltage due to bias current and better high-frequency common-
mode rejection.
Microphone,
Hydrophone
etc.
INA126
47kΩ
47kΩ
Thermocouple
INA126
10kΩ
INA126
Center-tap provides
bias current return.
图8-3. Providing an Input Common-Mode Current Path
8.2.2.4 Input Common-Mode Range
The input common-mode range of the INAx126 is shown in 节 6.7. The common-mode range is limited on the
negative side by the output voltage swing of A2, an internal circuit node that cannot be measured on an external
pin. The output voltage of A2 can be expressed as shown in 方程式2:
VO2 = 1.25 V– IN –(V+ IN –V– IN) (10 kΩ/RG)
(2)
where
• Voltages referred to Ref, pin 5
The internal op amp A2 is identical to A1, with an output swing typically limited to 0.7 V from the supply rails.
When the input common-mode range is exceeded (A2 output is saturated), A1 can still be in linear operation and
respond to changes in the noninverting input voltage. The output voltage, however, will be invalid.
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8.2.2.5 Input Protection
The inputs are protected with internal diodes connected to the power-supply rails. These diodes clamp the
applied signal to prevent the signal from exceeding the power supplies by more than approximately 0.7 V. If the
signal-source voltage can exceed the power supplies, the source current should be limited to less than 10 mA.
This limiting can generally be done with a series resistor. Some signal sources are inherently current-limited, and
do not require limiting resistors.
8.2.2.6 Channel Crosstalk—Dual Version
The two channels of the INA2126 are completely independent, including all bias circuitry. At dc and low
frequency, there is virtually no signal coupling between channels. Crosstalk increases with frequency and
depends on circuit gain, source impedance, and signal characteristics.
As source impedance increases, careful circuit layout can help achieve lowest channel crosstalk. Most crosstalk
is produced by capacitive coupling of signals from one channel to the input section of the other channel. To
minimize coupling, separate the input traces as far as practical from any signals associated with the opposite
channel. A grounded guard trace surrounding the inputs helps reduce stray coupling between channels.
Carefully balance the stray capacitance of each input to ground, and run the differential inputs of each channel
parallel to each other, or directly adjacent on top and bottom side of a circuit board. Stray coupling then tends to
produce a common-mode signal that is rejected by the IA input.
8.2.3 Application Curves
space
Differential signal is too small to be seen
图8-5. FFT of Signal in Previous Figure Shows
Both the 60-Hz Common-mode Along With 5-kHz
Differential Signal
图8-4. Common-mode Signal at INA126 Input
图8-6. Recovered Differential Signal at the Output
图8-7. FFT of the INA126 Output Shows that the
of the INA126 With a Gain of 250
60-Hz Common-mode Signal is Rejected
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9 Power Supply Recommendations
9.1 Low-Voltage Operation
The INAx126 can be operated on power supplies as low as ±1.35 V. Performance remains excellent with power
supplies ranging from ±1.35 V to ±18 V. Most parameters vary only slightly throughout this supply voltage range
(see 节 6.7). Operation at low supply voltage requires careful attention to make sure that the common-mode
voltage remains within the linear range (see 图6-5 and 图6-6).
The INAx126 operates from a single power supply with careful attention to input common-mode range, output
voltage swing of both op amps, and the voltage applied to the Ref pin. 图 9-1 shows a bridge amplifier circuit
operated from a single 5-V power supply. The bridge provides an input common-mode voltage near 2.5 V, with a
relatively small differential voltage.
The ADS7817’s VREF input current is proportional to conversion rate. A
conversion rate of 10kS/s or slower assures enough current to turn on the
reference diode. Converter input range is 1.2V. Output swing limitation of
+5V
INA126 limits the A/D converter to somewhat greater than 11 bits of range.
7
R1, C1, R2:
340Hz LP
INA126 and ADS7817
are available in fine-pitch
MSOP-8 package
INA126
2.5V + ∆V
3
8
6
A1
8
R1
40kΩ
!
1kΩ
2
6
5
7
Serial
Data
+IN
D
CS
Ck
10kΩ
Bridge
Sensor
RG
C1
0.47µF
10kΩ
ADS7817
12-Bit
A/D
3
1
Chip
–IN
Select
R2
1
2
1kΩ
A2
2.5V – ∆V
VREF
Clock
40kΩ
5
1.2V
33µA
4
6
8
4
4
REF1004C-1.2
A similar instrumentation amplifier, INA125, provides
an internal reference voltage for sensor excitation
and/or A/D converter reference.
!Dual version has external
sense connection. Pin numbers
shown are for single version.
图9-1. Bridge Signal Acquisition, Single 5-V Supply
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10 Layout
10.1 Layout Guidelines
Attention to good layout practices is always recommended. For best operational performance of the device, use
good printed circuit board (PCB) layout practices, including:
• Make sure that both input paths are well-matched for source impedance and capacitance to avoid converting
common-mode signals into differential signals. In addition, parasitic capacitance at the gain-setting pins can
also affect CMRR over frequency. For example, in applications that implement gain switching using switches
or PhotoMOS® relays to change the value of RG, select the component so that the switch capacitance is as
small as possible.
– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
• Separate grounding for analog and digital portions of the circuitry is one of the simplest and most effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current. For more detailed information, see
PCB Design Guidelines For Reduced EMI.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better
than in parallel with the noisy trace.
• Place the external components as close to the device as possible. As illustrated in 图10-1, keep RG close to
the pins to minimize parasitic capacitance.
• Keep the traces as short as possible
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10.2 Layout Example
Gain Resistor
Bypass
Capacitor
RG
V-IN
V+IN
V-
RG
V+
VO
V+
-
VIN
VOUT
GND
VIN
+
Ref
Bypass
Capacitor
V-
GND
图10-1. INA126 Layout Example
-
-
V-INA
V+INA
RGA
V-INB
V+INB
RGB
VIN
VIN
VIN
VIN
+
+
RGA
RGB
REFA
VOA
REFB
VOB
Gain Resistor
Gain Resistor
VOUT
VOUT
SENSEA
V-
SENSEB
V+
V-
V+
Bypass
Capacitor
Bypass
Capacitor
GND
图10-2. INA2126 Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 PSpice® for TI
PSpice® for TI is a design and simulation environment that helps evaluate performance of analog circuits. Create
subsystem designs and prototype solutions before committing to layout and fabrication, reducing development
cost and time to market.
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
PhotoMOS® is a registered trademark of Panasonic Corporation.
PSpice® is a registered trademark of Cadence Design Systems, Inc.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
29-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
250
250
(1)
(2)
(3)
(4/5)
(6)
INA126E/250
INA126E/250G4
INA126E/2K5
ACTIVE
VSSOP
VSSOP
VSSOP
DGK
8
8
8
RoHS & Green
RoHS & Green
Call TI | NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-55 to 125
-55 to 125
A26
BB
Samples
LIFEBUY
ACTIVE
DGK
NIPDAU
A26
BB
DGK
2500 RoHS & Green
250 RoHS & Green
Call TI | NIPDAU
A26
BB
Samples
INA126EA/250
INA126EA/2K5
ACTIVE
ACTIVE
VSSOP
VSSOP
DGK
DGK
8
8
Call TI | NIPDAU
Call TI | NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
A26
A26
A26
Samples
Samples
2500 RoHS & Green
2500 RoHS & Green
INA126EA/2K5G4
INA126U
LIFEBUY
ACTIVE
VSSOP
SOIC
DGK
D
8
8
NIPDAU
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
75
2500 RoHS & Green
75 RoHS & Green
RoHS & Green
INA
126U
Samples
Samples
Samples
INA126U/2K5
INA126UA
ACTIVE
ACTIVE
SOIC
SOIC
D
D
8
8
NIPDAU
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
INA
126U
INA
126U
A
INA126UA/2K5
INA2126E/250
INA2126E/2K5
INA2126EA/250
INA2126EA/2K5
INA2126U
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SSOP
SSOP
SSOP
SSOP
SOIC
D
8
2500 RoHS & Green
NIPDAU
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-2-260C-1 YEAR
INA
126U
A
Samples
Samples
Samples
Samples
Samples
Samples
DBQ
DBQ
DBQ
DBQ
D
16
16
16
16
16
250
RoHS & Green
INA
2126E
A
2500 RoHS & Green
Call TI | NIPDAU
Call TI | NIPDAU
NIPDAU
INA
2126E
A
250
RoHS & Green
INA
2126E
A
2500 RoHS & Green
INA
2126E
A
40
RoHS & Green
NIPDAU
INA2126U
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jun-2023
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
INA2126UA
INA2126UA/2K5
INA2126UE4
ACTIVE
SOIC
SOIC
SOIC
D
D
D
16
16
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-3-260C-168 HR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
INA2126U
A
Samples
Samples
ACTIVE
2500 RoHS & Green
40 RoHS & Green
NIPDAU
NIPDAU
INA2126U
A
LIFEBUY
INA2126U
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jun-2023
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
31-Mar-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
INA126E/250
INA126E/250
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
SOIC
DGK
DGK
DGK
DGK
DGK
DGK
DGK
DGK
D
8
8
250
250
180.0
180.0
330.0
330.0
180.0
180.0
330.0
330.0
330.0
330.0
180.0
330.0
330.0
180.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
16.4
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
6.4
6.4
6.4
6.4
6.4
6.4
6.4
6.5
3.4
3.4
3.4
3.4
3.4
3.4
3.4
3.4
5.2
5.2
5.2
5.2
5.2
5.2
5.2
10.3
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
INA126E/2K5
INA126E/2K5
INA126EA/250
INA126EA/250
INA126EA/2K5
INA126EA/2K5
INA126U/2K5
INA126UA/2K5
INA2126E/250
INA2126E/2K5
INA2126E/2K5
INA2126EA/250
INA2126EA/2K5
INA2126UA/2K5
8
2500
2500
250
8
8
8
250
8
2500
2500
2500
2500
250
8
8
SOIC
D
8
SSOP
SSOP
SSOP
SSOP
SSOP
SOIC
DBQ
DBQ
DBQ
DBQ
DBQ
D
16
16
16
16
16
16
2500
2500
250
2500
2500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
31-Mar-2023
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
INA2126UA/2K5
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
31-Mar-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
INA126E/250
INA126E/250
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
SOIC
DGK
DGK
DGK
DGK
DGK
DGK
DGK
DGK
D
8
8
250
250
210.0
210.0
356.0
356.0
210.0
210.0
356.0
367.0
356.0
356.0
210.0
356.0
356.0
210.0
356.0
356.0
356.0
185.0
185.0
356.0
356.0
185.0
185.0
356.0
367.0
356.0
356.0
185.0
356.0
356.0
185.0
356.0
356.0
356.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
INA126E/2K5
INA126E/2K5
INA126EA/250
INA126EA/250
INA126EA/2K5
INA126EA/2K5
INA126U/2K5
INA126UA/2K5
INA2126E/250
INA2126E/2K5
INA2126E/2K5
INA2126EA/250
INA2126EA/2K5
INA2126UA/2K5
INA2126UA/2K5
8
2500
2500
250
8
8
8
250
8
2500
2500
2500
2500
250
8
8
SOIC
D
8
SSOP
SSOP
SSOP
SSOP
SSOP
SOIC
DBQ
DBQ
DBQ
DBQ
DBQ
D
16
16
16
16
16
16
16
2500
2500
250
2500
2500
2500
SOIC
D
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
31-Mar-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
INA126U
INA126UA
INA2126U
D
D
D
D
D
SOIC
SOIC
SOIC
SOIC
SOIC
8
75
75
40
40
40
506.6
506.6
506.6
506.6
506.6
8
8
8
8
8
3940
3940
3940
3940
3940
4.32
4.32
4.32
4.32
4.32
8
16
16
16
INA2126UA
INA2126UE4
Pack Materials-Page 4
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DBQ0016A
SSOP - 1.75 mm max height
SCALE 2.800
SHRINK SMALL-OUTLINE PACKAGE
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
14X .0250
[0.635]
16
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.175
[4.45]
8
9
16X .008-.012
[0.21-0.30]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.007 [0.17]
C A
B
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
GAGE PLANE
.004-.010
[0.11-0.25]
0 - 8
.016-.035
[0.41-0.88]
DETAIL A
TYPICAL
(.041 )
[1.04]
4214846/A 03/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 inch, per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MO-137, variation AB.
www.ti.com
EXAMPLE BOARD LAYOUT
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SEE
DETAILS
SYMM
1
16
16X (.016 )
[0.41]
14X (.0250 )
[0.635]
8
9
(.213)
[5.4]
LAND PATTERN EXAMPLE
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
.002 MAX
[0.05]
ALL AROUND
.002 MIN
[0.05]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214846/A 03/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SYMM
1
16
16X (.016 )
[0.41]
SYMM
14X (.0250 )
[0.635]
9
8
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:8X
4214846/A 03/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
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