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INA2181-Q1 [TI]

AEC-Q100、26V、双通道、双向、350kHz 电流感应放大器;
INA2181-Q1
型号： INA2181-Q1
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

AEC-Q100、26V、双通道、双向、350kHz 电流感应放大器

放大器
文件： 总51页 (文件大小：1823K)
中文：  中文翻译
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INA181-Q1, INA2181-Q1, INA4181-Q1  
ZHCSI40B –APRIL 2018–REVISED MARCH 2019  
INAx181-Q1 汽车双向低侧和高侧电压输出  
电流感应放大器  
1 特性  
3 说明  
1
•
符合面向汽车应用的 AEC-Q100 标准  
INA181-Q1、INA2181-Q1 和 INA4181-Q1 (INAx181-  
Q1) 电流检测放大器专为经成本优化的 解决方案而设  
计。这些器件是一系列双向电流检测放大器（也称为电  
流分流监控器），可在独立于电源电压的 –0.2V 至  
+26V 范围内的共模电压中感测电流检测电阻器上的压  
降。INAx181-Q1 系列集成有一个匹配的电阻器增益网  
络，具有四个固定增益器件选项：20V/V、50V/V、  
100V/V 或 200V/V。该匹配增益电阻器网络可最大限  
度地减小增益误差并降低温漂。  
–
–
–
温度等级 1：–40°C ≤ TA ≤ +125°C  
HBM ESD 分类等级 2  
CDM ESD 分类等级 C6  
•
•
•
共模范围 (VCM)：–0.2V 至 +26V  
高带宽：350kHz（A1 器件）  
偏移电压：  
–
–
±150µV（最大值），VCM = 0V  
±500µV（最大值），VCM = 12V  
•
•
•
输出压摆率：2V/µs  
双向电流感应功能  
精度：  
这些器件由 2.7V 至 5.5V 单电源供电。单通道  
INA181-Q1 消耗的最大电源电流为 260µA；而双通道  
INA2181-Q1 消耗的最大电源电流为 500µA，四通道  
INA4181-Q1 消耗的最大电源电流为 900µA。  
–
–
±1% 增益误差（最大值）  
1µV/°C 温漂（最大值）  
INA181-Q1 可提供 6 引脚 SOT-23 封装。INA2181-  
Q1 可提供 10 引脚 VSSOP 封装。INA4181-Q1 可提  
供 20 引脚 TSSOP 封装。所有器件选项的额定扩展工  
作温度范围均为 –40°C 至 +125°C。  
•
增益选项：  
–
–
–
–
20V/V（A1 器件）  
50V/V（A2 器件）  
100V/V（A3 器件）  
200V/V（A4 器件）  
器件信息(1)  
器件型号  
INA181-Q1  
封装  
SOT-23 (6)  
封装尺寸（标称值）  
2.90mm × 1.60mm  
3.00mm × 3.00mm  
6.50mm × 4.40mm  
•
瞬态电流：最大为 260µA (INA181-Q1)  
2 应用  
INA2181-Q1  
INA4181-Q1  
VSSOP (10)  
TSSOP (20)  
•
•
•
•
•
电机控制  
(1) 如需了解所有可用封装，请参阅产品说明书末尾的封装选项附  
录。  
电池监控  
电源管理  
照明控制  
过流检测  
典型应用电路  
Bus Voltage, VCM  
Up To 26 V  
Power Supply, VS  
2.7 V to 5.5 V  
CBYPASS  
0.1 µF  
RSENSE  
Load  
INA4181-Q1 (quad-channel)  
INA2181-Q1 (dual-channel)  
INA181-Q1 (single-channel)  
Microcontroller  
INœ  
œ
OUT  
REF  
ADC  
+
IN+  
GND  
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确  
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。  
English Data Sheet: SLYS018  
 
 
 
 
INA181-Q1, INA2181-Q1, INA4181-Q1  
ZHCSI40B –APRIL 2018–REVISED MARCH 2019  
www.ti.com.cn  
目录  
1
2
3
4
5
6
7
特性.......................................................................... 1  
应用.......................................................................... 1  
说明.......................................................................... 1  
修订历史记录 ........................................................... 2  
Device Comparison Table..................................... 3  
Pin Configuration and Functions......................... 3  
Specifications......................................................... 6  
7.1 Absolute Maximum Ratings ..................................... 6  
7.2 ESD Ratings.............................................................. 6  
7.3 Recommended Operating Conditions....................... 6  
7.4 Thermal Information.................................................. 6  
7.5 Electrical Characteristics........................................... 7  
7.6 Typical Characteristics.............................................. 8  
Detailed Description ............................................ 15  
8.1 Overview ................................................................. 15  
8.2 Functional Block Diagrams ..................................... 15  
8.3 Feature Description................................................. 17  
8.4 Device Functional Modes........................................ 19  
9
Application and Implementation ........................ 22  
9.1 Application Information............................................ 22  
9.2 Typical Application .................................................. 29  
10 Power Supply Recommendations ..................... 31  
10.1 Common-Mode Transients Greater Than 26 V .... 31  
11 Layout................................................................... 32  
11.1 Layout Guidelines ................................................. 32  
11.2 Layout Example .................................................... 32  
12 器件和文档支持 ..................................................... 35  
12.1 器件支持................................................................ 35  
12.2 文档支持................................................................ 35  
12.3 相关链接................................................................ 35  
12.4 接收文档更新通知 ................................................. 35  
12.5 社区资源................................................................ 35  
12.6 商标....................................................................... 35  
12.7 静电放电警告......................................................... 35  
12.8 术语表 ................................................................... 35  
13 机械、封装和可订购信息....................................... 36  
8
4 修订历史记录  
注：之前版本的页码可能与当前版本有所不同。  
Changes from Revision A (July 2018) to Revision B  
Page  
•
•
•
•
已更改 将 INA181-Q1 器件从预览更改为生产数据（有效）................................................................................................... 1  
已添加 new paragraph regarding phase reversal to end of Input Differential Overload section .......................................... 20  
已更改 Figure 57 to fix pin number typos ............................................................................................................................. 32  
已更改 Figure 58 to fix pin number typos ............................................................................................................................ 33  
Changes from Original (April 2018) to Revision A  
Page  
•
•
已更改 将 INA4181-Q1 器件从预览更改为生产数据（有效）................................................................................................. 1  
Changed instances of INAx180 to INAx181 in Pin Configurations and Functions (typos)..................................................... 3  
2
Copyright © 2018–2019, Texas Instruments Incorporated  
 
INA181-Q1, INA2181-Q1, INA4181-Q1  
www.ti.com.cn  
ZHCSI40B –APRIL 2018–REVISED MARCH 2019  
5 Device Comparison Table  
PRODUCT  
NUMBER OF CHANNELS  
GAIN (V/V)  
20  
INA181A1-Q1  
INA181A2-Q1  
INA181A3-Q1  
INA181A4-Q1  
INA2181A1-Q1  
INA2181A2-Q1  
INA2181A3-Q1  
INA2181A4-Q1  
INA4181A1-Q1  
INA4181A2-Q1  
INA4181A3-Q1  
INA4181A4-Q1  
1
1
1
1
2
2
2
2
4
4
4
4
50  
100  
200  
20  
50  
100  
200  
20  
50  
100  
200  
6 Pin Configuration and Functions  
INA181-Q1: DBV Package  
6-Pin SOT-23  
Top View  
OUT  
GND  
IN+  
1
2
3
6
5
4
VS  
REF  
INœ  
Not to scale  
Pin Functions: INA181-Q1 (Single Channel)  
PIN  
TYPE  
DESCRIPTION  
NAME  
NO.  
GND  
2
Analog  
Ground  
Current-sense amplifier negative input. For high-side applications, connect to load  
side of sense resistor. For low-side applications, connect to ground side of sense  
resistor.  
IN–  
IN+  
4
3
Analog input  
Analog input  
Current-sense amplifier positive input. For high-side applications, connect to bus-  
voltage side of sense resistor. For low-side applications, connect to load side of  
sense resistor.  
OUT  
REF  
VS  
1
5
6
Analog output  
Analog input  
Analog  
Output voltage  
Reference input  
Power supply, 2.7 V to 5.5 V  
Copyright © 2018–2019, Texas Instruments Incorporated  
3
INA181-Q1, INA2181-Q1, INA4181-Q1  
ZHCSI40B –APRIL 2018–REVISED MARCH 2019  
www.ti.com.cn  
INA2181-Q1: DGS Package  
10-Pin VSSOP  
INA4181-Q1: PW Package  
20-Pin TSSOP  
Top View  
Top View  
REF1  
OUT1  
INœ1  
IN+1  
VS  
1
2
3
4
5
6
7
8
9
10  
20  
REF4  
OUT4  
INœ4  
IN+4  
GND  
IN+3  
INœ3  
OUT3  
REF3  
NC  
OUT1  
INœ1  
1
2
3
4
5
10  
9
VS  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OUT2  
INœ2  
IN+2  
REF2  
IN+1  
GND  
REF1  
8
7
6
IN+2  
INœ2  
OUT2  
REF2  
NC  
Not to scale  
Not to scale  
Pin Functions: INA2181-Q1 (Dual Channel) and INA4181-Q1 (Quad Channel)  
PIN  
TYPE  
DESCRIPTION  
NAME  
INA2181-Q1 INA4181-Q1  
GND  
4
16  
Analog  
Ground  
Current-sense amplifier negative input for channel 1. For high-side  
IN–1  
2
3
Analog input  
Analog input  
Analog input  
Analog input  
Analog input  
Analog input  
Analog input  
applications, connect to load side of channel-1 sense resistor. For low-  
side applications, connect to ground side of channel-1 sense resistor.  
Current-sense amplifier positive input for channel 1. For high-side  
applications, connect to bus-voltage side of channel-1 sense resistor. For  
low-side applications, connect to load side of channel-1 sense resistor.  
IN+1  
IN–2  
IN+2  
IN–3  
IN+3  
IN–4  
3
8
4
7
Current-sense amplifier negative input for channel 2. For high-side  
applications, connect to load side of channel-2 sense resistor. For low-  
side applications, connect to ground side of channel-2 sense resistor.  
Current-sense amplifier positive input for channel 2. For high-side  
applications, connect to bus-voltage side of channel-2 sense resistor. For  
low-side applications, connect to load side of channel-2 sense resistor.  
7
6
Current-sense amplifier negative input for channel 3. For high-side  
applications, connect to load side of channel-3 sense resistor. For low-  
side applications, connect to ground side of channel-3 sense resistor.  
—
—
—
14  
15  
18  
Current-sense amplifier positive input for channel 3. For high-side  
applications, connect to bus-voltage side of channel-3 sense resistor. For  
low-side applications, connect to load side of channel-3 sense resistor.  
Current-sense amplifier negative input for channel 4. For high-side  
applications, connect to load side of channel-4 sense resistor. For low-  
side applications, connect to ground side of channel-4 sense resistor.  
Current-sense amplifier positive input for channel 4. For high-side  
applications, connect to bus-voltage side of channel-4 sense resistor. For  
low-side applications, connect to load side of channel-4 sense resistor.  
IN+4  
NC  
—
—
17  
Analog input  
—
NC denotes no internal connection. These pins can be left floating or  
connected to any voltage between VS and ground.  
10, 11  
OUT1  
OUT2  
OUT3  
OUT4  
1
9
2
8
Analog output  
Analog output  
Analog output  
Analog output  
Channel 1 output voltage  
Channel 2 output voltage  
Channel 3 output voltage  
Channel 4 output voltage  
—
—
13  
19  
4
Copyright © 2018–2019, Texas Instruments Incorporated  
INA181-Q1, INA2181-Q1, INA4181-Q1  
www.ti.com.cn  
ZHCSI40B –APRIL 2018–REVISED MARCH 2019  
Pin Functions: INA2181-Q1 (Dual Channel) and INA4181-Q1 (Quad Channel) (continued)  
PIN  
TYPE  
DESCRIPTION  
NAME  
REF1  
REF2  
REF3  
REF4  
VS  
INA2181-Q1 INA4181-Q1  
5
6
1
9
Analog input  
Analog input  
Analog input  
Analog input  
Analog  
Channel 1 reference voltage, 0 to VS  
Channel 2 reference voltage, 0 to VS  
Channel 3 reference voltage, 0 to VS  
Channel 4 reference voltage, 0 to VS  
Power supply pin, 2.7 V to 5.5 V  
—
—
10  
12  
20  
5
Copyright © 2018–2019, Texas Instruments Incorporated  
5
INA181-Q1, INA2181-Q1, INA4181-Q1  
ZHCSI40B –APRIL 2018–REVISED MARCH 2019  
www.ti.com.cn  
7 Specifications  
7.1 Absolute Maximum Ratings  
over operating free-air temperature range (unless otherwise noted)(1)  
MIN  
MAX  
6
UNIT  
Supply voltage, VS  
V
Differential (VIN+) – (VIN–  
Common-mode(4)  
at REF pin  
)
–28  
28  
Analog inputs, IN+, IN–(2)(3)  
V
GND – 0.3  
GND – 0.3  
GND – 0.3  
28  
Input voltage range  
VS + 0.3  
VS + 0.3  
8
V
V
Output voltage  
Maximum output current, IOUT  
Operating free-air temperature, TA  
Junction temperature, TJ  
Storage temperature, Tstg  
mA  
°C  
°C  
°C  
–55  
–65  
150  
150  
150  
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings  
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended  
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) VIN+ and VIN– are the voltages at the IN+ and IN– pins, respectively.  
(3) Sustained operation between 26 V and 28 V for more than a few minutes may cause permanent damage to the device.  
(4) Input voltage at any pin can exceed the voltage shown if the current at that pin is limited to 5 mA.  
7.2 ESD Ratings  
VALUE  
±3000  
±1000  
UNIT  
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)  
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)  
V(ESD)  
Electrostatic discharge  
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.  
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.  
7.3 Recommended Operating Conditions  
MIN  
–0.2  
2.7  
NOM  
12  
MAX  
UNIT  
VCM  
VS  
Common-mode input voltage (IN+ and IN–)  
Operating supply voltage  
26  
5.5  
V
V
5
TA  
Operating free-air temperature  
–40  
125  
°C  
7.4 Thermal Information  
INA181-Q1  
DBV (SOT-23)  
6 PINS  
198.7  
INA2181-Q1  
DGS (VSSOP)  
10 PINS  
177.3  
INA4181-Q1  
PW (TSSOP)  
20 PINS  
97.0  
(1)  
THERMAL METRIC  
UNIT  
RθJA  
Junction-to-ambient thermal resistance  
Junction-to-case (top) thermal resistance  
Junction-to-board thermal resistance  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
RθJC(top)  
RθJB  
120.9  
68.7  
37.7  
52.3  
98.4  
48.3  
ψJT  
Junction-to-top characterization parameter  
Junction-to-board characterization parameter  
Junction-to-case (bottom) thermal resistance  
30.3  
12.6  
3.6  
ψJB  
52.0  
96.9  
47.9  
RθJC(bot)  
N/A  
N/A  
N/A  
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application  
report.  
6
Copyright © 2018–2019, Texas Instruments Incorporated  
INA181-Q1, INA2181-Q1, INA4181-Q1  
www.ti.com.cn  
ZHCSI40B –APRIL 2018–REVISED MARCH 2019  
7.5 Electrical Characteristics  
at TA = 25°C, VS = 5 V, VREF = VS / 2, VIN+ = 12 V, and VSENSE = VIN+ – VIN– (unless otherwise noted)  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
INPUT  
VIN+ = 0 V to 26 V, VSENSE = 0 mV,  
TA = –40°C to +125°C  
Common-mode rejection ratio,  
RTI  
CMRR  
84  
100  
dB  
(1)  
VSENSE = 0 mV  
±100  
±25  
0.2  
±500  
±150  
1
μV  
μV  
VOS  
Offset voltage, RTI  
VSENSE = 0 mV, VIN+ = 0 V  
VSENSE = 0 mV, TA = –40°C to +125°C  
dVOS/dT  
PSRR  
Offset drift, RTI  
μV/°C  
VS = 2.7 V to 5.5 V, VIN+ = 12 V,  
VSENSE = 0 mV  
Power-supply rejection ratio, RTI  
±8  
±40  
μV/V  
VSENSE = 0 mV, VIN+ = 0 V  
VSENSE = 0 mV  
-6  
75  
µA  
µA  
µA  
IIB  
Input bias current  
Input offset current  
IIO  
VSENSE = 0 mV  
±0.05  
OUTPUT  
A1 devices  
A2 devices  
A3 devices  
A4 devices  
20  
50  
V/V  
V/V  
V/V  
V/V  
G
Gain  
100  
200  
VOUT = 0.5 V to VS – 0.5 V,  
TA = –40°C to +125°C  
EG  
Gain error  
±0.1%  
±1%  
20  
Gain error vs temperature  
Nonlinearity error  
TA = –40°C to +125°C  
VOUT = 0.5 V to VS – 0.5 V  
No sustained oscillation  
1.5  
±0.01%  
1
ppm/°C  
nF  
Maximum capacitive load  
(2)  
VOLTAGE OUTPUT  
VSP  
VSN  
Swing to VS power-supply rail(3)  
RL = 10 kΩ to GND, TA = –40°C to +125°C  
RL = 10 kΩ to GND, TA = –40°C to +125°C  
(VS) – 0.02  
(VS) – 0.03  
V
V
(VGND) +  
0.0005  
(VGND) +  
0.005  
Swing to GND(3)  
FREQUENCY RESPONSE  
A1 devices, CLOAD = 10 pF  
A2 devices, CLOAD = 10 pF  
A3 devices, CLOAD = 10 pF  
A4 devices, CLOAD = 10 pF  
350  
210  
150  
105  
2
kHz  
kHz  
kHz  
kHz  
V/µs  
BW  
Bandwidth  
SR  
Slew rate  
NOISE, RTI(1)  
Voltage noise density  
POWER SUPPLY  
40  
195  
356  
690  
nV/√Hz  
VSENSE = 0 mV  
INA181-Q1  
260  
300  
µA  
µA  
µA  
µA  
µA  
µA  
VSENSE = 0 mV, TA = –40°C to +125°C  
VSENSE = 0 mV  
500  
IQ  
Quiescent current  
INA2181-Q1  
INA4181-Q1  
VSENSE = 0 mV, TA = –40°C to +125°C  
VSENSE = 0 mV  
520  
900  
VSENSE = 0 mV, TA = –40°C to +125°C  
1000  
(1) RTI = referred-to-input.  
(2) See 图 19.  
(3) Swing specifications are tested with an overdriven input condition.  
版权 © 2018–2019, Texas Instruments Incorporated  
7
 
INA181-Q1, INA2181-Q1, INA4181-Q1  
ZHCSI40B –APRIL 2018–REVISED MARCH 2019  
www.ti.com.cn  
7.6 Typical Characteristics  
at TA = 25°C, VS = 5 V, VREF = VS / 2, and VIN+ = 12 V (unless otherwise noted)  
D002  
D001  
Input Offset Voltage (mV)  
Input Offset Voltage (mV)  
图 1. Input Offset Voltage Production Distribution A1  
图 2. Input Offset Voltage Production Distribution A2  
D003  
D004  
Input Offset Voltage (mV)  
Input Offset Voltage (mV)  
图 3. Input Offset Voltage Production Distribution A3  
图 4. Input Offset Voltage Production Distribution A4  
100  
A1  
A2  
A3  
A4  
50  
0
-50  
-100  
-50  
-25  
0
25  
50  
75  
100  
125  
150  
Temperature (èC)  
D005  
D006  
Common-Mode Rejection Ratio (mV/V)  
图 5. Offset Voltage vs Temperature  
图 6. Common-Mode Rejection Production Distribution A1  
版权 © 2018–2019, Texas Instruments Incorporated  
8
INA181-Q1, INA2181-Q1, INA4181-Q1  
www.ti.com.cn  
ZHCSI40B –APRIL 2018–REVISED MARCH 2019  
Typical Characteristics (接下页)  
at TA = 25°C, VS = 5 V, VREF = VS / 2, and VIN+ = 12 V (unless otherwise noted)  
D007  
D008  
Common-Mode Rejection Ratio (mV/V)  
Common-Mode Rejection Ratio (mV/V)  
图 7. Common-Mode Rejection Production Distribution A2  
图 8. Common-Mode Rejection Production Distribution A3  
10  
A1  
A2  
8
A3  
A4  
6
4
2
0
-2  
-4  
-6  
-8  
-10  
-50  
-25  
0
25  
50  
75  
100  
125  
150  
Temperature (èC)  
D010  
D009  
Common-Mode Rejection Ratio (mV/V)  
图 10. Common-Mode Rejection Ratio vs Temperature  
图 9. Common-Mode Rejection Production Distribution A4  
D011  
D012  
Gain Error (%)  
Gain Error (%)  
图 11. Gain Error Production Distribution A1  
版权 © 2018–2019, Texas Instruments Incorporated  
图 12. Gain Error Production Distribution A2  
9
INA181-Q1, INA2181-Q1, INA4181-Q1  
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Typical Characteristics (接下页)  
at TA = 25°C, VS = 5 V, VREF = VS / 2, and VIN+ = 12 V (unless otherwise noted)  
D013  
D014  
Gain Error (%)  
Gain Error (%)  
图 13. Gain Error Production Distribution A3  
图 14. Gain Error Production Distribution A4  
50  
40  
30  
20  
10  
0
0.4  
0.3  
0.2  
0.1  
0
A1  
A1  
A2  
A3  
A4  
A2  
A3  
A4  
-0.1  
-0.2  
-0.3  
-0.4  
-10  
-50  
-25  
0
25  
50  
75  
100  
125  
150  
10  
100  
1k  
10k  
100k  
1M  
10M  
Temperature (èC)  
Frequency (Hz)  
D015  
D016  
图 15. Gain Error vs Temperature  
图 16. Gain vs Frequency  
120  
100  
80  
60  
40  
20  
0
140  
120  
100  
80  
A1  
A2  
A3  
A4  
60  
40  
20  
0
10  
100  
1k  
10k  
100k  
1M  
10  
100  
1k  
10k  
100k  
1M  
10M  
Frequency (Hz)  
Frequency (Hz)  
D017  
D018  
图 17. Power-Supply Rejection Ratio vs Frequency  
图 18. Common-Mode Rejection Ratio vs Frequency  
10  
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Typical Characteristics (接下页)  
at TA = 25°C, VS = 5 V, VREF = VS / 2, and VIN+ = 12 V (unless otherwise noted)  
VS  
VS – 1  
VS – 2  
120  
100  
80  
60  
40  
20  
0
–40°C  
25°C  
125°C  
GND + 2  
GND + 1  
GND  
-20  
0
5
10 15 20 25 30 35 40 45 50 55 60  
Output Current (mA)  
-5  
0
5
10  
15  
20  
25  
30  
Common-Mode Voltage (V)  
D019  
D020  
Supply voltage = 5 V  
图 19. Output Voltage Swing vs Output Current  
图 20. Input Bias Current vs Common-Mode Voltage  
120  
100  
80  
60  
40  
20  
0
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
-20  
-5  
0
5
10  
15  
20  
25  
30  
-50  
-25  
0
25  
50  
75  
100  
125  
150  
Common-Mode Voltage (V)  
Temperature (èC)  
D021  
D022  
Supply voltage = 0 V  
图 21. Input Bias Current vs Common-Mode Voltage (Both  
图 22. Input Bias Current vs Temperature  
Inputs, Shutdown)  
380  
375  
370  
365  
360  
355  
350  
345  
340  
210  
205  
200  
195  
190  
185  
180  
-50  
-25  
0
25  
50  
75  
100  
125  
150  
-50  
-25  
0
25  
50  
75  
100  
125  
150  
Temperature (èC)  
Temperature (èC)  
D023  
D023  
图 23. Quiescent Current vs Temperature (INA181-Q1)  
图 24. Quiescent Current vs Temperature (INA2181-Q1)  
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Typical Characteristics (接下页)  
at TA = 25°C, VS = 5 V, VREF = VS / 2, and VIN+ = 12 V (unless otherwise noted)  
710  
705  
700  
695  
690  
685  
680  
675  
670  
665  
660  
655  
650  
400  
350  
300  
250  
200  
150  
-50  
-25  
0
25  
50  
75  
100  
125  
150  
-5  
0
5
10  
15  
20  
25  
30  
Temperature (èC)  
Common-Mode Voltage (V)  
D038  
D031  
图 25. Quiescent Current vs Temperature (INA4181-Q1)  
图 26. IQ vs Common-Mode Voltage (INA181-Q1)  
750  
1450  
1350  
1250  
1150  
1050  
950  
700  
650  
600  
550  
500  
450  
400  
350  
300  
850  
750  
650  
550  
-5  
0
5
10  
15  
20  
25  
30  
-5  
0
5
10  
15  
20  
25  
30  
Common-Mode Voltage (V)  
Common-Mode Voltage (V)  
D031  
D039  
图 27. IQ vs Common-Mode Voltage (INA2181-Q1)  
图 28. IQ vs Common-Mode Voltage (INA4181-Q1)  
100  
80  
70  
60  
50  
40  
30  
20  
10  
10  
Time (1 s/div)  
100  
1k  
10k  
100k  
1M  
Frequency (Hz)  
D025  
D024  
图 30. 0.1-Hz to 10-Hz Voltage Noise (Referred-to-Input)  
图 29. Input-Referred Voltage Noise vs Frequency  
(A3 Devices)  
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Typical Characteristics (接下页)  
at TA = 25°C, VS = 5 V, VREF = VS / 2, and VIN+ = 12 V (unless otherwise noted)  
VCM  
VOUT  
Time (10 ms/div)  
Time (25 ms/div)  
D026  
D027  
80-mVPP input step  
图 31. Step Response  
图 32. Common-Mode Voltage Transient Response  
Inverting Input  
Output  
Noninverting Input  
Output  
0 V  
0 V  
Time (250 ms/div)  
Time (250 ms/div)  
D028  
D029  
图 33. Inverting Differential Input Overload  
图 34. Noninverting Differential Input Overload  
Supply Voltage  
Output Voltage  
Supply Voltage  
Output Voltage  
0 V  
0 V  
Time (10  
ms/div)  
Time (100 ms/div)  
D030  
D032  
图 35. Start-Up Response  
图 36. Brownout Recovery  
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Typical Characteristics (接下页)  
at TA = 25°C, VS = 5 V, VREF = VS / 2, and VIN+ = 12 V (unless otherwise noted)  
140  
130  
120  
110  
100  
90  
1000  
Ch1 onto Ch2  
Ch2 onto Ch1  
A1  
A2  
A3  
A4  
500  
200  
100  
50  
20  
10  
5
2
1
0.5  
80  
0.2  
0.1  
10  
70  
100  
1k  
10k  
100k  
1M  
100  
1k  
10k  
100k  
1M  
10M  
Frequency (Hz)  
Frequency (Hz)  
D034  
D033  
图 38. Channel Separation vs Frequency (INA2181-Q1)  
图 37. Output Impedance vs Frequency  
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8 Detailed Description  
8.1 Overview  
The INA181-Q1, INA2181-Q1, and INA4181-Q1 (INAx181-Q1) are automotive-grade, 26-V common-mode,  
current-sensing amplifiers used in both low-side and high-side configurations. These specially-designed, current-  
sensing amplifiers accurately measure voltages developed across current-sensing resistors on common-mode  
voltages that far exceed the supply voltage powering the device. Current can be measured on input voltage rails  
as high as 26 V, and the devices can be powered from supply voltages as low as 2.7 V.  
8.2 Functional Block Diagrams  
VS  
Single-Channel  
TI Device  
INœ  
œ
OUT  
+
IN+  
REF  
GND  
图 39. INA181-Q1 Functional Block Diagram  
VS  
Dual-Channel  
TI Device  
INœ1  
œ
OUT1  
+
REF1  
IN+1  
INœ2  
œ
OUT2  
REF2  
+
IN+2  
GND  
图 40. INA2181-Q1 Functional Block Diagram  
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Functional Block Diagrams (接下页)  
VS  
Quad-Channel  
TI Device  
INœ1  
œ
OUT1  
REF1  
+
IN+1  
INœ2  
œ
OUT2  
REF2  
+
IN+2  
INœ3  
œ
OUT3  
REF3  
+
IN+3  
INœ4  
œ
OUT4  
REF4  
+
IN+4  
GND  
图 41. INA4181-Q1 Functional Block Diagram  
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8.3 Feature Description  
8.3.1 High Bandwidth and Slew Rate  
The INAx181-Q1 support small-signal bandwidths as high as 350 kHz, and large-signal slew rates of 2 V/µs. The  
ability to detect rapid changes in the sensed current, as well as the ability to quickly slew the output, make the  
INAx181-Q1 a good choice for applications that require a quick response to input current changes. One  
application that requires high bandwidth and slew rate is low-side motor control, where the ability to follow rapid  
changing current in the motor allows for more accurate control over a wider operating range. Another application  
that requires higher bandwidth and slew rates is system fault detection, where the INAx181-Q1 are used with an  
external comparator and a reference to quickly detect when the sensed current is out of range.  
8.3.2 Bidirectional Current Monitoring  
The INA181-Q1 senses current flow through a sense resistor in both directions. The bidirectional current-sensing  
capability is achieved by applying a voltage at the REF pin to offset the output voltage. A positive differential  
voltage sensed at the inputs results in an output voltage that is greater than the applied reference voltage;  
likewise, a negative differential voltage at the inputs results in output voltage that is less than the applied  
reference voltage. The output voltage of the current-sense amplifier is shown in 公式 1.  
VOUT = ILOADì RSENSE ìGAIN + V  
(
)
REF  
where  
•
•
•
•
ILOAD is the load current to be monitored.  
RSENSE is the current-sense resistor.  
GAIN is the gain option of the selected device.  
VREF is the voltage applied to the REF pin.  
(1)  
8.3.3 Wide Input Common-Mode Voltage Range  
The INAx181-Q1 support input common-mode voltages from –0.2 V to +26 V. Because of the internal topology,  
the common-mode range is not restricted by the power-supply voltage (VS) as long as VS stays within the  
operational range of 2.7 V to 5.5 V. The ability to operate with common-mode voltages greater or less than VS  
allow the INAx181-Q1 to be used in high-side, as well as low-side, current-sensing applications, as shown in 图  
42.  
Bus Supply  
œ0.2 V to +26 V  
Direction of Positive  
IN+  
Current Flow  
High-Side Sensing  
RSENSE  
Common-mode voltage (VCM  
is bus-voltage dependent.  
)
INœ  
LOAD  
Direction of Positive  
Current Flow  
IN+  
Low-Side Sensing  
Common-mode voltage (VCM  
is always near ground and is  
)
RSENSE  
isolated from bus-voltage spikes.  
INœ  
图 42. High-Side and Low-Side Sensing Connections  
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Feature Description (接下页)  
8.3.4 Precise Low-Side Current Sensing  
When used in low-side current sensing applications the offset voltage of the INAx181-Q1 is within ±150 µV. The  
low offset performance of the INAx181-Q1 has several benefits. First, the low offset allows these devices to be  
used in applications that must measure current over a wide dynamic range. In this case, the low offset improves  
the accuracy when the sensed currents are on the low end of the measurement range. Another advantage of low  
offset is the ability to sense lower voltage drop across the sense resistor accurately, thus allowing a lower-value  
shunt resistor. Lower-value shunt resistors reduce power loss in the current sense circuit, and help improve the  
power efficiency of the end application.  
The gain error of the INAx181-Q1 is specified to be within 1% of the actual value. As the sensed voltage  
becomes much larger than the offset voltage, this voltage becomes the dominant source of error in the current  
sense measurement.  
8.3.5 Rail-to-Rail Output Swing  
The INAx181-Q1 allow linear current sensing operation with the output close to the supply rail and GND. The  
maximum specified output swing to the positive rail is 30 mV, and the maximum specified output swing to GND is  
only 5 mV. In order to compare the output swing of the INAx181-Q1 to an equivalent operational amplifier (op  
amp), the inputs are overdriven to approximate the open-loop condition specified in op amp data sheets. The  
current-sense amplifier is a closed-loop system; therefore, the output swing to GND can be limited by the product  
of the offset voltage and amplifier gain during unidirectional operation (VREF = 0 V).  
For devices that have positive offset voltages, the swing to GND is limited by the larger of either the offset  
voltage multiplied by the gain or the swing to GND specified in the Electrical Characteristics table.  
For example, in an application where the INA181A4-Q1 (gain = 200 V/V) is used for low-side current sensing and  
the device has an offset of 40 µV, the product of the device offset and gain results in a value of 8 mV, greater  
than the specified negative swing value. Therefore, the swing to GND for this example is 8 mV. If the same  
device has an offset of –40 µV, then the calculated zero differential signal is –8 mV. In this case, the offset helps  
overdrive the swing in the negative direction, and swing performance is consistent with the value specified in the  
Electrical Characteristics table.  
The offset voltage is a function of the common-mode voltage as determined by the CMRR specification;  
therefore, the offset voltage increases when higher common-mode voltages are present. The increase in offset  
voltage limits how low the output voltage can go during a zero-current condition when operating at higher  
common-mode voltages with VREF = 0 V . The typical limitation of the zero-current output voltage vs common-  
mode voltage for each gain option is shown in 图 43.  
0.06  
A1  
0.054  
A2  
A3  
A4  
0.048  
0.042  
0.036  
0.03  
0.024  
0.018  
0.012  
0.006  
0
0
2
4
6
8
10 12 14 16 18 20 22 24 26  
Common Mode Voltage (V)  
D033  
图 43. Zero-Current Output Voltage vs Common-Mode Voltage  
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8.4 Device Functional Modes  
8.4.1 Normal Mode  
The INAx181-Q1 are in normal operation when the following conditions are met:  
•
•
•
The power supply voltage (VS) is between 2.7 V and 5.5 V.  
The common-mode voltage (VCM) is within the specified range of –0.2 V to +26 V.  
The maximum differential input signal times gain plus VREF is less than VS minus the output voltage swing to  
VS.  
•
The minimum differential input signal times gain plus VREF is greater than the swing to GND (see the Rail-to-  
Rail Output Swing section).  
During normal operation, these devices produce an output voltage that is the gained-up representation of the  
difference voltage from IN+ to IN– plus the reference voltage at VREF  
.
8.4.2 Unidirectional Mode  
These devices can be configured to monitor current flowing in one direction (unidirectional) or in both directions  
(bidirectional) depending on how the REF pin is configured. The most common case is unidirectional where the  
output is set to ground when no current is flowing by connecting the REF pin to ground, as shown in 图 44. When  
the current flows from the bus supply to the load, the input signal across IN+ to IN– increases, and causes the  
output voltage at the OUT pin to increase.  
Bus Voltage  
Power Supply, VS  
2.7 V to 5.5 V  
œ0.2 V to +26 V  
CBYPASS  
0.1 µF  
RSENSE  
Load  
VS  
Single-Channel  
TI Device  
INœ  
OUT  
œ
Output  
+
IN+  
REF  
GND  
图 44. Unidirectional Application  
The linear range of the output stage is limited by how close the output voltage can approach ground under zero  
input conditions. In unidirectional applications where measuring very low input currents is desirable, bias the REF  
pin to a convenient value above 50 mV to get the output into the linear range of the device. To limit common-  
mode rejection errors, buffer the reference voltage connected to the REF pin.  
A less-frequently used output biasing method is to connect the REF pin to the power-supply voltage, VS. This  
method results in the output voltage saturating at 200 mV less than the supply voltage when no differential input  
signal is present. This method is similar to the output saturated low condition with no input signal when the REF  
pin is connected to ground. The output voltage in this configuration only responds to negative currents that  
develop negative differential input voltage relative to the device IN– pin. Under these conditions, when the  
differential input signal increases negatively, the output voltage moves downward from the saturated supply  
voltage. The voltage applied to the REF pin must not exceed VS.  
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Device Functional Modes (接下页)  
8.4.3 Bidirectional Mode  
The INAx181-Q1 are bidirectional, current-sense amplifiers capable of measuring currents through a resistive  
shunt in two directions. This bidirectional monitoring is common in applications that include charging and  
discharging operations where the current flowing through the resistor can change directions.  
Bus Voltage  
œ0.2 V to +26 V  
Power Supply, VS  
2.7 V to 5.5 V  
CBYPASS  
0.1 µF  
RSENSE  
Load  
VS  
Single-Channel  
TI Device  
Reference  
Voltage  
INœ  
œ
OUT  
REF  
Output  
+
IN+  
+
œ
GND  
图 45. Bidirectional Application  
The ability to measure this current flowing in both directions is enabled by applying a voltage to the REF pin, as  
shown in 图 45. The voltage applied to REF (VREF) sets the output state that corresponds to the zero-input level  
state. The output then responds by increasing above VREF for positive differential signals (relative to the IN– pin)  
and responds by decreasing below VREF for negative differential signals. This reference voltage applied to the  
REF pin can be set anywhere between 0 V to VS. For bidirectional applications, VREF is typically set at mid-scale  
for equal signal range in both current directions. In some cases, however, VREF is set at a voltage other than mid-  
scale when the bidirectional current and corresponding output signal do not need to be symmetrical.  
8.4.4 Input Differential Overload  
If the differential input voltage (VIN+ – VIN–) times gain exceeds the voltage swing specification, the INAx181-Q1  
drive the output as close as possible to the positive supply or ground, and does not provide accurate  
measurement of the differential input voltage. If this input overload occurs during normal circuit operation, then  
reduce the value of the shunt resistor or use a lower-gain version with the chosen sense resistor to avoid this  
mode of operation. If a differential overload occurs in a fault event, then the output of the INAx181-Q1 returns to  
the expected value approximately 20 µs after the fault condition is removed.  
When the INAx181-Q1 output is driven to either the supply rail or ground, increasing the differential input voltage  
does not damage the device as long as the absolute maximum ratings are not violated. Following these  
guidelines, the INAx181-Q1 output maintains polarity, and does not suffer from phase reversal.  
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Device Functional Modes (接下页)  
8.4.5 Shutdown Mode  
Although the INAx181-Q1 do not have a shutdown pin, the low power consumption of these devices allows the  
output of a logic gate or transistor switch to power the INAx181-Q1. This gate or switch turns on and off the  
INAx181-Q1 power-supply quiescent current.  
However, in current shunt monitoring applications, there is also a concern for how much current is drained from  
the shunt circuit in shutdown conditions. Evaluating this current drain involves considering the simplified  
schematic of the INAx181-Q1 in shutdown mode, as shown in 图 46.  
VS  
2.7 V to 5.5 V  
RPULL-UP  
10 kꢀ  
Bus Voltage  
œ0.2 V to +26 V  
Shutdown  
RSENSE  
Load  
CBYPASS  
0.1 µF  
VS  
Single-Channel  
TI Device  
INœ  
OUT  
REF  
œ
Output  
+
IN+  
GND  
图 46. Basic Circuit to Shut Down the INA181-Q1 With a Grounded Reference  
There is typically more than 500 kΩ of impedance (from the combination of 500-kΩ feedback and  
input gain set resistors) from each input of the INAx181-Q1 to the OUT pin and to the REF pin. The amount of  
current flowing through these pins depends on the voltage at the connection. For example, if the REF pin is  
grounded, the calculation of the effect of the 500 kΩ impedance from the shunt to ground is straightforward.  
However, if the reference is powered while the INAx181-Q1 is in shutdown mode, instead of assuming 500 kΩ to  
ground, assume 500 kΩ to the reference voltage.  
Regarding the 500-kΩ path to the output pin, the output stage of a disabled INAx181-Q1 does constitute a good  
path to ground. Consequently, this current is directly proportional to a shunt common-mode voltage present  
across a 500-kΩ resistor.  
As a final note, as long as the shunt common-mode voltage is greater than VS when the device is powered up,  
there is an additional and well-matched 55-µA typical current that flows in each of the inputs. If less than VS, the  
common-mode input currents are negligible, and the only current effects are the result of the 500-kΩ resistors.  
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9 Application and Implementation  
注
Information in the following applications sections is not part of the TI component  
specification, and TI does not warrant its accuracy or completeness. TI’s customers are  
responsible for determining suitability of components for their purposes. Customers should  
validate and test their design implementation to confirm system functionality.  
9.1 Application Information  
The INAx181-Q1 amplify the voltage developed across a current-sensing resistor as current flows through the  
resistor to the load or ground. The ability to drive the reference pin to adjust the functionality of the output signal  
offers multiple configurations, as discussed in previous sections.  
9.1.1 Basic Connections  
图 47 shows the basic connections of the INA181-Q1. Connect the input pins (IN+ and IN–) as closely as  
possible to the shunt resistor to minimize any resistance in series with the shunt resistor.  
Bus Voltage  
œ0.2 V to +26 V  
Power Supply, VS  
2.7 V to 5.5 V  
CBYPASS  
0.1 µF  
RSENSE  
Load  
VS  
Single-Channel  
TI Device  
INœ  
Microcontroller  
OUT  
œ
ADC  
+
IN+  
REF  
GND  
NOTE: To help eliminate ground offset errors between the device and the analog-to-digital converter (ADC), connect  
the REF pin to the ADC reference input and then to ground. For best performance, use an RC filter between the  
output of the INAx181-Q1 and the ADC. See Closed-Loop Analysis of Load-Induced Amplifier Stability Issues Using  
ZOUT for more details.  
图 47. Basic Connections for the INA181-Q1  
A power-supply bypass capacitor of at least 0.1 µF is required for proper operation. Applications with noisy or  
high-impedance power supplies may require additional decoupling capacitors to reject power-supply noise.  
Connect bypass capacitors close to the device pins.  
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Application Information (接下页)  
9.1.2 RSENSE and Device Gain Selection  
The accuracy of the INAx181-Q1 is maximized by choosing the current-sense resistor to be as large as possible.  
A large sense resistor maximizes the differential input signal for a given amount of current flow and reduces the  
error contribution of the offset voltage. However, there are practical limits as to how large the current-sense  
resistor can be in a given application. The INAx181-Q1 have typical input bias currents of 75 µA for each input  
when operated at a 12-V common-mode voltage input. When large current-sense resistors are used, these bias  
currents cause increased offset error and reduced common-mode rejection. Therefore, using current-sense  
resistors larger than a few ohms is generally not recommended for applications that require current-monitoring  
accuracy. A second common restriction on the value of the current-sense resistor is the maximum allowable  
power dissipation that is budgeted for the resistor. 公式 2 gives the maximum value for the current sense resistor  
for a given power dissipation budget:  
PDMAX  
RSENSE  
<
2
IMAX  
where:  
•
•
PDMAX is the maximum allowable power dissipation in RSENSE  
.
IMAX is the maximum current that will flow through RSENSE  
.
(2)  
An additional limitation on the size of the current-sense resistor and device gain is due to the power-supply  
voltage, VS, and device swing to rail limitations. In order to make sure that the current-sense signal is properly  
passed to the output, both positive and negative output swing limitations must be examined. 公式 3 provides the  
maximum values of RSENSE and GAIN to keep the device from hitting the positive swing limitation.  
IMAX ìRSENSE ìGAIN < VSP - VREF  
where:  
•
•
•
•
IMAX is the maximum current that will flow through RSENSE  
.
GAIN is the gain of the current sense-amplifier.  
VSP is the positive output swing as specified in the data sheet.  
VREF is the externally applied voltage on the REF pin.  
(3)  
To avoid positive output swing limitations when selecting the value of RSENSE, there is always a trade-off between  
the value of the sense resistor and the gain of the device under consideration. If the sense resistor selected for  
the maximum power dissipation is too large, then it is possible to select a lower-gain device in order to avoid  
positive swing limitations.  
The negative swing limitation places a limit on how small of a sense resistor can be used in a given application.  
公式 4 provides the limit on the minimum size of the sense resistor.  
IMIN ìRSENSE ìGAIN > VSN - VREF  
where:  
•
•
•
•
IMIN is the minimum current that will flow through RSENSE  
.
GAIN is the gain of the current sense amplifier.  
VSN is the negative output swing of the device (see Rail-to-Rail Output Swing).  
VREF is the externally applied voltage on the REF pin.  
(4)  
In addition to adjusting the offset and gain, the voltage applied to the REF pin can be slightly increased to avoid  
negative swing limitations.  
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Application Information (接下页)  
9.1.3 Signal Filtering  
Provided that the INAx181-Q1 output is connected to a high impedance input, the best location to filter is at the  
device output using a simple RC network from OUT to GND. Filtering at the output attenuates high-frequency  
disturbances in the common-mode voltage, differential input signal, and INAx181-Q1 power-supply voltage. If  
filtering at the output is not possible, or filtering of only the differential input signal is required, it is possible to  
apply a filter at the input pins of the device. 图 48 provides an example of how a filter can be used on the input  
pins of the device.  
Bus Voltage  
œ0.2 V to +26 V  
RSENSE  
Load  
VS  
2.7 V to 5.5 V  
1
VS  
Single-Channel  
f-3dB  
=
TI Device  
2p(RF + RF )CF  
RF < 10 ꢀ  
RINT  
INœ  
fœ3dB  
VOUT  
CF  
œ
OUT  
REF  
Bias  
+
RF < 10 ꢀ  
RINT  
VREF  
IN+  
图 48. Filter at Input Pins  
The addition of external series resistance creates an additional error in the measurement; therefore, the value of  
these series resistors must be kept to 10 Ω (or less, if possible) to reduce impact to accuracy. The internal bias  
network shown in 图 48 present at the input pins creates a mismatch in input bias currents when a differential  
voltage is applied between the input pins. If additional external series filter resistors are added to the circuit, the  
mismatch in bias currents results in a mismatch of voltage drops across the filter resistors. This mismatch  
creates a differential error voltage that subtracts from the voltage developed across the shunt resistor. This error  
results in a voltage at the device input pins that is different than the voltage developed across the shunt resistor.  
Without the additional series resistance, the mismatch in input bias currents has little effect on device operation.  
The amount of error these external filter resistors add to the measurement can be calculated using 公式 6, where  
the gain error factor is calculated using 公式 5.  
The amount of variance in the differential voltage present at the device input relative to the voltage developed at  
the shunt resistor is based both on the external series resistance (RF) value as well as internal input resistor RINT  
,
as shown in 图 48. The reduction of the shunt voltage reaching the device input pins appears as a gain error  
when comparing the output voltage relative to the voltage across the shunt resistor. A factor can be calculated to  
determine the amount of gain error that is introduced by the addition of external series resistance. Calculate the  
expected deviation from the shunt voltage to what is measured at the device input pins is given using 公式 5:  
1250ìRINT  
(1250ìRF ) + (1250ìRINT ) + (RF ìRINT  
Gain Error Factor =  
)
where:  
•
•
RINT is the internal input resistor.  
RF is the external series resistance.  
(5)  
24  
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Application Information (接下页)  
With the adjustment factor from 公式 5, including the device internal input resistance, this factor varies with each  
gain version, as shown in 表 1. Each individual device gain error factor is shown in 表 2.  
表 1. Input Resistance  
PRODUCT  
GAIN  
20  
RINT (kΩ)  
INAx181A1-Q1  
INAx181A2-Q1  
INAx181A3-Q1  
INAx181A4-Q1  
25  
10  
5
50  
100  
200  
2.5  
表 2. Device Gain Error Factor  
PRODUCT  
SIMPLIFIED GAIN ERROR FACTOR  
25000  
INAx181A1-Q1  
(21ìRF ) + 25000  
10000  
INAx181A2-Q1  
INAx181A3-Q1  
INAx181A4-Q1  
(9ìRF ) +10000  
1000  
RF +1000  
2500  
(3ìRF ) + 2500  
The gain error that can be expected from the addition of the external series resistors can then be calculated  
based on 公式 6:  
Gain Error (%) = 100 - (100 ´ Gain Error Factor)  
(6)  
For example, using an INA181A2-Q1 and the corresponding gain error equation from 表 2, a series resistance of  
10 Ω results in a gain error factor of 0.991. The corresponding gain error is then calculated using 公式 6,  
resulting in an additional gain error of approximately 0.89% solely because of the external 10-Ω series resistors.  
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9.1.4 Summing Multiple Currents  
The outputs of the INA2181-Q1 are easily summed by connecting the output of one channel to the reference  
input of a second channel. The circuit configuration shown in 图 49 is an easy way to achieve current summing.  
To correctly sum multiple output currents the values for the current sense resistor RSENSE must be the same for  
all channels.  
Power  
Supply  
Dual-Channel  
TI Device  
REF1  
OUT1  
IN+1  
+
RSENSE  
œ
INœ1  
LOAD1  
REF2  
OUT2  
IN+2  
+
ADC  
RSENSE  
œ
VOUT2 = (ILOAD1 + ILOAD2) × RSENSE × GAIN  
INœ2  
LOAD2  
GND  
图 49. Summing Multiple Currents  
Connect the output of one channel of the INA2181-Q1 to the reference input of the other channel. Use the  
reference input of the first circuit to set the reference of the final summed output operating point. The currents  
sensed at each circuit in the chain are summed at the output of the last device in the chain.  
26  
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An example output response of a summing configuration is shown in 图 50. The reference pin of the first circuit is  
connected to ground, and sine waves at different frequencies are applied to the two circuits to produce a  
summed output as shown. The sine wave voltage input for the first circuit is offset so that the whole wave is  
above GND.  
Output  
Inputs  
Time (4 ms/div)  
VREF = 0 V  
图 50. Current Summing Application Output Response (A2 Devices)  
9.1.5 Detecting Leakage Currents  
Occasionally, the need arises to confirm that the current going into a load is identical to the current coming out of  
a load; usually, as part of diagnostic testing or fault detection. This situation requires precision current  
differencing, which is the same as summing, except that the two amplifiers have the inputs connected opposite of  
each other. To correctly detect leakage currents, the values for the current sense resistor RSENSE must be the  
same for all channels. Also an external reference voltage must be provided to the REF1 input to allow  
bidirectional leakage current detection.  
If the current into a load is equal to the current out of the load, then the voltage at OUT2 is the same as the  
applied voltage to REF1. To enable accurate differences between the two currents, a reference voltage must be  
applied. The reference voltage prevents the output of the device from being driven to ground, and also enables  
detection if the current into the load is either greater than or less than the current coming out of the load.  
For current differencing, the dual-channel INA2181-Q1 must have the inputs connected opposite to each other,  
as shown in 图 51. The reference input of the first channel sets the output quiescent level for all the devices in  
the string. Connect the output of the first channel to the reference input of the second channel. The reference  
input of the first channel sets the reference at the output. This circuit example is identical to the current summing  
example, except that the two shunt inputs are reversed in polarity. Under normal operating conditions, the final  
output is very close to the reference value and proportional to any current difference. This current differencing  
circuit is useful in detecting when current in to and out of a load do not match.  
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Power  
Supply  
Dual-Channel  
TI Device  
REF1  
OUT1  
IN+1  
VREF1  
+
RSENSE  
œ
INœ1  
LOAD  
REF2  
OUT2  
IN+2  
+
ADC  
RSENSE  
œ
VOUT2 = VREF1 if there is no leakage current  
INœ2  
图 51. Detecting Leakage Currents  
An example output response of a difference configuration is shown in 图 52. The reference pin of the first  
channel is connected to a reference voltage of 2.048 V. The inputs to each circuit is a 100-Hz sine wave, 180°  
out-of-phase with each other, resulting in a zero output as shown. The sine wave input to the first circuit is offset  
so that the input wave is completely above GND.  
Output  
Inputs  
Time (4 ms/div)  
VREF = 2.048 V  
图 52. Current Differencing Application Output Response (A2 Devices)  
28  
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9.2 Typical Application  
One application for the INAx181-Q1 is to monitor bidirectional currents. Bidirectional currents are present in  
systems that have to monitor currents in both directions; common examples are monitoring the charging and  
discharging of batteries and bidirectional current monitoring in motor control. The device configuration for  
bidirectional current monitoring is shown in 图 53. Applying stable REF pin voltage closer to the middle of device  
supply voltage allows both positive- and negative-current monitoring, as shown in this configuration. Configure  
the INAx181-Q1 to monitor unidirectional currents by grounding the REF pin.  
Bus Voltage  
œ0.2 V to +26 V  
Power Supply, VS  
2.7 V to 5.5 V  
CBYPASS  
0.1 µF  
RSENSE  
Load  
VS  
Single-Channel  
TI Device  
Reference  
Voltage  
INœ  
œ
OUT  
REF  
Output  
+
IN+  
+
œ
GND  
图 53. Measuring Bidirectional Current  
9.2.1 Design Requirements  
The design requirements for the circuit shown in 图 53, are listed in 表 3  
表 3. Design Parameters  
DESIGN PARAMETER  
Power-supply voltage, VS  
Bus supply rail, VCM  
EXAMPLE VALUE  
5 V  
12 V  
RSENSE power loss  
< 450 mW  
±20 A  
Maximum sense current, IMAX  
Current sensing error  
Small-signal bandwidth  
Less than 3.5% at maximum current, TJ = 25°C  
> 100 kHz  
9.2.2 Detailed Design Procedure  
The maximum value of the current sense resistor is calculated based on the maximum power loss requirement.  
By applying 公式 2, the maximum value of the current-sense resistor is calculated to be 1.125 mΩ. This is the  
maximum value for sense resistor RSENSE; therefore, select RSENSE to be 1 mΩ because it is the closest standard  
resistor value that meets the power-loss requirement.  
The next step is to select the appropriate gain and reduce RSENSE, if needed, to keep the output signal swing  
within the VS range. The design requirements call for bidirectional current monitoring; therefore, a voltage  
between 0 and VS must be applied to the REF pin. The bidirectional currents monitored are symmetric around 0  
(that is, ±20 A); therefore, the ideal voltage to apply to VREF is VS / 2 or 2.5 V. If the positive current is greater  
than the negative current, using a lower voltage on VREF has the benefit of maximizing the output swing for the  
given range of expected currents. Using 公式 3, and given that IMAX = 20 A , RSENSE = 1 mΩ, and VREF = 2.5 V,  
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the maximum current-sense gain calculated to avoid the positive swing-to-rail limitations on the output is 122.5.  
Likewise, using 公式 4 for the negative-swing limitation results in a maximum gain of 124.75. Selecting the gain-  
of-100 device maximizes the output range while staying within the output swing range. If the maximum calculated  
gains are slightly less than 100, the value of the current-sense resistor can be reduced to keep the output from  
hitting the output-swing limitations.  
To calculate the accuracy at peak current, the two factors that must be determined are the gain error and the  
offset error. The gain error of the INAx181-Q1 is specified to be a maximum of 1%. The error due to the offset is  
constant, and is specified to be 500 µV (maximum) for the conditions where VCM = 12 V and VS = 5 V. Using 公  
式 7, the percentage error contribution of the offset voltage is calculated to be 2.5%, with total offset error = 500  
µV, RSENSE = 1 mΩ, and ISENSE = 20 A.  
Total Offset Error (V)  
Total Offset Error (%) =  
ì100%  
ISENSE ìRSENSE  
(7)  
One method of calculating the total error is to add the gain error to the percentage contribution of the offset error.  
However, in this case, the gain error and the offset error do not have an influence or correlation to each other. A  
more statistically accurate method of calculating the total error is to use the RSS sum of the errors, as shown in  
公式 8:  
Total Error (%) = Total Gain Error (%)2 + Total Offset Error (%)2  
(8)  
After applying 公式 8, the total current sense error at maximum current is calculated to be 2.7%, and that is less  
than the design example requirement of 3.5%.  
The INA181A3-Q1 (gain = 100) also has a bandwidth of 150 kHz that meets the small-signal bandwidth  
requirement of 100 kHz. If higher bandwidth is required, lower-gain devices can be used at the expense of either  
reduced output voltage range or an increased value of RSENSE  
.
9.2.3 Application Curve  
An example output response of a bidirectional configuration is shown in 图 54. With the REF pin connected to a  
reference voltage (2.5 V in this case), the output voltage is biased upwards by this reference level. The output  
rises above the reference voltage for positive differential input signals, and falls below the reference voltage for  
negative differential input signals.  
VOUT  
VREF  
0V  
Time (500 µs/div)  
C002  
图 54. Bidirectional Application Output Response  
30  
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10 Power Supply Recommendations  
The input circuitry of the INAx181-Q1 accurately measures beyond the power-supply voltage, VS. For example,  
VS can be 5 V, whereas the bus supply voltage at IN+ and IN– can be as high as 26 V. However, the output  
voltage range of the OUT pin is limited by the voltages on the VS pin. The INAx181-Q1 also withstand the full  
differential input signal range up to 26 V at the IN+ and IN– input pins, regardless of whether or not the device  
has power applied at the VS pin.  
10.1 Common-Mode Transients Greater Than 26 V  
With a small amount of additional circuitry, the INAx181-Q1 can be used in circuits subject to transients higher  
than 26 V, such as automotive applications. Use only Zener diodes or Zener-type transient absorbers  
(sometimes referred to as transzorbs)—any other type of transient absorber has an unacceptable time delay.  
Start by adding a pair of resistors as a working impedance for the Zener diode; see 图 55. Keep these resistors  
as small as possible; most often, around 10 Ω. Larger values can be used with an effect on gain that is  
discussed in the Signal Filtering section. This circuit limits only short-term transients; therefore, many applications  
are satisfied with a 10-Ω resistor along with conventional Zener diodes of the lowest acceptable power rating.  
This combination uses the least amount of board space. These diodes can be found in packages as small as  
SOT-523 or SOD-523.  
VS  
2.7 V to 5.5 V  
CBYPASS  
0.1 µF  
Bus Supply  
œ0.2 V to +26 V  
RSENSE  
Load  
VS  
Single-Channel  
TI Device  
INœ  
œ
OUT  
RPROTECT  
< 10 ꢀ  
Output  
+
REF  
IN+  
GND  
图 55. Transient Protection Using Dual Zener Diodes  
In the event that low-power Zener diodes do not have sufficient transient absorption capability, a higher-power  
transzorb must be used. The most package-efficient solution involves using a single transzorb and back-to-back  
diodes between the device inputs, as shown in 图 56. The most space-efficient solutions are dual, series-  
connected diodes in a single SOT-523 or SOD-523 package. In either of the examples shown in 图 55 and 图 56,  
the total board area required by the INAx181-Q1 with all protective components is less than that of an SO-8  
package, and only slightly greater than that of an MSOP-8 package.  
VS  
CBYPASS  
0.1 µF  
2.7 V to 5.5 V  
Bus Supply  
œ0.2 V to +26 V  
RSENSE  
Load  
VS  
Single-Channel  
TI Device  
< 10 ꢀ  
INœ  
œ
OUT  
Transorb  
Output  
+
< 10 ꢀ  
REF  
IN+  
GND  
图 56. Transient Protection Using a Single Transzorb and Input Clamps  
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Common-Mode Transients Greater Than 26 V (接下页)  
For more information, see Current Shunt Monitor With Transient Robustness Reference Design.  
11 Layout  
11.1 Layout Guidelines  
•
Connect the input pins to the sensing resistor using a Kelvin or 4-wire connection. This connection technique  
makes sure that only the current-sensing resistor impedance is detected between the input pins. Poor routing  
of the current-sensing resistor commonly results in additional resistance present between the input pins.  
Given the very low ohmic value of the current resistor, any additional high-current carrying impedance can  
cause significant measurement errors.  
•
•
Place the power-supply bypass capacitor as close as possible to the device power supply and ground pins.  
The recommended value of this bypass capacitor is 0.1 µF. Additional decoupling capacitance can be added  
to compensate for noisy or high-impedance power supplies.  
When routing the connections from the current sense resistor to the device, keep the trace lengths as close  
as possible in order to minimize any impedance mismatch..  
11.2 Layout Example  
Direction of Positive  
Current Flow  
RSHUNT  
Bus Voltage:  
œ0.2 V to +26 V  
4
5
6
3
IN+  
GND  
OUT  
INœ  
Connect REF to low  
impedance voltage reference  
or to GND pin if not used.  
2
1
REF  
VS  
Current  
Sense  
VIA to Ground  
Plane  
CBYPASS  
Power-Supply, VS  
2.7 V to 5.5 V  
图 57. Single-Channel Recommended Layout  
32  
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Layout Example (接下页)  
Bus Voltage:  
œ0.2 V to +26 V  
VIA to connect REF pins to low  
impedance voltage reference or  
to GND pin if not used.  
VIA to  
Ground  
Plane  
6
5
4
3
2
1
REF1  
GND  
IN+1  
INœ1  
REF2  
IN+2  
INœ2  
OUT2  
VS  
7
RSHUNT2  
8
RSHUNT1  
9
10  
OUT1  
Current Sense  
Output 2  
CBYPASS  
Current Sense  
Output 1  
Power Supply, VS:  
2.7 V to 5.5 V  
Load 2  
Load 1  
图 58. Dual-Channel Recommended Layout  
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Layout Example (接下页)  
Load 2  
Load 3  
Current Sense  
Output 2  
Current Sense  
Output 3  
Connect to GND or  
External Reference  
11  
12  
13  
14  
15  
16  
17  
10  
9
8
7
6
5
4
3
2
1
NC  
NC  
REF2  
OUT2  
INœ2  
IN+2  
REF3  
OUT3  
INœ3  
RSHUNT3  
RSHUNT2  
IN+3  
GND  
IN+4  
VIA to  
Ground  
Plane  
CBYPASS  
VS  
Bus Voltage 2:  
œ0.2 V to +26 V  
IN+1  
INœ1  
OUT1  
REF1  
Bus Voltage 3:  
œ0.2 V to +26 V  
INœ4 18  
19  
OUT4  
VIA to  
Ground  
Plane  
Power Supply, VS:  
2.7 V to 5.5 V  
20  
REF4  
Current Sense  
Output 4  
Current Sense  
Output 1  
Bus Voltage 4:  
Bus Voltage 1:  
œ0.2 V to +26 V  
œ0.2 V to +26 V  
RSHUNT4  
RSHUNT1  
Load 4  
Load 1  
图 59. Quad-Channel Recommended Layout  
34  
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12 器件和文档支持  
12.1 器件支持  
12.1.1 开发支持  
《具有瞬态稳定性的电流分流监控器参考设计》  
12.2 文档支持  
12.2.1 相关文档  
请参阅如下相关文档：  
•
•
•
德州仪器 (TI)，《INA180-181EVM 用户指南》  
德州仪器 (TI)，《INA2180-2181EVM 用户指南》  
德州仪器 (TI)，《INA4180-4181EVM 用户指南》  
12.3 相关链接  
表 4 列出了快速访问链接。类别包括技术文档、支持和社区资源、工具与软件，以及立即订购快速访问。  
表 4. 相关链接  
器件  
产品文件夹  
请单击此处  
请单击此处  
请单击此处  
立即订购  
请单击此处  
请单击此处  
请单击此处  
技术文档  
请单击此处  
请单击此处  
请单击此处  
工具与软件  
请单击此处  
请单击此处  
请单击此处  
支持和社区  
请单击此处  
请单击此处  
请单击此处  
INA181-Q1  
INA2181-Q1  
INA4181-Q1  
12.4 接收文档更新通知  
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产  
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。  
12.5 社区资源  
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，  
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。  
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration  
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help  
solve problems with fellow engineers.  
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and  
contact information for technical support.  
12.6 商标  
E2E is a trademark of Texas Instruments.  
All other trademarks are the property of their respective owners.  
12.7 静电放电警告  
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可  
能会损坏集成电路。  
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可  
能会导致器件与其发布的规格不相符。  
12.8 术语表  
SLYZ022 — TI 术语表。  
这份术语表列出并解释术语、缩写和定义。  
版权 © 2018–2019, Texas Instruments Incorporated  
35  
 
INA181-Q1, INA2181-Q1, INA4181-Q1  
ZHCSI40B –APRIL 2018–REVISED MARCH 2019  
www.ti.com.cn  
13 机械、封装和可订购信息  
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且  
不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请查阅左侧的导航栏。  
36  
版权 © 2018–2019, Texas Instruments Incorporated  
PACKAGE OPTION ADDENDUM  
www.ti.com  
10-Dec-2020  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
INA181A1QDBVRQ1  
INA181A2QDBVRQ1  
INA181A3QDBVRQ1  
INA181A4QDBVRQ1  
INA2181A1QDGSRQ1  
INA2181A2QDGSRQ1  
INA2181A3QDGSRQ1  
INA2181A4QDGSRQ1  
INA4181A1QPWRQ1  
INA4181A2QPWRQ1  
INA4181A3QPWRQ1  
INA4181A4QPWRQ1  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
SOT-23  
SOT-23  
SOT-23  
SOT-23  
VSSOP  
VSSOP  
VSSOP  
VSSOP  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
DBV  
DBV  
DBV  
DBV  
DGS  
DGS  
DGS  
DGS  
PW  
6
3000 RoHS & Green  
3000 RoHS & Green  
3000 RoHS & Green  
3000 RoHS & Green  
2500 RoHS & Green  
2500 RoHS & Green  
2500 RoHS & Green  
2500 RoHS & Green  
2000 RoHS & Green  
2000 RoHS & Green  
2000 RoHS & Green  
2000 RoHS & Green  
NIPDAU  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
1N13  
1MS3  
1MT3  
1MU3  
1O56  
1O66  
1O76  
1O86  
6
NIPDAU  
NIPDAU  
6
6
NIPDAU  
10  
10  
10  
10  
20  
20  
20  
20  
NIPDAUAG  
NIPDAUAG  
NIPDAUAG  
NIPDAUAG  
NIPDAU  
4181A1Q  
4181A2Q  
4181A3Q  
4181A4Q  
PW  
NIPDAU  
PW  
NIPDAU  
PW  
NIPDAU  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
10-Dec-2020  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
3-Jun-2022  
TAPE AND REEL INFORMATION  
REEL DIMENSIONS  
TAPE DIMENSIONS  
K0  
P1  
W
B0  
Reel  
Diameter  
Cavity  
A0  
A0 Dimension designed to accommodate the component width  
B0 Dimension designed to accommodate the component length  
K0 Dimension designed to accommodate the component thickness  
Overall width of the carrier tape  
W
P1 Pitch between successive cavity centers  
Reel Width (W1)  
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE  
Sprocket Holes  
Q1 Q2  
Q3 Q4  
Q1 Q2  
Q3 Q4  
User Direction of Feed  
Pocket Quadrants  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
INA181A1QDBVRQ1  
INA181A2QDBVRQ1  
INA181A3QDBVRQ1  
INA181A4QDBVRQ1  
INA2181A1QDGSRQ1  
INA2181A2QDGSRQ1  
INA2181A3QDGSRQ1  
INA2181A4QDGSRQ1  
INA4181A1QPWRQ1  
INA4181A2QPWRQ1  
INA4181A3QPWRQ1  
INA4181A4QPWRQ1  
SOT-23  
SOT-23  
SOT-23  
SOT-23  
VSSOP  
VSSOP  
VSSOP  
VSSOP  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
DBV  
DBV  
DBV  
DBV  
DGS  
DGS  
DGS  
DGS  
PW  
6
3000  
3000  
3000  
3000  
2500  
2500  
2500  
2500  
2000  
2000  
2000  
2000  
180.0  
180.0  
180.0  
180.0  
330.0  
330.0  
330.0  
330.0  
330.0  
330.0  
330.0  
330.0  
8.4  
8.4  
3.2  
3.2  
3.2  
3.2  
3.2  
3.2  
3.4  
3.4  
3.4  
3.4  
7.1  
7.1  
7.1  
7.1  
1.4  
1.4  
1.4  
1.4  
1.4  
1.4  
1.4  
1.4  
1.6  
1.6  
1.6  
1.6  
4.0  
4.0  
4.0  
4.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
Q3  
Q3  
Q3  
Q3  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
6
6
8.4  
3.2  
8.0  
6
8.4  
3.2  
8.0  
10  
10  
10  
10  
20  
20  
20  
20  
12.4  
12.4  
12.4  
12.4  
16.4  
16.4  
16.4  
16.4  
5.3  
12.0  
12.0  
12.0  
12.0  
16.0  
16.0  
16.0  
16.0  
5.3  
5.3  
5.3  
6.95  
6.95  
6.95  
6.95  
PW  
PW  
PW  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
3-Jun-2022  
TAPE AND REEL BOX DIMENSIONS  
Width (mm)  
H
W
L
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
INA181A1QDBVRQ1  
INA181A2QDBVRQ1  
INA181A3QDBVRQ1  
INA181A4QDBVRQ1  
INA2181A1QDGSRQ1  
INA2181A2QDGSRQ1  
INA2181A3QDGSRQ1  
INA2181A4QDGSRQ1  
INA4181A1QPWRQ1  
INA4181A2QPWRQ1  
INA4181A3QPWRQ1  
INA4181A4QPWRQ1  
SOT-23  
SOT-23  
SOT-23  
SOT-23  
VSSOP  
VSSOP  
VSSOP  
VSSOP  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
DBV  
DBV  
DBV  
DBV  
DGS  
DGS  
DGS  
DGS  
PW  
6
3000  
3000  
3000  
3000  
2500  
2500  
2500  
2500  
2000  
2000  
2000  
2000  
210.0  
210.0  
210.0  
210.0  
366.0  
366.0  
366.0  
366.0  
356.0  
356.0  
356.0  
356.0  
185.0  
185.0  
185.0  
185.0  
364.0  
364.0  
364.0  
364.0  
356.0  
356.0  
356.0  
356.0  
35.0  
35.0  
35.0  
35.0  
50.0  
50.0  
50.0  
50.0  
35.0  
35.0  
35.0  
35.0  
6
6
6
10  
10  
10  
10  
20  
20  
20  
20  
PW  
PW  
PW  
Pack Materials-Page 2  
PACKAGE OUTLINE  
DGS0010A  
VSSOP - 1.1 mm max height  
S
C
A
L
E
3
.
2
0
0
SMALL OUTLINE PACKAGE  
C
SEATING PLANE  
0.1 C  
5.05  
4.75  
TYP  
PIN 1 ID  
AREA  
A
8X 0.5  
10  
1
3.1  
2.9  
NOTE 3  
2X  
2
5
6
0.27  
0.17  
10X  
3.1  
2.9  
1.1 MAX  
0.1  
C A  
B
B
NOTE 4  
0.23  
0.13  
TYP  
SEE DETAIL A  
0.25  
GAGE PLANE  
0.15  
0.05  
0.7  
0.4  
0 - 8  
DETAIL A  
TYPICAL  
4221984/A 05/2015  
NOTES:  
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing  
per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not  
exceed 0.15 mm per side.  
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.  
5. Reference JEDEC registration MO-187, variation BA.  
www.ti.com  
EXAMPLE BOARD LAYOUT  
DGS0010A  
VSSOP - 1.1 mm max height  
SMALL OUTLINE PACKAGE  
10X (1.45)  
(R0.05)  
TYP  
SYMM  
10X (0.3)  
1
5
10  
SYMM  
6
8X (0.5)  
(4.4)  
LAND PATTERN EXAMPLE  
SCALE:10X  
SOLDER MASK  
OPENING  
SOLDER MASK  
OPENING  
METAL UNDER  
SOLDER MASK  
METAL  
0.05 MAX  
ALL AROUND  
0.05 MIN  
ALL AROUND  
SOLDER MASK  
DEFINED  
NON SOLDER MASK  
DEFINED  
SOLDER MASK DETAILS  
NOT TO SCALE  
4221984/A 05/2015  
NOTES: (continued)  
6. Publication IPC-7351 may have alternate designs.  
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.  
www.ti.com  
EXAMPLE STENCIL DESIGN  
DGS0010A  
VSSOP - 1.1 mm max height  
SMALL OUTLINE PACKAGE  
10X (1.45)  
SYMM  
(R0.05) TYP  
10X (0.3)  
8X (0.5)  
1
5
10  
SYMM  
6
(4.4)  
SOLDER PASTE EXAMPLE  
BASED ON 0.125 mm THICK STENCIL  
SCALE:10X  
4221984/A 05/2015  
NOTES: (continued)  
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate  
design recommendations.  
9. Board assembly site may have different recommendations for stencil design.  
www.ti.com  
PACKAGE OUTLINE  
DBV0006A  
SOT-23 - 1.45 mm max height  
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR  
C
3.0  
2.6  
0.1 C  
1.75  
1.45  
B
1.45 MAX  
A
PIN 1  
INDEX AREA  
1
2
6
5
2X 0.95  
1.9  
3.05  
2.75  
4
3
0.50  
6X  
0.25  
C A B  
0.15  
0.00  
0.2  
(1.1)  
TYP  
0.25  
GAGE PLANE  
0.22  
0.08  
TYP  
8
TYP  
0
0.6  
0.3  
TYP  
SEATING PLANE  
4214840/C 06/2021  
NOTES:  
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing  
per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.  
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.  
5. Refernce JEDEC MO-178.  
www.ti.com  
EXAMPLE BOARD LAYOUT  
DBV0006A  
SOT-23 - 1.45 mm max height  
SMALL OUTLINE TRANSISTOR  
PKG  
6X (1.1)  
1
6X (0.6)  
6
SYMM  
5
2
3
2X (0.95)  
4
(R0.05) TYP  
(2.6)  
LAND PATTERN EXAMPLE  
EXPOSED METAL SHOWN  
SCALE:15X  
SOLDER MASK  
OPENING  
SOLDER MASK  
OPENING  
METAL UNDER  
SOLDER MASK  
METAL  
EXPOSED METAL  
EXPOSED METAL  
0.07 MIN  
ARROUND  
0.07 MAX  
ARROUND  
NON SOLDER MASK  
DEFINED  
SOLDER MASK  
DEFINED  
(PREFERRED)  
SOLDER MASK DETAILS  
4214840/C 06/2021  
NOTES: (continued)  
6. Publication IPC-7351 may have alternate designs.  
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.  
www.ti.com  
EXAMPLE STENCIL DESIGN  
DBV0006A  
SOT-23 - 1.45 mm max height  
SMALL OUTLINE TRANSISTOR  
PKG  
6X (1.1)  
1
6X (0.6)  
6
SYMM  
5
2
3
2X(0.95)  
4
(R0.05) TYP  
(2.6)  
SOLDER PASTE EXAMPLE  
BASED ON 0.125 mm THICK STENCIL  
SCALE:15X  
4214840/C 06/2021  
NOTES: (continued)  
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate  
design recommendations.  
9. Board assembly site may have different recommendations for stencil design.  
www.ti.com  
PACKAGE OUTLINE  
PW0020A  
TSSOP - 1.2 mm max height  
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE  
SEATING  
PLANE  
C
6.6  
6.2  
TYP  
A
0.1 C  
PIN 1 INDEX AREA  
18X 0.65  
20  
1
2X  
5.85  
6.6  
6.4  
NOTE 3  
10  
B
11  
0.30  
20X  
4.5  
4.3  
NOTE 4  
0.19  
1.2 MAX  
0.1  
C A B  
(0.15) TYP  
SEE DETAIL A  
0.25  
GAGE PLANE  
0.15  
0.05  
0.75  
0.50  
A
20  
0 -8  
DETAIL A  
TYPICAL  
4220206/A 02/2017  
NOTES:  
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing  
per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not  
exceed 0.15 mm per side.  
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.  
5. Reference JEDEC registration MO-153.  
www.ti.com  
EXAMPLE BOARD LAYOUT  
PW0020A  
TSSOP - 1.2 mm max height  
SMALL OUTLINE PACKAGE  
SYMM  
20X (1.5)  
(R0.05) TYP  
20  
1
20X (0.45)  
SYMM  
18X (0.65)  
11  
10  
(5.8)  
LAND PATTERN EXAMPLE  
EXPOSED METAL SHOWN  
SCALE: 10X  
METAL UNDER  
SOLDER MASK  
SOLDER MASK  
OPENING  
SOLDER MASK  
OPENING  
METAL  
EXPOSED METAL  
EXPOSED METAL  
0.05 MAX  
ALL AROUND  
0.05 MIN  
ALL AROUND  
NON-SOLDER MASK  
DEFINED  
SOLDER MASK  
DEFINED  
15.000  
(PREFERRED)  
SOLDER MASK DETAILS  
4220206/A 02/2017  
NOTES: (continued)  
6. Publication IPC-7351 may have alternate designs.  
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.  
www.ti.com  
EXAMPLE STENCIL DESIGN  
PW0020A  
TSSOP - 1.2 mm max height  
SMALL OUTLINE PACKAGE  
20X (1.5)  
SYMM  
(R0.05) TYP  
20  
1
20X (0.45)  
SYMM  
18X (0.65)  
10  
11  
(5.8)  
SOLDER PASTE EXAMPLE  
BASED ON 0.125 mm THICK STENCIL  
SCALE: 10X  
4220206/A 02/2017  
NOTES: (continued)  
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate  
design recommendations.  
9. Board assembly site may have different recommendations for stencil design.  
www.ti.com  
重要声明和免责声明  
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，  
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保。  
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