INA226AQDGSRQ1 [TI]
具有警报功能的 AEC-Q100、36V、16 位、超精密、I2C 输出电流/电压/功率监控器 | DGS | 10 | -40 to 125;
| 型号： | INA226AQDGSRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有警报功能的 AEC-Q100、36V、16 位、超精密、I2C 输出电流/电压/功率监控器 | DGS | 10 | -40 to 125 监控 光电二极管 |
| 文件： | 总37页 (文件大小：1025K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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INA226-Q1
ZHCSE07 –JULY 2015
INA226-Q1 汽车级 36V、双向、零漂移、高精度、低侧/高侧、I2C 兼容电
流/功率监视器，具有可编程过流报警功能
1 特性
3 说明
•
具有符合 AEC-Q100 标准的下列结果：
INA226-Q1 是一款分流/功率监视器，具有 I2C™或
SMBUS 兼容接口。 该器件 监视分流压降和总线电源
电压。 可编程校准值、转换时间和取平均值功能与内
部乘法器相结合，可实现电流值（单位为安培）和功率
值（单位为瓦）的直接读取。
1
–
–
器件温度等级 1：-40°C 至 125°C
器件人体放电模式 (HBM) 静电放电 (ESD) 分类
等级 2
–
器件组件充电模式 (CDM) ESD 分类等级 C4B
•
•
•
•
感测的总线电压范围：0V 至 36V
高侧或低侧感测
INA226-Q1 可在 0V 至 36V 的共模总线电压范围内感
测电流，与电源电压无关。 该器件由一个 2.7V 至
5.5V 的单电源供电，电源电流典型值为 330μA。 该器
件的额定工作温度范围为 –40°C 至 125°C，I2C 兼容
接口上具有多达 16 个可编程地址。
报告电流、电压和功率
高精度：
–
–
0.1% 增益误差（最大值）
10μV 偏移（最大值）
器件信息(1)
•
•
•
•
可配置的取平均值选项
器件型号
INA226-Q1
封装
封装尺寸（标称值）
16 个可编程地址
VSSOP (10)
3.00mm x 3.00mm
由 2.7V 至 5.5V 电源供电
10 引脚 DGS 超薄小外形尺寸 (VSSOP) 封装
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
2 应用
•
•
•
•
•
混合动力汽车 (HEV)/电动汽车 (EV) 电池管理
车身控制模块
自动车锁电机控制
自动车窗电机控制
阀门控制
高侧或低侧感测应用
Power Supply
(0 V to 36 V)
CBYPASS
0.1 mF
VS
(Supply Voltage)
High-
Side
Shunt
VBUS
SDA
SCL
Power Register
Current Register
Voltage Register
Alert Register
´
Load
V
I
I2C or SMBus
Compatible
Interface
VIN+
ADC
Low-
Side
Shunt
Alert
A0
VIN–
A1
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBOS743
INA226-Q1
ZHCSE07 –JULY 2015
www.ti.com.cn
目录
7.5 Programming .......................................................... 15
7.6 Register Maps......................................................... 21
Application and Implementation ........................ 28
8.1 Application Information............................................ 28
8.2 Typical Applications ................................................ 28
Power Supply Recommendations...................... 30
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 7
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 13
8
9
10 Layout................................................................... 30
10.1 Layout Guidelines ................................................. 30
10.2 Layout Example .................................................... 30
11 器件和文档支持 ..................................................... 31
11.1 器件支持 ............................................................... 31
11.2 社区资源................................................................ 31
11.3 商标....................................................................... 31
11.4 静电放电警告......................................................... 31
11.5 Glossary................................................................ 31
12 机械、封装和可订购信息....................................... 31
7
4 修订历史记录
日期
修订版本
注释
7 月
*
首次发布。
2
Copyright © 2015, Texas Instruments Incorporated
INA226-Q1
www.ti.com.cn
ZHCSE07 –JULY 2015
5 Pin Configuration and Functions
DGS Package
10-Pin VSSOP
Top View
1
2
3
4
5
10
9
A1
IN+
A0
Alert
SDA
SCL
IN–
VBUS
8
7
GND
VS
6
Pin Functions
PIN
I/O
DESCRIPTION
NAME
A0
NO.
2
Digital input
Digital input
Digital output
Analog
Address pin. Connect to GND, SCL, SDA, or VS. 表 2 shows pin settings and corresponding addresses.
A1
1
Address pin. Connect to GND, SCL, SDA, or VS. 表 2 shows pin settings and corresponding addresses.
Multi-functional alert, open-drain output.
Ground.
Alert
GND
IN+
3
7
10
9
Analog input
Analog input
Digital input
Digital I/O
Connect to supply side of shunt resistor.
Connect to load side of shunt resistor.
Serial bus clock line, open-drain input.
Serial bus data line, open-drain input/output.
Bus voltage input.
IN–
SCL
SDA
VBUS
VS
5
4
8
Analog input
Analog
6
Power supply, 2.7 V to 5.5 V.
Copyright © 2015, Texas Instruments Incorporated
3
INA226-Q1
ZHCSE07 –JULY 2015
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
6
UNIT
VVS
Supply voltage
V
(2)
Differential (VIN+ – VIN-
)
–40
–0.3
40
40
40
6
Analog Inputs,
IN+, IN–
V
Common-Mode (VIN+ + VIN-) / 2
VVBUS
VSDA
VSCL
IIN
–0.3
V
V
GND – 0.3
GND – 0.3 VVS + 0.3
V
Input current into any pin
Open-drain digital output current
Junction temperature
5
mA
mA
°C
°C
IOUT
TJ
10
150
Tstg
Storage temperature range
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) IN+ and IN– may have a differential voltage between –40 V and 40 V. However, the voltage at these pins must not exceed the range
–0.3 V to 40 V.
6.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
Electrostatic
discharge
V(ESD)
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
12
MAX
UNIT
V
VCM
VVS
TA
Common-mode input voltage
Operating supply voltage
3.3
V
Operating free-air temperature
–40
125
°C
6.4 Thermal Information
INA226-Q1
THERMAL METRIC(1)
DGS (VSSOP)
10 PINS
171.4
42.9
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
91.8
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.5
ψJB
90.2
RθJC(bot)
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
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INA226-Q1
www.ti.com.cn
ZHCSE07 –JULY 2015
6.5 Electrical Characteristics
TA = 25°C, VVS = 3.3 V, VIN+ = 12 V, VSENSE = (VIN+ – VIN–) = 0 mV and VVBUS = 12 V, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT
Shunt voltage input range
Bus voltage input range(1)
Common-mode rejection
Shunt offset voltage, RTI(2)
Shunt offset voltage, RTI(2) vs
temperature
Shunt offset voltage, RTI(2) vs
Power supply
Bus offset voltage, RTI(2)
–81.9175
81.92
36
mV
V
0
CMRR
VOS
0 V ≤ VIN+ ≤ 36 V
126
140
dB
μV
±2.5
±10
0.1
–40°C ≤ TA ≤ 125°C
2.7 V ≤ VS ≤ 5.5 V
0.02
μV/°C
PSRR
VOS
2.5
±1.25
10
μV/V
mV
±7.5
40
Bus offset voltage, RTI(2) vs
temperature
–40°C ≤ TA ≤ 125°C
μV/°C
Bus offset voltage, RTI(2) vs power
supply
PSRR
IB
0.5
mV/V
Input bias current (IIN+, IIN– pins)
VBUS input impedance
10
μA
kΩ
830
(IN+ pin) + (IN– pin),
Power-down mode
(3)
Input leakage
0.1
0.5
μA
DC ACCURACY
ADC native resolution
16
2.5
Bits
μV
Shunt voltage
Bus voltage
1 LSB step size
1.25
mV
Shunt voltage gain error
0.02%
0.1%
50
Shunt voltage gain error vs
temperature
–40°C ≤ TA ≤ 125°C
–40°C ≤ TA ≤ 125°C
10
0.02%
10
ppm/°C
Bus voltage gain error
0.1%
50
Bus voltage gain error vs
temperature
ppm/°C
LSB
Differential nonlinearity
±0.1
140
CT bit = 000
CT bit = 001
CT bit = 010
CT bit = 011
CT bit = 100
CT bit = 101
CT bit = 110
CT bit = 111
154
224
204
μs
332
365
588
646
tCT
ADC conversion time
1.1
1.21
2.328
4.572
9.068
2.116
4.156
8.244
ms
ms
SMBus
SMBus timeout(4)
28
35
(1) While the input range is 36 V, the full-scale range of the ADC scaling is 40.96 V. See the Basic ADC Functions section. Do not apply
more than 36 V.
(2) RTI = Referred-to-input.
(3) Input leakage is positive (current flowing into the pin) for the conditions shown at the top of this table. Negative leakage currents can
occur under different input conditions.
(4) SMBus timeout in the INA226-Q1 resets the interface any time SCL is low for more than 28 ms.
版权 © 2015, Texas Instruments Incorporated
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INA226-Q1
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Electrical Characteristics (接下页)
TA = 25°C, VVS = 3.3 V, VIN+ = 12 V, VSENSE = (VIN+ – VIN–) = 0 mV and VVBUS = 12 V, unless otherwise noted
PARAMETER
DIGITAL INPUT/OUTPUT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input capacitance
3
pF
0 V ≤ VSCL ≤ VVS
,
0 V ≤ VSDA ≤ VVS
,
Leakage input current
0 V ≤ VAlert ≤ VVS
,
0.1
1
μA
0 V ≤ VA0 ≤ VVS
0 V ≤ VA1 ≤ VVS
,
VIH
VIL
High-level input voltage
Low-level input voltage
0.7×VVS
–0.5
0
6
0.3×VVS
0.4
V
V
VOL
Low-level output voltage, SDA, Alert IOL = 3 mA
Hysteresis
V
500
mV
POWER SUPPLY
Operating supply range
2.7
5.5
V
IQ
Quiescent current
330
0.5
2
420
μA
Quiescent current, power-down
(shutdown) mode
2
μA
VPOR
Power-on reset threshold
V
6
版权 © 2015, Texas Instruments Incorporated
INA226-Q1
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ZHCSE07 –JULY 2015
6.6 Typical Characteristics
At TA = 25°C, VVS = 3.3 V, VIN+ = 12 V, VSENSE = (VIN+ – VIN–) = 0 mV and VVBUS = 12 V, unless otherwise noted.
0
−10
−20
−30
−40
−50
−60
1
10
100
1k
10k
100k
Frequency (Hz)
G001
Input Offset Voltage (mV)
图 2. Shunt Input Offset Voltage Production Distribution
图 1. Frequency Response
−1
−1.2
−1.4
−1.6
−1.8
−2
170
160
150
140
−2.2
−2.4
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
G003
G004
图 3. Shunt Input Offset Voltage vs Temperature
图 4. Shunt Input Common-Mode Rejection Ratio vs
Temperature
600
500
400
300
200
100
0
−50
−25
0
25
50
75
100
125
Temperature (°C)
G007
Input Gain Error (m%)
图 5. Shunt Input Gain Error Production Distribution
图 6. Shunt Input Gain Error vs Temperature
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ZHCSE07 –JULY 2015
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Typical Characteristics (接下页)
At TA = 25°C, VVS = 3.3 V, VIN+ = 12 V, VSENSE = (VIN+ – VIN–) = 0 mV and VVBUS = 12 V, unless otherwise noted.
300
250
200
150
100
50
0
−50
0
4
8
12
16
20
24
28
32
36
Common−Mode Input Voltage (V)
G008
Input Offset Voltage (mV)
图 7. Shunt Input Gain Error vs Common-Mode Voltage
图 8. Bus Input Offset Voltage Production Distribution
−0.6
−0.8
−1.0
−1.2
−1.4
−50
−25
0
25
50
75
100
125
Temperature (°C)
G009
Input Gain Error (m%)
图 9. Bus Input Offset Voltage vs Temperature
图 10. Bus Input Gain Error Production Distribution
600
500
400
300
200
100
0
25
20
15
10
5
0
−50
−25
0
25
50
75
100
125
0
4
8
12
16
20
24
28
32
36
Temperature (°C)
Common−Mode Input Voltage (V)
G012
G012
图 11. Bus Input Gain Error vs Temperature
图 12. Input Bias Current vs Common-Mode Voltage
8
版权 © 2015, Texas Instruments Incorporated
INA226-Q1
www.ti.com.cn
ZHCSE07 –JULY 2015
Typical Characteristics (接下页)
At TA = 25°C, VVS = 3.3 V, VIN+ = 12 V, VSENSE = (VIN+ – VIN–) = 0 mV and VVBUS = 12 V, unless otherwise noted.
24
22
20
18
16
260
220
180
140
100
60
20
−50
−50
−25
0
25
50
75
100
125
−25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
G013
G014
图 13. Input Bias Current vs Temperature
图 14. Input Bias Current vs Temperature, Shutdown
1.2
500
400
300
200
100
1
0.8
0.6
0.4
0.2
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
G015
G016
图 15. Active IQ vs Temperature
图 16. Shutdown IQ vs Temperature
500
300
250
200
150
100
50
450
400
350
300
0
1
10
100
1,000
10,000
1
10
100
1,000
10,000
Frequency (kHz)
Frequency (kHz)
图 17. Active IQ vs I2C Clock Frequency
图 18. Shutdown IQ vs I2C Clock Frequency
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INA226-Q1
ZHCSE07 –JULY 2015
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7 Detailed Description
7.1 Overview
The INA226-Q1 is a digital current sense amplifier with an I2C- and SMBus-compatible interface. It provides
digital current, voltage, and power readings necessary for accurate decision-making in precisely-controlled
systems. Programmable registers allow flexible configuration for measurement resolution as well as continuous-
versus-triggered operation. Detailed register information appears at the end of this data sheet, beginning with 表
4. See the Functional Block Diagram section for a block diagram of the INA226-Q1 device.
7.2 Functional Block Diagram
Power(1)
Bus Voltage(1)
´
Current(1)
Shunt Voltage
Channel
ADC
Bus Voltage
Channel
Calibration(2)
´
Shunt Voltage(1)
Data Registers
(1) Read-only
(2) Read/write
7.3 Feature Description
7.3.1 Basic ADC Functions
The INA226-Q1 device performs two measurements on the power-supply bus of interest. The voltage developed
from the load current that flows through a shunt resistor creates a shunt voltage that is measured at the IN+ and
IN– pins. The device can also measure the power supply bus voltage by connecting this voltage to the VBUS pin.
The differential shunt voltage is measured with respect to the IN– pin while the bus voltage is measured with
respect to ground.
The device is typically powered by a separate supply that can range from 2.7 V to 5.5 V. The bus that is being
monitored can range in voltage from 0 V to 36 V. Based on the fixed 1.25-mV LSB for the Bus Voltage Register
that a full-scale register results in a 40.96 V value.
注
Do not apply more than 36 V of actual voltage to the input pins.
There are no special considerations for power-supply sequencing because the common-mode input range and
power-supply voltage are independent of each other; therefore, the bus voltage can be present with the supply
voltage off, and vice-versa.
The device takes two measurements, shunt voltage and bus voltage. It then converts these measurements to
current, based on the Calibration Register value, and then calculates power. Refer to the Programming the
Calibration Register section for additional information on programming the Calibration Register.
10
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INA226-Q1
www.ti.com.cn
ZHCSE07 –JULY 2015
Feature Description (接下页)
The device has two operating modes, continuous and triggered, that determine how the ADC operates following
these conversions. When the device is in the normal operating mode (that is, MODE bits of the Configuration
Register (00h) are set to '111'), it continuously converts a shunt voltage reading followed by a bus voltage
reading. After the shunt voltage reading, the current value is calculated (based on 公式 3). This current value is
then used to calculate the power result (using 公式 4). These values are subsequently stored in an accumulator,
and the measurement/calculation sequence repeats until the number of averages set in the Configuration
Register (00h) is reached. Following every sequence, the present set of values measured and calculated are
appended to previously collected values. After all of the averaging has been completed, the final values for shunt
voltage, bus voltage, current, and power are updated in the corresponding registers that can then be read. These
values remain in the data output registers until they are replaced by the next fully completed conversion results.
Reading the data output registers does not affect a conversion in progress.
The mode control in the Conversion Register (00h) also permits selecting modes to convert only the shunt
voltage or the bus voltage in order to further allow the user to configure the monitoring function to fit the specific
application requirements.
All current and power calculations are performed in the background and do not contribute to conversion time.
In triggered mode, writing any of the triggered convert modes into the Configuration Register (00h) (that is,
MODE bits of the Configuration Register (00h) are set to ‘001’, ‘010’, or ‘011’) triggers a single-shot conversion.
This action produces a single set of measurements; thus, to trigger another single-shot conversion, the
Configuration Register (00h) must be written to a second time, even if the mode does not change.
In addition to the two operating modes (continuous and triggered), the device also has a power-down mode that
reduces the quiescent current and turns off current into the device inputs, reducing the impact of supply drain
when the device is not being used. Full recovery from power-down mode requires 40µs. The registers of the
device can be written to and read from while the device is in power-down mode. The device remains in power-
down mode until one of the active modes settings are written into the Configuration Register (00h) .
Although the device can be read at any time, and the data from the last conversion remain available, the
Conversion Ready flag bit (Mask/Enable Register, CVRF bit) is provided to help coordinate one-shot or triggered
conversions. The Conversion Ready flag (CVRF) bit is set after all conversions, averaging, and multiplication
operations are complete.
The Conversion Ready flag (CVRF) bit clears under these conditions:
•
•
Writing to the Configuration Register (00h), except when configuring the MODE bits for power-down mode; or
Reading the Mask/Enable Register (06h)
7.3.1.1 Power Calculation
The Current and Power are calculated following shunt voltage and bus voltage measurements as shown in 图 19.
Current is calculated following a shunt voltage measurement based on the value set in the Calibration Register. If
there is no value loaded into the Calibration Register, the current value stored is zero. Power is calculated
following the bus voltage measurement based on the previous current calculation and bus voltage measurement.
If there is no value loaded in the Calibration Register, the power value stored is also zero. Again, these
calculations are performed in the background and do not add to the overall conversion time. These current and
power values are considered intermediate results (unless the averaging is set to 1) and are stored in an internal
accumulation register, not the corresponding output registers. Following every measured sample, the newly-
calculated values for current and power are appended to this accumulation register until all of the samples have
been measured and averaged based on the number of averages set in the Configuration Register (00h).
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Feature Description (接下页)
Current Limit Detect Following
Every Shunt Voltage Conversion
Bus and Power Limit Detect
Following Every Bus Voltage Conversion
V
I
I
V
I
V
I
V
I
V
I
V
I
V
I
V
I
V
I
V
I
V
I
V
I
V
I
V
I
V
I
V
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
Power Average
Bus Voltage Average
Shunt Voltage Average
图 19. Power Calculation Scheme
In addition to the current and power accumulating after every sample, the shunt and bus voltage measurements
are also collected. After all of the samples have been measured and the corresponding current and power
calculations have been made, the accumulated average for each of these parameters is then loaded to the
corresponding output registers, where they can then be read.
7.3.1.2 Alert Pin
The INA226-Q1 has a single Alert Limit Register (07h), that allows the Alert pin to be programmed to respond to
a single user-defined event or to a Conversion Ready notification if desired. The Mask/Enable Register allows
the user to select from one of the five available functions to monitor and/or set the Conversion Ready bit to
control the response of the Alert pin. Based on the function being monitored, the user would then enter a value
into the Alert Limit Register to set the corresponding threshold value that asserts the Alert pin.
The Alert pin allows for one of several available alert functions to be monitored to determine if a user-defined
threshold has been exceeded. The five alert functions that can be monitored are:
•
•
•
•
•
Shunt Voltage Over-Limit (SOL)
Shunt Voltage Under-Limit (SUL)
Bus Voltage Over-Limit (BOL)
Bus Voltage Under-Limit (BUL)
Power Over-Limit (POL)
The Alert pin is an open-drain output. This pin is asserted when the alert function selected in the Mask/Enable
Register exceeds the value programmed into the Alert Limit Register. Only one of these alert functions can be
enabled and monitored at a time. If multiple alert functions are enabled, the selected function in the highest
significant bit position takes priority and responds to the Alert Limit Register value. For example, if the Shunt
Voltage Over-Limit function and the Shunt Voltage Under-Limit function are both selected, the Alert pin asserts
when the Shunt Voltage Register exceeds the value in the Alert Limit Register.
The Conversion Ready state of the device can also be monitored at the Alert pin to inform the user when the
device has completed the previous conversion and is ready to begin a new conversion. Conversion Ready can
be monitored at the Alert pin along with one of the alert functions. If an alert function and the Conversion Ready
are both enabled to be monitored at the Alert pin, after the Alert pin is asserted, the Mask/Enable Register must
be read following the alert to determine the source of the alert. By reading the Conversion Ready Flag (CVRF, bit
3), and the Alert Function Flag (AFF, bit 4) in the Mask/Enable Register, the source of the alert can be
determined. If the Conversion Ready feature is not desired and the CNVR bit is not set, the Alert pin only
responds to an exceeded alert limit based on the alert function enabled.
If the alert function is not used, the Alert pin can be left floating without impacting the operation of the device.
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Feature Description (接下页)
Refer to 图 19 to see the relative timing of when the value in the Alert Limit Register is compared to the
corresponding converted value. For example, if the alert function that is enabled is Shunt Voltage Over-Limit
(SOL), following every shunt voltage conversion the value in the Alert Limit Register is compared to the
measured shunt voltage to determine if the measurements has exceeded the programmed limit. The AFF, bit 4 of
the Mask/Enable Register, asserts high any time the measured voltage exceeds the value programmed into the
Alert Limit Register. In addition to the AFF being asserted, the Alert pin is asserted based on the Alert Polarity Bit
(APOL, bit 1 of the Mask/Enable Register). If the Alert Latch is enabled, the AFF and Alert pin remain asserted
until either the Configuration Register (00h) is written to or the Mask/Enable Register is read.
The Bus Voltage alert functions compare the measured bus voltage to the Alert Limit Register following every
bus voltage conversion and assert the AFF bit and Alert pin if the limit threshold is exceeded.
The Power Over-Limit alert function is also compared to the calculated power value following every bus voltage
measurement conversion and asserts the AFF bit and Alert pin if the limit threshold is exceeded.
7.4 Device Functional Modes
7.4.1 Averaging and Conversion Time Considerations
The INA226-Q1 device offers programmable conversion times (tCT) for both the shunt voltage and bus voltage
measurements. The conversion times for these measurements can be selected from as fast as 140 μs to as long
as 8.244 ms. The conversion time settings, along with the programmable averaging mode, allow the device to be
configured to optimize the available timing requirements in a given application. For example, if a system requires
that data be read every 5ms, the device could be configured with the conversion times set to 588 μs for both
shunt and bus voltage measurements and the averaging mode set to 4. This configuration results in the data
updating approximately every 4.7ms. The device could also be configured with a different conversion time setting
for the shunt and bus voltage measurements. This type of approach is common in applications where the bus
voltage tends to be relatively stable. This situation can allow for the time focused on the bus voltage
measurement to be reduced relative to the shunt voltage measurement. The shunt voltage conversion time could
be set to 4.156 ms with the bus voltage conversion time set to 588 μs, with the averaging mode set to 1. This
configuration also results in data updating approximately every 4.7 ms.
There are trade-offs associated with the settings for conversion time and the averaging mode used. The
averaging feature can significantly improve the measurement accuracy by effectively filtering the signal. This
approach allows the device to reduce any noise in the measurement that may be caused by noise coupling into
the signal. A greater number of averages enables the device to be more effective in reducing the noise
component of the measurement.
The conversion times selected can also have an impact on the measurement accuracy. 图 20 shows multiple
conversion times to illustrate the impact of noise on the measurement. In order to achieve the highest accuracy
measurement possible, use a combination of the longest allowable conversion times and highest number of
averages, based on the timing requirements of the system.
Conversion Time: 140ms
Conversion Time: 1.1ms
Conversion Time: 8.244ms
0
200
400
600
800
1000
Number of Conversions
图 20. Noise vs Conversion Time
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Device Functional Modes (接下页)
7.4.2 Filtering and Input Considerations
Measuring current is often noisy, and such noise can be difficult to define. The INA226-Q1 device offers several
options for filtering by allowing the conversion times and number of averages to be selected independently in the
Configuration Register (00h). The conversion times can be set independently for the shunt voltage and bus
voltage measurements to allow added flexibility in configuring the monitoring of the power-supply bus.
The internal ADC is based on a delta-sigma (ΔΣ) front-end with a 500 kHz (±30%) typical sampling rate. This
architecture has good inherent noise rejection; however, transients that occur at or very close to the sampling
rate harmonics can cause problems. Because these signals are at 1 MHz and higher, they can be managed by
incorporating filtering at the input of the device. The high frequency enables the use of low-value series resistors
on the filter with negligible effects on measurement accuracy. In general, filtering the device input is only
necessary if there are transients at exact harmonics of the 500 kHz (±30%) sampling rate (greater than 1 MHz).
Filter using the lowest possible series resistance (typically 10 Ω or less) and a ceramic capacitor. Recommended
values for this capacitor are between 0.1 μF and 1 μF. 图 21 shows the device with a filter added at the input.
Overload conditions are another consideration for the device inputs. The device inputs are specified to tolerate
40 V across the inputs. A large differential scenario might be a short to ground on the load side of the shunt. This
type of event can result in full power-supply voltage across the shunt (as long the power supply or energy
storage capacitors support it). Removing a short to ground can result in inductive kickbacks that could exceed
the 40-V differential and common-mode rating of the device. Inductive kickback voltages are best controlled by
Zener-type transient-absorbing devices (commonly called transzorbs) combined with sufficient energy storage
capacitance. See the TI Design, Transient Robustness for Current Shunt Monitors (TIDU473), which describes a
high-side current shunt monitor used to measure the voltage developed across a current-sensing resistor when
current passes through it.
In applications that do not have large energy storage electrolytics on one or both sides of the shunt, an input
overstress condition may result from an excessive dV/dt of the voltage applied to the input. A hard physical short
is the most likely cause of this event, particularly in applications with no large electrolytics present. This problem
occurs because an excessive dV/dt can activate the ESD protection in the device in systems where large
currents are available. Testing demonstrates that the addition of 10-Ω resistors in series with each input of the
device sufficiently protects the inputs against this dV/dt failure up to the 40-V rating of the device. Selecting these
resistors in the range noted has minimal effect on accuracy.
Power Supply
(0 V to 36 V)
CBYPASS
0.1 µF
VS
(Supply Voltage)
VBUS
CFILTER
SDA
SCL
0.1 µF to 1 µF
Ceramic
Capacitor
Power Register
Current Register
Voltage Register
Alert Register
X
RFILTER
V
I
≤ 10 Ω
I2C or SMBus
Compatible
Interface
VIN+
ADC
Alert
A0
VIN-
RFILTER
A1
≤ 10 Ω
Load
GND
图 21. Input Filtering
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7.5 Programming
An important aspect of the INA226-Q1 device is that it does not necessarily measure current or power. The
device measures both the differential voltage applied between the IN+ and IN- input pins and the voltage applied
to the VBUS pin. In order for the device to report both current and power values, the user must program the
resolution of the Current Register (04h) and the value of the shunt resistor present in the application to develop
the differential voltage applied between the input pins. The Power Register (03h) is internally set to be 25 times
the programmed Current_LSB. Both the Current_LSB and shunt resistor value are used in the calculation of the
Calibration Register value the device uses to calculate the corresponding current and power values based on the
measured shunt and bus voltages.
The Calibration Register is calculated based on 公式 1. This equation includes the term Current_LSB, which is
the programmed value for the LSB for the Current Register (04h). The user uses this value to convert the value
in the Current Register (04h) to the actual current in amperes. The highest resolution for the Current Register
(04h) can be obtained by using the smallest allowable Current_LSB based on the maximum expected current as
shown in 公式 2. While this value yields the highest resolution, it is common to select a value for the
Current_LSB to the nearest round number above this value to simplify the conversion of the Current Register
(04h) and Power Register (03h) to amperes and watts respectively. The RSHUNT term is the value of the external
shunt used to develop the differential voltage across the input pins.
0.00512
Current_LSB · RSHUNT
CAL =
where
•
0.00512 is an internal fixed value used to ensure scaling is maintained properly
(1)
(2)
Maximum Expected Current
215
Current_LSB =
After programming the Calibration Register, the Current Register (04h) and Power Register (03h) update
accordingly based on the corresponding shunt voltage and bus voltage measurements. Until the Calibration
Register is programmed, the Current Register (04h) and Power Register (03h) remain at zero.
7.5.1 Programming the Calibration Register
图 27 shows a nominal 10-A load that creates a differential voltage of 20 mV across a 2-mΩ shunt resistor. The
bus voltage for the INA226-Q1 is measured at the external VBUS input pin, which in this example is connected to
the IN– pin to measure the voltage level delivered to the load. For this example, the VBUS pin measures less
than 12 V because the voltage at the IN– pin is 11.98 V as a result of the voltage drop across the shunt resistor.
For this example, assuming a maximum expected current of 15 A, the Current_LSB is calculated to be 457.7
μA/bit using 公式 2. Using a value for the Current_LSB of 500 μA/Bit or 1 mA/Bit would significantly simplify the
conversion from the Current Register (04h) and Power Register (03h) to amperes and watts. For this example, a
value of 1 mA/bit was chosen for the Current_LSB. Using this value for the Current_LSB does trade a small
amount of resolution for having a simpler conversion process on the user side. Using 公式 1 in this example with
a Current_LSB value of 1 mA/bit and a shunt resistor of 2 mΩ results in a Calibration Register value of 2560, or
A00h.
The Current Register (04h) is then calculated by multiplying the decimal value of the Shunt Voltage Register
(01h) contents by the decimal value of the Calibration Register and then dividing by 2048, as shown in 公式 3.
For this example, the Shunt Voltage Register contains a value of 8,000 (representing 20 mV), which is multiplied
by the Calibration Register value of 2560 and then divided by 2048 to yield a decimal value for the Current
Register (04h) of 10000, or 2710h. Multiplying this value by 1 mA/bit results in the original 10-A level stated in
the example.
ShuntVoltage · CalibrationRegister
Current =
2048
(3)
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Programming (接下页)
The LSB for the Bus Voltage Register (02h) is a fixed 1.25 mV/bit, which means that the 11.98 V present at the
VBUS pin results in a register value of 2570h, or a decimal equivalent of 9584. Note that the MSB of the Bus
Voltage Register (02h) is always zero because the VBUS pin is only able to measure positive voltages.
The Power Register (03h) is then be calculated by multiplying the decimal value of the Current Register, 10000,
by the decimal value of the Bus Voltage Register (02h), 9584, and then dividing by 20,000, as defined in 公式 4.
For this example, the result for the Power Register (03h) is 12B8h, or a decimal equivalent of 4792. Multiplying
this result by the power LSB (25 times the [1 × 10–3 Current_LSB]) results in a power calculation of (4792 × 25
mW/bit), or 119.82 W. The power LSB has a fixed ratio to the Current_LSB of 25. For this example, a
programmed 1 mA/bit Current_LSB results in a power LSB of 25 mW/bit. This ratio is internally programmed to
ensure that the scaling of the power calculation is within an acceptable range. A manual calculation for the power
being delivered to the load would use a bus voltage of 11.98 V (12 VCM – 20 mV shunt drop) multiplied by the
load current of 10 A to give a result of 119.8 W.
Current · BusVoltage
Power =
20,000
(4)
表 1 lists the steps for configuring, measuring, and calculating the values for current and power for this device.
表 1. Calculating Current and Power(1)
STEP
Step 1
Step 2
Step 3
Step 4
Step 5
Step 6
REGISTER NAME
Configuration Register
Shunt Register
ADDRESS
00h
CONTENTS
4127h
1F40h
2570h
A00h
DEC
—
LSB
—
VALUE
—
01h
8000
9584
2560
10000
4792
2.5 µV
1.25 mV
—
20 mV
11.98 V
—
Bus Voltage Register
Calibration Register
Current Register
02h
05h
04h
2710
1 mA
25 mW
10 A
Power Register
03h
12B8h
119.82 W
(1) Conditions: Load = 10 A, VCM = 12 V, RSHUNT = 2 mΩ, and VVBUS = 12 V.
7.5.2 Programming the Power Measurement Engine
7.5.2.1 Calibration Register and Scaling
The Calibration Register enables the user to scale the Current Register (04h) and Power Register (03h) to the
most useful value for a given application. For example, set the Calibration Register such that the largest possible
number is generated in the Current Register (04h) or Power Register (03h) at the expected full-scale point. This
approach yields the highest resolution using the previously calculated minimum Current_LSB in the equation for
the Calibration Register. The Calibration Register can also be selected to provide values in the Current Register
(04h) and Power Register (03h) that either provide direct decimal equivalents of the values being measured, or
yield a round LSB value for each corresponding register. After these choices have been made, the Calibration
Register also offers possibilities for end user system-level calibration. After determining the exact current by
using an external ammeter, the value of the Calibration Register can then be adjusted based on the measured
current result of the INA226-Q1 to cancel the total system error as shown in 公式 5.
Cal ´ MeasShuntCurrent
INA226_Current
Corrected_Full_Scale_Cal = trunc
(5)
7.5.3 Simple Current Shunt Monitor Usage (No Programming Necessary)
The device can be used without any programming if it is only necessary to read a shunt voltage drop and bus
voltage with the default power-on reset configuration and continuous conversion of shunt and bus voltages.
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Without programming the device Calibration Register, the device is unable to provide either a valid current or
power value, because these outputs are both derived using the values loaded into the Calibration Register.
7.5.4 Default Settings
The default power-up states of the registers are shown in the Register Maps section of this data sheet. These
registers are volatile, and if programmed to a value other than the default values shown in 表 4, they must be re-
programmed at every device power-up. Detailed information on programming the Calibration Register specifically
is given in the Programming section and calculated based on 公式 1.
7.5.5 Bus Overview
The INA226-Q1 offers compatibility with both I2C and SMBus interfaces. The I2C and SMBus protocols are
essentially compatible with one another.
The I2C interface is used throughout this data sheet as the primary example, with SMBus protocol specified only
when a difference between the two systems is discussed. Two lines, SCL and SDA, connect the device to the
bus. Both SCL and SDA are open-drain connections.
The device that initiates a data transfer is called a master, and the devices controlled by the master are slaves.
The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access,
and generates START and STOP conditions.
To address a specific device, the master initiates a start condition by pulling the data signal line (SDA) from a
high to a low logic level while SCL is high. All slaves on the bus shift in the slave address byte on the rising edge
of SCL, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the
slave being addressed responds to the master by generating an Acknowledge and pulling SDA low.
Data transfer is then initiated and eight bits of data are sent, followed by an Acknowledge bit. During data
transfer, SDA must remain stable while SCL is high. Any change in SDA while SCL is high is interpreted as a
start or stop condition.
After all data have been transferred, the master generates a stop condition, indicated by pulling SDA from low to
high while SCL is high. The device includes a 28 ms timeout on its interface to prevent locking up the bus.
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7.5.5.1 Serial Bus Address
To communicate with the INA226-Q1, the master must first address slave devices via a slave address byte. The
slave address byte consists of seven address bits and a direction bit that indicates whether the action is to be a
read or write operation.
The device has two address pins, A0 and A1. 表 2 lists the pin logic levels for each of the 16 possible addresses.
The device samples the state of pins A0 and A1 on every bus communication. Establish the pin states before
any activity on the interface occurs.
表 2. Address Pins and Slave Addresses
A1
GND
GND
GND
GND
VS
A0
GND
VS
SLAVE ADDRESS
1000000
1000001
1000010
1000011
1000100
1000101
1000110
1000111
1001000
1001001
1001010
1001011
1001100
1001101
1001110
1001111
SDA
SCL
GND
VS
VS
VS
SDA
SCL
GND
VS
VS
SDA
SDA
SDA
SDA
SCL
SCL
SCL
SCL
SDA
SCL
GND
VS
SDA
SCL
7.5.5.2 Serial Interface
The INA226-Q1 operates only as a slave device on both the I2C bus and the SMBus. Connections to the bus are
made via the open-drain SDA and SCL lines. The SDA and SCL pins feature integrated spike suppression filters
and Schmitt triggers to minimize the effects of input spikes and bus noise. Although the device integrates spike
suppression into the digital I/O lines, proper layout techniques help minimize the amount of coupling into the
communication lines. This noise introduction could occur from capacitively coupling signal edges between the
two communication lines themselves or from other switching noise sources present in the system. Routing traces
in parallel with ground in between layers on a printed circuit board (PCB) typically reduces the effects of coupling
between the communication lines. Shielded communication lines reduces the possibility of unintended noise
coupling into the digital I/O lines that could be incorrectly interpreted as start or stop commands.
The INA226-Q1 supports the transmission protocol for fast mode (1 kHz to 400 kHz) and high-speed mode (1
kHz to 2.94 MHz). All data bytes are transmitted most significant byte first.
7.5.5.3 Writing to and Reading from the INA226-Q1
Accessing a specific register on the INA226-Q1 is accomplished by writing the appropriate value to the register
pointer. Refer to 表 4 for a complete list of registers and corresponding addresses. The value for the register
pointer (as shown in 图 25) is the first byte transferred after the slave address byte with the R/W bit low. Every
write operation to the device requires a value for the register pointer.
Writing to a register begins with the first byte transmitted by the master. This byte is the slave address, with the
R/W bit low. The device then acknowledges receipt of a valid address. The next byte transmitted by the master is
the address of the register which data is written to. This register address value updates the register pointer to the
desired register. The next two bytes are written to the register addressed by the register pointer. The device
acknowledges receipt of each data byte. The master may terminate data transfer by generating a start or stop
condition.
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When reading from the device , the last value stored in the register pointer by a write operation determines which
register is read during a read operation. To change the register pointer for a read operation, a new value must be
written to the register pointer. This write is accomplished by issuing a slave address byte with the R/W bit low,
followed by the register pointer byte. No additional data are required. The master then generates a start condition
and sends the slave address byte with the R/W bit high to initiate the read command. The next byte is
transmitted by the slave and is the most significant byte of the register indicated by the register pointer. This byte
is followed by an Acknowledge from the master; then the slave transmits the least significant byte. The master
acknowledges receipt of the data byte. The master may terminate data transfer by generating a Not-
Acknowledge after receiving any data byte, or generating a start or stop condition. If repeated reads from the
same register are desired, it is not necessary to continually send the register pointer bytes; the device retains the
register pointer value until it is changed by the next write operation.
图 22 shows the write operation timing diagram. 图 23 shows the read operation timing diagram.
注
Register bytes are sent most-significant byte first, followed by the least significant byte.
1
9
1
9
1
9
1
9
SCL
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SDA
1
0
0
A3
A2
A1
A0
R/W
P7
P6
P5
P4
P3
P2
P1
P0
ACK By
ACK By
Stop By
Master
Start By
Master
ACK By
ACK By
Slave
Slave
Slave
Slave
Frame 1 Two-Wire Slave Address Byte(1)
Frame 2 Register Pointer Byte
Frame 3 Data MSByte
Frame 4 Data LSByte
(1) The value of the Slave Address byte is determined by the settings of the A0 and A1 pins. Refer to 表 2.
图 22. Timing Diagram for Write Word Format
1
9
1
9
1
9
SCL
D7 D6
D5
D4
D3
D2
D1
D0
SDA
1
0
0
A3
R/W
D15 D14 D13 D12 D11 D10
D9
D8
A2
A1
A0
From
No ACK By(3) Stop
Master
From
Start By
Master
ACK By
ACK By
Master
Slave
Slave
Slave
Frame 1 Two-Wire Slave Address Byte(1)
Frame 2 Data MSByte(2)
Frame 3 Data LSByte(2)
(1) The value of the Slave Address byte is determined by the settings of the A0 and A1 pins. Refer to 表 2.
(2) Read data is from the last register pointer location. If a new register is desired, the register pointer must be updated.
See 图 25.
(3) ACK by Master can also be sent.
图 23. Timing Diagram for Read Word Format
图 24 shows the timing diagram for the SMBus Alert response operation. 图 25 illustrates a typical register
pointer configuration.
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ALERT
SCL
1
9
1
9
SDA
0
0
0
1
1
0
0
R/W
1
0
0
A3
A2
A1
A0
0
Start By
Master
ACK By
From
Slave
NACK By Stop By
Slave
Master
Master
Frame 1 SMBus ALERT Response Address Byte
Frame 2 Slave Address Byte(1)
(1) The value of the Slave Address Byte is determined by the settings of the A0 and A1 pins. Refer to 表 2.
图 24. Timing Diagram for SMBus ALERT
1
9
1
9
SCL
¼
SDA
1
0
0
A3
A2
A1
A0
R/W
P7
P6
P5
P4
P3
P2
P1
P0
Stop
Start By
Master
ACK By
ACK By
Slave
Slave
Frame 1 Two-Wire Slave Address Byte(1)
Frame 2 Register Pointer Byte
(1) The value of the Slave Address Byte is determined by the settings of the A0 and A1 pins. Refer to 表 2.
图 25. Typical Register Pointer Set
7.5.5.3.1 High-Speed I2C Mode
When the bus is idle, both the SDA and SCL lines are pulled high by the pullup resistors. The master generates
a start condition followed by a valid serial byte containing high-speed (HS) master code 00001XXX. This
transmission is made in fast (400 kHz) or standard (100 kHz) (F/S) mode at no more than 400 kHz. The device
does not acknowledge the HS master code, but does recognize it and switches its internal filters to support 2.94
MHz operation.
The master then generates a repeated start condition (a repeated start condition has the same timing as the start
condition). After this repeated start condition, the protocol is the same as F/S mode, except that transmission
speeds up to 2.94 MHz are allowed. Instead of using a stop condition, use repeated start conditions to secure
the bus in HS-mode. A stop condition ends the HS-mode and switches all the internal filters of the device to
support the F/S mode.
t(LOW)
tF
tR
t(HDSTA)
SCL
SDA
t(SUSTO)
t(HDSTA)
t(HIGH) t(SUSTA)
t(HDDAT)
t(SUDAT)
t(BUF)
S
P
P
S
图 26. Bus Timing Diagram
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表 3. Bus Timing Diagram Definitions(1)
FAST MODE
HIGH-SPEED MODE
PARAMETER
MIN
MAX
MIN
MAX
UNIT
SCL operating frequency
f(SCL)
t(BUF)
0.001
0.4
0.001
2.94
MHz
Bus free time between stop and start
conditions
600
100
160
100
ns
ns
Hold time after repeated START condition.
After this period, the first clock is generated.
t(HDSTA)
Repeated start condition setup time
STOP condition setup time
Data hold time
t(SUSTA)
t(SUSTO)
t(HDDAT)
t(SUDAT)
t(LOW)
t(HIGH)
tF
100
100
10
100
100
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
900
100
Data setup time
100
1300
600
20
SCL clock low period
SCL clock high period
Data fall time
200
60
300
300
80
40
40
Clock fall time
tF
Clock rise time
tR
300
Clock/data rise time for SCLK ≤ 100kHz
tR
1000
(1) Values based on a statistical analysis of a one-time sample of devices. Minimum and maximum values are not guaranteed and not
production tested.
7.5.5.4 SMBus Alert Response
The INA226-Q1 is designed to respond to the SMBus Alert Response address. The SMBus Alert Response
provides a quick fault identification for simple slave devices. When an Alert occurs, the master can broadcast the
Alert Response slave address (0001 100) with the Read/Write bit set high. Following this Alert Response, any
slave device that generates an alert identifies itself by acknowledging the Alert Response and sending its
address on the bus.
The Alert Response can activate several different slave devices simultaneously, similar to the I2C General Call. If
more than one slave attempts to respond, bus arbitration rules apply. The losing device does not generate an
Acknowledge and continues to hold the Alert line low until the interrupt is cleared.
7.6 Register Maps
The INA226-Q1 uses
a bank of registers for holding configuration settings, measurement results,
minimum/maximum limits, and status information. 表 4 summarizes the device registers; refer to the Functional
Block Diagram section for an illustration of the registers.
All 16-bit device registers are two 8-bit bytes via the I2C interface.
表 4. Register Set Summary
POINTER
ADDRESS
POWER-ON RESET
BINARY
HEX
REGISTER NAME
FUNCTION
HEX
TYPE(1)
All-register reset, shunt voltage and bus
voltage ADC conversion times and
averaging, operating mode.
00h
Configuration Register
01000001 00100111
4127
R/W
01h
02h
Shunt Voltage Register
Bus Voltage Register
Shunt voltage measurement data.
Bus voltage measurement data.
00000000 00000000
00000000 00000000
0000
0000
R
R
Contains the value of the calculated
power being delivered to the load.
03h
Power Register(2)
00000000 00000000
0000
R
Contains the value of the calculated
current flowing through the shunt
resistor.
04h
Current Register(2)
00000000 00000000
0000
R
(1) Type: R = Read-Only, R/W = Read/Write.
(2) The Current Register (04h) and Power Register (03h) default to '0' because the Calibration register defaults to '0', yielding zero current
and power values until the Calibration register is programmed.
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Register Maps (接下页)
表 4. Register Set Summary (接下页)
POINTER
ADDRESS
POWER-ON RESET
BINARY
HEX
REGISTER NAME
FUNCTION
HEX
TYPE(1)
Sets full-scale range and LSB of current
05h
Calibration Register
and power measurements. Overall
system calibration.
00000000 00000000
0000
R/W
Alert configuration and Conversion
Ready flag.
06h
07h
FEh
FFh
Mask/Enable Register
Alert Limit Register
Manufacturer ID Register
Die ID Register
00000000 00000000
0000
0000
5449
2260
R/W
R/W
R
Contains the limit value to compare to
the selected Alert function.
00000000 00000000
0101010001001001
0010001001100000
Contains unique manufacturer
identification number.
Contains unique die identification
number.
R
7.6.1 Configuration Register (00h) (Read/Write)
表 5. Configuration Register (00h) (Read/Write) Descriptions
BIT NO.
D15
D14 D13 D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BIT
NAME
RST
—
1
—
0
—
0
AVG2
AVG1
AVG0
VBUSCT2 VBUSCT1 VBUSCT0 VSHCT2
VSHCT1
VSHCT0
MODE3 MODE2 MODE1
POR
VALUE
0
0
0
0
1
0
0
1
0
0
1
1
1
The Configuration Register settings control the operating modes for the device. This register controls the
conversion time settings for both the shunt and bus voltage measurements as well as the averaging mode used.
The operating mode that controls what signals are selected to be measured is also programmed in the
Configuration Register .
The Configuration Register can be read from at any time without impacting or affecting the device settings or a
conversion in progress. Writing to the Configuration Register halts any conversion in progress until the write
sequence is completed resulting in a new conversion starting based on the new contents of the Configuration
Register (00h). This halt prevents any uncertainty in the conditions used for the next completed conversion.
RST:
Reset Bit
Bit 15
Setting this bit to '1' generates a system reset that is the same as power-on reset. Resets all registers to default
values; this bit self-clears.
AVG:
Averaging Mode
Bits 9–11
Determines the number of samples that are collected and averaged. 表 6 shows all the AVG bit settings and related
number of averages for each bit setting.
表 6. AVG Bit Settings[11:9] Combinations
AVG2
D11
AVG1
D10
AVG0
D9
NUMBER OF
AVERAGES(1)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
4
16
64
128
256
512
1024
(1) Shaded values are default.
22
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VBUSCT:
Bus Voltage Conversion Time
Bits 6–8
Sets the conversion time for the bus voltage measurement. 表 7 shows the VBUSCT bit options and related
conversion times for each bit setting.
表 7. VBUSCT Bit Settings [8:6] Combinations
VBUSCT2
D8
VBUSCT1
D7
VBUSCT0
D6
CONVERSION
TIME(1)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
140 µs
204 µs
332 µs
588 µs
1.1 ms
2.116 ms
4.156 ms
8.244 ms
(1) Shaded values are default.
VSHCT:
Shunt Voltage Conversion Time
Bits 3–5
Sets the conversion time for the shunt voltage measurement. 表 8 shows the VSHCT bit options and related
conversion times for each bit setting.
表 8. VSHCT Bit Settings [5:3] Combinations
VSHCT2
D8
VSHCT1
D7
VSHCT0
D6
CONVERSION
TIME(1)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
140 µs
204 µs
332 µs
588 µs
1.1 ms
2.116 ms
4.156 ms
8.244 ms
(1) Shaded values are default.
MODE:
Operating Mode
Bits 0-2
Selects continuous, triggered, or power-down mode of operation. These bits default to continuous shunt and bus
measurement mode. The mode settings are shown in 表 9.
表 9. Mode Settings [2:0] Combinations
MODE3
D2
MODE2
D1
MODE1
D0
MODE(1)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Power-Down (or Shutdown)
Shunt Voltage, Triggered
Bus Voltage, Triggered
Shunt and Bus, Triggered
Power-Down (or Shutdown)
Shunt Voltage, Continuous
Bus Voltage, Continuous
Shunt and Bus, Continuous
(1) Shaded values are default.
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7.6.2 Shunt Voltage Register (01h) (Read-Only)
The Shunt Voltage Register stores the current shunt voltage reading, VSHUNT. Negative numbers are represented
in two's complement format. Generate the two's complement of a negative number by complementing the
absolute value binary number and adding 1. An MSB = '1' denotes a negative number.
Example: For a value of VSHUNT = –80 mV:
1. Take the absolute value: 80 mV
2. Translate this number to a whole decimal number (80 mV ÷ 2.5 µV) = 32000
3. Convert this number to binary = 0111 1101 0000 0000
4. Complement the binary result = 1000 0010 1111 1111
5. Add '1' to the complement to create the two's complement result = 1000 0011 0000 0000 = 8300h
If averaging is enabled, this register displays the averaged value.
Full-scale range = 81.92 mV (decimal = 7FFF); LSB: 2.5 μV.
表 10. Shunt Voltage Register (01h) (Read-Only) Description
BIT #
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BIT
NAME
SIGN
SD14
SD13
SD12
SD11
SD10
SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
POR
VALUE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(1)
7.6.3 Bus Voltage Register (02h) (Read-Only)
The Bus Voltage Register stores the most recent bus voltage reading, VBUS.
If averaging is enabled, this register displays the averaged value.
Full-scale range = 40.96 V (decimal = 7FFF); LSB = 1.25 mV.
表 11. Bus Voltage Register (02h) (Read-Only) Description
BIT #
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BIT
NAME
—
BD14
BD13
BD12
BD11
BD10
BD9
BD8
BD7
BD6
BD5
BD4
BD3
BD2
BD1
BD0
POR
VALUE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(1) D15 is always zero because bus voltage can only be positive.
7.6.4 Power Register (03h) (Read-Only)
If averaging is enabled, this register displays the averaged value.
The Power Register LSB is internally programmed to equal 25 times the programmed value of the Current_LSB.
The Power Register records power in Watts by multiplying the decimal values of the Current Register with the
decimal value of the Bus Voltage Register according to 公式 4.
表 12. Power Register (03h) (Read-Only) Description
BIT #
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BIT
NAME
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
POR
VALUE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7.6.5 Current Register (04h) (Read-Only)
If averaging is enabled, this register displays the averaged value.
The value of the Current Register is calculated by multiplying the decimal value in the Shunt Voltage Register
with the decimal value of the Calibration Register, according to 公式 3.
24
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表 13. Current Register (04h) (Read-Only) Register Description
BIT #
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BIT
NAME
CSIGN
CD14
CD13
CD12
CD11
CD10
CD9
CD8
CD7
CD6
CD5
CD4
CD3
CD2
CD1
CD0
POR
VALUE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7.6.6 Calibration Register (05h) (Read/Write)
This register provides the device with the value of the shunt resistor that was present to create the measured
differential voltage. It also sets the resolution of the Current Register. Programming this register sets the
Current_LSB and the Power_LSB. This register is also suitable for use in overall system calibration. See the
Programming the Calibration Register for additional information on programming the Calibration Register.
表 14. Calibration Register (05h) (Read/Write) Description
BIT #
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BIT
NAME
—
FS14
FS13
FS12
FS11
FS10
FS9
FS8
FS7
FS6
FS5
FS4
FS3
FS2
FS1
FS0
POR
VALUE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7.6.7 Mask/Enable Register (06h) (Read/Write)
The Mask/Enable Register selects the function that is enabled to control the Alert pin as well as how that pin
functions. If multiple functions are enabled, the highest significant bit position Alert Function (D15-D11) takes
priority and responds to the Alert Limit Register.
表 15. Mask/Enable Register (06h) (Read/Write)
BIT #
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BIT
NAME
SOL
SUL
BOL
BUL
POL
CNVR
—
—
—
—
—
AFF
CVRF
OVF
APOL
LEN
POR
VALUE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SOL:
Shunt Voltage Over-Voltage
Bit 15
Setting this bit high configures the Alert pin to be asserted if the shunt voltage measurement following a conversion
exceeds the value programmed in the Alert Limit Register.
SUL:
Shunt Voltage Under-Voltage
Bit 14
Setting this bit high configures the Alert pin to be asserted if the shunt voltage measurement following a conversion
drops below the value programmed in the Alert Limit Register.
BOL:
Bus Voltage Over-Voltage
Bit 13
Setting this bit high configures the Alert pin to be asserted if the bus voltage measurement following a conversion
exceeds the value programmed in the Alert Limit Register.
BUL:
Bus Voltage Under-Voltage
Bit 12
Setting this bit high configures the Alert pin to be asserted if the bus voltage measurement following a conversion
drops below the value programmed in the Alert Limit Register.
POL:
Power Over-Limit
Bit 11
Setting this bit high configures the Alert pin to be asserted if the Power calculation made following a bus voltage
measurement exceeds the value programmed in the Alert Limit Register.
CNVR:
Conversion Ready
Bit 10
Setting this bit high configures the Alert pin to be asserted when the Conversion Ready Flag, Bit 3, is asserted
indicating that the device is ready for the next conversion.
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AFF:
Alert Function Flag
Bit 4
While only one Alert Function can be monitored at the Alert pin at a time, the Conversion Ready can also be
enabled to assert the Alert pin. Reading the Alert Function Flag following an alert allows the user to determine if the
Alert Function was the source of the Alert.
When the Alert Latch Enable bit is set to Latch mode, the Alert Function Flag bit clears only when the Mask/Enable
Register is read. When the Alert Latch Enable bit is set to Transparent mode, the Alert Function Flag bit is cleared
following the next conversion that does not result in an Alert condition.
CVRF:
Conversion Ready Flag
Bit 3
Although the device can be read at any time, and the data from the last conversion is available, the Conversion
Ready Flag bit is provided to help coordinate one-shot or triggered conversions. The Conversion Ready Flag bit is
set after all conversions, averaging, and multiplications are complete. Conversion Ready Flag bit clears under the
following conditions:
1.) Writing to the Configuration Register (except for Power-Down selection)
2.) Reading the Mask/Enable Register
OVF:
Math Overflow Flag
Bit 2
This bit is set to '1' if an arithmetic operation resulted in an overflow error. It indicates that current and power data
may be invalid.
APOL:
Alert Polarity bit; sets the Alert pin polarity.
Bit 1
1 = Inverted (active-high open collector)
0 = Normal (active-low open collector) (default)
LEN:
Alert Latch Enable; configures the latching feature of the Alert pin and Alert Flag bits.
Bit 0
1 = Latch enabled
0 = Transparent (default)
When the Alert Latch Enable bit is set to Transparent mode, the Alert pin and Flag bit resets to the idle states when
the fault has been cleared. When the Alert Latch Enable bit is set to Latch mode, the Alert pin and Alert Flag bit
remains active following a fault until the Mask/Enable Register has been read.
7.6.8 Alert Limit Register (07h) (Read/Write)
The Alert Limit Register contains the value used to compare to the register selected in the Mask/Enable Register
to determine if a limit has been exceeded.
表 16. Alert Limit Register (07h) (Read/Write) Description
BIT #
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BIT
NAME
AUL15
AUL14
AUL13
AUL12
AUL11
AUL10
AUL9
AUL8
AUL7
AUL6
AUL5
AUL4
AUL3
AUL2
AUL1
AUL0
POR
VALUE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7.6.9 Manufacturer ID Register (FEh) (Read-Only)
The Manufacturer ID Register stores a unique identification number for the manufacturer.
表 17. Manufacturer ID Register (FEh) (Read-Only) Description
BIT #
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BIT
NAME
ID15
ID14
ID13
ID12
ID11
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
POR
VALUE
0
1
0
1
0
1
0
0
0
1
0
0
1
0
0
1
ID:
Manufacturer ID Bits
Stores the manufacturer identification bits
Bits 0-15
26
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7.6.10 Die ID Register (FFh) (Read-Only)
The Die ID Register stores a unique identification number and the revision ID for the die.
表 18. Die ID Register (FFh) (Read-Only) Description
BIT #
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BIT
NAME
DID11
DID10
DID9
DID8
DID7
DID6
DID5
DID4
DID3
DID2
DID1
DID0
RID3
RID2
RID1
RID0
POR
VALUE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DID:
Device ID Bits
Bits 4-15
Stores the device identification bits
RID:
Die Revision ID Bits
Bit 0-3
Stores the device revision identification bits
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Validate and test
the design implementation to confirm system functionality.
8.1 Application Information
The INA226-Q1 is a current shunt and power monitor with an I2C™ compatible interface. The device monitors
both a shunt voltage drop and bus supply voltage. Programmable calibration value, conversion times, and
averaging, combined with an internal multiplier, enable direct readouts of current in amperes and power in watts.
8.2 Typical Applications
8.2.1 High-Side Sensing Circuit Application
CBYPASS
+12-V Supply
0.1 µF
Pullup Resistors
VS
(Supply Voltage)
VBUS
SDA
SCL
Power Register
Current Register
Voltage Register
Alert Register
´
V
I
I2C
Interface
VIN+
ADC
RSHUNT
Alert
A0
2 mW
VIN-
A1
10-A
Load
GND
图 27. Typical Circuit Configuration, INA226-Q1
8.2.1.1 Design Requirements
INA226-Q1 measures the voltage developed across a current-sensing resistor (RSHUNT) when current passes
through it. The device also measures the bus supply voltage and can calculate power when calibrated. It comes
with alert capability where the alert pin can be programmed to respond to a user-defined event or to a conversion
ready notification. This design illustrates the ability of the alert pin to respond to a set threshold.
28
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Typical Applications (接下页)
8.2.1.2 Detailed Design Procedure
The Alert pin can be configured to respond to one of the five alert functions described in the Alert Pin section.
The alert pin must to be pulled up to the VVS pin voltage via the pull-up resistors. The configuration register is set
based on the required conversion time and averaging. The Mask/Enable Register is set to identify the required
alert function and the Alert Limit Register is set to the limit value used for comparison.
8.2.1.3 Application Curves
图 28 shows the Alert pin response to a shunt voltage over-limit of 80 mV for a conversion time (tCT) of 1.1 ms
and averaging set to 1. 图 29 shows the response for the same limit but with the conversion time reduced to 140
µs.
ALERT
INPUT
LIMIT
ALERT
INPUT
LIMIT
Time (20 Ps/div)
Time (200 Ps/div)
D002
D002
See 表 19
See 表 21
tCT = 1.1 ms
See 表 20
See 表 21
tCT = 140 µs
See 表 22
See 表 22
图 28. Alert Response
图 29. Alert Response
表 19. Configuration Register (00h) Settings for 图 28 (Value = 4025h)
BIT #
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BIT
NAME
VBUSC
T2
VBUSC VBUSC
RST
—
—
—
AVG2
AVG1
AVG0
VSHCT2 VSHCT1 VSHCT0 MODE3 MODE2 MODE1
T1
0
T0
0
POR
VALUE
0
1
0
0
0
0
0
0
1
0
0
1
0
1
表 20. Configuration Register (00h) Settings for 图 29 (Value = 4005h)
BIT #
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BIT
NAME
VBUSC
T2
VBUSC VBUSC
RST
—
—
—
AVG2
AVG1
AVG0
VSHCT2 VSHCT1 VSHCT0 MODE3 MODE2 MODE1
T1
0
T0
0
POR
VALUE
0
1
0
0
0
0
0
0
0
0
0
1
0
1
表 21. Mask/Enable Register (06h) Settings for 图 28 and 图 29 (Value = 8000h)
BIT #
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BIT
NAME
SOL
SUL
BOL
BUL
POL
CNVR
—
—
—
—
—
AFF
CVRF
OVF
APOL
LEN
POR
VALUE
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
表 22. Alert Limit Register (07h) Settings for 图 28 and 图 29 (Value = 7D00)
BIT #
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BIT
NAME
AUL15
AUL14
AUL13
AUL12
AUL11
AUL10
AUL9
AUL8
AUL7
AUL6
AUL5
AUL4
AUL3
AUL2
AUL1
AUL0
POR
VALUE
0
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
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9 Power Supply Recommendations
The input circuitry of the device can accurately measure signals on common-mode voltages beyond its power
supply voltage, VVS. For example, the voltage applied to the VVS power supply terminal can be 5 V, whereas the
load power-supply voltage being monitored (the common-mode voltage) can be as high as 36 V. Note also that
the device can withstand the full 0-V to 36-V range at the input terminals, regardless of whether the device has
power applied or not.
Place the required power-supply bypass capacitors as close as possible to the supply and ground terminals of
the device to ensure stability. A typical value for this supply bypass capacitor is 0.1 μF. Applications with noisy or
high-impedance power supplies may require additional decoupling capacitors to reject power-supply noise.
10 Layout
10.1 Layout Guidelines
Connect the input pins (IN+ and IN-) to the sensing resistor using a Kelvin connection or a 4-wire connection.
These connection techniques ensure that only the current-sensing resistor impedance is detected between the
input pins. Poor routing of the current-sensing resistor commonly results in additional resistance present between
the input pins. Given the very low ohmic value of the current-sensing resistor, any additional high-current carrying
impedance causes significant measurement errors. Place the power-supply bypass capacitor as close as
possible to the supply and ground pins.
10.2 Layout Example
A1
IN+
IN±
Sense/Shunt
Resistor
A0
(1)
Alert
SDA
SCL
VBUS
GND
VS
Alert output
(Can be left floating if unused)
2
Supply bypass
capacitor
I C/SMBUS
interface
Via to Ground Plane
Via to Power Plane
(1) connect the VBUS pin to the power supply rail.
图 30. INA226-Q1 Layout Example
30
版权 © 2015, Texas Instruments Incorporated
INA226-Q1
www.ti.com.cn
ZHCSE07 –JULY 2015
11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
•
《INA226EVM 评估板和软件教程》（文献编号：SBOU113）
11.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 商标
E2E is a trademark of Texas Instruments.
I2C is a trademark of NXP Semiconductors.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不
对本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2015, Texas Instruments Incorporated
31
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JESD48 最新标准中止提供任何产品和服务。客户在下订单前应获取最新的相关信息, 并验证这些信息是否完整且是最新的。所有产品的销售
都遵循在订单确认时所提供的TI 销售条款与条件。
TI 保证其所销售的组件的性能符合产品销售时 TI 半导体产品销售条件与条款的适用规范。仅在 TI 保证的范围内，且 TI 认为 有必要时才会使
用测试或其它质量控制技术。除非适用法律做出了硬性规定，否则没有必要对每种组件的所有参数进行测试。
TI 对应用帮助或客户产品设计不承担任何义务。客户应对其使用 TI 组件的产品和应用自行负责。为尽量减小与客户产品和应 用相关的风险，
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在转售 TI 组件或服务时，如果对该组件或服务参数的陈述与 TI 标明的参数相比存在差异或虚假成分，则会失去相关 TI 组件 或服务的所有明
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对 TI 及其代理造成的任何损失。
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TI 组件未获得用于 FDA Class III（或类似的生命攸关医疗设备）的授权许可，除非各方授权官员已经达成了专门管控此类使 用的特别协议。
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IMPORTANT NOTICE
邮寄地址： 上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122
Copyright © 2015, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
INA226AQDGSRQ1
ACTIVE
VSSOP
DGS
10
2500 RoHS & Green
NIPDAUAG
Level-2-250C-1 YEAR
-40 to 125
226Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
DGS0010A
VSSOP - 1.1 mm max height
S
C
A
L
E
3
.
2
0
0
SMALL OUTLINE PACKAGE
C
SEATING PLANE
0.1 C
5.05
4.75
TYP
PIN 1 ID
AREA
A
8X 0.5
10
1
3.1
2.9
NOTE 3
2X
2
5
6
0.27
0.17
10X
3.1
2.9
1.1 MAX
0.1
C A
B
B
NOTE 4
0.23
0.13
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.7
0.4
0 - 8
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
www.ti.com
EXAMPLE BOARD LAYOUT
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
(R0.05)
TYP
SYMM
10X (0.3)
1
5
10
SYMM
6
8X (0.5)
(4.4)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221984/A 05/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
SYMM
(R0.05) TYP
10X (0.3)
8X (0.5)
1
5
10
SYMM
6
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221984/A 05/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
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担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
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束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2020 德州仪器半导体技术（上海）有限公司
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