INA229AQDGSRQ1 [TI]
INA229-Q1 AEC-Q100, 85-V, 20-Bit, Ultra-Precise Power/Energy/Charge Monitor With SPI Interface;
| 型号： | INA229AQDGSRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | INA229-Q1 AEC-Q100, 85-V, 20-Bit, Ultra-Precise Power/Energy/Charge Monitor With SPI Interface |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INA229-Q1
SLYS024A – MAY 2020 – REVISED JUNE 2021
INA229-Q1 AEC-Q100, 85-V, 20-Bit, Ultra-Precise Power/Energy/Charge Monitor With
SPI Interface
1 Features
3 Description
•
AEC-Q100 qualified for automotive applications:
– Temperature grade 1: –40°C to +125°C, TA
Functional Safety-Capable
– Documentation available to aid functional safety
system design
The INA229-Q1 is an ultra-precise digital power
monitor with a 20-bit delta-sigma ADC specifically
designed for current-sensing applications. The device
can measure a full-scale differential input of ±163.84
mV or ±40.96 mV across a resistive shunt sense
element with common-mode voltage support from –
0.3 V to +85 V.
•
•
•
High-resolution, 20-bit delta-sigma ADC
Current monitoring accuracy:
– Offset voltage: ±1 µV (maximum)
– Offset drift: ±0.01 µV/°C (maximum)
– Gain error: ±0.05% (maximum)
– Gain error drift: ±20 ppm/°C (maximum)
– Common mode rejection: 154 dB (minimum)
Power monitoring accuracy:
The INA229-Q1 reports current, bus voltage,
temperature, power, energy and charge accumulation
while employing
a
precision ±0.5% integrated
oscillator, all while performing the needed calculations
in the background. The integrated temperature sensor
is ±1°C accurate for die temperature measurement
and is useful in monitoring the system ambient
temperature.
•
•
– 0.5% full scale, –40°C to +125°C (maximum)
Energy and charge accuracy:
– 1.0% full scale (maximum)
Fast alert response: 75 μs
Wide common-mode range: –0.3 V to +85 V
Bus voltage sense input: 0 V to 85 V
Shunt full-scale differential range:
The low offset and gain drift design of the INA229-
Q1 allows the device to be used in precise systems
that do not undergo multi-temperature calibration
during manufacturing. Further, the very low offset
voltage and noise allow for use in mA to kA
sensing applications and provide a wide dynamic
range without significant power dissipation losses
on the sensing shunt element. The low input bias
current of the device permits the use of larger current-
sense resistors, thus providing accurate current
measurements in the micro-amp range.
•
•
•
•
±163.84 mV / ±40.96 mV
•
•
•
•
•
•
Input bias current: 2.5 nA (maximum)
Temperature sensor: ±1°C (maximum at 25°C)
Programmable resistor temperature compensation
Programmable conversion time and averaging
10-MHz SPI communication interface
Operates from a 2.7-V to 5.5-V supply:
– Operational current: 640 µA (typical)
– Shutdown current: 5 µA (maximum)
The device allows for selectable ADC conversion
times from 50 µs to 4.12 ms as well as sample
averaging from 1x to 1024x, which further helps
reduce the noise of the measured data.
2 Applications
Device Information(1)
•
•
•
•
Automotive battery management systems
EV / HEV mA - KA sense applications
DC/DC converters and power inverters
ADAS domain controllers
PART NUMBER
PACKAGE
BODY SIZE (NOM)
INA229-Q1
VSSOP (10)
3.00 mm × 3.00 mm
(1) For all available packages, see the package option
addendum at the end of the data sheet.
VS
Power
Reference
IN+
IN-
SCLK
Voltage Current
Power Energy
Charge Temp
MOSI
MISO
CS
20 Bit
ADC
MUX
SPI
VBUS
+
Oscillator
Out-of-range
Threshold
ALERT
œ
GND
Simplified Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
INA229-Q1
SLYS024A – MAY 2020 – REVISED JUNE 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 3
6.1 Absolute Maximum Ratings ....................................... 3
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................4
6.5 Electrical Characteristics ............................................5
6.6 Timing Requirements (SPI) ........................................7
6.7 Timing Diagram ..........................................................7
6.8 Typical Characteristics................................................8
7 Detailed Description......................................................12
7.1 Overview...................................................................12
7.2 Functional Block Diagram.........................................12
7.3 Feature Description...................................................12
7.4 Device Functional Modes..........................................18
7.5 Programming............................................................ 18
7.6 Register Maps...........................................................20
8 Application and Implementation..................................30
8.1 Application Information............................................. 30
8.2 Typical Application.................................................... 35
9 Power Supply Recommendations................................39
10 Layout...........................................................................39
10.1 Layout Guidelines................................................... 39
10.2 Layout Example...................................................... 39
11 Device and Documentation Support..........................40
11.1 Receiving Notification of Documentation Updates..40
11.2 Support Resources................................................. 40
11.3 Trademarks............................................................. 40
11.4 Electrostatic Discharge Caution..............................40
11.5 Glossary..................................................................40
12 Mechanical, Packaging, and Orderable
Information.................................................................... 40
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (May 2020) to Revision A (June 2021)
Page
•
•
•
•
Changed data sheet status from: Advanced Information to: Production Data....................................................1
Added Functional Safety bullets......................................................................................................................... 1
Updated the numbering format for tables, figures, and cross-references throughout the document..................1
Updated the figures and equations throughput the document to align with the commercial data sheet.............1
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5 Pin Configuration and Functions
CS
MOSI
1
2
3
4
5
10
9
IN+
IN–
ALERT
MISO
8
VBUS
GND
VS
7
SCLK
6
Not to scale
Figure 5-1. DGS Package 10-Pin VSSOP Top View
Table 5-1. Pin Functions
PIN
TYPE
DESCRIPTION
NO.
1
NAME
CS
Digital input
Digital input
Digital output
Digital output
Digital input
Power supply
Ground
SPI chip select (Active Low).
SPI digital data input.
2
MOSI
ALERT
MISO
SCLK
VS
3
Open-drain alert output, default state is active low.
SPI digital data output (push-pull).
SPI clock input.
4
5
6
Power supply, 2.7 V to 5.5 V.
Ground.
7
GND
VBUS
8
Analog input
Bus voltage input.
Negative input to the device. For high-side applications, connect to load side of sense resistor. For
low-side applications, connect to ground side of sense resistor.
9
IN–
IN+
Analog input
Analog input
Positive input to the device. For high-side applications, connect to power supply side of sense
resistor. For low-side applications, connect to load side of sense resistor.
10
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
V
VS
Supply voltage
6
40
Differential (VIN+) – (VIN–
)
–40
–0.3
V
(2)
VIN+, VIN–
Common-mode
85
V
VVBUS
VIO
–0.3
85
V
MOSI, MISO, SCLK, ALERT
Input current into any pin
Digital output current
GND – 0.3
vs. + 0.3
5
V
IIN
mA
mA
°C
°C
IOUT
TJ
10
Junction temperature
Storage temperature
150
150
Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) VIN+ and VIN– are the voltages at the IN+ and IN– pins, respectively.
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6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per AEC Q100-002, all pins(1) HBM
ESD Classification Level 2
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per AEC Q100-011, all pins CDM
ESD Classification Level C6
±1000
(1) AEC Q100-002 indicated that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
–0.3
2.7
NOM
MAX
85
UNIT
V
VCM
VS
Common-mode input range
Operating supply range
Ambient temperature
5.5
V
TA
–40
125
°C
6.4 Thermal Information
INA229-Q1
THERMAL METRIC(1)
DGS
10 PINS
177.6
66.4
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
99.5
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
9.7
YJB
97.6
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
at TA = 25 °C, VS = 3.3 V, VSENSE = VIN+ – VIN– = 0 V, VCM = VIN– = 48 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
INPUT
VCM
Common-mode input range
Bus voltage input range
Common-mode rejection
TA = –40 °C to +125 °C
–0.3
0
85
85
V
VVBUS
CMRR
V
–0.3 V < VCM < 85 V, TA = –40 °C to +125 °C
TA = –40 °C to +125 °C, ADCRANGE = 0
TA = –40 °C to +125 °C, ADCRANGE = 1
VCM = 48 V, TCT > 280 µs
154
170
dB
mV
mV
µV
µV
–163.84
–40.96
163.84
40.96
±1
VDIFF
Shunt voltage input range
Shunt offset voltage
±0.3
±0.3
±2
Vos
VCM = 0 V, TCT > 280 µs
±1
dVos/dT Shunt offset voltage drift
TA = –40 °C to +125 °C
±10 nV/°C
PSRR
Shunt offset voltage vs. power supply VS = 2.7 V to 5.5 V, TA = –40 °C to +125 °C
±0.05
±1
±0.5
±2.5
µV/V
mV
Vos_bus
VBUS offset voltage
VBUS = 20 mV
dVos/dT VBUS offset voltage drift
TA = –40 °C to +125 °C
VS = 2.7 V to 5.5 V
±4
±20 µV/°C
mV/V
PSRR
IB
VBUS offset voltage vs. power supply
±0.25
0.1
Input bias current
Either input, IN+ or IN–, VCM = 85 V
Active mode
2.5
1.2
nA
MΩ
nA
ZVBUS
IVBUS
RDIFF
VBUS pin input impedance
VBUS pin leakage current
Input differential impedance
0.8
1
Shutdown mode, VBUS = 85 V
Active mode, VIN+ – VIN– < 164 mV
10
92
kΩ
DC ACCURACY
GSERR
Shunt voltage gain error
VCM = 24 V
±0.01
±0.01
±0.05
%
GS_DRFT Shunt voltage gain error drift
±20 ppm/°C
GBERR
GB_DRFT VBUS voltage gain error drift
VBUS voltage gain error
±0.05
%
±20 ppm/°C
PTME
ETME
Power total measurment error (TME)
Energy and charge TME
ADC resolution
TA = –40 °C to +125 °C, at full scale
at full scale power
±0.5
±1
%
%
20
312.5
78.125
195.3125
7.8125
50
Bits
nV
Shunt voltage, ADCRANGE = 0
Shunt voltage, ADCRANGE = 1
Bus voltage
nV
1 LSB step size
µV
Temperature
m°C
Conversion time field = 0h
Conversion time field = 1h
Conversion time field = 2h
Conversion time field = 3h
Conversion time field = 4h
Conversion time field = 5h
Conversion time field = 6h
Conversion time field = 7h
84
150
280
TCT
ADC conversion-time(1)
µs
540
1052
2074
4120
±2
INL
Integral Non-Linearity
m%
LSB
DNL
Differential Non-Linearity
0.2
CLOCK SOURCE
FOSC
Internal oscillator frequency
1
MHz
%
TA = 25 °C
±0.5
±1
FOSC_TOL Internal oscillator frequency tolerance
TA = –40 °C to +125 °C
%
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6.5 Electrical Characteristics (continued)
at TA = 25 °C, VS = 3.3 V, VSENSE = VIN+ – VIN– = 0 V, VCM = VIN– = 48 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
TEMPERATURE SENSOR
Measurement range
–40
+125
±1
°C
°C
°C
TA = 25 °C
±0.15
±0.2
Temperature accuracy
TA = –40 °C to +125 °C
±2
POWER SUPPLY
VS
Supply voltage
2.7
5.5
750
1.1
5
V
VSENSE = 0 V
640
µA
mA
µA
IQ
Quiescent current
VSENSE = 0 V, TA = –40 °C to +125 °C
Shuntdown mode
IQSD
TPOR
Quiescent current, shutdown
Device start-up time
2.8
300
60
Power-up (NPOR)
µs
From shutdown mode
DIGITAL INPUT / OUTPUT
VIH
VIL
Logic input level, high
Logic input level, low
Logic output level, low
Logic output level, high
1.2
GND
VS
0.4
0.4
VS
1
V
V
VOL
VOH
IOL = 1 mA
IOL = 1 mA
0 ≤ VIN ≤ VS
GND
V
VS – 0.4
–1
V
IIO_LEAK Digital leakage input current
µA
(1) Subject to oscillator accuracy and drift
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6.6 Timing Requirements (SPI)
MIN
NOM
MAX
UNIT
SERIAL INTERFACE
fSPI
SPI bit frequency
10
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCLK_H
SCLK high time
40
40
10
10
50
tSCLK_L
SCLK low time
tCSF_SCLKR
tSCLKF_CSR
tFRM_DLY
tMOSI_RF
tMOSI_ST
tMOSI_HLD
tMISO_RF
tMISO_ST
tMISO_HLD
tCS_MISO_DLY
tCS_MISO_HIZ
CS fall to first SCLK rise time
Last SCLK fall to CS rise time
Sequential transfer delay (1)
MOSI Rise and Fall time, 10 MHz SCLK
MOSI data setup time
15
15
10
20
MOSI data hold time
MISO Rise and Fall time, CLOAD = 200 pF
MISO data setup time
20
20
MISO data hold time
CS falling edge to MISO data valid delay time
CS rising edge to MISO high impedance delay time
25
25
(1) Optional. The SPI interface can operate without the CS pin assistance as long as the pin is held low.
6.7 Timing Diagram
tFRM_DLY
CS
tSCLK_L
tCSF_SCLKR
tSCLK_H
tSCLK_L
tSCLKF_CSR
SCLK
MOSI
MISO
tMOSI_RF
tMOSI_ST tMOSI_HLD
undefined
MSB
undefined
LSB
LSB
tCS_MISO_HIZ
tMISO_RF
High-Z
MSB
High-Z
X
tMISO_HLD
tCS_MISO_DLY
tMISO_ST
Figure 6-1. SPI Timing Diagram
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6.8 Typical Characteristics
at TA = 25 °C, VVS = 3.3 V, VCM = 48 V, VSENSE = 0, and VVBUS = 48 V (unless otherwise noted)
VCM = 48 V
VCM = 0 V
Figure 6-2. Shunt Input Offset Voltage Production Distribution
Figure 6-3. Shunt Input Offset Voltage Production Distribution
Figure 6-4. Shunt Input Offset Voltage vs. Temperature
Figure 6-5. Common-Mode Rejection Ratio Production
Distribution
Figure 6-6. Shunt Input Common-Mode Rejection Ratio vs.
Temperature
VCM = 24 V
Figure 6-7. Shunt Input Gain Error Production Distribution
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6.8 Typical Characteristics (continued)
at TA = 25 °C, VVS = 3.3 V, VCM = 48 V, VSENSE = 0, and VVBUS = 48 V (unless otherwise noted)
Figure 6-9. Shunt Input Gain Error vs. Common-Mode Voltage
VCM = 24 V
Figure 6-8. Shunt Input Gain Error vs. Temperature
VVBUS = 20 mV
VVBUS = 20 mV
Figure 6-11. Bus Input Offset Voltage vs. Temperature
Figure 6-10. Bus Input Offset Voltage Production Distribution
Figure 6-12. Bus Input Gain Error Production Distribution
Figure 6-13. Bus Input Gain Error vs. Temperature
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6.8 Typical Characteristics (continued)
at TA = 25 °C, VVS = 3.3 V, VCM = 48 V, VSENSE = 0, and VVBUS = 48 V (unless otherwise noted)
Figure 6-14. Input Bias Current vs. Differential Input Voltage
Figure 6-15. Input Bias Current (IB+ or IB–) vs. Common-Mode
Voltage
Figure 6-16. Input Bias Current vs. Temperature
Figure 6-17. Input Bias Current vs. Temperature, Shutdown
Figure 6-18. Active IQ vs. Temperature
Figure 6-19. Active IQ vs. Supply Voltage
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6.8 Typical Characteristics (continued)
at TA = 25 °C, VVS = 3.3 V, VCM = 48 V, VSENSE = 0, and VVBUS = 48 V (unless otherwise noted)
Figure 6-21. Shutdown IQ vs. Temperature
Figure 6-20. Shutdown IQ vs. Supply Voltage
Figure 6-22. Active IQ vs. Clock Frequency
Figure 6-23. Shutdown IQ vs. Clock Frequency
Figure 6-25. Internal Clock Frequency vs. Temperature
Figure 6-24. Internal Clock Frequency vs. Power Supply
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7 Detailed Description
7.1 Overview
The INA229-Q1 device is a digital current sense amplifier with a 4-wire SPI digital interface. It measures shunt
voltage, bus voltage and internal temperature while calculating current, power, energy and charge necessary for
accurate decision making in precisely controlled systems. Programmable registers allow flexible configuration for
measurement precision as well as continuous or triggered operation. Detailed register information is found in
Section 7.6.
7.2 Functional Block Diagram
VS
Power
Reference
IN+
IN-
SCLK
MOSI
MISO
CS
Voltage Current
Power Energy
20 Bit
ADC
MUX
SPI
VBUS
Charge
Temp
+
Oscillator
Out-of-range
Threshold
ALERT
œ
GND
7.3 Feature Description
7.3.1 Versatile High Voltage Measurement Capability
The INA229-Q1 operates off a 2.7 V to 5.5 V supply but can measure voltage and current on rails as high as
85 V. The current is measured by sensing the voltage drop across a external shunt resistor at the IN+ and IN–
pins. The input stage of the INA229-Q1 is designed such that the input common-mode voltage can be higher
than the device supply voltage, VS. The supported common-mode voltage range at the input pins is –0.3 V to
+85 V, which makes the device well suited for both high-side and low-side current measurements. There are no
special considerations for power-supply sequencing because the common-mode input range and device supply
voltage are independent of each other; therefore, the bus voltage can be present with the supply voltage off, and
vice-versa without damaging the device.
The device also measures the bus supply voltage through the VBUS pin and temperature through the integrated
temperature sensor. The differential shunt voltage is measured between the IN+ and IN– pins, while the bus
voltage is measured with respect to device ground. Monitored bus voltages can range from 0 V to 85 V, while
monitored temperatures can range from -40 ºC to +125 ºC.
Shunt voltage, bus voltage, and temperature measurements are multiplexed internally to a single ADC as shown
in Figure 7-1.
ADCp
ADCn
Bus Voltage
VBUS
Shunt Voltage
Internal Temp.
IN+
IN-
ADC_IN+
To ADC Input
ADC_IN-
Vs
PTAT Temp.
Sensor
MUX digital
Control
Figure 7-1. High-Voltage Input Multiplexer
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7.3.2 Internal Measurement and Calculation Engine
The current and charge are calculated after a shunt voltage measurement, while the power and energy are
calculated after a bus voltage measurement. Power and energy are calculated based on the previous current
calculation and the latest bus voltage measurement. If the value loaded into the SHUNT_CAL register is zero,
the power, energy and charge values will be reported as zero.
The current, voltage, and temperature values are immediate results when the number of averages is set to one
as shown in Figure 7-2. However, when averaging is used, each ADC measurement is an intermediate result
which is stored in the corresponding averaging registers. Following every ADC sample, the newly-calculated
values for current, voltage, and temperature are appended to their corresponding averaging registers until the
set number of averages is achieved. After all of the samples have been measured the average current and
voltage is determined, the power is calculated and the results are loaded to the corresponding output registers
where they can then be read.
The energy and charge values are accumulated for each conversion cycle. Therefore the INA229-Q1 averaging
function is not applied to these.
Calculations for power, charge and energy are performed in the background and do not add to the overall
conversion time.
ADC,
Temperature, Current,
Voltage
i
v
i
v
T
T
i
v
T
i
v
T
T
i
v
i
T
p1
Power register
Charge register
p2
p3
p4
p5
Q1 =
i1 x t1
Q.. =
i.. x t..
Q.. =
i.. x t..
Q.. =
i.. x t..
Q.. =
i.. x t..
E1 =
p1 x t2
E.. =
p.. x t..
E.. =
p.. x t..
E.. =
p.. x t..
E.. =
p.. x t..
Energy register
Figure 7-2. Power, Energy and Charge Calculation Scheme
7.3.3 Low Bias Current
The INA229-Q1 features very low input bias current which provides several benefits. The low input bias current
of the INA229-Q1 reduces the current consumed by the device in both active and shutdown state. Another
benefit of low bias current is that it allows the use of input filters to reject high-frequency noise before the signal
is converted to digital data. In traditional digital current-sense amplifiers, the addition of input filters comes at
the cost of reduced accuracy. However, as a result of the low bias current, the reduction in accuracy due to
input filters is minimized. An additional benefit of low bias current is the ability to use a larger shunt resistor to
accurately sense smaller currents. Use of a larger value for the shunt resistor allows the device to accurately
monitor currents in the sub-mA range.
The bias current in the INA229-Q1 is the smallest when the sensed current is zero. As the current starts to
increase, the differential voltage drop across the shunt resistor increases which results in an increase in the bias
current as shown in Input Bias Current vs. Differential Input Voltage.
7.3.4 High-Precision Delta-Sigma ADC
The integrated ADC is a high-performance, low-offset, low-drift, delta-sigma ADC designed to support
bidirectional current flow at the shunt voltage measurement channel. The measured inputs are selected through
the high-voltage input multiplexer to the ADC inputs as shown in Figure 7-1. The ADC architecture enables
lower drift measurement across temperature and consistent offset measurements across the common-mode
voltage, temperature, and power supply variations. A low-offset ADC is preferred in current sensing applications
to provide a near 0-V offset voltage that maximizes the useful dynamic range of the system.
The INA229-Q1 can measure the shunt voltage, bus voltage, and die temperature, or a combination of any
based on the selected MODE bits setting in the ADC_CONFIG register. This permits selecting modes to convert
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only the shunt voltage or bus voltage to further allow the user to configure the monitoring function to fit the
specific application requirements. When no averaging is selected, once an ADC conversion is completed, the
converted values are independently updated in their corresponding registers where they can be read through
the digital interface at the time of conversion end. The conversion time for shunt voltage, bus voltage, and
temperature inputs are set independently from 50 µs to 4.12ms depending on the values programmed in the
ADC_CONFIG register. Enabled measurement inputs are converted sequentially so the total time to convert
all inputs depends on the conversion time for each input and the number of inputs enabled. When averaging
is used, the intermediate values are subsequently stored in an averaging accumulator, and the conversion
sequence repeats until the number of averages is reached. After all of the averaging has been completed, the
final values are updated in the corresponding registers that can then be read. These values remain in the data
output registers until they are replaced by the next fully completed conversion results. In this case, reading the
data output registers does not affect a conversion in progress.
The ADC has two conversion modes—continuous and triggered—set by the MODE bits in ADC_CONFIG
register. In continuous-conversion mode, the ADC will continuously convert the input measurements and update
the output registers as described above in an indefinite loop. In triggered-conversion mode, the ADC will convert
the input measurements as described above, after which the ADC will go into shutdown mode until another
single-shot trigger is generated by writing to the MODE bits. Writing the MODE bits will interrupt and restart
triggered or continuous conversions that are in progress. Although the device can be read at any time, and
the data from the last conversion remains available, the Conversion Ready flag (CNVRF bit in DIAG_ALRT
register) is provided to help coordinate triggered conversions. This bit is set after all conversions and averaging
is completed.
The Conversion Ready flag (CNVRF) clears under these conditions:
•
•
Writing to the ADC_CONFIG register (except for selecting shutdown mode); or
Reading the DIAG_ALRT Register
While the INA229-Q1 device is used in either one of the conversion modes, a dedicated digital engine is
calculating the current, power, charge and energy values in the background as described in Section 7.3.2. In
triggered mode, the accumulation registers (ENERGY and CHARGE) are invalid, as the device does not keep
track of elapsed time. For applications that need critical measurements in regards to accumulation of time for
energy and charge measurements, the device must be configured to use continuous conversion mode, as the
accumulated results are continuously updated and can provide true system representation of charge and energy
consumption in a system. All of the calculations are performed in the background and do not contribute to
conversion time.
For applications that must synchronize with other components in the system, the INA229-Q1 conversion can be
delayed by programming the CONVDLY bits in CONFIG register in the range between 0 (no delay) and 510
ms. The resolution in programming the conversion delay is 2 ms. The conversion delay is set to 0 by default.
Conversion delay can assist in measurement synchronization when multiple external devices are used for
voltage or current monitoring purposes. In applications where an time aligned voltage and current measurements
are needed, two devices can be used with the current measurement delayed such that the external voltage and
current measurements will occur at approximately the same time. Keep in mind that even though the internal
time base for the ADC is precise, synchronization will be lost over time due to internal and external time base
mismatch.
7.3.4.1 Low Latency Digital Filter
The device integrates a low-pass digital filter that performs both decimation and filtering on the ADC output
data, which helps with noise reduction. The digital filter is automatically adjusted for the different output data
rates and always settles within one conversion cycle. The user has the flexibility to choose different output
conversion time periods TCT from 50 µs to 4.12 ms. With this configuration the first amplitude notch appears
at the Nyquist frequency of the output signal which is determined by the selected conversion time period and
defined as fNOTCH= 1 / (2 x TCT). This means that the filter cut-off frequency will scale proportionally with the data
output rate as described. ADC Frequency Response shows the filter response when the 1.052 ms conversion
time period is selected.
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0
−10
−20
−30
−40
−50
−60
1
10
100 1k
Frequency (Hz)
10k
100k
G001
Conversion time = 1.052 ms, single
conversion only
Figure 7-3. ADC Frequency Response
7.3.4.2 Flexible Conversion Times and Averaging
ADC conversion times for shunt voltage, bus voltage and temperature can be set independently from 50 μs to
4.12 ms. The flexibility in conversion time allows for robust operation in a variety of noisy environments. The
device also allows for programmable averaging times from a single conversion all the way to an average of
1024 conversions. The amount of averaging selected applies uniformly to all active measurement inputs. The
ADC_CONFIG register shown in Table 7-6 provides additional details on the supported conversion times and
averaging modes. The INA229-Q1 effective resolution of the ADC can be increased by increasing the conversion
time and increasing the number of averages. Figure 7-4 and Figure 7-5 shown below illustrate the effect of
conversion time and averaging on a constant input signal.
Figure 7-4. Noise vs Conversion Time (Averaging = 1)
Figure 7-5. Noise vs. Conversion Time (Averaging = 128)
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Settings for the conversion time and number of conversions averaged impact the effective measurement
resolution. For more detailed information on how averaging reduces noise and increases the effective number of
bits (ENOB) see Section 8.1.3.
7.3.5 Shunt Resistor Drift Compensation
The INA229-Q1 device has an internal temperature sensor which can measure die temperature from –40 °C
to +125 °C. The accuracy of the temperature sensor is ±2 °C across the operational temperature range. The
temperature value is stored inside the DIETEMP register and can be read through the digital interface.
The device has the capability to utilize the temperature measurement to compensate for shunt resistor
temperature variance. This feature can be enabled by setting the TEMPCOMP bit in the CONFIG register, while
the SHUNT_TEMPCO is the register that can be programmed to enter the temperature coefficient of the used
shunt. The full scale value of the SHUNT_TEMPCO register is 16384 ppm/°C. The temperature compensation
is referenced to +25 °C . The shunt is always assumed to have a positive temperature coefficient and the
temperature compensation follows Equation 1:
RNOM x (DIETEMP - 25) x SHUNT_TEMPCO
RADJ = RNOM
+
106
(1)
where
•
•
•
RNOM is the nominal shunt resistance in Ohms at 25 °C.
DIETEMP is the temperature value in the DIETEMP register in °C.
SHUNT_TEMPCO is the shunt temperature coefficient in ppm/°C.
When this feature is enabled and correctly programmed, the CURRENT register data is corrected by constantly
monitoring the die temperature and becomes a function of temperature. The effectiveness of the compensation
will depend on how well the resistor and the INA229-Q1 are thermally coupled since the die temperature of the
INA229-Q1 is used for the compensation.
Note
Warning: If temperature compensation is enabled under some conditions, the calculated current
result may be lower than the actual value. This condition typically occurs when there is a high value
of shunt voltage ( >70% of full range), there is a shunt with high temperature-coefficient value ( >2000
ppm/°C), and there is a high temperature ( >100°C). Consider the example of constant current flowing
through a high temperature coefficient shunt such that at lower temperatures the shunt voltage is
in its upper range. As the temperature increases, the device will correctly report a constant current
until the maximum shunt voltage is reached. As temperature continues to increase after the maximum
shunt voltage is reached, the device will start reporting lower currents. This is because the effective
resistance calculated will continue to increase while the detected shunt voltage will remain constant
due to the voltage exceeding the selected ADC range.
7.3.6 Integrated Precision Oscillator
The internal timebase of the device is provided by an internal oscillator that is trimmed to less than 0.5%
tolerance at room temperature. The precision oscillator is the timing source for ADC conversions, as well as
the time-count used for calculation of energy and charge. The digital filter response varies with conversion time;
therefore, the precise clock ensures filter response and notch frequency consistency across temperature. On
power up, the internal oscillator and ADC take roughly 300 µs to reach <1% error stability. Once the clock
stabilizes, the ADC data output will be accurate to the electrical specifications provided in Section 6.
7.3.7 Multi-Alert Monitoring and Fault Detection
The INA229-Q1 includes a multipurpose, open-drain ALERT output pin that can be used to report multiple
diagnostics or as an indicator that the ADC conversion is complete when the device is operating in both
triggered and continuous conversion mode. The diagnostics listed in Table 7-1 are constantly monitored and can
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be reported through the ALERT pin whenever the monitored output value crosses its associated out-of-range
threshold.
Table 7-1. ALERT Diagnostics Description
OUT-OF-RANGE
THRESHOLD
REGISTER (R/W)
STATUS BIT IN DIAG_ALRT REGISTER
(RO)
REGISTER DEFAULT
VALUE
INA229-Q1 DIAGNOSTIC
0x8000 h
(two's complement)
Shunt Under Voltage Limit
SHNTUL
SHNTOL
SUVL
SOVL
0x7FFF h
(two's complement)
Shunt Over Voltage Limit
Bus Voltage Over-Limit
0x7FFF h
(two's complement,
positive values only)
BUSOL
BUSUL
BOVL
BUVL
0x0000 h
(two's complement,
positive values only)
Bus Voltage Under-Limit
0xFFFF h
Temperature Over-Limit
Power Over-Limit
TMPOL
POL
TEMP_LIMIT
PWR_LIMIT
(two's complement,
positive values only)
0x7FFF h
(two's complement)
A read of the DIAG_ALRT register is used to determine which diagnostic has triggered the ALERT pin. This
register, shown in Table 7-16, is also used to monitor other associated diagnostics as well as configure some
ALERT pin functions.
•
Alert latch enable — In case the ALERT pin is triggered, this function will hold the value of the pin even after
all diagnostic conditions have cleared. A read of the DIAG_ALRT register will reset the status of the ALERT
pin. This function is enabled by setting the ALATCH bit.
•
Conversion ready enable — Enables the ALERT pin to assert when an ADC conversion has completed and
output values are ready to be read through the digital interface. This function is enabled by setting the CNVR
bit. The conversion completed events can also be read through the CNVRF bit regardless of the CNVR bit
setting.
•
•
Alert comparison on averaged output — Allows the out-of-range threshold value to be compared to the
averaged data values produced by the ADC. This helps to additionally remove noise from the output data
when compared to the out-of-range threshold to avoid false alerts due to noise. However, the diagnostic will
be delayed due to the time needed for averaging. This function is enabled by setting the SLOWALERT bit.
Alert polarity — Allows the device to invert the active state of the ALERT pin. Note that the ALERT pin is an
open-drain output that must be pulled-up by a resistor. The ALERT pin is active-low by default and can be
configured for active high function using the APOL control bit.
Other diagnostic functions that are not reported by the ALERT pin but are available by reading the DIAG_ALRT
register:
•
•
•
•
Math overflow — Indicated by the MATHOF bit, reports when an arithmetic operation has caused an internal
register overflow.
Memory status — Indicated by the MEMSTAT bit, monitors the health of the device non-volatile trim memory.
This bit should always read '1' when the device is operating properly.
Energy overflow — Indicated by the ENERGYOF bit, reports when the ENERGY register has reached an
overflow state due to data accumulation.
Charge overflow — Indicated by the CHARGEOF bit, reports when the CHARGE register has reached an
overflow state due to data accumulation.
When the ALERT pin is configured to report the ADC conversion complete event, the ALERT pin becomes a
multipurpose reporting output. Figure 7-6 shows an example where the device reports ADC conversion complete
events while the INA229-Q1 device is subject to shunt over voltage (over current) event, bus under voltage
event, over temperature event and over power-limit event.
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Shunt Over Voltage Threshold
Shunt Voltage
Bus Voltage
Bus Under Voltage Threshold
Over Temp Threshold
Temperature
Power
Power Over Limit Threshold
ALERT
(ALATCH = 0)
(APOL = 0)
(CNVR = 1)
SOV
SET
BUV
CLEAR
SOV
&
SOV
CLEAR
BUV
&
BUV
&
BUV
SET
BUV
SET
OT
SET
OT
&
OP
SET
- No diag. error -
Conversion Complete
Reported
Figure 7-6. Multi-Alert Configuration
7.4 Device Functional Modes
7.4.1 Shutdown Mode
In addition to the two conversion modes (continuous and triggered), the device also has a shutdown mode
(selected by the MODE bits in ADC_CONFIG register) that reduces the quiescent current to less than 5 µA and
turns off current into the device inputs, reducing the impact of supply drain when the device is not being used.
The registers of the device can be written to and read from while the device is in shutdown mode. The device
remains in shutdown mode until another triggered conversion command or continuous conversion command is
received.
The device can be triggered to perform conversions while in shutdown mode. When a conversion is triggered,
the ADC will start conversion; once conversion completes the device will return to the shutdown state.
Note that the shutdown current is specified with an inactive communications bus. Active clock and data activity
will increase the current consumption as a function of the bus frequency as shown in Shutdown IQ vs. Clock
Frequency.
7.4.2 Power-On Reset
Power-on reset (POR) is asserted when VS drops below 1.26V (typical) at which all of the registers are reset to
their default values. A manual device reset can be initiated by setting the RST bit in the CONFIG register. The
default power-up register values are shown in the reset column for each register description. Links to the register
descriptions are shown in Section 7.6.
7.5 Programming
7.5.1 Serial Interface
The primary communication between the INA229-Q1 and the external MCU is through the SPI bus, which
provides full-duplex communications in a main-secondary configuration. The external MCU is always the primary
or main SPI device, sending command requests on the MOSI pin, and receiving device responses on the MISO
pin. The INA229-Q1 is always an SPI secondary device, receiving command requests and sending responses
(status, measured values) to the external MCU over the MISO pin.
•
SPI is a 4-pin interface with pins as:
– CS - SPI Chip Select (input)
– SCLK - SPI Clock (input)
– MOSI - SPI Secondary In / Main Out data (input)
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– MISO - SPI Secondary Out / Main In data (tri-state output)
•
The SPI frame size is variable in length depending on the INA229-Q1 register accessed through the SPI
interface as following:
– Main to Secondary (MOSI): 6 bits for register Address; 1 bit low; 1 R/W bit (read / not write); variable
length of low bits depending on the INA229-Q1 register length.
– Secondary to Main (MISO): 8 bits low; variable length of bits depending on the INA229-Q1 register length.
SPI bit-speed up to 10 Mbit/s
Both Main commands and INA229-Q1 data are shifted MSB first, LSB last
The data on the MOSI line is sampled on the falling edge of SCLK
The data on the MISO line is shifted out on the rising edge of SCLK
•
•
•
•
The SPI communication starts with the CS falling edge, and ends with CS rising edge. The CS high level keeps
secondary SPI interface in an idle state, and MISO output is tri-stated.
Since the MISO output is push-pull it is ideal to have the INA229-Q1 supply at the same voltage as the primary
device I/O supply. If different supply voltages are used, level translation is recommended.
7.5.1.1 SPI Frame
SPI communication to the INA229-Q1 device is performed through register address access. Communication to
every register starts with a 6-bit register address followed by a "0" and a R/W bit. Setting the R/W bit to "1"
indicates that the current SPI frame will read from a device register while setting the R/W bit to "0" indicates the
current SPI frame will write data to a device register.
16 œ 40 bits
CS
SCLK
MOSI
MISO
ADDR
5
ADDR
4
ADDR
3
ADDR
2
ADDR
1
ADDR
0
R
DATA
MSB
DATA
DATA
DATA
DATA
DATA
DATA
DATA
LSB
. . . .
. . . . . .
Figure 7-7. SPI Read Frame
16 bits
CS
SCLK
MOSI
ADDR
5
ADDR
4
ADDR
3
ADDR
2
ADDR
1
ADDR
0
DATA
MSB
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
LSB
. . . . . .
. . . .
W
MISO
DATA
MSB
DATA
LSB
. . . .
. . . . .
Figure 7-8. SPI Write Frame
Note that while the read frame can be variable in length due to the different length registers in the INA229-Q1
device, the write frame is fixed in length as all writable registers are 16 bits wide. During an SPI write frame,
while new data is shifted into the INA229-Q1 register, the old data from the same register is shifted out on the
MISO line.
The first 8-bits of each SPI frame are presented in Table 7-2, which shows access to a certain register address
on the MOSI line as well as read/write functionality. On an SPI read operation, the INA229-Q1 returns the data
read in the same SPI frame.
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Table 7-2. First 8-MSB Bits of SPI Frame
COMMAND
READ
b7
b6
b5
b4
b3
b2
b1
b0
1
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
0
WRITE
0
7.6 Register Maps
7.6.1 INA229-Q1 Registers
Table 7-3 lists the INA229-Q1 registers. All register locations not listed in Table 7-3 should be considered as
reserved locations and the register contents should not be modified.
Table 7-3. INA229-Q1 Registers
Acronym
Register Name
Register Size (bits)
Section
Address
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
10h
CONFIG
Configuration
16
16
16
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
ADC_CONFIG
SHUNT_CAL
SHUNT_TEMPCO
VSHUNT
VBUS
ADC Configuration
Shunt Calibration
Shunt Temperature Coefficient 16
Shunt Voltage Measurement
Bus Voltage Measurement
Temperature Measurement
Current Result
24
24
16
24
24
40
40
16
16
DIETEMP
CURRENT
POWER
Power Result
ENERGY
CHARGE
DIAG_ALRT
SOVL
Energy Result
Charge Result
Diagnostic Flags and Alert
Shunt Overvoltage Threshold
SUVL
Shunt Undervoltage Threshold 16
BOVL
Bus Overvoltage Threshold
Bus Undervoltage Threshold
16
16
16
BUVL
TEMP_LIMIT
Temperature Over-Limit
Threshold
11h
3Eh
3Fh
PWR_LIMIT
Power Over-Limit Threshold
Manufacturer ID
16
16
16
Go
Go
Go
MANUFACTURER_ID
DEVICE_ID
Device ID
Complex bit access types are encoded to fit into small table cells. Table 7-4 shows the codes that are used for
access types in this section.
Table 7-4. INA229-Q1 Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default
value
7.6.1.1 Configuration (CONFIG) Register (Address = 0h) [reset = 0h]
The CONFIG register is shown in Table 7-5.
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Return to the Summary Table.
Table 7-5. CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
RST
R/W
0h
Reset Bit. Setting this bit to '1' generates a system reset that is the
same as power-on reset.
Resets all registers to default values.
0h = Normal Operation
1h = System Reset sets registers to default values
This bit self-clears.
14
RSTACC
R/W
R/W
0h
0h
Resets the contents of accumulation registers ENERGY and
CHARGE to 0
0h = Normal Operation
1h = Clears registers to default values for ENERGY and CHARGE
registers
13-6
CONVDLY
Sets the Delay for initial ADC conversion in steps of 2 ms.
0h = 0 s
1h = 2 ms
FFh = 510 ms
5
4
TEMPCOMP
ADCRANGE
RESERVED
R/W
R/W
R
0h
0h
0h
Enables temperature compensation of an external shunt
0h = Shunt Temperature Compensation Disabled
1h = Shunt Temperature Compensation Enabled
Shunt full scale range selection across IN+ and IN–.
0h = ±163.84 mV
1h = ± 40.96 mV
3-0
Reserved. Always reads 0.
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7.6.1.2 ADC Configuration (ADC_CONFIG) Register (Address = 1h) [reset = FB68h]
The ADC_CONFIG register is shown in Table 7-6.
Return to the Summary Table.
Table 7-6. ADC_CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15-12
MODE
R/W
Fh
The user can set the MODE bits for continuous or triggered mode on
bus voltage, shunt voltage or temperature measurement.
0h = Shutdown
1h = Triggered bus voltage, single shot
2h = Triggered shunt voltage, single shot
3h = Triggered shunt voltage and bus voltage, single shot
4h = Triggered temperature, single shot
5h = Triggered temperature and bus voltage, single shot
6h = Triggered temperature and shunt voltage, single shot
7h = Triggered bus voltage, shunt voltage and temperature, single
shot
8h = Shutdown
9h = Continuous bus voltage only
Ah = Continuous shunt voltage only
Bh = Continuous shunt and bus voltage
Ch = Continuous temperature only
Dh = Continuous bus voltage and temperature
Eh = Continuous temperature and shunt voltage
Fh = Continuous bus voltage, shunt voltage and temperature
11-9
VBUSCT
VSHCT
VTCT
R/W
R/W
R/W
5h
5h
5h
Sets the conversion time of the bus voltage measurement:
0h = 50 µs
1h = 84 µs
2h = 150 µs
3h = 280 µs
4h = 540 µs
5h = 1052 µs
6h = 2074 µs
7h = 4120 µs
8-6
Sets the conversion time of the shunt voltage measurement:
0h = 50 µs
1h = 84 µs
2h = 150 µs
3h = 280 µs
4h = 540 µs
5h = 1052 µs
6h = 2074 µs
7h = 4120 µs
5-3
Sets the conversion time of the temperature measurement:
0h = 50 µs
1h = 84 µs
2h = 150 µs
3h = 280 µs
4h = 540 µs
5h = 1052 µs
6h = 2074 µs
7h = 4120 µs
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Table 7-6. ADC_CONFIG Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2-0
AVG
R/W
0h
Selects ADC sample averaging count. The averaging setting applies
to all active inputs.
When >0h, the output registers are updated after the averaging has
completed.
0h = 1
1h = 4
2h = 16
3h = 64
4h = 128
5h = 256
6h = 512
7h = 1024
7.6.1.3 Shunt Calibration (SHUNT_CAL) Register (Address = 2h) [reset = 1000h]
The SHUNT_CAL register is shown in Table 7-7.
Return to the Summary Table.
Table 7-7. SHUNT_CAL Register Field Descriptions
Bit
15
Field
Type
Reset
Description
RESERVED
SHUNT_CAL
R
0h
Reserved. Always reads 0.
14-0
R/W
1000h
The register provides the device with a conversion constant value
that represents shunt resistance used to calculate current value in
Amperes.
This also sets the resolution for the CURRENT register.
Value calculation under Section 8.1.2.
7.6.1.4 Shunt Temperature Coefficient (SHUNT_TEMPCO) Register (Address = 3h) [reset = 0h]
The SHUNT_TEMPCO register is shown in Table 7-8.
Return to the Summary Table.
Table 7-8. SHUNT_TEMPCO Register Field Descriptions
Bit
Field
Type
Reset
Description
15-14
13-0
RESERVED
TEMPCO
R
0h
Reserved. Always reads 0.
R/W
0h
Temperature coefficient of the shunt for temperature compensation
correction. Calculated with respect to +25 °C.
The full scale value of the register is 16383 ppm/°C.
The 16 bit register provides a resolution of 1ppm/°C/LSB
0h = 0 ppm/°C
3FFFh = 16383 ppm/°C
7.6.1.5 Shunt Voltage Measurement (VSHUNT) Register (Address = 4h) [reset = 0h]
The VSHUNT register is shown in Table 7-9.
Return to the Summary Table.
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Table 7-9. VSHUNT Register Field Descriptions
Bit
Field
Type
Reset
Description
23-4
VSHUNT
R
0h
Differential voltage measured across the shunt output. Two's
complement value.
Conversion factor:
312.5 nV/LSB when ADCRANGE = 0
78.125 nV/LSB when ADCRANGE = 1
3-0
RESERVED
R
0h
Reserved. Always reads 0.
7.6.1.6 Bus Voltage Measurement (VBUS) Register (Address = 5h) [reset = 0h]
The VBUS register is shown in Table 7-10.
Return to the Summary Table.
Table 7-10. VBUS Register Field Descriptions
Bit
Field
Type
Reset
Description
23-4
VBUS
R
0h
Bus voltage output. Two's complement value, however always
positive.
Conversion factor: 195.3125 µV/LSB
3-0
RESERVED
R
0h
Reserved. Always reads 0.
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7.6.1.7 Temperature Measurement (DIETEMP) Register (Address = 6h) [reset = 0h]
The DIETEMP register is shown in Table 7-11.
Return to the Summary Table.
Table 7-11. DIETEMP Register Field Descriptions
Bit
Field
Type
Reset
Description
15-0
DIETEMP
R
0h
Internal die temperature measurement. Two's complement value.
Conversion factor: 7.8125 m°C/LSB
7.6.1.8 Current Result (CURRENT) Register (Address = 7h) [reset = 0h]
The CURRENT register is shown in Table 7-12.
Return to the Summary Table.
Table 7-12. CURRENT Register Field Descriptions
Bit
Field
Type
Reset
Description
23-4
CURRENT
R
0h
Calculated current output in Amperes. Two's complement value.
Value description under Section 8.1.2.
3-0
RESERVED
R
0h
Reserved. Always reads 0.
7.6.1.9 Power Result (POWER) Register (Address = 8h) [reset = 0h]
The POWER register is shown in Table 7-13.
Return to the Summary Table.
Table 7-13. POWER Register Field Descriptions
Bit
Field
Type
Reset
Description
23-0
POWER
R
0h
Calculated power output.
Output value in watts.
Unsigned representation. Positive value.
Value description under Section 8.1.2.
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7.6.1.10 Energy Result (ENERGY) Register (Address = 9h) [reset = 0h]
The ENERGY register is shown in Table 7-14.
Return to the Summary Table.
Table 7-14. ENERGY Register Field Descriptions
Bit
Field
Type
Reset
Description
39-0
ENERGY
R
0h
Calculated energy output.
Output value is in Joules.Unsigned representation. Positive value.
Value description under Section 8.1.2.
7.6.1.11 Charge Result (CHARGE) Register (Address = Ah) [reset = 0h]
The CHARGE register is shown in Table 7-15.
Return to the Summary Table.
Table 7-15. CHARGE Register Field Descriptions
Bit
Field
Type
Reset
Description
39-0
CHARGE
R
0h
Calculated charge output. Output value is in Coulombs.Two's
complement value.
Value description under Section 8.1.2.
7.6.1.12 Diagnostic Flags and Alert (DIAG_ALRT) Register (Address = Bh) [reset = 0001h]
The DIAG_ALRT register is shown in Table 7-16.
Return to the Summary Table.
Table 7-16. DIAG_ALRT Register Field Descriptions
Bit
Field
Type
Reset
Description
15
ALATCH
R/W
0h
When the Alert Latch Enable bit is set to Transparent mode, the
Alert pin and Flag bit reset to the idle state when the fault has been
cleared.
When the Alert Latch Enable bit is set to Latch mode, the Alert pin
and Alert Flag bit remain active following a fault until the DIAG_ALRT
Register has been read.
0h = Transparent
1h = Latched
14
13
CNVR
R/W
R/W
0h
0h
Setting this bit high configures the Alert pin to be asserted when
the Conversion Ready Flag (bit 1) is asserted, indicating that a
conversion cycle has completed.
0h = Disable conversion ready flag on ALERT pin
1h = Enables conversion ready flag on ALERT pin
SLOWALERT
When enabled, ALERT function is asserted on the completed
averaged value.
This gives the flexibility to delay the ALERT until after the averaged
value.
0h = ALERT comparison on non-averaged (ADC) value
1h = ALERT comparison on averaged value
12
11
APOL
R/W
R
0h
0h
Alert Polarity bit sets the Alert pin polarity.
0h = Normal (Active-low, open-drain)
1h = Inverted (active-high, open-drain )
ENERGYOF
This bit indicates the health of the ENERGY register.
If the 40 bit ENERGY register has overflowed this bit is set to 1.
0h = Normal
1h = Overflow
Clears when the ENERGY register is read.
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Table 7-16. DIAG_ALRT Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
10
CHARGEOF
R
0h
This bit indicates the health of the CHARGE register.
If the 40 bit CHARGE register has overflowed this bit is set to 1.
0h = Normal
1h = Overflow
Clears when the CHARGE register is read.
9
MATHOF
R
0h
This bit is set to 1 if an arithmetic operation resulted in an overflow
error.
It indicates that current and power data may be invalid.
0h = Normal
1h = Overflow
Must be manually cleared by triggering another conversion or by
clearing the accumulators with the RSTACC bit.
8
7
RESERVED
TMPOL
R
0h
0h
Reserved. Always read 0.
R/W
This bit is set to 1 if the temperature measurement exceeds the
threshold limit in the temperature over-limit register.
0h = Normal
1h = Over Temp Event
When ALATCH =1 this bit is cleared by reading this register.
6
5
4
3
2
1
0
SHNTOL
SHNTUL
BUSOL
BUSUL
POL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
0h
1h
This bit is set to 1 if the shunt voltage measurement exceeds the
threshold limit in the shunt over-limit register.
0h = Normal
1h = Over Shunt Voltage Event
When ALATCH =1 this bit is cleared by reading this register.
This bit is set to 1 if the shunt voltage measurement falls below the
threshold limit in the shunt under-limit register.
0h = Normal
1h = Under Shunt Voltage Event
When ALATCH =1 this bit is cleared by reading this register.
This bit is set to 1 if the bus voltage measurement exceeds the
threshold limit in the bus over-limit register.
0h = Normal
1h = Bus Over-Limit Event
When ALATCH =1 this bit is cleared by reading this register.
This bit is set to 1 if the bus voltage measurement falls below the
threshold limit in the bus under-limit register.
0h = Normal
1h = Bus Under-Limit Event
When ALATCH =1 this bit is cleared by reading this register.
This bit is set to 1 if the power measurement exceeds the threshold
limit in the power limit register.
0h = Normal
1h = Power Over-Limit Event
When ALATCH =1 this bit is cleared by reading this register.
CNVRF
MEMSTAT
This bit is set to 1 if the conversion is completed.
0h = Normal
1h = Conversion is complete
When ALATCH =1 this bit is cleared by reading this register or
starting a new triggered conversion.
This bit is set to 0 if a checksum error is detected in the device trim
memory space.
0h = Memory Checksum Error
1h = Normal Operation
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7.6.1.13 Shunt Overvoltage Threshold (SOVL) Register (Address = Ch) [reset = 7FFFh]
If negative values are entered in this register, then a shunt voltage measurement of 0 V will trip this alarm. When
using negative values for the shunt under and overvoltage thresholds be aware that the over voltage threshold
must be set to the larger (that is, less negative) of the two values. The SOVL register is shown in Table 7-17.
Return to the Summary Table.
Table 7-17. SOVL Register Field Descriptions
Bit
Field
Type
Reset
Description
15-0
SOVL
R/W
7FFFh
Sets the threshold for comparison of the value to detect Shunt
Overvoltage (overcurrent protection). Two's complement value.
Conversion Factor: 5 µV/LSB when ADCRANGE = 0
1.25 µV/LSB when ADCRANGE = 1.
7.6.1.14 Shunt Undervoltage Threshold (SUVL) Register (Address = Dh) [reset = 8000h]
The SUVL register is shown in Table 7-18.
Return to the Summary Table.
Table 7-18. SUVL Register Field Descriptions
Bit
Field
Type
Reset
Description
15-0
SUVL
R/W
8000h
Sets the threshold for comparison of the value to detect Shunt
Undervoltage (undercurrent protection). Two's complement value.
Conversion Factor: 5 µV/LSB when ADCRANGE = 0
1.25 µV/LSB when ADCRANGE = 1.
7.6.1.15 Bus Overvoltage Threshold (BOVL) Register (Address = Eh) [reset = 7FFFh]
The BOVL register is shown in Table 7-19.
Return to the Summary Table.
Table 7-19. BOVL Register Field Descriptions
Bit
15
Field
Type
Reset
Description
Reserved
BOVL
R
0h
Reserved. Always reads 0.
14-0
R/W
7FFFh
Sets the threshold for comparison of the value to detect Bus
Overvoltage (overvoltage protection). Unsigned representation,
positive value only. Conversion factor: 3.125 mV/LSB.
7.6.1.16 Bus Undervoltage Threshold (BUVL) Register (Address = Fh) [reset = 0h]
The BUVL register is shown in Table 7-20.
Return to the Summary Table.
Table 7-20. BUVL Register Field Descriptions
Bit
15
Field
Type
Reset
Description
Reserved
BUVL
R
0h
Reserved. Always reads 0.
14-0
R/W
0h
Sets the threshold for comparison of the value to detect Bus
Undervoltage (undervoltage protection). Unsigned representation,
positive value only. Conversion factor: 3.125 mV/LSB.
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7.6.1.17 Temperature Over-Limit Threshold (TEMP_LIMIT) Register (Address = 10h) [reset = 7FFFh]
The TEMP_LIMIT register is shown in Table 7-21.
Return to the Summary Table.
Table 7-21. TEMP_LIMIT Register Field Descriptions
Bit
Field
Type
Reset
Description
15-0
TOL
R/W
7FFFh
Sets the threshold for comparison of the value to detect over
temperature measurements. Two's complement value.
The value entered in this field compares directly against the value
from the DIETEMP register to determine if an over temperature
condition exists. Conversion factor: 7.8125 m°C/LSB.
7.6.1.18 Power Over-Limit Threshold (PWR_LIMIT) Register (Address = 11h) [reset = FFFFh]
The PWR_LIMIT register is shown in Table 7-22.
Return to the Summary Table.
Table 7-22. PWR_LIMIT Register Field Descriptions
Bit
Field
Type
Reset
Description
15-0
POL
R/W
FFFFh
Sets the threshold for comparison of the value to detect power over-
limit measurements. Unsigned representation, positive value only.
The value entered in this field compares directly against the value
from the POWER register to determine if an over power condition
exists. Conversion factor: 256 × Power LSB.
7.6.1.19 Manufacturer ID (MANUFACTURER_ID) Register (Address = 3Eh) [reset = 5449h]
The MANUFACTURER_ID register is shown in Table 7-23.
Return to the Summary Table.
Table 7-23. MANUFACTURER_ID Register Field Descriptions
Bit
Field
Type
Reset
Description
15-0
MANFID
R
5449h
Reads back TI in ASCII.
7.6.1.20 Device ID (DEVICE_ID) Register (Address = 3Fh) [reset = 2291h]
The DEVICE_ID register is shown in Table 7-24.
Return to the Summary Table.
Table 7-24. DEVICE_ID Register Field Descriptions
Bit
15-4
3-0
Field
Type
Reset
229h
1h
Description
DIEID
REV_ID
R
Stores the device identification bits.
Device revision identification.
R
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
8.1.1 Device Measurement Range and Resolution
The INA229-Q1 device supports two input ranges for the shunt voltage measurement. The supported full scale
differential input across the IN+ and IN– pins can be either ±163.84 mV or ±40.96 mV depending on the
ADCRANGE bit in CONFIG register. The range for the bus voltage measurement is from 0 V to 85 V. The
internal die temperature sensor range extends from –256 °C to +256 °C but is limited by the package to –40 °C
to 125 °C.
Table 8-1 provides a description of full scale voltage on shunt, bus, and temperature measurements, along with
their associated step size.
Table 8-1. ADC Full Scale Values
PARAMETER
FULL SCALE VALUE
±163.84 mV (ADCRANGE = 0)
±40.96 mV (ADCRANGE = 1)
0 V to 85 V
RESOLUTION
312.5 nV/LSB
Shunt voltage
78.125 nV/LSB
195.3125 µV/LSB
7.8125 m°C/LSB
Bus voltage
Temperature
–40 °C to +125 °C
The device shunt voltage measurements, bus voltage, and temperature measurements can be read through the
VSHUNT, VBUS, and DIETEMP registers, respectively. The digital output in VSHUNT and VBUS registers is
20-bits. The shunt voltage measurement can be positive or negative due to bidirectional currents in the system;
therefore the data value in VSHUNT can be positive or negative. The VBUS data value is always positive. The
output data can be directly converted into voltage by multiplying the digital value by its respective resolution size.
The digital output in the DIETEMP register is 16-bit and can be directly converted to °C by multiplying by the
above resolution size. This output value can also be positive or negative.
Furthermore, the device provides the flexibility to report calculated current in Amperes, power in Watts, charge in
Coulombs and energy in Joules as described in Section 8.1.2.
8.1.2 Current , Power, Energy, and Charge Calculations
For the INA229-Q1 device to report current values in Ampere units, a constant conversion value must be written
in the SHUNT_CAL register that is dependent on the maximum measured current and the shunt resistance used
in the application. The SHUNT_CAL register is calculated based on Equation 2. The term CURRENT_LSB is the
LSB step size for the CURRENT register where the current in Amperes is stored. The value of CURRENT_LSB
is based on the maximum expected current as shown in Equation 3, and it directly defines the resolution of the
CURRENT register. While the smallest CURRENT_LSB value yields highest resolution, it is common to select a
higher round-number (no higher than 8x) value for the CURRENT_LSB in order to simplify the conversion of the
CURRENT.
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The RSHUNT term is the resistance value of the external shunt used to develop the differential voltage across the
IN+ and IN– pins. Use Equation 2 for ADCRANGE = 0. For ADCRANGE = 1, the value of SHUNT_CAL must be
multiplied by 4.
SHUNT_CAL = 13107.2 x 106 x CURRENT_LSB x RSHUNT
(2)
where
•
•
13107.2 x 106 is an internal fixed value used to ensure scaling is maintained properly.
the value of SHUNT_CAL must be multiplied by 4 for ADCRANGE = 1.
Maximum Expected Current
CURRENT_LSB =
219
(3)
Note that the current is calculated following a shunt voltage measurement based on the value set in the
SHUNT_CAL register. If the value loaded into the SHUNT_CAL register is zero, the current value reported
through the CURRENT register is also zero.
After programming the SHUNT_CAL register with the calculated value, the measured current in Amperes can be
read from the CURRENT register. The final value is scaled by CURRENT_LSB and calculated in Equation 4:
Current [A] = CURRENT_LSB x CURRENT
(4)
where
•
CURRENT is the value read from the CURRENT register
The power value can be read from the POWER register as a 24-bit value and converted to Watts by using
Equation 5:
Power [W] = 3.2 x CURRENT_LSB x POWER
(5)
where
•
•
POWER is the value read from the POWER register.
CURRENT_LSB is the lsb size of the current calculation as defined by Equation 3.
The energy value can be read from the ENERGY register as a 40-bit unsigned value in Joules units. The energy
value in Joules is converted by using Equation 6:
Energy [J] = 16 x 3.2 x CURRENT_LSB x ENERGY
(6)
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The charge value can be read from the CHARGE register as a 40-bit, two's complement value in Coulombs. The
charge value in Coulomb is converted by using Equation 7:
Charge [C] = CURRENT_LSB x CHARGE
(7)
where
•
•
CHARGE is the value read from the CHARGE register.
CURRENT_LSB is the lsb size of the current calculation as described in Equation 3.
Upon overflow, the ENERGY and CHARGE registers will roll over and start from zero. The register values can
also be reset at any time by setting the RSTACC bit in the CONFIG register.
For a design example using these equations refer to Section 8.2.2.
8.1.3 ADC Output Data Rate and Noise Performance
The INA229-Q1 noise performance and effective resolution depend on the ADC conversion time. The device
also supports digital averaging which can further help decrease digital noise. The flexibility of the device to
select ADC conversion time and data averaging offers increased signal-to-noise ratio and achieves the highest
dynamic range with lowest offset. The profile of the noise at lower signals levels is dominated by the system
noise that is comprised mainly of 1/f noise or white noise. The INA229-Q1 effective resolution of the ADC can be
increased by increasing the conversion time and increasing the number of averages.
Table 8-2 summarizes the output data rate conversion settings supported by the device. The fastest conversion
setting is 50 µs. Typical noise-free resolution is represented as Effective Number of Bits (ENOB) based on
device measured data. The ENOB is calculated based on noise peak-to-peak values, which assures that full
noise distribution is taken into consideration.
Table 8-2. INA229-Q1 Noise Performance
NOISE-FREE ENOB
(±163.84-mV)
(ADCRANGE = 0)
NOISE-FREE ENOB
(±40.96-mV)
(ADCRANGE = 1)
ADC CONVERSION
TIME PERIOD [µs]
OUTPUT SAMPLE
AVERAGING [SAMPLES]
OUTPUT SAMPLE PERIOD
[ms]
50
84
0.05
0.084
0.15
0.28
0.54
1.052
2.074
4.12
0.2
12.4
12.6
13.3
13.8
14.2
14.5
15.3
16.0
13.1
13.9
14.3
14.9
15.1
15.8
16.1
16.5
10.4
10.4
11.4
11.8
12.4
12.6
13.3
13.8
11.4
11.8
12.2
12.8
13.0
13.8
14.3
14.4
150
280
540
1052
2074
4120
50
1
84
0.336
0.6
150
280
540
1052
2074
4120
1.12
2.16
4.208
8.296
16.48
4
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Table 8-2. INA229-Q1 Noise Performance (continued)
NOISE-FREE ENOB
(±163.84-mV)
(ADCRANGE = 0)
NOISE-FREE ENOB
(±40.96-mV)
(ADCRANGE = 1)
ADC CONVERSION
TIME PERIOD [µs]
OUTPUT SAMPLE
AVERAGING [SAMPLES]
OUTPUT SAMPLE PERIOD
[ms]
50
84
0.8
1.344
2.4
13.9
14.7
15.1
15.8
16.3
16.5
17.1
17.7
15.0
15.9
16.4
16.9
17.7
17.7
18.1
18.7
15.5
16.3
16.9
17.1
18.1
18.1
18.7
19.7
15.5
16.7
17.4
17.7
18.7
18.7
19.7
19.7
16.7
17.4
17.7
18.7
18.7
19.7
19.7
19.7
12.3
12.9
13.0
13.7
14.3
14.6
15.3
15.9
13.3
13.8
14.4
14.5
15.3
15.9
16.3
16.5
13.4
14.3
14.7
15.2
15.9
16.4
16.9
17.1
14.4
14.7
15.3
15.7
16.1
16.7
17.4
17.7
14.3
15.4
15.5
16.3
16.5
17.4
17.7
18.7
150
280
540
1052
2074
4120
50
4.48
16
8.64
16.832
33.184
65.92
3.2
84
5.376
9.6
150
280
540
1052
2074
4120
50
17.92
34.56
67.328
132.736
263.68
6.4
64
84
10.752
19.2
150
280
540
1052
2074
4120
50
35.84
69.12
134.656
265.472
527.36
12.8
128
256
512
84
21.504
38.4
150
280
540
1052
2074
4120
50
71.68
138.24
269.312
530.944
1054.72
25.6
84
43
150
280
540
1052
2074
4120
76.8
143.36
276.48
538.624
1061.888
2109.44
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Table 8-2. INA229-Q1 Noise Performance (continued)
NOISE-FREE ENOB
(±163.84-mV)
(ADCRANGE = 0)
NOISE-FREE ENOB
(±40.96-mV)
(ADCRANGE = 1)
ADC CONVERSION
TIME PERIOD [µs]
OUTPUT SAMPLE
AVERAGING [SAMPLES]
OUTPUT SAMPLE PERIOD
[ms]
50
84
51.2
86.016
153.6
17.1
17.7
18.1
18.7
19.7
19.7
19.7
20
15.0
15.9
16.0
16.9
17.1
17.7
18.1
18.7
150
280
540
1052
2074
4120
286.72
552.96
1077.248
2123.776
4218.88
1024
8.1.4 Input Filtering Considerations
As previously discussed, INA229-Q1 offers several options for noise filtering by allowing the user to select the
conversion times and number of averages independently in the ADC_CONFIG register. The conversion times
can be set independently for the shunt voltage and bus voltage measurements to allow added flexibility in
monitoring of the power-supply bus.
The internal ADC has good inherent noise rejection; however, the transients that occur at or very close to the
sampling rate harmonics can cause problems. Because these signals are at 1 MHz and higher, they can be
managed by incorporating filtering at the input of the device. Filtering high frequency signals enables the use of
low-value series resistors on the filter with negligible effects on measurement accuracy. For best results, filter
using the lowest possible series resistance (typically 100 Ω or less) and a ceramic capacitor. Recommended
values for this capacitor are between 0.1 µF and 1 µF. Figure 8-1 shows the device with a filter added at the
input.
Overload conditions are another consideration for the device inputs. The device inputs are specified to tolerate
±40 V differential across the IN+ and IN– pins. A large differential scenario might be a short to ground on the
load side of the shunt. This type of event can result in full power-supply voltage across the shunt (as long
the power supply or energy storage capacitors support it). Removing a short to ground can result in inductive
kickbacks that could exceed the 40-V differential or 85-V common-mode absolute maximum rating of the device.
Inductive kickback voltages are best controlled by Zener-type transient-absorbing devices (commonly called
transzorbs) combined with sufficient energy storage capacitance. See the Transient Robustness for Current
Shunt Monitors reference design which describes a high-side current shunt monitor used to measure the voltage
developed across a current-sensing resistor when current passes through it.
In applications that do not have large energy storage, electrolytic capacitors on one or both sides of the shunt,
an input overstress condition may result from an excessive dV/dt of the voltage applied to the input. A hard
physical short is the most likely cause of this event. This problem occurs because an excessive dV/dt can
activate the ESD protection in the device in systems where large currents are available. Testing demonstrates
that the addition of 10-Ω resistors in series with each input of the device sufficiently protects the inputs against
this dV/dt failure up to the 40-V maximum differential voltage rating of the device. Selecting these resistors in the
range noted has minimal effect on accuracy.
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Load
Supply
VS = 2.7Vœ 5.5V
100 nF
VS
RFILTER
VBUS
IN+
<100 ꢀ
RSHUNT
RDIFF
<100 ꢀ
IN-
GND
Load
CFILTER
0.1µF to 1µF
Figure 8-1. Input Filtering
Do not use values greater than 100 ohms for RFILTER. Doing so will degrade gain error and increase non-
linearity.
8.2 Typical Application
The low offset voltage and low input bias current of the INA229-Q1 allow accurate monitoring of a wide range
of currents. To accurately monitor currents with high resolution, select the value of the shunt resistor so that the
resulting sense voltage is close to the maximum allowable differential input voltage range (either ±163.84 mV
or ±40.96 mV, depending on register settings). The circuit for monitoring currents in a high-side configuration is
shown in Figure 8-2.
VS = 2.7 V to 5.5 V
100 nF
VS
SCLK
MOSI
MISO
CS
VBUS
IN+
SPI
I/F
48 V
BATT
VS
To
MCU
RSHUNT
IN-
10 kꢀ
ALERT
GND
LOAD
CHARGER
GND
Figure 8-2. INA229-Q1 High-Side Sensing Application Diagram
8.2.1 Design Requirements
The INA229-Q1 measures the voltage developed across a current-sensing resistor (RSHUNT) when current
passes through it. The device also measures the bus supply voltage and calculates power when calibrated. It
also comes with alert capability, where the alert pin can be programmed to respond to a user-defined event or a
conversion ready notification.
The design requirements for the circuit shown in Figure 8-2 are listed in Table 8-3.
Table 8-3. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Power-supply voltage (VS)
5 V
48 V
52 V
6 A
Bus supply rail (VCM
)
Bus supply rail over voltage fault threshold
Average Current
Overcurrent fault threshold (IMAX
)
10 A
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Table 8-3. Design Parameters (continued)
DESIGN PARAMETER
ADC Range Selection (VSENSE_MAX
Temperature
EXAMPLE VALUE
±163.84 mV
25 ºC
)
Charge Accumulation Period
1 hour
8.2.2 Detailed Design Procedure
8.2.2.1 Select the Shunt Resistor
Using values from Table 8-3, the maximum value of the shunt resistor is calculated based on the value of
the maximum current to be sensed (IMAX) and the maximum allowable sense voltage (VSENSE_MAX) for the
chosen ADC range. When operating at the maximum current, the differential input voltage must not exceed the
maximum full scale range of the device, VSENSE_MAX. Using Equation 8 for the given design parameters, the
maximum value for RSHUNT is calculated to be 16.38 mΩ. The closest standard resistor value that is smaller than
the maximum calculated value is 16.2 mΩ. Also keep in mind that RSHUNT must be able to handle the power
dissipated across it in the maximum load condition.
VSENSE_MAX
RSHUNT
<
IMAX
(8)
8.2.2.2 Configure the Device
The first step to program the INA229-Q1 is to properly set the device and ADC configuration registers. On initial
power up the CONFIG and ADC_CONFIG registers are set to the reset values as shown in Table 7-5 and
Table 7-6. In this default power on state the device is set to measured on the ±163.84 mV range with the ADC
continuously converting the shunt voltage, bus voltage, and temperature. If the default power up conditions do
not meet the design requirements, these registers will need to be set properly after each VS power cycle event.
8.2.2.3 Program the Shunt Calibration Register
The shunt calibration register needs to be correctly programmed at each VS power up in order for the device
to properly report any result based on current. The first step in properly setting this register is to calculate the
LSB value for the current by using Equation 3. Applying this equation with the maximum expected current of
10 A results in an LSB size of 19.0735 μA. Applying Equation 2 to the Current_LSB and selected value for the
shunt resistor results in a shunt calibration register setting of 4050d (FD2h). Failure to set the value of the shunt
calibration register will result in a zero value for any result based on current.
8.2.2.4 Set Desired Fault Thresholds
Fault thresholds are set by programming the desired trip threshold into the corresponding fault register. The list
of supported fault registers is shown in Table 7-1. Since the fault limit registers are 16 bits in length, the effective
LSB size for these registers is 16 times greater than the corresponding 20 bit LSB used in calculating returned
values for bus voltage and current.
An over current threshold is set by programming the shunt over voltage limit register (SOVL). The voltage that
needs to be programmed into this register is calculated by multiplying the over current threshold by the shunt
resistor. In this example the over current threshold is 10 A and the value of the current sense resistor is 16.2 mΩ,
which give a shunt voltage limit of 162 mV. Once the shunt voltage limit is known, the value for the shunt over
voltage limit register is calculated by dividing the shunt voltage limit by the shunt voltage LSB size.
In this example, the calculated value of the shunt over voltage limit register is 162 mV / (312.5 nV × 16) =
32400d (7E90h).
An over voltage fault threshold on the bus voltage is set by programming the bus over voltage limit register
(BOVL). In this example the desired over voltage threshold is 52 V. The value that needs to be programmed into
this register is calculated by dividing the target threshold voltage by the bus voltage fault limit LSB value of 3.125
mV. For this example, the target value for the BOVL register is 52 V / (195.3125 μV × 16) = 16640d (4100h).
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When setting the power over-limit value, the LSB size used to calculate the value needed in the limit registers
will be 256 times greater than the power LSB. This is because the power register is a 24 bits in length while the
power fault limit register is 16 bits.
Values stored in the alert limit registers are set to the default values after VS power cycle events and need to be
reprogrammed each time power is applied.
8.2.2.5 Calculate Returned Values
Parametric values are calculated by multiplying the returned value by the LSB value. Table 8-4 below shows the
returned values for this application example assuming the design requirements shown in Table 8-3.
Table 8-4. Calculating Returned Values
PARAMETER
Shunt voltage (V)
Current (A)
Returned Value
LSB Value
Calculated Value
0.0972 V
6 A
311040d
312.5 nV/LSB
314572d
10 A/ 219 = 19.073486 µA/LSB
195.3125 µV/LSB
Bus voltage (V)
Power (W)
245760d
48 V
4718604d
1061683200d
1132462080d
3200d
Current LSB x 3.2 = 61.035156 µW/LSB
Power LSB x 16 = 976.5625 µJ/LSB
Current LSB = 19.073486 µC/LSB
7.8125 m°C/LSB
288 W
Energy (J)
1036800 J
21600 C
25°C
Charge (C)
Temperature (°C)
Shunt Voltage, Current, Bus Voltage (positive only), Charge, and Temperature return values in two's complement
format. In two's complement format a negative value in binary is represented by having a 1 in the most
significant bit of the returned value. These values can be converted to decimal by first inverting all the bits
and adding 1 to obtain the unsigned binary value. This value should then be converted to decimal with the
negative sign applied. For example, assume a shunt voltage reading returns 1011 0100 0001 0000 0000. This is
a negative value due to the MSB having a value of one. Inverting the bits and adding one results in 0100 1011
1111 0000 0000 (311040d) which from the shunt voltage example in Table 8-4 correlates to a voltage of 97.2 mV.
Since the returned value was negative the measured shunt voltage value is -97.2 mV.
8.2.3 Application Curves
Figure 8-3 and Figure 8-4 show the ALERT pin response to a bus overvoltage fault with a conversion time of
50 μs, averaging set to 1, and the SLOWALERT bit set to 0 for bus only conversions. For these scope shots,
persistence was enabled on the ALERT channel to show the variation in the alert response for many sequential
fault events. If the magnitude of the fault is sufficient the ALERT response can be as fast as one quarter of the
ADC conversion time as shown in Figure 8-3. For fault conditions that are just exceeding the limit threshold,
the response time for the ALERT pin can vary from approximately 0.5 to 1.5 conversion cycles as shown in
Figure 8-4. Variation in the alert response exists because the external fault event is not synchronized to the
internal ADC conversion start. Also the ADC is constantly sampling to get a result, so the response time for fault
events starting from zero will slower than fault events starting from values near the set fault threshold. Since the
timing of the alert can be difficult to predict, applications where the alert timing is critical should assume a alert
response equal to 1.5 times the ADC conversion time for bus voltage or shunt voltage only conversions.
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Fault Threshold: 1.9 V
Fault Threshold: 0.2 V
Maximum Delay: 37.9 µs
Maximum Delay: 73.2 µs
Minimum Delay: 12.4 µs
TIME (10 µs / div)
Minimum Delay: 24 µs
TIME (10 µs / div)
Figure 8-3. Alert Response Time (Sampled Values Figure 8-4. Alert Response Time (Sampled Values
Significantly Above Threshold) Slightly Above Threshold)
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9 Power Supply Recommendations
The input circuitry of the device can accurately measure signals on common-mode voltages beyond its power-
supply voltage, VS. For example, the voltage applied to the VS power supply terminal can be 5 V, whereas the
load power-supply voltage being monitored (the common-mode voltage) can be as high as 85 V. Note that the
device can also withstand the full 0 V to 85 V range at the input terminals, regardless of whether the device has
power applied or not. Avoid applications where the GND pin is disconnected while device is actively powered.
Place the required power-supply bypass capacitors as close as possible to the supply and ground terminals of
the device. A typical value for this supply bypass capacitor is 0.1 µF. Applications with noisy or high-impedance
power supplies may require additional decoupling capacitors to reject power-supply noise.
10 Layout
10.1 Layout Guidelines
Connect the input pins (IN+ and IN–) to the sensing resistor using a Kelvin connection or a 4-wire connection.
This connection technique ensures that only the current-sensing resistor impedance is sensed between the input
pins. Poor routing of the current-sensing resistor commonly results in additional resistance present between
the input pins. Given the very low ohmic value of the current-sensing resistor, any additional high-current
carrying impedance causes significant measurement errors. Place the power-supply bypass capacitor as close
as possible to the supply and ground pins.
10.2 Layout Example
CS
IN+
INt
Sense/Shunt
resistor
MOSI
ALERT
MISO
SCLK
(1)
Alert output
(2)
VBUS
GND
VS
SPI
interface
Supply bypass
capacitor
Via to Ground Plane
Via to Power Plane
(1) Connect the VBUS pin to the voltage powering the load for load power calculations..
(2) Can be left floating if unused.
Figure 10-1. INA229-Q1 Layout Example
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
7-Jul-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
INA229AQDGSRQ1
ACTIVE
VSSOP
DGS
10
2500 RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
229Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF INA229-Q1 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Jul-2021
Catalog : INA229
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Jul-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
INA229AQDGSRQ1
VSSOP
DGS
10
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Jul-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VSSOP DGS 10
SPQ
Length (mm) Width (mm) Height (mm)
366.0 364.0 50.0
INA229AQDGSRQ1
2500
Pack Materials-Page 2
PACKAGE OUTLINE
DGS0010A
VSSOP - 1.1 mm max height
S
C
A
L
E
3
.
2
0
0
SMALL OUTLINE PACKAGE
C
SEATING PLANE
0.1 C
5.05
4.75
TYP
PIN 1 ID
AREA
A
8X 0.5
10
1
3.1
2.9
NOTE 3
2X
2
5
6
0.27
0.17
10X
3.1
2.9
1.1 MAX
0.1
C A
B
B
NOTE 4
0.23
0.13
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.7
0.4
0 - 8
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
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EXAMPLE BOARD LAYOUT
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
(R0.05)
TYP
SYMM
10X (0.3)
1
5
10
SYMM
6
8X (0.5)
(4.4)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221984/A 05/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
SYMM
(R0.05) TYP
10X (0.3)
8X (0.5)
1
5
10
SYMM
6
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221984/A 05/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
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