INA233AIDGSR [TI]
具有警报功能的 36V、16 位、超精密 I2C 和 PMBus 输出电流/电压/功率/能量监控器 | DGS | 10 | -40 to 125;
| 型号： | INA233AIDGSR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有警报功能的 36V、16 位、超精密 I2C 和 PMBus 输出电流/电压/功率/能量监控器 | DGS | 10 | -40 to 125 监控 光电二极管 |
| 文件： | 总51页 (文件大小：1284K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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INA233
ZHCSG76 –APRIL 2017
INA233 高侧或低侧测量双向电流和功率监视器（具有兼容 I2C、SMBus 和
PMBus 的接口）
1 特性
3 说明
1
•
•
•
•
•
感测的总线电压范围：0V 至 36V
INA233 器件是一款电流、电压和功率监控器，具有兼
容 I2C、SMBus 和 PMBus 的接口，并可与 1.8V 至
5.0V 的数字总线电压兼容。该器件监控并报告电流、
电压和功率值。集成电源累加器可用于能源和平均功耗
计算。可编程校准值、转换时间和取平均值与内部乘法
器结合使用时，可实现电流值（单位为安培）和功率值
（单位为瓦特）的直接读取。
高侧或低侧感测
报告电流、电压和功率
用于能源和平均功耗监控的集成电源累加器
高精度：
–
–
0.1% 增益误差（最大值）
10µV 偏移（最大值）
•
•
•
•
•
•
可配置取平均选项
INA233 可在独立于电源电压的 0V 至 36V 共模总线电
压范围内感测电流。该器件由一个 2.7V 至 5.5V 的单
电源供电，在正常运行条件下消耗 310μA 的典型电源
电流。可以将该器件置于低功耗待机模式，该模式下的
典型工作电流仅有 2µA。该器件的额定工作温度范围
为 –40°C 至 +125°C 并 具有 多达 16 个可编程地址。
电流、总线电压和功率的独立警报限值
兼容 I2C、SMBus、PMBus 接口的 1.8V 电压
16 个可编程地址
由 2.7V 至 5.5V 电源供电
10 引脚 DGS 超薄小外形尺寸 (VSSOP) 封装
器件信息(1)
2 应用范围
器件型号
INA233
封装
封装尺寸（标称值）
•
•
•
•
•
•
•
服务器
VSSOP (10)
3.00mm x 3.00mm
电信基础设施
高性能计算
电能计量
电池充电器
电源
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
测试设备
高侧或低侧感测应用
Supply Voltage
(2.7 V to 5.5 V)
CBYPASS
0.1 µF
Bus Voltage
(0 V to 36 V)
INA233
High-
Side
VS
VBUS
Shunt
Power Register
ì
SDA
SCL
Power Accumulator
Current Register
Load
I2C-, SMBus-,
PMBus
V
I
IN+
IN-
Compatible
ADC
Low-
Side
Shunt
Interface
ALERT
A0
Voltage Register
Alert Register
A1
GND
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBOS790
INA233
ZHCSG76 –APRIL 2017
www.ti.com.cn
目录
7.6 Register Maps......................................................... 23
Application and Implementation ........................ 41
8.1 Application Information............................................ 41
8.2 Typical Application .................................................. 41
Power Supply Recommendations...................... 44
1
2
3
4
5
6
特性.......................................................................... 1
8
9
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics ............................................. 7
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 13
7.5 Programming........................................................... 15
10 Layout................................................................... 44
10.1 Layout Guidelines ................................................. 44
10.2 Layout Example .................................................... 44
11 器件和文档支持 ..................................................... 45
11.1 器件支持 ............................................................... 45
11.2 文档支持................................................................ 45
11.3 接收文档更新通知 ................................................. 45
11.4 社区资源................................................................ 45
11.5 商标....................................................................... 45
11.6 静电放电警告......................................................... 45
11.7 Glossary................................................................ 45
12 机械、封装和可订购信息....................................... 45
7
4 修订历史记录
日期
修订版本
注释
2017 年 4 月
*
首次发布。
2
Copyright © 2017, Texas Instruments Incorporated
INA233
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ZHCSG76 –APRIL 2017
5 Pin Configuration and Functions
DGS Package
10-Pin VSSOP
Top View
A1
A0
1
2
3
4
5
10
9
IN+
INœ
ALERT
SDA
8
VBUS
GND
VS
7
SCL
6
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
A0
NO.
2
Digital input
Digital input
Address pin. Connect to GND, SCL, SDA, or VS. Table 3 lists the pin settings and corresponding addresses.
Address pin. Connect to GND, SCL, SDA, or VS. Table 3 lists the pin settings and corresponding addresses.
A1
1
PMBus-compatible multifunctional alert, open-drain output. This pin alerts on independent settings for
overcurrent, under- and overvoltage, and overpower conditions.
ALERT
3
Digital output
GND
IN–
7
9
Analog
Ground
Analog input
Analog input
Digital input
Digital I/O
Analog input
Analog
Connect to the load side of the shunt resistor
Connect to the supply side of the shunt resistor
Serial bus clock line, open-drain input
Serial bus data line, open-drain input/output
Bus voltage input
IN+
10
5
SCL
SDA
VBUS
VS
4
8
6
Power supply, 2.7 V to 5.5 V
Copyright © 2017, Texas Instruments Incorporated
3
INA233
ZHCSG76 –APRIL 2017
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
6
UNIT
VVS
Supply voltage
V
(2)
Differential (VIN+ – VIN–
)
–40
–0.3
40
40
40
6
Analog Inputs, IN+, IN–
V
Common-mode
VVBUS
VSDA
VA
VBUS pin voltage
–0.3
V
V
SDA, SCL pin voltages
A0, A1 pin voltages
GND – 0.3
GND – 0.3
6
V
IIN
Input current into any pin
Open-drain digital output current
Junction temperature
Storage temperature
5
mA
mA
°C
°C
IOUT
TJ
10
150
150
Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) IN+ and IN– can have a differential voltage between –40 V and 40 V. However, the voltage at these pins must not exceed the range of
–0.3 V to 40 V.
6.2 ESD Ratings
VALUE
±2500
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
0
NOM
MAX
36
UNIT
V
VCM
VVS
TA
Common-mode input voltage
Operating supply voltage
2.7
–40
5.5
V
Operating free-air temperature
125
°C
6.4 Thermal Information
INA233
THERMAL METRIC(1)
DGS (VSSOP)
10 PINS
171.4
42.9
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
91.8
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.5
ψJB
90.2
RθJC(bot)
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2017, Texas Instruments Incorporated
INA233
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ZHCSG76 –APRIL 2017
6.5 Electrical Characteristics
at TA = 25°C, VVS = 3.3 V, VIN+ = 12 V, VSENSE = (VIN+ – VIN–) = 0 mV, and VVBUS = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT
Shunt voltage input range
Bus voltage input range(1)
Common-mode rejection ratio
–81.92
0
81.9175
36
mV
V
CMRR
VOS
0 V ≤ VIN+ ≤ 36 V
126
140
±2.5
±1.25
0.02
10
dB
µV
mV
Shunt voltage
±10
±7.5
0.1
Offset voltage, RTI(2)
Bus voltage
Shunt voltage, –40°C ≤ TA ≤ +125°C
Bus voltage, –40°C ≤ TA ≤ +125°C
Shunt voltage, 2.7 V ≤ VS ≤ 5.5 V
Bus voltage
VOS (RTI(2)) vs temperature
Power-supply rejection ratio (RTI(2)
µV/°C
40
1
µV/V
mV/V
μA
PSRR
IB
)
0.5
Input bias current (IIN+, IIN– pins)
VBUS input impedance
8
830
kΩ
(IN+) + (IN–),
power-down mode
Input leakage(3)
0.1
0.5
µA
DC ACCURACY
ADC native resolution
16
2.5
Bits
μV
Shunt voltage
Bus voltage
1-LSB step size
1.25
mV
Shunt voltage gain error
0.02%
0.1%
25
Shunt voltage gain error vs
temperature
–40°C ≤ TA ≤ +125°C
5
0.02%
10
ppm/°C
ppm/°C
Bus voltage gain error
0.1%
50
Bus voltage gain error vs
temperature
–40°C ≤ TA ≤ +125°C
VBUS = 12 V, VIN+ – VIN– = –80 mV
to 80 mV
Power gain error
0.05%
0.2%
50
Power gain error vs temperature
Differential nonlinearity
–40°C ≤ TA ≤ +125°C
10
±0.1
140
ppm/°C
LSB
DNL
CT bit = 000
CT bit = 001
CT bit = 010
CT bit = 011
CT bit = 100
CT bit = 101
CT bit = 110
CT bit = 111
154
224
204
µs
332
365
588
646
tCT
ADC conversion time
1.1
1.21
2.328
4.572
9.068
2.116
4.156
8.244
ms
ms
SMBus
SMBus timeout(4)
28
35
(1) Although the input range is 36 V, the full-scale range of the ADC scaling is 40.96 V; see the High-Accuracy Analog-to-Digital Convertor
(ADC) section. Do not apply more than 36 V.
(2) RTI = Referred-to-input.
(3) Input leakage is positive (current flowing into the pin) for the conditions shown at the top of this table. Negative leakage currents can
occur under different input conditions.
(4) SMBus timeout in the INA233 resets the interface whenever SCL is low for more than 28 ms.
Copyright © 2017, Texas Instruments Incorporated
5
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ZHCSG76 –APRIL 2017
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Electrical Characteristics (continued)
at TA = 25°C, VVS = 3.3 V, VIN+ = 12 V, VSENSE = (VIN+ – VIN–) = 0 mV, and VVBUS = 12 V (unless otherwise noted)
PARAMETER
DIGITAL INPUT/OUTPUT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input capacitance
3
pF
0 V ≤ VSCL ≤ VVS
0 V ≤ VSDA ≤ VVS
0 V ≤ VAlert ≤ VVS
,
,
,
Leakage input current
0.5
2
µA
0 V ≤ VA0 ≤ VVS
,
0 V ≤ VA1 ≤ VVS
VIH
VIL
High-level input voltage
Low-level input voltage
Low-level output voltage
Hysteresis
SDA pin
SDA pin
1.4
–0.3
0
6
0.4
0.4
V
V
VOL
IOL = 3 mA, SDA and ALERT pins
V
500
mV
POWER SUPPLY
Operating supply range
2.7
5.5
V
IQ
Quiescent current
310
2
400
µA
Quiescent current, power-down
(shutdown) mode
5
µA
V
Power-on-reset (POR) threshold
voltage
VPOR
2
6
版权 © 2017, Texas Instruments Incorporated
INA233
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ZHCSG76 –APRIL 2017
6.6 Typical Characteristics
at TA = 25°C, VVS = 3.3 V, VIN+ = 12 V, VSENSE = (VIN+ – VIN–) = 0 mV, and VVBUS = 12 V (unless otherwise noted)
0
−10
−20
−30
−40
−50
−60
1
10
100 1k
Frequency (Hz)
10k
100k
G001
D002
Input Offset Voltage (mV)
图 1. Frequency Response
图 2. Shunt Input Offset Voltage Production Distribution
160
1
0.8
0.6
0.4
0.2
0
140
120
100
80
-0.2
-0.4
-0.6
-0.8
-1
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Temperature (èC)
Temperature (èC)
D003
D004
图 3. Shunt Input Offset Voltage vs Temperature
图 4. Shunt Input CMRR vs Temperature
100
80
60
40
20
0
-20
-40
-60
-80
-100
-50
-25
0
25
50
75
100
125
150
Temperature (èC)
D006
D005
Input Gain Error (%)
图 6. Shunt Input Gain Error vs Temperature
图 5. Shunt Input Gain Error Production Distribution
版权 © 2017, Texas Instruments Incorporated
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Typical Characteristics (接下页)
at TA = 25°C, VVS = 3.3 V, VIN+ = 12 V, VSENSE = (VIN+ – VIN–) = 0 mV, and VVBUS = 12 V (unless otherwise noted)
100
80
60
40
20
0
-20
-40
-60
-80
-100
0
4
8
12
16
20
24
28
32
36
Common - Mode Input Voltage (V)
D007
Bus Input Offset Voltage (mV)
D008
图 7. Shunt Input Gain Error vs Common-Mode Voltage
图 8. Bus Input Offset Voltage Production Distribution
0
-0.5
-1
-1.5
-2
-2.5
-3
-3.5
-4
-4.5
-5
-50
-25
0
25
50
75
100
125
150
Temperature (èC)
D010
D009
Bus Gain Error (%)
图 9. Bus Input Offset Voltage vs Temperature
图 10. Bus Input Gain Error Production Distribution
100
80
60
40
20
0
-20
-40
-60
-80
-100
-50
-25
0
25
50
75
100
125
150
Temperature (èC)
D012
D011
Power Gain Error (%)
图 11. Bus Input Gain Error vs Temperature
图 12. Power Gain Error Production Distribution
版权 © 2017, Texas Instruments Incorporated
8
INA233
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ZHCSG76 –APRIL 2017
Typical Characteristics (接下页)
at TA = 25°C, VVS = 3.3 V, VIN+ = 12 V, VSENSE = (VIN+ – VIN–) = 0 mV, and VVBUS = 12 V (unless otherwise noted)
200
150
100
50
0
-50
-100
-150
-200
-50
-25
0
25
50
75
100
125
150
Temperature (èC)
D023
D013
CMR (mV/V)
图 13. Power Gain Error vs Temperature
图 14. Input Common-Mode Rejection Distribution
25
20
15
10
5
0
0
4
8
12
16
20
24
28
32
36
Common - Mode Input Voltage (V)
PSR (mV/V)
D016
D024
(IN+) + (IN–)
图 16. Input Bias Current vs Common-Mode Voltage
图 15. Power-Supply Rejection Distribution
20
19
18
17
16
15
14
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-0.2
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Temperature (èC)
Temperature (èC)
D017
D018
(IN+) + (IN–)
(IN+) + (IN–)
图 17. Input Bias Current vs Temperature
图 18. Input Bias Shutdown Current vs Temperature
版权 © 2017, Texas Instruments Incorporated
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ZHCSG76 –APRIL 2017
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Typical Characteristics (接下页)
at TA = 25°C, VVS = 3.3 V, VIN+ = 12 V, VSENSE = (VIN+ – VIN–) = 0 mV, and VVBUS = 12 V (unless otherwise noted)
420
390
360
330
300
270
240
6.5
5.5
4.5
3.5
2.5
1.5
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Temperature (èC)
Temperature (èC)
D019
D020
图 19. Active IQ vs Temperature
图 20. Shutdown IQ vs Temperature
360
340
320
300
80
60
40
20
0
1k
10k
100k
Frequency (Hz)
1M 2M
1k
10k
100k
Frequency (Hz)
1M 2M
D021
D022
图 21. Active IQ vs SCL Frequency
图 22. Shutdown IQ vs SCL Frequency
10
版权 © 2017, Texas Instruments Incorporated
INA233
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ZHCSG76 –APRIL 2017
7 Detailed Description
7.1 Overview
The INA233 is a digital current-sense amplifier with an I2C-, SMBus-, and PMBus-compatible interface. The
device provides digital current, voltage, and power readings necessary for accurate decision-making in precisely-
controlled systems. The INA233 also has a built-in power accumulator that can be used for energy or average
power measurements. Programmable out-of-range limits can be set to issue alerts when the voltage, current, or
power is outside the normal range of operation. The integrated analog-to-digital converter (ADC) can be set to
different averaging modes and configured for continuous-versus-triggered operation. The Register Maps section
provides detailed register information for the INA233.
7.2 Functional Block Diagram
Power Accumulator
Power
Bus Voltage
Current
Shunt Voltage
Channel
ADC
Bus Voltage
Channel
Calibration
Shunt Voltage
Copyright © 2017, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 High-Accuracy Analog-to-Digital Convertor (ADC)
The INA233 integrates a highly accurate, 16-bit, delta-sigma (ΔΣ) ADC. This ADC is multiplexed to process both
the shunt voltage and bus voltage measurements. The shunt voltage measurement is a differential measurement
of the voltage developed when the load current flows through a shunt resistor as measured at the IN+ and IN–
pins. The shunt voltage measurement has an maximum offset voltage of only 10 µV and a maximum gain error
of only 0.1%. The low offset voltage of the shunt voltage measurement allows for increased accuracy at light load
conditions for a given shunt resistor value. Another advantage of low offset is the ability to sense lower voltage
drop across the sense resistor accurately, thus allowing for a lower-value shunt resistor. Lower-value shunt
resistors reduce power loss in the current-sense circuit and help improve the power efficiency of the end
application. The device can also measure the power-supply bus voltage by connecting this voltage to the VBUS
pin. Internally, the voltage at VBUS is divided down to a voltage that can be measured by the ADC. The
impedance of the VBUS pin to ground is approximately 830 kΩ. The differential shunt voltage is measured
between the IN+ and IN– pins and the bus voltage is measured between the VBUS pin and GND.
The device takes two measurements: shunt voltage and bus voltage. The INA233 then converts these
measurements to current, based on the calibration register value, and then calculates power; see the Calibration
Register and Scaling section for additional information on programming the calibration register.
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Feature Description (接下页)
Although the device can be read at any time, and the data from the last conversion remain available, the
conversion ready flag bit (MFR_ALERT_MASK, conversion ready bit) is provided to help coordinate one-shot or
triggered conversions. The conversion ready bit is set after all conversions, averaging, and multiplication
operations are complete.
The conversion ready bit clears under these conditions:
•
•
Writing to the MFR_ADC_CONFIG register, except when configuring the MODE bits for power-down mode; or
Reading the MFR_ALERT_MASK register
7.3.2 Interleaved Power Calculation
The current and shunt voltage measurements are interleaved to minimize time alignment errors in the power
measurement. 图 23 shows that power is calculated following the bus voltage measurement based on the
previous current calculation and bus voltage measurement. The power calculation is performed in the
background and does not add to the overall conversion times for bus voltage or current. These current and
power values are considered intermediate results (unless the averaging is set to 1) and are stored in an internal
accumulation register instead of the corresponding output registers. Following every measured sample, the
newly-calculated values for current and power are appended to this accumulation register until all samples are
measured and averaged based on the number of averages set in the MFR_ADC_CONFIG register.
Current Limit Detect Following
Every Shunt Voltage Conversion
Bus and Power Limit Detect
Following Every Bus Voltage Conversion
V
I
I
V
I
V
I
V
I
V
I
V
I
V
I
V
I
V
I
V
I
V
I
V
I
V
I
V
I
V
I
V
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
Power Average
Bus Voltage Average
Shunt Voltage Average
图 23. Power Calculation Scheme
In addition to the current and power accumulating after every sample, the shunt and bus voltage measurements
are also collected. After all samples are measured and the corresponding current and power calculations are
made, the accumulated average for each parameter is then loaded to the corresponding output registers and can
then be read.
7.3.3 Power Accumulator and Energy Measurement
The INA233 has an integrated power accumulator that records the total accumulated power and the
corresponding sample count and rollover counts. The accumulated power and sample count is accessible
through the READ_EIN PMBus command and can be used for both energy metering and on-demand average
power calculations. The READ_EIN section details how to use the power accumulator for both average power
and energy calculations.
7.3.4 I2C-, SMBus-, and PMBus-Compatible Digital Interface
The INA233 features an I2C-compatible, 2-wire interface with an open-drain alert output. The data transfer format
is SMBus version 3.0 compliant and the device supports multiple PMBus commands that allow the device to be
easily used along side PMBus version 1.3 devices. Logic levels of 0.4 V (maximum VIL) and 1.4 V (minimum VIH)
allow the device to be used with digital bus voltages ranging from 1.8 V to 5.0 V (5.5-V maximum operating). The
digital interface can support clock speeds as high as 400 kHz and offers packet error checking for increased
communications robustness. The device supports group protocol as defined in the PMBus version 1.3.1
specification that allows the host processor to easily communicate with multiple devices on the bus.
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Feature Description (接下页)
7.3.5 Multiple Fault Event Reporting
The INA233 open-drain ALERT pin can report if any of the following errors simultaneously occur:
•
•
•
•
•
•
•
Overcurrent warning
Overpower warning
Bus overvoltage warning
Bus undervoltage warning
Communication faults
ADC overflow
Conversion ready
The warning thresholds for the current, power, and bus voltages are set with the IOUT_OC_WARN_LIMIT,
PIN_OP_WARN_LIMIT, VIN_UV_WARN_LIMIT, and VIN_OV_WARN_LIMIT standard PMBus commands.
Various bus communications faults are supported as outlined in the STATUS_CML PMBus command.
The status for the conversion ready and ADC overflow bits can be monitored by the STATUS_MFR_SPECIFIC
command. The conversion ready bit notifies when the device completes the previous conversion and is ready to
begin a new conversion. Conversion ready can be monitored at the ALERT pin along with one of the alert
functions. If an alert function and the conversion ready are both enabled to be monitored at the ALERT pin, then
after the ALERT pin is asserted, the MFR_ALERT_MASK register or the PMBus status registers must be read
following the alert to determine the source of the alert.
If the alert function is not used, the ALERT pin can be left floating without affecting device operation.
7.4 Device Functional Modes
7.4.1 Continuous verses Triggered Operation
The internal ADC has two operating modes, continuous and triggered, that determine how the ADC operates
following shunt voltage and bus voltage conversions. When the device is in normal operating mode, the INA233
continuously converts a shunt voltage reading followed by a bus voltage reading. After the shunt voltage reading,
the current value is calculated. This current value is then used to calculate the power result. These values are
subsequently stored in an accumulator, and the measurement and calculation sequence repeats until the number
of averages set in the MFR_ADC_CONFIG register is reached. Following every sequence, the present set of
values measured and calculated are appended to previously collected values. After all averaging completes, the
final values for the shunt voltage, bus voltage, current, and power are updated in the corresponding registers that
can then be read.
The MFR_ADC_CONFIG command allows for selecting modes that only convert the shunt voltage or the bus
voltage to further allow the monitoring function to be configured to better fit the specific application requirements.
This command also allows the device to be configured in continuous-versus-triggered operation. In triggered
mode, writing any of the triggered convert modes into the MFR_ADC_CONFIG register triggers a single-shot
conversion. This action produces a single set of measurements; thus, to trigger another single-shot conversion,
the MFR_ADC_CONFIG register must be written to a second time, even if the mode does not change.
7.4.2 Device Shutdown
In addition to the two operating modes (continuous and triggered), the internal ADC also has a power-down
mode that reduces the quiescent current and turns off current into the device inputs, reducing the effect of supply
drain when the device is not being used. Full recovery from power-down mode requires 40 µs. The device
registers can be written to and read from when the device is in power-down mode. The device remains in power-
down mode until one of the active modes settings is selected using the MFR_ADC_CONFIG command.
7.4.3 Averaging and Conversion Time Considerations
The INA233 offers programmable conversion times (tCT) for both the shunt voltage and bus voltage
measurements. The conversion times for these measurements can be selected from as fast as 140 µs to as long
as 8.244 ms. The conversion time settings, along with the programmable averaging mode, allow the device to be
configured to optimize the available timing requirements in a given application. For example, if a system requires
that data be read every 5 ms, the device can be configured with the conversion times set to 588 µs for both
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Device Functional Modes (接下页)
shunt and bus voltage measurements and the averaging mode set to 4. This configuration results in the data
updating approximately every 4.7 ms. The device can also be configured with a different conversion time setting
for the shunt and bus voltage measurements. This type of approach is common in applications where the bus
voltage tends to be relatively stable. This situation can allow for the time focused on the bus voltage
measurement to be reduced relative to the shunt voltage measurement. The shunt voltage conversion time can
be set to 4.156 ms with the bus voltage conversion time set to 588 µs and averaging mode set to 1. This
configuration also results in data updating approximately every 4.7 ms.
There are trade-offs associated with the settings for conversion time and the averaging mode used. The
averaging feature can significantly improve the measurement accuracy by effectively filtering the signal. This
approach allows the device to reduce any noise in the measurement that may be caused by noise coupling into
the signal. A greater number of averages enables the device to be more effective in reducing the noise
component of the measurement.
The conversion times selected can also have an effect on the measurement accuracy. 图 24 shows multiple
conversion times to illustrate the effect of noise on the measurement. In order to achieve the highest accuracy
measurement possible, use a combination of the longest allowable conversion times and highest number of
averages, based on the timing requirements of the system.
Conversion Time: 140ms
Conversion Time: 1.1ms
Conversion Time: 8.244ms
0
200
400
600
800
1000
Number of Conversions
图 24. Noise vs Conversion Time
7.4.4 Filtering and Input Considerations
Measuring current is often noisy and such noise can be difficult to define. The INA233 offers several options for
filtering by allowing the conversion times and number of averages to be selected independently in the
MFR_ADC_CONFIG register. The conversion times can be set independently for the shunt voltage and bus
voltage measurements to allow added flexibility when configuring the monitoring of the power-supply bus.
The internal ADC is based on a delta-sigma (ΔΣ) front-end with a 500-kHz (±10% max) sampling rate. This
architecture has good inherent noise rejection; however, transients that occur at or very close to the sampling
rate harmonics can cause problems. These signals are at 1 MHz and higher and can be managed by
incorporating filtering at the device input. The high frequency enables the use of low-value series resistors on the
filter with negligible effects on measurement accuracy. In general, filtering the device input is only necessary if
there are transients at exact harmonics of the 500 kHz (±10% max) sampling rate (greater than 1 MHz). Filter
using the lowest possible series resistance (typically 10 Ω or less) and a ceramic capacitor. Recommended
values for this capacitor are between 0.1 µF and 1 µF. 图 25 illustrates the device with a filter added at the input.
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Device Functional Modes (接下页)
Supply Voltage
(2,7 V to 5.5 V)
BUS Voltage
(0 V to 36 V)
CBYPASS
0.1 µF
INA233
VBUS
VS
CFILTER
0.1 µF to 1 µF
Ceramic
SDA
SCL
Capacitor
RFILTER
7 10ꢀ
IN+
ALERT
A0
IN-
RFILTER
GND
7 10ꢀ
A1
Load
Copyright © 2016, Texas Instruments Incorporated
图 25. Input Filtering
Overload conditions are another consideration for the device inputs. The device inputs are specified to tolerate
40 V across the inputs. A large differential scenario can be a short to ground on the load side of the shunt. This
type of event can result in full power-supply voltage across the shunt (as long the power supply or energy
storage capacitors can support this voltage). Removing a short to ground can result in inductive kickbacks that
can exceed the 40-V differential and common-mode rating of the device. Inductive kickback voltages are best
controlled by Zener-type, transient-absorbing devices (commonly called transzorbs) combined with sufficient
energy storage capacitance. The Current Shunt Monitor with Transient Robustness Reference Design describes
a high-side, current-shunt monitor used to measure the voltage developed across a current-sensing resistor and
how to better protect the current-sense device from transient overvoltage conditions.
In applications that do not have large energy storage electrolytics on one or both sides of the shunt, an input
overstress condition can result from an excessive dV/dt of the voltage applied to the input. A hard physical short
is the most likely cause of this event, particularly in applications with no large electrolytics present. This problem
occurs because an excessive dV/dt can activate the ESD protection in the device in systems where large
currents are available. Testing demonstrates that the addition of 10-Ω resistors in series with each input of the
device sufficiently protects the inputs against this dV/dt failure up to the 40-V rating of the device. Selecting these
resistors in the range noted has minimal effect on accuracy.
7.5 Programming
The device can be used without any programming only when reading a shunt voltage drop and bus voltage with
the default power-on reset configuration and with continuous conversion of the shunt and bus voltages.
Without setting the device register with the MFR_CALIBRATION command, the device is unable to provide either
a valid current or power value because these outputs are both derived using the values loaded into the
calibration register. The MFR_CALIBRATION command sets the current LSB size based on the desired full-scale
range and value of the shunt resistor.
7.5.1 Default Settings
The default power-up states of the registers are shown in the Register Maps section. These registers are volatile
and, if programmed to a value other than the default values listed in 表 4, must be reprogrammed at every device
power-up. Detailed information on programming the calibration register specifically is given in the Programming
section and calculated based on 公式 1.
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Programming (接下页)
7.5.2 Calibration Register and Scaling
An important aspect of the INA233 is that the device does not necessarily measure current or power. The device
measures both the differential voltage applied between the IN+ and IN– input pins and the voltage applied to the
VBUS pin. By correctly setting the calibration register scaling with the MFR_CALIBRATION command, returned
values are calculated in voltage, amperes, and watts by scaling the returned value by the appropriate lest
significant bit value (LSB) or by using the PMBus direct mode equation (公式 3).
公式 1 is used to obtain the value for the MFR_CALIGRATION register. This equation includes the term
Current_LSB, which is the chosen value for the LSB for the READ_IIN command. As 公式 2 shows, the highest
resolution for current measurements can be obtained by using the smallest allowable Current_LSB based on the
maximum expected current. Although this value yields the highest resolution, the Current_LSB value is
commonly selected as the nearest full number above this value to simplify the conversion of returned values for
current and power to amperes and watts, respectively. The RSHUNT term is the value of the external shunt used to
develop the differential voltage across the input pins.
0.00512
Current_LSB · RSHUNT
CAL =
where
•
0.00512 is an internal fixed value used to ensure that scaling is maintained properly
(1)
(2)
Maximum Expected Current
215
Current_LSB =
After programming the calibration register, the values returned by the read current, power, and energy
commands update accordingly based on the corresponding shunt voltage and bus voltage measurements.
Returned values for voltage, current, and power are calculated by multiplying the appropriate LSB value by the
returned value, or can be calculated with PMBus coefficients as detailed in the Reading and Writing Telemetry
Data and Warning Thresholds section. The size of the Power_LSB is internally set as 25 times the selected
Current_LSB. The voltage LSB for bus voltage (READ_VIN and READ_VOUT commands) and shunt voltage
(MFR_READ_VSHUNT) are fixed at 1.25 mV/bit and 2.5 µV/bit, respectively.
The MFR_CALIBRATION command allows the values returned by the READ_IN and READ_PIN commands to
be scaled to the most useful value for a given application. For example, set the MFR_CALIBRATION register so
that the largest possible number is returned by the READ_IN and READ_PIN commands at the expected full-
scale point. This approach yields the highest resolution using the previously calculated minimum Current_LSB in
公式 1. The calibration register can also be selected so that READ_IN and READ_PIN return direct decimal
equivalents of the values being measured, or to yield a full LSB value for each corresponding register.
7.5.3 Reading and Writing Telemetry Data and Warning Thresholds
All telemetry data are measured using a 16-bit ADC. Telemetry data and user-programmed warning thresholds
are communicated in 16-bit, two's compliment, signed data. Data are read or written in 2-byte increments
conforming to the DIRECT format as described in section 8.3.3 of the PMBus Power System Management
Protocol Specification 1.3 Part II. Device telemetry uses all 16 bits of the internal ADC; however, the warning
registers only use the upper 12 bits for out-of-range comparisons. See each individual warning command
(IOUT_OC_WARN_LIMIT, VIN_OV_WARN_LIMIT, VIN_UV_WARN_LIMIT, and PIN_OP_WARN_LIMIT) for the
format of the warning threshold word.
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Programming (接下页)
7.5.4 Reading Telemetry Data and Warning Thresholds
Conversion from direct format to real-world dimensions of current, voltage, and power is accomplished by
determining the appropriate coefficients as described in section 7.2.1 of the PMBus Power System Management
Protocol Specification 1.3 Part II. According to this specification, the host system converts the received values
using 公式 3 into a reading of volts, amperes, watts, or other such units.
1
(Y x 10-R - b)
X =
m
where
•
•
•
•
•
•
X = the calculated real-world value (volts, amps, watts, and so forth)
m = the slope coefficient
Y = a 2-byte, two's complement integer received from the device
b = the offset, which is a 2-byte, two's complement integer
R = the exponent, which is a 1-byte, two's complement integer
R is only necessary in systems where m is required to be an integer (for example, where m can be stored in a
register of an integrated circuit) and R must only be large enough to yield the desired accuracy
(3)
The values for m and R (listed in 表 1) must be calculated for current and power measurements based off the
selected value of the Current_LSB. For example, assume a Current_LSB of 0.75 mA/bit is selected for a given
application. The value for m is calculated by inverting the LSB value (for this case, m = 1 / 0.00075 = 1333.333).
Moving the decimal point so the value of m is maximized and remains within the required range of –32768 to
32767 is preferable because this value of m is relatively small and contains decimal information. Moving the
decimal point one place to the right results in a final m value of 13333 with an R value of –1 resulting from the
shift in decimal location. Moving the decimal point to maximize the value of m is critical to minimize rounding
errors. The m coefficient for power can be calculated by applying 1 / (25 × Current_LSB). For this example, the
value for the m power coefficient is calculated to be 53.333. Again (to maximize accuracy), the decimal location
is shifted by 2 to the right to give a final m value of 5333 with an R coefficient of –2. Care must be taken to adjust
the exponent coefficient, R, such that the value of m remains within the range of –32768 to 32767. However,
rounding errors resulting from the limitations on the value of m can be mitigated by carefully selecting a slightly
higher current LSB size. For example, if a Current_LSB of 1 mA/bit is selected instead of 0.75 mA/bit, the
calculated value for m is 1 / 0.001 or 1000; because this value is a whole number there is no rounding errors and
the value for R is 0. Positive values for R signify the number of times the decimal point is shifted to the left,
whereas negative values for R signify the number of decimal point shifts to the right.
表 1. Telemetry and Warning Conversion Coefficients (RS in mΩ)
NUMBER OF
DATA BYTES
COMMANDS
FORMAT
DIRECT
DIRECT
m
b
0
0
R
2
UNIT
V
READ_VIN
VIN_OV_WARN_LIMIT
VIN_UV_WARN_LIMIT
2
8
READ_IIN, READ_IOUT
MFR_IIN_OC_WARN_LIMIT
Calculated from
Current_LSB
2
Calculated
A
READ_PIN, READ_EIN
MFR_PIN_OP_WARN_LIMIT
Calculated from
Current_LSB
DIRECT
DIRECT
2
2
0
0
Calculated
5
W
V
MFR_READ_VSHUNT
4
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7.5.4.1 Writing Telemetry Data and Warning Thresholds
There are several PMBus commands that require writing telemetry data in order to be used. Use the same
coefficients previously calculated for the application and apply these coefficients using 公式 4.
Y = (mX + b) × 10R
where
•
•
•
•
•
X = the real-world value (volts, amps, watts, temperature, and so forth)
m = the slope coefficient, a 2-byte, two's complement integer
Y = a 2-byte, two's complement integer written to the device
b = the offset, which is a 2-byte, two's complement integer
R = the exponent, which is a 1-byte, two's complement integer
(4)
7.5.5 System-Level Calibration With MFR_CALIRATION Command
The calibration register also offers possibilities for end-user, system-level calibration. After determining the exact
current by using an external ammeter, the value of the MFR_CALIBRATION register can then be adjusted (as
shown in 公式 5) based on the measured current result of the INA233 to cancel the total system error.
≈
CalìMeasShuntCurrent
Device _Reported_Current
’
Corrected_Full_Scale _Cal = trunc
∆
«
÷
◊
(5)
7.5.6 Bus Overview
The INA233 features an I2C-compatible, 2-wire interface with an open-drain Alert output. The data transfer format
is SMBus version 3.0 compliant and the device supports multiple PMBus commands that allow the device to be
easily used along with PMBus version 1.3 devices.
The device that initiates a data transfer is called a master, and the devices controlled by the master are slaves.
The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access,
and generates START and STOP conditions.
To address a specific device, the master initiates a START condition by pulling the data signal line (SDA) from a
high to a low logic level when SCL is high. All slaves on the bus shift in the slave address byte on the rising edge
of SCL, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the
slave being addressed responds to the master by generating an Acknowledge and pulling SDA low.
Data transfer is then initiated and eight bits of data are sent, followed by an Acknowledge bit. During data
transfer, SDA must remain stable when SCL is high. Any change in SDA when SCL is high is interpreted as a
START or STOP condition.
After all data are transferred, the master generates a STOP condition, indicated by pulling SDA from low to high
when SCL is high. The device includes a 28-ms timeout on the interface to prevent bus lockup.
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7.5.6.1 Serial Bus Address
To communicate with the INA233, the master must first address slave devices via a slave address byte. The
slave address byte consists of seven address bits and a direction bit that indicates whether the action is to be a
read or write operation.
The device has two address pins, A0 and A1. 表 2 lists the pin logic levels for each of the 16 possible addresses.
The device samples the state of the A0 and A1 pins on every bus communication. Establish the pin states before
any activity on the interface occurs.
表 2. Address Pins and Slave Addresses
A1
GND
GND
GND
GND
VS
A0
GND
VS
SLAVE ADDRESS
1000000
1000001
1000010
1000011
1000100
1000101
1000110
1000111
1001000
1001001
1001010
1001011
1001100
1001101
1001110
1001111
SDA
SCL
GND
VS
VS
VS
SDA
SCL
GND
VS
VS
SDA
SDA
SDA
SDA
SCL
SCL
SCL
SCL
SDA
SCL
GND
VS
SDA
SCL
7.5.6.2 Serial Interface
The INA233 operates only as a slave device on both the I2C bus and the SMBus. Connections to the bus are
made via the open-drain SDA and SCL lines. The SDA and SCL pins feature integrated spike-suppression filters
and Schmitt triggers to minimize the effects of input spikes and bus noise. Although the device integrates spike
suppression into the digital I/O lines, proper layout techniques help minimize the amount of coupling into the
communication lines. This noise introduction can occur from capacitively coupling signal edges between the two
communication lines themselves or from other switching noise sources present in the system. Routing traces in
parallel with ground in between layers on a printed circuit board (PCB) typically reduces the effects of coupling
between the communication lines. Shielded communication lines reduce the possibility of unintended noise
coupling into the digital I/O lines that can be incorrectly interpreted as START or STOP commands.
All data bytes are transmitted least significant byte first.
7.5.6.3 Writing to and Reading From the INA233
Both writing and reading to the INA233 is accomplished through the use of various PMBus commands. Each
PMBus command code is an address that allows read or write access to the internal registers; see the PMBus
Command Support section for a complete list of supported PMBus commands and corresponding addresses.
The value for the command address is the first byte transferred after the slave address byte with the R/W bit low.
Every write operation to the device requires a value for the command address.
Writing to the device begins with the first byte transmitted by the master. This byte is the slave address with the
R/W bit low. The device then acknowledges receipt of a valid address. The next byte transmitted by the master is
the PMBus command address to the register that data are written to. This command address value updates the
register pointer to the desired register. The next two bytes are written to the register addressed by the PMBus
command. The device acknowledges receipt of each data byte. The master can terminate data transfer by
generating a START or STOP condition.
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The timing structure for SEND BYTE commands is the same as WRITE WORD commands except no data
packets are sent.
When reading from the device, first the device is written to with the desired PMBus command that is to return the
desired value. This write is accomplished by issuing a slave address byte with the R/W bit low, followed by the
PMBus command code. No additional data are required. The master then generates a repeated START
condition and sends the slave address byte with the R/W bit high to initiate the read command. The next byte is
transmitted by the slave and is the most significant byte of the register indicated by the register pointer. This byte
is followed by an Acknowledge (ACK) from the master; then the slave transmits the least significant byte. The
master acknowledges receipt of the data byte. The master can terminate data transfer by generating a Not-
Acknowledge after receiving any data byte, or by generating a START or STOP condition. If repeated reads from
the same register are desired, the register pointer bytes do not have to be continually sent; the device retains the
register pointer value until the value is changed by the next write operation.
The READ BYTE format has the same timing structure as the READ WORD format except a byte of data is
returned instead of a word.
图 26 shows the write operation timing diagram. 图 27 shows the read operation timing diagram.
注
Register bytes are sent least-significant byte first, followed by the most significant byte.
1
1
9
1
9
1
9
1
9
SkL
{7
{6
{5
{4 {3 {2
{1 {0
{15 {14 {13 {12 {11 {10 {9 {8
Ãr"më 4 {"t" MSaytë
S{!
0
0
!3 !2 !1
!0
R/W
P7
P6
P5
P4
P3
P2
P1
P0
!kK ay
Slave
!kK ay
Slave
Stopay
M"stër
St"rt ay
M"stër
!kK ay
Slave
!kK ay
Slave
Ãr"më 1 Two-W¸rë Sl"vë !||rëss aytë (1)
Ãr"më 2 PMaus komm"n|ko|ë
Ãr"më 3 {"t" LSaytë
(1) The value of the slave address byte is determined by the settings of the A0 and A1 pins; see 表 2.
图 26. Timing Diagram for Write Word Format
1
1
9
1
9
SkL
S{!
0
0
!3
!2
!1
!0
R/W
P7
P6
P5
P4
P3
P2
P1
P0
Stop
St"rt ay
M"stër
!kK ay
Slave
!kK ay
Slave
Ãr"më 1 Two-W¸rë Sl"vë !||rëss aytë (1)
Ãr"më 2 PMaus komm"n| ko|ë
1
9
1
9
1
9
SkL
{15 {14 {13 {12 {11 {10 {9 {8
Ãrom
{7 {6
{5
{4
{3
{2
{1 {0
S{!
1
0
0
!3
!2
!1
!0 R/W
(1)
Ãrom
Slave
No !kK a(y3) Stop
M"stër
RëSt"rt ay
M"stër
!kK ay
Slave
!kK ay
M"stër
Slave
(2)
(2)
Ãr"më 1 Two-W¸rë Sl"vë !||rëss aytë
Ãr"më 2 {"t" LSaytë
Ãr"më 3 {"t" MSaytë
(1) The value of the slave address byte is determined by the settings of the A0 and A1 pins; see 表 2.
(2) Read data are from the previous PMBus command code.
(3) An Acknowledge by the master can also be sent.
图 27. Timing Diagram for Read Word Format
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A block read is similar to the read word format in that first the device is written to with the desired PMBus
command that is to return the desired value. This write is accomplished by issuing a slave address byte with the
R/W bit low, followed by the PMBus command code. The master then generates a repeated START condition
and sends the slave address byte with the R/W bit high to initiate the read command. The next byte is
transmitted by the slave is the total number of bytes that are sent to the master. This byte is followed by an
Acknowledge (ACK) from the master; then the slave transmits the first data byte. At the end of each byte the
master sends an Acknowledge and the next byte is sent by the slave. The master can terminate data transfer by
generating a Not-Acknowledge after receiving any data byte, or by generating a START or STOP condition.
图 28 shows the block read operation timing diagram. 图 29 shows the timing diagram for the SMBus Alert
response operation.
9
1
9
1
9
1
SkL
1
0
0
!3
!2
!1
!0
S{!
1
0
0
!3
!2
!1
!0 R/W
P7
P6
P5
P4
P3
P2
P1
P0
R/W
St"rt ay
M"stër
!kK ay
Slave
!kK ay Rëpë"të| St"rt
Sl"vë ay M"stër
!kK ay
Master
Ãr"më 1 Sl"vë !||rëssaytë(1)
Ãr"më 2 PMaus komm"n|ko|ë
Ãr"më 3 Sl"vë !||rëssaytë
1
9
1
9
1
9
SkL
{7 {6
{5
{4
{3 {2 {1 {0
{7 {6
{5
{4
{3 {2 {1 {0
{7 {6
{5
{4
{3 {2
{1 {0
S{!
!kK ay
Master
No !kK ay
Master
Stopby
M"stër
!kK ay
Master
Ãr"më 4 Numbër oÕ
aytës = N
Ãr"më 5 {"t" aytë 1
Ãr"më N+4 {"t" aytë N
A. The value of the slave address byte is determined by the settings of the A0 and A1 pins; see 表 2.
图 28. Timing Diagram for Block Read Format
ALERT
1
9
1
9
SCL
SDA
0
0
0
1
1
0
0
R/W
1
0
0
A3
A2
A1
A0
0
Start By
Master
ACK By
From
Slave
NACK By Stop By
Master Master
Slave
Frame 1 SMBus ALERT Response Address Byte
Frame 2 Slave Address Byte(1)
(1) The value of the slave address byte is determined by the settings of the A0 and A1 pins; see 表 2.
图 29. Timing Diagram for SMBus ALERT Response
7.5.6.3.1 Packet Error Checking
The INA233 supports packet error checking as described in the SMBus version 3.0 specification. Packet error
checking is a method to improve the reliably and communication robustness of the digital interface. Packet error
checking is implemented by appending a packet error code (PEC) at the end of each message transfer. To
maximize compatibly, devices that support packet error checking must be able to communicate with the host and
other devices that do not support the error checking protocol. Therefore, packet error checking can help improve
the communication robustness when desired but is optional when not supported by the master or other devices
on the bus. See the SMBus version 3.0 specification for additional details on implementing packet error checking
in an SMBus environment.
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7.5.6.3.2 Bus Timing Requirements
When the bus is idle, both the SDA and SCL lines are pulled high by the pullup resistors. The master generates
a START condition followed by a valid serial byte containing high-speed (HS) master code 00001XXX. This
transmission can be made at 400-kHz data rates. 图 30 shows a timing diagram for the bus and 表 3 lists the bus
timing definitions.
t(LOW)
tF
tR
t(HDSTA)
SCL
SDA
t(SUSTO)
t(HDSTA)
t(HIGH) t(SUSTA)
t(HDDAT)
t(SUDAT)
t(BUF)
S
P
P
S
图 30. Bus Timing Diagram
表 3. Bus Timing Definitions(1)
MIN
MAX
UNIT
kHz
µs
f(SCL)
t(BUF)
SCL operating frequency
10
400
Bus free time between STOP and START conditions
0.6
Hold time after a repeated START condition.
After this period, the first clock is generated.
t(HDSTA)
0.6
µs
t(SUSTA)
t(SUSTO)
t(HDDAT)
t(SUDAT)
t(LOW)
t(HIGH)
tF
Repeated START condition setup time
STOP condition setup time
Data hold time
0.6
0.6
0
µs
µs
ns
ns
µs
µs
ns
ns
ns
Data setup time
100
1.3
0.6
SCL clock low period
SCL clock high period
Data fall time
50
300
300
300
tF
Clock fall time
tR
Clock rise time
(1) Values are based on a statistical analysis of a one-time sample of devices. Minimum and maximum values are not specified and are not
production tested.
7.5.6.4 SMBus Alert Response
When SMBus alerts are latched, the INA233 is designed to respond to the SMBus alert response address. The
SMBus alert response provides a quick fault identification for simple slave devices. When an alert occurs, the
master can broadcast the alert response slave address (0001 100) with the R/W bit set high. Following this alert
response, any slave device that generates an alert is identified by acknowledging the alert response and sending
its address on the bus.
The alert response can activate several different slave devices simultaneously, similar to the I2C general call. If
more than one slave attempts to respond, bus arbitration rules apply and the device with the lowest address wins
and is serviced first. The losing devices do not generate an Acknowledge and continue to hold the alert line low
until the interrupt is cleared. The winning device responds with its address and releases the SMBus alert line.
Even though the INA233 releases the SMBus line, the internal error flags are not cleared until done so by the
host.
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7.6 Register Maps
7.6.1 PMBus Command Support
The device features an SMBus interface that allows the use of PMBus commands to set warn levels, error
masks, and obtain telemetry on bus voltage, current, power, and shunt voltage. 表 4 lists the supported PMBus
commands.
表 4. Supported PMBus Commands
NUMBER
DEFAULT
CODE
NAME
FUNCTION
R/W
OF DATA
BYTES
VALUE
Clears the status registers and rearms the black
box registers for updating
03h
CLEAR_FAULTS
Send byte
0
N/A
12h
19h
RESTORE_DEFAULT_ALL
CAPABILITY
Restores internal registers to the default values
Retrieves the device capability
Send byte
R
0
1
N/A
B0h
Retrieves or stores the output overcurrent warn
limit threshold
4Ah
57h
58h
6Bh
78h
79h
IOUT_OC_WARN_LIMIT
VIN_OV_WARN_LIMIT
VIN_UV_WARN_LIMIT
PIN_OP_WARN_LIMIT
STATUS BYTE
R/W
R/W
R/W
R/W
R
2
2
2
2
1
2
7FF8h
7FF8h
0000h
7FF8h
00h
Retrieves or stores the input overvoltage warn
limit threshold
Retrieves or stores the input undervoltage warn
limit threshold
Retrieves or stores the output overpower warn
limit threshold
Retrieves information about the device operating
status
Retrieves information about the device operating
status
STATUS_WORD
R
1000h
Retrieves information about the output current
status
7Bh
7Ch
7Eh
STATUS_IOUT
STATUS_INPUT
STATUS_CML
R/W, CLR
R/W, CLR
R/W, CLR
1
1
1
00h
00h
00h
Retrieves information about the input status
Retrieves information about the communications
status
Retrieves information about the manufacturer
specific device status
80h
86h
STATUS_MFR_SPECIFIC
READ_EIN
R/W, CLR
Block read
1
6
20h
00h, 00h,
00h, 00h,
00h, 00h
Retrieves the energy reading measurement
88h
89h
READ_VIN
READ_IN
Retrieves the measurement for the VBUS voltage
R
R
2
2
0000h
Retrieves the input current measurement,
supports both positive and negative currents
0000h
8Bh
8Ch
READ_VOUT
READ_IOUT
Mirrors READ_VIN
R
R
2
2
0000h
0000h
Mirror of READ_IN for compatibility
Mirror of READ_PIN for compatibility with
possible VBUS connections
96h
97h
99h
READ_POUT
READ_PIN
MFR_ID
R
R
2
2
2
0000h
0000h
Retrieves the input power measurement
Retrieves the manufacturer ID in ASCII
characters (TI)
Block read
54h, 49h
49h, 4Eh,
41h, 32h,
33h, 33h
Retrieves the device number in ASCII characters
(INA233)
9Ah
MFR_MODEL
Block read
6
Retrieves the device revision letter and number in
ASCII (for instance, A0)
9Bh
D0h
MFR_REVISION
R
2
2
41h, 30h
4127h
Configures the ADC averaging modes,
conversion times, and operating modes
MFR_ADC_CONFIG
R/W
D1h
D2h
MFR_READ_VSHUNT
MFR_ALERT_MASK
Retrieves the shunt voltage measurement
Allows masking of device warnings
R
2
1
0000h
F0h
R/W
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Register Maps (接下页)
表 4. Supported PMBus Commands (接下页)
NUMBER
OF DATA
BYTES
DEFAULT
VALUE
CODE
NAME
FUNCTION
R/W
Allows the value of the current-sense resistor
D4h
MFR_CALIBRATION
calibration value to be input. Must be programed
at power-up. Default value is set to 1.
R/W
2
0001h
D5h
D6h
MFR_DEVICE_CONFIG
CLEAR_EIN
Allows the ALERT pin polarity to be changed
Clears the energy accumulator
R/W
1
0
02h
N/A
Send byte
ASCII TI,
5449h
E0h
E1h
E2h
TI_MFR_ID
Returns a unique word for the manufacturer ID
R
R
R
2
2
2
Returns a unique word for the manufacturer
model
TI_MFR_MODEL
TI_MFR_REVISION
ASCII 33
ASCII A0
Returns a unique word for the manufacturer
revision
7.6.2 Standard PMBus Commands
7.6.2.1 CLEAR_FAULTS (03h)
CLEAR_FAULTS is a standard PMBus command that resets all stored warning and fault flags and the alert
signal. If a fault or warning condition still exists when the CLEAR_FAULTS command is issued, the ALERT signal
clears but reasserts almost immediately. This command uses the PMBus send byte protocol.
7.6.2.2 RESTORE_DEFAULT_ALL (12h)
The RESTORE_DEFAULT_ALL command restores the internal device register settings to the default values.
注
When issued, values in the calibration register are cleared and must be reconfigured by
the master.
7.6.2.3 CAPABILITY (19h)
The CAPABILITY command is a standard PMBus command that returns information about the PMBus functions
supported by the INA233. This command is read with the PMBus read byte protocol.
表 5. CAPABILITY Register
VALUE
MEANING
DEFAULT
B0h
Supports packet error check, 400 kbits/sec, supports SMBus alert response address
(ARA)
B0h
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7.6.2.4 IOUT_OC_WARN_LIMIT (4Ah) [default = 01111111 11111000]
This command is an overcurrent warn limit. This standard PMBus command is used to set or read the threshold
of the first level warning of high output currents. Use the PMBus read or write word protocol to access this
command. The contents of the IOUT_OC_WARN_LIMIT register are compared to the current-sense ADC
telemetry value to detect high output current. This warning threshold applies to both positive and negative
currents.
Enter the value in the register in amps with the same scaling and coefficients used for reading current.
When this input overcurrent warning limit is exceeded, the device:
•
•
•
•
•
•
Sets the NONE OF THE ABOVE bit in the STATUS_BYTE register
Sets the IOUT bit in the STATUS_WORD register
Sets the IOUT_OC_WARNING bit in the STATUS_IOUT register
Sets the INPUT bit in the STATUS_WORD register
Sets the IIN_OC_WARNING bit in the STATUS_INPUT register
Notifies (if unmasked) the host using the ALERT pin
This warning is masked with the MFR_ALERT_MASK command with the IIN_OC_WARN bit.
See the Reading and Writing Telemetry Data and Warning Thresholds and Writing Telemetry Data and Warning
Thresholds sections for additional information on reading and setting warning thresholds.
图 31. IOUT_OC_WARN_LIMIT
15
—
14
13
12
IO9
11
IO8
10
IO7
9
8
IO11
R/W-1
IO10
R/W-1
IO6
IO5
R-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
7
6
5
4
3
2
1
0
IO4
IO3
IO2
IO1
IO0
—
—
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R-0
R-0
R-0
表 6. IOUT_OC_WARN_LIMIT Field Descriptions
Bit
Field
—
Type
R
Default
Description
15
0
1
Reserved; always 0.
14:3
IO[11:0]
R/W
These bits control the IOUT_OC_WARN_LIMIT. The bit
weightings in this register match the bit weightings in the
READ_IOUT register (IO0 = II3).
2:0
—
R
0
Reserved; always 0.
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7.6.2.5 VIN_OV_WARN_LIMIT (57h) [default = 01111111 11111000]
VIN_OV_WARN_LIMIT is a standard PMBus command that allows configuring or reading the threshold for a
VBUS overvoltage warning detection. Use the coefficients listed in 表 1 when reading and writing to this register.
Use the PMBus read or write word protocol to access this command.
When this input overvoltage warning limit is exceeded, the device:
•
•
•
•
Sets the NONE OF THE ABOVE bit in the STATUS_BYTE register
Sets the INPUT bit in the STATUS_WORD register
Sets the IOUT_OC_WARNING bit in the STATUS_INPUT register
Notifies (if unmasked) the host using the ALERT pin
This fault is masked with the MFR_ALERT_MASK command using the VIN_OV_WARNING
See the Reading and Writing Telemetry Data and Warning Thresholds and Writing Telemetry Data and Warning
Thresholds sections for additional information on reading and setting warning thresholds.
Full-scale range = 40.96 V (7FFFh) and LSB = 1.25 mV.
图 32. VIN_OV_WARN_LIMIT
15
—
14
13
12
V9
11
V8
10
V7
9
8
V11
V10
V6
V5
R-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
7
6
5
4
3
2
1
0
V4
V3
V2
V1
V0
—
—
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R-0
R-0
R-0
表 7. VIN_OV_WARN_LIMIT Field Descriptions
Bit
Field
—
Type
R
Default
Description
15
0
1
Reserved; always 0.
14:3
V[11:0]
R/W
These bits control the VIN_OV_WARN_LIMIT. The bit weightings
in this register match the bit weightings in the READ_VIN register
(V0 = BV3).
2:0
—
R/W
0
Reserved; always 0.
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7.6.2.6 VIN_UV_WARN_LIMIT (58h) [default = 00000000 00000000]
VIN_UV_WARN_LIMIT is a standard PMBus command that allows configuring or reading the threshold for the
VBUS undervoltage warning detection. Use the coefficients listed in 表 1 when reading and writing to this
register. Use the PMBus read or write word protocol to access this command.
When this input undervoltage warning limit is exceeded, the device:
•
•
•
•
Sets the NONE OF THE ABOVE bit in the STATUS_BYTE register
Sets the INPUT bit in the STATUS_WORD register
Sets the VIN_UV_WARNING bit in the STATUS_INPUT register
Notifies (if unmasked) the host using the ALERT pin
This fault is masked with the MFR_ALERT_MASK command using the VIN_UV_WARNING bit.
See the Reading and Writing Telemetry Data and Warning Thresholds and Writing Telemetry Data and Warning
Thresholds sections for additional information on reading and setting warning thresholds.
Full-scale range = 40.96 V (7FFFh) and LSB = 1.25 mV.
图 33. VIN_UV_WARN_LIMIT
15
—
14
13
12
V9
11
V8
10
V7
9
8
V11
V10
V6
V5
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
V4
V3
V2
V1
V0
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R-0
R-0
表 8. VIN_UV_WARN_LIMIT Field Descriptions
Bit
Field
—
Type
R
Default
Description
15
0
0
Reserved; always 0.
14:3
V[11:0]
R/W
These bits control the VIN_UV_WARN_LIMIT. The bit weightings
in this register match the bit weightings in the READ_VIN register
(V0 = BV3).
2:0
—
R
0
Reserved; always 0.
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7.6.2.7 PIN_OP_WARN_LIMIT (6Bh) [default = 11111111 11110000]
PIN_OP_WARN_LIMIT is a standard PMBus command that allows setting or reading the threshold for the input
overpower warning. Use the PMBus read or write word protocol to access the POUT_OP_WARN_LIMIT
command. The contents of this register are compared to the calculated telemetry power value.
When the PIN_OP_WARN_LIMIT is exceeded, the device:
•
•
•
Sets the INPUT bit in the upper byte of the STATUS_WORD register
Sets the PIN_OP_WARNING bit in the STATUS_INPUT register
Notifies the host by asserting the ALERT pin
This warning is masked with the MFR_ALERT_MASK command using the IIN_OP_WARNING bit.
图 34. PIN_OP_WARN_LIMIT
15
14
13
D9
12
D8
11
D7
10
D6
9
8
D11
D10
D5
D4
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
7
6
5
4
3
2
1
0
D3
D2
D1
D0
—
—
—
—
R/W-1
R/W-1
R/W-1
R/W-1
R-0
R-0
R-0
R-0
表 9. PIN_OP_WARN_LIMIT Field Descriptions
Bit
Field
Type
Default
Description
15:4
D[11:0]
R/W
1
These bits control the VIN_UV_WARN_LIMIT. The bit weightings
in this register match the bit weightings in the READ_PIN register
(D0 = P4).
3:0
—
R
0
Reserved; always 0.
7.6.2.8 STATUS_BYTE (78h)
STATUS_BYTE is a standard PMBus command that returns the value of a number of flags indicating the state of
the INA233. Use the PMBus read byte protocol to access this command. To clear bits in this register, clear the
underlying fault and issue a CLEAR_FAULTS command. 表 10 lists the definitions for this command.
表 10. STATUS_BYTE Definitions
BIT
7
NAME
BUSY
MEANING
Not supported
DEFAULT
0
0
0
0
0
0
0
0
6
OFF
Not supported
5
VOUT_OV
IOUT_OC
Not supported
4
Not supported
3
VIN_UV
Not supported
2
TEMPERATURE
CML
Not supported
1
A communication fault has occurred
0
NONE OF THE ABOVE
A fault or warning not listed in bits[7:1] has
occurred
NONE OF THE ABOVE (bit 0) is set by the logical OR of the following status bits from other registers:
•
•
•
•
IOUT_OC_WARNING
VIN_OV_WARNING
VIN_UV_WARNING
IIN_OC_WARNING
This bit can only be cleared by clearing all the contributing status bits.
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7.6.2.9 STATUS_WORD (79h)
STATUS_WORD is a standard PMBus command that returns the value of a number of flags indicating the state
of the INA233. Use the PMBus read word protocol to access this command. To clear bits in this register, clear
the underlying fault and issue a CLEAR_FAULTS command. The INPUT and VIN UV flags default to 1 on
startup. 表 11 lists the definitions for this command.
表 11. STATUS_WORD Definitions
BIT
15
NAME
VOUT
MEANING
DEFAULT
Not supported
0
0
14
IOUT/POUT
An output current or power warning has
occurred
13
12
INPUT
MFR
An input voltage, current, or power warning
has occurred
0
1
A manufacturer-specific fault or warning has
occurred
11
10
9
POWER_GOOD#
FANS
Not supported
Not supported
0
0
0
0
0
0
0
0
0
0
0
0
OTHER
Not supported
8
UNKNOWN
BUSY
Not supported
7
Not supported
6
OFF
Not supported
5
VOUT_OV
IOUT_OC
VIN_UV
Not supported
4
Not supported
3
Not supported
2
TEMPERATURE
CML
Not supported
1
A communication fault has occurred
0
NONE OF THE ABOVE
A fault or warning not listed in bits[7:1] has
occurred
7.6.2.10 STATUS_IOUT (7Bh)
STATUS_IOUT is a standard PMBus command that returns the value of the of a number of flags related to
output, current, and power. Use the PMBus read byte protocol to access this command. To clear bits in this
register, clear the underlying fault and issue a CLEAR_FAULTS command or write a 1 to the bit to be cleared. 表
12 lists the definitions for this command.
表 12. STATUS_IOUT Definitions
BIT
7
NAME
IOUT_OC fault
MEANING
Not supported
DEFAULT
0
0
0
0
0
0
0
0
6
IOUT_OC fault with LV shutdown
IOUT_OC_WARN
IOUT_UC fault
Not supported
5
An input undercurrent warning has occurred
Not supported
4
3
Current share fault
In power-limiting mode
POUT_OP fault
Not supported
2
Not supported
1
Not supported
0
POUT_OP_WARN
Not supported
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7.6.2.11 STATUS_INPUT (7Ch)
STATUS_INPUT is a standard PMBus command that returns the value of the of a number of flags related to
input voltage, current, and power. Use the PMBus read byte protocol to access this command. To clear bits in
this register, clear the underlying fault and issue a CLEAR_FAULTS command or write a 1 to the bit to be
cleared. 表 13 lists the definitions for this command.
表 13. STATUS_INPUT Definitions
BIT
7
NAME
MEANING
Not supported
DEFAULT
VIN_OV fault
0
0
0
0
0
0
0
0
6
VIN_OV_WARN
VIN_UV_WARN
VIN_UV fault
An input overvoltage warning has occurred
An input undervoltage warning has occurred
Not supported
5
4
3
Insufficient voltage
IIN_OC fault
Not supported
2
Not supported
1
IIN_OC_WARN
PIN_OP_WARN
An input overcurrent warning has occurred
An input overpower warning has occurred
0
7.6.2.12 STATUS_CML (7Eh)
STATUS_CML is a standard PMBus command that returns the value of a number of flags related to
communication faults. Use the PMBus read byte protocol to access this command. To clear bits in this register,
issue a CLEAR FAULTS command or write a 1 to the bit to be cleared. 表 14 lists the definitions for this
command.
表 14. STATUS_CML Definitions
BIT
7
MEANING
Invalid or unsupported command received
Not supported
DEFAULT
0
0
0
0
0
0
0
0
6
5
Packet error check failed
Memory fault detected (trim fuse CRC failed, ECC active)
Not supported
4
3
2
Reserved
1
Not supported
0
Not supported
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7.6.2.13 STATUS_MFR_SPECIFIC (80h)
STATUS_MFR_SPECIFIC is
a standard PMBus command that contains manufacturer-specific status
information. Use the PMBus read byte protocol to access this command. To clear bits in this register, clear the
underlying fault and issue a CLEAR_FAULTS command or write a 1 to the bit to be cleared. 表 15 lists the
definitions for this command.
表 15. STATUS_MFR_SPECIFIC Definitions
BIT
7
MEANING
DEFAULT
Conversion ready
0
0
6
Arithmetic overflow flag. If the bit is set to 1 then an arithmetic
operation results from an overflow error. This bit indicates that
either the current or power data is invalid.
5
Power-on-reset event detected. To detect power-on or power
glitch events, this bit must be cleared after initial power up. If
power is interrupted this bit is reset to the default value of 1.
1
4
3
2
1
0
Communications or memory fault (or of STATUS_CML)
Input overpower warning
0
0
0
0
0
Input overcurrent warning
Input overvoltage warning
Input undervoltage warning
7.6.2.14 READ_EIN (86h)
READ_EIN is a command that returns information that the host can use to calculate energy or to average input
power consumption. Use the PMBus block read protocol to access this command. Six bytes of data are returned
by this command. The first two bytes are the 16-bit, unsigned output of an accumulator that continuously sums
samples of the instantaneous input power. These two data bytes are formatted such that returned values can be
converted to watts using the power m, b, and R coefficients. The third data byte is a count of the rollover events
for the accumulator. This byte is an unsigned integer indicating the number of times that the accumulator has
rolled over from the maximum positive value (FFFFh) to zero. The last three data bytes are a 24-bit unsigned
integer that counts the number of samples of the instantaneous input power that are applied to the accumulator.
The combination of the accumulator and the rollover count can overflow within a few seconds depending on the
ADC conversion time. The host software must detect and appropriately handle this overflow. Similarly, the
sample count value overflows, but this event only occurs one time every few hours using 1-ms ADC conversion
times.
To convert the data obtained with the READ_EIN command to average power, first convert the accumulator and
rollover count to an unsigned integer.
Total Accumulated Unscaled Power (Accumulator_24) = (rollover_count × 216) + Accumulator
Overflow detection and handling are done on the 24 bits of accumulator data and the sample count now. As
shown in 公式 6, data from the previous calculation must be saved and used in this calculation to obtain the
unscaled average power. 表 16 lists the definitions for this command.
Accumulator _ 24 n - Accumulator _ 24 n -1
[ ]
[
]
Sample _count n - Sample _count n -1
where
•
•
•
accumulator_24 [n] = Overflow corrected, 24-bit accumulator data from this read
Sample_count [n] = Sample count data from this read
accumulator_24[n-1] = Overflow corrected 24-bit accumulator data from the previous read Sample_count [n-1]
= Sample count data from the previous read
•
•
Unscaled average power is now in the same units as the data from the READ_PIN command
PMBus coefficients are used to convert the unscaled average power to watts
(6)
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表 16. READ_EIN Definitions
BYTE
MEANING
DEFAULT
6
5
4
3
2
1
0
Sample count high byte
Sample count mid byte
Sample count low byte
Power accumulator rollover count
Power accumulator high byte
Power accumulator low byte
Number of bytes
0
0
0
0
0
0
6
When the average power is calculated over a known number of samples, energy can be calculated by taking the
product of the average power and the time interval for that average. The time interval can be externally
measured or calculated by multiplying the number of samples reported by the ADC conversion time inclusive of
any device averaging modes. However, calculating the energy consumption using the ADC conversion time
results in a 10% error in the energy reading because of variations in the internal sampling oscillator. For
increased precision in the energy measurement, using a higher accuracy external time measurement method is
recommended.
The energy accumulator can be configured by the MFR_DEVICE_CONFIG command to automatically clear with
each READ_EIN command. The ability to clear the accumulator on a read permits the device to be easily
synchronised to an external timer and allows the accumulator to always start at 0, thus eliminating the need to
subtract the initial accumulated values and sample counts.
The READ_EIN power accumulator can also be cleared by issuing
a CLEAR_EIN command or
RESTORE_DEFAULTS_ALL command. Clearing the power accumulator with the RESTORE_DEFAULTS_ALL
command is not recommended because this command also clears the calibration register used to scale the
accumulated power.
7.6.2.15 READ_VIN (88h)
READ_VIN is a standard PMBus command that returns the 16-bit measured value of the input voltage as read
from the VBUS pin. Use the coefficients listed in 表 1 to read this register. Use the PMBus read word protocol to
access this command. This value is also used internally for the VIN_OV_WARN and VIN_UV_WARN detection.
表 17. READ_VIN Register
VALUE
MEANING
DEFAULT
0h–7FFFh Measured value for VBUS
0000h
Full-scale range = 40.96 V (7FFFh) and LSB = 1.25 mV.
7.6.2.16 READ_IIN (89h)
READ_IN is a standard PMBus command that returns the 16-bit signed value of the sensed current. Use the
PMBus read word protocol to access this command. This value is also used internally for the IOUT_OC_WARN
detection.
表 18. READ_IIN Register
VALUE
MEANING
DEFAULT
0000h–FFFFh Measured value for IIN
0000h
If averaging is enabled, this register displays the averaged value. The value returned by the READ_IIN command
is calculated by multiplying the decimal value in the READ_VHSUNT_OUT register with the decimal value of the
MFR_CALIBRATION register.
7.6.2.17 READ_VOUT (8Bh)
This command is a mirror of the READ_VIN command supported for cases where VBUS is connected to the
output.
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7.6.2.18 READ_IOUT (8Ch, R)
This command is a mirror of the READ_IOUT command for software compatibility.
7.6.2.19 READ_POUT (96h, R)
READ_POUT is mirror of the READ_PIN command to support applications that connect the VBUS pin to the
output.
7.6.2.20 READ_PIN (97h, R)
READ_PIN is a standard PMBus command that returns the 16-bit measured unsigned absolute value of the input
power when VBUS is connected to the input.
Use the PMBus read word protocol to access this command. This value is also used internally for the
POUT_OP_WARN detection.
表 19. READ_PIN Register
VALUE
MEANING
DEFAULT
0h–FFFFh
Measured value for PIN
0000h
7.6.2.21 MFR_ID (99h)
MFR_ID is a standard PMBus command that returns the identification of the manufacturer. Use the PMBus block
read protocol to read the manufacturer ID.
表 20. MFR_ID Register
BYTE
NAME
Number of bytes
MFR ID-1
VALUE
02h
0
1
2
54h, ASCII (T)
49h, ASCII (I)
MFR ID-2
7.6.2.22 MFR_MODEL (9Ah)
MFR_MODEL is a standard PMBus command that returns the part number of the device. Use the PMBus block
read protocol to read the manufacturer model.
表 21. MFR_MODEL Register
BYTE
NAME
VALUE
0
1
2
3
4
5
6
Number of bytes
MFR MODEL-1
MFR MODEL-2
MFR MODEL-3
MFR MODEL-4
MFR MODEL-5
MFR MODEL-6
06h
49h, ASCII (I)
4Eh, ASCII (N)
41h, ASCII (A)
32h, ASCII (2)
33h, ASCII (3)
33h, ASCII (3)
7.6.2.23 MFR_REVISION (9Bh)
MFR_REVISION is a standard PMBus command that returns the revision level of the device. Use the PMBus
block read protocol to read the manufacturer revision.
表 22. MFR_REVISION Register
BYTE
NAME
VALUE
02h
0
1
2
Number of bytes
MFR REV-1
MFR REV-2
41h, ASCII (A)
41h, ASCII (0)
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7.6.3 Manufacturer-Specific PMBus Commands
7.6.3.1 MFR_ADC_CONFIG (D0h) [default = 01000001 00100111]
The MFR_ADC_CONFIG command settings control the operating modes for the device ADC. This command
controls the conversion time settings for both the shunt and bus voltage measurements as well as the averaging
mode used. The operating mode that controls what signals are selected to be measured is also set with this
command. Reading with the MFR_ADC_CONFIG command can be done at any time without affecting the device
settings or a conversion in progress. Writing with the MFR_ADC_CONFIG command halts any conversion in
progress until the write sequence is completed, resulting in a new conversion starting based on the updated
contents. This halt prevents any uncertainty in the conditions used for the next completed conversion.
图 35. MFR_ADC_CONFIG
15
—
14
—
13
—
12
—
11
10
9
8
AVG2
R/W-0
AVG1
R/W-0
AVG0
R/W-0
VBUSCT2
R/W-1
R-0
R-1
R-0
R-0
7
6
5
4
3
2
1
0
VBUSCT1
R/W-0
VBUSCT0
R/W-0
VSHCT2
R/W-1
VSHCT1
R/W-0
VSHCT0
R/W-0
MODE3
R/W-1
MODE2
R/W-1
MODE1
R/W-1
表 23. MFR_ADC_CONFIG Field Descriptions
Bit
15
14
13:12
11
10
9
Field
Type
Default
Description
—
R
0
1
0
0
0
0
1
0
0
1
0
0
1
Reserved.
AVG2
AVG1
AVG0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Averaging mode.
These bits determine the number of samples that are collected
and averaged. 表 24 lists AVG bit settings and related number of
averages for each bit setting.
8
VBUSCT2
VBUSCT1
VBUSCT0
VSHCT2
Bus voltage conversion time.
These bits set the conversion time for the bus voltage
measurement. 表 25 lists the VBUSCT bit options and related
conversion times for each bit setting.
7
6
5
Shunt voltage conversion time.
These bits set the conversion time for the shunt voltage
measurement. 表 26 lists the VSHCT bit options and related
conversion times for each bit setting.
4
VSHCT1
3
VSHCT0
2:0
MODE[3:1]
Operating mode.
These bits select the continuous, triggered, or power-down mode
of operation. These bits default to continuous shunt and bus
measurement mode. 表 27 lists the mode settings.
表 24. AGV[2:0] Bit Setting Combinations
NUMBER OF
AVERAGES
AVG2
AVG1
AVG0
0 (default)
0 (default)
0 (default)
1 (default)
4
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
16
64
128
256
512
1024
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表 25. VBUSCT[2:0] Bit Setting Combinations
VBUSCT2
VBUSCT1
VBUSCT0
CONVERSION TIME
140 µs
0
0
0
0
0
1
204 µs
0
1
0
332 µs
0
1
1
588 µs
1 (default)
0 (default)
0 (default)
1.1 ms (default)
2.116 ms
1
1
1
0
1
1
1
0
1
4.156 ms
8.244 ms
表 26. VSHCT[2:0] Bit Setting Combinations
VSHCT2
VSHCT1
VSHCT0
CONVERSION TIME
140 µs
0
0
0
0
0
1
204 µs
0
1
0
332 µs
0
1
1
588 µs
1 (default)
0 (default)
0 (default)
1.1 ms (default)
2.116 ms
1
1
1
0
1
1
1
0
1
4.156 ms
8.244 ms
表 27. Mode[3:1] Bit Settings Combinations
MODE3
MODE2
MODE1
MODE
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Power-down (or shutdown)
Shunt voltage, triggered
Bus voltage, triggered
Shunt and bus, triggered
Power-down (or shutdown)
Shunt voltage, continuous
Bus voltage, continuous
Shunt and bus, continuous
(default)
1 (default)
1 (default)
1 (default)
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7.6.3.2 MFR_READ_VSHUNT (D1h) [default = 00000000 00000000]
This register stores the current shunt voltage reading, VSHUNT. Negative numbers are represented in two's-
complement format. Generate the two's complement of a negative number by complementing the absolute value
binary number and adding 1. An MSB = 1 denotes a negative number.
If averaging is enabled, this register displays the averaged value. Full-scale range = 81.92 mV (7FFFh) and LSB:
2.5 µV.
This command only supports the PMBus direct data format.
图 36. MFR_READ_VSHUNT
15
14
SD14
R-0
13
SD13
R-0
12
SD12
R-0
11
SD11
R-0
10
SD10
R-0
9
8
Sign
R-0
SD9
R-0
SD8
R-0
7
6
5
4
3
2
1
0
SD7
R-0
SD6
R-0
SD5
R-0
SD4
R-0
SD3
R-0
SD2
R-0
SD1
R-0
SD0
R-0
表 28. MFR_READ_VSHUNT Field Descriptions
Bit
Field
Type
Default
Description
15
Sign
R
0
This bit determines the sign for the returned value.
0 = Positive
1 = Negative
14:0
SD[14:0]
R
0
These bits set the shunt voltage data.
7.6.3.3 MFR_ALERT_MASK (D2h) [default = XXXXXXXX 11110000]
The bits in this register correspond to the bits in the STATUS_MFR_SPECIFIC register. Setting a bit in this
register blocks the corresponding bit in the STATUS_MFR_SPECIFIC register from having an effect on the
ALERT pin.
图 37. MFR_ALERT_MASK
7
6
5
4
3
2
1
0
Conversion
ready
ADC overflow
detected
POR event
detected
Communication IN_OP_WARNI IN_OC_WARNI IN_OV_WARNI IN_UV_WARNI
s
NG
NG
NG
NG
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
表 29. MFR_ALERT_MASK Field Descriptions
Bit
Field
Type
Default
Description
7
Conversion ready
R/W
1
Masks the conversion ready signal to the ALERT pin (masked by
default).
6
5
4
3
2
1
0
ADC overflow detected
POR event detected
Communications
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
0
0
0
0
Masks the ADC overflow detection
Masks the detection of a power-on-reset event.
Communications or memory fault (or of STATUS_CML)
Input overpower warning mask
IN_OP_WARNING
IN_OC_WARNING
IN_OV_WARNING
IN_UV_WARNING
Input overcurrent warning mask
Input overvoltage warning mask
Input undervoltage warning mask
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7.6.3.4 MFR_CALIBRATION (D4h) [default = 00000000 00000001]
This register provides the device with the value of the shunt resistor that was present to create the measured
differential voltage. This register also sets the resolution of the current register. Programming this register sets
the Current_LSB and the Power_LSB. This register is also suitable for use in overall system calibration. See the
Calibration Register and Scaling section for additional information on programming the calibration register.
The Current_LSB can be used to scale the value in the READ_IOUT register.
图 38. MFR_CALIBRATION
15
—
14
13
12
11
10
9
8
CAL
R/W-0
R/W-0
6
R/W-0
5
R/W-0
4
R/W-0
R/W-0
2
R/W-0
1
R/W-0
0
7
3
CAL
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
表 30. MFR_CALIBRATION Field Descriptions
Bit
Field
—
Type
R/W
R/W
Default
Description
15
14:1
0
0
0
1
Reserved
CAL
Calibration register value
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7.6.3.5 MFR_DEVICE_CONFIG (D5h) [default = 00000010]
This register configures various behaviors of the device in regards to data communications and alerts.
图 39. MFR_DEVICE_CONFIG
7
6
5
4
3
2
1
0
READ_EIN
Autoclear
EIN_STATUS
R/W-0
Reserved
R/W-0
EIN_ACCUM
R/W-0
I2C_FILT
R/W-0
Alert Behavior
R/W-1
APOL
R/W-0
R/W-0
表 31. MFR_DEVICE_CONFIG Field Descriptions
Bit
Field
EIN_STATUS
Type
Default
Description
7
R/W
0
0 = All values added to the EIN accumulator match the setting of
EIN_ACCUM
1 = The EIN accumulator encountered a value inconsistent with
the selected mode of operation. For EIN_ACCUM = 01, a
negative value of the sign bit of READ_IIN is detected. For
EIN_ACCUM = 10, a positive value of the sign bit of READ_IIN is
detected. EIN_STATUS is not set when EIN_ACCUM is 00 or 11.
6
Reserved
R/W
R/W
0
Reserved
5:4
EIN_ACCUM
00
00, 11 = The READ_EIN accumulator sums all values of the
READ_POUT register. Both negative and currents will increase
the accumulator.
01 = The READ_EIN only sums positive values of the
READ_POUT register based on the sign bit of the READ_IIN
register; the sample count continues to increment for negative
values
10 = The READ_EIN only sums negative values of the
READ_POUT register based on the sign bit of the READ_IIN
register; the sample count continues to increment for positive
values
3
2
1
0
I2C_FILT
R/W
R/W
R/W
R/W
0
0
1
0
0 = Normal operation
1 = Disables the I2C input filter
READ_EIN Autoclear
Alert Behavior
APOL
0 = Does not clear the sample count and accumulator
1 = Clears the sample count and accumulator after read
0 = Transparent
1 = Latched
Alert polarity bit.
0 = Normal
1 = Inverted
7.6.3.6 5.1.1 CLEAR_EIN (D6h)
No data are associated with this command.
This register clears the READ_EIN accumulator and counters. One sample of data may be lost.
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7.6.3.7 TI_MFR_ID (E0h) [value = 01010100 01001001]
图 40. TI_MFR_ID
15
14
13
12
11
10
9
8
ID15
R-0
ID14
R-1
ID13
R-0
ID12
R-1
ID11
R-0
ID10
R-1
ID9
R-0
ID8
R-0
7
6
5
4
3
2
1
0
ID7
R-0
ID6
R-1
ID5
R-0
ID4
R-0
ID3
R-0
ID2
R-0
ID1
R-0
ID0
R-1
表 32. TI_MFR_ID Field Descriptions
Bit
Field
ID15
ID14
ID13
ID12
ID11
ID10
ID[9:7]
ID6
Type
R
Value
Description
15
14
13
12
11
10
9:7
6
0
1
0
1
0
1
0
1
0
1
This command returns the same two bytes of data as the Read
MFR_ID command except in an I2C-compatible format of word
read. The value that the device returns is ASCII TI (5449h).
R
R
R
R
R
R
R
5:1
0
ID[5:1]
ID0
R
R
7.6.3.8 TI_MFR_MODEL (E1h) [value = 00110011 00110011]
图 41. TI_MFR_MODEL
15
MD15
R-0
14
MD14
R-0
13
MD13
R-1
12
MD12
R-1
11
MD11
R-0
10
MD10
R-0
9
8
MD9
R-1
MD8
R-1
7
6
5
4
3
2
1
0
MD7
R-0
MD6
R-0
MD5
R-1
MD4
R-1
MD3
R-0
MD2
R-0
MD1
R-1
MD0
R-1
表 33. TI_MFR_MODEL Field Descriptions
Bit
Field
Type
R
Value
Description
15:14
13:12
11:10
9:8
MD[15:14]
MD[13:12]
MD[11:10]
MD[9:8]
0
1
0
1
0
1
0
1
This command returns the two bytes of data coded to represent
the manufacturer model. The value that the device returns is
ASCII 33.
R
R
R
7:6
MD[7:6]
R
5:4
MD[5:4]
R
3:2
MD[3:2]
R
1:0
MD[1:0]
R
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7.6.3.9 TI_MFR_REVISION (E2h) [value = 01000001 00110000]
图 42. TI_MFR_REVISION
15
RV15
R-0
14
RV14
R-1
13
RV13
R-0
12
RV12
R-0
11
RV11
R-0
10
RV10
R-0
9
8
RV9
R-0
RV8
R-1
7
6
5
4
3
2
1
0
RV7
R-0
RV6
R-0
RV5
R-1
RV4
R-1
RV3
R-0
RV2
R-0
RV1
R-0
RV0
R-0
表 34. TI_MFR_REVISION Field Descriptions
Bit
Field
Type
R
Value
Description
15
14
RV[15]
RV[14]
RV[13:9]
RV[8]
0
1
0
1
0
1
0
This command returns the same two bytes of data as the Read
MFR_REVISION command except in an I2C-compatible format
of word read. The value that the device returns is ASCII A0
(4130h).
R
13:9
8
R
R
7:6
5:4
3:0
RV[7:6]
RV[5:4]
RV[3:0]
R
R
R
40
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Validate and test
the design implementation to confirm system functionality.
8.1 Application Information
The INA233 is a current shunt and power monitor with an I2C-, SMBus-, and PMBus-compatible interface. The
device monitors both a shunt voltage drop and bus supply voltage. Programmable calibration value, conversion
times, and averaging (combined with an internal multiplier) enable direct readouts of current in amperes and
power in watts.
8.2 Typical Application
3.3-V Supply
Voltage
CBYPASS
0.1 µF
5 - Bus Supply
Pullup Resistors
INA233
VBUS
VS
SDA
SCL
IN+
IN-
RSHUNT
2 mW
ALERT
A0
10-A
Load
GND
A1
Copyright © 2017, Texas Instruments Incorporated
图 43. Typical High-Side Sensing Circuit Configuration, INA233
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Typical Application (接下页)
8.2.1 Design Requirements
The INA233 measures the voltage developed across a current-sensing resistor (RSHUNT) when current passes
through it. The device also measures the bus supply voltage and can calculate power when the calibration
register is properly configured. The device comes with alert capability where the ALERT pin can be programmed
to respond to a user-defined event or to a conversion ready notification. This design illustrates the ability of the
ALERT pin to respond to a set input overvoltage threshold and how to correctly set the calibration registers and
calculate returned values. 表 35 details the requirements for this design.
表 35. Design Requirements
PARAMETER
DESIGN TARGET
Power-supply voltage, VS
Nominal bus supply voltage, VBUS
VBUS overvoltage warning threshold
Nominal load current
5 V
5 V
5.5 V
10 A
15 A
15 A
2 mΩ
Peak load current
Overcurrent warning threshold
RSHUNT
8.2.2 Detailed Design Procedure
This design example walks through the process of programming the calibration register, calculating the PMBus
coefficients, setting the correct overvoltage and overcurrent warning thresholds, and how to properly scale
returned values from the device. The device alert response time is also examined with 140-µs and 1.1-ms ADC
conversion rates.
8.2.2.1 Programming the Calibration Register
For this example, assuming a peak current of less than 15 A, the Current_LSB is calculated to be 457.7 μA/bit
using 公式 2. Selecting a value for the Current_LSB of 500 μA/bit or 1 mA/bit significantly simplifies the
conversion of the returned value from the READ_IN and READ_PIN commands to amperes and watts. For this
example, a value of 1 mA/bit is chosen for the Current_LSB. Using this value for the Current_LSB does trade a
small amount of resolution for having a simpler conversion process on the user side. Using 公式 1 in this
example with a Current_LSB value of 1 mA/bit and a shunt resistor of 2 mΩ results in a MFR_CALIBRATION
register value of 2560d (or A00h).
8.2.2.2 Calculating PMBus Coefficients
The m, b, and R coefficients are fixed for bus voltage measurements returned by the READ_VIN and
READ_VOUT and are available from 表 1.
For current and power measurements, the value for the m and R coefficients must be calculated. For current
measurements returned by the READ_IIN and READ_IOUT commands, the value for m is calculated by inverting
the Current_LSB used to set the MFR_CALIBRATION register and shifting the decimal location if needed to
minimize rounding errors. In this example, using the Current_LSB of 1 mA/bit, the value of m is calculated to be
1000. Shifting the decimal location does not obtain higher accuracy because the value for m is a whole number.
The value for R in this example is 0 because the decimal location for the value of m does not need shifting.
The POWER_LSB value is 25 times the value of the CURRENT_LSB, therefore, the value for m is reduced by a
factor of 25. For this example, the value for the m power coefficient 1000 / 25 or 40. For this case, the R
coefficient is also 0 because m is a whole number. If m is not a whole number, then shifting the decimal place is
advantageous to reduce rounding errors while keeping the value between –32768 and 32767. Decimal shifts to
the right result in negative values for R and shifts to the left result in positive values; the number of shifts is the
absolute value of R.
The value of 0 can be used for b for both current and power measurements with very little loss in accuracy
because the offset for power and current measurements is very low. The m, b, and R coefficients are fixed for
bus voltage measurements returned by the READ_VIN and READ_VOUT and are available from 表 1.
42
版权 © 2017, Texas Instruments Incorporated
INA233
www.ti.com.cn
ZHCSG76 –APRIL 2017
8.2.2.3 Programming Warning Thresholds
Warning thresholds are set by converting the warning value from volts, amperes, and watts to the appropriate
digital word using 公式 4 with the correct values for m, b, and R. For example, to set a bus voltage overvoltage
warning at 5.5 V with the VIN_OV_WARN_LIMIT command, the correct value to write with this command is
4400d or 1130h. The least significant last three bits of the 16-bit word are hard coded to 0 because the warning
thresholds only have 12 bits of effective resolution. For this example there is no change to what is written in the
VIN_OV_WARN_LIMIT register because the last three bits are already zero. To set an overcurrent warning level
at 15 A with the IIN_OC_WARN_LIMIT command, the correct value to write to the device is 15000d (or 3A98h).
8.2.2.4 Calculating Returned Telemetry Values
When the value for the m, b, and R coefficients are known, returned values can be translated to volts, amperes,
or watts by using 公式 3 with the calculated m, b, and R coefficients. Alternatively, returned values can be
calculated by multiplying the returned code by the corresponding LSB size as discussed in the Calibration
Register and Scaling section.
8.2.3 Application Curves
图 44 shows the ALERT pin response to a bus overvoltage limit of 5.6 V for a conversion time (tCT) of 1.1 ms and
averaging set to 1. 图 45 shows the response for the same limit but with the conversion time reduced to 140 µs.
For the scope shots shown in these figures, persistence was enabled on the ALERT channel. 图 44 and 图 45
show how the ALERT response time can vary depending on when the fault condition occurs relative to the
internal ADC clock of the INA233. For fault conditions that are just exceeding the limit threshold, the response
time for the ALERT pin can vary from one to two conversion cycles. As mentioned previously, the variation is
because of the timing on when the fault event occurs relative to the start time of the internal ADC conversion
cycle. For fault events that greatly exceed the limit threshold, the alert can respond in less than one conversion
cycle because fewer samples are required for the average to exceed the limit threshold value.
280 ms (2 conversions)
2.2 ms (2 conversions)
1.1 ms (1 conversion)
140 ms (1 conversion)
TIME (500 ms /div)
TIME (50 ms /div)
图 45. Alert Response (tCT = 1.1 ms)
图 44. Alert Response (tCT = 140 µs)
版权 © 2017, Texas Instruments Incorporated
43
INA233
ZHCSG76 –APRIL 2017
www.ti.com.cn
9 Power Supply Recommendations
The device input circuitry can accurately measure signals on common-mode voltages beyond the power-supply
voltage, VVS. For example, the voltage applied to the VS power supply pin can be 5 V, whereas the load power-
supply voltage being monitored (the common-mode voltage) can be as high as 36 V. The device can also
withstand the full 0-V to 36-V range at the input pins, regardless of whether the device has power applied or not.
Place the required power-supply bypass capacitors as close as possible to the supply and ground pins of the
device to ensure stability. A typical value for this supply bypass capacitor is 0.1 µF. Applications with noisy or
high-impedance power supplies can require additional decoupling capacitors to reject power-supply noise.
10 Layout
10.1 Layout Guidelines
Connect the input pins (IN+ and IN–) to the sensing resistor using a Kelvin connection or a 4-wire connection.
These connection techniques ensure that only the current-sensing resistor impedance is detected between the
input pins. Poor routing of the current-sensing resistor commonly results in additional resistance present between
the input pins. Given the very low ohmic value of the current-sensing resistor, any additional high-current carrying
impedance causes significant measurement errors. Place the power-supply bypass capacitor as close as
possible to the supply and ground pins.
10.2 Layout Example
A1
IN+
INœ
Sense, Shunt
Resistor
A0
(1)
ALERT
SDA
SCL
VBUS
GND
VS
Alert Output
(Can be left floating if unused)
2
Supply Bypass
Capacitor
I C, SMBus
Interface
Via to Ground Plane
Via to Power Plane
(1) Connect the VBUS pin to the power-supply rail.
图 46. INA233 Layout Example
44
版权 © 2017, Texas Instruments Incorporated
INA233
www.ti.com.cn
ZHCSG76 –APRIL 2017
11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
•
《INA226EVM 评估板和软件教程》
11.2 文档支持
11.2.1 相关文档ꢀ
相关文档请参阅以下部分：
《具有瞬态稳定性的电流分流监控器参考设计》
11.3 接收文档更新通知
如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册
后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
11.4 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2017, Texas Instruments Incorporated
45
PACKAGE OPTION ADDENDUM
www.ti.com
30-Apr-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
INA233AIDGSR
INA233AIDGST
ACTIVE
ACTIVE
VSSOP
VSSOP
DGS
DGS
10
10
2500 RoHS & Green
250 RoHS & Green
NIPDAUAG | SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
233
233
NIPDAUAG | SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Apr-2022
Addendum-Page 2
PACKAGE OUTLINE
DGS0010A
VSSOP - 1.1 mm max height
S
C
A
L
E
3
.
2
0
0
SMALL OUTLINE PACKAGE
C
SEATING PLANE
0.1 C
5.05
4.75
TYP
PIN 1 ID
AREA
A
8X 0.5
10
1
3.1
2.9
NOTE 3
2X
2
5
6
0.27
0.17
10X
3.1
2.9
1.1 MAX
0.1
C A
B
B
NOTE 4
0.23
0.13
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.7
0.4
0 - 8
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
www.ti.com
EXAMPLE BOARD LAYOUT
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
(R0.05)
TYP
SYMM
10X (0.3)
1
5
10
SYMM
6
8X (0.5)
(4.4)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221984/A 05/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
SYMM
(R0.05) TYP
10X (0.3)
8X (0.5)
1
5
10
SYMM
6
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221984/A 05/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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