INA240PMPWPSEP [TI]
采用增强型航天塑料、具有增强的 PWM 抑制能力的 -4V 至 80V、超精密电流感应放大器 | PW | 8 | -55 to 125;
| 型号： | INA240PMPWPSEP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用增强型航天塑料、具有增强的 PWM 抑制能力的 -4V 至 80V、超精密电流感应放大器 | PW | 8 | -55 to 125 放大器 |
| 文件： | 总36页 (文件大小：1921K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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INA240-SEP
ZHCSJ78 –DECEMBER 2018
采用增强型航天塑料的 INA240-SEP 宽共模范围高侧和低侧
双向零漂移电流检测放大器
1 特性
2 应用
1
•
•
VID V62/18615
耐辐射
•
•
•
•
•
支持近地球轨道空间 应用
电源监控
过流和欠流检测
卫星遥测
–
单粒子锁定 (SEL) 在 125°C 下的抗扰度可达
43MeV-cm2/mg
–
–
在高达 30krad(Si) 的条件下无 ELDRS
电机控制环路
每个晶圆批次的 RLAT 总电离剂量 (TID) 高达
3 说明
20krad(Si)
•
增强型航天塑料
INA240-SEP 器件是一款电压输出、电流检测放大器，
具有增强型 PWM 抑制功能，可在独立于电源电压的
–4V 至 80V 宽共模电压范围内检测分流电阻器上的压
降。负共模电压允许器件的工作电压低于接地电压，从
而适应典型螺线管应用 的反激周期。增强型 PWM 抑
制功能可为使用脉宽调制 (PWM) 信号的系统（例如，
电机驱动和螺线管控制系统）中的较大共模瞬变
(ΔV/Δt) 提供高水平的抑制。凭借该功能，可精确测量
电流，而不会使输出电压产生较大的瞬变及相应的恢复
纹波。
–
–
–
–
–
–
–
–
–
–
受控基线
金线
NiPdAu 铅涂层
同一组装和测试场所
同一制造场所
支持军用（-55°C 至 125°C）温度范围
延长的产品生命周期
延长的产品变更通知
产品可追溯性
采用增强型模具化合物实现低释气
该器件可由一个电压为 2.7V 至 5.5V 的单电源供电，
最大电源电流为 2.4mA。固定增益为 20V/V。零漂移
架构的低偏移使得该器件能够在分流器上的最大压降低
至 10mV（满量程）的情况下进行电流检测。
•
•
•
•
增强型 PWM 抑制
出色的 CMRR：132dB（典型值）
宽共模范围：–4V 至 80V
增益：20V/V：
器件信息(1)
–
–
增益误差：0.2%（最大值）
器件型号
封装
封装尺寸（标称值）
增益漂移：2.5ppm/°C（最大值）
INA240PMPWTPSEP
INA240PMPWPSEP
•
•
•
失调电压：±25µV（最大值）
温漂：250nV/°C（最大值）
静态电流：2.4mA（最大值）
TSSOP (8)
3.00mm × 4.40mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
典型应用
增强型 PWM 抑制
270
3.5
3
Y1
240
Supply
(2.7 V to 5.5 V)
2.5
2
210
180
150
150
1.5
1
Common-Mode Step
INA240-SEP OUT
120
90
60
30
0
INœ
0.5
3.50
Y1
OUT
+
IN+
REF2
3
2.5
2
REF1
1.5
-30
Time (2 µs/div)
D004
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS956
INA240-SEP
ZHCSJ78 –DECEMBER 2018
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
8
9
Application and Implementation ........................ 19
8.1 Application Information............................................ 19
8.2 Typical Applications ................................................ 21
8.3 Do's and Don'ts ...................................................... 24
Power Supply Recommendations...................... 24
9.1 Power Supply Decoupling....................................... 24
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 6
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 13
10 Layout................................................................... 25
10.1 Layout Guidelines ................................................. 25
10.2 Layout Example .................................................... 25
11 器件和文档支持 ..................................................... 26
11.1 接收文档更新通知 ................................................. 26
11.2 社区资源................................................................ 26
11.3 商标....................................................................... 26
11.4 静电放电警告......................................................... 26
11.5 术语表 ................................................................... 26
12 机械、封装和可订购信息....................................... 27
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
日期
修订版本
说明
2018 年 12 月
*
初始发行版。
2
Copyright © 2018, Texas Instruments Incorporated
INA240-SEP
www.ti.com.cn
ZHCSJ78 –DECEMBER 2018
5 Pin Configuration and Functions
INA240-SEP PW Package
8-Pin TSSOP
Top View
NC- no internal connection
Pin Functions
PIN
I/O
DESCRIPTION
NAME
PW (TSSOP)
GND
4
Analog
Ground.
Analog
input
IN–
3
Connect to load side of shunt resistor.
Analog
input
IN+
NC
2
1
8
Connect to supply side of shunt resistor.
Reserved. Connect to ground.
Output voltage.
—
Analog
output
OUT
Analog
input
Reference 1 voltage. Connect to 0 V to VS; see the Adjusting the Output Midpoint With
the Reference Pins section for connection options.
REF1
7
Analog
input
Reference 2 voltage. Connect to 0 V to VS; see the Adjusting the Output Midpoint With
the Reference Pins section for connection options.
REF2
VS
6
5
—
Power supply, 2.7 V to 5.5 V.
Copyright © 2018, Texas Instruments Incorporated
3
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ZHCSJ78 –DECEMBER 2018
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
6
UNIT
Supply voltage
V
Differential (VIN+) – (VIN–
)
–80
–6
80
(2)
Analog inputs, VIN+, VIN–
V
Common-mode
90
REF1, REF2, NC inputs
Output
GND – 0.3
GND – 0.3
–55
VS + 0.3
VS + 0.3
150
V
V
Operating free-air temperature, TA
Junction temperature, TJ
°C
°C
°C
150
Storage temperature, Tstg
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) VIN+ and VIN– are the voltages at the IN+ and IN– pins, respectively.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
–4
NOM
MAX
80
UNIT
VCM
VS
Common-mode input voltage
Operating supply voltage
V
V
2.7
–55
5.5
TA
Operating free-air temperature
125
°C
6.4 Thermal Information
INA240-SEP
THERMAL METRIC(1)
PW (TSSOP)
8 PINS
149.1
33.2
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
78.4
Junction-to-top characterization parameter
Junction-to-board characterization parameter
1.5
ψJB
76.4
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2018, Texas Instruments Incorporated
INA240-SEP
www.ti.com.cn
ZHCSJ78 –DECEMBER 2018
6.5 Electrical Characteristics
at TA = –55°C to 125°C, VS = 5 V, VSENSE = VIN+ – VIN–, VCM = 12 V, and VREF1 = VREF2 = VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
INPUT
VIN+ = –4 V to 80 V, VSENSE = 0 mV
TA = –55°C to 125°C
VCM
Common-mode input range
Common-mode rejection ratio
–4
80
V
VIN+ = –4 V to 80 V, VSENSE = 0 mV
TA = –55°C to 125°C
120
132
CMRR
dB
µV
f = 50 kHz
93
±5
VOS
Offset voltage, input-referred
Offset voltage drift
VSENSE = 0 mV
±25
dVOS/dT
VSENSE = 0 mV, TA = –55°C to 125°C
±50
±250 nV/°C
VS = 2.7 V to 5.5 V, VSENSE = 0 mV
TA = –55°C to 125°C
PSRR
IB
Power-supply rejection ratio
±1
90
±10
VS
µV/V
Input bias current
IB+, IB–, VSENSE = 0 mV
µA
V
Reference input range
0
OUTPUT
G
Gain
20
±0.05%
±0.5
V/V
GND + 50 mV ≤ VOUT ≤ VS – 200 mV
TA = –55°C to 125°C
±0.20%
Gain error
±2.5 ppm/°C
0.1%
Nonlinearity error
GND + 10 mV ≤ VOUT ≤ VS – 200 mV
±0.01%
VOUT = | (VREF1 – VREF2) | / 2 at VSENSE
0 mV, TA = –55°C to 125°C
=
Reference divider accuracy
0.02%
Reference voltage rejection ratio
(input-referred)
RVRR
20
1
µV/V
nF
Maximum capacitive load
No sustained oscillation
VOLTAGE OUTPUT(1)
RL = 10 kΩ to GND
TA = –55°C to 125°C
Swing to VS power-supply rail
VS – 0.05
VGND + 1
VS – 0.2
V
RL = 10 kΩ to GND, VSENSE = 0 mV
VREF1 = VREF2 = 0 V
TA = –55°C to 125°C
Swing to GND
VGND + 10
mV
FREQUENCY RESPONSE
All gains, –3-dB bandwidth
All gains, 2% THD+N(2)
400
100
BW
Bandwidth
kHz
Settling time - output settles to 0.5% of
final value
9.6
2
µs
SR
Slew rate
V/µs
NOISE (INPUT REFERRED)
Voltage noise density
POWER SUPPLY
40
nV/√Hz
VS
Operating voltage range
TA = –55°C to 125°C
VSENSE = 0 mV
2.7
5.5
2.4
V
1.8
IQ
Quiescent current
mA
IQ vs temperature,
TA = –55°C to 125°C
2.6
TEMPERATURE RANGE
Specified range
–55
125
°C
(1) See Figure 10.
(2) See the Input Signal Bandwidth section for more details.
Copyright © 2018, Texas Instruments Incorporated
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ZHCSJ78 –DECEMBER 2018
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6.6 Typical Characteristics
at TA = –55°C to 125°C, VS = 5 V, VCM = 12 V, and VREF = VS / 2 (unless otherwise noted)
50
40
30
20
10
0
-10
-20
-30
-40
-50
-55
-35
-15
5
25
45
65
85
105 125
Temperature (èC)
D022
D001
VOS (mV)
Figure 1. Input Offset Voltage Production Distribution
Figure 2. Offset Voltage vs Temperature
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-55
-35
-15
5
25
45
65
85
105 125
Temperature (èC)
D004
D003
CMR (mV/V)
Figure 4. Common-Mode Rejection Ratio vs Temperature
Figure 3. Common-Mode Rejection Production Distribution
100
75
50
25
0
-25
-50
-75
-100
-55
-35
-15
5
25
45
65
85
105 125
Temperature (èC)
D600
D501
Gain Error (%)
Figure 6. Gain Error vs Temperature
Figure 5. Gain Error Production Distribution
6
Copyright © 2018, Texas Instruments Incorporated
INA240-SEP
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ZHCSJ78 –DECEMBER 2018
Typical Characteristics (continued)
at TA = –55°C to 125°C, VS = 5 V, VCM = 12 V, and VREF = VS / 2 (unless otherwise noted)
140
120
100
80
60
50
40
30
20
10
0
60
40
-10
1
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
D007
VCM = 0 V
VDIF = 10-mVPP sine
Figure 8. Power-Supply Rejection Ratio vs Frequency
Figure 7. Gain vs Frequency
150
VS
25èC
125èC
-55èC
135
120
105
90
VS - 1
VS - 2
GND + 3
GND + 2
GND + 1
GND
75
60
1
10
100
1k
10k
100k
1M
0
1
2
3
4
5
6
7
Frequency (Hz)
Output Current (mA)
D010
Figure 9. Common-Mode Rejection Ratio vs Frequency
240
Figure 10. Output Voltage Swing vs Output Current
200
160
120
80
200
160
120
80
40
40
0
0
-40
-40
-10
0
10
20
30
40
50
60
70
80
90
-10
0
10
20
30
40
50
60
70
80
90
Common-Mode Voltage (V)
Common-Mode Voltage (V)
D011
D012
VS = 5 V
VS = 0 V
Figure 11. Input Bias Current vs Common-Mode Voltage
Figure 12. Input Bias Current vs Common-Mode Voltage
Copyright © 2018, Texas Instruments Incorporated
7
INA240-SEP
ZHCSJ78 –DECEMBER 2018
www.ti.com.cn
Typical Characteristics (continued)
at TA = –55°C to 125°C, VS = 5 V, VCM = 12 V, and VREF = VS / 2 (unless otherwise noted)
100
95
90
85
80
75
70
65
60
55
50
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
VS = 5 V
VS = 3.3 V
VS = 2.7 V
-55
-35
-15
5
25
45
65
85
105 125
-55
-35
-15
5
25
45
65
85
105 125
Temperature (èC)
Temperature (èC)
D013
D014
Figure 13. Input Bias Current vs Temperature
Figure 14. Quiescent Current vs Temperature
100
10
Time (1 s/div)
1
10
100
1k
10k
100k
1M
Frequency (Hz)
D016
VS = ±2.5 V
VCM = 0 V
VDIF = 0 V
VREF1 = VREF2 = 0 V
Input referred
Figure 15. Input-Referred Voltage Noise vs Frequency
Figure 16. 0.1-Hz to 10-Hz Voltage Noise
240
3.5
3
2-VPP Output Signal
Y1
240
210
2.5
2
180
150
120
90
60
30
0
1.5
3.5
10-mVPP Input Signal
Y1
3
2.5
2
1.5
1
Common-Mode Input Signal
INA240-SEP Output
1
-30
Time (10 ms/div)
Time (0.25 ms/div)
VREF1 = VREF2 = 0 V
10-mVPP input step
D021
Rising edge
Figure 17. Step Response
Figure 18. Common-Mode Voltage Transient Response
8
Copyright © 2018, Texas Instruments Incorporated
INA240-SEP
www.ti.com.cn
ZHCSJ78 –DECEMBER 2018
Typical Characteristics (continued)
at TA = –55°C to 125°C, VS = 5 V, VCM = 12 V, and VREF = VS / 2 (unless otherwise noted)
240
3.5
3
Y1
240
210
2.5
2
0
180
150
120
90
60
30
0
1.5
Common-Mode Input Signal
INA240-SEP Output
3.5
Y1
3
2.5
2
0
1.5
1
1
-30
Time (2 ms/div)
Time (0.25 ms/div)
D019
D022
VREF1 = VREF2 = 0 V
Falling edge
Figure 19. Common-Mode Voltage Transient Response
Figure 20. Start-Up Response
Copyright © 2018, Texas Instruments Incorporated
9
INA240-SEP
ZHCSJ78 –DECEMBER 2018
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7 Detailed Description
7.1 Overview
The INA240-SEP is a current-sense amplifier that offers a wide common-mode range, precision, zero-drift
topology, excellent common-mode rejection ratio (CMRR), and features enhanced pulse width modulation (PWM)
rejection. Enhanced PWM rejection reduces the effect of common-mode transients on the output signal that are
associated with PWM signals.
7.2 Functional Block Diagram
VS
INœ
œ
PWM
OUT
Rejection
IN+
+
50 kꢀ
50 kꢀ
REF2
REF1
GND
7.3 Feature Description
7.3.1 Amplifier Input Signal
The INA240-SEP is designed to handle large common-mode transients over a wide voltage range. Input signals
from current measurement applications for linear and PWM applications can be connected to the amplifier to
provide a highly accurate output, with minimal common-mode transient artifacts.
7.3.1.1 Enhanced PWM Rejection Operation
The enhanced PWM rejection feature of the INA240-SEP provides increased attenuation of large common-mode
ΔV/Δt transients. Large ΔV/Δt common-mode transients associated with PWM signals are employed in
applications such as motor or solenoid drive and switching power supplies. Traditionally, large ΔV/Δt common-
mode transitions are handled strictly by increasing the amplifier signal bandwidth, which can increase chip size,
complexity and ultimately cost. The INA240-SEP is designed with high common-mode rejection techniques to
reduce large ΔV/Δt transients before the system is disturbed as a result of these large signals. The high AC
CMRR, in conjunction with signal bandwidth, allows the INA240-SEP to provide minimal output transients and
ringing compared with standard circuit approaches.
7.3.1.2 Input Signal Bandwidth
The INA240-SEP input signal, which represents the current being measured, is accurately measured with
minimal disturbance from large ΔV/Δt common-mode transients as previously described. For PWM signals
typically associated with motors, solenoids, and other switching applications, the current being monitored varies
at a significantly slower rate than the faster PWM frequency.
The INA240-SEP bandwidth is defined by the –3-dB bandwidth of the current-sense amplifier inside the device;
see the Electrical Characteristics table. The device bandwidth provides fast throughput and fast response
required for the rapid detection and processing of overcurrent events. Without the higher bandwidth, protection
circuitry may not have adequate response time and damage may occur to the monitored application or circuit.
10
Copyright © 2018, Texas Instruments Incorporated
INA240-SEP
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ZHCSJ78 –DECEMBER 2018
Feature Description (continued)
Figure 21 shows the performance profile of the device over frequency. Harmonic distortion increases at the
upper end of the amplifier bandwidth with no adverse change in detection of overcurrent events. However,
increased distortion at the highest frequencies must be considered when the measured current bandwidth begins
to approach the INA240-SEP bandwidth.
For applications requiring distortion sensitive signals, Figure 21 provides information to show that there is an
optimal frequency performance range for the amplifier. The full amplifier bandwidth is always available for fast
overcurrent events at the same time that the lower frequency signals are amplified at a low distortion level. The
output signal accuracy is reduced for frequencies closer to the maximum bandwidth. Individual requirements
determine the acceptable limits of distortion for high-frequency, current-sensing applications. Testing and
evaluation in the end application or circuit is required to determine the acceptance criteria and to validate the
performance levels meet the system specifications.
10%
1%
0.1%
90% FS Input
100k 1M
0.01%
1
10
100
1k
10k
Frequency (Hz)
D006
Figure 21. Performance Over Frequency
7.3.2 Selecting the Sense Resistor (RSENSE
)
The INA240-SEP determines the current magnitude from measuring the differential voltage developed across a
resistor. This resistor is referred to as a current-sensing resistor or a current-shunt resistor. The flexible design of
the device allows a wide input signal range across this current-sensing resistor.
The current-sensing resistor is ideally chosen solely based on the full-scale current to be measured, the full-scale
input range of the circuitry following the device. The minimum current-sensing resistor is a design-based decision
in order to maximize the input range of the signal chain circuitry. Full-scale output signals that are not maximized
to the full input range of the system circuitry limit the ability of the system to exercise the full dynamic range of
system control.
Two important factors to consider when finalizing the current-sensing resistor value are: the required current
measurement accuracy and the maximum power dissipation across the resistor. A larger resistor voltage
provides for a more accurate measurement, but increases the power dissipation in the resistor. The increased
power dissipation generates heat, which reduces the sense resistor accuracy because of the temperature
coefficient. The voltage signal measurement uncertainty is reduced when the input signal gets larger because
any fixed errors become a smaller percentage of the measured signal. The design trade-off to improve
measurement accuracy increases the current-sensing resistor value. The increased resistance value results in an
increased power dissipation in the system which can additionally decrease the overall system accuracy. Based
on these relationships, the measurement accuracy is inversely proportional to both the resistance value and
power dissipation contributed by the current-shunt selection.
Table 1 shows an example of the different results obtained from using two different gain versions of the INA240-
SEP. From the table data, the higher gain device allows a smaller current-shunt resistor and decreased power
dissipation in the element. The Calculating Total Error section provides information on the error calculations that
must be considered in addition to the gain and current-shunt value when designing with the INA240-SEP.
Copyright © 2018, Texas Instruments Incorporated
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ZHCSJ78 –DECEMBER 2018
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Feature Description (continued)
Table 1. RSENSE Selection and Power Dissipation(1)
PARAMETER
EQUATION
—
RESULTS
Gain
20 V/V
150 mV
15 mΩ
1.5 W
VDIFF
Ideal maximum differential input voltage
Current-sense resistor value
Current-sense resistor power dissipation
VDIFF = VOUT / Gain
RSENSE = VDIFF / IMAX
RSENSE
PRSENSE
2
RSENSE × IMAX
(1) Full-scale current = 10 A, and full-scale output voltage = 3 V.
12
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INA240-SEP
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ZHCSJ78 –DECEMBER 2018
7.4 Device Functional Modes
7.4.1 Adjusting the Output Midpoint With the Reference Pins
Figure 22 shows a test circuit for reference-divider accuracy. The INA240-SEP output is configurable to allow for
unidirectional or bidirectional operation.
VS
VS
INœ
œ
OUT
+
IN+
REF2
REF1
GND
Figure 22. Test Circuit For Reference Divider Accuracy
NOTE
Do not connect the REF1 pin or the REF2 pin to any voltage source lower than GND or
higher than VS.
The output voltage is set by applying a voltage or voltages to the reference voltage inputs, REF1 and REF2. The
reference inputs are connected to an internal gain network. There is no operational difference between the two
reference pins.
7.4.2 Reference Pin Connections for Unidirectional Current Measurements
Unidirectional operation allows current measurements through a resistive shunt in one direction. For
unidirectional operation, connect the device reference pins together and then to the negative rail (see the Ground
Referenced Output section) or the positive rail (see the VS Referenced Output section). The required differential
input polarity depends on the output voltage setting. The amplifier output moves away from the referenced rail
proportional to the current passing through the external shunt resistor. If the amplifier reference pins are
connected to the positive rail, then the input polarity must be negative to move the amplifier output down
(towards ground). If the amplifier reference pins are connected at ground, then the input polarity must be positive
to move the amplifier output up (towards supply).
The following sections describe how to configure the output for unidirectional operation cases.
7.4.2.1 Ground Referenced Output
When using the INA240-SEP in a unidirectional mode with a ground referenced output, both reference inputs are
connected to ground; this configuration takes the output to ground when there is a 0-V differential at the input (as
Figure 23 shows).
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13
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Device Functional Modes (continued)
VS
VS
INœ
œ
OUT
REF2
REF1
+
IN+
GND
Figure 23. Ground Referenced Output
7.4.2.2 VS Referenced Output
Unidirectional mode with a VS referenced output is configured by connecting both reference pins to the positive
supply. Use this configuration for circuits that require power-up and stabilization of the amplifier output signal and
other control circuitry before power is applied to the load (as shown in Figure 24).
VS
VS
INœ
œ
OUT
+
REF2
REF1
IN+
GND
Figure 24. VS Referenced Output
7.4.3 Reference Pin Connections for Bidirectional Current Measurements
Bidirectional operation allows the INA240-SEP to measure currents through a resistive shunt in two directions.
For this operation case, the output voltage can be set anywhere within the reference input limits. A common
configuration is to set the reference inputs at half-scale for equal range in both directions. However, the reference
inputs can be set to a voltage other than half-scale when the bidirectional current is non-symmetrical.
7.4.3.1 Output Set to External Reference Voltage
Connecting both pins together and then to a reference voltage results in an output voltage equal to the reference
voltage for the condition of shorted input pins or a 0-V differential input; this configuration is shown in Figure 25.
The output voltage decreases below the reference voltage when the IN+ pin is negative relative to the IN– pin
and increases when the IN+ pin is positive relative to the IN– pin. This technique is the most accurate way to
bias the output to a precise voltage.
14
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ZHCSJ78 –DECEMBER 2018
Device Functional Modes (continued)
VS
VS
INœ
œ
OUT
REF2
REF1
+
IN+
2.5-V
Reference
GND
Figure 25. External Reference Output
7.4.3.2 Output Set to Midsupply Voltage
By connecting one reference pin to VS and the other to the GND pin, the output is set at half of the supply when
there is no differential input, as shown in Figure 26. This method creates a ratiometric offset to the supply
voltage, where the output voltage remains at VS / 2 for 0 V applied to the inputs.
VS
VS
INœ
œ
OUT
Output
+
IN+
REF2
REF1
GND
Figure 26. Midsupply Voltage Output
Copyright © 2018, Texas Instruments Incorporated
15
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Device Functional Modes (continued)
7.4.3.3 Output Set to Mid-External Reference
In this case, an external reference is divided by two by connecting one REF pin to ground and the other REF pin
to the reference, as shown in Figure 27.
VS
VS
INœ
œ
OUT
+
IN+
REF2
REF1
2.5-V
Reference
GND
Figure 27. Mid-External Reference Output
7.4.3.4 Output Set Using Resistor Divider
The INA240-SEP REF1 and REF2 pins allow for the midpoint of the output voltage to be adjusted for system
circuitry connections to analog to digital converters (ADCs) or other amplifiers. The REF pins are designed to be
connected directly to supply, ground, or a low-impedance reference voltage. The REF pins can be connected
together and biased using a resistor divider to achieve a custom output voltage. If the amplifier is used in this
configuration, as shown in Figure 28, use the output as a differential signal with respect to the resistor divider
voltage. Use of the amplifier output as a single-ended signal in this configuration is not recommended because
the internal impedance shifts can adversely affect device performance specifications.
VS
VS
R1
INœ
œ
OUT
TO ADC+
TO ADCœ
+
IN+
REF2
REF1
R2
GND
Figure 28. Setting the Reference Using a Resistor Divider
7.4.4 Calculating Total Error
The INA240-SEP electrical specifications (see the Electrical Characteristics table) include typical individual errors
terms (such as gain error, offset error, and nonlinearity error). Total error, including all of these individual error
components, is not specified in the Electrical Characteristics table. In order to accurately calculate the expected
error of the device, the device operating conditions must first be known. Some current-shunt monitors specify a
total error in the product data sheet. However, this total error term is accurate under only one particular set of
operating conditions. Specifying the total error at this point has limited value because any deviation from these
specific operating conditions no longer yields the same total error value. This section discusses the individual
error sources and how the device total error value can be calculated from the combination of these errors for
specific conditions.
16
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Device Functional Modes (continued)
Two examples are provided in Table 2 and Table 3 that detail how different operating conditions can affect the
total error calculations. Typical and maximum calculations are shown as well to provide the user more
information on how much error variance is present from device to device.
7.4.4.1 Error Sources
The typical error sources that have the largest effect on the total error of the device are gain error, nonlinearity,
common-mode rejection ratio, and input offset voltage error. For the INA240-SEP, an additional error source
(referred to as the reference voltage rejection ratio) is also included in the total error value.
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Device Functional Modes (continued)
7.4.4.2 Reference Voltage Rejection Ratio Error
Reference voltage rejection ratio refers to the amount of error induced by applying a reference voltage to the
INA240-SEP that deviates from the mid-point of the device supply voltage.
7.4.4.2.1 Total Error Example 1
Table 2. Total Error Calculation: Example 1(1)
TERM
SYMBOL
EQUATION
TYPICAL VALUE
Initial input offset voltage
VOS
—
5 µV
1
CMRR_dB
Added input offset voltage
because of common-
mode voltage
´ (VCM - 12V)
(
VOS_CM
0 µV
(
20
10
Added input offset voltage
because of reference
voltage
VOS_REF
VOS_Total
Error_VOS
RVRR × |VS / 2 – VREF
|
0 µV
5 µV
(VOS)2 + (VOS_CM)2 + (VOS_REF
)
2
Total input offset voltage
VOS_Total
Error from input offset
voltage
0.05%
´ 100
VSENSE
Gain error
Error_Gain
Error_Lin
—
—
0.05%
0.01%
Nonlinearity error
(Error_VOS)2 + (Error_Gain)2 + (Error_Lin)2
Total error
—
0.07%
(1) The data for Table 2 was taken with the INA240-SEP, VS = 5 V, VCM = 12 V, VREF1 = VREF2 = VS / 2, and VSENSE = 10 mV.
7.4.4.2.2 Total Error Example 2
Table 3. Total Error Calculation: Example 2(1)
TERM
SYMBOL
EQUATION
TYPICAL VALUE
Initial input offset voltage
VOS
—
5 µV
1
CMRR_dB
Added input offset voltage
because of common-
mode voltage
´ (VCM - 12V)
(
VOS_CM
12.1 µV
(
20
10
Added input offset voltage
because of reference
voltage
VOS_REF
VOS_Total
Error_VOS
RVRR × |VS / 2 – VREF
|
5 µV
14 µV
0.14%
(VOS)2 + (VOS_CM)2 + (VOS_REF
)
2
Total input offset voltage
VOS_Total
Error from input offset
voltage
´ 100
VSENSE
Gain error
Error_Gain
Error_Lin
—
—
0.05%
0.01%
Nonlinearity error
(Error_VOS)2 + (Error_Gain)2 + (Error_Lin)2
Total error
—
0.15%
(1) The data for Table 3 was taken with the INA240-SEP, VS = 5 V, VCM = 60 V, VREF1 = VREF2 = 0 V, and VSENSE = 10 mV.
18
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The INA240-SEP measures the voltage developed as current flows across the current-sensing resistor. The
device provides reference pins to configure operation as either unidirectional or bidirectional output swing. When
using the INA240-SEP for inline motor current sense, the device is commonly configured for bidirectional
operation.
8.1.1 Input Filtering
NOTE
Input filters are not required for accurate measurements using the INA240-SEP, and use
of filters in this location is not recommended. If filter components are used on the input of
the amplifier, follow the guidelines in this section to minimize the effects on performance.
Based strictly on user design requirements, external filtering of the current signal may be desired. The initial
location that can be considered for the filter is at the output of the current amplifier. Although placing the filter at
the output satisfies the filtering requirements, this location changes the low output impedance measured by any
circuitry connected to the output voltage pin. The other location for filter placement is at the current amplifier
input pins. This location satisfies the filtering requirement also, however the components must be carefully
selected to minimally impact device performance. Figure 29 shows a filter placed at the inputs pins.
VS
INœ
RS
t
Bias
OUT
R
+
RS
REF2
REF1
IN+
GND
Figure 29. Filter at Input Pins
External series resistance provide a source of additional measurement error, so keep the value of these series
resistors to 10 Ω or less to reduce loss of accuracy. The internal bias network shown in Figure 29 creates a
mismatch in input bias currents (see Figure 30) when a differential voltage is applied between the input pins. If
additional external series filter resistors are added to the circuit, a mismatch is created in the voltage drop across
the filter resistors. This voltage is a differential error voltage in the shunt resistor voltage. In addition to the
absolute resistor value, mismatch resulting from resistor tolerance can significantly impact the error because this
value is calculated based on the actual measured resistance.
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Application Information (continued)
250
200
150
100
50
IB+
IB-
0
-50
-100
0
0.2
0.4
0.6
0.8
1
Differential Input Voltage (V)
Figure 30. Input Bias Current vs Differential Input Voltage
The measurement error expected from the additional external filter resistors can be calculated using Equation 1,
where the gain error factor is calculated using Equation 2.
Gain Error (%) = 100 - (100 ´ Gain Error Factor)
(1)
The gain error factor, shown in Equation 1, can be calculated to determine the gain error introduced by the
additional external series resistance. Equation 1 calculates the deviation of the shunt voltage resulting from the
attenuation and imbalance created by the added external filter resistance. Table 4 provides the gain error factor
and gain error for several resistor values.
3000
Gain Error Factor =
RS + 3000
Where:
•
RS is the external filter resistance value
(2)
Table 4. Gain Error Factor and Gain Error For External Input Resistors
EXTERNAL RESISTANCE (Ω)
GAIN ERROR FACTOR
GAIN ERROR (%)
5
0.998
0.997
0.968
0.17
0.33
3.23
10
100
20
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INA240-SEP
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ZHCSJ78 –DECEMBER 2018
8.2 Typical Applications
The INA240-SEP offers advantages for multiple applications including the following:
•
•
•
High common-mode range and excellent CMRR enables direct inline sensing
Ultra-low offset and drift eliminates the necessity of calibration
Wide supply range enables a direct interface with most microprocessors
Two specific applications are provided and include more detailed information.
8.2.1 Inline Motor Current-Sense Application
5 V
VS
40 V
IN+
OUT
INA240-SEP
GND
REF2
REF1
INœ
100 mΩ
Figure 31. Inline Motor Application Circuit
8.2.1.1 Design Requirements
Inline current sensing has many advantages in motor control, from torque ripple reduction to real-time motor
health monitoring. However, the full-scale PWM voltage requirements for inline current measurements provide
challenges to accurately measure the current. Switching frequencies in the 50-kHz to 100-kHz range create
higher ΔV/Δt signal transitions that must be addressed to obtain accurate inline current measurements.
With a superior common-mode rejection capability, high precision, and a high common-mode specification, the
INA240-SEP provides performance for a wide range of common-mode voltages.
8.2.1.2 Detailed Design Procedure
For this application, the INA240-SEP measures current in the drive circuitry of a 36-V, 4000-RPM motor.
To demonstrate the performance of the device, the INA240-SEP with a gain of 20 V/V was selected for this
design and powered from a 5-V supply.
Using the information in the Adjusting the Output Midpoint With the Reference Pins section, the reference point is
set to midscale by splitting the supply with REF1 connected to ground and REF2 connected to supply. This
configuration allows for bipolar current measurements. Alternatively, the reference pins can be tied together and
driven with an external precision reference.
The current-sensing resistor is sized so that the output of the INA240-SEP is not saturated. A value of 100-mΩ
was selected to maintain the analog input within the device limits.
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Typical Applications (continued)
8.2.1.3 Application Curve
120
90
3.5
3
2.5
2
1.5
Input Signal
INA240-SEP Output
1
60
30
0
-30
Time (25 µs/div)
C005
Figure 32. Inline Motor Current-Sense Input and Output Signals
22
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Typical Applications (continued)
8.2.2 Solenoid Drive Current-Sense Application
12 V
5 V
VS
Control
IN+
OUT
10 mꢀ
INA240-SEP
GND
REF2
REF1
INœ
Figure 33. Solenoid Drive Application Circuit
8.2.2.1 Design Requirements
Challenges exist in solenoid drive current sensing that are similar to those in motor inline current sensing. In
certain topologies, the current-sensing amplifier is exposed to the full-scale PWM voltage between ground and
supply. The INA240-SEP is well suited for this type of application.
8.2.2.2 Detailed Design Procedure
For this application, the INA240-SEP measures current in the driver circuit of a 24-V, 500-mA water valve.
Using the information in the Adjusting the Output Midpoint With the Reference Pins section, the reference point is
set to midscale by splitting the supply with REF1 connected to ground and REF2 connected to supply.
Alternatively, the reference pins can be tied together and driven with an external precision reference.
A value of 10 mΩ was selected to maintain the analog input within the device limits.
8.2.2.3 Application Curve
66
6
2
Y
5
2
2
4
1
1
3
1
42
2
36
30
24
18
12
6
1
Common-Mode Input Signal
INA240-SEP Output
0
-1
-2
3.50
3.50
Y1
3
2.5
2
1.5
0
-6
Time (20 ms/div)
D020
Figure 34. Solenoid Drive Current Sense Input and Output Signals
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ZHCSJ78 –DECEMBER 2018
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8.3 Do's and Don'ts
8.3.1 High-Precision Applications
For high-precision applications, verify accuracy and stability of the amplifier by:
•
•
•
Providing a precision reference connected to REF1 and REF2
Optimizing the layout of the power and sensing path of the sense resistor (see the Layout section)
Providing adequate bypass capacitance on the supply pin (see the Power Supply Decoupling section)
8.3.2 Kelvin Connection from the Current-Sense Resistor
To provide accurate current measurements, verify the routing between the current-sense resistor and the
amplifier uses a Kelvin connection. Use the information provided in Figure 35 and the Connection to the Current-
Sense Resistor section during device layout.
RSHUNT
RSHUNT
INA240-SEP
INA240-SEP
DO
DON‘T
Kelvin Connection from Shunt Resistor
Non-Kelvin Connection from Shunt Resistor
Figure 35. Shunt Connections to the INA240-SEP
9 Power Supply Recommendations
The INA240-SEP makes accurate measurements beyond the connected power-supply voltage (VS) because the
inputs (IN+ and IN–) operate anywhere between –4 V and 80 V independent of VS. For example, the VS power
supply equals 5 V and the common-mode voltage of the measured shunt can be as high as 80 V.
Although the common-mode voltage of the input can be beyond the supply voltage, the output voltage range of
the INA240-SEP series is constrained to the supply voltage.
9.1 Power Supply Decoupling
Place the power-supply bypass capacitor as close as possible to the supply and ground pins. TI recommends a
bypass capacitor value of 0.1 μF. Additional decoupling capacitance can be added to compensate for noisy or
high-impedance power supplies.
24
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INA240-SEP
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ZHCSJ78 –DECEMBER 2018
10 Layout
10.1 Layout Guidelines
10.1.1 Connection to the Current-Sense Resistor
Poor routing of the current-sensing resistor can result in additional resistance between the input pins of the
amplifier. Any additional high-current carrying impedance can cause significant measurement errors because the
current resistor has a very-low-ohmic value. Use a Kelvin or 4-wire connection to connect to the device input
pins. This connection technique ensures that only the current-sensing resistor impedance is detected between
the input pins.
10.2 Layout Example
RSHUNT
Power
Supply
Load
VIA to
Ground
Plane
VIA to
Ground
Plane
GND
INœ
IN+
NC
CBYPASS
INA240-SEP
OUT
VS
REF2 REF1
Output Voltage
VIA to
Ground
Plane
Supply
Voltage
Figure 36. Recommended TSSOP Package Layout
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25
INA240-SEP
ZHCSJ78 –DECEMBER 2018
www.ti.com.cn
11 器件和文档支持
11.1 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.2 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.3 商标
E2E is a trademark of Texas Instruments.
11.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.5 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
26
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ZHCSJ78 –DECEMBER 2018
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2018, Texas Instruments Incorporated
27
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
INA240PMPWPSEP
INA240PMPWTPSEP
V62/18615-01XE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
8
8
8
8
150
250
250
150
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-55 to 125
-55 to 125
-55 to 125
-55 to 125
240SEP
NIPDAU
NIPDAU
NIPDAU
240SEP
240SEP
240SEP
V62/18615-01XE-T
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF INA240-SEP :
Automotive : INA240-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
INA240PMPWTPSEP
TSSOP
PW
8
250
180.0
12.4
7.0
3.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP PW
SPQ
Length (mm) Width (mm) Height (mm)
210.0 185.0 35.0
INA240PMPWTPSEP
8
250
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
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5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
INA240PMPWPSEP
V62/18615-01XE-T
PW
PW
TSSOP
TSSOP
8
8
150
150
530
530
10.2
10.2
3600
3600
3.5
3.5
Pack Materials-Page 3
PACKAGE OUTLINE
PW0008A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
8
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
SEATING PLANE
TYP
PIN 1 ID
AREA
A
0.1 C
6X 0.65
8
5
1
3.1
2.9
NOTE 3
2X
1.95
4
0.30
0.19
8X
4.5
4.3
1.2 MAX
B
0.1
C A
B
NOTE 4
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
0 - 8
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
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EXAMPLE BOARD LAYOUT
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM
8X (0.45)
(R0.05)
1
4
TYP
8
SYMM
6X (0.65)
5
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221848/A 02/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM
(R0.05) TYP
8X (0.45)
1
4
8
SYMM
6X (0.65)
5
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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