INA3221-Q1 [TI]
具有警报功能的 AEC-Q100、26V、三通道、13 位、I2C 输出电流/电压监控器;
| 型号： | INA3221-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有警报功能的 AEC-Q100、26V、三通道、13 位、I2C 输出电流/电压监控器 监控 |
| 文件： | 总49页 (文件大小：2395K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INA3221-Q1
ZHCSEU5C –MARCH 2016 –REVISED MARCH 2021
INA3221-Q1 带警报功能、符合AEC-Q100 标准的26V、三通道、13 位、I2C 输
出电流和电压监控器
1 特性
3 说明
• 符合汽车应用要求
• 具有符合AEC-Q100 标准的下列特性：
– 器件温度等级1：-40°C 至125°C
• 提供功能安全
INA3221-Q1 是一款三通道、高侧电流和总线电压监视
器，具有一个兼容 I2C 和 SMBUS 的接口。INA3221-
Q1 不仅能够监视分流压降和总线电源电压，还针对这
些信号提供有可编程的转换时间和平均值计算模式。
INA3221-Q1 提供关键报警和警告报警，用于检测每条
通道上可编程的多种超范围情况。
– 可帮助进行功能安全系统设计的文档
• 感测的总线电压范围：0V 至26V
• 报告分流和总线电压
INA3221-Q1 感测总线（电压在 0V 至 +26V 范围内变
化）上的电流。此器件由 2.7V 至 5.5V 单电源供电，
电源电流消耗为 350μA（典型值）。INA3221-Q1 的
额定工作温度范围为 –40°C 至 +125°C。兼容 I2C 和
SMBUS 的接口采用四个可编程地址。
• 高准确度：
– 失调电压：±80µV（最大值）
– 增益误差：0.25%（最大值）
• 可配置取平均选项
• 四个可编程地址
• 可编程报警和警告输出
• 电源运行：2.7V 至5.5V
器件信息(1)
封装尺寸（标称值）
器件型号
INA3221-Q1
封装
VQFN (16)
4.00mm x 4.00mm
2 应用
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
• 信息娱乐
• 后座信息娱乐系统
• 数字集群
• 电子控制单元
Power Supply
(0 V to 26 V)
CBYPASS
0.1 µF
Load 1
VS (Supply
Voltage)
VIN+1
VINœ1
10 kꢀ
Power Supply
(0 V to 26 V)
SDA
I2C-
SCL
and
CH 1
Bus
Voltages 1-3
SMBus-
Compatible
Interface
A0
CH 2
VIN+2
VINœ2
VPU
VS
Shunt
Voltages 1-3
ADC
10 kꢀ
Critical Limit
Alerts 1-3
VPU
Power Valid (PV)
Critical
CH 3
Shunt Voltage
Sum Alerts
Load 2
Warning
Timing Control (TC)
GND
VIN+3
VINœ3
Power Supply
(0 V to 26 V)
Load 3
典型应用
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS776
INA3221-Q1
ZHCSEU5C –MARCH 2016 –REVISED MARCH 2021
www.ti.com.cn
Table of Contents
8.6 Register Maps...........................................................24
9 Application and Implementation..................................37
9.1 Application Information............................................. 37
9.2 Typical Application.................................................... 37
10 Power Supply Recommendations..............................39
11 Layout...........................................................................40
11.1 Layout Guidelines................................................... 40
11.2 Layout Example...................................................... 40
12 Device and Documentation Support..........................41
12.1 Device Support....................................................... 41
12.2 Documentation Support.......................................... 41
12.3 接收文档更新通知................................................... 41
12.4 支持资源..................................................................41
12.5 Trademarks.............................................................41
12.6 静电放电警告.......................................................... 41
12.7 术语表..................................................................... 41
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................4
7.5 Electrical Characteristics.............................................5
7.6 Typical Characteristics................................................7
8 Detailed Description......................................................10
8.1 Overview...................................................................10
8.2 Functional Block Diagram.........................................10
8.3 Feature Description...................................................11
8.4 Device Functional Modes..........................................16
8.5 Programming............................................................ 20
Information.................................................................... 41
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision B (March 2016) to Revision C (March 2021)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• 添加了“提供功能安全”项目符号......................................................................................................................1
Changes from Revision A (March 2016) to Revision B (March 2016)
Page
• Changed HBM value from ±2000 V to ±2500 V in ESD Ratings table .............................................................. 4
Changes from Revision * (March 2016) to Revision A (March 2016)
Page
• 已从产品预发布更改为量产数据......................................................................................................................... 1
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5 Device Comparison Table
DEVICE
DESCRIPTION
INA226-Q1
INA220-Q1
INA212-Q1
INA282-Q1
Automotive, 36-V, Ultrahigh Accuracy, Low- or High-Side, I2C Out, Current and Power Monitor With Alert
Automotive, 26-V, Bidirectional, Zero-Drift, Low- or High-Side, I2C Out, Current and Power Monitor
Automotive, 26-V, Bidirectional, Zero-Drift, Precision, Low- or High-Side, Voltage Out, Current Sense Amplifier
Automotive, 80-V, Bidirectional, High-Accuracy, Low- or High-Side, Voltage Out, Current Shunt Monitor
6 Pin Configuration and Functions
1
12 IN+1
11 IN-1
10 PV
IN-3
IN+3
GND
VS
2
3
4
9
Critical
图6-1. RGV Package 16-Pin VQFN Top View
表6-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
Address pin. Connect to GND, SCL, SDA, or VS. 表8-1 shows pin settings and
corresponding addresses.
A0
5
Digital input
Critical
GND
9
3
Digital output
Analog
Conversion-triggered critical alert; open-drain output.
Ground
Connect to load side of the channel 1 shunt resistor. Bus voltage is the measurement
from this pin to ground.
11
12
14
15
1
Analog input
Analog input
Analog input
Analog input
Analog input
IN–1
IN+1
Connect to supply side of the channel 1 shunt resistor.
Connect to load side of the channel 2 shunt resistor. Bus voltage is the measurement
from this pin to ground.
IN–2
IN+2
Connect to supply side of the channel 2 shunt resistor.
Connect to load side of the channel 3 shunt resistor. Bus voltage is the measurement
from this pin to ground.
IN–3
IN+3
PV
2
10
6
Analog input
Digital output
Digital input
Digital I/O
Connect to supply side of the channel 3 shunt resistor.
Power valid alert; open-drain output.
SCL
SDA
TC
Serial bus clock line; open-drain input.
7
Serial bus data line; open-drain input/output.
Timing control alert; open-drain output.
13
16
4
Digital output
Analog input
Analog
VPU
VS
Pull-up supply voltage used to bias power valid output circuitry.
Power supply, 2.7 V to 5.5 V.
Warning
8
Digital output
Averaged measurement warning alert; open-drain output.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Voltage
Supply, VS
IN+, IN–
VPU
6
V
(2)
26
Differential (VIN+) –(VIN–
)
–26
Analog inputs
V
Common-mode (VIN+) + (VIN–) / 2
26
–0.3
26
Critical, warning, power valid
Timing control
6
Digital outputs
Serial bus
Current
V
V
26
Data line, SDA
6
(VS + 0.3)
5
(GND –0.3)
(GND –0.3)
Clock line, SCL
Input, into any pin
Open-drain, digital output
Operating, TA
mA
10
125
–40
–65
Temperature
Junction, TJ
150
°C
Storage, Tstg
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) VIN+ and VIN– can have a differential voltage of –26 V to +26 V; however, the voltage at these pins must not exceed the range of
–0.3 V to +26 V.
7.2 ESD Ratings
VALUE
±2500
±1000
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.7
NOM
MAX
5.5
UNIT
V
Operating supply voltage
Operating temperature, TA
125
°C
–40
7.4 Thermal Information
INA3221-Q1
RGV (VQFN)
16 PINS
36.5
THERMAL METRIC(1)
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
42.7
14.7
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.5
14.8
ψJB
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INA3221-Q1
THERMAL METRIC(1)
RGV (VQFN)
16 PINS
3.3
UNIT
RθJC(bot)
Junction-to-case (bottom) thermal resistance
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
7.5 Electrical Characteristics
at TA = 25°C, VS = 3.3 V, VIN+ = 12 V, VSHUNT = (VIN+) –(VIN–) = 0 mV, and VBUS = VIN– = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT
VSHUNT
VBUS
Shunt voltage input
163.8
26
mV
V
–163.84
Bus voltage input
0
CMR
Common-mode rejection
VIN+ = 0 V to +26 V
110
120
±40
0.1
15
dB
±80
0.5
μV
VOS
Shunt offset voltage, RTI(1)
Bus offset voltage, RTI(1)
TA = –40°C to +125°C
μV/°C
μV/V
mV
PSRR
VOS
vs power supply, VS = 2.7 V to 5.5 V
±8
±16
80
TA = –40°C to +125°C
μV/°C
mV/V
μA
PSRR
IIN+
vs power supply
0.5
10
Input bias current at IN+
Input bias current at IN–
Input leakage(2)
IIN–
10 || 670
0.1
μA || kΩ
μA
0.5
(IN+ pin) + (IN–pin), power-down mode
DC ACCURACY
ADC native resolution
13
40
Bits
μV
mV
Shunt voltage
Bus voltage
1-LSB step size
8
0.1%
10
0.25%
Shunt voltage gain error
50 ppm/°C
0.25%
TA = –40°C to +125°C
TA = –40°C to +125°C
0.1%
10
Bus voltage gain error
Differential nonlinearity
50 ppm/°C
LSB
DNL
±0.1
140
204
332
588
1.1
CT bit = 000
CT bit = 001
CT bit = 010
CT bit = 011
CT bit = 100
CT bit = 101
CT bit = 110
CT bit = 111
154
224
365
µs
646
tCONVERT
ADC conversion time
1.21
2.116
4.156
8.244
2.328
4.572
9.068
ms
ms
SMBus
SMBus timeout(3)
DIGITAL INPUT/OUTPUT
28
35
CI
Input capacitance
3
pF
μA
V
Leakage input current
High-level input voltage
Low-level input voltage
0.1
1
6
0 V ≤VIN ≤VS
VIH
VIL
0.7 (VS)
0.3 (VS)
0.4
V
–0.5
SDA, critical, warning, PV VS > +2.7 V, IOL = 3 mA
0
0
Low-level output
voltage
VOL
Vhys
V
TC
VS > +2.7 V, IOL = 1.2 mA
0.4
Hysteresis voltage
500
mV
POWER SUPPLY
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at TA = 25°C, VS = 3.3 V, VIN+ = 12 V, VSHUNT = (VIN+) –(VIN–) = 0 mV, and VBUS = VIN– = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
350
0.5
2
MAX
450
2
UNIT
μA
V
Quiescent current
Power-down mode
Power-on reset threshold
(1) RTI = Referred-to-input.
(2) Input leakage is positive (current flows into the pin) for the conditions shown at the top of this table. Negative leakage currents can
occur under different input conditions.
(3) SMBus timeouts in the INA3221-Q1 reset the interface whenever SCL is low for more than 28 ms.
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7.6 Typical Characteristics
at TA = 25 °C, VS = 3.3 V,VIN+ = 12 V, VSHUNT = (VIN+) –(VIN–) = 0 mV, and VBUS = VIN– = 12 V (unless otherwise noted)
0
−10
−20
−30
−40
−50
−60
1
10
100 1k
Frequency (Hz)
10k
100k
Input Offset Voltage (µV)
G001
G003
图7-1. Frequency Response
图7-2. Shunt Input Offset Voltage Production Distribution
50
45
40
35
30
130
125
120
115
−50
−25
0
25
Temperature (°C)
50
75
100
125
150
−50
−25
0
25
Temperature (°C)
50
75
100
125
150
G004
G005
图7-3. Shunt Input Offset Voltage vs. Temperature
图7-4. Shunt Input Common-Mode Rejection Ratio vs.
Temperature
400
350
300
250
200
150
100
50
0
−50
−25
0
25
50
75
Temperature (°C)
100
125
150
G007
Input Gain Error (%)
G006
图7-6. Shunt Input Gain Error vs. Temperature
图7-5. Shunt Input Gain Error Production Distribution
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7.6 Typical Characteristics (continued)
at TA = 25 °C, VS = 3.3 V,VIN+ = 12 V, VSHUNT = (VIN+) –(VIN–) = 0 mV, and VBUS = VIN– = 12 V (unless otherwise noted)
200
150
100
50
0
2
4
6
8
10 12 14 16 18 20 22 24 26
Common−Mode Input Voltage (V)
G008
Input Offset Voltage (mV)
G009
图7-7. Shunt Input Gain Error vs. Common-Mode Voltage
图7-8. Bus Input Offset Voltage Production Distribution
8
4
0
−4
−8
−12
−16
−50
−25
0
25
50
75
100
125
150
Temperature (°C)
G010
Input Gain Error (%)
G011
图7-9. Bus Input Offset Voltage vs. Temperature
图7-10. Bus Input Gain Error Production Distribution
400
350
300
250
200
150
100
50
50
45
40
35
30
25
20
15
10
5
IB−
IB+
0
−50
0
−25
0
25
Temperature (°C)
50
75
100
125
150
0
4
8
Common−Mode Input Voltage (V)
12
16
20
24
28
G012
G013
图7-11. Bus Input Gain Error vs. Temperature
图7-12. Input Bias Current vs. Common-Mode Voltage
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7.6 Typical Characteristics (continued)
at TA = 25 °C, VS = 3.3 V,VIN+ = 12 V, VSHUNT = (VIN+) –(VIN–) = 0 mV, and VBUS = VIN– = 12 V (unless otherwise noted)
30
25
20
15
10
5
450
400
350
300
250
200
150
100
50
IB−
IB+
IB+, IB−
0
−50
0
−50
−25
0
25
50
75
100
125
150
−25
0
25
50
75
100
125
150
Temperature (°C)
Temperature (°C)
G014
G015
图7-13. Input Bias Current vs. Temperature
图7-14. Input Bias Current vs. Temperature (Shutdown)
500
450
400
350
300
250
200
3.5
3
2.5
2
1.5
1
0.5
0
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
100
125
150
Temperature (°C)
Temperature (°C)
G016
G017
图7-15. Active IQ vs. Temperature
图7-16. Shutdown IQ vs. Temperature
700
650
600
550
500
450
400
350
300
350
300
250
200
150
100
50
0
0.01
0.01
0.1
Frequency (MHz)
1
4
0.1
Frequency (MHz)
1
4
G018
G019
图7-17. Active IQ vs. I2C Clock Frequency
图7-18. Shutdown IQ vs. I2C Clock Frequency
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8 Detailed Description
8.1 Overview
The INA3221-Q1 is a current-shunt and bus voltage monitor that communicates over an I2C- and SMBus-
compatible interface. The INA3221-Q1 provides digital shunt and bus voltage readings necessary for accurate
decision making in precisely-controlled systems, and also monitors multiple rails to maintain compliance
voltages. Programmable registers offer flexible configuration for measurement precision, and continuous versus
single-shot operation. The Register Maps section provides details of the INA3221-Q1 registers, beginning with
表8-3.
8.2 Functional Block Diagram
Bus Voltage(1)
X
Power Valid
Upper Limit (2)
Shunt Voltage
Channel
Channel 2
Channel 3
ADC
Bus Voltage
Channel
Power Valid
Lower Limit(2)
Shunt Voltage(1)
X
Critical Limit(2)
Warning Limit(2)
Channel 2
Channel 3
Summation(1)
Summation Limit(2)
A. Read-only.
B. Read/write.
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8.3 Feature Description
8.3.1 Basic ADC Functions
The INA3221-Q1 performs two measurements on up to three power supplies of interest. The voltage developed
from the load current passing through a shunt resistor creates a shunt voltage that is measured between the IN+
and IN– pins. The device also internally measures the power-supply bus voltage at the IN– pin for each
channel. The differential shunt voltage is measured with respect to the IN– pin, and the bus voltage is
measured with respect to ground.
The INA3221-Q1 is typically powered by a separate power supply that ranges from 2.7 V to 5.5 V. The monitored
supply buses range from 0 V to 26 V.
CAUTION
Based on the fixed 8-mV bus-voltage register LSB (for any channel), a full-scale register value
results in 32.76 V. However, the actual voltage applied to the INA3221-Q1 input pins must not
exceed 26 V.
There are no special power-supply sequencing considerations between the common-mode input ranges and the
device power-supply voltage because they are independent of each other; therefore, the bus voltages can be
present with the supply voltage off and vice versa.
The INA3221-Q1 takes two measurements for each channel: one for shunt voltage and one for bus voltage.
Each measurement can be independently or sequentially measured, based on the mode setting (bits 2-0 in the
Configuration register). When the INA3221-Q1 is in normal operating mode (that is, the MODE bits of the
Configuration register are set to 111), the device continuously converts a shunt-voltage reading followed by a
bus-voltage reading. This procedure converts one channel, and then continues to the shunt voltage reading of
the next enabled channel, followed by the bus-voltage reading for that channel, and so on, until all enabled
channels have been measured. The programmed Configuration register mode setting applies to all channels.
Any channels that are not enabled are bypassed in the measurement sequence, regardless of mode setting.
The INA3221-Q1 has two operating modes, continuous and single-shot, that determine the internal ADC
operation after these conversions complete. When the INA3221-Q1 is set to continuous mode (using the MODE
bit settings), the device continues to cycle through all enabled channels until a new configuration setting is
programmed.
The Configuration register MODE control bits also enable modes to be selected that convert only the shunt or
bus voltage. This feature further allows the device to fit specific application requirements.
In single-shot (triggered) mode, setting any single-shot convert mode to the Configuration register (that is, the
Configuration register MODE bits set to 001, 010, or 011) triggers a single-shot conversion. This action produces
a single set of measurements for all enabled channels. To trigger another single-shot conversion, write to the
Configuration register a second time, even if the mode does not change. When a single-shot conversion is
initiated, all enabled channels are measured one time and then the device enters a power-down state. The
INA3221-Q1 registers can be read at any time, even while in power-down. The data present in these registers
are from the last completed conversion results for the corresponding register. The conversion ready flag bit
(Mask/Enable register, CVRF bit) helps coordinate single-shot conversions, and is especially helpful during
longer conversion time settings. The CVRF bit is set after all conversions are complete. The CVRF bit clears
under the following conditions:
1. Writing to the Configuration register, except when configuring the MODE bits for power-down mode; or
2. Reading the Mask/Enable register.
In addition to the two operating modes (continuous and single-shot), the INA3221-Q1 also has a separate
selectable power-down mode that reduces the quiescent current and turns off current into the INA3221-Q1
inputs. Power-down mode reduces the impact of supply drain when the device is not used. Full recovery from
power-down mode requires 40 µs. The INA3221-Q1 registers can be written to and read from while the device is
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in power-down mode. The device remains in power-down mode until one of the active MODE settings are written
to the Configuration register.
8.3.2 Alert Monitoring
The INA3221-Q1 allows programmable thresholds that make sure the intended application operates within the
desired operating conditions. Multiple monitoring functions are available using four alert pins: Critical, Warning,
PV (power valid), and TC (timing control). These alert pins are open-drain connections.
8.3.2.1 Critical Alert
The critical-alert feature monitors functions based on individual conversions of each shunt-voltage channel. The
critical-alert limit feature compares the shunt-voltage conversion for each shunt-voltage channel to the value
programmed into the corresponding limit register, in order to determine if the measured value exceeds the
intended limit. Exceeding the programmed limit indicates that the current through the shunt resistor is too high.
At power-up, the default critical-alert limit value for each channel is set to the positive full-scale value, effectively
disabling the alert. Program the corresponding limit registers at any time to begin monitoring for out-of-range
conditions. The Critical alert pin pulls low if any channel measurement exceeds the limit present in the
corresponding-channel critical-alert limit register. When the Critical alert pulls low, read the Mask/Enable register
to determine which channel caused the critical alert flag indicator bit (CF1-3) to assert (= 1).
8.3.2.1.1 Summation Control Function
The INA3221-Q1 also allows the Critical alert pin to be controlled by the summation control function. This
function adds the single shunt-voltage conversions for the desired channels (set by SCC1-3 in the Mask/Enable
register) in order to compare the combined sum to the programmed limit.
The SCC bits either disable the summation control function or allow the summation control function to switch
between including two or three channels in the Shunt-Voltage Sum register. The Shunt-Voltage Sum Limit
register contains the programmed value that is compared to the value in the Shunt-Voltage Sum register in order
to determine if the total summed limit is exceeded. If the shunt-voltage sum limit value is exceeded, the Critical
alert pin pulls low. Either the summation alert flag indicator bit (SF) or the individual critical alert limit bits (CF1-3)
in the Mask/Enable register determine the source of the alert when the Critical alert pin pulls low.
For the summation limit to have a meaningful value, use the same shunt-resistor value on all included channels.
Unless equal shunt-resistor values are used for each channel, do not use this function to add the individual
conversion values directly together in the Shunt-Voltage Sum register to report the total current.
8.3.2.2 Warning Alert
The warning alert monitors the averaged value of each shunt-voltage channel. The averaged value of each
shunt-voltage channel is based on the number of averages set with the averaging mode bits (AVG1-3) in the
Configuration register. The average value updates in the shunt-voltage output register each time there is a
conversion on the corresponding channel. The device compares the averaged value to the value programmed in
the corresponding-channel Warning Alert Limit register to determine if the averaged value has been exceeded,
indicating whether the average current is too high. At power-up, the default warning-alert limit value for each
channel is set to the positive full-scale value, effectively disabling the alert. The corresponding limit registers can
be programmed at any time to begin monitoring for out-of-range conditions. The Warning alert pin pulls low if any
channel measurements exceed the limit present in the corresponding-channel Warning Alert Limit register. When
the Warning alert pin pulls low, read the Mask/Enable register in order to determine which channel warning alert
flag indicator bit (WF1-3) is asserted (= 1).
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8.3.2.3 Power-Valid Alert
The power-valid alert verifies if all power rails are above the required levels. This feature manages power
sequencing, and validates the reported measurements based on system configuration. Power-valid mode starts
at power-up, and detects when each channel exceeds a 10-V threshold. This 10-V level is the default value
programmed into the Power-Valid Upper-Limit register. This value can be reprogrammed when the INA3221-Q1
is powered up to a valid supply-voltage level of at least 2.7 V. When all three bus-voltage measurements reach
the programmed value loaded to the Power-Valid Upper-Limit register, the power-valid (PV) alert pin pulls high.
PV powers up in a low state, and does not pull high until the power-valid conditions are met, indicating all bus-
voltage rails are above the power-valid upper-limit value. This sequence is shown in 图8-1.
All enabled channel bus voltages are
above the power-valid upper limit.
All enabled channel bus voltages are
above the power-valid upper limit.
High
Low
Power
Valid
Output
All enabled channel bus voltages are
not above the power-valid upper limit.
At least one bus voltage channel has
dropped below the power-valid lower limit.
图8-1. Power-Valid State Diagram
When the power-valid conditions are met, and the PV pin pulls high, the INA3221-Q1 monitors if any bus-voltage
measurements drop below 9 V. This 9-V level is the default value programmed into the Power-Valid Lower-Limit
register. This value can also be reprogrammed when the INA3221-Q1 powers up to a supply voltage of at least
2.7 V. If any bus-voltage measurement on the three channels drops below the Power-Valid Lower-Limit register
value, the PV pin goes low, indicating that the power-valid condition is no longer met. At this point, the INA3221-
Q1 resumes monitoring the power rails for a power-valid condition set in the Power-Valid Upper-Limit register.
The power-valid alert function is based on the power-valid conditions requirement that all three channels reach
the intended Power-Valid Upper-Limit register value. If all three channels are not used, connect the unused-
channel IN– pin externally to one of the used channels in order to use the power-valid alert function. If the
unused channel is not connected to a valid rail, the power-valid alert function cannot detect if all three channels
reach the power-valid level. Float the unused channel IN+ pin.
The power-valid function also requires that bus-voltage measurements are monitored. To detect changes in the
power-valid state, enable bus-voltage measurements through one of the corresponding MODE-bit settings in the
Configuration register. The single-shot bus-voltage mode periodically cycles between the bus-voltage
measurements to make sure that the power-valid conditions are met.
When all three bus-voltage measurements are completed, the device compares the results to the power-valid
threshold values to determine the power-valid state. The bus-voltage measurement values remain in the
corresponding channel output registers until the bus-voltage measurements are taken again, thus updating the
output registers. When the output registers are updated, the values are again compared to the power-valid
thresholds. Without taking periodic bus-voltage measurements, the INA3221-Q1 is unable to determine if the
power-valid conditions are maintained.
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The PV pin allows for a 0-V output that indicates a power-invalid condition. An output equal to the pull-up supply
voltage connected to the VPU pin indicates a power-valid condition, as shown in 图 8-2. It is also possible to
divide down the high power-valid pull-up voltage by adding a resistor to ground at the PV output, thus allowing
this function to interface with lower-voltage circuitry, if needed.
VS
INA3321
VPU
RPU_ext
PV
RPU
(1)
RDIV
Power-Valid
Detection
A. RDIV can be used to level-shift the PV output high.
图8-2. Power-Valid Output Structure
8.3.2.4 Timing-Control Alert
The INA3221-Q1 timing-control alert function helps verify proper power-supply sequencing. At power-up, the
default INA3221-Q1 setting is continuous shunt- and bus-voltage conversion mode, and the INA3221-Q1
internally begins comparing the channel-1 bus voltage to determine when a 1.2-V level is reached. This
comparison is made each time the sequence returns to the channel-1 bus-voltage measurement. When a 1.2-V
level is detected on the channel-1 bus-voltage measurement, the INA3221-Q1 begins checking for a 1.2-V level
present on the channel-2 bus-voltage measurement. After a 1.2-V level is detected on channel 1, if the INA3221-
Q1 does not detect a 1.2-V value or greater on the bus voltage measurement following four complete cycles of
all three channels, the timing control (TC) alert pin pulls low to indicate that the INA3221-Q1 has not detected a
valid power rail on channel 2. As shown in 图 8-3, this sequence allows for approximately 28.6 ms from the time
1.2 V is detected on channel 1 for a valid voltage to be detected on channel 2. 图 8-4 illustrates the state
diagram for the TC alert pin.
1.2 V Detected on Channel-1
Bus-Voltage Measurement
Measure For 1.2 V on
Channel-2 Bus Voltage
Signal
SB SB SB SB SB SB SB SB SB SB SB SB SB SB SB
Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch
Channel
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
2.2 ms
28.6 ms
NOTE: The signal refers to the corresponding shunt (S) and bus (B) voltage measurement for each channel.
图8-3. Timing Control Timing Diagram
1.2 V Detected on Channel-1
Bus-Voltage Measurement
Measure for 1.2 V
on Channel-2 Bus Voltage
1.2 V on Channel 2 Detected
High
Timing
Control
Output
28.6 ms
1.2 V on Channel 2 Not Detected
Low
图8-4. Timing Control State Diagram
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The timing control alert function is only monitored at power-up or when a software reset is issued by setting the
reset bit (RST, bit 15) in the Configuration register. The timing control alert function timing is based on the default
device settings at power-up. Writing to the Configuration register before the timing control alert function
completes the full sequence results in disabling the timing control alert until power is cycled or a software reset is
issued.
8.3.2.5 Default Settings
The default register power-up states are listed in the Register Maps section. These registers are volatile; if
programmed to a value other than the default values shown in 表8-3, the registers must be reprogrammed every
time the device powers up.
8.3.3 Software Reset
The INA3321 features a software reset that reinitializes the device and register settings to default power-up
values without having to cycle power to the device. Use bit 15 (RST) of the Configuration register to perform a
software reset. Setting RST reinitializes all registers and settings to the default power state with the exception of
the power-valid output state.
If a software reset is issued, the INA3221-Q1 holds the output of the PV pin until the power-valid detection
sequence completes. The Power-Valid Upper Limit and Power-Valid Lower limit registers return to the default
state when the software reset has been issued. Therefore, any reprogrammed limit registers are reset, resulting
in the original power-valid thresholds validating the power-valid conditions. This architecture prevents
interruption to circuitry connected to the power valid output during a software reset event.
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8.4 Device Functional Modes
8.4.1 Averaging Function
The INA3221-Q1 includes three channels to monitor up to three independent supply buses; however,
multichannel monitoring sometimes results in poor shunt-resistor placement. Ideally, shunt resistors are placed
as close as possible to the corresponding channel input pins. However, because of system layout and multiple
power-supply rails, one or more shunt resistors may have to be located further away, thus presenting potentially
larger measurement errors. These errors result from additional trace inductance and other parasitic impedances
between the shunt resistor and input pins. Longer traces also create an additional potential for coupling noise
into the signal if they are routed near noise-generating sections of the board.
The INA3221-Q1 averaging function mitigates this potential problem by limiting the impact that any single
measurement has on the averaged value of each measured signal. This limitation reduces the influence that
noise has on the averaged value, thereby effectively creating an input-signal filter.
The averaging function is illustrated in 图 8-5. Operation begins by first measuring the shunt input signal on
channel 1. This value is then subtracted from the previous value that was present in the corresponding data
output register. This difference is then divided by the value programmed by the averaging mode setting (AVG2-0,
Configuration register bits 11-9) and stored in an internal accumulation register. The computed result is then
added to the previously-loaded data output register value, and the resulting value is loaded to the corresponding
data output register. After the update, the next signal to be measured follows the same process. The larger the
value selected for the averaging mode setting, the less impact or influence any new conversion has on the
average value, as shown in 图 8-6. This averaging feature functions as a filter to reduce input noise from the
averaged measurement value.
+
+
÷
AVG #
New
Sample
Output
Register
ꢀ
ꢀ
œ
+
图8-5. Averaging Function Block Diagram
26
1 Average
16 Averages
1024 Averages
25
24
23
22
21
20
1000
2000
3000
4000
5000
6000
7000
Samples
G020
图8-6. Average Setting Example
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8.4.2 Multiple Channel Monitoring
The INA3221-Q1 monitors shunt and voltage measurements for up to three unique power-supply rails, and
measures up to six different signals. Adjust the number of channels and signals being measured by setting the
channel enable (CH1en to CH3en) and mode (MODE3-1) bits in the Configuration register. This adjustment
allows the device to be optimized based on application requirements for the system in use.
8.4.2.1 Channel Configuration
If all three channels must be monitored at power-up, but only one channel must be monitored after the system
has stabilized, disable the other two channels after power-up. This configuration allows the INA3221-Q1 to only
monitor the power-supply rail of interest. Disable unused channels to help improve system response time by
more quickly returning to sampling the channel of interest. The INA3221-Q1 linearly monitors the enabled
channels. That is, if all three channels are enabled for both shunt- and bus-voltage measurements, an additional
five conversions complete after a signal is measured before the device returns to that particular signal to begin
another conversion. To reduce this requirement down to two conversions before the device begins a new
conversion on a particular channel again, change the operating mode to monitor only the shunt voltage.
A timing aspect is also involved in reducing the measured signals. The amount of time to complete an all-
channel, shunt- and bus-voltage sequence is equal to the sum of the shunt-voltage conversion time and the bus-
voltage conversion time (programmed by the CT bits in the Configuration register) multiplied by the three
channels. The conversion times for the shunt- and bus-voltage measurements are programmed independently;
however, the selected shunt- and bus-voltage conversion times apply to all channels.
Enable a single channel with only one signal measured to allow for that particular signal to be monitored solely.
This setting enables the fastest response over time to changes in that specific input signal because there is no
delay from the end of one conversion before the next conversion begins on that channel. Conversion time is not
affected by enabling or disabling other channels. Selecting both the shunt- and bus-voltage settings, as well as
enabling additional channels, extends the time from the end of one conversion on a signal before the beginning
of the next conversion of that signal.
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8.4.2.2 Averaging and Conversion-Time Considerations
The INA3221-Q1 has programmable conversion times for both the shunt- and bus-voltage measurements. The
selectable conversion times for these measurements range from 140 μs to 8.244 ms. The conversion-time
settings, along with the programmable-averaging mode, enable the INA3221-Q1 to optimize available timing
requirements in a given application. For example, if a system requires data to be read every 2 ms with all three
channels monitored, configure the INA3221-Q1 with the conversion times for the shunt- and bus-voltage
measurements set to 332 μs.
The INA3221-Q1 can also be configured with a different conversion-time setting for the shunt- and bus-voltage
measurements. This approach is common in applications where the bus voltage tends to be relatively stable,
and allows for the time focused on the bus voltage measurement to be reduced relative to the shunt-voltage
measurement. For example, the shunt-voltage conversion time can be set to 4.156 ms with the bus-voltage
conversion time set to 588 μs for a 5-ms update time.
There are trade-offs associated with the conversion-time and averaging-mode settings. The averaging feature
significantly improves the measurement accuracy by effectively filtering the signal. This approach allows the
INA3221-Q1 to reduce the amount of noise in the measurement caused by noise coupling into the signal. A
greater number of averages allows the INA3221-Q1 to be more effective in reducing the measurement noise
component. The trade-off to this noise reduction is that the averaged value has a longer response time to input-
signal changes. This aspect of the averaging feature is mitigated to some extent with the critical-alert feature that
compares each single conversion to determine if a measured signal (with noise component) has exceeded the
maximum acceptable level.
The selected conversion times also have an impact on measurement accuracy. This effect can seen in 图 8-7.
The multiple conversion times shown in 图 8-7 illustrate the impact of noise on measurement. These curves
shown do not use averaging. In order to achieve the highest-accuracy measurement possible, use a
combination of the longest allowable conversion times and highest number of averages, based on system timing
requirements.
120
Conversion Time: 140 µs
80
40
Conversion Time: 332 µs
0
Þ40
Conversion Time: 1.1 ms
Þ80
Þ120
0
200
400
600
800
1000
Number of Conversions
图8-7. Noise Versus Conversion Time
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8.4.3 Filtering and Input Considerations
Measuring current is often noisy, and such noise can be difficult to define. The INA3221-Q1 offers several
filtering options by allowing conversion times and the number of averages to be selected independently in the
Configuration register. The conversion times can be set independently for the shunt- and bus-voltage
measurements as well, for added flexibility in configuring power-supply bus monitoring.
The internal ADC is based on a delta-sigma (ΔΣ) front-end with a 500-kHz (±30%) typical sampling rate. This
architecture has good inherent noise rejection; however, transients that occur at or very close to the sampling-
rate harmonics can cause problems. These transient signals are at 1 MHz and higher; therefore, the signals are
managed by incorporating filtering at the INA3221-Q1 input. High-frequency signals allow for the use of low-
value series resistors on the filter, with negligible effects on measurement accuracy. In general, filtering the
INA3221-Q1 input is only necessary if there are transients at exact harmonics of the 500-kHz (±30%) sampling
rate that are greater than 1 MHz. Filter using the lowest-possible series resistance (typically 10 Ω or less) and a
ceramic capacitor. Recommended capacitor values are 0.1 μF to 1.0 μF. 图8-8 shows the INA3221-Q1 with an
additional filter added at the input.
Power Supply
(0 V to 26 V)
Ch 1
RFILTER
≤ 10 ꢀ
Ch 2
VIN+2
ADC
CFILTER
VIN-2
RFILTER
≤ 10 ꢀ
Ch 3
Load 2
CFILTER: 0.1-ꢁF to 1-ꢁF
Ceramic Capacitor
图8-8. INA3221-Q1 With Input Filtering
The INA3221-Q1 inputs are specified to tolerate 26 V across the inputs. However, overload conditions are
another consideration for the INA3221-Q1 inputs. For example, a large differential-input scenario might be a
short to ground on the load side of the shunt. This type of event results in the full power-supply voltage applied
across the shunt, if supported by the power supply or energy-storage capacitors. Keep in mind that removing a
short to ground may result in inductive kickbacks that can exceed the 26-V differential and common-mode rating
of the INA3221-Q1. Inductive kickback voltages are best controlled by zener-type transient-absorbing devices
(commonly called transzorbs) combined with sufficient energy-storage capacitance.
In applications that do not have large energy-storage electrolytic capacitors on one or both sides of the shunt, an
input overstress condition can result from an excessive dV/dt of the voltage applied to the input. A hard physical
short is the most likely cause of this event, particularly in applications without large electrolytic capacitors
present. This problem occurs because an excessive dV/dt can activate the INA3221-Q1 ESD protection in
systems where large currents are available. Testing has demonstrated that the addition of 10-Ω resistors in
series with each INA3221-Q1 input sufficiently protects the inputs against this dV/dt failure up to the 26-V device
rating. Selecting these resistors in the range noted has minimal effect on accuracy.
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8.5 Programming
8.5.1 Bus Overview
The INA3221-Q1 offers compatibility with both I2C and SMBus interfaces. The I2C and SMBus protocols are
essentially compatible with one another.
The I2C interface is used throughout this data sheet as the primary example, with the SMBus protocol specified
only when a difference between the two systems is discussed. Two I/O lines, the serial clock (SCL) and data
signal line (SDA), connect the INA3221-Q1 to the bus. Both SCL and SDA are open-drain connections.
The device that initiates a data transfer is called a master, and the devices controlled by the master are slaves.
The bus must be controlled by the master device that generates the SCL, controls the bus access, and
generates start and stop conditions.
To address a specific device, the master initiates a start condition by pulling SDA from a high to a low logic level
while SCL is high. All slaves on the bus shift in the slave address byte on the SCL rising edge, with the last bit
indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being addressed
responds to the master by generating an acknowledge bit and pulling SDA low.
Data transfer is then initiated and eight bits of data are sent, followed by an acknowledge bit. During data
transfer, SDA must remain stable while SCL is high. Any change in SDA while SCL is high is interpreted as a
start or stop condition.
After all data are transferred, the master generates a stop condition by pulling SDA from low to high while SCL is
high. The INA3221-Q1 includes a 28-ms timeout on the interface to prevent locking up the bus.
8.5.1.1 Serial Bus Address
To communicate with the INA3221-Q1, the master must first address slave devices with a slave address byte.
This byte consists of seven address bits and a direction bit to indicate whether the intended action is a read or
write operation.
The INA3221-Q1 has one address pin, A0. 表 8-1 describes the pin logic levels for each of the four possible
addresses. The state of the A0 pin is sampled on every bus communication and must be set before any activity
on the interface occurs.
表8-1. Address Pins and Slave Addresses
A0
GND
VS
SLAVE ADDRESS
1000000
1000001
SDA
SCL
1000010
1000011
8.5.1.2 Serial Interface
The INA3221-Q1 only operates as a slave device on the I2C bus and SMBus. Bus connections are made using
the open-drain I/O lines, SDA and SCL. The SDA and SCL pins feature integrated spike-suppression filters and
Schmitt triggers to minimize the effects of input spikes and bus noise. While there is spike suppression
integrated into the digital I/O lines, use proper layout to minimize the amount of coupling into the communication
lines. Noise introduction occurs from capacitively coupling signal edges between the two communication lines
themselves, or from other switching noise sources present in the system. Routing traces in parallel with ground
between layers on a printed circuit board (PCB) typically reduces the effects of coupling between the
communication lines. Shield communication lines to reduce the possibility of unintended noise coupling into the
digital I/O lines that could be incorrectly interpreted as start or stop commands.
The INA3221-Q1 supports a transmission protocol for Fast (1 kHz to 400 kHz) and High-speed (1 kHz to 2.44
MHz) modes. All data bytes are transmitted MSB first.
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8.5.2 Writing To and Reading From the INA3221-Q1
To access a specific INA3221-Q1 register, write the appropriate value to the register pointer. See 表 8-3 for a
complete list of registers and corresponding addresses. The value for the register pointer, as shown in 图 8-9, is
the first byte transferred after the slave address byte with the R/ W bit low. Every write operation to the INA3221-
Q1 requires a register pointer value.
1
9
1
9
SCL
SDA
1
0
0
0
0
0
A0
R/W
D7 D6 D5 D4 D3 D2 D1 D0
Start By
Master
ACK By
Device
ACK By
Device
Stop By
Master
Frame 1: Two-Wire Slave Address Byte(1)
Frame 2: Register Pointer Byte
A. The value of the Slave Address Byte is determined by the A0 pin setting; see 表8-1.
图8-9. Typical Register Pointer Set
Register writes begin with the first byte transmitted by the master. This byte is the slave address, with the R/ W
bit low. The INA3221-Q1 then acknowledges receipt of a valid address. The next byte transmitted by the master
is the register address that data are written to. This register address value updates the register pointer to the
desired register. The next two bytes are written to the register addressed by the register pointer. The INA3221-
Q1 acknowledges receipt of each data byte. The master terminates data transfer by generating a start or stop
condition.
When reading from the INA3221-Q1, the last value stored in the register pointer by a write operation determines
which register is read during a read operation. To change the register pointer for a read operation, write a new
value to the register pointer. This write is accomplished by issuing a slave address byte with the R/ W bit low,
followed by the register pointer byte. No additional data are required. The master then generates a start
condition and sends the slave address byte with the R/ W bit high to initiate the read command. The next byte is
transmitted by the slave and is the most significant byte of the register indicated by the register pointer. This byte
is followed by an acknowledge from the master; then the slave transmits the least significant byte. The master
acknowledges receipt of the data byte. The master terminates data transfer by generating a not-acknowledge
after receiving any data byte, or generating a start or stop condition. If repeated reads from the same register are
desired, it is not necessary to continually send the register pointer bytes; the INA3221-Q1 retains the register
pointer value until it is changed by the next write operation.
图8-10 and 图8-11 show the write and read operation timing diagrams, respectively. Note that register bytes are
sent most-significant byte first, followed by the least significant byte.
1
9
1
9
1
9
SCL
SDA
1
0
0
0
0
0
A0
R/W
D15 D14 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
Start By
Master
ACK By
Device
ACK By
Device
ACK By
Device
Stop By
Master
Frame 1: Two-Wire Slave Address Byte (1)
Frame 2: Data MSByte
Frame 3: Data LSByte
A. The value of the slave address byte is determined by the A0 pin setting; see 表8-1.
图8-10. Timing Diagram for Write Word Format
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1
9
1
9
1
9
SCL
SDA
1
0
0
0
0
0
A0 R/W
D15 D14 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
Start By
Master
ACK By
Device
From
Device
ACK By
Master
From
Device
No ACK By
Master(3)
Stop By
Master
Frame 1: Two-Wire Slave Address Byte(1)
Frame 2: Data MSByte(2)
Frame 3: Data LSByte(2)
A. The value of the slave address byte is determined by the A0 pin setting; see 表8-1.
B. Read data are from the last register pointer location. If a new register is desired, the register pointer must be updated. See 图8-9.
C. The master can also send an ACK.
图8-11. Timing Diagram for Read Word Format
图8-12 shows the timing diagram for the SMBus Alert response operation.
1
9
1
9
SCL
SDA
0
0
0
1
1
0
0
R/W
1
0
0
0
0
0
A0
0
Start By
Master
ACK By
Device
From
Device
No ACK By
Master
Stop By
Master
Frame 2: Slave Address Byte(1)
Frame 1: SMBus ALERT Response Address Byte
A. The value of the Slave Address Byte is determined by the A0 pin setting; see 表8-1.
图8-12. Timing Diagram for SMBus Alert
8.5.2.1 High-Speed I2C Mode
When the bus is idle, the SDA and SCL lines are pulled high by the pull-up resistors. The master generates a
start condition followed by a valid serial byte with the high-speed (Hs) master code 00001XXX. This transmission
is made in fast (400 kHz) or standard (100 kHz) (F/S) mode at no more than 400 kHz. The INA3221-Q1 does not
acknowledge the Hs master code, but does recognize it and switches its internal filters to support 2.44-MHz
operation.
The master then generates a repeated start condition (a repeated start condition has the same timing as the
start condition). After this repeated start condition, the protocol is the same as F/S mode, except that
transmission speeds up to 2.44 MHz are allowed. Instead of using a stop condition, the master uses a repeated
start conditions to secure the bus in Hs mode. A stop condition ends the Hs mode, and switches all internal
INA3221-Q1 filters to support F/S mode.
图8-13 shows the bus timing, and 表8-2 lists the bus timing definitions.
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t(LOW)
tr
tfCL
SCL
t(HDSTA)
t(SUSTA)
t(SUDAT)
t(HIGH)
t(SUSTO)
t(HDDAT)
t(VDDAT)
t(HDSTA)
tfDA
SDA
t(BUF)
S
P
P
S
图8-13. Bus Timing
表8-2. Bus Timing Definitions(1)
FAST MODE
HIGH-SPEED MODE
PARAMETER
SCL operating frequency
MIN
MAX
MIN
0.001
160
MAX
UNIT
MHz
ns
f(SCL)
t(BUF)
0.001
0.4
2.44
Bus free time between stop and start conditions
1300
600
Hold time after repeated START condition.
After this period, the first clock is generated.
t(HDSTA)
160
ns
t(SUSTA)
t(SUSTO)
t(HDDAT)
t(VDDAT)
t(SUDAT)
t(LOW)
t(HIGH)
tfDA
Repeated start condition setup time
STOP condition setup time
Data hold time
600
600
0
160
160
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data valid time
1200
260
Data setup time
100
1300
600
10
270
60
SCL clock low period
SCL clock high period
Data fall time
500
300
150
40
tfCL
Clock fall time
Clock rise time
300
40
tr
1000
Clock rise time for SCLK ≤100 kHz
(1) Values based on a statistical analysis of a one-time sample of devices. Minimum and maximum values are not production tested.
A0 = A1 = 0.
8.5.3 SMBus Alert Response
The INA3221-Q1 responds to the SMBus alert response address. The SMBus alert response provides a quick
fault identification for simple slave devices. When an alert occurs, the master broadcasts the alert response
slave address (0001 100) with the R/ W bit set high. Following this alert response, any slave devices that
generated an alert identify themselves by acknowledging the alert response, and sending their respective
address on the bus.
The alert response can activate several different slave devices simultaneously, similar to the I2C general call. If
more than one slave attempts to respond, bus arbitration rules apply. The losing device does not generate an
acknowledge, and continues to hold the alert line low until the interrupt is cleared.
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8.6 Register Maps
The INA3221-Q1 uses a bank of registers for holding configuration settings, measurement results, minimum and
maximum limits, and status information. 表 8-3 summarizes the INA3221-Q1 registers; see the Functional Block
Diagram section for an illustration of the registers.
8.6.1 Summary of Register Set
表8-3. Summary of Register Set
POINTER
ADDRESS
(Hex)
POWER-ON RESET
BINARY
REGISTER NAME
Configuration
DESCRIPTION
HEX
TYPE(1)
All-register reset, shunt and bus voltage ADC conversion times and
averaging, operating mode.
0
01110001 00100111
7127
R/ W
1
2
3
4
5
6
Channel-1 Shunt Voltage Averaged shunt voltage value.
Channel-1 Bus Voltage Averaged bus voltage value.
Channel-2 Shunt Voltage Averaged shunt voltage value.
Channel-2 Bus Voltage Averaged bus voltage value.
Channel-3 Shunt Voltage Averaged shunt voltage value.
00000000 00000000
00000000 00000000
00000000 00000000
00000000 00000000
00000000 00000000
00000000 00000000
0000
0000
0000
0000
0000
0000
R
R
R
R
R
R
Channel-3 Bus Voltage
Averaged bus voltage value.
Channel-1 Critical Alert
Limit
Contains limit value to compare each conversion value to determine
if the corresponding limit has been exceeded.
7
8
01111111 11111000
01111111 11111000
01111111 11111000
01111111 11111000
01111111 11111000
01111111 11111000
00000000 00000000
01111111 11111110
00000000 00000010
00100111 00010000
7FF8
7FF8
7FF8
7FF8
7FF8
7FF8
0000
7FFE
0002
2710
R/ W
R/ W
R/ W
R/ W
R/ W
R/ W
R
Channel-1 Warning Alert Contains limit value to compare to averaged measurement to
Limit
determine if the corresponding limit has been exceeded.
Channel-2 Critical Alert
Limit
Contains limit value to compare each conversion value to determine
if the corresponding limit has been exceeded.
9
Channel-2 Warning Alert Contains limit value to compare to averaged measurement to
Limit
A
B
C
D
E
F
determine if the corresponding limit has been exceeded.
Channel-3 Critical Alert
Limit
Contains limit value to compare each conversion value to determine
if the corresponding limit has been exceeded.
Channel-3 Warning Alert Contains limit value to compare to averaged measurement to
Limit
determine if the corresponding limit has been exceeded.
Contains the summed value of the each of the selected shunt
voltage conversions.
Shunt-Voltage Sum
Contains limit value to compare to the Shunt Voltage Sum register to
determine if the corresponding limit has been exceeded.
Shunt-Voltage Sum Limit
Mask/Enable
R/ W
R/ W
R/ W
Alert configuration, alert status indication, summation control and
status.
Contains limit value to compare all bus voltage conversions to
determine if the Power Valid level has been reached.
10
Power-Valid Upper Limit
Contains limit value to compare all bus voltage conversions to
determine if the any voltage rail has dropped below the Power Valid
range.
11
Power-Valid Lower Limit
00100011 00101000
2328
R/ W
FE
FF
Manufacturer ID
Die ID
Contains unique manufacturer identification number.
Contains unique die identification number.
01010100 01001001
00110010 00100000
5449
3220
R
R
(1) Type: R = read-only, R/ W = read/write.
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8.6.2 Register Descriptions
All 16-bit INA3221-Q1 registers are two 8-bit bytes via the I2C interface. 表8-4 shows a register map for the INA3221-Q1.
表8-4. Register Map
ADDRESS
REGISTER
Configuration
(Hex)
D15
RST
D14
CH1en
SD11
BD11
SD11
BD11
SD11
BD11
D13
CH2en
SD10
BD10
SD10
BD10
SD10
BD10
D12
CH3en
SD9
BD9
SD9
BD9
SD9
BD9
D11
AVG2
SD8
BD8
SD8
BD8
SD8
BD8
D10
AVG1
SD7
BD7
SD7
BD7
SD7
BD7
D9
AVG0
SD6
BD6
SD6
BD6
SD6
BD6
D8
D7
D6
D5
D4
D3
D2
D1
D0
00
VBUSCT2 VBUSCT1 VBUSCT0 VSHCT2 VSHCT1 VSHCT0 MODE3 MODE2 MODE1
Channel-1 Shunt Voltage
Channel-1 Bus Voltage
Channel-2 Shunt Voltage
Channel-2 Bus Voltage
Channel-3 Shunt Voltage
Channel-3 Bus Voltage
01
SIGN
SIGN
SIGN
SIGN
SIGN
SIGN
SD5
BD5
SD5
BD5
SD5
BD5
SD4
BD4
SD4
BD4
SD4
BD4
SD3
BD3
SD3
BD3
SD3
BD3
SD2
BD2
SD2
BD2
SD2
BD2
SD1
BD1
SD1
BD1
SD1
BD1
SD0
BD0
SD0
BD0
SD0
BD0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
02
03
04
05
06
Channel-1 Critical-Alert
Limit
07
08
09
0A
0B
0C
C1L12
W1L12
C2L12
W2L12
C3L12
W3L12
C1L11
W1L11
C2L11
W2L11
C3L11
W3L11
C1L10
W1L10
C2L10
W2L10
C3L10
W3L10
C1L9
W1L9
C2L9
W2L9
C3L9
W3L9
C1L8
W1L8
C2L8
W2L8
C3L8
W3L8
C1L7
W1L7
C2L7
W2L7
C3L7
W3L7
C1L6
W1L6
C2L6
W2L6
C3L6
W3L6
C1L5
W1L5
C2L5
W2L5
C3L5
W3L5
C1L4
W1L4
C2L4
W2L4
C3L4
W3L4
C1L3
W1L3
C2L3
W2L3
C3L3
W3L3
C1L2
W1L2
C2L2
W2L2
C3L2
W3L2
C1L1
W1L1
C2L1
W2L1
C3L1
W3L1
C1L0
W1L0
C2L0
W2L0
C3L0
W3L0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Channel-1 Warning-Alert
Limit
Channel-2 Critical-Alert
Limit
Channel-2 Warning-Alert
Limit
Channel-3 Critical-Alert
Limit
Channel-3 Warning-Alert
Limit
Shunt-Voltage Sum
Shunt-Voltage Sum Limit
Mask/Enable
0D
0E
0F
10
11
SIGN
SIGN
SV13
SVL13
SCC1
PVU11
PVL11
1
SV12
SVL12
SCC2
PVU10
PVL10
0
SV11
SVL11
SCC3
PVU9
PVL9
1
SV10
SVL10
WEN
PVU8
PVL8
0
SV9
SVL9
CEN
PVU7
PVL7
1
SV8
SVL8
CF1
PVU6
PVL6
0
SV7
SVL7
CF2
PVU5
PVL5
0
SV6
SVL6
CF3
PVU4
PVL4
0
SV5
SVL5
SF
SV4
SVL4
WF1
PVU2
PVL2
0
SV3
SVL3
WF2
PVU1
PVL1
0
SV2
SVL2
WF3
PVU0
PVL0
1
SV1
SVL1
PVF
SV0
SVL0
TCF
—
—
CVRF
—
PVU12
PVL12
0
Power-Valid Upper Limit
Power-Valid Lower Limit
Manufacturer ID
PVU3
PVL3
1
—
—
0
—
—
0
—
—
1
FE
FF
Die ID
0
0
1
1
0
0
1
0
0
0
1
0
0
0
0
0
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8.6.2.1 Configuration Register (address = 00h) [reset = 7127h]
The Configuration register settings control the operating modes for the shunt- and bus-voltage measurements for
the three input channels. This register controls the conversion time settings for both the shunt- and bus-voltage
measurements and the averaging mode used. The Configuration register is used to independently enable or
disable each channel, as well as select the operating mode that controls which signals are selected to be
measured.
This register can be read from at any time without impacting or affecting either device settings or conversions in
progress. Writing to this register halts any conversion in progress until the write sequence is completed, resulting
in a new conversion starting, based on the new Configuration register contents. This architecture prevents any
uncertainty in the conditions used for the next completed conversion.
表8-5. Configuration Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VBUS
CT2
VBUS
CT1
VBUS
CT0
VSH
CT2
VSH
CT1
VSH
CT0
MODE
3
MODE
2
MODE
1
RST
RW-0
CH1en
RW-1
CH2en
RW-1
CH3en
RW-1
AVG2
RW-0
AVG1
RW-0
AVG0
RW-0
RW-1
RW-0
RW-0
RW-1
RW-0
RW-0
RW-1
RW-1
RW-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-6. Configuration Register Field Descriptions
Bit
Field
Type
Reset
Description
15
RST
R/W
0h
Reset bit. Set this bit = 1 to generate a system reset that is the
same as a power-on reset (POR). This bit resets all registers to
default values and self-clears.
14
13
CH1en
CH2en
CH3en
AVG2-0
R/W
R/W
7h
0h
Channel enable mode. These bits allow each channel to be
independently enabled or disabled.
0 = Channel disable
12
1 = Channel enable (default)
11-9
Averaging mode. These bits set the number of samples that are
collected and averaged together.
000 = 1 (default)
001 = 4
010 = 16
011 = 64
100 = 128
101 = 256
110 = 512
111 = 1024
8-6
VBUSCT2-0
R/W
4h
Bus-voltage conversion time. These bits set the conversion time
for the bus-voltage measurement.
000 = 140 μs
001 = 204 μs
010 = 332 μs
011 = 588 μs
100 = 1.1 ms (default)
101 = 2.116 ms
110 = 4.156 ms
111 = 8.244 ms
5-3
VSHCT2-0
R/W
4h
Shunt-voltage conversion time. These bits set the conversion
time for the shunt-voltage measurement.
The conversion-time bit settings for VSHCT2-0 are the same as
VBUSCT2-0 (bits 8-6) listed in the previous row.
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表8-6. Configuration Register Field Descriptions (continued)
Bit
Field
MODE3-1
Type
Reset
Description
2-0
R/W
7h
Operating mode. These bits select continuous, single-shot
(triggered), or power-down mode of operation. These bits default
to continuous shunt and bus mode.
000 = Power-down
001 = Shunt voltage, single-shot (triggered)
010 = Bus voltage, single-shot (triggered)
011 = Shunt and bus, single-shot (triggered)
100 = Power-down
101 = Shunt voltage, continuous
110 = Bus voltage, continuous
111 = Shunt and bus, continuous (default)
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8.6.2.2 Channel-1 Shunt-Voltage Register (address = 01h), [reset = 00h]
This register contains the averaged shunt-voltage measurement for channel 1. This register stores the current
shunt-voltage reading, VSHUNT, for channel 1. Negative numbers are represented in twos complement format.
Generate the twos complement of a negative number by complementing the absolute value binary number and
adding 1. Extend the sign, denoting a negative number by setting MSB = 1.
Full-scale range = 163.8 mV (decimal = 7FF8); LSB (SD0): 40 μV.
Example: For a value of VSHUNT = –80 mV:
1. Take the absolute value: 80 mV
2. Translate this number to a whole decimal number (80 mV / 40 µV) = 2000
3. Convert this number to binary = 011 1110 1000 0_ _ _ (last three bits are set to 0)
4. Complement the binary result = 100 0001 0111 1111
5. Add 1 to the complement to create the twos complement result = 100 0001 1000 0000
6. Extend the sign and create the 16-bit word: 1100 0001 1000 0000 = C180h
表8-7. Channel-1 Shunt-Voltage Register
15
SIGN SD11 SD10
R-0 R-0 R-0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SD9
R-0
SD8
R-0
SD7
R-0
SD6
R-0
SD5
R-0
SD4
R-0
SD3
R-0
SD2
R-0
SD1
R-0
SD0
R-0
—
—
—
R-0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-8. Channel-1 Shunt-Voltage Register Field Descriptions
Bit
Field
Type
Reset
Description
15
SIGN
R
0h
Sign bit.
0 = positive number
1 = negative number in twos complement format
Channel-1 shunt-voltage data bits
Reserved
14-3
2-0
SD11-0
R
R
0h
0h
Reserved
8.6.2.3 Channel-1 Bus-Voltage Register (address = 02h) [reset = 00h]
This register stores the bus voltage reading, VBUS, for channel 1. Full-scale range = 32.76 V (decimal = 7FF8);
LSB (BD0) = 8 mV. Although the input range is 26 V, the full-scale range of the ADC scaling is 32.76 V. Do not
apply more than 26 V.
表8-9. Channel-1 Bus-Voltage Register
15
SIGN BD11 BD10
R-0 R-0 R-0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BD9
R-0
BD8
R-0
BD7
R-0
BD6
R-0
BD5
R-0
BD4
R-0
BD3
R-0
BD2
R-0
BD1
R-0
BD0
R-0
—
—
—
R-0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-10. Channel-1 Bus-Voltage Register Field Descriptions
Bit
Field
Type
Reset
Description
15
SIGN
R
0h
Sign bit.
0 = positive number
1 = negative number in twos complement format.
Channel-1 bus-voltage data bits
Reserved
14-3
2-0
BD11-0
R
R
0h
0h
Reserved
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8.6.2.4 Channel-2 Shunt-Voltage Register (address = 03h) [reset = 00h]
This register contains the averaged shunt voltage measurement for channel 2. Full-scale range = 163.8 mV
(decimal = 7FF8); LSB (SD0): 40 μV. Although the input range is 26 V, the full-scale range of the ADC scaling is
32.76 V. Do not apply more than 26 V.
表8-11. Channel-2 Shunt-Voltage Register
15
SIGN SD11 SD10
R-0 R-0 R-0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SD9
R-0
SD8
R-0
SD7
R-0
SD6
R-0
SD5
R-0
SD4
R-0
SD3
R-0
SD2
R-0
SD1
R-0
SD0
R-0
—
—
—
R-0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-12. Channel-2 Shunt-Voltage Register Field Descriptions
Bit
Field
Type
Reset
Description
15
SIGN
R
0h
Sign bit.
0 = positive number
1 = negative number in twos complement format
Channel-2 shunt-voltage data bits
Reserved
14-3
2-0
SD11-0
R
R
0h
0h
Reserved
8.6.2.5 Channel-2 Bus-Voltage Register (address = 04h) [reset = 00h]
This register stores the bus voltage reading, VBUS, for channel 2. Full-scale range = 32.76 V (decimal = 7FF8);
LSB (BD0) = 8 mV. Although the input range is 26 V, the full-scale range of the ADC scaling is 32.76 V. Do not
apply more than 26 V.
表8-13. Channel-2 Bus-Voltage Register
15
SIGN BD11 BD10
R-0 R-0 R-0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BD9
R-0
BD8
R-0
BD7
R-0
BD6
R-0
BD5
R-0
BD4
R-0
BD3
R-0
BD2
R-0
BD1
R-0
BD0
R-0
—
—
—
R-0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-14. Channel-2 Bus-Voltage Register Field Descriptions
Bit
Field
Type
Reset
Description
15
SIGN
R
0h
Sign bit.
0 = positive number
1 = negative number in twos complement format
Channel-2 bus-voltage data bits
Reserved
14-3
2-0
BD11-0
R
R
0h
0h
Reserved
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8.6.2.6 Channel-3 Shunt-Voltage Register (address = 05h) [reset = 00h]
This register contains the averaged shunt voltage measurement for channel 3. Full-scale range = 163.8 mV
(decimal = 7FF8); LSB (SD0): 40 μV.
表8-15. Channel-3 Shunt-Voltage Register
15
SIGN SD11 SD10
R-0 R-0 R-0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SD9
R-0
SD8
R-0
SD7
R-0
SD6
R-0
SD5
R-0
SD4
R-0
SD3
R-0
SD2
R-0
SD1
R-0
SD0
R-0
—
—
—
R-0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-16. Channel-3 Shunt-Voltage Register Field Descriptions
Bit
Field
Type
Reset
Description
15
SIGN
R
0h
Sign bit.
0 = positive number
1 = negative number in twos complement format
Channel-3 shunt-voltage data bits
Reserved
14-3
2-0
SD11-0
R
R
0h
0h
Reserved
8.6.2.7 Channel-3 Bus-Voltage Register (address = 06h) [reset = 00h]
This register stores the bus voltage reading, VBUS, for channel 3. Full-scale range = 32.76 V (decimal = 7FF8);
LSB (BD0) = 8 mV. Although the input range is 26 V, the full-scale range of the ADC scaling is 32.76 V. Do not
apply more than 26 V.
表8-17. Channel-3 Bus-Voltage Register
15
SIGN BD11 BD10
R-0 R-0 R-0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BD9
R-0
BD8
R-0
BD7
R-0
BD6
R-0
BD5
R-0
BD4
R-0
BD3
R-0
BD2
R-0
BD1
R-0
BD0
R-0
—
—
—
R-0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-18. Channel-3 Bus-Voltage Register Field Descriptions
Bit
Field
Type
Reset
Description
15
SIGN
R
0h
Sign bit.
0 = positive number
1 = negative number in twos complement format
Channel-3 bus-voltage data bits
Reserved
14-3
2-0
BD11-0
R
R
0h
0h
Reserved
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8.6.2.8 Channel-1 Critical-Alert Limit Register (address = 07h) [reset = 7FF8h]
This register contains the value used to compare to each shunt voltage conversion on channel 1 to detect fast
overcurrent events.
表8-19. Channel-1 Critical-Alert Limit Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
C1L12 C1L11 C1L10 C1L9
C1L8
C1L7
C1L6
C1L5
C1L4
C1L3
C1L2
C1L1
C1L0
—
—
—
RW-0 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-0 RW-0 RW-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-20. Channel-1 Critical-Alert Limit Register Field Descriptions
Bit
15-3
2-0
Field
Type
R/W
R/W
Reset
FFFh
0h
Description
C1L12-0
Reserved
Channel-1 critical-alert-limit data bits
Reserved
8.6.2.9 Warning-Alert Channel-1 Limit Register (address = 08h) [reset = 7FF8h]
This register contains the value used to compare to the averaged shunt voltage value of channel 1 to detect a
longer duration overcurrent event.
表8-21. Channel-1 Warning-Alert Limit Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
W1L12 W1L11 W1L10 W1L9 W1L8 W1L7 W1L6 W1L5 W1L4 W1L3 W1L2 W1L1 W1L0
—
—
—
RW-0 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-0 RW-0 RW-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-22. Channel-1 Warning-Alert Limit Register Field Descriptions
Bit
15-3
2-0
Field
Type
R/W
R/W
Reset
FFFh
0h
Description
W1L12-0
Reserved
Channel-1 warning-alert-limit data bits
Reserved
8.6.2.10 Channel-2 Critical-Alert Limit Register (address = 09h) [reset = 7FF8h]
This register contains the value used to compare to each shunt voltage conversion on channel 2 to detect fast
overcurrent events.
表8-23. Channel-2 Critical-Alert Limit Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
C2L12 C2L11 C2L10 C2L9
C2L8
C2L7
C2L6
C2L5
C2L4
C2L3
C2L2
C2L1
C2L0
—
—
—
RW-0 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-0 RW-0 RW-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-24. Channel-2 Critical-Alert Limit Register Field Descriptions
Bit
15-3
2-0
Field
Type
R/W
R/W
Reset
FFFh
0h
Description
C2L12-0
Reserved
Channel-2 critical-alert-limit data bits
Reserved
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8.6.2.11 Channel-2 Warning-Alert Limit Register (address = 0Ah) [reset = 7FF8h]
This register contains the value used to compare to the averaged shunt voltage value of channel 2 to detect a
longer duration overcurrent event.
表8-25. Channel-2 Warning-Alert Limit Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
W2L12 W2L11 W2L10 W2L9 W2L8 W2L7 W2L6 W2L5 W2L4 W2L3 W2L2 W2L1 W2L0
—
—
—
RW-0 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-0 RW-0 RW-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-26. Channel-2 Warning-Alert Limit Register Field Descriptions
Bit
15-3
2-0
Field
Type
R/W
R/W
Reset
FFFh
0h
Description
W2L12-0
Reserved
Channel-2 warning-alert-limit data bits
Reserved
8.6.2.12 Channel-3 Critical-Alert Limit Register (address = 0Bh) [reset = 7FF8h]
This register contains the value used to compare to each shunt voltage conversion on channel 3 to detect fast
overcurrent events.
表8-27. Channel-3 Critical-Alert Limit Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
C3L12 C3L11 C3L10 C3L9
C3L8
C3L7
C3L6
C3L5
C3L4
C3L3
C3L2
C3L1
C3L0
—
—
—
RW-0 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-0 RW-0 RW-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-28. Channel-3 Critical-Alert Limit Register Field Descriptions
Bit
15-3
2-0
Field
Type
R/W
R/W
Reset
FFFh
0h
Description
C3L12-0
Reserved
Channel-3 critical-alert-limit data bits
Reserved
8.6.2.13 Channel-3 Warning-Alert Limit Register (address = 0Ch) [reset = 7FF8h]
This register contains the value used to compare to the averaged shunt voltage value of channel 3 to detect a
longer duration overcurrent event.
表8-29. Channel-3 Warning-Alert Limit Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
W3L12 W3L11 W3L10 W3L9 W3L8 W3L7 W3L6 W3L5 W3L4 W3L3 W3L2 W3L1 W3L0
—
—
—
RW-0 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-0 RW-0 RW-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-30. Channel-3 Warning-Alert Limit Register Field Descriptions
Bit
15-3
2-0
Field
Type
R/W
R/W
Reset
FFFh
0h
Description
W3L12-0
Reserved
Channel-3 warning-alert limit data bits
Reserved
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8.6.2.14 Shunt-Voltage Sum Register (address = 0Dh) [reset = 00h]
This register contains the sum of the single conversion shunt voltages of the selected channels based on the
summation control bits 12, 13, and 14 in the Mask/Enable register.
This register is updated with the most recent sum following each complete cycle of all selected channels. The
Shunt-Voltage Sum register LSB value is 40 µV.
表8-31. Shunt-Voltage Sum Register
15
SIGN SV13 SV12 SV11 SV10
R-0 R-0 R-0 R-0 R-0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SV9
R-0
SV8
R-0
SV7
R-0
SV6
R-0
SV5
R-0
SV4
R-0
SV3
R-0
SV2
R-0
SV1
R-0
SV0
R-0
—
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-32. Shunt-Voltage Sum Register Field Descriptions
Bit
Field
Type
Reset
Description
15
SIGN
R
0h
Sign bit.
0 = positive number
1 = negative number in twos complement format
Shunt-voltage sum data bits
Reserved
14-1
0
SV13-0
R
R
0h
0h
Reserved
8.6.2.15 Shunt-Voltage Sum-Limit Register (address = 0Eh) [reset = 7FFEh]
This register contains the value that is compared to the Shunt-Voltage Sum register value following each
completed cycle of all selected channels to detect for system overcurrent events. The Shunt-Voltage Sum-Limit
register LSB value is 40 µV.
表8-33. Shunt-Voltage Sum-Limit Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SIGN SVL13 SVL12 SVL11 SVL10 SVL9 SVL8 SVL7 SVL6 SVL5 SVL4 SVL3 SVL2 SVL1 SVL0
—
RW-0 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-34. Shunt-Voltage Sum-Limit Register Field Descriptions
Bit
Field
Type
Reset
Description
15
SIGN
R
0h
Sign bit.
0 = positive number
1 = negative number in twos complement format
14-1
0
SVL13-0
Reserved
R
R
0h
0h
Shunt-voltage sum-limit data bits
Reserved
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8.6.2.16 Mask/Enable Register (address = 0Fh) [reset = 0002h]
This register selects which function is enabled to control the Critical alert and Warning alert pins, and how each
warning alert responds to the corresponding channel. Read the Mask/Enable register to clear any flag results
present. Writing to this register does not clear the flag bit status. To make sure that there is no uncertainty in the
warning function setting that resulted in a flag bit being set, the Mask/Enable register should be read from to
clear the flag bit status before changing the warning function setting.
表8-35. Mask/Enable Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SCC1 SCC2 SCC3 WEN
CEN
CF1
CF2
CF3
SF
WF1
WF2
WF3
PVF
TCF
CVRF
—
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-1 RW-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-36. Mask/Enable Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
15
Reserved
0h
Reserved
14-12 SCC1-3
0h
Summation channel control. These bits determine which shunt voltage measurement
channels are enabled to fill the Shunt-Voltage Sum register. The selection of these bits
does not impact the individual channel enable or disable status, or the corresponding
channel measurements. The corresponding bit is used to select if the channel is used
to fill the Shunt-Voltage Sum register.
0 = Disabled (default)
1 = Enabled
11
10
9-7
6
WEN
CEN
CF1-3
SF
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
Warning alert latch enable. These bits configure the latching feature of the Warning
alert pin.
0 = Transparent (default)
1 = Latch enabled
Critical alert latch enable. These bits configure the latching feature of the Critical alert
pin.
0 = Transparent (default)
1 = Latch enabled
Critical-alert flag indicator. These bits are asserted if the corresponding channel
measurement has exceeded the critical alert limit resulting in the Critical alert pin being
asserted. Read these bits to determine which channel caused the critical alert. The
critical alert flag bits are cleared when the Mask/Enable register is read back.
Summation-alert flag indicator. This bit is asserted if the Shunt Voltage Sum register
exceeds the Shunt Voltage Sum Limit register. If the summation alert flag is asserted,
the Critical alert pin is also asserted. The Summation Alert Flag bit is cleared when the
Mask/Enable register is read back.
5-3
WF1-3
Warning-alert flag indicator. These bits are asserted if the corresponding channel
averaged measurement has exceeded the warning alert limit, resulting in the Warning
alert pin being asserted. Read these bits to determine which channel caused the
warning alert. The Warning Alert Flag bits clear when the Mask/Enable register is read
back.
2
1
PVF
TCF
R/W
R/W
0h
Power-valid-alert flag indicator. This bit can be used to be able to determine if the
power valid (PV) alert pin has been asserted through software rather than hardware.
The bit setting corresponds to the status of the PV pin. This bit does not clear until the
condition that caused the alert is removed, and the PV pin has cleared.
11h
Timing-control-alert flag indicator. Use this bit to determine if the timing control (TC)
alert pin has been asserted through software rather than hardware. The bit setting
corresponds to the status of the TC pin. This bit does not clear after it has been
asserted unless the power is recycled or a software reset is issued. The default state
for the timing control alert flag is high.
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表8-36. Mask/Enable Register Field Descriptions (continued)
Bit
Field
CVRF
Type
Reset
Description
0
R/W
0h
Conversion-ready flag. Although the INA3221-Q1 can be read at any time, and the
data from the last conversion are available, the conversion ready bit is provided to help
coordinate single-shot conversions. The conversion bit is set after all conversions are
complete. Conversion ready clears under the following conditions:
1. Writing the Configuration register (except for power-down or disable-mode
selections).
2. Reading the Mask/Enable register.
8.6.2.17 Power-Valid Upper-Limit Register (address = 10h) [reset = 2710h]
This register contains the value used to determine if the power-valid conditions are met. The power-valid
condition is reached when all bus-voltage channels exceed the value set in this limit register. When the power-
valid condition is met, the PV alert pin asserts high to indicate that the INA3221-Q1 has confirmed all bus voltage
channels are above the power-valid upper-limit value. In order for the power-valid conditions to be monitored, the
bus measurements must be enabled through one of the corresponding MODE bits set in the Configuration
register. The power-valid upper-limit LSB value is 8 mV. Power-on reset value is 2710h = 10.000 V.
表8-37. Power-Valid Upper-Limit Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SIGN PVU11 PVU10 PVU9 PVU8 PVU7 PVU6 PVU5 PVU4 PVU3 PVU2 PVU1 PVU0
—
—
—
RW-0 RW-0 RW-1 RW-0 RW-0 RW-1 RW-1 RW-1 RW-0 RW-0 RW-0 RW-1 RW-0 RW-0 RW-0 RW-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-38. Power-Valid Upper-Limit Register Field Descriptions
Bit
Field
Type
Reset
Description
15
SIGN
R/W
0h
Sign bit.
0 = positive number
1 = negative number in twos complement format
14-3
2-0
PVU11-0
Reserved
R/W
R/W
4E2h
0h
Power-valid upper-limit data bits
Reserved
8.6.2.18 Power-Valid Lower-Limit Register (address = 11h) [reset = 2328h]
This register contains the value used to determine if any of the bus-voltage channels drops below the power-
valid lower-limit when the power-valid conditions are met. This limit contains the value used to compare all bus-
channel readings to make sure that all channels remain above the power-valid lower-limit, thus maintaining the
power-valid condition. If any bus-voltage channel drops below the power-valid lower-limit, the PV alert pin pulls
low to indicate that the INA3221-Q1 detects a bus voltage reading below the power-valid lower-limit. In order for
the power-valid condition to be monitored, the bus measurements must be enabled through the mode
(MODE3-1) bits set in the Configuration register. The power-valid lower-limit LSB value is 8 mV. Power-on reset
value is 2328h = 9.000 V.
表8-39. Power-Valid Lower-Limit Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SIGN PVL11 PVL10 PVL9 PVL8 PVL7 PVL6 PVL5 PVL4 PVL3 PVL2 PVL1 PVL0
—
—
—
RW-0 RW-0 RW-1 RW-0 RW-0 RW-0 RW-1 RW-1 RW-0 RW-0 RW-1 RW-0 RW-1 RW-0 RW-0 RW-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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表8-40. Power-Valid Lower-Limit Register Field Descriptions
Bit
Field
Type
Reset
Description
15
SIGN
R/W
0h
Sign bit.
0 = positive number
1 = negative number in twos complement format
14-3
2-0
PVL11-0
R/W
R/W
465h
0h
Power-valid lower-limit data bits
Reserved
Reserved
8.6.2.19 Manufacturer ID Register (address = FEh) [reset = 5449h]
This register contains a factory-programmable identification value that identifies this device as being
manufactured by Texas Instruments. This register distinguishes this device from other devices that are on the
same I2C bus. The contents of this register are 5449h, or TI in ASCII.
表8-41. Manufacturer ID Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
D15
R-0
D14
R-1
D13
R-0
D12
R-1
D11
R-0
D10
R-1
D9
R-0
D8
R-0
D7
R-0
D6
R-1
D5
R-0
D4
R-0
D3
R-1
D2
R-0
D1
R-0
D0
R-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-42. Manufacturer ID Register Field Descriptions
Bit
Field
Type
Reset
Description
15-0
D15-0
R
5449h
Manufacturer ID bits
8.6.2.20 Die ID Register (address = FFh) [reset = 3220]
This register contains a factory-programmable identification value that identifies this device as an INA3221-Q1.
This register distinguishes this device from other devices that are on the same I2C bus. The Die ID for the
INA3221-Q1 is 3220h.
表8-43. Die ID Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
D15
R-0
D14
R-0
D13
R-1
D12
R-1
D11
R-0
D10
R-0
D9
R-1
D8
R-0
D7
R-0
D6
R-0
D5
R-1
D4
R-0
D3
R-0
D2
R-0
D1
R-0
D0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-44. Die ID Register Field Descriptions
Bit
Field
Type
Reset
Description
15-0
D15-0
R
3220h
Die ID bits
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
INA3221 is a three-channel current and bus voltage monitor with I2C/SMBUS-compatible interface. It features
programmable conversion times and averaging modes and offers both critical and warning alerts to detect
multiple programmable out-of-range conditions for each channel.
9.2 Typical Application
The INA3221-Q1 measures the voltage developed across a current-sensing resistor when current passes
through it. The device also measures the bus supply voltage at the IN- pin. Multiple monitoring functions are
supported using four alert pins: Critical, Warning, PV, and TC. Programmable thresholds make sure operation is
within desired operating conditions. This design illustrates the ability of the Critical alert pin to respond to a set
threshold.
图 9-1 illustrates a typical INA3221-Q1 application circuit using all three channels. For best performance, use a
0.1-μF ceramic capacitor for power-supply bypassing, placed as close as possible to the supply and ground
pins. The digital pins (SCL, SDA, Critical, Warning, TC) are connected to supply through pull-up resistors. The
power valid (PV) alert pin is connected to the VPU pin through a pull-up resistor to enable power-valid
monitoring.
Power Supply
(0 V to 26 V)
CBYPASS
0.1 µF
Load 1
VS (Supply
Voltage)
VIN+1
VINœ1
10 kꢀ
Power Supply
(0 V to 26 V)
SDA
SCL
I2C-
and
CH 1
Bus
Voltages 1-3
SMBus-
Compatible
Interface
A0
CH 2
VIN+2
VINœ2
VPU
VS
Shunt
Voltages 1-3
ADC
10 kꢀ
Critical Limit
Alerts 1-3
VPU
Power Valid (PV)
Critical
CH 3
Shunt Voltage
Sum Alerts
Load 2
Warning
Timing Control (TC)
GND
VIN+3
VINœ3
Power Supply
(0 V to 26 V)
Load 3
图9-1. INA3221-Q1 as an Overcurrent Sensor
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9.2.1 Design Requirements
For this design example, use the input parameters shown in 表9-1. All other register settings are default.
表9-1. Design Parameters
DESIGN PARAMETER
Supply voltage, VS
Pull-up resistors
EXAMPLE VALUE
5 V
10 kΩ
Input range
–163.84 to +163.8
Enabled channel
CH1
Operating mode
Shunt voltage, continuous
Average setting
1
Critical alert limit
80 mV
7D0h
Critical Alert Limit register setting
9.2.2 Detailed Design Procedure
This design shows two shunt voltage conversion times in order to demonstrate the difference in the alert
response times. This design generates a critical-alert response when the input voltage exceeds 80 mV on
channel 1. See 表9-1 for all design parameters.
For the first example the shunt voltage conversion time is set to 1.1 ms. When the input signal exceeds 80 mV,
the Critical alert pin pulls low after the conversion cycle completes, indicating an overcurrent condition, as shown
in 图9-2.
For the second example, the conversion time is set to 588 µs, and the response is shown in 图9-3.
9.2.3 Application Curves
图9-2 shows the Critical alert pin response to a shunt voltage overlimit of 80 mV for a conversion time of 1.1 ms.
图9-3 shows the response for the same limit, but with the conversion time reduced to 588 µs.
CRITICAL ALERT
INPUT
LIMIT
CRITICAL ALERT
INPUT
LIMIT
Time (200 ms/div)
Time (100 ms/div)
Configuration register = 4125h, conversion time = 588 µs
Configuration register = 40DDh, conversion time = 588 µs
图9-2. Critical Alert Response for 1.1-ms
图9-3. Critical Alert Response for 588-µs
Conversion Time
Conversion Time
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10 Power Supply Recommendations
The input circuitry of the device can accurately measure signals on common-mode voltages beyond its power
supply voltage, VS. For example, the voltage applied to the VS power supply terminal can be 5 V, whereas the
load power-supply voltage being monitored (the common-mode voltage) on any one of the three channels can
be as high as 26 V. Note also that the device can withstand the full 0-V to 26-V range at the input terminals,
regardless of whether the device has power applied or not. Place the required power-supply bypass capacitors
as close as possible to the supply and ground terminals of the device to ensure stability. A typical value for this
supply bypass capacitor is 0.1 μF. Applications with noisy or high-impedance power supplies may require
additional decoupling capacitors to reject power-supply noise.
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ZHCSEU5C –MARCH 2016 –REVISED MARCH 2021
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11 Layout
11.1 Layout Guidelines
Connect the input pins (IN+ and IN–) of all the used channels to the sensing resistor using a Kelvin connection
or a 4-wire connection. These connection techniques ensure that only the current-sensing resistor impedance is
detected between the input pins. Poor routing of the current-sensing resistor commonly results in additional
resistance present between the input pins. Given the very low ohmic value of the current-sensing resistor, any
additional high-current carrying impedance causes significant measurement errors. Place the power-supply
bypass capacitor as close as possible to the supply and ground pins.
11.2 Layout Example
Timing Control Output
Connect to
bus power-
supply rail
To Bus Power Supply
To Load
IN+1
IN-3
IN-1
IN+3
GND
VS
Connect
to VPU
PV
Supply
Bypass
Capacitor
Critical
Output
Critical
To Bus Power
Supply
To Load
Via to Ground Plane
Via to Power Plane
I2C- and SMBUS-
Compatible Interface
Warning Output
图11-1. Layout Example
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
• For INA3221 evaluation module (EVM), go to www.ti.com/tool/INA3221EVM
12.2 Documentation Support
12.2.1 Related Documentation
• INA3221EVM User Guide, SBOU126
12.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
12.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
INA3221AQRGVRQ1
ACTIVE
VQFN
RGV
16
2500 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
I32
21Q1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
INA3221AQRGVRQ1
VQFN
RGV
16
2500
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VQFN RGV 16
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 33.0
INA3221AQRGVRQ1
2500
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGV 16
4 x 4, 0.65 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224748/A
www.ti.com
PACKAGE OUTLINE
RGV0016A
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.15
3.85
A
B
PIN 1 INDEX AREA
4.15
3.85
C
1.0
0.8
SEATING PLANE
0.08 C
0.05
0.00
2.16 0.1
2X 1.95
SYMM
(0.2) TYP
5
8
(0.37) TYP
EXPOSED
THERMAL PAD
9
4
SYMM
2X 1.95
17
2.16 0.1
12X 0.65
1
12
PIN 1 ID
0.38
16X
0.23
13
16
0.1
C A B
0.65
0.45
16X
0.05
4219037/A 06/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGV0016A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.16)
SYMM
SEE SOLDER MASK
DETAIL
16
13
16X (0.75)
12
1
16X (0.305)
12X (0.65)
17
SYMM
(0.83)
(3.65)
4
9
(R0.05) TYP
(
0.2) TYP
VIA
5
8
(0.83)
(3.65)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
SOLDER MASK DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219037/A 06/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGV0016A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.58) TYP
13
16
16X (0.75)
1
12
16X (0.305)
(0.58) TYP
(3.65)
17
SYMM
12X (0.65)
4X (0.96)
4
9
(R0.05) TYP
8
5
4X (0.96)
SYMM
(3.65)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
EXPOSED PAD 17
79% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4219037/A 06/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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