INA333SKGD2 [TI]

Micro-Power, Zero-Drift, Rail-to-Rail Out Instrumentation Amplifier;
INA333SKGD2
型号: INA333SKGD2
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

Micro-Power, Zero-Drift, Rail-to-Rail Out Instrumentation Amplifier

放大器
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INA333-HT  
www.ti.com  
SBOS514 MARCH 2010  
Micro-Power, Zerø-Drift, Rail-to-Rail Out  
Instrumentation Amplifier  
Check for Samples: INA333-HT  
1
FEATURES  
SUPPORTS EXTREME TEMPERATURE  
APPLICATIONS  
2
Low Offset Voltage: 25 mV (max at 25°C),  
G 100  
Controlled Baseline  
One Assembly/Test Site  
One Fabrication Site  
Available in Extreme (–55°C/210°C)  
Temperature Range(1)  
Low Drift: 0.2 mV/°C, G 1000  
Low Noise: 55 nV/Hz, G 100  
High CMRR: 100 dB (min at 25°C), G 10  
Supply Range: +1.8 V to +5.5 V  
Input Voltage: (V–) +0.1 V to (V+) –0.1 V  
Output Range: (V–) +0.05 V to (V+) –0.05V  
Low Quiescent Current: 198 mA  
RFI Filtered Inputs  
Extended Product Life Cycle  
Extended Product-Change Notification  
Product Traceability  
Texas Instruments' high temperature products  
utilize highly optimized silicon (die) solutions  
with design and process enhancements to  
maximize performance over extended  
temperatures.  
APPLICATIONS  
Down-Hole Drilling  
High Temperature Environments  
(1) Custom temperature ranges available  
DESCRIPTION  
The INA333 is a low-power, precision instrumentation amplifier offering excellent accuracy. The versatile 3-op  
amp design, small size, and low power make it ideal for a wide range of portable applications.  
A single external resistor sets any gain from 1 to 1000. The INA333 is designed to use an industry-standard gain  
equation: G = 1 + (100k/RG).  
The INA333 provides very low offset voltage (25 mV at 25°C, G 100), excellent offset voltage drift (0.2 mV/°C,  
G 100), and high common-mode rejection (100 dB at 25°C, G 10). It operates with power supplies as low as  
1.8 V (±0.9V), and quiescent current is only 50 mA—ideal for battery-operated systems. Using autocalibration  
techniques to ensure excellent precision over the extended industrial temperature range, the INA333 also offers  
exceptionally low noise density (55 nV/Hz) that extends down to dc.  
The INA333 is is specified over the TA = –55°C to +210°C temperature range.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2010, Texas Instruments Incorporated  
SBOS514 MARCH 2010  
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V+  
7
2
1
VIN-  
RFI Filtered Inputs  
150kW  
150kW  
A1  
RFI Filtered Inputs  
50kW  
6
5
VOUT  
A3  
RG  
50kW  
8
3
RFI Filtered Inputs  
RFI Filtered Inputs  
150kW  
150kW  
REF  
A2  
VIN+  
INA333  
4
100kW  
V-  
G = 1 +  
RG  
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with  
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.  
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more  
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.  
ORDERING INFORMATION(1)  
TA  
PACKAGE(2)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING  
NA  
KGD  
JD  
INA333SKGD1  
–55°C to 210°C  
INA333SJD  
INA333SJD  
INA333SHKJ  
HKJ  
INA333SHKJ  
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI  
web site at www.ti.com.  
(2) Package drawings, standard packaging quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/packaging.  
ABSOLUTE MAXIMUM RATINGS(1)  
INA333  
+7  
UNIT  
V
Supply voltage  
Analog input voltage range(2)  
Output short-circuit(3)  
(V–) – 0.3 to (V+) + 0.3  
V
Continuous  
Operating temperature range, TA  
Storage temperature range, TSTG  
Junction temperature, TJ  
–55 to +210  
–65 to +210  
+210  
°C  
°C  
°C  
V
Human body model (HBM)  
4000  
ESD rating  
Charged device model (CDM)  
Machine model (MM)  
1000  
V
200  
V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may  
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond  
those specified is not implied.  
(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.3V beyond the supply rails should  
be current limited to 10mA or less.  
(3) Short-circuit to ground.  
2
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PIN CONFIGURATIONS  
JD OR HKJ PACKAGE  
MSOP-8  
(TOP VIEW)  
RG  
VIN-  
VIN+  
V-  
RG  
1
2
3
4
8
7
6
5
V+  
VOUT  
REF  
INA333  
BARE DIE INFORMATION  
BACKSIDE  
POTENTIAL  
BOND PAD  
METALLIZATION COMPOSITION  
DIE THICKNESS  
15 mils.  
BACKSIDE FINISH  
Silicon with backgrind  
V-  
Al-Si-Cu (0.5%)  
Origin  
a
c
b
d
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Table 1. Bond Pad Coordinates in Microns  
DISCRIPTION  
PAD NUMBER  
a
b
c
d
RG  
VIN-  
VIN+  
NC  
1
2
3
4
5
6
7
8
9
250  
1604.8  
1300  
978.5  
748.65  
300  
326  
1680.8  
1376  
1054.5  
824.65  
376  
21.2  
97.2  
21.2  
97.2  
21.2  
97.2  
V-  
31.3  
107.3  
1148.15  
1375.8  
1365.7  
1147  
REF  
VOUT  
V+  
1072.15  
1299.8  
1289.7  
1071  
21.2  
97.2  
216.2  
700  
292.2  
776  
RG  
1604.8  
1680.8  
RG  
RG  
VIN-  
VIN+  
NC  
V+  
V-  
VOUT  
REF  
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THERMAL CHARACTERISTICS FOR JD PACKAGE  
over operating free-air temperature range (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
High-K board(2), no airflow  
MIN  
TYP  
64.9  
83.4  
27.9  
6.49  
MAX  
UNIT  
qJA  
Junction-to-ambient thermal resistance(1)  
°C/W  
No airflow  
qJB  
qJC  
Junction-to-board thermal resistance  
Junction-to-case thermal resistance  
High-K board without underfill  
°C/W  
°C/W  
(1) The intent of qJA specification is solely for a thermal performance comparison of one package to another in a standardized environment.  
This methodolgy is not meant to and will not predict the performance of a package in an application-specific environment.  
(2) JED51-7, high effective thermal conductivity test board for leaded surface mount packages.  
THERMAL CHARACTERISTICS FOR HKJ PACKAGE  
over operating free-air temperature range (unless otherwise noted)  
PARAMETER  
MIN  
TYP  
MAX  
5.7  
UNIT  
Junction-to-case thermal resistance (to bottom of case)  
Junction-to-case thermal resistance (to top of case lid - as if formed dead bug)  
qJC  
°C/W  
13.7  
ELECTRICAL CHARACTERISTICS: VS = +1.8 V to +5.5 V  
At TA = +25°C, RL = 10k, VREF = VS/2, and G = 1, unless otherwise noted.  
TA = –55°C to +125°C  
TA = +210°C  
TYP  
PARAMETER  
INPUT(1)  
TEST CONDITIONS  
MIN  
TYP  
MAX  
MIN  
MAX  
UNIT  
Offset voltage,  
RTI(2)  
VOSI  
PSR  
±10 ±25/G  
±25 ±75/G  
±15  
mV  
vs Temperature  
vs Power supply  
Long-term stability  
±0.1 ±0.5/G(3)  
0.2(4)(5)  
2.5(4)  
mV/°C  
mV/V  
1.8 V VS 5.5 V  
±1 ±5/G  
±5 ±15/G  
(6)  
See note  
Turn-on time to specified  
VOSI  
See Typical characteristics  
See Typical characteristics  
Impedance  
Differential  
ZIN  
100 || 3  
100 || 3  
100 || 3  
100 || 3  
G|| pF  
G|| pF  
Common-mode  
ZIN  
Common-mode  
voltage range  
VCM  
VO = 0 V  
(V–) + 0.1  
(V+) – 0.1  
(V–) + 0.1  
(V+) – 0.1 V  
V
Common-mode  
rejection  
CMR  
DC to 60 Hz  
VCM = (V–) + 0.1 V to  
(V+) – 0.1 V  
G = 1  
80  
90  
dB  
dB  
dB  
dB  
VCM = (V–) + 0.1 V to  
(V+) – 0.1 V  
G = 10  
G = 100  
G = 1000  
100  
100  
100  
110  
115  
115  
VCM = (V–) + 0.1 V to  
(V+) – 0.1 V  
110  
113  
VCM = (V–) + 0.1 V to  
(V+) – 0.1 V  
INPUT BIAS CURRENT  
Input bias current  
IB  
±70  
±200  
±1260  
±2044  
pA  
pA/°C  
pA  
vs Temperature  
See Typical Characteristic curve  
±50 ±200  
See Typical Characteristic curve  
See Typical Characteristic curve  
Input offset current  
IOS  
vs Temperature  
See Typical Characteristic curve  
pA/°C  
(1) Total VOS, Referred-to-input = (VOSI) + (VOSO/G).  
(2) RTI = Referred-to-input.  
(3) Temperature drift is measured from –55°C to +125°C.  
(4) G = 1000  
(5) Temperature drift is measured from 125°C to +210°C.  
(6) 300-hour life test at +150°C demonstrated randomly distributed variation of approximately 1 mV.  
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ELECTRICAL CHARACTERISTICS: VS = +1.8 V to +5.5 V (continued)  
At TA = +25°C, RL = 10k, VREF = VS/2, and G = 1, unless otherwise noted.  
TA = –55°C to +125°C  
TA = +210°C  
TYP  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
MIN  
MAX  
UNIT  
INPUT VOLTAGE NOISE  
Input voltage noise  
f = 10 Hz  
eNI  
G = 100, RS = 0 Ω  
42  
40  
50  
2
63  
70  
55  
6
nV/Hz  
nV/Hz  
nV/Hz  
mVPP  
f = 100 Hz  
f = 1 kHz  
f = 0.1Hz to 10 Hz  
Input current noise  
f = 10Hz  
iN  
100  
2
fA/Hz  
f = 0.1Hz to 10Hz  
GAIN  
pAPP  
Gain equation  
Range of gain(7)  
G
1 + (100k/RG)  
1 + (100k/RG)  
V/V  
V/V  
1
1000  
100  
1000  
VS = 5.5 V,  
Gain error  
(V–) + 100mV VO ≤  
(V+) – 100mV  
G = 1  
±0.02  
±0.05  
±0.01  
±0.43  
±0.1  
±0.5  
%
%
%
%
G = 10  
G = 100  
±0.5  
±1.3  
±1.7  
G = 1000  
±1.15  
GAIN (continued)  
Gain vs Temperature  
G = 1  
±1  
±5  
ppm/°C  
ppm/°C  
G > 1(8)  
±15  
±50  
VS = 5.5 V,  
(V–) + 100mV VO  
(V+) – 100mV  
Gain nonlinearity  
G = 1 to 1000  
RL = 10 kΩ  
10  
10  
ppm  
OUTPUT  
Output voltage swing from  
rail(9)  
(9)  
VS = 5.5 V, RL = 10 kΩ  
See note  
50  
185  
mV  
pF  
Capacitive load drive  
500  
500  
Short-circuit  
current  
ISC  
Continuous to common  
–55, +5  
–36, +1  
mA  
FREQUENCY  
RESPONSE  
Bandwidth, –3dB  
Range of gain(7)  
G = 1  
150  
35  
kHz  
kHz  
kHz  
Hz  
G = 10  
G = 100  
3.5  
350  
3.1  
G = 1000  
Slew rate  
G = 1  
300  
SR  
tS  
VS = 5 V, VO = 4 V Step  
0.16  
0.06  
0.25  
0.04  
V/ms  
V/ms  
G = 100  
Settling time to  
0.01%  
G = 1  
VSTEP = 4 V  
VSTEP = 4 V  
35  
32  
ms  
ms  
G = 100  
240  
326  
Settling time to  
0.001%  
tS  
(7) Not recommend gain < 100 for 210°C application.  
(8) Does not include effects of external resistor RG.  
(9) See Typical Characteristics curve, Output Voltage Swing vs Output Current (Figure 31).  
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ELECTRICAL CHARACTERISTICS: VS = +1.8 V to +5.5 V (continued)  
At TA = +25°C, RL = 10k, VREF = VS/2, and G = 1, unless otherwise noted.  
TA = –55°C to +125°C  
TA = +210°C  
PARAMETER  
G = 1  
TEST CONDITIONS  
VSTEP = 4 V  
MIN  
TYP  
60  
MAX  
MIN  
TYP  
55  
MAX  
UNIT  
ms  
G = 100  
VSTEP = 4 V  
500  
52  
530  
28  
ms  
Overload recovery  
REFERENCE INPUT  
RIN  
50% overdrive  
ms  
300  
300  
kΩ  
Voltage range  
POWER SUPPLY  
Voltage range  
Single  
V–  
V+  
V–  
V+  
V
+1.8  
±0.9  
+5.5  
±2.75  
75  
+1.8  
±0.9  
+5.5  
V
V
Dual  
±2.75  
Quiescent current  
vs Temperature  
IQ  
VIN = VS/2  
50  
mA  
mA  
80  
198  
345  
TEMPERATURE RANGE  
Specified temperature  
range  
–55  
–55  
+125  
+125  
–55  
–55  
+210  
+210  
°C  
°C  
Operating temperature  
range  
1000000  
100000  
10000  
1000  
100  
Electromigration Fail Mode  
10  
1
110  
130  
150  
170  
Continous TJ (°C)  
190  
210  
230  
Notes  
1. See datasheet for absolute maximum and minimum recommended operating conditions.  
2. Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package  
interconnect life).  
Figure 1. INA333SKGD1 Operating Life Derating Chart  
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TYPICAL CHARACTERISTICS  
At TA = +25°C, VS = 5V, RL = 10k, VREF = midsupply, and G = 1, unless otherwise noted.  
INPUT VOLTAGE OFFSET DRIFT  
INPUT OFFSET VOLTAGE  
(–40°C to +125°C)  
VS = 5.5V  
VS = 5.5V  
Input Offset Voltage (mV)  
Input Voltage Offset Drift (mV/°C)  
Figure 2.  
Figure 3.  
INPUT VOLTAGE OFFSET DRIFT  
(125°C to +210°C)  
OUTPUT OFFSET VOLTAGE  
VS = 5.5V  
Vs = 5.5V  
Gain = 1000  
Output Offset Voltage (mV)  
Input Voltage Offset Drift (µV/°C)  
Figure 4.  
Figure 5.  
8
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TYPICAL CHARACTERISTICS (continued)  
At TA = +25°C, VS = 5V, RL = 10k, VREF = midsupply, and G = 1, unless otherwise noted.  
OUTPUT VOLTAGE OFFSET DRIFT  
(–40°C to +125°C)  
OFFSET VOLTAGE vs COMMON-MODE VOLTAGE  
0
VS = 5.5V  
VS = 1.8V  
-5  
VS = 5V  
-10  
-15  
-20  
-25  
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0  
VCM (V)  
Output Voltage Offset Drift (mV/°C)  
Figure 6.  
Figure 7.  
0.1Hz TO 10Hz NOISE  
0.1Hz TO 10Hz NOISE  
Gain = 1  
Gain = 100  
Time (1s/div)  
Time (1s/div)  
Figure 8.  
Figure 9.  
SPECTRAL NOISE DENSITY  
NONLINEARITY ERROR  
1000  
100  
10  
1000  
100  
10  
0.012  
0.008  
0.004  
0
G = 1000  
G = 100  
G = 10  
G = 1  
VS = ±2.75V  
Output Noise  
Current Noise  
Input Noise  
-0.004  
-0.008  
-0.012  
2
(Output Noise)  
G
Total Input-Referred Noise =  
(Input Noise)2  
+
1
1
0.1  
1
10  
100  
1k  
10k  
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5  
VOUT (V)  
Frequency (Hz)  
Figure 10.  
Figure 11.  
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TYPICAL CHARACTERISTICS (continued)  
At TA = +25°C, VS = 5V, RL = 10k, VREF = midsupply, and G = 1, unless otherwise noted.  
LARGE SIGNAL RESPONSE  
LARGE-SIGNAL STEP RESPONSE  
Gain = 1  
Gain = 100  
Time (25ms/div)  
Time (100ms/div)  
Figure 12.  
Figure 13.  
SMALL-SIGNAL STEP RESPONSE  
SMALL-SIGNAL STEP RESPONSE  
Gain = 1  
Gain = 100  
Time (10ms/div)  
Time (100ms/div)  
Figure 14.  
Figure 15.  
SETTLING TIME vs GAIN  
STARTUP SETTLING TIME  
10000  
1000  
100  
Gain = 1  
Supply  
VOUT  
0.001%  
0.01%  
0.1%  
10  
Time (50ms/div)  
1
10  
100  
1000  
Gain (V/V)  
Figure 16.  
Figure 17.  
10  
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TYPICAL CHARACTERISTICS (continued)  
At TA = +25°C, VS = 5V, RL = 10k, VREF = midsupply, and G = 1, unless otherwise noted.  
GAIN vs FREQUENCY  
COMMON-MODE REJECTION RATIO  
80  
60  
VS = 5.5V  
G = 1000  
G = 100  
G = 10  
40  
20  
G = 1  
0
-20  
-40  
-60  
10  
100  
1k  
10k  
100k  
1M  
Frequency (Hz)  
CMRR (mV/V)  
Figure 18.  
Figure 19.  
COMMON-MODE REJECTION RATIO vs TEMPERATURE  
COMMON-MODE REJECTION RATIO vs FREQUENCY  
160  
10  
Vs = 2ꢀ.5V  
Vs = 0ꢀꢁV  
8
6
140  
G = 1000  
120  
4
2
0
G = 100  
100  
80  
G = 100  
G = 1000  
-2  
-4  
60  
G = 1  
-6  
40  
20  
G = 10  
-8  
-10  
0
-65 -40 -15 10 35 60 85 110 135 160 185 210  
10  
100  
1k  
10k  
100k  
Temperature (°C)  
Frequency (Hz)  
Figure 20.  
Figure 21.  
TYPICAL COMMON-MODE RANGE vs OUTPUT VOLTAGE  
TYPICAL COMMON-MODE RANGE vs OUTPUT VOLTAGE  
2.5  
5
VS = ±2.5V  
VS = +5V  
2.0  
VREF = 0  
VREF = 0  
4
1.0  
All Gains  
3
All Gains  
0
2
1
0
-1.0  
-2.0  
2.5  
-2.5 -2.0  
-1.0  
0
1.0  
2.0 2.5  
0
1
2
3
4
5
Output Voltage (V)  
Output Voltage (V)  
Figure 22.  
Figure 23.  
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TYPICAL CHARACTERISTICS (continued)  
At TA = +25°C, VS = 5V, RL = 10k, VREF = midsupply, and G = 1, unless otherwise noted.  
TYPICAL COMMON-MODE RANGE vs OUTPUT VOLTAGE  
TYPICAL COMMON-MODE RANGE vs OUTPUT VOLTAGE  
0.9  
1.8  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0
VS = ±0.9V  
VS = +1.8V  
VREF = 0  
0.7  
VREF = 0  
0.5  
0.3  
0.1  
All Gains  
All Gains  
-0.1  
-0.3  
-0.5  
-0.7  
-0.9  
-0.9 -0.7 -0.5 -0.3 -0.1 0.1 0.3  
0.5  
0.7  
0.9  
0
0.2  
0.4  
0.5  
0.8  
1.0 1.2  
1.4  
1.6  
1.8  
Output Voltage (V)  
Output Voltage (V)  
Figure 24.  
Figure 25.  
POSITIVE POWER-SUPPLY REJECTION RATIO  
NEGATIVE POWER-SUPPLY REJECTION RATIO  
160  
160  
VS = 5V  
140  
120  
100  
80  
140  
120  
100  
80  
G = 100  
G = 1000  
G = 1000  
G = 100  
G = 10  
60  
60  
40  
G = 10  
G = 1  
40  
20  
G = 1  
20  
0
0
-20  
1
10  
100  
1k  
10k  
100k  
1M  
0.1  
1
10  
100  
1k  
10k  
100k  
1M  
Frequency (Hz)  
Frequency (Hz)  
Figure 26.  
Figure 27.  
INPUT BIAS CURRENT vs TEMPERATURE  
| INPUT BIAS CURRENT | vs COMMON-MODE VOLTAGE  
200  
1400  
180  
160  
140  
120  
100  
80  
+IB  
-IB  
1200  
1000  
800  
600  
400  
200  
0
60  
Vs = ±ꢀ0ꢁ7V  
Vs = ±±0.V  
VS = 5V  
40  
20  
VS = 1.8V  
-200  
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0  
VCM (V)  
-65 -40 -15 10  
35  
60  
85 110 135 160 185 210  
Temperature (°C)  
Figure 28.  
Figure 29.  
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TYPICAL CHARACTERISTICS (continued)  
At TA = +25°C, VS = 5V, RL = 10k, VREF = midsupply, and G = 1, unless otherwise noted.  
INPUT OFFSET CURRENT vs TEMPERATURE  
OUTPUT VOLTAGE SWING vs OUTPUT CURRENT  
(V+)  
(V+) - 0.25  
(V+) - 0.50  
(V+) - 0.75  
(V+) - 1.00  
(V+) - 1.25  
(V+) - 1.50  
(V+) - 1.75  
150  
100  
50  
VS = ±2.75V  
VS = ±0.9V  
Vs = ±ꢀ0ꢁ7V  
(V-) + 1.75  
(V-) + 1.50  
(V-) + 1.25  
(V-) + 1.00  
(V-) + 0.75  
(V-) + 0.50  
(V-) + 0.25  
(V-)  
0
+125°C  
+25°C  
-40°C  
Vs = ±±0.V  
-50  
0
10  
20  
30  
40  
50  
60  
-65 -40 -15 10 35 60 85 110 135 160 185 210  
IOUT (mA)  
Temperature (°C)  
Figure 30.  
Figure 31.  
QUIESCENT CURRENT vs TEMPERATURE  
QUIESCENT CURRENT vs COMMON-MODE VOLTAGE  
80  
250  
200  
150  
100  
50  
70  
VS = 5V  
60  
50  
40  
Vs =  
5V  
VS = 1.8V  
30  
20  
10  
0
Vs = 1.8V  
0
0
1.0  
2.0  
3.0  
4.0  
5.0  
-65 -40 -15 10 35 60 85 110 135 160 185 210  
VCM (V)  
Temperature (°C)  
Figure 32.  
Figure 33.  
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APPLICATION INFORMATION  
Application information below is provided for  
commercial temperature as a reference and not for  
high temperature.  
SETTING THE GAIN  
Gain of the INA333 is set by a single external  
resistor, RG, connected between pins 1 and 8. The  
value of RG is selected according to Equation 1:  
It is not recommonded to use gain < 100 for the high  
temperature (210°C) application. A filter is needed  
between Pin 1 and Pin 9 for gain = 100 and  
gain = 1000 in 210°C application. Recommended  
resistor value is 3.5 kΩ and capacitor value is 10 nF.  
G = 1 + (100 k/RG)  
(1)  
(1)  
Table 2 lists several commonly-used gains and  
resistor values. The 100 kterm in Equation 1  
comes from the sum of the two internal feedback  
resistors of A1 and A2. These on-chip resistors are  
laser trimmed to accurate absolute values. The  
accuracy and temperature coefficient of these  
resistors are included in the gain accuracy and drift  
specifications of the INA333.  
Figure 34 shows the basic connections required for  
operation of the INA333. Good layout practice  
mandates the use of bypass capacitors placed close  
to the device pins as shown.  
The output of the INA333 is referred to the output  
reference (REF) terminal, which is normally  
grounded. This connection must be low-impedance to  
assure good common-mode rejection. Although 15 Ω  
or less of stray resistance can be tolerated while  
maintaining specified CMRR, small stray resistances  
of tens of ohms in series with the REF pin can cause  
noticeable degradation in CMRR.  
The stability and temperature drift of the external gain  
setting resistor, RG, also affects gain. The contribution  
of RG to gain accuracy and drift can be directly  
inferred from the gain Equation 1. Low resistor values  
required for high gain can make wiring resistance  
important. Sockets add to the wiring resistance and  
contribute additional gain error (possibly an unstable  
gain error) in gains of approximately 100 or greater.  
To ensure stability, avoid parasitic capacitance of  
more than a few picofarads at the RG connections.  
Careful matching of any parasitics on both RG pins  
maintains optimal CMRR over frequency.  
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V+  
0.1mF  
7
2
1
RFI Filter  
RFI Filter  
VIN-  
150kW  
150kW  
A1  
VO = G ´ (VIN+ - VIN-  
)
100kW  
50kW  
G = 1 +  
RG  
6
5
RG  
A3  
50kW  
+
8
3
VO  
Load  
-
RFI Filter  
RFI Filter  
150kW  
150kW  
A2  
VIN+  
Ref  
INA333  
4
0.1mF  
V-  
Also drawn in simplified form:  
VIN-  
RG  
VO  
INA333  
Ref  
VIN+  
Figure 34. Basic Connections  
Table 2. Commonly-Used Gains and Resistor Values  
DESIRED GAIN  
RG ()  
NC(1)  
100k  
NEAREST 1% RG ()  
1
2
NC  
100k  
24.9k  
11k  
5
25k  
10  
11.1k  
5.26k  
2.04k  
1.01k  
502.5  
200.4  
100.1  
20  
5.23k  
2.05  
1k  
50  
100  
200  
500  
1000  
499  
200  
100  
(1) NC denotes no connection. When using the SPICE model, the simulation will not converge unless a resistor is connected to the RG pins;  
use a very large resistor value.  
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INTERNAL OFFSET CORRECTION  
Without a bias current path, the inputs will float to a  
potential that exceeds the common-mode range of  
the INA333, and the input amplifiers will saturate. If  
the differential source resistance is low, the bias  
current return path can be connected to one input  
(see the thermocouple example in Figure 36). With  
higher source impedance, using two equal resistors  
provides a balanced input with possible advantages  
of lower input offset voltage as a result of bias current  
and better high-frequency common-mode rejection.  
The INA333 internal op amps use an auto-calibration  
technique with a time-continuous 350-kHz op amp in  
the signal path. The amplifier is zero-corrected every  
8 ms using a proprietary technique. Upon power-up,  
the amplifier requires approximately 100 ms to  
achieve specified VOS accuracy. This design has no  
aliasing or flicker noise.  
OFFSET TRIMMING  
Most applications require no external offset  
adjustment; however, if necessary, adjustments can  
be made by applying a voltage to the REF terminal.  
Figure 35 shows an optional circuit for trimming the  
output offset voltage. The voltage applied to REF  
terminal is summed at the output. The op amp buffer  
provides low impedance at the REF terminal to  
preserve good common-mode rejection.  
Microphone,  
Hydrophone,  
etc.  
INA333  
47kW  
47kW  
mIN-  
m+  
Thermocouple  
INA333  
RG  
mO  
INA333  
Ref  
100mA  
1/2 REF200  
mIN+  
10kW  
100W  
100W  
OPA333  
10ꢀm  
Adjustꢀent Range  
10kW  
INA333  
100mA  
1/2 REF200  
Center tap provides  
bias current return.  
m-  
Figure 35. Optional Trimming of Output Offset  
Voltage  
Figure 36. Providing an Input Common-Mode  
Current Path  
NOISE PERFORMANCE  
INPUT COMMON-MODE RANGE  
The auto-calibration technique used by the INA333  
results in reduced low frequency noise, typically only  
50 nV/Hz, (G = 100). The spectral noise density can  
be seen in detail in Figure 10. Low frequency noise of  
the INA333 is approximately 1 mVPP measured from  
0.1 Hz to 10 Hz, (G = 100).  
The linear input voltage range of the input circuitry of  
the INA333 is from approximately 0.1 V below the  
positive supply voltage to 0.1 V above the negative  
supply. As a differential input voltage causes the  
output voltage to increase, however, the linear input  
range is limited by the output voltage swing of  
amplifiers A1 and A2. Thus, the linear common-mode  
input range is related to the output voltage of the  
complete amplifier. This behavior also depends on  
supply voltage—see Typical Characteristic curves  
Typical Common-Mode Range vs Output Voltage  
(Figure 22 to Figure 25).  
INPUT BIAS CURRENT RETURN PATH  
The input impedance of the INA333 is extremely  
high—approximately 100 G. However, a path must  
be provided for the input bias current of both inputs.  
This input bias current is typically ±70 pA. High input  
impedance means that this input bias current  
changes very little with varying input voltage.  
Input overload conditions can produce an output  
voltage that appears normal. For example, if an input  
Input circuitry must provide a path for this input bias  
current for proper operation. Figure 36 illustrates  
various provisions for an input bias current path.  
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overload condition drives both input amplifiers to the  
respective positive output swing limit, the difference  
voltage measured by the output amplifier is near  
zero. The output of the INA333 is near 0 V even  
though both inputs are overloaded.  
+3V  
3V  
2V - DV  
RG  
VO  
INA333  
300W  
Ref  
1.5V  
OPERATING VOLTAGE  
2V + DV  
The INA333 operates over a power-supply range of  
+1.8 V to +5.5 V (±0.9 V to ±2.75 V). Supply voltages  
150W  
(1)  
R1  
higher than +7  
V
(absolute maximum) can  
permanently damage the device. Parameters that  
vary over supply voltage or temperature are shown in  
the Typical Characteristics section of this data sheet.  
(1) R1 creates proper common-mode voltage, only for low-voltage  
operation—see the Single-Supply Operation section.  
Figure 37. Single-Supply Bridge Amplifier  
LOW VOLTAGE OPERATION  
The INA333 can be operated on power supplies as  
low as ±0.9 V. Most parameters vary only slightly  
throughout this supply voltage range—see the Typical  
Characteristics section. Operation at very low supply  
voltage requires careful attention to assure that the  
input voltages remain within the linear range. Voltage  
swing requirements of internal nodes limit the input  
common-mode range with low power-supply voltage.  
INPUT PROTECTION  
The input terminals of the INA333 are protected with  
internal diodes connected to the power-supply rails.  
These diodes clamp the applied signal to prevent it  
from damaging the input circuitry. If the input signal  
voltage can exceed the power supplies by more than  
0.3 V, the input signal current should be limited to  
less than 10 mA to protect the internal clamp diodes.  
This current limiting can generally be done with a  
series input resistor. Some signal sources are  
inherently current-limited and do not require limiting  
resistors.  
The  
Typical  
Characteristic  
curves  
Typical  
Common-Mode Range vs Output Voltage (Figure 22  
to Figure 25) show the range of linear operation for  
various supply voltages and gains.  
SINGLE-SUPPLY OPERATION  
GENERAL LAYOUT GUIDELINES  
The INA333 can be used on single power supplies of  
+1.8 V to +5.5 V. Figure 37 illustrates a basic  
single-supply circuit. The output REF terminal is  
connected to mid-supply. Zero differential input  
voltage demands an output voltage of mid-supply.  
Actual output voltage swing is limited to  
approximately 50 mV above ground, when the load is  
referred to ground as shown. The typical  
characteristic curve Output Voltage Swing vs Output  
Current (Figure 31) shows how the output voltage  
swing varies with output current.  
Attention to good layout practices is always  
recommended. Keep traces short and, when  
possible, use a printed circuit board (PCB) ground  
plane with surface-mount components placed as  
close to the device pins as possible. Place a 0.1-mF  
bypass capacitor closely across the supply pins.  
These guidelines should be applied throughout the  
analog circuit to improve performance and provide  
benefits  
such  
as  
reducing  
the  
electromagnetic-interference (EMI) susceptibility.  
With single-supply operation, VIN+ and VIN– must both  
be 0.1V above ground for linear operation. For  
instance, the inverting input cannot be connected to  
ground to measure a voltage connected to the  
noninverting input.  
Instrumentation amplifiers vary in the susceptibility to  
radio-frequency interference (RFI). RFI can generally  
be identified as a variation in offset voltage or dc  
signal levels with changes in the interfering RF signal.  
The INA333 has been specifically designed to  
minimize susceptibility to RFI by incorporating  
passive RC filters with an 8-MHz corner frequency at  
the VIN+ and VIN– inputs. As a result, the INA333  
demonstrates remarkably low sensitivity compared to  
previous generation devices. Strong RF fields may  
continue to cause varying offset levels, however, and  
may require additional shielding.  
To illustrate the issues affecting low voltage  
operation, consider the circuit in Figure 37. It shows  
the INA333 operating from a single 3-V supply. A  
resistor in series with the low side of the bridge  
assures that the bridge output voltage is within the  
common-mode range of the amplifier inputs.  
APPLICATION IDEAS  
Additional application ideas are shown in Figure 38 to  
Figure 41.  
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2.8kW  
VO  
LA  
RG/2  
INA333  
Ref  
RA  
2.8kW  
G = 10  
390kW  
1/2  
OPA2333  
1/2  
10kW  
RL  
OPA2333  
390kW  
Figure 38. ECG Amplifier With Right-Leg Drive  
+VS  
fLPF = 150Hz  
C4  
R1  
100kW  
1/2  
1.06nF  
OPA2333  
RA  
R14  
GTOT = 1kV/V  
1MW  
R7  
+VS  
7
100kW  
+VS  
2
1
GINA = 5  
6
R12  
R6  
+VS  
5kW  
100kW  
R2  
100kW  
LL  
1/2  
RG  
INA333  
OPA2333  
8
3
VOUT  
OPA333  
4
C3  
5
GOPA = 200  
1mF  
R13  
R8  
318kW  
100kW  
+VS  
+VS  
dc  
ac  
R3  
100kW  
LA  
1/2  
1/2  
OPA2333  
Wilson  
OPA2333  
VCENTRAL  
C1  
(RA + LA + LL)/3  
47pF  
fHPF = 0.5Hz  
(provides ac signal coupling)  
1/2 VS  
R5  
390kW  
+VS  
VS = +2.7V to +5.5V  
BW = 0.5Hz to 150Hz  
R9  
+VS  
20kW  
R4  
100kW  
RL  
1/2  
OPA2333  
1/2  
OPA2333  
Inverted  
VCM  
+VS  
R10  
1MW  
1/2 VS  
R11  
C2  
1MW  
0.64mF  
fO = 0.5Hz  
Figure 39. Single-Supply, Very Low Power, ECG Circuit  
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TINA-TI  
Virtual instruments offer users the ability to select  
input waveforms and probe circuit nodes, voltages,  
and waveforms, creating a dynamic quick-start tool.  
(FREE DOWNLOAD SOFTWARE)  
Using TINA-TI SPICE-Based Analog Simulation  
Program with the INA333  
Figure 40 and Figure 41 show example TINA-TI  
circuits for the INA333 that can be used to develop,  
modify, and assess the circuit design for specific  
applications. Links to download these simulation files  
are given below.  
TINA is a simple, powerful, and easy-to-use circuit  
simulation program based on a SPICE engine.  
TINA-TI is a free, fully functional version of the TINA  
software, preloaded with a library of macromodels in  
addition to a range of both passive and active  
models. It provides all the conventional dc, transient,  
and frequency domain analysis of SPICE as well as  
additional design capabilities.  
NOTE: these files require that either the TINA  
software (from DesignSoft) or TINA-TI software be  
installed. Download the free TINA-TI software from  
the TINA-TI folder.  
Available as a free download from the Analog eLab  
Design  
Center,  
TINA-TI  
offers  
extensive  
post-processing capability that allows users to format  
results in a variety of ways.  
VoA1  
1/2 of matched  
monolithic dual  
RELATED PRODUCTS  
NPN transistors  
(example: MMDT3904)  
For monolithic logarithmic amplifiers (such as LOG112 or LOG114) see the link in footnote 1.  
Vout  
2
_
4
U1 INA333  
3
V-  
RG  
2
-
-
R8 10k  
+
1
8
Out  
6
+
1
V
Input I 10n  
Ref  
5
4
+
+
+
VM1  
RG  
V+  
5
U1 OPA335  
U5 OPA369  
+
3
7
Vdiff  
Optional buffer for driving  
SAR converters with  
sampling systems of ³ 33kHz.  
1/2 of matched  
monolithic dual  
NPN transistors  
(example: MMDT3904)  
VoA2  
V1 5  
Rset 2.5M  
uC Vref/2 2.5  
3
1
2
-
+
NOTE: Temperature compensation  
of logging transistors is not shown.  
+
4
5
U6 OPA369  
(1) The following link launches the TI logarithmic amplifiers web page: Logarithmic Amplifier Products Home Page  
Figure 40. Low-Power Log Function Circuit for Portable Battery-Powered Systems  
(Example Glucose Meter)  
To download a compressed file that contains the TINA-TI simulation file for this circuit, click the following link:  
Log Circuit.  
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3V  
R1  
2kW  
RWa  
3W  
EMU21 RTD3  
Pt100 RTD  
-
U2  
OPA333  
RWb  
3W  
+
+
2
VT+  
RTD+  
_
4
U1 INA333  
Out  
VT 25  
3V  
V-  
RG  
VT-  
RTD-  
VDIFF  
1
8
MSP430  
RGAIN  
PGA112  
Mon+ Mon-  
100kW  
Ref  
6
RG  
+
V+  
RWc  
4W  
5
RZERO  
100W  
3
7
Temp (°C)  
+
V
(Volts = °C)  
VREF+  
3V  
VRTD  
RWd  
3W  
RTD Resistance  
(Volts = Ohms)  
+
+
IREF1  
IREF2  
A
A
3V  
VREF  
3V  
VREF  
VREF  
U1 REF3212  
Use BF861A  
T3 BF256A  
S
3V  
Use BF861A  
T1 BF256A  
EN  
In  
OUTF  
OUTS  
+
+
+
+
OPA3331 OPA333  
GNDF GNDS  
U3  
OPA333  
3V  
C7  
-
G
-
470nF  
V4 3  
RSET2  
RSET1  
2.5kW  
2.5kW  
RWa, RWb, RWc, and RWd simulate wire resistance. These resistors are included to show the four-wire sense technique immunity to line  
mismatches. This method assumes the use of a four-wire RTD.  
Figure 41. Four-Wire, 3V Conditioner for a PT100 RTD With Programmable Gain Acquisition System  
To download a compressed file that contains the TINA-TI simulation file for this circuit, click the following link:  
PT100 RTD.  
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PACKAGE OPTION ADDENDUM  
www.ti.com  
2-Apr-2010  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
INA333SHKJ  
INA333SJD  
ACTIVE  
ACTIVE  
ACTIVE  
CFP  
HKJ  
8
8
0
25  
45  
1
TBD  
TBD  
TBD  
Call TI  
POST-PLATE N / A for Pkg Type  
Call TI N / A for Pkg Type  
N / A for Pkg Type  
CDIP SB  
XCEPT  
JD  
INA333SKGD1  
KGD  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 1  
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