INA381A3IDGSR [TI]
具有集成过流比较器的 26V、350kHz 电流检测放大器 | DGS | 10 | -40 to 125;
| 型号： | INA381A3IDGSR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成过流比较器的 26V、350kHz 电流检测放大器 | DGS | 10 | -40 to 125 放大器 比较器 |
| 文件： | 总44页 (文件大小：2877K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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INA381
ZHCSHT3B –DECEMBER 2017–REVISED OCTOBER 2019
具有集成比较器的 INA381 26V 高速电流感应放大器
1 特性
3 说明
1
•
•
共模输入范围：–0.2V 至 +26V
高精度放大器：
INA381 包含 26V 共模电流感应放大器和高速比较
器。该器件通过测量分流电阻器两侧的电压并将该电压
与用户定义的阈值限值（通过比较器基准引脚进行设
置）作比较来检测过流情况。该电流分流监控器可在独
立于电源电压的 –0.2V 至 26V 共模电压范围内测量差
动电压信号。
–
TA = 25°C 时的失调电压
–
–
VCM = 12V 时为 500µV（最大值）
VCM = 0V 时为 150µV（最大值）
–
–
–
失调电压漂移：1µV/°C（最大值）
增益误差：25°C 时为 1%（最大值）
增益误差漂移：20ppm/°C（最大值）
开漏极警报输出可配置为在两种模式下运行：透明或锁
存。在透明模式下，输出状态与输入状态保持一致。在
锁存模式下，警报输出仅在锁存复位时清除。独立比较
器大信号警报响应时间小于 2µs，能够快速检测过流事
件。由 INA381 提供的总系统过电流保护响应时间小于
10µs。
•
•
•
可用放大器增益：
–
–
–
–
INA381A1：20V/V
INA381A2：50V/V
INA381A3：100V/V
INA381A4：200V/V
该器件由 2.7V 至 5.5V 单电源供电，消耗取最大电源
电流为 350µA。该器件具有–40°C 至 +125°C 的工作
温度范围，并采用 8 引脚和 10 引脚 VSSOP 封装。
开漏比较器：
–
–
–
–
迟滞：50mV
传播延迟：400ns（典型值）
通过外部基准电压设置警报阈值
支持透明和锁存模式
器件信息(1)
器件型号
INA381
封装
VSSOP (10)
WSON (8)
封装尺寸（标称值）
3.00mm × 3.00mm
2.00mm × 2.00mm
封装：VSSOP-10 和 WSON-8
2 应用
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
•
•
•
•
•
商用网络和服务器 PSU
商用直流/直流转换器
直流输入 BLDC 电机驱动器
无线电动工具
耳麦、耳机和耳塞
典型应用
VS+
2.7 V to 5.5 V
0 V to 26 V
INA381
10 kW
RPULL-UP
Microcontroller
ADC
IN+
+
VOUT
G = 20, 50,
100, 200
RSENSE
INœ
œ
CMPIN
ALERT
+
-
GPIO
Load
GPIO
GND
RESET
CMPREF
5 V R1
R2
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS848
INA381
ZHCSHT3B –DECEMBER 2017–REVISED OCTOBER 2019
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 17
Applications and Implementation ...................... 19
8.1 Application Information............................................ 19
8.2 Typical Applications ................................................ 25
Power Supply Recommendations...................... 29
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 6
Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 14
8
9
10 Layout................................................................... 30
10.1 Layout Guidelines ................................................. 30
10.2 Layout Example .................................................... 30
11 器件和文档支持 ..................................................... 31
11.1 文档支持................................................................ 31
11.2 接收文档更新通知 ................................................. 31
11.3 支持资源................................................................ 31
11.4 商标....................................................................... 31
11.5 静电放电警告......................................................... 31
11.6 Glossary................................................................ 31
12 机械、封装和可订购信息....................................... 31
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (April 2018) to Revision B
Page
•
•
•
•
•
•
已添加 在数据表中添加了 DGS (VSSOP-8) 封装和相关内容................................................................................................. 1
已添加 失调电压和增益误差特性列表项中添加了 额定 温度................................................................................................... 1
已更改 将响应时间 特性 列表项 500ns 更改成了传播延迟 400ns .......................................................................................... 1
已更改 在 新项目中添加了应用列表项 .................................................................................................................................... 1
Added plus-minus symbol to TYP and MAX values of comparator offset voltage................................................................. 5
已更改 Figure 54 to remove reset connection to supply ...................................................................................................... 30
Changes from Original (December 2017) to Revision A
Page
•
已发布至生产 .......................................................................................................................................................................... 1
2
Copyright © 2017–2019, Texas Instruments Incorporated
INA381
www.ti.com.cn
ZHCSHT3B –DECEMBER 2017–REVISED OCTOBER 2019
5 Pin Configuration and Functions
DGS Package
10-Pin VSSOP
Top View
DSG Package
8-Pin WSON
Top View
IN+
VS+
1
2
3
4
5
10
9
INœ
IN+
VS+
1
2
3
4
8
7
6
5
INœ
VOUT
CMPIN
CMPREF
NC
VOUT
CMPIN
CMPREF
Thermal Pad
ALERT
RESET
GND
8
ALERT
RESET
7
6
Not to scale
Not to scale
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
DGS
DSG
ALERT
3
8
7
3
6
5
Digital output
Analog input
Analog input
Overlimit alert, active low, open-drain output
Signal input to the comparator
CMPIN
CMPREF
Input reference to the comparator
Device ground. Connect the thermal pad to the system ground. See the layout
example in 图 54.
GND
5
—
Ground
IN–
IN+
10
1
8
1
Analog input
Analog input
Connect this pin to the load side of the shunt resistor
Connect this pin to the supply side of the shunt resistor
Not internal connection to device. This pin can be left floating, grounded, or
connected to the supply.
NC
6
4
—
4
—
Transparent or latch mode selection input. See the Alert Modes section for a
detailed description on pin connections.
RESET
Digital input
VOUT
VS+
9
2
7
2
Analog output Current-sense amplifier output voltage
Supply
Power supply: 2.7 V to 5.5 V
Thermal
Pad
Thermal
Pad
Ground reference for the device that is also the thermal pad used to conduct heat
from the device. Tie this pad externally to ground.
—
—
Copyright © 2017–2019, Texas Instruments Incorporated
3
INA381
ZHCSHT3B –DECEMBER 2017–REVISED OCTOBER 2019
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
6
UNIT
VS
Supply voltage
V
(2)
Differential (VIN+) – (VIN–
)
–26
GND – 0.3
GND – 0.3
GND – 0.3
GND – 0.3
GND – 0.3
GND – 0.3
26
VIN+,VIN– Analog inputs (IN+, IN–)
V
V
(3)
Common-mode
26
CMPIN
CMPREF
OUT
(VS) + 0.3
(VS) + 0.3
(VS) + 0.3
(VS) + 0.3
6
VI
Analog input
VO
Analog output
V
V
Digital input
RESET
ALERT
Digital output
V
TJ
Junction temperature
Storage temperature
150
°C
°C
Tstg
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) VIN+ and VIN– are the voltages at the IN+ and IN– pins, respectively.
(3) Input voltage may exceed the voltage shown without causing damage to the device if the current at that terminal is limited to 5 mA.
6.2 ESD Ratings
VALUE
±3000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
–0.2
2.7
NOM
12
MAX
26
UNIT
VCM
VS
Common-mode input voltage
Operating supply voltage
V
V
5
5.5
TA
Operating free-air temperature
–40
125
°C
6.4 Thermal Information
INA381
THERMAL METRIC(1)
DGS (VSSOP)
10 PINS
188.6
DSG (WSON)
UNIT
8 PINS
77
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
78.1
96.5
43.4
5.4
111.0
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
17.5
ΨJB
109.2
43.6
18.8
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2017–2019, Texas Instruments Incorporated
INA381
www.ti.com.cn
ZHCSHT3B –DECEMBER 2017–REVISED OCTOBER 2019
6.5 Electrical Characteristics
at TA = 25°C, VSENSE = VIN+ – VIN– = 10 mV, VS = 5 V, VIN+ = 12 V, and CMPREF = 2 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT
CMRR
Common-mode rejection ratio, RTI(1)
Offset voltage, RTI(1)
VIN+ = 0 V to 26 V, TA= –40ºC to +125ºC
VIN+ = 12 V, VIN– = 12 V
84
100
±100
±25
0.1
dB
±500
±150
1
VOS
μV
VIN+ = 0 V, VIN– = 0 V
dVOS/dT
PSRR
IB
Offset voltage drift, RTI(1)
Power-supply rejection ratio
Input bias current
TA= –40ºC to +125ºC
μV/°C
μV/V
μA
VS = 2.7 V to 5.5 V, TA= –40ºC to +125ºC
VSENSE = 0 mV, IB+, IB–
±8
±40
80
IOS
Input offset current
VSENSE = 0 mV
±0.05
μA
OUTPUT
INA381A1
20
50
INA381A2
G
Gain
V/V
INA381A3
100
INA381A4
200
EG
Gain error
VOUT = 0.5 V to VS – 0.5 V
TA= –40ºC to +125ºC
VOUT= 0.5 V to VS – 0.5 V
No sustained oscillation
±0.1%
1.5
±1%
20
Gain error drift
ppm/°C
nF
Nonlinearity error
Maximum capacitive load
±0.01%
1
VOLTAGE OUTPUT
Swing to VS power-supply rail
RL = 10 kΩ to GND, TA= –40ºC to +125ºC
RL = 10 kΩ to GND, TA= –40ºC to +125ºC
VS – 0.02
VS – 0.05
V
V
VGND
+
VGND +
0.005
Swing to GND(2)
0.0005
FREQUENCY RESPONSE
INA381A1
INA381A2
INA381A3
INA381A4
350
210
150
105
2
BW
Bandwidth
kHz
SR
Slew rate
V/µs
NOISE
Voltage noise density
40
nV/√Hz
COMPARATOR
Propagation delay time, comparator only
CMPIN Input overdrive = 20 mV
0.4
0.4
1
2
Large-signal propagation
delay, comparator only
CMPIN step = 0.5 V to 4.5, VCMPREF = 4 V
tp
µs
Small-signal total alert propogation delay,
comparator and amplifier
Input overdrive = 1 mV
2
3
5
Slew rate limited total alert propagation
delay, comparator and amplifier
VOUT = 0.5 V to 4.5, VCMPREF = 4 V
10
±5
VOS
HYS
VIH
Comparator offset voltage
Hysteresis
±1
50
mV
mV
V
High-level input voltage
Low-level input voltage
Alert low-level output voltage
ALERT pin leakage input current
Digital leakage input current
1.4
0
6
0.4
300
1
VIL
V
VOL
IOL = 3 mA
VOH = 3.3 V
0 ≤ VIN ≤ VS
70
0.1
1
mV
μA
μA
POWER SUPPLY
VSENSE = 10 mV, TA = +25ºC
TA = –40ºC to +125ºC
250
350
450
IQ
Quiescent current
μA
(1) RTI = referred-to-input.
(2) Swing specifications are tested with an overdriven input condition.
Copyright © 2017–2019, Texas Instruments Incorporated
5
INA381
ZHCSHT3B –DECEMBER 2017–REVISED OCTOBER 2019
www.ti.com.cn
6.6 Typical Characteristics
at TA = 25°C, VS = 5 V, VIN+ = 12 V, and alert pullup resistor = 10 kΩ (unless otherwise noted)
D002
D001
Input Offset Voltage (mV)
Input Offset Voltage (mV)
VIN+ = 0 V
VIN+ = 0 V
图 2. Input Offset Voltage Production Distribution
图 1. Input Offset Voltage Production Distribution
(INA381A2)
(INA381A1)
D003
D004
Input Offset Voltage (mV)
Input Offset Voltage (mV)
VIN+ = 0 V
VIN+ = 0 V
图 3. Input Offset Voltage Production Distribution
图 4. Input Offset Voltage Production Distribution
(INA381A3)
(INA381A4)
100
50
A1
A2
A3
A4
0
-50
-100
-50
-25
0
25
50
75
100
125
150
D006
Temperature (èC)
Common-Mode Rejection Ratio (mV/V)
D005
VIN+ = 0 V
图 5. Offset Voltage vs Temperature
图 6. Common-Mode Rejection Production Distribution
(INA381A1)
6
版权 © 2017–2019, Texas Instruments Incorporated
INA381
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ZHCSHT3B –DECEMBER 2017–REVISED OCTOBER 2019
Typical Characteristics (接下页)
at TA = 25°C, VS = 5 V, VIN+ = 12 V, and alert pullup resistor = 10 kΩ (unless otherwise noted)
D007
D008
Common-Mode Rejection Ratio (mV/V)
Common-Mode Rejection Ratio (mV/V)
图 7. Common-Mode Rejection Production Distribution
图 8. Common-Mode Rejection Production Distribution
(INA381A2)
(INA381A3)
10
A1
A2
A3
A4
8
6
4
2
0
-2
-4
-6
-8
-10
-50
-25
0
25
50
75
100
125
150
D009
Temperature (èC)
Common-Mode Rejection Ratio (mV/V)
D010
图 9. Common-Mode Rejection Production Distribution
图 10. Common-Mode Rejection Ratio vs Temperature
(INA381A4)
D011
D012
Gain Error (%)
Gain Error (%)
图 12. Gain Error Production Distribution (INA381A2)
图 11. Gain Error Production Distribution (INA381A1)
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INA381
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www.ti.com.cn
Typical Characteristics (接下页)
at TA = 25°C, VS = 5 V, VIN+ = 12 V, and alert pullup resistor = 10 kΩ (unless otherwise noted)
D013
D014
Gain Error (%)
Gain Error (%)
图 13. Gain Error Production Distribution (INA381A3)
图 14. Gain Error Production Distribution (INA381A4)
50
40
30
20
10
0
0.4
A1
A2
A3
A4
A1
A2
A3
A4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-10
-50
-25
0
25
50
75
100
125
150
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
Temperature (èC)
D015
D016
图 15. Gain Error vs Temperature
图 16. Gain vs Frequency
120
100
80
60
40
20
0
140
120
100
80
A1
A2
A3
A4
60
40
20
10
100
1k 10k
Frequency (Hz)
100k
1M
10
100
1k 10k
Frequency (Hz)
100k
1M
D017
D018
图 17. Power-Supply Rejection Ratio vs Frequency
图 18. Common-Mode Rejection Ratio vs Frequency
8
版权 © 2017–2019, Texas Instruments Incorporated
INA381
www.ti.com.cn
ZHCSHT3B –DECEMBER 2017–REVISED OCTOBER 2019
Typical Characteristics (接下页)
at TA = 25°C, VS = 5 V, VIN+ = 12 V, and alert pullup resistor = 10 kΩ (unless otherwise noted)
VS
VS – 1
VS – 2
120
100
80
60
40
20
0
–40°C
25°C
125°C
GND + 2
GND + 1
GND
-20
0
5
10 15 20 25 30 35 40 45 50 55 60
Output Current (mA)
-5
0
5
10
15
Common-Mode Voltage (V)
20
25
30
D019
D020
Supply voltage = 5 V
图 19. Output Voltage Swing vs Output Current
图 20. Input Bias Current vs Common-Mode Voltage
120
100
80
60
40
20
0
85
84
83
82
81
80
79
78
77
76
75
-20
-5
0
5
10
Common-Mode Voltage (V)
15
20
25
30
-50
-25
0
25
50
75
100
125
150
Temperature (èC)
D021
D022
Supply voltage = 0 V
图 21. Input Bias Current vs Common-Mode Voltage (Both
图 22. Input Bias Current vs Temperature
Inputs, Shutdown)
260
255
250
245
240
235
450
400
350
300
250
200
-75
-50
-25
0
25
50
75
100 125 150
-5
0
5
Common-Mode Voltage (V)
10
15
20
25
30
Temperature (èC)
D023
D025
图 23. Quiescent Current vs Temperature
图 24. Quiescent Current vs Common-Mode Voltage
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INA381
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Typical Characteristics (接下页)
at TA = 25°C, VS = 5 V, VIN+ = 12 V, and alert pullup resistor = 10 kΩ (unless otherwise noted)
100
80
70
60
50
40
30
20
10
10
Time (1 s/div)
100
1k 10k
Frequency (Hz)
100k
1M
D025
D024
图 26. 0.1-Hz to 10-Hz Voltage Noise (Referred-to-Input)
图 25. Input-Referred Voltage Noise vs Frequency
(INA381A3 Devices)
VCM
VOUT
Time (10 ms/div)
Time (25 ms/div)
D026
D027
80-mVPP input step
图 27. Step Response
图 28. Common-Mode Voltage Transient Response
Inverting Input
Output
Noninverting Input
Output
0 V
0 V
Time (250 ms/div)
Time (250 ms/div)
D028
D029
图 29. Inverting Differential Input Overload
图 30. Noninverting Differential Input Overload
10
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INA381
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ZHCSHT3B –DECEMBER 2017–REVISED OCTOBER 2019
Typical Characteristics (接下页)
at TA = 25°C, VS = 5 V, VIN+ = 12 V, and alert pullup resistor = 10 kΩ (unless otherwise noted)
Supply Voltage
Output Voltage
VS
ALERT
VOUT
0 V
Time (5 ms/div)
Time (100 ms/div)
D033
D032
图 31. Start-Up Response
图 32. Brownout Recovery
VSENSE
ALERT
CMPREF
VOUT
CMPIN
ALERT
CMPREF
Time (100 ns)
Time (1 ms/div)
D036
D037
图 33. Comparator Propagation Delay
图 34. VSENSE Voltage Response
280
270
260
250
240
230
220
2.5
2.4
2.3
2.2
2.1
2
A1
A2
A3
A4
1.9
1.8
1.7
1.6
1.5
1.4
-75
-50
-25
0
25
50
75
100 125 150
-75
-50
-25
0
25
50
75
100 125 150
Temperature (èC)
Temperature (èC)
D038
D039
图 35. Comparator Propagation Delay vs Temperature
图 36. Total Propagation Delay vs Temperature
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Typical Characteristics (接下页)
at TA = 25°C, VS = 5 V, VIN+ = 12 V, and alert pullup resistor = 10 kΩ (unless otherwise noted)
140
120
100
80
49.8
49.5
49.2
48.9
48.6
48.3
48
60
47.7
47.4
47.1
46.8
40
20
0
0
1
2
3
4
5
6
7
Low-Level Output Current (mA)
8
9
10
-75
-50
-25
0
25
50
75
100 125 150
Temperature (èC)
D040
D041
图 37. Low-Level Output Voltage vs Low-Level Output
图 38. Hysteresis vs Temperature
Current
RESET
ALERT
Time (5 ms/div)
D042
图 39. Reset and Alert Voltage Response
12
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7 Detailed Description
7.1 Overview
The INA381 is a zero-drift topology, current-sensing amplifier with an integrated comparator that can be used in
both low-side and high-side current-sensing and protection applications. This specially designed, current-sensing
amplifier accurately measures voltages developed across current-sensing resistors (also known as current-shunt
resistors) on common-mode voltages that far exceed the supply voltage powering the device. Current can be
measured on input voltage rails as high as 26 V, and the device can be powered from supply voltages as low as
2.7 V. The device can also withstand the full 26-V common-mode voltage at the input pins when the supply
voltage is removed without causing damage.
The zero-drift topology enables high-precision measurements with maximum input offset voltages as low as
150 µV, and a temperature contribution of only 1 µV/°C over the full temperature range of –40°C to +125°C. The
low total offset voltage of the INA381 enables the use of smaller current-sense resistor values, and allows for
more efficient system operation without sacrificing measurement accuracy due to the smaller input signal.
The device uses a reference input that simplifies setting the corresponding current threshold level to use for out-
of-range comparison. Combining the precision measurement of the current-sense amplifier and the onboard
comparator enables an all-in-one overcurrent detection device. This combination creates a highly-accurate
design that quickly detects out-of-range conditions, and allows the system to take corrective actions to prevent
potential component or system-wide damage.
7.2 Functional Block Diagram
VS+
2.7 V to 5.5 V
0 V to 26 V
INA381
10 kW
RPULL-UP
Microcontroller
IN+
+
VOUT
G = 20, 50,
100, 200
ADC
RSENSE
INœ
œ
CMPIN
ALERT
+
GPIO
GPIO
œ
Load
GND
RESET
CMPREF
5 V R1
R2
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7.3 Feature Description
7.3.1 Wide Input Common-Mode Voltage Range
The INA381 supports input common-mode voltages from –0.2 V to +26 V. As a result of the internal topology, the
common-mode range is not restricted by the power-supply voltage (VS) as long as VS stays within the operational
range of 2.7 V to 5.5 V. As 图 40 shows, the ability to operate with common-mode voltages greater or less than
VS allows the INA381 to be used in high-side, as well as low-side, current-sensing applications.
œ0.2 V to +26 V
Power Supply
IN+
High-side sensing
common-mode voltage (VCM
is bus-voltage dependent.
RSENSE
)
INœ
Load
IN+
Low-side sensing
common-mode voltage (VCM
is always near ground and is
isolated from bus-voltage spikes.
)
RSENSE
INœ
GND
图 40. High-Side and Low-Side Current Sensing
7.3.2 Precise Low-Side Current Sensing
When used in low-side current-sensing applications, the offset voltage of the INA381 is less than 150 µV. The
low offset performance of the device has several benefits. First, the low offset allows the device to be used in
applications that must measure current over a wide dynamic range. In this case, the low offset voltage improves
accuracy when the sense currents are on the low end of the measurement range. Another advantage of low
offset voltage is the ability to sense lower voltage drops across the sense resistor accurately, thus allowing for a
lower-value shunt resistor. Lower-value shunt resistors reduce power loss in the current-sense circuit, and help
improve the power efficiency of the end application.
The gain error of the INA381 is specified to be within 1% of the actual value. As the sensed voltage becomes
much larger than the offset voltage, this gain error becomes the dominant source of error in the current-sense
measurement.
7.3.3 High Bandwidth and Slew Rate
The INA381 supports small-signal bandwidths as high as 350 kHz, and large-signal slew rates of 2 V/µs. The
ability to detect rapid changes in the sensed current, as well as the ability to quickly slew the output, makes the
INA381 a good choice for applications that require a quick response to input current changes. One application
that requires high bandwidth and slew rate is low-side motor control, where the ability to follow rapid changing
current in the motor allows for more accurate control over a wider operating range. Another application that
requires higher bandwidth and slew rates is system fault detection. The integrated comparator within the INA381
is designed to quickly detect when the sense current is out-of-range, and provide a digital output on the ALERT
pin for quicker and faster responses.
14
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Feature Description (接下页)
7.3.4 Alert Output
The ALERT pin is an active-low, open-drain output pulls low when the input conditions are out-of-range. This
open-drain output pin is recommended to include a 10-kΩ pullup resistor to the supply voltage. This open-drain
pin can be pulled up to a voltage beyond the supply voltage, VS, but must not exceed 5.5 V.
图 41 shows the alert output response of the internal comparator. When the output voltage of the amplifier is less
than the reference voltage set on CMPREF, the comparator output is in the default high state. When the amplifier
output voltage exceeds the reference voltage set at the CMPREF pin, the comparator output becomes active and
pulls low. This active low output indicates that the measured signal at the amplifier input has exceeded the
programmed threshold level, indicating an overcurrent or out-of-range condition has occurred. See the Alert
Modes section for more information about how to set the alert output behavior.
6
ALERT
VOUT
5
CMPREF
4
3
2
1
0
-1
Time (2ms/div)
图 41. Overcurrent Alert Response
7.3.5 Adjustable Overcurrent Threshold
The VOUT voltage is the amplified voltage developed across the current-sensing resistor. The signal developed
at the VOUT pin is the input voltage across the IN+ and IN– pins multiplied by the gain of the amplifier. The
INA381 has four gain options, as shown in 图 42: 20 V/V, 50 V/V, 100 V/V, and 200 V/V. If additional hysteresis
is not required, directly connect the VOUT pin to the CMPIN pin.
VS+
2.7 V to 5.5 V
INA381
10 kW
RPULL-UP
Microcontroller
+
G = 20, 50,
VOUT
ADC
100, 200
œ
CMPIN
+
GPIO
œ
ALERT
RESET
GPIO
CMPREF
GND
5 V R1
R2
图 42. Resistor Divider Voltage
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Feature Description (接下页)
The device determines if an overcurrent event is present by comparing the voltage on the CMPIN pin to the
corresponding signal developed at the CMPREF pin. The threshold voltage for the CMPREF pin can be set with
a resistive divider, or by connecting an external voltage source (such as a reference generator device). 图 43
depicts the REF3140 used as an external reference source.
VS+
2.7 V to 5.5 V
INA381
10 kW
RPULL-UP
CMPIN, VOUT
+
4 V
Vs
VOUT
G = 20, 50,
100, 200
œ
ALERT
CMPIN
ALERT
+
œ
VS+
4 V
CMPREF
RESET
CMPREF
GND
4 V
0.2% , 15ppm/°C
REF3140
5 V
图 43. External Reference Voltage
7.3.6 Comparator Hysteresis
The onboard comparator in the INA381 is designed to reduce the possibility of oscillations in the alert output
when the measured signal level is near the overlimit threshold level as a result of noise. When the voltage
(VCMPIN) exceeds the voltage developed at the CMPREF pin, the ALERT pin asserts and pulls low. The output
voltage must drop to less than the CMPREF pin threshold voltage, as shown in 图 44, by the hysteresis level of
50 mV so that the ALERT pin deasserts and returns to the nominal high state. The INA381 is designed with a
hysteresis of 50 mV.
ALERT
Alert
Output
VCMPIN
VCMPREF
VCMPREF œ 50 mV
图 44. Typical Comparator Hysteresis
16
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ZHCSHT3B –DECEMBER 2017–REVISED OCTOBER 2019
7.4 Device Functional Modes
7.4.1 Alert Modes
The device has two output operating modes, transparent and latched, that are selected based on the RESET pin
setting. These modes change how the ALERT pin responds after an alert when the overcurrent condition is
removed.
7.4.1.1 Transparent Output Mode
The device is set to transparent mode when the RESET pin is pulled low, allowing the output alert state to
change and follow the input signal with respect to the programmed alert threshold. For example, when the
differential input signal exceeds the alert threshold, the alert output pin is pulled low. When the differential input
signal drops to less than the alert threshold, the output returns to the default high-output state. A common
implementation using the device in transparent mode is to connect the ALERT pin to a hardware interrupt input
on a microcontroller. When an overcurrent condition is detected and the ALERT pin is pulled low, the controller
interrupt pin detects the output state change and begins making changes to the system operation required to
address the overcurrent condition. Under this configuration, the ALERT pin high-to-low transition is captured by
the microcontroller, and the output returns to the default high state when the overcurrent event is removed.
7.4.1.2 Latch Output Mode
Some applications cannot continuously monitor the state of the output ALERT pin to detect an overcurrent
condition, as described in the Transparent Output Mode section. A typical example of this type of application is a
system that only periodically polls the ALERT pin state to determine if the system is functioning correctly. If the
device is set to transparent mode in this type of application, the state change of the ALERT pin can be missed
when ALERT is pulled low if the out-of-range condition does not appear during one of these periodic polling
events. Latch output mode is specifically intended to accommodate these applications.
As shown in 表 1, the device is placed into the corresponding output mode based on the signal connected to
RESET. The difference between latch mode and transparent mode is how the alert output responds when an
overcurrent event ends. In transparent mode (RESET = low), when the differential input signal drops below the
limit threshold level after the ALERT pin asserts because of an overcurrent event, the state of the ALERT pin
returns to the default high setting to indicate that the overcurrent event is complete.
表 1. Output Mode Settings
OUTPUT MODE
Transparent
Latch
RESET PIN SETTING
RESET = low
RESET = high
In latch mode (RESET = high), when an overlimit condition is detected and the ALERT pin is pulled low, the
ALERT pin does not return to the default high state when the differential input signal drops to less than the alert
threshold level. To clear the alert, the RESET pin must be pulled low for at least 100 ns. If the differential input
signal is less than the alert threshold, pull the RESET pin low to return ALERT to the default high level. If the
input signal exceeds the threshold limit when the RESET pin is pulled low, the ALERT pin remains low. When the
alert condition is detected by the system controller, set the RESET pin back to high to place the device back in
latch mode.
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图 45 shows the latch and transparent modes. In 图 45, when VIN drops to less than the VLIMIT threshold for the
first time, the RESET pin pulls high. With the RESET pin pulled high, the device is set to latch mode so that the
alert output state does not return high when the input signal drops to less than the VLIMIT threshold. Only when
the RESET pin is pulled low does the ALERT pin return to the default high level, thus indicating that the input
signal is below the limit threshold. When the input signal drops to less than the limit threshold for the second
time, the RESET pin is already pulled low. The device is set to transparent mode at this point, and the ALERT
pin is pulled back high when the input signal drops below the alert threshold.
VCPMPREF
VOUT
(VIN+ œ VINœ) × GAIN
0 V
Latch Mode
RESET
Transparent Mode
Alert Clears
ALERT1
Alert Does Not Clear
图 45. Transparent Mode Versus Latch Mode
18
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ZHCSHT3B –DECEMBER 2017–REVISED OCTOBER 2019
8 Applications and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The INA381 is designed to enable easy configuration for detecting overcurrent conditions in an application. This
device is individually targeted towards unidirectional overcurrent detection of a single threshold. However, this
device can also be paired with additional devices and circuitry to create more complex monitoring functional
blocks.
8.1.1 Select a Current-Sensing Resistor
The device measures the differential voltage developed across a resistor when current flows through the
component to determine if the current being monitored exceeds a defined limit. This resistor is commonly
referred to as a current-sensing resistor or a current-shunt resistor, with each term commonly used
interchangeably. The flexible design of the device allows for measuring a wide differential input signal range
across this current-sensing resistor.
Selecting the value of this current-sensing resistor is based primarily on two factors: the required accuracy of the
current measurement and the allowable power dissipation across the current-sensing resistor. Larger voltages
developed across this resistor allow for more accurate measurements to be made. Amplifiers have fixed internal
errors that are largely dominated by the inherent input offset voltage. When the input signal decreases, these
fixed internal amplifier errors become a larger portion of the measurement and increase the uncertainty in the
measurement accuracy. When the input signal increases, the measurement uncertainty is reduced because the
fixed errors are a smaller percentage of the signal being measured. Therefore, the use of larger-value, current-
sensing resistors inherently improves measurement accuracy.
However, a system design trade-off must be evaluated through use of larger input signals for improving the
measurement accuracy. Increasing the current-sense resistor value results in increased power dissipation across
the current-sensing resistor. Increasing the value of the current-shunt resistor increases the differential voltage
developed across the resistor when current passes through the component. This increase in voltage across the
resistor increases the power that the resistor must be able to dissipate. Decreasing the value of the current-shunt
resistor value reduces the power dissipation requirements of the resistor, but increases the measurement errors
resulting from the decreased input signal. Selecting the optimal value for the shunt resistor requires factoring
both the accuracy requirement for the specific application and the allowable power dissipation of this component.
An increasing number of very low ohmic-value resistors are becoming more widely available with values reaching
down as low as 1 mΩ or lower with power dissipations of up to 5 W that enable large currents to be accurately
monitored with sensing resistors.
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Application Information (接下页)
8.1.1.1 Select a Current-Sensing Resistor: Example
In this example, the trade-offs involved in selecting a current-sensing resistor are discussed. This example
requires 5% accuracy for detecting a 10-A overcurrent event under 20 µs where only 250 mW is allowable for the
dissipation across the current-sensing resistor at the full-scale current level. Although the maximum power
dissipation is defined as 250 mW, a lower dissipation is preferred to improve system efficiency. Given the total
error budget of 5%, the INA381 total error is less than 1%. The INA381 is well suited for this application because
up to 1% of error is available to be attributed to the measurement error of the device under these conditions.
As shown in 表 2, the maximum value calculated for the current-sensing resistor with these requirements is 2.5
mΩ. Although this value satisfies the maximum power dissipation requirement of 250 mW, headroom is available
from the 2.5% maximum total overcurrent detection error to reduce the value of the current-sensing resistor and
reduce the power dissipation further. Selecting a 1.5-mΩ, current-sensing resistor value offers a good tradeoff for
reducing the power dissipation in this scenario by approximately 40% and still remaining within the accuracy
region.
表 2. Calculating the Current-Sensing Resistor (RSENSE
)
PARAMETER
EQUATION
VALUE
10
UNIT
A
IMAX
Maximum current
PD_MAX
RSENSE_MAX
VOS
Maximum allowable power dissipation
Maximum allowable RSENSE
Offset voltage, VCM = 12 V
Initial offset voltage error
250
2.5
mW
mΩ
µV
2
PD_MAX / IMAX
500
2%
VOS_ERROR
EG
(VOS / (RSENSE_MAX × IMAX ) × 100
Gain error
1%
√(VOS_ERROR2 + EG
)
2.23%
5%
2
ERRORTOTAL
Total measurement error
Allowable current threshold accuracy
Total system overcurrent response time
Allowable overcurrent response
tp
10
µs
µs
20
20
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ZHCSHT3B –DECEMBER 2017–REVISED OCTOBER 2019
8.1.2 Increase Comparator Hysteresis
The onboard comparator of the device is designed with a hysteresis of 50 mV. The INA381 is designed for the
user to change the hysteresis from a preset value of 50 mV by connecting an external resistor between VOUT
and CMPIN. 图 46 shows a detailed block diagram of adding additional hysteresis.
VS+
2.7 V to 5.5 V
0 V to 26 V
INA381
10 kW
RPULL-UP
IN+
+
VOUT
RHYS
G = 20, 50,
100, 200
RSENSE
VS+
INœ
4 µA
œ
12.5 k
Internal
Hysteresis
Control
CMPIN
ALERT
+
Load
œ
RESET
CMPREF
R2
GND
5 V
R1
图 46. Increase Hysteresis to the Comparator
The default hysteresis is 50 mV. Internal to the comparator, the INA381 has a current source of 4 µA in series
with 12.5 kΩ. The internal current source and hysteresis of the comparator is set by the internal hysteresis
control circuit that is enabled only after ALERT is asserted low. ALERT is asserted low during an overcurrent
condition when the voltage on VOUT exceeds the threshold set on the CMPREF pin. The internal 4-µA
hysteresis circuits are triggered only after ALERT is asserted low.
To increase hysteresis to greater than the default 50 mV, the RHYS resistor must be connected between the
VOUT and CMPIN pins. 公式 1 describes the internal configuration to set the external hysteresis resistor.
VHYS - 4 mA ì12500 W
(
)
RHYS
=
4 mA
where
•
•
VHYS is the desired hysteresis voltage
RHYS is the external resistor on the input of the CMPIN pin
(1)
表 3 lists the external resistors required at the input of the CMPIN pin to set the hysteresis.
表 3. Hysteresis Resistor Selection
HYSTERESIS VOLTAGE
50 mV
EXTERNAL RESISTOR AT THE CMPIN PIN
0 Ω
75 mV
6.25 kΩ
12.5 kΩ
18.75 kΩ
25 kΩ
100 mV
125 mV
150 mV
200 mV
37.5 kΩ
50 kΩ
250 mV
300 mV
62.5 kΩ
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www.ti.com.cn
8.1.3 Operation With Common-Mode Transients Greater Than 26 V
With a small amount of additional circuitry, the INA381 can be used in circuits subject to transients greater than
26 V. Use only Zener diodes or Zener-type transient absorbers (sometimes referred to as transorbs)—any other
type of transient absorber has an unacceptable time delay. Start by adding a pair of resistors as shown in 图 47
as a working impedance for the Zener diode. Keep these resistors as small as possible; most often
approximately 10 Ω. Larger values can be used with an effect on gain that is discussed in the Input Filtering
section. This circuit limits only short-term transients and, therefore, many applications are satisfied with a 10-Ω
resistor along with conventional Zener diodes of the lowest acceptable power rating. This combination uses the
least amount of board space. These diodes can be found in packages as small as SOT-523 or SOD-523.
VS+
2.7 V to 5.5 V
0 V to 26 V
INA381
10 kW
RPULL-UP
< 10 ꢀ
< 10 ꢀ
IN+
+
VOUT
G = 20, 50,
100, 200
RSENSE
INœ
œ
CMPIN
+
Load
œ
ALERT
RESET
GND
5 V R1
CMPREF
R2
图 47. Transient Protection
In the event that low-power Zener diodes do not have sufficient transient absorption capability, use a higher-
power transorb. 图 47 shows that the most package-efficient solution involves using a single transorb and back-
to-back diodes between the device inputs. The most space-efficient solutions are dual, series-connected diodes
in a single SOT-523 or SOD-523 package. In either of the examples provided in 图 47 and 图 48, the total board
area required by the INA381 with all protective components is less than that of an SOIC-8 package, and only
slightly greater than that of a VSSOP-8 package.
VS+
2.7 V to 5.5 V
œ0.2 V to 26 V
INA381
10 kW
RPULL-UP
< 10 ꢀ
IN+
+
G = 20, 50,
VOUT
RSENSE
100, 200
< 10 ꢀ
INœ
œ
CMPIN
+
Load
œ
ALERT
RESET
GND
5 V R1
CMPREF
R2
图 48. Transient Protection Using a Single Transorb and Input Clamps
22
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ZHCSHT3B –DECEMBER 2017–REVISED OCTOBER 2019
8.1.4 Input Filtering
If the INA381 output is connected to a high-impedance input, the device output is the best location to filter, using
a simple RC network from VOUT to GND. Filtering at the output attenuates high-frequency disturbances in the
common-mode voltage, differential input signal, and INA381 power-supply voltage. If filtering at the output is not
possible, or if only the differential input signal needs filtering, a filter can be applied at the input pins of the
device.
External filtering helps reduce the amount of noise that reaches the comparator, and thereby reduces the
likelihood of a false alert. The tradeoff to adding this noise filter is that the alert response time is increased
because both the input signal and noise are filtered. 图 49 shows the implementation of an input filter for the
device.
VS+
2.7 V œ 5.5 V
0 V to 26 V
INA381
10 kW
RPULL-UP
< 10 ꢀ
IN+
+
VOUT
G = 20, 50,
100, 200
CFILTER
RSENSE
INœ
œ
CMPIN
ALERT
< 10 ꢀ
+
œ
Load
GND
RESET
CMPREF
5 V R1
R2
图 49. Input Filter
The addition of external series resistance creates an additional error in the measurement; therefore, the value of
these series resistors must be kept to 10 Ω (or less, if possible) to reduce impact to accuracy. As shown in 图 49,
the internal bias network present at the input pins creates a mismatch in input bias currents when a differential
voltage is applied between the input pins. If additional external series filter resistors are added to the circuit, the
mismatch in bias currents results in a mismatch of voltage drops across the filter resistors. This mismatch
creates a differential error voltage that subtracts from the voltage developed across the shunt resistor. This error
results in a voltage at the device input pins that is different than the voltage developed across the shunt resistor.
Without the additional series resistance, the mismatch in input bias currents has negligible effect on device
operation. 公式 2 is used to calculate the gain error factor that is used with 公式 3 to calculate the percentage
gain error when using external filter resistors.
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www.ti.com.cn
公式 2 shows that the amount of variance in the differential voltage present at the device input relative to the
voltage developed at the shunt resistor is based both on the external series resistance (RF) value as well as
internal input resistor RINT. The reduction of the shunt voltage reaching the device input pins appears as a gain
error when comparing the output voltage relative to the voltage across the shunt resistor. Use 公式 2 to calculate
the expected deviation from the shunt voltage to what is measured at the device input pins:
1250ìRINT
(1250ìRF ) + (1250ìRINT ) + (RF ìRINT
Gain Error Factor =
)
where:
•
•
RINT is the internal input resistor
RF is the external series resistance
(2)
The adjustment factor from 公式 2 including the device internal input resistance shown in 表 4 varies with each
gain version. 表 5 lists each individual device gain error factor.
表 4. Input Resistance
PRODUCT
INA381A1
INA381A2
INA381A3
INA381A4
GAIN
20
RINT (kΩ)
25
10
5
50
100
200
2.5
表 5. Device Gain Error Factor
PRODUCT
SIMPLIFIED GAIN ERROR FACTOR
25000
INA381A1
(21ìRF ) + 25000
10000
INA381A2
INA381A3
INA381A4
(9ìRF ) +10000
1000
RF +1000
2500
(3ìRF ) + 2500
Use 公式 3 to then calculate the gain error that can be expected from the addition of the external series resistors:
Gain Error (%) = 100 - (100 ´ Gain Error Factor)
(3)
For example, using an INA381A2 and the corresponding gain error equation from 表 5, a series resistance of
10 Ω results in a gain error factor of 0.991. The corresponding gain error is then calculated using 公式 3,
resulting in an additional gain error of approximately 0.89% solely because of the external 10-Ω series resistors.
24
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ZHCSHT3B –DECEMBER 2017–REVISED OCTOBER 2019
8.2 Typical Applications
8.2.1 Bidirectional Window Comparator
VS+
2.7 V to 5.5 V
INA381
VS
10 kW
RPULL-UP
IN+
+
VOUT
G = 20, 50,
100, 200
œ
INœ
CMPIN
+
œ0.2 V to +26 V
œ
ALERT
RESET
CMPREF
R1
R2
RSENSE
5 V
VS+
2.7 V to 5.5 V
Load
INA381
10 kW
RPULL-UP
IN+
+
G = 20, 50,
VOUT
INœ 100, 200
œ
CMPIN
ALERT
+
œ
RESET
CMPREF
R3
R4
5 V
图 50. Bidirectional Window Comparator
8.2.1.1 Design Requirements
表 6 lists the parameters for a design example of a high-side INA381 measuring in the forward direction, and one
low-side INA381 measuring in the reverse direction. This example designs for maximum accuracy and also uses
the alert function of both devices.
表 6. Design Parameters
DESIGN PARAMETER
RSENSE
EXAMPLE VALUE
12 mΩ
5 V
Power-supply voltage
Common-mode voltage
Maximum sense current
Small-signal bandwidth
Alert current threshold
20 V
20 A
> 120 kHz
19 A
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8.2.1.2 Detailed Design Procedure
Although the device is only able to measure current through a current-sensing resistor flowing in one direction, a
second INA381 can be used to create a bidirectional monitor. With the input pins of a second device reversed
across the same current-sensing resistor, the second device is now able to detect current flowing in the other
direction relative to the first device; see 图 50. The outputs of each device connect to an AND gate to detect if
either of the limit threshold levels are exceeded. As shown in 表 7, the output of the AND gate is high if neither
overcurrent limit thresholds are exceeded. A low output state of the AND gate indicates that the positive
overcurrent limit or the negative overcurrent limit has been exceeded.
表 7. Bidirectional Overcurrent Output Status
OCP STATUS
OCP+
OUTPUT
0
0
1
OCP–
No OCP
In this scenario, the maximum current expected through the shunt resistor is 20 A in either the forward or reverse
direction. Maximum accuracy is desired; therefore, the shunt resistor is maximized by taking the maximum output
swing divided by the smallest gain and divided by the maximum current. The design parameters used in 表 6
yield a shunt value of 12.3 mΩ. The closest standard 1% and 0.1% device is 12 mΩ, and this value is used by
both INA381 devices.
Because corrective action must be taken when the current exceeds ±19 A, the comparators require a value of
4.56 V (19 A × 0.012 Ω × 20 V/V). In this instance, a voltage divider consisting of two 4.53-kΩ resistors (R1 and
R3) and two 5-kΩ resistors (R2 and R4) off the 5-V rail supply a voltage close to this value. To be certain that
both device alert functions can trigger a single GPIO pin on a microcontroller, both comparator outputs feed into
an AND gate.
8.2.1.3 Application Curve
Positive Limit
0V
Negtive Limit
Time (5 ms/div)
图 51. Bidirectional Operation
26
版权 © 2017–2019, Texas Instruments Incorporated
INA381
www.ti.com.cn
ZHCSHT3B –DECEMBER 2017–REVISED OCTOBER 2019
8.2.2 Solenoid Low-Side Current Sensing
12 V
90 V
Boost
Converter
VS+
5 V
5 V
Gate
Driver
Enable, Disable
INA381
10 kΩ
RPULL-UP
IN+
+
VOUT
5 mꢀ
G = 200
INœ
œ
CMPIN
+
-
ALERT
RESET
GND
CMPREF
R2
R1
5 V
2.5 kΩ 10 kΩ
图 52. Solenoid Low-Side Current-Sensing
8.2.2.1 Design Requirements
表 8 lists the parameters of an application design using the INA381 and ALERT functionality to create a low-side
current-sense amplifier with less than a 20-µs system shutdown.
表 8. Design Parameters
DESIGN PARAMETERS
Power-supply voltage
Low-side current sensing
Mode of operation
EXAMPLE VALUE
5 V
VCM = 0 V
Unidirectional
4.0 A
Maximum current sense threshold
ALERT response time
ALERT pin mode
< 20 µs
Transparent
5 mΩ
RSENSE resistor
Gain option
200 V/V
版权 © 2017–2019, Texas Instruments Incorporated
27
INA381
ZHCSHT3B –DECEMBER 2017–REVISED OCTOBER 2019
www.ti.com.cn
8.2.2.2 Detailed Design Procedure
The INA381 can measure current across a shunt resistor with common-mode voltage ranges from –0.3 V to
+26 V. The INA381 is capable of measuring low-side current sensing allowing enough margin below ground to
accurately measure current through the load. One common application for low-side current sensing is a solenoid
control application. As described in 图 52, a typical high-voltage solenoid application consists of a high-voltage
NMOS transistor, a low-ohmic shunt resistor connected to the source of the NMOS transistor, and a solenoid. A
solenoid is often used for applications that control a relay that triggers an on-off state. As current flows through
the solenoid, the current flowing through the copper windings generate a magnetic field around the iron that can
be used to open or close a relay. Industrial valves, electromechanical relays, and PLC control relays are often
built of solenoids, and the driver circuitry for solenoids are designed discretely, as shown in 图 52.
A microcontroller unit is often used to control the duty cycle of the NMOS switch to control the position of the
solenoid. By controlling the duty cycle of the solenoid driver, the current flowing through the solenoid can be
controlled, which in turn can be used to perform position control. However, for applications that need two states,
on and off, a microcontroller can be expensive and overkill. If a solenoid is located remotely in specific
application, the routing of the current-sense amplifier signal back to the microcontroller can create additional
overhead and often increase the cost of the application. The INA381 has a built-in comparator that can be
programmed to assert an ALERT when the CMPIN signal exceeds the CMPREF threshold signal. The ALERT
signal can be used to feed the ALERT signal back to the gate driver circuitry of the NMOS, which can disable the
NMOS switch to turn the circuit off to protect from damage. Effective impedance of a solenoid is an inductor in
series with a resistance. If the solenoid is prone to damage, the inductor can lose inductance and behave as a
shorted resistor. If not protected, high current can flow through the solenoid and damage the system, causing
permanent failure. The INA381, with an ALERT pin that responds in as fast as 10 µs, can be directly connected
to the NMOS driver to remove power from the solenoid in the event of an overcurrent condition. When the load
current decreases to less than the safe operating limit, the ALERT clears and enables safe operation of the
solenoid. This design example can be used as a guideline to implement the INA381 for a solenoid application.
Based on 公式 4, the design example for the CMPREF voltage is 4 V. The threshold voltage is set using simple
resistor dividers R1 and R2. R1 is set with 2.5 kΩ, and R2 is set with 10 kΩ. This 4-V threshold is set at the
CMPREF pin. When the current exceeds 4 A, voltage on VOUT exceeds 4 V, and the ALERT pin asserts a low
signal indicating a fault detection. The device is configured in transparent mode by connecting the RESET pin to
ground. Because of this configuration, when the current signal falls below 4 A of current, the ALERT pin is pulled
high and resets the fault detection, maintaining safe operation of the solenoid. This example explains a
methodology where a solenoid can be self-protected and triggered based on a set, safe-operating, current
threshold.
In this application, 4 A and higher are considered overcurrent conditions and some corrective action must be
taken to prevent the current from destroying the system. The INA381 offers corrective action through an ALERT
pin that can be tailored for a specific overcurrent condition through the CMPREF pin. To set the proper CMPREF
value, a gain option and an RSENSE value must first be determined. This design example uses a gain of 200 V/V
and an RSENSE value of 5 mΩ. CMPREF is calculated according to 公式 4 in this particular case. This value is
calculated to be approximately 4 V. This value can be achieved through either a voltage divider or LDO. In this
particular instance, the voltage divider was chosen.
CMPREF (V) = [Alert Threshold (A) × Shunt Resistor (Ω) + VOS (V)] × Gain
(4)
28
版权 © 2017–2019, Texas Instruments Incorporated
INA381
www.ti.com.cn
ZHCSHT3B –DECEMBER 2017–REVISED OCTOBER 2019
8.2.2.3 Application Curve
6
5
ALERT
VOUT
CMPREF
4
3
2
1
0
-1
Time (2ms/div)
图 53. Low-Side Sensing Application Curve
9 Power Supply Recommendations
The device input circuitry accurately measures signals on common-mode voltages beyond the power-supply
voltage, VS. For example, the voltage applied to the VS+ power-supply pin can be 5 V, whereas the load power-
supply voltage being monitored (VCM) can be as high as 26 V. The device can withstand the full –0.2-V to +26-V
range at the input pins, regardless of whether the device has power applied or not.
Power-supply bypass capacitors are required for stability and must be placed as closely as possible to the supply
and ground pins of the device. A typical value for this supply bypass capacitor is 0.1 µF. Applications with noisy
or high-impedance power supplies can require additional decoupling capacitors to reject power-supply noise.
版权 © 2017–2019, Texas Instruments Incorporated
29
INA381
ZHCSHT3B –DECEMBER 2017–REVISED OCTOBER 2019
www.ti.com.cn
10 Layout
10.1 Layout Guidelines
•
Place the power-supply bypass capacitor as closely as possible to the supply and ground pins. The
recommended value of this bypass capacitor is 0.1 µF. Add decoupling capacitance to compensate for noisy
or high-impedance power supplies.
•
•
Make sure that the thermal pad and GND are connected to a solid ground plane of the PCB.
Pull up the open-drain output pin to the supply voltage rail through a 10-kΩ pullup resistor.
10.2 Layout Example
RSHUNT
Power Supply
Load
VIA to
Ground
Plane
VIA to
Ground
Plane
10
9
1
2
3
4
IN+
VS+
INœ
CBYPASS
VOUT
CMPIN
CMPREF
8
ALERT
RESET
VIA to
Power
Supply
7
图 54. Recommended Layout for DSG Package
RSHUNT
Power Supply
Load
VIA to
Ground
Plane
10
9
1
2
3
4
IN+
VS+
INœ
CBYPASS
VOUT
CMPIN
CMPREF
N.C.
INA381DGS
8
ALERT
RESET
GND
VIA to
Power
Supply
7
6
5
VIA to Ground
Plane
图 55. Recommended Layout for DGS Package
30
版权 © 2017–2019, Texas Instruments Incorporated
INA381
www.ti.com.cn
ZHCSHT3B –DECEMBER 2017–REVISED OCTOBER 2019
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
请参阅如下相关文档：
•
•
德州仪器 (TI)，《REF31xx 15ppm/°C 最大值、100μA、SOT-23 系列电压基准》数据表
德州仪器 (TI)，《INA381EVM 用户指南》
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2017–2019, Texas Instruments Incorporated
31
PACKAGE OPTION ADDENDUM
www.ti.com
27-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
INA381A1IDGSR
INA381A1IDGST
INA381A1IDSGR
INA381A1IDSGT
INA381A2IDGSR
INA381A2IDGST
INA381A2IDSGR
INA381A2IDSGT
INA381A3IDGSR
INA381A3IDGST
INA381A3IDSGR
INA381A3IDSGT
INA381A4IDGSR
INA381A4IDGST
INA381A4IDSGR
INA381A4IDSGT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
WSON
WSON
VSSOP
VSSOP
WSON
WSON
VSSOP
VSSOP
WSON
WSON
VSSOP
VSSOP
WSON
WSON
DGS
DGS
DSG
DSG
DGS
DGS
DSG
DSG
DGS
DGS
DSG
DSG
DGS
DGS
DSG
DSG
10
10
8
2500 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAUAG | SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
1XM6
1XM6
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
NIPDAUAG | SN
NIPDAU
1HWY
1HWY
1XN6
1XN6
1HXY
1HXY
1XO6
1XO6
1HZY
1HZY
1XP6
1XP6
1I1Y
8
NIPDAU
10
10
8
NIPDAUAG | SN
NIPDAUAG | SN
NIPDAU
8
NIPDAU
10
10
8
NIPDAUAG | SN
NIPDAUAG | SN
NIPDAU
8
NIPDAU
10
10
8
NIPDAUAG | SN
NIPDAUAG | SN
NIPDAU
8
NIPDAU
1I1Y
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
27-Jun-2023
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF INA381 :
Automotive : INA381-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
INA381A1IDGSR
INA381A1IDGST
INA381A1IDSGR
INA381A1IDSGT
INA381A2IDGSR
INA381A2IDGST
INA381A2IDSGR
INA381A2IDSGT
INA381A3IDGSR
INA381A3IDGST
INA381A3IDSGR
INA381A3IDSGT
INA381A4IDGSR
INA381A4IDGSR
INA381A4IDGST
INA381A4IDGST
VSSOP
VSSOP
WSON
WSON
VSSOP
VSSOP
WSON
WSON
VSSOP
VSSOP
WSON
WSON
VSSOP
VSSOP
VSSOP
VSSOP
DGS
DGS
DSG
DSG
DGS
DGS
DSG
DSG
DGS
DGS
DSG
DSG
DGS
DGS
DGS
DGS
10
10
8
2500
250
330.0
330.0
180.0
180.0
330.0
330.0
180.0
180.0
330.0
330.0
180.0
180.0
330.0
330.0
330.0
330.0
12.4
12.4
8.4
5.3
5.3
2.3
2.3
5.3
5.3
2.3
2.3
5.3
5.3
2.3
2.3
5.3
5.3
5.3
5.3
3.4
3.4
2.3
2.3
3.4
3.4
2.3
2.3
3.4
3.4
2.3
2.3
3.4
3.4
3.4
3.4
1.4
1.4
8.0
8.0
4.0
4.0
8.0
8.0
4.0
4.0
8.0
8.0
4.0
4.0
8.0
8.0
8.0
8.0
12.0
12.0
8.0
Q1
Q1
Q2
Q2
Q1
Q1
Q2
Q2
Q1
Q1
Q2
Q2
Q1
Q1
Q1
Q1
3000
250
1.15
1.15
1.4
8
8.4
8.0
10
10
8
2500
250
12.4
12.4
8.4
12.0
12.0
8.0
1.4
3000
250
1.15
1.15
1.4
8
8.4
8.0
10
10
8
2500
250
12.4
12.4
8.4
12.0
12.0
8.0
1.4
3000
250
1.15
1.15
1.4
8
8.4
8.0
10
10
10
10
2500
2500
250
12.4
12.4
12.4
12.4
12.0
12.0
12.0
12.0
1.4
1.4
250
1.4
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jun-2023
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
INA381A4IDSGR
INA381A4IDSGT
WSON
WSON
DSG
DSG
8
8
3000
250
180.0
180.0
8.4
8.4
2.3
2.3
2.3
2.3
1.15
1.15
4.0
4.0
8.0
8.0
Q2
Q2
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
INA381A1IDGSR
INA381A1IDGST
INA381A1IDSGR
INA381A1IDSGT
INA381A2IDGSR
INA381A2IDGST
INA381A2IDSGR
INA381A2IDSGT
INA381A3IDGSR
INA381A3IDGST
INA381A3IDSGR
INA381A3IDSGT
INA381A4IDGSR
INA381A4IDGSR
INA381A4IDGST
INA381A4IDGST
INA381A4IDSGR
INA381A4IDSGT
VSSOP
VSSOP
WSON
WSON
VSSOP
VSSOP
WSON
WSON
VSSOP
VSSOP
WSON
WSON
VSSOP
VSSOP
VSSOP
VSSOP
WSON
WSON
DGS
DGS
DSG
DSG
DGS
DGS
DSG
DSG
DGS
DGS
DSG
DSG
DGS
DGS
DGS
DGS
DSG
DSG
10
10
8
2500
250
366.0
366.0
210.0
210.0
366.0
366.0
210.0
210.0
366.0
366.0
210.0
210.0
366.0
366.0
366.0
366.0
210.0
210.0
364.0
364.0
185.0
185.0
364.0
364.0
185.0
185.0
364.0
364.0
185.0
185.0
364.0
364.0
364.0
364.0
185.0
185.0
50.0
50.0
35.0
35.0
50.0
50.0
35.0
35.0
50.0
50.0
35.0
35.0
50.0
50.0
50.0
50.0
35.0
35.0
3000
250
8
10
10
8
2500
250
3000
250
8
10
10
8
2500
250
3000
250
8
10
10
10
10
8
2500
2500
250
250
3000
250
8
Pack Materials-Page 3
PACKAGE OUTLINE
DGS0010A
VSSOP - 1.1 mm max height
S
C
A
L
E
3
.
2
0
0
SMALL OUTLINE PACKAGE
C
SEATING PLANE
0.1 C
5.05
4.75
TYP
PIN 1 ID
AREA
A
8X 0.5
10
1
3.1
2.9
NOTE 3
2X
2
5
6
0.27
0.17
10X
3.1
2.9
1.1 MAX
0.1
C A
B
B
NOTE 4
0.23
0.13
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.7
0.4
0 - 8
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
www.ti.com
EXAMPLE BOARD LAYOUT
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
(R0.05)
TYP
SYMM
10X (0.3)
1
5
10
SYMM
6
8X (0.5)
(4.4)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221984/A 05/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
SYMM
(R0.05) TYP
10X (0.3)
8X (0.5)
1
5
10
SYMM
6
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221984/A 05/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
DSG 8
2 x 2, 0.5 mm pitch
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224783/A
www.ti.com
PACKAGE OUTLINE
DSG0008A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
0.32
0.18
PIN 1 INDEX AREA
2.1
1.9
0.4
0.2
ALTERNATIVE TERMINAL SHAPE
TYPICAL
0.8
0.7
C
SEATING PLANE
0.05
0.00
SIDE WALL
0.08 C
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
EXPOSED
THERMAL PAD
(DIM A) TYP
0.9 0.1
5
4
6X 0.5
2X
1.5
9
1.6 0.1
8
1
0.32
0.18
PIN 1 ID
(45 X 0.25)
8X
0.4
0.2
8X
0.1
C A B
C
0.05
4218900/E 08/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
(
0.2) VIA
8X (0.5)
TYP
1
8
8X (0.25)
(0.55)
SYMM
9
(1.6)
6X (0.5)
5
4
SYMM
(1.9)
(R0.05) TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218900/E 08/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
8X (0.5)
METAL
8
SYMM
1
8X (0.25)
(0.45)
SYMM
9
(0.7)
6X (0.5)
5
4
(R0.05) TYP
(0.9)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4218900/E 08/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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