INA592_V01 [TI]
INA592 High-Precision, Wide-Bandwidth e-trim⢠Difference Amplifier;
| 型号： | INA592_V01 |
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TEXAS INSTRUMENTS |
| 描述： | INA592 High-Precision, Wide-Bandwidth e-trim⢠Difference Amplifier |
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INA592
SBOS914D – OCTOBER 2018 – REVISED DECEMBER 2020
INA592 High-Precision, Wide-Bandwidth e-trim™ Difference Amplifier
1 Features
3 Description
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G = 1/2 amplifier
G = 2 amplifier
The INA592 device is a low-power, wide bandwidth
difference amplifier consisting of precision
a
operational amplifier (op amp) and a precision resistor
network. Excellent tracking of resistors (TCR)
maintains gain accuracy and common-mode rejection
over temperature. Unique features such as low offset
40 μV (maximum), low offset drift (2 μV/°C maximum)
high slew rate (18 V/μs), and high capacitive load
drive of up to 500 pF make the INA592 a robust, high-
performance difference amplifier for high-voltage
industrial applications. The common-mode range of
the internal op amp extends to the negative supply,
enabling the device to operate in single-supply
applications. The device operates on single (4.5 V to
36 V) or dual supplies (±2.25 V to ±18 V).
Low offset voltage: 40 μV (maximum)
Low offset voltage drift: ±2 μV/°C (maximum)
Low noise: 18 nV/√Hz at 1 kHz
Low gain error: ±0.03% (maximum)
High common-mode rejection: 88 dB (minimum)
Wide bandwidth: 2 MHz GBW
Low quiescent current: 1.1 mA per amplifier
High slew rate: 18 V/μs
High capacitive load drive capability: 500 pF
Wide supply range:
– Single supply: 4.5 V to 36 V
– Dual supply: ±2.25 V to ±18 V
Specified temperature range:
–40°C to +125°C
The difference amplifier is the foundation of many
commonly used circuits. The INA592 provides this
circuit function without using an expensive precision
resistor network.
•
•
Packages: 8-Pin MSOP, SOIC and 10-pin VSON
packages (Preview)
Device Information
2 Applications
PART NUMBER
PACKAGE(1)
SOIC (8) (Preview)
VSSOP (8)
BODY SIZE (NOM)
4.90 mm × 3.91 mm
3.00 mm × 3.00 mm
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AC drive position feedback
Servo drive position feedback
Condition monitoring module (voltage, current)
Power supply module
INA592
VSON (10) (Preview) 3.00 mm × 3.00 mm
(1) For all available packages, see the package option
addendum at the end of the data sheet.
Semiconductor test
VCC
20%
15%
10%
5%
INA592
V+
SENSE
œIN
12 kꢀ
12 kꢀ
6 kꢀ
œ
ADC
16 Bits Out
AIN
OUT
REF
+
6 kꢀ
+IN
Vœ
0
1
2
-40 -32 -24 -16
-8
0
8
16
24
32
40
V
=
ì
-
(V+IN V-IN
)
OUT
Offset Voltage (mV)
Typical Distribution of Offset Voltage (RTO)
G = 1/2, VS = ±18 V
INA592D/DGK in a Differential Input Data
Acquisition Application
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
INA592
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SBOS914D – OCTOBER 2018 – REVISED DECEMBER 2020
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings ....................................... 5
6.2 ESD Ratings .............................................................. 5
6.3 Recommended Operating Conditions ........................5
6.4 Thermal Information ...................................................5
6.5 Electrical Characteristics: G = 1/2 ..............................6
6.6 Electrical Characteristics: G = 2 .................................7
6.7 Typical Characteristics................................................9
7 Detailed Description......................................................24
7.1 Overview...................................................................24
7.2 Functional Block Diagram.........................................24
7.3 Feature Description...................................................24
7.4 Device Functional Modes..........................................24
8 Application and Implementation..................................25
8.1 Application Information............................................. 25
8.2 Typical Application.................................................... 25
9 Power Supply Recommendations................................31
10 Layout...........................................................................31
10.1 Layout Guidelines................................................... 31
10.2 Layout Example...................................................... 32
11 Device and Documentation Support..........................34
11.1 Receiving Notification of Documentation Updates..34
11.2 Support Resources................................................. 34
11.3 Trademarks............................................................. 34
11.4 Electrostatic Discharge Caution..............................34
11.5 Glossary..................................................................34
12 Mechanical, Packaging, and Orderable
Information.................................................................... 34
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (November 2020) to Revision D (December 2020)
Page
•
Added DRC advanced information (preview) package and associated content.................................................1
Changes from Revision B (February 2020) to Revision C (November 2020)
Page
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Added D (SOIC-8) advanced information (preview) package and associated content.......................................1
Deleted input voltage to Absolute Maximum Ratings......................................................................................... 5
Added input current to Absolute Maximum Ratings............................................................................................5
Changed common-mode voltage show correct equation .................................................................................. 6
Added input impedance value for differential and common-mode......................................................................6
Changed common-mode voltage show correct equation................................................................................... 7
Added input impedance for differential and common-mode............................................................................... 7
Changed Fig. 6-39, Positive Output Voltage vs Output Current (sourcing) G = ½, Y-axis unit from µV to V......9
Changes from Revision A (December 2018) to Revision B (February 2020)
Page
•
Changed Figure 79, Pseudoground Generator, output on pin 6 from (V+) / 2 to (V+) / 3.................................28
Changes from Revision * (October 2018) to Revision A (December 2018)
Page
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First release of production-data data sheet ....................................................................................................... 1
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SBOS914D – OCTOBER 2018 – REVISED DECEMBER 2020
Device Comparison Table
DEVICE
DESCRIPTION
GAIN EQUATION
G = 0.5 V/V or 2 V/V
G = 0.2 V/V
INA592 High-precision, wide-bandwidth e-trim™ difference amplifier
INA159 G = 0.2 V differential amplifier for ±10-V to 3-V and 5-V conversion
INA137 Audio differential line receiver ±6 dB (G = 1/2 or 2)
INA132 Low power, single-supply difference amplifier
G = 0.5 V/V or 2 V/V
G = 1 V/V
INA819 35-µV offset, 0.4 µV/°C VOS drift, 8-nV/√ Hz noise, low-power, precision instrumentation amplifier
G = 1 + 50 kΩ / RG
INA821 35-µV offset, 0.4 µV/°C VOS drift, 7-nV/√ Hz noise, high-bandwidth, precision instrumentation amplifier G = 1 + 49.4 kΩ / RG
INA333 25-µV VOS, 0.1 µV/°C VOS drift, 1.8-V to 5-V, RRO, 50-µA IQ, chopper-stabilized INA
PGA280 20-mV to ±10-V programmable gain IA with 3-V or 5-V differential output; analog supply up to ±18 V
PGA112 Precision programmable gain op amp with SPI
G = 1 + 100 kΩ / RG
Digital programmable
Digital programmable
5 Pin Configuration and Functions
REF
1
8
7
6
NC
V+
œ
œIN
2
+
+IN
3
4
OUT
Vœ
5
SENSE
NC = No Connection
Figure 5-1. D (SOIC-8, Preview) and DGK (VSSOP-8) Packages, Top View
–INOP
REF
+INOP
NC
1
2
3
4
5
10
9
V+
Thermal pad
–IN
8
OUT
+IN
V–
7
SENSE
6
NC= No Connection
Figure 5-2. DRC Package 10-Pin VSON With Thermal Pad Top View
Pin Functions
PIN
I/O
DESCRIPTION
DGK, D
(VSSOP, SOIC)
NAME
+IN
DRC (VSON)
12-kΩ resistor to non-inverting terminal of op amp. Used as positive input in G =
½ configuration. Used as reference pin in G = 2 configuration.
3
2
4
3
I
I
12-kΩ resistor to inverting terminal of op amp. Used as negative input in G = ½
configuration. Connect to output in G = 2 configuration.
–IN
+INOP
–INOP
OUT
—
—
6
10
1
I
I
Direct connection to non-inverting terminal of op amp
Direct connection to inverting terminal of op amp
Output
7
O
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Pin Functions (continued)
PIN
I/O
DESCRIPTION
DGK, D
(VSSOP, SOIC)
NAME
REF
DRC (VSON)
6-kΩ resistor to non-inverting terminal of op amp. Used as reference pin in G =
½ configuration. Used as positive input in G = 2 configuration.
1
5
2
6
I
I
6-kΩ resistor to inverting terminal of op amp. Connect to output in G = ½
configuration. Used as negative input in G = 2 configuration.
SENSE
V+
V–
NC
7
4
8
8
5
9
—
—
—
Positive (highest) power supply
Negative (lowest) power supply
No internal connection (can be left floating)
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
36
UNIT
V
Single supply, (V+) to (V–)
V±
Dual supply, (V+) – (V–)
±18
10
IIN
IS
Input current
mA
Output short circuit (to ground)
Operating temperature
Junction temperature
Storage temperature
Continuous
–55
TA
125
125
150
°C
°C
°C
TJ
–55
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Theseare stress ratings
only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under Section 6.3.
Exposure to absolute-maximum-rated conditions for extended periods mayaffect device reliability.
6.2 ESD Ratings
VALUE
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
NOM
MAX
36
UNIT
V
Single supply, VS = (V+)
V±
TA
Supply voltage
Dual supply, VS = (V+) – (V–)
±2.25
–40
±18
125
Specified temperature
°C
6.4 Thermal Information
INA592
THERMAL METRIC
DGK
8 PINS
158
DRC
10 PINS
47.4
D
UNIT
8 PINS
115
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
48.6
78.7
3.9
49.6
52.4
59.2
9.5
21.0
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.8
ψJB
77.3
N/A
20.9
58.3
N/A
RθJC(bot)
5.3
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6.5 Electrical Characteristics: G = 1/2
at TA = 25°C, VS = ±2.25 V to ±18 V, VCM = VOUT = VS / 2, RL = 10 kΩ connected to ground, and REF pin connected to
ground (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
OFFSET VOLTAGE (RTO)(1)
RTO, VS = ±2.25 V to ±3 V, VCM = –3 V
RTO, VS = ±3 V to ±18 V
±14
±14
±40
µV
±40
VOS
Input offset voltage
Input offset voltage
drift
dVOS/dT
PSRR
±0.7
±0.5
±2.0 µV/°C
±5 µV/V
Power-supply
rejection ratio
VS = ±3 V to ±18 V
INPUT VOLTAGE
Common-mode
voltage
3[(V–)+0.1]
–2VREF
VCM
VO = 0 V
3(V+)–2VREF
V
88
82
88
72
100
90
RTO, 3 [(V−) – 0.1 V)]
≤ VCM ≤ 3 [(V+) – 3 V]
TA = –40°C to
+125°C
Common-mode
rejection ratio
CMRR
dB
100
90
RTO, 3 [(V+) – 1.5 V)]
≤ VCM ≤ 3 [(V+))]
TA = –40°C to
+125°C
INPUT IMPEDANCE(2)
zid
Differential
VO = 0 V
24
9
kΩ
kΩ
zic
Common-mode
GAIN
G
Initial
1/2
±0.01
±0.2
1
V/V
%
GE
Gain error
Gain drift(3)
Gain nonlinearity
VO = –10 V to +10 V, VS = ±15 V
VO = –10 V to +10 V, VS = ±15 V
±0.03
±0.5 ppm/°C
ppm
OUTPUT
Positive rail
Negative rail
(V+) – 170
(V−) + 190
(V+) – 220
(V−) + 220
Output votlage
swing
VO
mV
mA
Short-circuit
current
ISC
±65
NOISE
En
Output voltage
noise
f = 0.1 Hz to 10 Hz, RTO
f = 1 kHz, RTO
3
μVpp
Output voltage
noise density
en
18
nV/√Hz
FREQUENCY RESPONSE
Small-signal –3
BW
2.0
MHz
V/µs
dB- bandwidth
SR
tS
Slew rate
18
1
To 0.1% of final value, VO = 10-V step
To 0.01% of final value, VO = 10-V step
Settling time
µs
1.3
Total harmonic
distortion + noise
THD+N
tDR
f = 1 kHz, VO = 2.8 VRMS
0.00038
–116
%
dB
ns
Noise floor, RTO
80-kHz bandwidth, VO = 3.5 VRMS
Overload recovery
time
200
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6.5 Electrical Characteristics: G = 1/2 (continued)
at TA = 25°C, VS = ±2.25 V to ±18 V, VCM = VOUT = VS / 2, RL = 10 kΩ connected to ground, and REF pin connected to
ground (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
POWER SUPPLY
1.1
1.2
1.5
mA
mA
IQ
Quiescent current IO = 0 mA
TA = –40°C to
+125°C
(1) Includes effects of input bias and offset currents of amplifier.
(2) Resistors are ratio matched but have ±20% absolute value.
(3) Specified by wafer test to 95% confidence level.
6.6 Electrical Characteristics: G = 2
at TA = 25°C, VS = ±2.25 V to ±18 V, VCM = VOUT = VS / 2, RL = 10 kΩ connected to ground, and REF pin connected to
ground (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
OFFSET VOLTAGE (RTO)(1)
VS = ±2.25 V to ±3 V,
VCM = –1.5 V
±28
±28
±80
µV
VOS
Input offset voltage
VS = ±3 V to ±18 V
±80
Input offset voltage
drift
dVOS/dT
PSRR
±1.4
±4 µV/°C
Power-supply
rejection ratio
±1
±5 µV/V
INPUT VOLTAGE
Common-mode
voltage
1/2[3(V–)
+0.1]–VREF
VCM
VO = 0 V
1/2[3(V+)–VREF
]
V
82
80
82
65
94
84
94
84
RTO, 1.5 [(V−) – 0.1 V)]
≤ VCM ≤ 1.5 [(V+) – 3 V]
TA = –40°C to
+125°C
Common-mode
rejection ratio
CMRR
dB
RTO, 1.5 [(V+) – 1.5 V)]
≤ VCM ≤ 1.5 (V+)
TA = –40°C to
+125°C
INPUT IMPEDANCE(2)
zid
Differential
VO = 0 V
12
9
kΩ
kΩ
zic
Common-mode
GAIN
G
Initial
2
±0.01
±0.25
1
V/V
%
GE
Gain error
Gain drift(3)
Gain nonlinearity
VO = –10 V to +10 V, VS = ±15 V
VO = –10 V to +10 V, VS = ±15 V
±0.03
±0.5 ppm/°C
ppm
OUTPUT
Positive rail
Negative rail
(V+ ) – 130
(V−) + 140
±65
(V+ ) – 180
(V−) + 180
Output voltage
swing
VO
mV
mA
ISC
Short-circuit current
NOISE
Output voltage
noise
En
en
f = 0.1 Hz to 10 Hz, RTO
f = 1 kHz, RTO
6
μVpp
Output voltage
noise density
36
nV/√Hz
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6.6 Electrical Characteristics: G = 2 (continued)
at TA = 25°C, VS = ±2.25 V to ±18 V, VCM = VOUT = VS / 2, RL = 10 kΩ connected to ground, and REF pin connected to
ground (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
FREQUENCY RESPONSE
Small-signal –3 dB-
bandwidth
BW
0.8
MHz
V/µs
SR
tS
Slew rate
18
1.0
1.7
To 0.1% of final value, VO = 10-V step
To 0.01% of final value, VO = 10-V step
Settling time
µs
Total harmonic
distortion + noise
THD+N
f = 1 kHz, VO = 2.8 VRMS
0.00066
–110
%
dB
ns
Noise floor, RTO
80-kHz bandwidth, VO = 3.5 VRMS
Overload recovery
time
tDR
200
POWER SUPPLY
1.1
1.2
IQ
Quiescent current
IO = 0 mA
mA
1.5
TA = –40°C to
+125°C
(1) Includes effects of input bias and offset currents of amplifier.
(2) Resistors are ratio matched but have ±20% absolute value.
(3) Specified by wafer test to 95% confidence level.
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6.7 Typical Characteristics
at TA = 25°C, VS = ±18 V, VCM =VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, and G = 1/2 (unless otherwise
noted)
Table 6-1. Table of Graphs
DESCRIPTION
Typical Distribution of Offset Voltage (RTO) G= 1/2, VS = ±2.25 V
Typical Distribution of Offset Voltage (RTO) G= 2, , VS = ±2.25 V
Typical Distribution of Offset Voltage (RTO) G= 1/2, , VS = ±18 V
Typical Distribution of Offset Voltage (RTO) G= 2, VS = ±18 V
Typical Distribution of Offset Voltage Drift (RTO) G = 1/2
Typical Distribution of Offset Voltage Drift (RTO) G = 2
Output Offset Voltage vs Temperature G = 1/2
Output Offset Voltage vs Temperature G = 2
FIGURE
Figure 6-1
Figure 6-2
Figure 6-3
Figure 6-4
Figure 6-5
Figure 6-6
Figure 6-7
Figure 6-8
Figure 6-9
Figure 6-10
Figure 6-11
Figure 6-12
Figure 6-13
Figure 6-14
Figure 6-15
Figure 6-16
Figure 6-17
Figure 6-18
Figure 6-19
Figure 6-20
Figure 6-21
Figure 6-22
Figure 6-23
Figure 6-24
Figure 6-25
Figure 6-26
Figure 6-27
Figure 6-28
Figure 6-29
Figure 6-30
Figure 6-31
Figure 6-32
Figure 6-33
Figure 6-34
Figure 6-35
Figure 6-36
Figure 6-37
Figure 6-38
Figure 6-39
Figure 6-40
Figure 6-41
Figure 6-42
Offset Voltage vs Common-Mode Voltage G = 1/2
Offset Voltage vs Common-Mode Voltage G = 2
Input Bias Current vs Temperature G = 1/2 and G = 2
Input Offset Current vs Temperature
Input Bias Current vs Common Mode Voltage G = 1/2
Input Bias Current vs Common Mode Voltage G = 2
Typical CMRR Distribution G = 1/2, VS = ±2.25 V
Typical CMRR Distribution G = 2, VS = ±2.25 V
Typical CMRR Distribution G = 1/2, VS = ±18 V
Typical CMRR Distribution G = 2, VS = ±18 V
CMRR vs Temperature G = 1/2
CMRR vs Temperature G = 2
Common-Mode Rejection Ratio vs Frequency (RTI) G = 1/2 and 2
Maximum Output Voltage vs Frequency
PSRR vs Temperature G = 1/2
PSRR vs Temperature G = 2
PSRR vs Frequency (RTI) G = 1/2
PSRR vs Frequency (RTI) G = 2
Typical Distribution of Gain Error G = 1/2, Vs = ±2.25V
Typical Distribution of Gain Error G = 2, Vs = ±2.25V
Gain Error vs Temperature G = 1 /2
Gain Error vs Temperature G = 2
Closed-Loop Gain vs Frequency G = 1/2
Closed-Loop Gain vs Frequency G = 2
Voltage Noise Spectral Density vs Frequency (RTI) G = 1/2
Voltage Noise Spectral Density vs Frequency (RTI) G = 2
0.1-Hz to 10-Hz RTI Voltage Noise G = 1/2
0.1-Hz to 10-Hz RTI Voltage Noise G = 2
Integrated Output Voltage Noise vs Noise Bandwidth G = 1/2
Integrated Output Voltage Noise vs Noise Bandwidth G = 2
Positive Output Voltage vs Output Current (sourcing) G = 1/2
Positive Output Voltage vs Output Current (sourcing) G = 2
Negative Output Voltage vs Output Current (sinking) G = 1/2
Negative Output Voltage vs Output Current (sinking) G = 2
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6.7 Typical Characteristics
at TA = 25°C, VS = ±18 V, VCM =VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, and G = 1/2 (unless otherwise
noted)
Table 6-1. Table of Graphs (continued)
DESCRIPTION
FIGURE
Settling Time G = 1/2
Settling Time G = 2
Figure 6-43
Figure 6-44
Figure 6-45
Figure 6-46
Figure 6-47
Figure 6-48
Figure 6-49
Figure 6-50
Figure 6-51
Figure 6-52
Figure 6-53
Figure 6-54
Figure 6-55
Figure 6-56
Figure 6-57
Figure 6-58
Figure 6-59
Figure 6-60
Figure 6-61
Figure 6-62
Figure 6-63
Figure 6-64
Figure 6-65
Figure 6-66
Figure 6-67
Figure 6-68
Figure 6-69
Figure 6-70
Figure 6-71
Figure 6-72
Figure 6-73
Large Signal Step Response G = 1/2
Large Signal Step Response G =2
Slew Rate over Temperature
Overload Recovery (Normalized to 0V)
Small-Signal Overshoot vs Capacitive Load G = 1/2
Small-Signal Overshoot vs Capacitive Load G = 2
Small-Signal Step Response G = 1/2
Small-Signal Step Response G = 2
THD+N vs Frequency G = 1/2
THD+N vs Frequency G = 2
THD+N Ratio vs Output Amplitude G = 1/2
THD+N Ratio vs Output Amplitude G = 2
Supply Current vs Temperature G = 1/2
Supply Current vs Temperature G = 2
Supply Current vs Supply Voltage G = 1/2
Supply Current vs Supply Voltage G = 2
Short Circuit Current vs Temperature G = 1/2
Short Circuit Current vs Temperature G = 2
Differential-Mode EMI Rejection Ratio G = 1/2
Differential-Mode EMI Rejection Ratio G = 2
Common-Mode EMI Rejection Ratio G = 1/2
Common-Mode EMI Rejection Ratio G = 2
Input Common-Mode Voltage vs Output Voltage G = 1/2, Bipolar Supply
Input Common-Mode Voltage vs Output Voltage G= 2, Bipolar Supply
Input Common-Mode Voltage vs Output Voltage G = 1/2, 5-V Supply
Input Common-Mode Voltage vs Output Voltage G = 2, 5-V Supply
Input Common-Mode Voltage vs Output Voltage G = 1/2, 36-V Supply
Input Common-Mode Voltage vs Output Voltage G = 2, 36-V Supply
Closed-Loop Output Impedance vs Frequency
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SBOS914D – OCTOBER 2018 – REVISED DECEMBER 2020
6.7 Typical Characteristics
at TA = 25°C, VS = ±18 V, VCM =VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, and G = 1/2 (unless otherwise
noted)
50%
40%
30%
20%
10%
0
50%
40%
30%
20%
10%
0
-40 -32 -24 -16
-8
0
8
16
24
32
40
-80
-60
-40
-20
0
20
40
60
80
Offset Voltage (mV)
Offset Voltage (mV)
N = 470
Mean = 0.82 μV Std. Dev. = 2.91 μV
N = 470
Mean = 1.64 μV Std. Dev. = 5.82 μV
Figure 6-1. Typical Distribution of Offset Voltage (RTO)
G = 1/2, VS = ±2.25 V, VCM = –3 V
Figure 6-2. Typical Distribution of Offset Voltage (RTO)
G = 2, VS = ±2.25 V, VCM = –3 V
20%
15%
10%
5%
20%
15%
10%
5%
0
0
-40 -32 -24 -16
-8
0
8
16
24
32
40
-80
-60
-40
-20
0
20
40
60
80
Offset Voltage (mV)
Offset Voltage (mV)
N = 470
Mean = –5.22 μV Std. Dev. = 8.38 μV
N = 470
Mean = –10.43 μV Std. Dev. = 16.77 μV
Figure 6-3. Typical Distribution of Offset Voltage (RTO)
G = 1/2, VS = ±18 V
Figure 6-4. Typical Distribution of Offset Voltage (RTO)
G = 2, VS = ±18 V
30%
25%
20%
15%
10%
5%
35%
30%
25%
20%
15%
10%
5%
0
0
-2 -1.6 -1.2 -0.8 -0.4
0
0.4 0.8 1.2 1.6
2
-4 -3.2 -2.4 -1.6 -0.8
0
0.8 1.6 2.4 3.2
4
Offset Voltage Drift (mV/èC)
Offset Voltage Drift (mV/èC)
N = 30
Mean = –0.075 μV/°C Std. Dev. = 0.502 μV/°C
N = 30
Mean = –0.325 μV/°C Std. Dev. = 0.887 μV/°C
Figure 6-5. Typical Distribution of Offset Voltage Drift (RTO)
G = 1/2
Figure 6-6. Typical Distribution of Offset Voltage Drift (RTO)
G = 2
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SBOS914D – OCTOBER 2018 – REVISED DECEMBER 2020
6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM =VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, and G = 1/2 (unless otherwise
noted)
100
75
150
100
50
50
25
0
0
-50
-25
-50
-75
-100
-125
-150
-100
-150
-200
-250
-300
-40
-20
0
20
40
Temperature ( C )
60
80
100 120 140
-40
-20
0
20
40
Temperature ( C )
60
80
100 120 140
VS = ±18 V
30 Units
VS = ±18 V
30 Units
Figure 6-7. Output Offset Voltage vs Temperature G = 1/2
Figure 6-8. Output Offset Voltage vs Temperature G = 2
1500
800
600
1000
500
400
200
0
0
-200
-400
-600
-800
-1000
-500
-1000
-1500
-60
-40
-20
0
VCM ( V )
20
40
60
-30 -25 -20 -15 -10 -5
0
VCM ( V )
5
10 15 20 25 30
VS = ±18 V
12 Units
VS = ±18 V
12 Units
Figure 6-9. Offset Voltage vs Common-Mode Voltage G = 1/2
Figure 6-10. Offset Voltage vs Common-Mode Voltage G = 2
1200
50
0
1000
800
600
400
200
0
-50
-100
-150
-200
-250
-300
-350
-400
-450
-500
-550
-200
-40 -20
0
20
40
60
Temperature ( C )
80
100 120 140
-40
-20
0
20
40
60
Temperature ( C )
80
100 120 140
VS = ±18 V
Figure 6-12. Input Offset Current vs Temperature
Figure 6-11. Input Bias Current vs Temperature
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SBOS914D – OCTOBER 2018 – REVISED DECEMBER 2020
6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM =VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, and G = 1/2 (unless otherwise
noted)
3500
3000
2500
2000
1500
1000
500
3500
3000
2500
2000
1500
1000
500
-40èC
25èC
125 èC
-40èC
25èC
125èC
0
0
-500
-1000
-1500
-500
-1000
-1500
-60
-40
-20
0
VCM ( V )
20
40
60
-30 -25 -20 -15 -10 -5
0
VCM ( V )
5
10 15 20 25 30
VS = ±18 V
VS = ±18 V
Figure 6-13. Input Bias Current vs Common Mode Voltage
G = 1/2
Figure 6-14. Input Bias Current vs Common Mode Voltage
G = 2
30%
25%
20%
15%
10%
5%
30%
25%
20%
15%
10%
5%
0
0
-40 -32 -24 -16 -8
0
8
16
24
32
40
-80
-60
-40
-20
0
20
40
60
80
Common-mode Rejection Ratio (mV/V)
Common-mode Rejection Ratio (mV/V)
N = 470
Mean = 6.01 μV/V
Std. Dev. = 4.85 μV/V
N = 470 Mean = –6.22 μV/V
Std. Dev. = 10.74 μV/V
Figure 6-15. Typical CMRR Distribution G = 1/2, VS = ±2.25 V
Figure 6-16. Typical CMRR Distribution G = 2, VS = ±2.25 V
40%
30%
25%
20%
15%
10%
5%
30%
20%
10%
0
0
-40 -32 -24 -16
-8
0
8
16
24
32
40
-80
-60
-40
-20
0
20
40
60
80
Common-mode Rejection Ratio (mV/V)
Common-mode Rejection Ratio (mV/V)
N = 470
Mean = 4.86 μV/V Std. Dev. = 4.75 μV/V
N = 470
Mean = –8.64 μV/V
Std. Dev. = 9.70 μV/V
Figure 6-17. Typical CMRR Distribution G = 1/2, VS = ±18 V
Figure 6-18. Typical CMRR Distribution G = 2, VS = ±18 V
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SBOS914D – OCTOBER 2018 – REVISED DECEMBER 2020
6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM =VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, and G = 1/2 (unless otherwise
noted)
-5
-7.5
-10
35
30
25
20
15
10
5
-12.5
-15
-17.5
-20
0
-22.5
-25
-5
-10
-15
-27.5
-30
-40 -20
0
20
40
60
Temperature ( C )
80
100 120 140
-40 -20
0
20
40
60
Temperature ( C )
80
100 120 140
VS = ±18 V
24 Units
VS = ±18 V
24 Units
Figure 6-20. CMRR vs Temperature G = 2
Figure 6-19. CMRR vs Temperature G = 1/2
120
100
80
40
35
30
25
20
15
10
5
G=1/2
G=2
Vs=ê18 V
Vs=ê4 V
60
40
20
100m
0
1
10
100
1k
Frequency (Hz)
10k 100k
1M
10M
1
10
100
1k 10k
Frequency (Hz)
100k
1M
10M
D001
G = 1/2 and G = 2
VS = ±18 V
Figure 6-21. Common-Mode Rejection Ratio vs Frequency,
Referred to Input
Figure 6-22. Maximum Output Voltage vs Frequency
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-40
-20
0
20
40
Temperature ( C )
60
80
100 120 140
-40
-20
0
20
40
Temperature ( C )
60
80
100 120 140
VS = ±18 V
24 Units
VS = ±18 V
24 Units
Figure 6-23. PSRR vs Temperature G = 1/2
Figure 6-24. PSRR vs Temperature G = 2
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SBOS914D – OCTOBER 2018 – REVISED DECEMBER 2020
6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM =VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, and G = 1/2 (unless otherwise
noted)
140
120
100
80
140
120
100
80
PSRR+
PSRR-
PSRR+
PSRR-
60
60
40
40
20
20
0
0
1
10
100
1k 10k
Frequency (Hz)
100k
1M
10M
1
10
100
1k 10k
Frequency (Hz)
100k
1M
10M
Figure 6-25. PSRR vs Frequency (RTI) G = 1/2
Figure 6-26. PSRR vs Frequency (RTI) G = 2
50%
40%
30%
20%
10%
0
50%
40%
30%
20%
10%
0
-0.03
-0.025
-0.02
-0.015
Gain Error (%)
-0.01
-0.005
0
0
0.005
0.01
0.015
Gain Error (%)
0.02
0.025
0.03
N = 470 Mean = –0.0076%
Std. Dev. = 0.0015 %
N = 470
Mean = 0.0085%
Std. Dev. = 0.0014%
Figure 6-28. Typical Distribution of Gain Error G = 2
Figure 6-27. Typical Distribution of Gain Error G = 1/2
0.0095
0.009
-0.002
-0.0025
-0.003
-0.0035
-0.004
-0.0045
-0.005
-0.0055
-0.006
-0.0065
-0.007
-0.0075
-0.008
-0.0085
-0.009
-0.0095
-0.01
0.0085
0.008
0.0075
0.007
0.0065
0.006
0.0055
0.005
0.0045
0.004
0.0035
0.003
0.0025
0.002
-40 -20
0
20
40
60
Temperature ( C )
80
100 120 140
-40
-20
0
20
40
60
Temperature ( C )
80
100 120 140
VS = ±18 V
30 Units
VS = ±18 V
30 Units
Figure 6-30. Gain Error vs Temperature G = 2
Figure 6-29. Gain Error vs Temperature G = 1 /2
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SBOS914D – OCTOBER 2018 – REVISED DECEMBER 2020
6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM =VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, and G = 1/2 (unless otherwise
noted)
10
20
10
0
CLOAD = 20 pF
CLOAD = 100 pF
CLOAD = 20 pF
CLOAD = 100 pF
0
-10
-20
-30
-10
-20
100
1k
10k 100k
Frequency (Hz)
1M
10M
100
1k
10k 100k
Frequency (Hz)
1M
10M
VS = ±18 V
VS = ±18 V
Figure 6-31. Closed-Loop Gain vs Frequency G = 1/2
Figure 6-32. Closed-Loop Gain vs Frequency G = 2
1000
1000
100
10
1
100
10
1
100m
1
10
100
Frequency (Hz)
1k
10k
100k
100m
1
10
100
Frequency (Hz)
1k
10k
100k
VS = ±18 V
VS = ±18 V
Figure 6-33. Voltage Noise Spectral Density vs Frequency (RTI) Figure 6-34. Voltage Noise Spectral Density vs Frequency (RTI)
G = 1/2
G = 2
Time (1 s/div)
Time (1 s/div)
VS = ±18 V
VS = ±18 V
Figure 6-35. 0.1-Hz to 10-Hz RTI Voltage Noise G = 1/2
Figure 6-36. 0.1-Hz to 10-Hz RTI Voltage Noise G = 2
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SBOS914D – OCTOBER 2018 – REVISED DECEMBER 2020
6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM =VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, and G = 1/2 (unless otherwise
noted)
100
10
1
100
10
1
0.1
0.1
1
10
100 1k
Frequency (Hz)
10k
100k
1
10
100 1k
Frequency (Hz)
10k
100k
VS = ±18 V
VS = ±18 V
Figure 6-37. Integrated Output Voltage Noise vs Noise
Bandwidth G = 1/2
Figure 6-38. Integrated Output Voltage Noise vs Noise
Bandwidth G = 2
18
18
-40èC
-40èC
25èC
85èC
125èC
17.5
17.5
17
25èC
17
85èC
125èC
16.5
16.5
16
16
15.5
15
15.5
15
14.5
14
14.5
14
13.5
13
13.5
13
12.5
12
12.5
12
11.5
11.5
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75
ILoad (mA)
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75
ILoad ( mA )
VS = ±18 V
VS = ±18 V
Figure 6-39. Positive Output Voltage vs Output Current
(sourcing) G = 1/2
Figure 6-40. Positive Output Voltage vs Output Current
(sourcing) G = 2
-14
-14
-14.25
-14.5
-14.75
-15
-40èC
25èC
85èC
125èC
-14.25
-14.5
-14.75
-15
-40èC
25èC
85èC
125èC
-15.25
-15.5
-15.75
-16
-15.25
-15.5
-15.75
-16
-16.25
-16.5
-16.75
-17
-16.25
-16.5
-16.75
-17
-17.25
-17.5
-17.75
-18
-17.25
-17.5
-17.75
-18
-5
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75
ILoad ( mA )
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75
ILoad ( mA )
VS = ±18 V
VS = ±18 V
Figure 6-41. Negative Output Voltage vs Output Current
(sinking) G = 1/2
Figure 6-42. Negative Output Voltage vs Output Current
(sinking) G = 2
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SBOS914D – OCTOBER 2018 – REVISED DECEMBER 2020
6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM =VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, and G = 1/2 (unless otherwise
noted)
Falling
Rising
Falling
Rising
Time (1 ms/div)
Time (1 ms/div)
VS = ±18 V
VS = ±18 V
Figure 6-43. Settling Time G = 1/2
Figure 6-44. Settling Time G = 2
VIN-
VIN+
VOUT
VIN-
VIN+
VOUT
Time (1 ms/div)
Time (1 ms/div)
VS = ±18 V
VS = ±18 V
Figure 6-46. Large Signal Step Response G = 2
Figure 6-45. Large Signal Step Response G = 1/2
30
24
18
12
Negative
Positive
Rising
Falling
-60
-35
-10
15
40
65
90
115
140
Time (200 ns/div)
Temperature (èC)
VS = ±18 V
VS = ±18 V
Figure 6-47. Slew Rate over Temperature
Figure 6-48. Overload Recovery (Normalized to 0 V)
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SBOS914D – OCTOBER 2018 – REVISED DECEMBER 2020
6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM =VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, and G = 1/2 (unless otherwise
noted)
80
70
60
50
40
30
20
10
0
50
40
30
20
10
0
RISO = 0
RISO = 25
RISO = 50
RISO = 0
RISO = 25
RISO = 50
10
100
Capactiance (pF)
1000
10
100
Capactiance (pF)
1000
VS = ±18 V
VS = ±18 V
Figure 6-49. Small-Signal Overshoot vs Capacitive Load G = 1/2 Figure 6-50. Small-Signal Overshoot vs Capacitive Load G = 2
VIN-
VIN+
VOUT
VIN-
VIN+
VOUT
Time (1 ms/div)
Time (1 ms/div)
VS = ±18 V
Figure 6-51. Small-Signal Step Response G = 1/2
VS = ±18 V
Figure 6-52. Small-Signal Step Response G = 2
1
-40
1
-40
RLoad = 10k W
RLoad = 2k W
RLoad = 600 W
RLoad = 10k W
RLoad = 2k W
RLoad = 600 W
0.1
-60
0.1
-60
0.01
-80
0.01
-80
0.001
0.0001
-100
-120
0.001
0.0001
-100
-120
100
1k
Frequency (Hz)
10k
100
1k
Frequency (Hz)
10k
VS = ±18 V
VOUT = 3.5 Vrms
VS = ±18 V
Vout = 3.5 Vrms
Figure 6-53. THD+N vs Frequency G = 1/2
Figure 6-54. THD+N vs Frequency G = 2
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SBOS914D – OCTOBER 2018 – REVISED DECEMBER 2020
6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM =VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, and G = 1/2 (unless otherwise
noted)
1
-40
1
-40
RLoad = 10K W
RLoad = 2k W
RLoad = 600 W
RLoad = 10K W
RLoad = 2k W
RLoad = 600 W
0.1
-60
0.1
-60
0.01
-80
0.01
-80
0.001
-100
-120
0.001
-100
-120
0.0001
0.0001
10m
100m
Output Amplitude (V
1
10
10m
100m
Output Amplitude (V
1
)
RMS
10
)
RMS
VS = ±18 V
VS = ±18 V
Figure 6-55. THD+N Ratio vs Output Amplitude G = 1/2
Figure 6-56. THD+N Ratio vs Output Amplitude G = 2
1.1
1.07
1.06
1.05
1.04
1.03
1.02
1.01
1
1.08
1.06
1.04
1.02
1
0.99
0.98
0.97
0.96
0.98
-40 -20
0
20
40
Temperature ( C )
60
80
100 120 140
-40 -20
0
20
40
Temperature ( C )
60
80
100 120 140
VS = ±18 V
30 Units
VS = ±18 V
30 Units
Figure 6-57. Supply Current vs Temperature G = 1/2
Figure 6-58. Supply Current vs Temperature G = 2
5
4.5
4
5
4.5
4
3.5
3
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
-0.5
0
5
10
15
20
25
Total Supply ( V )
30
35
40
0
5
10
15
20
25
Total Supply ( V )
30
35
40
VS = ±18 V
30 Units
VS = ±18 V
30 Units
Figure 6-60. Supply Current vs Supply Voltage G = 2
Figure 6-59. Supply Current vs Supply Voltage G = 1/2
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SBOS914D – OCTOBER 2018 – REVISED DECEMBER 2020
6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM =VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, and G = 1/2 (unless otherwise
noted)
100
80
100
80
60
60
40
40
20
20
0
0
-20
-40
-60
-80
-20
-40
-60
-80
-40 -20
0
20
40
Temperature ( C )
60
80
100 120 140
-40 -20
0
20
40
Temperature ( C )
60
80
100 120 140
VS = ±18 V
30 Units
VS = ±18 V
30 Units
Figure 6-61. Short Circuit Current vs Temperature G = 1/2
Figure 6-62. Short Circuit Current vs Temperature G = 2
150
160
140
130
120
110
100
90
140
120
100
80
60
10M
100M
Frequency (Hz)
1G
10G
10M
100M
Frequency (Hz)
1G
10G
VS = ±18 V
VS = ±18 V
Figure 6-63. Differential-Mode EMI Rejection Ratio G = 1/2
Figure 6-64. Differential-Mode EMI Rejection Ratio G = 2
180
140
130
120
110
100
90
160
140
120
100
80
80
60
70
10M
100M
Frequency (Hz)
1G
10G
10M
100M
Frequency (Hz)
1G
10G
VS = ±18 V
VS = ±18 V
Figure 6-65. Common-Mode EMI Rejection Ratio G = 1/2
Figure 6-66. Common-Mode EMI Rejection Ratio G = 2
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SBOS914D – OCTOBER 2018 – REVISED DECEMBER 2020
6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM =VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, and G = 1/2 (unless otherwise
noted)
80
60
40
30
Vs = ±2.25V
Vs = ±18V
Vs = ±2.25V
Vs = ±18V
40
20
20
10
0
0
-20
-40
-60
-80
-10
-20
-30
-40
-20 -16 -12 -8
-4
0
4
8
12 16 20
-20 -16 -12 -8
-4
0
4
8
12 16 20
Vout (V)
Vout (V)
Vref = 0 V
Vref = 0 V
Figure 6-67. Input Common-Mode Voltage vs Output Voltage
G = 1/2, Bipolar Supply
Figure 6-68. Input Common-Mode Voltage vs Output Voltage
G = 2, Bipolar Supply
10
7.5
5
20
15
10
5
2.5
0
0
-5
-2.5
-5
-10
-1.25
0
1.25
2.5
3.75
5
6.25
-1.25
0
1.25
2.5
3.75
5
6.25
Vout (V)
Vout (V)
Vref = 0 V
Vref = 0 V
Figure 6-70. Input Common-Mode Voltage vs Output Voltage
G = 2, 5-V Supply
Figure 6-69. Input Common-Mode Voltage vs Output Voltage
G = 1/2, 5-V Supply
60
50
40
30
20
10
0
120
100
80
60
40
20
0
-20
-40
-60
-10
-20
0
4
8
12
16
20
24
28
32
36
40
0
4
8
12
16
20
24
28
32
36
40
Vout (V)
Vout (V)
Vref = 0 V
Vref = 0 V
Figure 6-71. Input Common-Mode Voltage vs Output Voltage
G = 1/2, 36-V Supply
Figure 6-72. Input Common-Mode Voltage vs Output Voltage
G = 2, 36-V Supply
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM =VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, and G = 1/2 (unless otherwise
noted)
1000
100
10
1
0.1
0.01
0.001
0.0001
G = 2
G = 0.5
1
10
100
1k 10k
Frequency (Hz)
100k
1M
10M
VS = ±18 V
Figure 6-73. Closed-Loop Output Impedance vs Frequency
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7 Detailed Description
7.1 Overview
The INA592 consists of a high precision, e-trim™ op amp and four trimmed resistors. These resistors can be
connected to make a wide variety of amplifier configurations, including difference, noninverting, and inverting
configurations. Using the on-chip resistors of the INA592 provides the designer with several advantages over a
discrete design. The INA59 also includes internal compensation capacitors, as shown in Section 7.2.
7.2 Functional Block Diagram
V+
INA592
12 kꢀ
6 kꢀ
œIN
SENSE
16 pF
œ
OUT
+
16 pF
Vœ
12 kꢀ
6 kꢀ
+IN
REF
Vœ
7.3 Feature Description
Much of the dc performance of op amp circuits depends on the accuracy of the surrounding resistors. The
resistors on the INA592 are laid out to be tightly matched. The resistors of each part are matched on-chip and
tested for their matching accuracy. As a result of this trimming and testing, the INA592 provides high accuracy
for specifications such as gain drift, common-mode rejection, and gain error.
7.4 Device Functional Modes
The INA592 can measure voltages beyond the rails. For the G = ½ and G = 2 difference amplifier configurations,
see the input voltage range in Section 6.5 and Section 6.6 for details. The INA592 can be configured in several
ways; see Figure 8-4 to Figure 8-8. These configurations rely on the internal, matched resistors,; therefore all of
these configurations have excellent gain accuracy and gain drift.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
Figure 8-1 shows the basic connections required for operation of the INA592. Connect power supply bypass
capacitors close to the device pins.
The differential input signal is connected to pins 2 and 3 as shown. The source impedances connected to the
inputs must be nearly equal to provide good common-mode rejection. An 8-Ω mismatch in source impedance
degrades the common-mode rejection of a typical device to approximately 80 dB. Gain accuracy is also slightly
affected. If the source has a known impedance mismatch, use an additional resistor in series with one input to
preserve good common-mode rejection.
As shown in the figure, sense measurements at the load.
8.2 Typical Application
V–
V+
1 µF
1 µF
4
7
INA592
R1
R2
2
3
5
6
V2
12 kW
6 kW
R3
V3
RL
12 kW
R4
6 kW
VOUT = V3 – V2
1
Ref
Copyright © 2018, Texas Instruments Incorporated
Figure 8-1. Basic Power Supply and Signal Connections
8.2.1 Design Requirements
For the application shown in Figure 8-1, the design requirements are:
• Gain of G = ½
• Offset of output voltage VoutOS = 0 V
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8.2.2 Detailed Design Procedure
8.2.2.1 Operating Voltage
The INA592 operates from single (4.5 V to 36 V) or dual (±2.25 V to ±18 V) supplies with excellent performance.
Specifications are production tested with 5-V and ±15-V supplies. Most behavior remains unchanged throughout
the full operating voltage range. Parameters that vary significantly with operating voltage are shown in the
Section 6.7. The internal op amp in the INA592 is a single-supply design. This design allows linear operation
with the op amp common-mode voltage equal to, or slightly less than V– (or single-supply ground). Although
input voltages on pins 2 and 3 that are bless than the negative supply voltage do not damage the device,
operation in this region is not recommended. Transient conditions at the inverting input terminal less than the
negative supply can cause a positive feedback condition that could lock the device output to the negative rail.
The INA592 can accurately measure differential signals that are greater than the positive power supply. For
example in G = ½, the linear common-mode range extends to nearly three times the positive power-supply
voltage; see the Typical Characteristics as well as Section 8.2.2.3.
8.2.2.2 Offset Voltage Trim
The INA592 is production trimmed for low offset voltage and drift. Most applications require no external offset
adjustment. Figure 8-2 shows an optional circuit for trimming the output offset voltage. The output is referred to
the output reference terminal (pin 1), which is normally grounded. A voltage applied to the REF pin is summed
with the output signal. This summing operation can be used to null offset voltage. To maintain good common-
mode rejection, the source impedance of a signal applied to the REF pin must be less than 8 Ω. For low
impedance at the REF pin, the trim voltage can be buffered with an op amp, such as the OPA177.
INA592
R1
R2
2
5
6
V2
VO
8 W
R3
3
V3
R4
+15 V
1
Ref
R = 237 kW
VO = V3 – V2
1ꢀꢀ kW
Offset Adjustment
Range = 5ꢀꢀ ꢁV
8 W
–15 V
NOTE: For 75ꢀ ꢁV rangeꢂ R = 158 kW.
Copyright © 2ꢀ17ꢂ Texas Instruments Incorporated
Figure 8-2. Offset Adjustment
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8.2.2.3 Input Voltage Range
The INA592 is able to measure input voltages beyond the supply rails. The internal resistors divide down the
voltage before the voltage reaches the internal op amp, and provide protection to the op amp inputs. Figure 8-3
shows an example of how the voltage division works in a difference-amplifier configuration. For the INA592 to
measure correctly, the input voltages at the input nodes of the internal op amp must stay less than 0.1 V of the
positive supply rail, and can exceed the negative supply rail by 0.1 V. See Section 9 for more details.
R2
-INOP =
*V+IN
R1+R2
R3
R4
V-IN
SENSE
œ
OUT
+
V-
R1
R2
V+IN
REF
R2
+INOP =
*V+IN
R1+R2
Figure 8-3. Voltage Division in the Difference Amplifier Configuration
The INA592 has integrated ESD diodes at the inputs that provide overvoltage protection. This feature simplifies
system design by eliminating the need for additional external protection circuitry, and enables a more robust
system. The voltages at any of the inputs of the devices in G = ½ configuration with ±18-V supplies can safely
range from +VS − 54 V up to −VS + 54 V. For example, on ±10-V supplies, input voltages can go as high as
±30 V.
8.2.2.4 Capacitive Load Drive Capability
The INA592 can drive large capacitive loads, even at low supplies. The device is stable with a 500-pF load; see
Section 6.7.
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8.2.2.5 Other Examples for Difference Amplifier Configurations
The INA592 can be combined with op amps to form a complete instrumentation amplifier with specialized
performance characteristics, as shown in Figure 8-4.
V1
INA592
–In
A1
2
5
R2
6
R1
VO
R2
1
3
A2
V2
+In
VO = (1 + 2R2/R1) (V2 –V1)
Copyright © 2017, Texas Instruments Incorporated
Figure 8-4. Precision Instrumentation Amplifier
Texas Instruments offers many complete high-performance instrumentation amplifiers (IAs). See Table 8-1 for
some of the products with related performance.
Table 8-1. Recommended Products to Use With the INA592
A1, A2
FEATURE
SIMILAR TI IA
OPA27
Low noise
INA103
OPA129
OPA177
OPA2130
OPA2234
OPA2237
Ultra-low bias current (fA)
Low offset drift, low noise
Low power, FET-input (pA)
Single supply, precision, low power
SIngle supply, low power, 8-pin MSOP
INA116
INA114, INA128
INA111
INA122. INA118
INA122, INA126
BUF634 inside feedback
INA592
loop contributes no error.
2
5
6
–In
BUF634
VO
RL
1
3
(Low IQ mode)
+In
Copyright © 2017, Texas Instruments Incorporated
Figure 8-5. Low Power, High-Output Current Precision Difference Amplifier
V+
V+
3
INA592
2
5
7
6
(V+) / 3
1
4
Ground
Ground
Figure 8-6. Pseudoground Generator
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+5 V
7
INA592
2
5
6
1
–In
12 Bits
Out
ADS7806
0 V - 4 V
Input
3
+In
4
VCM = 0 V to 8 V
tS = 45 µs (4 V Step to 0.01%)
Copyright © 2017, Texas Instruments Incorporated
Figure 8-7. Differential Input Data Acquisition
V+
12.5 kꢀ
50 kꢀ
1 kꢀ
0V to 10V
in
7
œ
Set R1 = R2
6 kꢀ
12 kꢀ
5
2
6
+15V
+
R1
R2
œ
-IN
R1
50.1 ꢀ
OPA192
2
REF10
4
2N3904
INA592
+
Vout
6
R3
R4
R2
1
3
10V
50.1 ꢀ
+IN
Vref
6 kꢀ
12 kꢀ
For 4-20mA applications,
The REF10 sets the 4 mA
low-scale output for 0 V input.
4
RL
Iout = 4 to 20mA
≈
∆
«
’
÷
◊
1
1
Iout = 2*
-
VIN+ VIN-
+
(
)
40kW R2
Figure 8-8. Precision Voltage-to-Current Conversion
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The difference amplifier is a highly versatile building block that is useful in a wide variety of applications. See the
INA105 data sheet for additional applications ideas, including:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Current Receiver with Compliance to Rails
Precision Unity-Gain Inverting Amplifier
±10-V Precision Voltage Reference
±5-V Precision Voltage Reference
Precision Unity-Gain Buffer
Precision Average Value Amplifier
Precision G = 2 Amplifier
Precision Summing Amplifier
Precision G = 1/2 Amplifier
Precision Bipolar Offsetting
Precision Summing Amplifier with Gain
Instrumentation Amplifier Guard Drive Generator
Precision Summing Instrumentation Amplifier
Precision Absolute Value Buffer
Precision Voltage-to-Current Converter with Differential Inputs
Differential Input Voltage-to-Current Converter for Low IOUT
Isolating Current Source
Differential Output Difference Amplifier
Isolating Current Source with Buffering Amplifier for Greater Accuracy
Window Comparator with Window Span and Window Center Inputs
Precision Voltage-Controlled Current Source with Buffered Differential Inputs and Gain
Digitally Controlled Gain of ±1 Amplifier
8.2.3 Application Curve
The interaction between the output stage of an operational amplifier (op amp) and capacitive loads can impact
the stability of the circuit. Throughout the industry, op-amp output-stage requirements have changed greatly
since their original creation. Classic output stages with the class-AB, common-emitter, bipolar-junction transistor
(BJT) have now been replaced with common-collector BJT and common-drain, complementary metal-oxide
semiconductor (CMOS) devices. Both of these technologies enable rail-to-rail output voltages for single-supply
and battery-powered applications. A result of changing these output-stage structures is that the op-amp open-
loop output impedance (ZO) changed from the largely resistive behavior of early BJT op amps to a frequency-
dependent ZO that features capacitive, resistive, and inductive portions. Proper understanding of ZO over
frequency, and also the resulting closed-loop output impedance over frequency, is crucial for the understanding
of loop-gain, bandwidth, and stability analysis. Figure 8-9 shows how the INA592 closed-loop output impedance
varies over frequency.
1000
100
10
1
0.1
0.01
0.001
0.0001
G = 2
G = 0.5
1
10
100
1k 10k
Frequency (Hz)
100k
1M
10M
VS = ±18 V
Figure 8-9. Closed-Loop Output Impedance vs Frequency
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9 Power Supply Recommendations
The nominal performance of the INA592 is specified with a supply voltage of ±15 V and midsupply reference
voltage. The device operates using power supplies from ±2.25 V (4.5 V) to ±18 V (36 V) and non midsupply
reference voltages with excellent performance. Parameters that can vary significantly with operating voltage and
reference voltage are shown in Section 6.7.
10 Layout
10.1 Layout Guidelines
Attention to good layout practices is always recommended. For best operational performance of the device, use
good PCB layout practices, including:
•
Make sure that both input paths are well-matched for source impedance and capacitance to avoid converting
common-mode signals into differential signals.
•
Noise propagates into analog circuitry through the power pins of the circuit as a whole and of the device.
Bypass capacitors reduce the coupled noise by providing low-impedance power sources local to the analog
circuitry.
– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
•
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better than in
parallel with the noisy trace.
•
•
Place the external components as close to the device as possible.
Keep the traces as short as possible.
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10.2 Layout Example
V-
V+
1ꢁF
1ꢁF
C1
C2
4
7
12 kꢀ
6 kꢀ
2
3
5
-IN
SENSE
R1
R2
œ
6
Vout
+
OUT
RL
R3
R4
1
+IN
Vref = GND
REF
12 kꢀ
6 kꢀ
1*
2
Vout=
-
)
(V+IN V-IN
+V
Low-impedance
connection for
reference terminal
GND
C2
Use ground pours for
shielding the input
signal pairs
INA592
1
NC
8
REF
œ
œIN
V+
2
7
6
œIN
+
+IN
3
OUT
SENSE
+IN
Vout
Vœ
4
5
C1
GND
RL
Place bypass
capacitors as close to
IC as possible
GND
-V
Figure 10-1. Example Schematic and Associated PCB Layout
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Vœ
V+
1 ꢁF
1 ꢁF
C1
C2
5
8
12 kꢀ
6 kꢀ
3
6
VœIN
SENSE
œIN
R1
R2
œ
1
-INOP
+INOP
7
VOUT
+
10
OUT
RL
R3
R4
4
2
V+IN
VREF = GND
REF
+IN
12 kꢀ
6 kꢀ
1
=
VOUT
∂ V+IN - V-IN
(
)
2
Low-impedance
connection for
reference terminal
INA597
1
2
GND
Þ INOP
+INOP
10
REF
NC
V+
9
8
œ
œIN
œIN
3
4
5
+
C2
+IN
+IN
OUT
7
6
+INOP
Vœ
SENSE
GND
NC= No Connection
RL
C1
Use ground pours
for shielding
the input
Place bypass capacitors
as close to IC as
possible
signal pairs
œV
Figure 10-2. Example Schematic and Associated PCB Layout with VSON Package
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Trademarks
e-trim™ and TI E2E™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
INA592ID
PREVIEW
SOIC
D
8
75
RoHS (In work)
& Non-Green
Call TI
Call TI
-40 to 125
INA592IDGKR
INA592IDGKT
INA592IDR
ACTIVE
ACTIVE
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
2500 RoHS & Green
NIPDAUAG
NIPDAUAG
Call TI
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Call TI
-40 to 125
-40 to 125
-40 to 125
1OK6
1OK6
250 RoHS & Green
PREVIEW
2500 RoHS (In work)
& Non-Green
PINA592IDR
ACTIVE
SOIC
D
8
2500 RoHS (In work)
& Non-Green
Call TI
Call TI
-40 to 125
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Dec-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
INA592IDGKR
INA592IDGKT
VSSOP
VSSOP
DGK
DGK
8
8
2500
250
330.0
330.0
12.4
12.4
5.3
5.3
3.4
3.4
1.4
1.4
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Dec-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
INA592IDGKR
INA592IDGKT
VSSOP
VSSOP
DGK
DGK
8
8
2500
250
366.0
366.0
364.0
364.0
50.0
50.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
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warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated
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