INA818 [TI]

2MHz、35μV 失调电压、8nV/√Hz 噪声、350µA 功耗、精密（增益引脚 1、8）仪表放大器;


型号：	INA818
厂家：	TEXAS INSTRUMENTS
描述：	2MHz、35μV 失调电压、8nV/√Hz 噪声、350µA 功耗、精密（增益引脚 1、8）仪表放大器放大器仪表仪表放大器
文件：	总43页 (文件大小：1585K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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INA818

ZHCSJM1A –APRIL 2019–REVISED JUNE 2019

INA818 35µV 失调电压、8nV/√Hz 噪声、低功耗、精密仪表放大器

1 特性

3 说明

•

低失调电压：10µV（典型值）、35µV（最大值）

INA818 是一款高精度仪表放大器，此放大器提供低功

耗并且可在极宽的单电源或双电源电压范围内工作。可

通过单个外部电阻器在 1 到 10000 范围内设置增益。

由于采用超 β 输入晶体管（这些晶体管可提供极低的

输入失调电压、失调电压漂移、输入偏置电流、输入电

压和电流噪声），该器件可提供出色的精度。附加电路

可以为输入提供高达 ±60V 的过压保护。

•

增益漂移：5ppm/°C (G = 1)、

35ppm/°C (G > 1)（最大值）

•

噪声：8nV/√Hz

带宽：2MHz (G = 1)、270kHz (G = 100)

采用 1nF 容性负载时保持稳定

输入保护电压高达 ±60V

共模抑制：110dB，G = 10（最小值）

电源抑制：100dB，G = 1（最小值）

电源电流：385µA（最大值）

电源电压范围：

INA818 经过优化，可提供较高的共模抑制比。当 G =

1 时，整个输入共模范围内共模抑制比超过 90dB。根

据设计，此器件采用低电压运行，由 4.5V 单电源和高

达 ±18V 的双电源供电。

–

单电源：4.5V 至 36V

INA818 采用 8 引脚 SOIC 封装，且额定工作温度范围

为 –40°C 至 +125°C。

双电源：±2.25V 至 ±18V

•

额定温度范围：–40°C 至 +125°C

封装：8 引脚 SOIC

器件信息⁽¹⁾

器件型号

INA818

封装

SOIC (8)

封装尺寸（标称值）

2 应用

4.90mm × 3.91mm

•

工业监控器

(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。

流量变送器

电池测试设备

多参数患者监视器

模拟输入模块

半导体测试设备

便携式仪表

INA818 简化内部原理图

输入阶段失调电压漂移的典型分布

+VS

25%

22.5%

20%

17.5%

15%

12.5%

10%

7.5%

Over-

Voltage

40 kꢀ

-IN

Protection

25 kꢀ

R_G

OUT

REF

+IN

Over-

Voltage

40 kꢀ

Protection

2.5%

-VS

50 kW

R_G

G = 1+

V_O= G V_+IN- V_-IN+ V

(

)

REF

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

Input Stage Offset Voltage Drift (mV/èC)

D002

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SBOS894

INA818

ZHCSJM1A –APRIL 2019–REVISED JUNE 2019

www.ti.com.cn

8.3 Feature Description................................................. 20

8.4 Device Functional Modes........................................ 26

Application and Implementation ........................ 26

9.1 Application Information............................................ 26

9.2 Typical Applications ................................................ 29

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Device Comparison Table..................................... 3

Pin Configuration and Functions......................... 4

Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 ESD Ratings ............................................................ 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 5

7.5 Electrical Characteristics........................................... 6

7.6 Typical Characteristics: Table of Graphs.................. 8

7.7 Typical Characteristics............................................ 10

Detailed Description ............................................ 19

8.1 Overview ................................................................. 19

8.2 Functional Block Diagram ....................................... 19

10 Power Supply Recommendations ..................... 32

11 Layout................................................................... 32

11.1 Layout Guidelines ................................................. 32

11.2 Layout Example .................................................... 33

12 器件和文档支持 ..................................................... 34

12.1 文档支持................................................................ 34

12.2 接收文档更新通知 ................................................. 34

12.3 社区资源................................................................ 34

12.4 商标....................................................................... 34

12.5 静电放电警告......................................................... 34

12.6 Glossary................................................................ 34

13 机械、封装和可订购信息....................................... 34

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Original (April 2019) to Revision A

Page

•

已更改将文档状态从“预告信息”更改成了“生产数据” .............................................................................................................. 1

INA818

www.ti.com.cn

ZHCSJM1A –APRIL 2019–REVISED JUNE 2019

5 Device Comparison Table

DEVICE

DESCRIPTION

GAIN EQUATION

RG PINS AT PIN

35-µV Offset, 0.4 µV/°C V_OSDrift, 8-nV/√Hz Noise, Low-Power,

Precision Instrumentation Amplifier

INA818

INA819

INA821

INA828

INA333

PGA280

G = 1 + 50 kΩ / RG

1, 8

35-µV Offset, 0.4 µV/°C V_OSDrift, 8-nV/√Hz Noise, Low-Power,

Precision Instrumentation Amplifier

G = 1 + 50 kΩ / RG

G = 1 + 49.4 kΩ / RG

G = 1 + 50 kΩ / RG

G = 1 + 100 kΩ / RG

Digital programmable

2, 3

1, 8

N/A

35-µV Offset, 0.4 µV/°C V_OSDrift, 7-nV/√Hz Noise, High-

Bandwidth, Precision Instrumentation Amplifier

50-µV Offset, 0.5 µV/°C V_OSDrift, 7-nV/√Hz Noise, Low-Power,

Precision Instrumentation Amplifier

25-µV V_OS, 0.1 µV/°C V_OSDrift, 1.8-V to 5-V, RRO, 50-µA I_Q,

Chopper-Stabilized INA

20-mV to ±10-V Programmable Gain IA With 3-V or 5-V

Differential Output; Analog Supply up to ±18 V

G = 0.2 V Differential Amplifier for ±10-V to 3-V and 5-V

Conversion

INA159

G = 0.2 V/V

N/A

PGA112

Precision Programmable Gain Op Amp With SPI

Digital programmable

INA818

ZHCSJM1A –APRIL 2019–REVISED JUNE 2019

www.ti.com.cn

6 Pin Configuration and Functions

D Package

8-Pin SOIC

Top View

œIN

+VS

OUT

REF

+IN

œVS

Not to scale

Pin Functions

I/O

DESCRIPTION

NAME

–IN

NO.

Negative (inverting) input

+IN

Positive (noninverting) input

Output

OUT

REF

Reference input. This pin must be driven by a low-impedance source.

Gain setting pin. Place a gain resistor between pin 1 and pin 8.

Negative supply

1, 8

—

–VS

+VS

Positive supply

INA818

www.ti.com.cn

ZHCSJM1A –APRIL 2019–REVISED JUNE 2019

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

Supply voltage dual supply, V_S= (V+) – (V–)

Supply voltage single supply, V_S= (V+) – (V–)

±20

40, (single

supply)

Signal input pins

–60

–20

VREF pin

Signal output pins maximum voltage

Signal output pins maximum current

Output short-circuit⁽²⁾

(-V_s) - 0.5

-50

(+V_s) + 0.5

Continuous

Operating Temperature, T_A

Junction Temperature, T_J

Storage Temperature, T_stg

–50

150

175

150

°C

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Short-circuit to V_S/ 2.

7.2 ESD Ratings

VALUE

±1500

±750

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

4.5

MAX

UNIT

Single-supply

Supply voltage V_S

Dual-supply

±2.25

–40

±18

125

Specified temperature

°C

7.4 Thermal Information

INA818

D (SOIC)

8 PINS

119.6

66.3

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

61.9

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

20.5

ψ_JB

61.4

R_θJC(bot)

N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

INA818

ZHCSJM1A –APRIL 2019–REVISED JUNE 2019

www.ti.com.cn

7.5 Electrical Characteristics

at T_A= 25°C, V_S= ±15 V, R_L= 10 kΩ, V_REF= 0 V, and G = 1 (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT

µV

Input stage offset

voltage⁽¹⁾⁽²⁾

V_OSI

T_A= –40°C to 125°C⁽³⁾

drift vs temperature, T_A= –40°C to 125°C

0.4

300

800

µV/°C

µV

Output stage offset

voltage⁽¹⁾⁽²⁾

V_OSO

T_A= –40°C to 125°C⁽³⁾

drift vs temperature, T_A= –40°C to 125°C

G = 1, RTI

µV

µV/°C

110

114

130

136

120

130

G = 10, RTI

Power-supply rejection

ratio

PSRR

G = 100, RTI

135

G = 1000, RTI

140

z_id

z_ic

Differential impedance

100 || 1

100 || 4

GΩ || pF

GΩ || pF

MHz

Common-mode impedance

RFI filter, –3-dB frequency

(V–) + 2

(V+) – 2

±60

V_CM

Operating input range⁽⁴⁾

Input overvoltage range

V_S= ±2.25 V to ±18 V, T_A= –40°C to 125°C

T_A= –40°C to 125°C⁽³⁾

See 图 51 to 图 54

At DC to 60 Hz, RTI, V_CM= (V–) + 2 V to (V+) – 2 V,

G = 1

110

130

140

105

125

145

150

At DC to 60 Hz, RTI, V_CM= (V–) + 2 V to (V+) – 2 V,

G = 10

Common-mode rejection

ratio

CMRR

At DC to 60 Hz, RTI, V_CM= (V–) + 2 V to (V+) – 2 V,

G = 100

At DC to 60 Hz, RTI, V_CM= (V–) + 2 V to (V+) – 2 V,

G = 1000

BIAS CURRENT

V_CM= V_S/ 2

0.15

0.5

I_B

Input bias current

T_A= –40°C to 125°C

V_CM= V_S/ 2

0.5

I_OS

Input offset current

T_A= –40°C to 125°C

NOISE VOLTAGE

f = 1 kHz, G = 100, R_S= 0 Ω

f_B= 0.1 Hz to 10 Hz, G = 100, R_S= 0 Ω

f = 1 kHz, R_S= 0 Ω

0.19

nV/√Hz

µV_PP

Input stage voltage

e_NI

noise⁽⁵⁾

nV/√Hz

µV_PP

Output stage voltage

noise⁽⁵⁾

e_NO

f_B= 0.1 Hz to 10 Hz, R_S= 0 Ω

f = 1 kHz

2.6

130

4.7

fA/√Hz

pA_PP

I_n

Noise current

f_B= 0.1 Hz to 10 Hz, G = 100

GAIN

Gain equation

Gain

1 + (50 kΩ / R_G)

V/V

1000

±0.025%

±0.15%

G = 1, V_O= ±10 V

±0.005%

±0.025%

±0.05%

G = 10, V_O= ±10 V

Gain error

G = 100, V_O= ±10 V

G = 1000, V_O= ±10 V

G = 1, T_A= –40°C to 125°C, V_O= ±10 V

G > 1, T_A= –40°C to 125°C, V_O= ±10 V

±5

Gain error drift⁽⁶⁾

ppm/°C

±35

(1) Total offset, referred-to-input (RTI): V_OS= (V_OSI) + (V_OSO/ G).

(2) Offset drifts are uncorrelated. Input-referred offset drift is calculated using: ΔV_OS(RTI)= √[ΔV_OSI²+ (ΔV_OSO/ G)²]

(3) Specified by characterization.

(4) Input voltage range of the INA818 input stage. The input range depends on the common-mode voltage, differential voltage, gain, and

reference voltage. See Typical Characteristic curves 图 51 through 图 54 for more information.

(5) Total RTI voltage noise is equal to: e_N(RTI)= √[e_NI²+ (e_NO/ G)²]

(6) The values specified for G > 1 do not include the effects of the external gain-setting resistor, R_G.

INA818

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ZHCSJM1A –APRIL 2019–REVISED JUNE 2019

Electrical Characteristics (continued)

at T_A= 25°C, V_S= ±15 V, R_L= 10 kΩ, V_REF= 0 V, and G = 1 (unless otherwise noted)

PARAMETER

TEST CONDITIONS

G = 1 to 10, V_O= –10 V to 10 V, R_L= 10 kΩ

G = 100, V_O= –10 V to 10 V, R_L= 10 kΩ

G = 1000, V_O= –10 V to 10 V, R_L= 10 kΩ

G = 1 to 100, V_O= –10 V to 10 V, R_L= 2 kΩ

MIN

TYP

MAX

UNIT

Gain nonlinearity

ppm

OUTPUT

Voltage swing

(V–) + 0.15

(V+) – 0.15

Load capacitance stability

1000

5.0

Closed-loop output

impedance

Z_O

I_SC

f = 10 kHz

Ω

Short-circuit current

Continuous to V_S/ 2

±20

FREQUENCY RESPONSE

G = 1

2.0

890

270

MHz

kHz

G = 10

t_S

Bandwidth, –3 dB

Slew rate

G = 100

G = 1000

G = 1, V_O= ±10 V

0.9

V/µs

0.01%, G = 1 to 100, V_STEP= 10 V

0.01%, G = 1000, V_STEP= 10 V

0.001%, G = 1 to 100, V_STEP= 10 V

0.001%, G = 1000, V_STEP= 10 V

Settling time

µs

REFERENCE INPUT

R_INInput impedance

kΩ

Voltage range

(V–)

(V+)

Gain to output

V/V

Reference gain error

0.01%

POWER SUPPLY

V_IN= 0 V

350

385

520

I_QQuiescent current

µA

V_IN= 0 V, T_A= –40°C to 125°C

INA818

ZHCSJM1A –APRIL 2019–REVISED JUNE 2019

www.ti.com.cn

7.6 Typical Characteristics: Table of Graphs

表 1. Table of Graphs

DESCRIPTION

Typical Distribution of Input Stage Offset Voltage

Typical Distribution of Input Stage Offset Voltage Drift

Typical Distribution of Output Stage Offset Voltage

Typical Distribution of Output Stage Offset Voltage Drift

Input Stage Offset Voltage vs Temperature

Output Stage Offset Voltage vs Temperature

Typical Distribution of Input Bias Current T_A= 25°C

Typical Distribution of Input Bias Current T_A= 90°C

Typical Distribution of Input Offset Current

Input Bias Current vs Temperature

FIGURE

图 1

图 2

图 3

图 4

图 5

图 6

图 7

图 8

图 9

图 10

图 11

图 12

图 13

图 14

图 15

图 16

图 17

图 18

图 19

图 20

图 21

图 22

图 23

图 24

图 25

图 26

图 28

图 29

图 27

图 30

图 31

图 32

图 33

图 34

图 35

图 36

图 37

图 38

图 39

图 40

图 41

图 42

图 43

图 44

图 45

图 46

Input Offset Current vs Temperature

Typical CMRR Distribution G = 1

Typical CMRR Distribution G = 10

CMRR vs Temperature G = 1

CMRR vs Temperature G = 10

Input Current vs Input Overvoltage

CMRR vs Frequency (RTI)

CMRR vs Frequency (RTI, 1-kΩ source imbalance)

Positive PSRR vs Frequency (RTI)

Negative PSRR vs Frequency (RTI)

Gain vs Frequency

Voltage Noise Spectral Density vs Frequency (RTI)

Current Noise Spectral Density vs Frequency (RTI)

0.1-Hz to 10-Hz RTI Voltage Noise G = 1

0.1-Hz to 10-Hz RTI Voltage Noise G = 1000

0.1-Hz to 10-Hz RTI Current Noise

Typical Distribution of Gain Error G = 1

Typical Distribution of Gain Error G = 10

Input Bias Current vs Common-Mode Voltage

Gain Error vs Temperature G = 1

Gain Error vs Temperature G = 10

.Supply Current vs Temperature

Gain Nonlinearity G = 1

Gain Nonlinearity G = 10

Offset Voltage vs Negative Common-Mode Voltage

Offset Voltage vs Positive Common-Mode Voltage

Positive Output Voltage Swing vs Output Current

Negative Output Voltage Swing vs Output Current

Short Circuit Current vs Temperature

Large-Signal Frequency Response

THD+N vs Frequency

Overshoot vs Capacitive Loads

Small-Signal Response G = 1

Small-Signal Response G = 10

Small-Signal Response G = 100

Small-Signal Response G = 1000

INA818

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ZHCSJM1A –APRIL 2019–REVISED JUNE 2019

Typical Characteristics: Table of Graphs (接下页)

表 1. Table of Graphs (接下页)

DESCRIPTION

FIGURE

图 47

图 48

图 49

图 50

图 51

图 52

图 53

图 54

Large Signal Step Response

Closed-Loop Output Impedance

Differential-Mode EMI Rejection Ratio

Common-Mode EMI Rejection Ratio

Input Common-Mode Voltage vs Output Voltage G = 1, V_S= 5 V

Input Common-Mode Voltage vs Output Voltage G = 100, V_S= 5 V

Input Common-Mode Voltage vs Output Voltage V_S=±5 V

Input Common-Mode Voltage vs Output Voltage V_S=±15 V

INA818

ZHCSJM1A –APRIL 2019–REVISED JUNE 2019

www.ti.com.cn

7.7 Typical Characteristics

at T_A= 25°C, V_S= ±15 V, R_L= 10 kΩ, V_REF= 0 V, and G = 1 (unless otherwise noted)

20%

15%

10%

25%

22.5%

20%

17.5%

15%

12.5%

10%

7.5%

2.5%

-50 -40 -30 -20 -10

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

Input Stage Offset Voltage (mV)

Input Stage Offset Voltage Drift (mV/èC)

D001

D002

N = 1555

Mean = 4.71 µV

Std. Dev. = 7.12 µV

N = 45

Mean = 0.0357 µV/°C

Std. Dev. = 0.099 µV/°C

图 1. Typical Distribution of Input Stage Offset Voltage

图 2. Typical Distribution of Input Stage Offset Voltage Drift

0.15

30%

25%

20%

15%

10%

0.1

0.05

-200 -150 -100

-50

100

150

200

-5

-4

-3

-2

-1

Output Stage Offset Voltage (mV)

Output Stage Offset Voltage Drift (mV/èC)

D003

D004

N = 1555

Mean = –3.18 µV

Std. Dev. = 41.26 µV

N = 45

Mean = –1.49 µV/°C

Std. Dev. = 0.89 µV/°C

图 3. Typical Distribution of Output Stage Offset Voltage

图 4. Typical Distribution of Output Stage Offset Voltage

Drift

100

500

Mean

+3s

-3s

400

300

200

100

-20

-40

-100

-200

-300

-400

-500

-60

Mean

+3s

-3s

-80

-100

-50

-25

100

125

150

-50

-25

100

125

150

Temperature (èC)

D005

D051

45 units, 1 wafer lot

45 units, 1 wafer lots

图 5. Input Stage Offset Voltage vs Temperature

图 6. Output Stage Offset Voltage vs Temperature

INA818

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ZHCSJM1A –APRIL 2019–REVISED JUNE 2019

Typical Characteristics (接下页)

at T_A= 25°C, V_S= ±15 V, R_L= 10 kΩ, V_REF= 0 V, and G = 1 (unless otherwise noted)

0.25

0.2

0.15

0.1

0.05

25%

20%

15%

10%

-300

-200

-100

100

200

300

-250 -200 -150 -100 -50

50 100 150 200 250

Input Bias Current (pA)

D006

D007

N = 94

Mean = 37.13 pA

Std. Dev. = 57.65 pA

N = 94

T_A= 90°C

Mean = –27.65 pA

Std. Dev. = 52.58 pA

T_A= 25°C

图 7. Typical Distribution of Input Bias Current

图 8. Typical Distribution of Input Bias Current

25%

20%

15%

10%

500

400

300

200

100

-100

-200

-300

-400

-500

Avg

+3s

-3s

-300

-200

-100

100

200

300

-50

-25

100

125

150

Input Offset Current (pA)

Temperature (èC)

D008

D009

N = 94

G = 1

N = 94

Mean = –38.82 pA

Std. Dev. = 47.24 pA

图 9. Typical Distribution of Input Offset Current

图 10. Input Bias Current vs Temperature

300

250

200

150

100

20%

15%

10%

-50

-100

-150

-200

-250

-300

Avg

+3s

-3s

-50 -30 -10 10

90 110 130 150

-20 -16 -12

-8

-4

Temperature (èC)

Common-Mode Rejection Ratio (mV/V)

D010

D011

N = 94

G = 1

N = 94

G = 1

Mean = 3.23 µV/V

Std. Dev. = 5.38 µV/V

图 11. Input Offset Current vs Temperature

图 12. Typical CMRR Distribution

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ZHCSJM1A –APRIL 2019–REVISED JUNE 2019

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Typical Characteristics (接下页)

at T_A= 25°C, V_S= ±15 V, R_L= 10 kΩ, V_REF= 0 V, and G = 1 (unless otherwise noted)

25%

20%

15%

10%

150

125

100

Unit 1

Unit 2

Unit 3

Unit 4

Unit 5

-2

-1.5

-1

-0.5

0.5

1.5

-50

-25

100

125

150

Common-Mode Rejection Ratio (mV/V)

Temperature (èC)

D012

D013

N = 94

G = 10

Mean = 0.34 µV/V Std. Dev. = 0.54 µV/V

5 typical units

G = 1

图 13. Typical CMRR Distribution

图 14. CMRR vs Temperature

175

150

125

100

-2

-4

-6

-8

-10

-4

-8

Unit 1

Unit 2

Unit 3

Unit 4

Unit 5

-12

-16

-20

Input Current

Output Voltage

-50

-25

100

125

150

-50 -40 -30 -20 -10

Temperature (èC)

Input Voltage (V)

D014

D015

5 typical units

V_S= 36 V

G = 10

图 15. CMRR vs Temperature

图 16. Input Current vs Input Overvoltage

160

140

120

100

150

125

100

1000

100

1000

100

10k

100k

100

10k

100k

Frequency (Hz)

D016

D017

1-kΩ source imbalance

图 17. CMRR vs Frequency (RTI)

图 18. CMRR vs Frequency (RTI)

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Typical Characteristics (接下页)

at T_A= 25°C, V_S= ±15 V, R_L= 10 kΩ, V_REF= 0 V, and G = 1 (unless otherwise noted)

170

140

110

160

140

120

100

G = 1

G = 10

G = 100

G = 1000

G = 10

G = 100

G = 1000

-10

-40

-20

-40

100

10k

100k

100

10k

100k

Frequency (Hz)

D018

D019

图 19. Positive PSRR vs Frequency (RTI)

图 20. Negative PSRR vs Frequency (RTI)

1000

500

G = 1

G = 100

300

200

100

-20

-40

-60

G = 1

G = 10

G = 100

G = 1000

100

10k

100k

10M

100m

100

10k

100k

Frequency (Hz)

D020

D021

图 21. Gain vs Frequency

图 22. Voltage Noise Spectral Density vs Frequency (RTI)

1000

700

500

300

200

100

-1

-2

-3

100m

100

10k

Frequency (Hz)

Time (s/div)

D022

D023

G = 1

图 23. Current Noise Spectral Density vs Frequency (RTI)

图 24. 0.1-Hz to 10-Hz RTI Voltage Noise

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Typical Characteristics (接下页)

at T_A= 25°C, V_S= ±15 V, R_L= 10 kΩ, V_REF= 0 V, and G = 1 (unless otherwise noted)

100

1.5

0.5

-20

-40

-60

-80

-100

-0.5

-1

-1.5

-2

-5

-4

-3

-2

-1

-5

-4

-3

-2

-1

Time (1 s/div)

D024

D025

G = 1000

图 25. 0.1-Hz to 10-Hz RTI Voltage Noise

图 26. 0.1-Hz to 10-Hz RTI Current Noise

20%

17.5%

15%

12.5%

10%

7.5%

0.5

0.4

0.3

0.2

0.1

-0.1

-0.2

-0.3

-0.4

-0.5

-45 èC

2.5%

25 èC

125 èC

-15 -12

-9

-6

-3

-250 -200 -150 -100 -50

50 100 150 200 250

Common Mode Voltage (V)

Gain Error (ppm)

D026

D027

V_S= ±15 V

N = 94

G = 1

Mean = –48 ppm

Std. Dev. = 58 ppm

图 27. Input Bias Current vs Common-Mode Voltage

图 28. Typical Distribution of Gain Error G = 1

20%

-20

-30

-40

-50

-60

-70

18%

16%

14%

12%

10%

-80

-50

-300 -150

150

300

450

600

750

900

-25

100

125

150

Gain Error (ppm)

Temperature (èC)

D028

D029

N = 94

G = 10

Mean = 286 ppm

Std. Dev. = 204 ppm

G = 1

图 29. Typical Distribution of Gain Error G = 10

图 30. Gain Error vs Temperature

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Typical Characteristics (接下页)

at T_A= 25°C, V_S= ±15 V, R_L= 10 kΩ, V_REF= 0 V, and G = 1 (unless otherwise noted)

500

450

400

350

300

250

200

150

100

0.5

0.45

0.4

0.35

0.3

VS = ê 15 V

VS = ê 2.25 V

0.25

-50

-25

100

125

150

-60

-30

120

150

Temperature (èC)

D030

D031

G = 10

图 31. Gain Error vs Temperature

图 32. Supply Current vs Temperature

0.8

0.6

0.4

0.2

LREG

-1

-2

-3

-4

-5

-0.2

-0.4

-0.6

-0.8

-1

-10

-8

-6

-4

-2

-10

-8

-6

-4

-2

Output Voltage (V)

D032

D033

G = 1

G = 10

图 33. Gain Nonlinearity

图 34. Gain Nonlinearity

175

150

125

100

150

125

100

-40 èC

25 èC

-40 èC

25 èC

85 èC

125 èC

-25

-50

-75

-25

-50

-15

-14.6 -14.2 -13.8 -13.4

-13

-12.6 -12.2 -11.8

12.4

12.8

13.2

13.6

14.4

14.8

Input Common-Mode Voltage (V)

D034

D035

图 35. Offset Voltage vs Negative Common-Mode Voltage

图 36. Offset Voltage vs Positive Common-Mode Voltage

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Typical Characteristics (接下页)

at T_A= 25°C, V_S= ±15 V, R_L= 10 kΩ, V_REF= 0 V, and G = 1 (unless otherwise noted)

14.9

14.8

14.7

14.6

14.5

14.4

14.3

14.2

14.1

-14

-14.1

-14.2

-14.3

-14.4

-14.5

-14.6

-14.7

-14.8

-14.9

-15

-40èC

25èC

85èC

125èC

-40èC

25èC

85èC

125èC

Output Current (mA)

D036

D037

图 37. Positive Output Voltage Swing vs Output Current

图 38. Negative Output Voltage Swing vs Output Current

I_{SC, Source}

I_{SC, Sink}

VS = ê15 V

VS = ê5 V

-10

-20

-30

-40

-50

-60

-50 -30 -10 10

90 110 130 150

100

10k

100k

10M

Temperature (èC)

Frequency (Hz)

D038

D039

图 39. Short Circuit Current vs Temperature

图 40. Large-Signal Frequency Response

0.1

-40

-60

-80

-100

G = 1

G = 10

G = 100

0.01

Positive

Negative

0.001

100

10k

100k

100

Frequency (Hz)

Cload (pF)

D040

D041

500-kHz measurement bandwidth

1-V_RMSoutput voltage 100-kΩ load

图 41. THD+N vs Frequency

图 42. Overshoot vs Capacitive Loads

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Typical Characteristics (接下页)

at T_A= 25°C, V_S= ±15 V, R_L= 10 kΩ, V_REF= 0 V, and G = 1 (unless otherwise noted)

100

-20

-40

-60

-80

-100

-20

-40

-60

-80

-100

-5

-2.5

2.5

7.5

12.5

-5

-2.5

2.5

7.5

12.5

Time (ms)

D042

D043

G = 1

R_L= 10 kΩ

C_L= 100 pF

G = 10

R_L= 10 kΩ

C_L= 100 pF

图 43. Small-Signal Response

图 44. Small-Signal Response

100

-20

-40

-60

-80

-100

-20

-40

-60

-80

-100

-5

-2.5

2.5

7.5

12.5

C_L= 100 pF

图 45. Small-Signal Response

-25 -12.5

12.5 25 37.5 50 62.5 75 87.5 100

Time (ms)

D044

D045

G = 100

R_L= 10 kΩ

G = 1000

R_L= 10 kΩ

C_L= 100 pF

图 46. Small-Signal Response

Output

Input

100

0.1

Time (10 µs/div)

100

10k

100k

10M

Frequency (Hz)

D046

C0xx

图 48. Closed-Loop Output Impedance

图 47. Large Signal Step Response

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Typical Characteristics (接下页)

at T_A= 25°C, V_S= ±15 V, R_L= 10 kΩ, V_REF= 0 V, and G = 1 (unless otherwise noted)

100

140

120

100

10M

100M

Frequency (Hz)

10G

10M

100M

Frequency (Hz)

10G

D047

D048

图 49. Differential-Mode EMI Rejection Ratio

图 50. Common-Mode EMI Rejection Ratio

VREF = 0 V

VREF = 2.5 V

Output Voltage (V)

G = 1

Output Voltage (V)

C006

V_S= 5 V

G = 100

图 51. Input Common-Mode Voltage vs Output Voltage

图 52. Input Common-Mode Voltage vs Output Voltage

-5

-1

-2

-3

-10

-15

G = 1

-4

G = 100

-20

G = 100

-5

±±

±4

±2

Output Voltage (V)

C006

C00±

V_S= ±5 V

V_REF= 0 V

V_S= ±15 V

V_REF= 0 V

图 53. Input Common-Mode Voltage vs Output Voltage

图 54. Input Common-Mode Voltage vs Output Voltage

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8 Detailed Description

8.1 Overview

The INA818 is a monolithic, precision instrumentation amplifier incorporating a current-feedback input stage and

a four-resistor difference amplifier output stage. The functional block diagram in the next section shows how the

differential input voltage is buffered by transistors Q₁and Q₂and is forced across resistor R_G, which causes a

signal current to flow through resistors R_G, R₁, and R₂. The output difference amplifier, A₃, removes the common-

mode component of the input signal and refers the output signal to the REF pin. The V_BEand voltage drop

across R₁and R₂produce output voltages on A₁and A₂that are approximately 0.8 V lower than the input

voltages.

Each input is protected by two field-effect transistors (FETs) that provide a low series resistance under normal

signal conditions, and preserve excellent noise performance. When excessive voltage is applied, these

transistors limit input current to approximately 8 mA.

8.2 Functional Block Diagram

+V_S

V_B

R_B

I_BCancellation

40 kꢀ

-V_S+V_S

40 kꢀ

A₁

A₂

A₃

OUT

REF

40 kꢀ

+V_S

-V_S+V_S

Q₂

Q₁

Super-ꢁ

-IN

+IN

NPN

Overvoltage

Protection

+V_S

Overvoltage

Protection

R₂

25 kꢀ

R₁

25 kꢀ

R_G

(External)

-V_S

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8.3 Feature Description

8.3.1 Setting the Gain

图 55 shows that the gain of the INA818 is set by a single external resistor (R_G) connected between the RG pins

(pins 1 and 8).

V+

+VS

Overvoltage

Protection

40 kꢀ

-IN

50 kW

R_G

25 kꢀ

OUT

REF

G = 1+

R_G

V_O= G V_+IN- V_-IN+ V

(

)

REF

+IN

Overvoltage

Protection

40 kꢀ

-VS

V-

图 55. Simplified Diagram of the INA818 With Gain and Output Equations

The value of R_Gis selected according to 公式 1:

50 kW

R_G

G = 1+

(1)

表 2 lists several commonly-used gains and resistor values. The 50-kΩ term in 公式 1 comes from the sum of the

two internal 25-kΩ feedback resistors. These on-chip resistors are laser-trimmed to accurate absolute values.

The accuracy and temperature coefficients of these resistors are included in the gain accuracy and drift

specifications of the INA818. As shown in 图 55 and explained in more details in the Layout section, make sure

to connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground that are placed as

close to the device as possible.

表 2. Commonly-Used Gains and Resistor Values

DESIRED GAIN

R_G(Ω)

NEAREST 1% R_G(Ω)

49.9 k

12.4 k

5.49 k

2.61 k

1.02 k

511

50 k

12.5 k

5.556 k

2.632 k

1.02 k

505.1

251.3

100.2

50.05

100

200

500

1000

249

100

49.9

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8.3.1.1 Gain Drift

The stability and temperature drift of the external gain setting resistor (R_G) also affects gain. The contribution of

R_Gto gain accuracy and drift is determined from 公式 1.

The best gain drift of 5 ppm/℃ (maximum) is achieved when the INA818 uses G = 1 without R_Gconnected. In

this case, gain drift is limited by the mismatch of the temperature coefficient of the integrated 40-kΩ resistors in

the differential amplifier (A₃). At gains greater than 1, gain drift increases as a result of the individual drift of the

25-kΩ resistors in the feedback of A₁and A₂, relative to the drift of the external gain resistor (R_G.) The low

temperature coefficient of the internal feedback resistors improves the overall temperature stability of applications

using gains greater than 1 V/V over alternate solutions.

Low resistor values required for high gain make wiring resistance an important consideration. Sockets add to the

wiring resistance and contribute additional gain error (such as a possible unstable gain error) at gains of

approximately 100 or greater. To maintain stability, avoid parasitic capacitance of more than a few picofarads at

R_Gconnections. Careful matching of any parasitics on the R_Gpins maintains optimal CMRR over frequency.

8.3.2 EMI Rejection

Texas Instruments developed a method to accurately measure the immunity of an amplifier over a broad

frequency spectrum extending from 10 MHz to 6 GHz. This method uses an EMI rejection ratio (EMIRR) to

quantify the ability of the INA818 to reject EMI. The offset resulting from an input EMI signal is calculated using

公式 2:

EMIRR (dB)

≈

’

≈

∆

’

V_{RF_PEAK}

100 mV_P

∆

◊

DV_OS

∂10

∆

◊

where

•

V_{RF_PEAK}is the peak amplitude of the input EMI signal.

(2)

图 56 and 图 57 show the INA818 EMIRR graphs for differential and common-mode EMI rejection across this

frequency range. 表 3 lists the EMIRR values for the INA818 at frequencies commonly encountered in real-world

applications. Applications listed in 表 3 are centered on or operated near the frequency shown. Depending on the

end-system requirements, additional EMI filters may be required near the signal inputs of the system.

Incorporating known good practices, such as using short traces, low-pass filters, and damping resistors

combined with parallel and shielded signal routing may also be required.

140

120

100

10M

100M

Frequency (Hz)

10G

10M

100M

Frequency (Hz)

10G

D048

D047

图 56. Common-Mode EMIRR Testing

图 57. Differential Mode EMIRR Testing

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表 3. INA818 EMIRR for Frequencies of Interest

DIFFERENTIAL

EMIRR

COMMON-MODE

EMIRR

FREQUENCY

400 MHz

APPLICATION OR ALLOCATION

Mobile radio, mobile satellite, space operation, weather, radar, ultrahigh-frequency (UHF)

applications

52 dB

55 dB

58 dB

80 dB

71 dB

73 dB

Global system for mobile communications (GSM) applications, radio communication, navigation,

GPS (up to 1.6 GHz), GSM, aeronautical mobile, UHF applications

900 MHz

GSM applications, mobile personal communications, broadband, satellite,

L-band (1 GHz to 2 GHz)

1.8 GHz

802.11b, 802.11g, 802.11n, Bluetooth^®, mobile personal communications, industrial, scientific

and medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)

2.4 GHz

3.6 GHz

5 GHz

59 dB

78 dB

70 dB

95 dB

96 dB

Radiolocation, aero communication and navigation, satellite, mobile, S-band

802.11a, 802.11n, aero communication and navigation, mobile communication, space and

satellite operation, C-band (4 GHz to 8 GHz)

100 dB

8.3.3 Input Common-Mode Range

The linear input voltage range of the INA818 input circuitry extends within 1.5 V (typical) of both power supplies

and maintains excellent common-mode rejection throughout this range. The common-mode range for the most

common operating conditions are shown in 图 58, 图 53, and 图 54. The common-mode range for other

operating conditions is best calculated using the Common-Mode Input Range Calculator for Instrumentation

Amplifiers.

VREF = 0 V

VREF = 2.5 V

Output Voltage (V)

C006

V_S= 5 V

G = 1

V_S= 5 V

G = 100

图 58. Input Common-Mode Voltage vs Output Voltage

图 59. Input Common-Mode Voltage vs Output Voltage

-5

-1

-2

-3

-10

-15

-20

G = 1

-4

G = 100

-5

±±

±4

±2

Output Voltage (V)

C006

C00±

V_S= ±5 V

V_REF= 0 V

V_S= ±15 V

V_REF= 0 V

图 60. Input Common-Mode Voltage vs Output Voltage

图 61. Input Common-Mode Voltage vs Output Voltage

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8.3.4 Input Protection

The inputs of the INA818 device are individually protected for voltages up to ±60 V. For example, a condition of

–60 V on one input and +60 V on the other input does not cause damage. Internal circuitry on each input

provides low series impedance under normal signal conditions. If the input is overloaded, the protection circuitry

limits the input current to a value of approximately 8 mA.

ZD1

+V_S

Overvoltage

Protection

Input Voltage

Source

Input Transistor

-V_S

ZD2

-V

图 62. Input Current Path During an Overvoltage Condition

During an input overvoltage condition, current flows through the input protection diodes into the power supplies;

see 图 62. If the power supplies are unable to sink current, then Zener diode clamps (ZD1 and ZD2 in 图 62)

must be placed on the power supplies to provide a current pathway to ground. 图 63 shows the input current for

input voltages from –50 V to +50 V when the INA818 is powered by ±15-V supplies.

-2

-4

-6

-8

-10

-4

-8

-12

-16

-20

Input Current

Output Voltage

-50 -40 -30 -20 -10

Input Voltage (V)

D015

图 63. Input Current vs Input Overvoltage

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8.3.5 Operating Voltage

The INA818 operates over a power-supply range of 4.5 V to 36 V (±2.25 V to ±18 V).

CAUTION

Supply voltages higher than 40 V (±20 V) can permanently damage the device.

Parameters that vary over supply voltage or temperature are shown in Typical

Characteristics .

8.3.6 Error Sources

Most modern signal-conditioning systems calibrate errors at room temperature. However, calibration of errors

that result from a change in temperature is normally difficult and costly. Therefore, minimize these errors by

choosing high-precision components, such as the INA818, that have improved specifications in critical areas that

impact the precision of the overall system. 图 64 shows an example application.

+15 V

R_S+

1 kꢀ

V_OUT

1 V

V_DIFF= V_OUT/ G

INA

5.49 kꢀ

R_Sœ

0.99 kꢀ

VCM

10 V

œ15 V

图 64. Example Application With G = 10 V/V and 1-V Output Voltage

Resistor-adjustable devices (such as the INA818) show the lowest gain error in G = 1 because of the inherently

well-matched drift of the internal resistors of the differential amplifier. At gains greater than 1 (for instance, G =

10 V/V or G = 100 V/V), the gain error becomes a significant error source because of the contribution of the

resistor drift of the 25-kΩ feedback resistors in conjunction with the external gain resistor. Except for very high

gain applications, the gain drift is by far the largest error contributor compared to other drift errors, such as offset

drift.

The INA818 offers excellent gain error over temperature for both G > 1 and G = 1 (no external gain resistor). 表 5

summarizes the major error sources in common INA applications and compares the three cases of G = 1 (no

external resistor) and G = 10 (5.49-kΩ external resistor) and G = 100 (511-Ω external resistor). All calculations

are assuming an output voltage of V_OUT= 1 V. Thus, the input signal V_DIFF(given by V_DIFF= V_OUT/ G) exhibits

smaller and smaller amplitudes with increasing gain G. V_DIFF= 1 mV at G = 1000 in this example. All calculations

refer the error to the input for easy comparison and system evaluation. As 表 5 shows, errors generated by the

input stage (such as input offset voltage) are more dominant at higher gain, while the effects of output stage are

suppressed because they are divided by the gain when referring them back to the input. The gain error and gain

drift error are much more significant for gains greater than 1 because of the contribution of the resistor drift of the

25-kΩ feedback resistors in conjunction with the external gain resistor. In most applications, static errors

(absolute accuracy errors) can readily be removed during calibration in production, while the drift errors are the

key factors limiting overall system performance.

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表 4. System Specifications for Error Calculation

QUANTITY

VALUE

UNIT

V_OUT

VCM

R_S+

R_S–

1000

999

0.01

RG tolerance

RG drift

ppm/°C

°C

Temperature range upper limit

105

表 5. Error Calculation

INA818 VALUES

G = 1

G = 100

ERROR

(ppm)

G = 1000

ERROR

(ppm)

ERROR SOURCE

ERROR CALCULATION

SPECIFICATION

UNIT

ERROR

(ppm)

ABSOLUTE ACCURACY AT 25°C

Input offset voltage

V_OSI/ V_DIFF

300

0.5

µV

300

350

300

3500

300

Output offset voltage

V_OSO/ (G × V_DIFF)

Input offset current

I_OS× maximum (R_S+, R_S–) / V_DIFF

90 (G = 1),

110 (G = 10),

130 (G = 100)

V_CM/ (10^CMRR/20× V_DIFF

)

CMRR (min)

PSRR (min)

316

110 (G = 1),

114 (G = 10),

130 (G = 100)

(V_CC-V_S)/ (10^PSRR/20× V_DIFF

)

0.02 (G = 1),

0.15 (G = 10, 100)

GE(%) × 10⁴

sum of all errors

Gain error from INA (max)

—

200

100

955

1500

100

1500

100

Gain error from external resistor RG (max)

0.01

—

Total absolute accuracy error (ppm) at 25°C,

worst case

2591

5798

Total absolute accuracy error (ppm) at 25°C,

average

rms sum of all errors

GTC × (T_A– 25)

—

491

1604

3835

DRIFT TO 105°C

5 (G = 1),

35 (G = 10, 100)

Gain drift from INA (max)

ppm/°C

400

2800

Gain drift from external resistor RG (max)

Input offset voltage drift (max)

Output offset voltage drift

GTC × (T_A– 25)

0.4

ppm/°C

µV/°C

800

320

400

800

3200

400

(V_{OSI_TC}/ V_DIFF) × (T_A– 25)

[V_{OSO_TC}/ ( G × V_DIFF)] × (T_A– 25)

400

I_{OS_TC}× maximum (R_S+, R_S–) ×

(T_A– 25) / V_DIFF

Offset current drift

pA/°C

160

Total drift error to 105°C (ppm), worst case

Total drift error to 105°C (ppm), typical

RESOLUTION

sum of all errors

—

1634

980

4336

2957

7360

4348

rms sum of all errors

10 (G = 1, 10),

15 (G = 100)

Gain nonlinearity

ppm of FS

µV_PP

1204

0.3

1070

3941

e_NO

e_NI= 8,

e_NO= 90

(e_NI

Voltage noise (at 1 kHz)

V_DIFF

I_N× maximum (R_S+, R_S–) × √BW /

Current noise (at 1kHz)

0.13

pA/√Hz

V_DIFF

Total resolution error (ppm), worst case

Total resolution error (ppm), typical

TOTAL ERROR

sum of all errors

—

1214

1204

1080

1070

3956

3941

rms sum of all errors

Total error (ppm), worst case

Total error (ppm), typical

sum of all errors

—

3802

1628

8007

3530

17113

7010

rms sum of all errors

INA818

ZHCSJM1A –APRIL 2019–REVISED JUNE 2019

www.ti.com.cn

8.4 Device Functional Modes

The INA818 has a single functional mode and operates when the power-supply voltage is greater than 4.5 V

(±2.25 V). The maximum power-supply voltage for the INA818 is 36 V (±18 V.)

9 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.1.1 Reference Pin

The output voltage of the INA818 is developed with respect to the voltage on the reference pin, REF. In dual-

supply operation, REF (pin 6) is connected to the low-impedance system ground. In single-supply operation,

offsetting the output signal to a precise midsupply level is useful (for example, 2.5 V in a 5-V supply

environment). To accomplish this level shift, a voltage source must be connected to the REF pin to level-shift the

output so that the INA818 drives a single-supply ADC.

The voltage source applied to the reference pin must have a low output impedance. As shown in 图 65, any

resistance at the reference pin (shown as R_REFin 图 65) is in series with an internal 40-kΩ resistor.

V+

+VS

Overvoltage

Protection

40 kꢀ

-IN

25 kꢀ

R_G

OUT

REF

+IN

Overvoltage

Protection

R_REF

40 kꢀ

-VS

V-

图 65. Parasitic Resistance Shown at the Reference Pin

INA818

www.ti.com.cn

ZHCSJM1A –APRIL 2019–REVISED JUNE 2019

Application Information (接下页)

The parasitic resistance at the reference pin (R_REF) creates an imbalance in the four resistors of the internal

difference amplifier, which degrades the common-mode rejection ratio (CMRR). 图 66 shows the degradation in

CMRR of the INA818 as a result of increased resistance at the reference pin. For the best performance, keep the

source impedance to the REF pin (R_REF) below 5 Ω.

120

100

0 Ω

5 Ω

10 Ω

15 Ω

20 Ω

100

Frequency (Hz)

10k

图 66. The Effect of Increasing Resistance at the Reference Pin

Voltage-reference devices are a suitable option for providing a low-impedance voltage source for the reference

pin. However, if a resistor voltage divider generates a reference voltage, the divider must be buffered by an op

amp, as 图 67 shows, in order to avoid CMRR degradation.

5 V

+IN

R_G

INA818

OUT

œIN

5 V

100 kꢀ

OPA191

1 ꢁF

100 kꢀ

图 67. Using an Op Amp to Buffer Reference Voltages

INA818

ZHCSJM1A –APRIL 2019–REVISED JUNE 2019

www.ti.com.cn

Application Information (接下页)

9.1.2 Input Bias Current Return Path

The input impedance of the INA818 is extremely high—approximately 100 GΩ. However, a path must be

provided for the input bias current of both inputs. This input bias current is typically 150 pA. High input

impedance means that this input bias current changes very little with varying input voltage.

For proper operation, input circuitry must provide a path for input bias current. 图 68 shows various provisions for

an input bias current path. Without a bias current path, the inputs float to a potential that exceeds the common-

mode range of the INA818, and the input amplifiers saturate. If the differential source resistance is low, the bias

current return path can connect to one input (as shown in the thermocouple example in 图 68). With a higher

source impedance, using two equal resistors provides a balanced input with possible advantages of a lower input

offset voltage as a result of bias current and better high-frequency common-mode rejection.

Microphone,

Hydrophone,

and So Forth

TI Device

47 kW

Thermocouple

TI Device

10 kW

TI Device

Center tap provides

bias current return.

图 68. Providing an Input Common-Mode Current Path

INA818

www.ti.com.cn

ZHCSJM1A –APRIL 2019–REVISED JUNE 2019

9.2 Typical Applications

9.2.1 Three-Pin Programmable Logic Controller (PLC)

图 69 shows a three-pin programmable-logic controller (PLC) design for the INA818. This PLC reference design

accepts inputs of ±10 V or ±20 mA. The output is a single-ended voltage of 2.5 V ±2.3 V (or 200 mV to 4.8 V).

Many PLCs typically have these input and output ranges.

±10 V

15 V

REF5025

= 100 kΩ

= 4.17 kΩ

V_OUT

GND

V_IN

1 ꢀF

15 V

±20 mA

-IN

+VS

INA818

-VS

REF

2.5 V ± 2.3 V

OUT

= 10.5 kΩ

OUT

20 Ω

+IN

-15 V

图 69. PLC Input (±10 V, 4 mA to 20 mA)

9.2.1.1 Design Requirements

For this application, the design requirements are as follows:

•

4-mA to 20-mA input with less than 20-Ω burden

±20-mA input with less than 20-Ω burden

±10-V input with impedance of approximately 100 kΩ

Maximum 4-mA to 20-mA or ±20-mA burden voltage equal to ±0.4 V

Output range within 0 V to 5 V

9.2.1.2 Detailed Design Procedure

There are two modes of operation for the circuit shown in 图 69: current input and voltage input. This design

requires R₁>> R₂>> R₃. Given this relationship, 公式 3 calculates the current input mode transfer function.

V_OUT-I= V_D´ G + V_REF= -(I_IN´ R₃) ´ G + V_REF

where

•

G represents the gain of the instrumentation amplifier

V_Drepresents the differential voltage at the INA818 inputs

V_REFis the voltage at the INA818 REF pin

I_INis the input current

(3)

公式 4 shows the transfer function for the voltage input mode.

R₂

V_OUT-V= V_D´ G + V_REF= - V_IN

´ G + V_REF

R₁+ R₂

where

•

V_INis the input voltage

(4)

INA818

ZHCSJM1A –APRIL 2019–REVISED JUNE 2019

www.ti.com.cn

Typical Applications (接下页)

R₁sets the input impedance of the voltage input mode. The minimum typical input impedance is 100 kΩ. 100 kΩ

is selected for R₁because increasing the R₁value also increases noise. The value of R₃must be extremely

small compared to R₁and R₂. 20 Ω for R₃is selected because that resistance value is much smaller than R₁and

yields an input voltage of ±400 mV when operated in current mode (±20 mA).

Use 公式 5 to calculate R₂given V_D= ±400 mV, V_IN= ±10 V, and R₁= 100 kΩ.

R₂

R₁´ V_D

V_D= V_IN´

® R₂=

= 4.167 kW

R₁+ R₂

V_IN- V_D

(5)

The value obtained from 公式 5 is not a standard 0.1% value, so 4.17 kΩ is selected. R₁and R₂also use 0.1%

tolerance resistors to minimize error.

Use 公式 6 to calculate the ideal gain of the instrumentation amplifier.

_OUT- V_REF

4.8 V - 2.5 V

G =

= 5.75

V_D

400 mV

(6)

(7)

公式 7 calculates the gain-setting resistor value using the INA818 gain equation, 公式 1.

50 kW 50 kW

R_G

= 10.5 kW

G -1 5.75 -1

10.5 kΩ is a standard 0.1% resistor value that can be used in this design.

9.2.1.3 Application Curves

图 70 and 图 71 show typical characteristic curves for the circuit in 图 69.

C001

-10

-5

-20

-10

Input Voltage (V)

Input Current (mA)

C001

图 70. PLC Output Voltage vs Input Voltage

图 71. PLC Output Voltage vs Input Current

INA818

www.ti.com.cn

ZHCSJM1A –APRIL 2019–REVISED JUNE 2019

Typical Applications (接下页)

9.2.2 Resistance Temperature Detector Interface

图 72 illustrates a 3-wire interface circuit for resistance temperature detectors (RTDs). The circuit incorporates

analog linearization and has an output voltage range from 0 V to 5 V. The linearization technique employed is

described in the Analog linearization of resistance temperature detectors analog application journal. Series and

parallel combinations of standard 1% resistor values are used to achieve less than 0.02°C of error over a 200°C

temperature span.

15 V

REF5050

V_OUT

GND

V_IN

4.99

kꢀ

4.99

kꢀ

-IN

V_OUT

1.13

kꢀ

100

kꢀ

2.87

kꢀ

0 V at 0°C

5 V at 200°C

25 mV/°C

100 ꢀ

INA818

OUT

+IN

Pt100 RTD

100 ꢀ

-15 V

105 kꢀ 1.18 kꢀ

图 72. A 3-Wire Interface for RTDs With Analog Linearization

4.5

0.018

0.016

0.014

0.012

0.01

3.5

2.5

0.008

0.006

0.004

0.002

1.5

0.5

100

150

200

100

150

200

Temperature (°C)

C001

图 73. Transfer Function of a 3-Wire RTD Interface

图 74. Temperature Error Over the Full Temperature Range

INA818

ZHCSJM1A –APRIL 2019–REVISED JUNE 2019

www.ti.com.cn

10 Power Supply Recommendations

The nominal performance of the INA818 is specified with a supply voltage of ±15 V and midsupply reference

voltage. The device can also be operated using power supplies from ±2.25 V (4.5 V) to ±18 V (36 V) and non-

midsupply reference voltages with excellent performance. Parameters that can vary significantly with operating

voltage and reference voltage are shown in the Typical Characteristics section.

11 Layout

11.1 Layout Guidelines

Attention to good layout practices is always recommended. For best operational performance of the device, use

good PCB layout practices, including:

•

Take care to make sure that both input paths are well-matched for source impedance and capacitance to

avoid converting common-mode signals into differential signals. Even slight mismatch in parasitic capacitance

at the gain setting pins can degrade CMRR over frequency. For example, in applications that implement gain

switching using switches or PhotoMOS^®relays to change the value of R_G, select the component so that the

switch capacitance is as small as possible and most importantly so that capacitance mismatch between the

RG pins is minimized.

•

Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of the device

itself. Bypass capacitors reduce the coupled noise by providing low-impedance power sources local to the

analog circuitry.

–

Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as

close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-

supply applications.

•

To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If

these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better than in

parallel with the noisy trace.

•

Place the external components as close to the device as possible. As shown in 图 75, keeping R_Gclose to

the pins minimizes parasitic capacitance.

Keep the traces as short as possible.

INA818

www.ti.com.cn

ZHCSJM1A –APRIL 2019–REVISED JUNE 2019

11.2 Layout Example

+IN

-IN

INA818

OUT

Ground plane

removed at gain

-V

resistor to minimize

parasitic capacitance

Use ground pours for

shielding the input

signal pairs

GND

œIN

+IN

œIN

+IN

-VS

+VS

OUT

REF

Input traces routed

adjacent to each other

OUT

Low-impedance

connection for

reference terminal

GND

Place bypass

capacitors as close to

IC as possible

-V

图 75. Example Schematic and Associated PCB Layout

INA818

ZHCSJM1A –APRIL 2019–REVISED JUNE 2019

www.ti.com.cn

12 器件和文档支持

12.1 文档支持

12.1.1 相关文档

请参阅如下相关文档：

•

德州仪器 (TI)，《通用仪表放大器 EVM》用户指南

德州仪器 (TI)，《仪表放大器的综合误差计算》应用手册

12.2 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.3 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.4 商标

E2E is a trademark of Texas Instruments.

Bluetooth is a registered trademark of Bluetooth SIG, Inc.

PhotoMOS is a registered trademark of Panasonic Electric Works Europe AG.

All other trademarks are the property of their respective owners.

12.5 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

12.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

INA818ID

ACTIVE

SOIC

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

INA818

INA818IDR

2500 RoHS & Green

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

INA818IDR

SOIC

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SOIC

SPQ

Length (mm) Width (mm) Height (mm)

356.0 356.0 35.0

INA818IDR

2500

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

TUBE

T - Tube

height

L - Tube length

W - Tube

width

B - Alignment groove width

*All dimensions are nominal

Device

Package Name Package Type

SOIC

Pins

SPQ

L (mm)

W (mm)

T (µm)

B (mm)

INA818ID

506.6

3940

4.32

Pack Materials-Page 3

PACKAGE OUTLINE

D0008A

SOIC - 1.75 mm max height

SCALE 2.800

SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE

.228-.244 TYP

[5.80-6.19]

.004 [0.1] C

PIN 1 ID AREA

6X .050

[1.27]

.189-.197

[4.81-5.00]

NOTE 3

.150

[3.81]

4X (0 -15 )

8X .012-.020

[0.31-0.51]

.150-.157

[3.81-3.98]

NOTE 4

.069 MAX

[1.75]

.010 [0.25]

C A B

.005-.010 TYP

[0.13-0.25]

4X (0 -15 )

SEE DETAIL A

.010

[0.25]

.004-.010

[0.11-0.25]

0 - 8

.016-.050

[0.41-1.27]

DETAIL A

TYPICAL

(.041)

[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

www.ti.com

EXAMPLE BOARD LAYOUT

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

SEE

DETAILS

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

6X (.050 )

[1.27]

(.213)

[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED

METAL

EXPOSED

METAL

.0028 MAX

[0.07]

.0028 MIN

[0.07]

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

6X (.050 )

[1.27]

(.213)

[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

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TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

INA818 [TI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E