INA819ID [TI]
2MHz、35μV 失调电压、8nV/√Hz 噪声、350µA 功耗、精密（增益引脚 2、3）仪表放大器 | D | 8 | -40 to 125;
| 型号： | INA819ID |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2MHz、35μV 失调电压、8nV/√Hz 噪声、350µA 功耗、精密（增益引脚 2、3）仪表放大器 | D | 8 | -40 to 125 放大器 仪表 仪表放大器 |
| 文件： | 总51页 (文件大小：2724K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INA819
ZHCSJ44D –DECEMBER 2018 –REVISED APRIL 2022
INA819 35 μV 失调电压、8 nV/√Hz 噪声、低功耗、精密仪表放大器
1 特性
3 说明
• 低失调电压：10 µV（典型值），35 µV（最大值）
INA819 是一款高精度仪表放大器，可提供低功耗并且
可在极宽的单电源或双电源电压范围内工作。可通过单
个外部电阻器在 1 到 10,000 范围内设置任意增益。由
于采用超 β 输入晶体管（这些晶体管可提供极低的输
入失调电压、失调电压漂移、输入偏置电流、输入电压
和电流噪声），该器件可提供出色的精度。附加电路可
以为输入提供高达±60V 的过压保护。
• 增益漂移：5 ppm/°C (G = 1)、
35 ppm/°C (G > 1)（最大值）
• 噪声：8 nV/√Hz
• 带宽：2 MHz (G = 1)、270 kHz (G = 100)
• 在1 nF 容性负载下保持稳定
• 输入保护电压高达±60V
• 共模抑制：110 dB，G = 10（最小值）
• 电源抑制：110 dB，G = 1（最小值）
• 电源电流：385 µA（最大值）
• 电源电压范围：
INA819 经过优化，可提供较高的共模抑制比。当 G =
1 时，整个输入共模范围内的共模抑制比超过 90 dB。
根据设计，此器件在低电压下运行，由 4.5V 单电源和
高达±18V 的双电源供电。
– 单电源：4.5V 至36V
– 双电源：±2.25V 至±18V
• 额定温度范围：–40°C 至+125°C
• 封装：8 引脚SOIC、VSSOP、WSON
INA819 采用 8 引脚 SOIC、VSSOP 和WSON 封装，
并且额定工作温度范围为–40°C 至+125°C。
器件信息(1)
封装尺寸（标称值）
器件型号
封装
SOIC (8)
2 应用
4.90mm × 3.91mm
3.00mm × 3.00mm
3.00mm × 3.00mm
• 模拟输入模块
• 流量发送器
• 电池测试
• LCD 测试
INA819
VSSOP (8)
WSON (8)
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
• 心电图(ECG)
• 外科手术设备
• 过程分析（pH、气体、浓度、力和湿度）
+VS
25%
22.5%
20%
17.5%
15%
12.5%
10%
7.5%
5%
Overvoltage
40 k
+
–
40 k
–IN
RG
RG
Protection
–
+
25 k
25 k
OUT
REF
RG
+IN
–
+
Overvoltage
Protection
40 k
40 k
2.5%
0
–VS
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
50 k
G = 1 +
VO = G(V+IN – V–IN) + VREF
Input Stage Offset Voltage Drift (mV/èC)
D002
RG
输入阶段失调电压漂移的典型分布
INA819 简化版内部原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS959
INA819
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ZHCSJ44D –DECEMBER 2018 –REVISED APRIL 2022
Table of Contents
9 Application and Implementation..................................27
9.1 Application Information............................................. 27
9.2 Typical Applications.................................................. 30
10 Power Supply Recommendations..............................33
11 Layout...........................................................................33
11.1 Layout Guidelines................................................... 33
11.2 Layout Example...................................................... 34
12 Device and Documentation Support..........................35
12.1 Device Support....................................................... 35
12.2 Documentation Support.......................................... 35
12.3 接收文档更新通知................................................... 35
12.4 支持资源..................................................................35
12.5 Trademarks.............................................................35
12.6 Electrostatic Discharge Caution..............................36
12.7 术语表..................................................................... 36
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings .............................................................. 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................5
7.5 Electrical Characteristics.............................................6
7.6 Typical Characteristics................................................8
8 Detailed Description......................................................19
8.1 Overview...................................................................19
8.2 Functional Block Diagram.........................................19
8.3 Feature Description...................................................20
8.4 Device Functional Modes..........................................27
Information.................................................................... 36
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision C (June 2020) to Revision D (April 2022)
Page
• Changed input stage offset voltage specification for INA819DRG from 10 µV typical to 6 µV typical, and from
35 µV maximum to 30 µV maximum, in Typical Characteristics ........................................................................6
• Changed maximum input stage offset voltage vs temperature specification for INA819DRG from 0.4 µV/°C to
0.35 µV/°C in Typical Characteristics .................................................................................................................6
• Changed Figures 7-10 and 7-11 to correct units from nA to pA......................................................................... 8
• Changed input common-mode range calculator link from outdated Common-Mode Input Range Calculator for
Instrumentation Amplifiers to Analog Engineers Calculator..............................................................................22
Changes from Revision B (July 2019) to Revision C (June 2020)
Page
• 向数据表添加了DRG (WSON) 封装和相关内容.................................................................................................1
• Added row for thermal pad to Pin Functions table .............................................................................................4
• Added bullet regarding exposed thermal pad to end of Layout Guidelines section .........................................33
Changes from Revision A (May 2019) to Revision B (July 2019)
Page
• 将DGK (VSSOP) 封装从预告信息（预发布）更改为量产数据（正在供货）.....................................................1
Changes from Revision * (December 2018) to Revision A (April 2019)
Page
• 向数据表添加了8 引脚DGK (VSSOP) 封装预告信息和相关内容...................................................................... 1
• 更改了应用要点..................................................................................................................................................1
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ZHCSJ44D –DECEMBER 2018 –REVISED APRIL 2022
5 Device Comparison Table
DEVICE
DESCRIPTION
GAIN EQUATION
RG PINS AT PIN
35-µV Offset, 0.4-µV/°C VOS Drift, 8-nV/√Hz Noise, Low-Power,
Precision Instrumentation Amplifier
INA819
INA818
INA821
INA828
INA333
PGA280
2, 3
G = 1 + 50 kΩ/ RG
35-µV Offset, 0.4-µV/°C VOS Drift, 8-nV/√Hz Noise, Low-Power,
Precision Instrumentation Amplifier
1, 8
2, 3
1, 8
1, 8
N/A
G = 1 + 50 kΩ/ RG
G = 1 + 49.4 kΩ/ RG
35-µV Offset, 0.4-µV/°C VOS Drift, 7-nV/√Hz Noise, High-
Bandwidth, Precision Instrumentation Amplifier
50-µV Offset, 0.5-µV/°C VOS Drift, 7-nV/√Hz Noise, Low-Power,
Precision Instrumentation Amplifier
G = 1 + 50 kΩ/ RG
G = 1 + 100 kΩ/ RG
Digital programmable
25-µV VOS, 0.1-µV/°C VOS Drift, 1.8-V to 5-V, RRO, 50-µA IQ,
Chopper-Stabilized INA
20-mV to ±10-V Programmable Gain IA With 3-V or 5-V Differential
Output; Analog Supply up to ±18 V
G = 0.2 V Differential Amplifier for ±10-V to 3-V and 5-V
Conversion
INA159
G = 0.2 V/V
N/A
N/A
PGA112
Precision Programmable Gain Op Amp With SPI
Digital programmable
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6 Pin Configuration and Functions
œIN
RG
RG
+IN
1
2
3
4
8
7
6
5
+VS
OUT
REF
œVS
œIN
RG
RG
+IN
1
2
3
4
8
7
6
5
+VS
OUT
REF
œVS
Thermal
Pad
Not to scale
Not to scale
图6-1. D (8-Pin SOIC) and DGK (8-Pin VSSOP)
Packages, Top View
图6-2. DRG Package, 8-Pin WSON, Top View
表6-1. Pin Functions
PIN
TYPE
DESCRIPTION
NAME
–IN
NO.
1
Input
Input
Negative (inverting) input
Positive (noninverting) input
Output
+IN
4
OUT
7
Output
RG
2, 3
6
Gain setting pin. Place a gain resistor between pin 2 and pin 3.
Reference input. This pin must be driven by a low impedance source.
Negative supply
—
REF
Input
5
–VS
+VS
—
—
—
8
Positive supply
Thermal pad
Thermal pad internally connected to –VS. Connect externally to –VS or leave floating.
—
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
V
±20
Supply voltage dual supply, VS = (V+) –(V–)
Supply voltage single supply, VS = (V+) –(V–)
Signal input pins
40
V
60
20
V
–60
–20
VREF pin
V
Signal output pins maximum voltage
Signal output pins maximum current
Output short-circuit(2)
(+Vs) + 0.5
50
V
(–Vs) –0.5
–50
mA
Continuous
Operating Temperature, TA
Junction Temperature, TJ
150
175
150
°C
°C
°C
–50
–65
Storage Temperature, Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Short-circuit to VS / 2.
7.2 ESD Ratings
VALUE
±1500
±750
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
MAX
36
UNIT
Single-supply
Supply voltage, VS
V
Dual-supply
±2.25
–40
±18
125
Specified temperature, TA
Specified temperature
°C
7.4 Thermal Information
INA819
THERMAL METRIC(1)
D (SOIC)
8 PINS
119.6
66.3
DGK (VSSOP) DRG (WSON)
UNIT
8 PINS
215.4
66.3
8 PINS
55.6
57.9
28.6
1.8
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
61.9
97.8
20.5
10.5
ψJT
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
61.4
96.1
28.6
12.1
ψJB
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
10
6
MAX
UNIT
INPUT
INA819ID
35
40
30
INA819IDGK
INA819IDRG
µV
INA819ID,
INA819DRG
Input stage offset
voltage(1) (3)
75
80
VOSI
TA = –40°C to +125°C(2)
INA819IDGK
INA819D,
INA819DGK
0.4
vs temperature,
TA = –40°C to +125°C
µV/°C
INA819DRG
0.35
300
800
5
50
µV
Output stage offset
voltage(1) (3)
VOSO
TA = –40°C to +125°C(2)
vs temperature, TA = –40°C to +125°C
G = 1, RTI
µV/°C
110
114
130
136
120
130
G = 10, RTI
Power-supply rejection
ratio
PSRR
dB
G = 100, RTI
135
G = 1000, RTI
140
zid
zic
Differential impedance
100 || 1
GΩ|| pF
GΩ || pF
Common-mode
impedance
100 || 4
32
RFI filter, –3-dB
frequency
MHz
(V–) + 2
(V+) –2
VCM
Operating input range(4)
Input overvoltage range
V
V
VS = ±2.25 V to ±18 V, TA = –40°C to +125°C
TA = –40°C to +125°C(2)
See 图7-51 through 图7-54
±60
At DC to 60 Hz, RTI, VCM = (V–) + 2 V to (V+) –2 V,
G = 1
90
110
130
140
105
125
145
150
At DC to 60 Hz, RTI, VCM = (V–) + 2 V to (V+) –2 V,
G = 10
Common-mode rejection
ratio
CMRR
dB
At DC to 60 Hz, RTI, VCM = (V–) + 2 V to (V+) –2 V,
G = 100
At DC to 60 Hz, RTI, VCM = (V–) + 2 V to (V+) –2 V,
G = 1000
BIAS CURRENT
VCM = VS / 2
0.15
0.15
0.5
2
IB
Input bias current
nA
nA
TA = –40°C to +125°C
VCM = VS / 2
0.5
2
IOS
Input offset current
TA = –40°C to +125°C
NOISE VOLTAGE
8
0.19
80
f = 1 kHz, G = 100, RS = 0 Ω
fB = 0.1 Hz to 10 Hz, G = 100, RS = 0 Ω
f = 1 kHz, RS = 0 Ω
nV/√Hz
µVPP
Input stage voltage
eNI
eNO
In
noise(6)
nV/√Hz
µVPP
Output stage voltage
noise(6)
2.6
fB = 0.1 Hz to 10 Hz, RS = 0 Ω
f = 1 kHz
130
4.7
fA/√Hz
Noise current
fB = 0.1 Hz to 10 Hz, G = 100
pAPP
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7.5 Electrical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
GAIN
Gain equation
Gain
V/V
V/V
1 + (50 kΩ / RG)
G
1
10000
±0.025%
±0.15%
±0.15%
G = 1, VO = ±10 V
G = 10, VO = ±10 V
G = 100, VO = ±10 V
±0.005%
±0.025%
±0.025%
±0.05%
GE
Gain error
G = 1000, VO = ±10 V
±5
±35
10
G = 1, TA = –40°C to +125°C
Gain vs temperature(5)
ppm/°C
ppm
G > 1, TA = –40°C to +125°C
1
G = 1 to 10, VO = –10 V to +10 V, RL = 10 kΩ
G = 100, VO = –10 V to +10 V, RL = 10 kΩ
G = 1000, VO = –10 V to +10 V, RL = 10 kΩ
G = 1 to 100, VO = –10 V to +10 V, RL = 2 kΩ
15
Gain nonlinearity
10
30
OUTPUT
(V–) +
0.15
Voltage swing
V
(V+) –0.15
Load capacitance stability
1000
5.0
pF
Closed-loop output
impedance
ZO
f = 10 kHz
Ω
ISC
Short-circuit current
Continuous to VS / 2
±20
mA
FREQUENCY RESPONSE
G = 1
2.0
890
270
30
MHz
kHz
G = 10
BW
SR
tS
Bandwidth, –3 dB
Slew rate
G = 100
G = 1000
G = 1, VO = ±10 V
0.9
12
V/µs
0.01%, G = 1 to 100, VSTEP = 10 V
0.01%, G = 1000, VSTEP = 10 V
0.001%, G = 1 to 100, VSTEP = 10 V
0.001%, G = 1000, VSTEP = 10 V
40
Settling time
µs
16
60
REFERENCE INPUT
RIN Input impedance
40
kΩ
V
Voltage range
(V+)
(V–)
Gain to output
1
V/V
Reference gain error
0.01%
POWER SUPPLY
VIN = 0 V
350
385
520
IQ Quiescent current
µA
vs temperature, TA = –40°C to +125°C
(1) Total offset, referred-to-input (RTI): VOS = (VOSI) + (VOSO / G).
(2) Specified by characterization.
(3) Offset drifts are uncorrelated. Input-referred offset drift is calculated using: ΔVOS(RTI) = √[ΔVOSI 2 + (ΔVOSO / G)2].
(4) Input voltage range of the Instrumentation Amplifier input stage. The input range depends on the common-mode voltage, differential
voltage, gain, and reference voltage.
(5) The values specified for G > 1 do not include the effects of the external gain-setting resistor, RG.
(6) Total RTI voltage noise is equal to: eN(RTI) = √[eNI 2 + (eNO / G)2].
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7.6 Typical Characteristics
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
表7-1. Table of Graphs
DESCRIPTION
FIGURE
图7-1
Typical Distribution of Input Stage Offset Voltage
Typical Distribution of Input Stage Offset Voltage Drift
Typical Distribution of Output Stage Offset Voltage
Typical Distribution of Output Stage Offset Voltage Drift
Input Stage Offset Voltage vs Temperature
Output Stage Offset Voltage vs Temperature
Typical Distribution of Input Bias Current, TA = 25°C
Typical Distribution of Input Bias Current, TA = 90°C
Typical Distribution of Input Offset Current
Input Bias Current vs Temperature
图7-2
图7-3
图7-4
图7-5
图7-6
图7-7
图7-8
图7-9
图7-10
图7-11
图7-12
图7-13
图7-14
图7-15
图7-16
图7-17
图7-18
图7-19
图7-20
图7-21
图7-22
图7-23
图7-24
图7-25
图7-26
图7-27
图7-28
图7-29
图7-30
图7-31
图7-32
图7-33
图7-34
图7-35
图7-36
图7-37
图7-38
图7-39
图7-40
Input Offset Current vs Temperature
Typical CMRR Distribution, G = 1
Typical CMRR Distribution, G = 10
CMRR vs Temperature, G = 1
CMRR vs Temperature, G = 10
Input Current vs Input Overvoltage
CMRR vs Frequency (RTI)
CMRR vs Frequency (RTI, 1-kΩsource imbalance)
Positive PSRR vs Frequency (RTI)
Negative PSRR vs Frequency (RTI)
Gain vs Frequency
Voltage Noise Spectral Density vs Frequency (RTI)
Current Noise Spectral Density vs Frequency (RTI)
0.1-Hz to 10-Hz RTI Voltage Noise, G = 1
0.1-Hz to 10-Hz RTI Voltage Noise, G = 1000
0.1-Hz to 10-Hz RTI Current Noise
Input Bias Current vs Common-Mode Voltage
Typical Distribution of Gain Error, G = 1
Typical Distribution of Gain Error, G = 10
Gain Error vs Temperature, G = 1
Gain Error vs Temperature, G = 10
Supply Current vs Temperature
Gain Nonlinearity, G = 1
Gain Nonlinearity, G = 10
Offset Voltage vs Negative Common-Mode Voltage
Offset Voltage vs Positive Common-Mode Voltage
Positive Output Voltage Swing vs Output Current
Negative Output Voltage Swing vs Output Current
Short Circuit Current vs Temperature
Large-Signal Frequency Response
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7.6 Typical Characteristics
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
表7-1. Table of Graphs (continued)
DESCRIPTION
FIGURE
图7-41
图7-42
图7-43
图7-44
图7-45
图7-46
图7-47
图7-48
图7-49
图7-50
图7-51
图7-52
图7-53
图7-54
THD+N vs Frequency
Overshoot vs Capacitive Loads
Small-Signal Response, G = 1
Small-Signal Response, G = 10
Small-Signal Response, G = 100
Small-Signal Response, G = 1000
Large Signal Step Response
Closed-Loop Output Impedance
Differential-Mode EMI Rejection Ratio
Common-Mode EMI Rejection Ratio
Input Common-Mode Voltage vs Output Voltage, G = 1, VS = 5 V
Input Common-Mode Voltage vs Output Voltage, G = 100, VS = 5 V
Input Common-Mode Voltage vs Output Voltage, VS =±5 V
Input Common-Mode Voltage vs Output Voltage, VS =±15 V
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7.6 Typical Characteristics
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
20%
15%
10%
5%
25%
22.5%
20%
17.5%
15%
12.5%
10%
7.5%
5%
2.5%
0
0
-50 -40 -30 -20 -10
0
10
20
30
40
50
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
Input Stage Offset Voltage (mV)
Input Stage Offset Voltage Drift (mV/èC)
D001
D002
N = 1555
Mean = 4.71 µV
Std. Dev. = 7.12 µV
N = 45
Mean = 0.0357 µV/°C Std. Dev. = 0.099 µV/°C
图7-1. Typical Distribution of Input Stage Offset Voltage
图7-2. Typical Distribution of Input Stage Offset Voltage Drift
0.15
30%
25%
20%
15%
10%
5%
0.1
0.05
0
0
-200 -150 -100
-50
0
50
100
150
200
-5
-4
-3
-2
-1
0
1
2
3
4
5
Output Stage Offset Voltage (mV)
Output Stage Offset Voltage Drift (mV/èC)
D003
D004
N = 1555
Std. Dev. = 41.26 µV
N = 45
Std. Dev. = 0.89 µV/°C
Mean = –1.49 µV/°C
Mean = –3.18 µV
图7-3. Typical Distribution of Output Stage Offset Voltage
图7-4. Typical Distribution of Output Stage Offset Voltage Drift
100
80
60
40
20
0
500
Mean
+3s
-3s
400
300
200
100
0
-20
-40
-100
-200
-300
-400
-500
-60
Mean
+3s
-3s
-80
-100
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Temperature (èC)
Temperature (èC)
D005
D051
45 units, 1 wafer lot
45 units, 1 wafer lots
图7-5. Input Stage Offset Voltage vs Temperature
图7-6. Output Stage Offset Voltage vs Temperature
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7.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
0.25
0.2
0.15
0.1
0.05
0
25%
20%
15%
10%
5%
0
-250 -200 -150 -100 -50
-300
-200
-100
Input Bias Current (pA)
0
100
200
300
0
Input Bias Current (pA)
50 100 150 200 250
D006
D007
N = 94
TA = 25°C
图7-7. Typical Distribution of Input Bias Current
Mean = 37.13 pA Std. Dev. = 57.65 pA
Mean = –27.65
N = 94
Std. Dev. = 52.58 pA
pA
TA = 90°C
图7-8. Typical Distribution of Input Bias Current
25%
500
Avg
ꢁ3
−3
400
300
200
100
0
20%
15%
10%
5%
-100
-200
-300
-400
-500
0
-300
-200
-100
Input Offset Current (pA)
0
100
200
300
-50
-25
0
25
50
75
100
125
150
Temperature (ꢀC)
D008
N = 94
G = 1
Mean = –38.82
N = 94
Std. Dev. = 47.24 pA
pA
图7-10. Input Bias Current vs Temperature
图7-9. Typical Distribution of Input Offset Current
300
250
200
150
100
50
20%
15%
10%
5%
0
-50
-100
-150
Avg
ꢁ3
−3
-200
-250
-300
0
-50 -30 -10 10
30
50
70
90 110 130 150
-20 -16 -12
-8
-4
0
4
8
12
16
20
Temperature (ꢀC)
Common-Mode Rejection Ratio (mV/V)
D011
N = 94
G = 1
N = 94
G = 1
Mean = 3.23 µV/V Std. Dev. = 5.38 µV/V
图7-11. Input Offset Current vs Temperature
图7-12. Typical CMRR Distribution
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7.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
25%
20%
15%
10%
5%
150
125
100
75
Unit 1
Unit 2
Unit 3
Unit 4
Unit 5
0
50
-2
-1.5
-1
-0.5
0
0.5
1
1.5
-50
-25
0
25
50
75
100
125
150
Common-Mode Rejection Ratio (mV/V)
Temperature (èC)
D012
D013
N = 94
Mean = 0.34 µV/V Std. Dev. = 0.54 µV/V
5 typical units
G = 1
G = 10
图7-13. Typical CMRR Distribution
图7-14. CMRR vs Temperature
175
150
125
100
75
10
20
16
12
8
8
6
4
2
4
0
0
-2
-4
-6
-8
-10
-4
-8
Unit 1
Unit 2
Unit 3
Unit 4
Unit 5
-12
-16
-20
Input Current
Output Voltage
50
-50
-25
0
25
50
75
100
125
150
-50 -40 -30 -20 -10
0
Input Voltage (V)
10
20
30
40
50
Temperature (èC)
D014
D015
5 typical units
G = 10
VS = 36 V
图7-15. CMRR vs Temperature
图7-16. Input Current vs Input Overvoltage
160
140
120
100
80
150
1
10
100
1000
1
10
100
1000
125
100
75
50
25
0
60
40
20
0
1
10
100
1k
Frequency (Hz)
10k
100k
1M
1
10
100
1k
Frequency (Hz)
10k
100k
1M
D016
D017
1-kΩsource imbalance
图7-18. CMRR vs Frequency (RTI)
图7-17. CMRR vs Frequency (RTI)
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7.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
170
140
110
80
160
140
120
100
80
60
50
40
20
20
G = 1
G = 1
0
G = 10
G = 100
G = 1000
G = 10
G = 100
G = 1000
-10
-40
-20
-40
1
10
100
1k
Frequency (Hz)
10k
100k
1M
1
10
100 1k
Frequency (Hz)
10k
100k
D018
D019
图7-19. Positive PSRR vs Frequency (RTI)
图7-20. Negative PSRR vs Frequency (RTI)
80
60
40
20
0
1000
500
G = 1
G = 100
300
200
100
50
30
20
10
-20
-40
-60
G = 1
5
G = 10
G = 100
G = 1000
3
2
1
100m
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
1
10
100
Frequency (Hz)
1k
10k
100k
D020
D021
图7-21. Gain vs Frequency
图7-22. Voltage Noise Spectral Density vs Frequency (RTI)
1000
700
3
500
2
1
300
200
100
70
0
50
-1
-2
-3
30
20
10
100m
1
10 100
Frequency (Hz)
1k
10k
0
1
2
3
4
5
Time (s/div)
6
7
8
9
10
D022
D023
G = 1
图7-23. Current Noise Spectral Density vs Frequency (RTI)
图7-24. 0.1-Hz to 10-Hz RTI Voltage Noise
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7.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
100
80
2
1.5
1
60
40
0.5
0
20
0
-20
-40
-60
-80
-100
-0.5
-1
-1.5
-2
-5
-4
-3
-2
-1
Time (1 s/div)
0
1
2
3
4
5
-5
-4
-3
-2
-1
Time (1 s/div)
0
1
2
3
4
5
D024
D025
G = 1000
图7-25. 0.1-Hz to 10-Hz RTI Voltage Noise
图7-26. 0.1-Hz to 10-Hz RTI Current Noise
0.5
0.4
0.3
0.2
0.1
0
20%
17.5%
15%
12.5%
10%
7.5%
5%
-0.1
-0.2
-0.3
-0.4
-0.5
-45 èC
25 èC
125 èC
2.5%
0
-15 -12
-9
-6
-3
0
3
6
Common Mode Voltage (V)
9
12
15
-250 -200 -150 -100 -50
0
Gain Error (ppm)
50 100 150 200 250
D026
D027
VS = ±15 V
N = 94
G = 1
Std. Dev. = 58 ppm
Mean = –48 ppm
图7-27. Input Bias Current vs Common-Mode Voltage
图7-28. Typical Distribution of Gain Error,
G = 1
20%
18%
16%
14%
12%
10%
8%
-20
-30
-40
-50
-60
-70
-80
6%
4%
2%
0
-300 -150
0
150
300
Gain Error (ppm)
450
600
750
900
-50
-25
0
25
50
75
100
125
150
Temperature (èC)
D028
D029
N = 94
G = 10
Mean = 286 ppm
Std. Dev. = 204 ppm
G = 1
图7-29. Typical Distribution of Gain Error,
图7-30. Gain Error vs Temperature
G = 10
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7.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
500
450
400
350
300
250
200
150
100
50
0.5
0.45
0.4
0.35
0.3
VS = ê 15 V
VS = ê 2.25 V
0
0.25
-50
-25
0
25
50
75
100
125
150
-60
-30
0
30
60
90
120
150
Temperature (èC)
Temperature (èC)
D030
D031
G = 10
图7-31. Gain Error vs Temperature
图7-32. Supply Current vs Temperature
1
0.8
0.6
0.4
0.2
0
5
4
EP
LREG
EP
LREG
3
2
1
0
-0.2
-0.4
-0.6
-0.8
-1
-1
-2
-3
-4
-5
-10
-8
-6
-4
-2
Output Voltage (V)
0
2
4
6
8
10
-10
-8
-6
-4
-2
Output Voltage (V)
0
2
4
6
8
10
D032
D033
G = 1
G = 10
图7-33. Gain Nonlinearity
图7-34. Gain Nonlinearity
175
150
125
100
75
150
125
100
75
-40 èC
25 èC
-40 èC
25 èC
85 èC
85 èC
125 èC
125 èC
50
50
25
25
0
0
-25
-50
-75
-25
-50
-15
-14.6 -14.2 -13.8 -13.4
-13
Input Common-Mode Voltage (V)
-12.6 -12.2 -11.8
12
12.4
12.8
13.2
13.6
Input Common-Mode Voltage (V)
14
14.4
14.8
D034
D035
图7-35. Offset Voltage vs Negative Common-Mode Voltage
图7-36. Offset Voltage vs Positive Common-Mode Voltage
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7.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
15
14.9
14.8
14.7
14.6
14.5
14.4
14.3
14.2
14.1
14
-14
-14.1
-14.2
-14.3
-14.4
-14.5
-14.6
-14.7
-14.8
-14.9
-15
-40èC
25èC
85èC
125èC
-40èC
25èC
85èC
125èC
0
4
8
Output Current (mA)
12
16
0
2
4
6
8
Output Current (mA)
10
12
14
16
D036
D037
图7-37. Positive Output Voltage Swing vs Output Current
图7-38. Negative Output Voltage Swing vs Output Current
40
20
ISC, Source
ISC, Sink
VS = ê15 V
VS = ê5 V
30
18
20
10
16
14
12
10
8
0
-10
-20
-30
-40
-50
-60
6
4
2
0
-50 -30 -10 10
30
50
70
90 110 130 150
100
1k
10k 100k
Frequency (Hz)
1M
10M
Temperature (èC)
D038
D039
图7-39. Short Circuit Current vs Temperature
图7-40. Large-Signal Frequency Response
1
-40
50
45
40
35
30
25
20
15
10
5
G = 1
G = 10
G = 100
0.1
-60
0.01
-80
Positive
Negative
0.001
-100
100k
0
1
10
100
1k
Frequency (Hz)
10k
10
100
1k
Cload (pF)
D040
D041
500-kHz measurement bandwidth
1-VRMS output voltage
图7-41. THD+N vs Frequency
100-kΩload
图7-42. Overshoot vs Capacitive Loads
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7.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
100
80
100
80
60
60
40
40
20
20
0
0
-20
-40
-60
-80
-100
-20
-40
-60
-80
-100
-5
-2.5
0
2.5
5
7.5
10
12.5
15
-5
-2.5
0
2.5
5
7.5
10
12.5
15
Time (ms)
Time (ms)
D042
D043
G = 1
CL = 100 pF
G = 10
CL = 100 pF
RL = 10 kΩ
RL = 10 kΩ
图7-43. Small-Signal Response
图7-44. Small-Signal Response
100
80
100
80
60
60
40
40
20
20
0
0
-20
-40
-60
-80
-100
-20
-40
-60
-80
-100
-5
-2.5
0
2.5
5
7.5
10
12.5
15
-25 -12.5
0
12.5 25 37.5 50 62.5 75 87.5 100
Time (ms)
Time (ms)
D044
D045
G = 100
CL = 100 pF
G = 1000
CL = 100 pF
RL = 10 kΩ
RL = 10 kΩ
图7-45. Small-Signal Response
图7-46. Small-Signal Response
Output
Input
1k
100
10
1
0.1
1
10
100
1k 10k
Frequency (Hz)
100k
1M
10M
Time (10 µs/div)
D046
C0xx
图7-47. Large Signal Step Response
图7-48. Closed-Loop Output Impedance
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7.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
100
80
60
40
20
0
140
120
100
80
60
40
20
10M
100M
Frequency (Hz)
1G
10G
10M
100M
Frequency (Hz)
1G
10G
D047
D048
图7-49. Differential-Mode EMI Rejection Ratio
图7-50. Common-Mode EMI Rejection Ratio
5
5
VREF = 0 V
VREF = 0 V
VREF = 2.5 V
VREF = 2.5 V
4
3
2
1
0
4
3
2
1
0
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Output Voltage (V)
Output Voltage (V)
C006
C006
VS = 5 V
G = 1
VS = 5 V
G = 100
图7-51. Input Common-Mode Voltage vs Output Voltage
图7-52. Input Common-Mode Voltage vs Output Voltage
15
5
4
10
5
3
2
1
0
0
-5
-1
-2
-3
-10
-15
G = 1
G = 1
-4
G = 100
-20
G = 100
-5
0
10
20
0
2
4
±
20
10
±±
±4
±2
Output Voltage (V)
Output Voltage (V)
C006
C00±
VS = ±5 V
VREF = 0 V
VS = ±15 V
VREF = 0 V
图7-53. Input Common-Mode Voltage vs Output Voltage
图7-54. Input Common-Mode Voltage vs Output Voltage
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8 Detailed Description
8.1 Overview
The INA819 is a monolithic precision instrumentation amplifier that incorporates a current-feedback input stage
and a four-resistor difference amplifier output stage. The functional block diagram in the next section shows how
the differential input voltage is buffered by Q1 and Q2 and is forced across RG, which causes a signal current to
flow through RG, R1, and R2. The output difference amplifier, A3, removes the common-mode component of the
input signal and refers the output signal to the REF pin. The VBE and voltage drop across R1 and R2 produce
output voltages on A1 and A2 that are approximately 0.8 V lower than the input voltages.
Each input is protected by two field-effect transistors (FETs) that provide a low series resistance under normal
signal conditions, and preserve excellent noise performance. When excessive voltage is applied, these
transistors limit input current to approximately 8 mA.
8.2 Functional Block Diagram
+VS
VB
RB
RB
IB Cancellation
IB Cancellation
40 k
–VS +VS
40 k
–
A1
A2
A3
+
OUT
REF
40 k
40 k
+VS
+VS
–VS +VS
Q2
Q1
Super-
NPN
Super-
NPN
–IN
+IN
Overvoltage
Protection
+VS
+VS
Overvoltage
Protection
R2
25 k
R1
25 k
RG
(External)
–VS
–VS
RG
RG
–VS
–VS
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8.3 Feature Description
8.3.1 Setting the Gain
图8-1 shows that the gain of the INA819 is set by a single external resistor (RG) connected between the RG pins
(pins 1 and 8).
V+
+VS
Overvoltage
Protection
40 kꢀ
+
40 kꢀ
-IN
œ
RG
œ
50 kW
RG
25 kꢀ
25 kꢀ
OUT
REF
G = 1+
RG
+
VO = G V+IN - V-IN + V
(
)
REF
RG
+IN
œ
Overvoltage
Protection
+
40 kꢀ
40 kꢀ
-VS
Copyright © 2017, Texas Instruments Incorporated
V-
图8-1. Simplified Diagram of the INA819 With Gain and Output Equations
The value of RG is selected according to 方程式1:
50 kW
G = 1+
RG
(1)
表 8-1 lists several commonly used gains and resistor values. The 50-kΩ term in 方程式 1 is a result of the sum
of the two internal 25-kΩ feedback resistors. These on-chip resistors are laser-trimmed to accurate absolute
values. The accuracy and temperature coefficients of these resistors are included in the gain accuracy and drift
specifications of the INA819. As shown in 图 8-1 and explained in more details in 节 11, make sure to connect
low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground that are placed as close to the
device as possible.
表8-1. Commonly Used Gains and Resistor Values
DESIRED GAIN
RG (Ω)
NEAREST 1% RG (Ω)
1
2
NC
NC
49.9 k
12.4 k
5.49 k
2.61 k
1.02 k
511
50 k
5
12.5 k
5.556 k
2.632 k
1.02 k
505.1
251.3
100.2
50.05
10
20
50
100
200
500
1000
249
100
49.9
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8.3.1.1 Gain Drift
The stability and temperature drift of the external gain setting resistor (RG ) also affects gain. The contribution of
RG to gain accuracy and drift is determined from 方程式1.
The best gain drift of 5 ppm/℃ (maximum) is achieved when the INA819 uses G = 1 without RG connected. In
this case, gain drift is limited by the mismatch of the temperature coefficient of the integrated 40-kΩ resistors in
the differential amplifier (A3). At gains greater than 1, gain drift increases as a result of the individual drift of the
25-kΩ resistors in the feedback of A1 and A2, relative to the drift of the external gain resistor (RG.) The low
temperature coefficient of the internal feedback resistors improves the overall temperature stability of
applications using gains greater than 1 V/V over alternate solutions.
Low resistor values required for high gain make wiring resistance an important consideration. Sockets add to the
wiring resistance and contribute additional gain error (such as a possible unstable gain error) at gains of
approximately 100 or greater. To maintain stability, avoid parasitic capacitance of more than a few picofarads at
RG connections. Careful matching of any parasitics on the RG pins maintains optimal CMRR over frequency; see
图7-17.
8.3.2 EMI Rejection
Texas Instruments developed a method to accurately measure the immunity of an amplifier over a broad
frequency spectrum extending from 10 MHz to 6 GHz. This method uses an EMI rejection ratio (EMIRR) to
quantify the ability of the INA819 to reject EMI. The offset resulting from an input EMI signal is calculated using
Equation 2:
EMIRR (dB)
≈
’
2
≈
∆
’
÷
-
VRF_PEAK
100 mVP
∆
«
÷
◊
20
DVOS
=
∂10
∆
«
÷
◊
(2)
where
• VRF_PEAK is the peak amplitude of the input EMI signal.
图 8-2 and 图 8-3 show the INA819 EMIRR graph for differential and common-mode EMI rejection across this
frequency range. 表 8-2 lists the EMIRR values for the INA819 at frequencies commonly encountered in real-
world applications. Applications listed in 表 8-2 are centered on or operated near the frequency shown.
Depending on the end-system requirements, additional EMI filters may be required near the signal inputs of the
system. Incorporating known good practices such as using short traces, low-pass filters, and damping resistors
combined with parallel and shielded signal routing may be required.
140
120
100
80
100
80
60
40
20
0
60
40
20
10M
100M
Frequency (Hz)
1G
10G
10M
100M
Frequency (Hz)
1G
10G
D048
D047
图8-2. Common-Mode EMIRR Testing
图8-3. Differential Mode EMIRR Testing
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表8-2. INA819 EMIRR for Frequencies of Interest
DIFFERENTIAL
EMIRR
COMMON-MODE
EMIRR
FREQUENCY
400 MHz
APPLICATION OR ALLOCATION
Mobile radio, mobile satellite, space operation, weather, radar, ultrahigh-frequency (UHF)
applications
52 dB
55 dB
58 dB
80 dB
71 dB
73 dB
Global system for mobile communications (GSM) applications, radio communication,
navigation, GPS (up to 1.6 GHz), GSM, aeronautical mobile, UHF applications
900 MHz
GSM applications, mobile personal communications, broadband, satellite,
L-band (1 GHz to 2 GHz)
1.8 GHz
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific
and medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
2.4 GHz
3.6 GHz
5 GHz
59 dB
78 dB
70 dB
95 dB
96 dB
Radiolocation, aero communication and navigation, satellite, mobile, S-band
802.11a, 802.11n, aero communication and navigation, mobile communication, space and
satellite operation, C-band (4 GHz to 8 GHz)
100 dB
8.3.3 Input Common-Mode Range
The linear input voltage range of the INA819 input circuitry extends within 1.5 volts (typical) of both power
supplies and maintains excellent common-mode rejection throughout this range. The common-mode range for
the most common operating conditions are shown in 图 8-4 to 图 8-7. The common-mode range for other
operating conditions is best calculated using the Analog Engineers Calculator.
5
4
3
2
1
0
5
4
3
2
1
0
VREF = 0 V
VREF = 0 V
VREF = 2.5 V
VREF = 2.5 V
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Output Voltage (V)
Output Voltage (V)
C006
C006
VS = 5 V
G = 1
VS = 5 V
G = 100
图8-4. Input Common-Mode Voltage
图8-5. Input Common-Mode Voltage
vs Output Voltage
vs Output Voltage
15
10
5
5
4
3
2
1
0
0
-5
-1
-2
-3
-10
-15
-20
G = 1
G = 1
-4
G = 100
G = 100
-5
0
10
20
0
2
4
±
20
10
±±
±4
±2
Output Voltage (V)
Output Voltage (V)
C006
C00±
VS = ±5 V
VREF = 0 V
VS = ±15 V
VREF = 0 V
图8-6. Input Common-Mode Voltage
图8-7. Input Common-Mode Voltage
vs Output Voltage
vs Output Voltage
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8.3.4 Input Protection
The inputs of the INA819 device are individually protected for voltages up to ±60 V. For example, a condition of
–60 V on one input and +60 V on the other input does not cause damage. Internal circuitry on each input
provides low series impedance under normal signal conditions. If the input is overloaded, the protection circuitry
limits the input current to a value of approximately 8 mA.
+V
ZD1
+VS
IN
Overvoltage
Protection
Input Voltage
Source
+
Input Transistor
œ
-VS
ZD2
-V
图8-8. Input Current Path During an Overvoltage Condition
During an input overvoltage condition, current flows through the input protection diodes into the power supplies;
see 图 8-8. If the power supplies are unable to sink current, then Zener diode clamps (ZD1 and ZD2 in 图 8-8)
must be placed on the power supplies to provide a current pathway to ground. 图8-9 shows the input current for
input voltages from –50 V to 50 V when the INA819 is powered by ±15-V supplies.
10
8
20
16
12
8
6
4
2
4
0
0
-2
-4
-6
-8
-10
-4
-8
-12
-16
-20
Input Current
Output Voltage
-50 -40 -30 -20 -10
0
Input Voltage (V)
10
20
30
40
50
D015
图8-9. Input Current vs Input Overvoltage
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8.3.5 Operating Voltage
The INA819 operates over a power-supply range of 4.5 V to 36 V (±2.25 V to ±18 V).
CAUTION
Supply voltages higher than 40 V (±20 V) can permanently damage the device. Parameters that vary
over supply voltage or temperature are shown in 节7.6 .
8.3.6 Error Sources
Most modern signal-conditioning systems calibrate errors at room temperature. However, calibration of errors
that result from a change in temperature is normally difficult and costly. Therefore, minimize these errors by
choosing high-precision components, such as the INA819, that have improved specifications in critical areas that
impact the precision of the overall system. 图8-10 shows an example application.
+15 V
C2
RS+
1 kꢀ
RG
VDIFF = VOUT / G
INA
RG
5.49 kꢀ
VOUT = 1 V
RSœ
0.99 kꢀ
VCM = 10 V
C1
œ15 V
图8-10. Example Application with G = 10 V/V and 1-V Output Voltage
Resistor-adjustable devices (such as the INA819) show the lowest gain error in G = 1 because of the inherently
well-matched drift of the internal resistors of the differential amplifier. At gains greater than 1 (for instance, G =
10 V/V or G = 100 V/V), the gain error becomes a significant error source because of the contribution of the
resistor drift of the 25-kΩ feedback resistors in conjunction with the external gain resistor. Except for very high
gain applications, the gain drift is by far the largest error contributor compared to other drift errors, such as offset
drift.
The INA819 offers excellent gain error over temperature for both G > 1 and G = 1 (no external gain resistor). 表
8-4 summarizes the major error sources in common INA applications and compares the three cases of G = 1 (no
external resistor) and G = 10 (5.49-kΩ external resistor) and G = 100 (511-Ω external resistor). All calculations
are assuming an output voltage of VOUT = 1 V. Thus, the input signal VDIFF (given by VDIFF= VOUT/G) exhibits
smaller and smaller amplitudes with increasing gain G. In this example, VDIFF = 1 mV at G = 1000. All
calculations refer the error to the input for easy comparison and system evaluation. As 表 8-4 shows, errors
generated by the input stage (such as input offset voltage) are more dominant at higher gain, while the effects of
output stage are suppressed because they are divided by the gain when referring them back to the input. The
gain error and gain drift error are much more significant for gains greater than 1 because of the contribution of
the resistor drift of the 25-kΩ feedback resistors in conjunction with the external gain resistor. In most
applications, static errors (absolute accuracy errors) can readily be removed during calibration in production,
while the drift errors are the key factors limiting overall system performance.
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表8-3. System Specifications for Error Calculation
QUANTITY
VALUE
UNIT
VOUT
1
V
V
V
VCM
10
VS
1
RS+
RS–
1000
999
0.01
10
Ω
Ω
RG tolerance
RG drift
%
ppm/°C
°C
Temperature range upper limit
105
表8-4. Error Calculation
INA819 VALUES
G = 1
G = 100
ERROR
(ppm)
G = 1000
ERROR
(ppm)
ERROR SOURCE
ERROR CALCULATION
SPECIFICATION
UNIT
ERROR
(ppm)
ABSOLUTE ACCURACY AT 25°C
Input offset voltage
VOSI / VDIFF
35
300
0.5
µV
µV
nA
35
300
1
350
300
5
3500
300
50
Output offset voltage
VOSO / (G × VDIFF)
Input offset current
IOS × maximum (RS+, RS–) / VDIFF
90 (G = 1),
110 (G = 10),
130 (G = 100)
CMRR (min)
VCM / (10CMRR/20 × VDIFF
)
dB
dB
316
3
316
20
316
32
110 (G = 1),
114 (G = 10),
130 (G = 100)
(VCC –VS)/ (10PSRR/20 × VDIFF
)
PSRR (min)
0.02 (G = 1),
0.15 (G = 10, 100)
Gain error from INA (max)
GE(%) × 104
%
%
—
200
100
955
1500
100
1500
100
Gain error from external resistor RG (max) GE(%) × 104
0.01
Total absolute accuracy error (ppm) at
sum of all errors
2591
5798
—
25°C, worst case
Total absolute accuracy error (ppm) at
rms sum of all errors
491
1604
3835
—
—
25°C, average
DRIFT TO 105°C
5 (G = 1),
35 (G = 10, 100)
Gain drift from INA (max)
ppm/°C
400
2800
2800
GTC × (TA –25)
Gain drift from external resistor RG (max)
Input offset voltage drift (max)
Output offset voltage drift
10
0.4
5
ppm/°C
µV/°C
µV/°C
800
32
800
320
400
800
3200
400
GTC × (TA –25)
(VOSI_TC / VDIFF) × (TA –25)
400
[VOSO_TC / ( G × VDIFF)] × (TA –25)
IOS_TC × maximum (RS+, RS–) ×
(TA –25) / VDIFF
Offset current drift
20
pA/°C
2
16
160
Total drift error to 105°C (ppm), worst case sum of all errors
1634
980
4336
2957
7360
4348
—
—
—
—
Total drift error to 105°C (ppm), typical
RESOLUTION
rms sum of all errors
10 (G = 1, 10),
15 (G = 100)
Gain nonlinearity
ppm of FS
µVPP
10
1204
0.3
10
1070
2
15
3941
11
2
eNO
G
6
eNI = 8,
eNO = 90
2
(eNI
+
´
´
BW
Voltage noise (at 1 kHz)
VDIFF
IN × maximum (RS+, RS–) × √BW /
Current noise (at 1kHz)
0.13
pA/√Hz
VDIFF
Total resolution error (ppm), worst case
Total resolution error (ppm), typical
TOTAL ERROR
sum of all errors
1214
1204
1080
1070
3956
3941
—
—
—
—
rms sum of all errors
Total error (ppm), worst case
sum of all errors
3802
8007
17113
—
—
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表8-4. Error Calculation (continued)
INA819 VALUES
G = 1
G = 100
ERROR
(ppm)
G = 1000
ERROR
(ppm)
ERROR SOURCE
ERROR CALCULATION
SPECIFICATION
UNIT
ERROR
(ppm)
Total error (ppm), typical
rms sum of all errors
1628
3530
7010
—
—
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8.4 Device Functional Modes
The INA819 has a single functional mode and operates when the power-supply voltage is greater than 4.5 V
(±2.25 V). The maximum power-supply voltage for the INA819 is 36 V (±18 V.)
9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
9.1.1 Reference Pin
The output voltage of the INA819 is developed with respect to the voltage on the reference pin (REF.) Often, in
dual-supply operation, REF (pin 6) is connected to the low-impedance system ground. In single-supply
operation, offsetting the output signal to a precise midsupply level is useful (for example, 2.5 V in a 5-V supply
environment). To accomplish this level shift, a voltage source must be connected to the REF pin to level-shift the
output so that the INA819 drives a single-supply analog-to-digital converter (ADC).
The voltage source applied to the reference pin must have a low output impedance. As shown in 图 9-1, any
resistance at the reference pin (shown as RREF in 图9-1) is in series with an internal 40-kΩresistor.
V+
+VS
Overvoltage
40 kꢀ
+
40 kꢀ
-IN
Protection
œ
RG
œ
25 kꢀ
25 kꢀ
RG
OUT
REF
+
RG
+IN
œ
Overvoltage
Protection
+
RREF
40 kꢀ
40 kꢀ
-VS
V-
图9-1. Parasitic Resistance Shown at the Reference Pin
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The parasitic resistance at the reference pin (RREF) creates an imbalance in the four resistors of the internal
difference amplifier that results in a degraded common-mode rejection ratio (CMRR). 图 9-2 shows the
degradation in CMRR of the INA819 as a result of increased resistance at the reference pin. For the best
performance, keep the source impedance to the REF pin (RREF) less than 5 Ω.
120
100
80
60
0 Ω
40
5 Ω
10 Ω
20
15 Ω
20 Ω
0
10
100
1k
Frequency (Hz)
10k
图9-2. The Effect of Increasing Resistance at the Reference Pin
Voltage reference devices are an excellent option for providing a low-impedance voltage source for the
reference pin. However, if a resistor voltage divider generates a reference voltage, the divider must be buffered
by an op amp, as 图9-3 shows, to avoid CMRR degradation.
5 V
+IN
RG
INA819
RG
OUT
RG
œIN
5 V
5 V
100 kꢀ
+
OPA191
1 ꢁF
œ
100 kꢀ
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图9-3. Using an Op Amp to Buffer Reference Voltages
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9.1.2 Input Bias Current Return Path
The input impedance of the INA819 is extremely high—approximately 100 GΩ. However, a path must be
provided for the input bias current of both inputs. This input bias current is typically 150 pA. High input
impedance means that this input bias current changes very little with varying input voltage.
For proper operation, input circuitry must provide a path for input bias current. 图 9-4 shows various provisions
for an input bias current path. Without a bias current path, the inputs float to a potential that exceeds the
common-mode range of the INA819, and the input amplifiers saturate. If the differential source resistance is low,
the bias current return path can connect to one input (as shown in the thermocouple example in 图 9-4). With a
higher source impedance, using two equal resistors provides a balanced input with possible advantages of a
lower input offset voltage as a result of bias current and better high-frequency common-mode rejection.
Microphone,
Hydrophone,
and So Forth
TI Device
47 kW
47 kW
Thermocouple
TI Device
10 kW
TI Device
Center tap provides
bias current return.
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图9-4. Providing an Input Common-Mode Current Path
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9.2 Typical Applications
9.2.1 Three-Pin Programmable Logic Controller (PLC)
图9-5 shows a three-pin programmable-logic controller (PLC) design for the INA819. This PLC reference design
accepts inputs of ±10 V or ±20 mA. The output is a single-ended voltage of 2.5 V ±2.3 V (or 200 mV to 4.8 V).
Many PLCs typically have these input and output ranges.
10 V
15 V
REF5025
R
= 100 kΩ
= 4.17 kΩ
1
VOUT
GND
VIN
NR
1 ꢀF
1 ꢀF
1 ꢀF
15 V
+VS
R
2
20 mA
-IN
RG
REF
R
3
=
V
2.5 V 2.3 V
INA819
OUT
R
= 10.5 kΩ
OUT
G
20 Ω
RG
+IN
-VS
-15 V
Copyright © 2018, Texas Instruments Incorporated
图9-5. PLC Input (±10 V, 4 mA to 20 mA)
9.2.1.1 Design Requirements
For this application, the design requirements are as follows:
• 4-mA to 20-mA input with less than 20-Ωburden
• ±20-mA input with less than 20-Ωburden
• ±10-V input with impedance of approximately 100 kΩ
• Maximum 4-mA to 20-mA or ±20-mA burden voltage equal to ±0.4 V
• Output range within 0 V to 5 V
9.2.1.2 Detailed Design Procedure
There are two modes of operation for the circuit shown in 图 9-5: current input and voltage input. This design
requires R1 >> R2 >> R3. Given this relationship, Equation 3 calculates the current input mode transfer function.
VOUT-I = VD ´ G + VREF = -(IIN ´ R3) ´ G + VREF
(3)
where
• G represents the gain of the instrumentation amplifier.
• VD represents the differential voltage at the INA819 inputs.
• VREF is the voltage at the INA819 REF pin.
• IIN is the input current.
Equation 4 shows the transfer function for the voltage input mode.
R2
VOUT-V = VD ´ G + VREF = - VIN
´
´ G + VREF
R1 + R2
(4)
where
• VIN is the input voltage.
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R1 sets the input impedance of the voltage input mode. The minimum typical input impedance is 100 kΩ. The R1
value is 100 kΩbecause increasing the R1 value also increases noise. The value of R3 must be extremely small
compared to R1 and R2. 20 Ω for R3 is selected because that resistance value is much smaller than R1 and
yields an input voltage of ±400 mV when operated in current mode (±20 mA).
Use Equation 5 to calculate R2 given VD = ±400 mV, VIN = ±10 V, and R1 = 100 kΩ.
R2
R1 ´ VD
VD = VIN
´
® R2 =
= 4.167 kW
R1 + R2
VIN - VD
(5)
The value obtained from Equation 5 is not a standard 0.1% value, so 4.17 kΩ is selected. R1 and R2 also use
0.1% tolerance resistors to minimize error.
Use Equation 6 to calculate the ideal gain of the instrumentation amplifier.
V
OUT - VREF
V
4.8 V - 2.5 V
G =
=
= 5.75
V
VD
400 mV
(6)
(7)
Equation 7 calculates the gain-setting resistor value using the INA819 gain equation (方程式1).
50 kW 50 kW
RG
=
=
= 10.5 kW
G -1 5.75 -1
Use a standard 0.1% resistor value of 10.5 kΩfor this design.
9.2.1.3 Application Curves
图9-6 and 图9-7 show typical characteristic curves for the circuit in 图9-5.
C001
5
5
4
4
3
3
2
2
1
1
0
0
-10
-5
0
5
10
-20
-10
0
10
20
Input Voltage (V)
Input Current (mA)
C001
图9-6. PLC Output Voltage vs Input Voltage
图9-7. PLC Output Voltage vs Input Current
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9.2.2 Resistance Temperature Detector Interface
图 9-8 illustrates a 3-wire interface circuit for resistance temperature detectors (RTDs). The circuit incorporates
analog linearization and has an output voltage range from 0 V to 5 V. The linearization technique employed is
described in Analog linearization of resistance temperature detectors analog application journal. Series and
parallel combinations of standard 1% resistor values are used to achieve less than 0.02°C of error over a 200°C
temperature span.
15 V
REF5050
VOUT
GND
VIN
NR
4.99
kꢀ
4.99
kꢀ
-IN
RG
VOUT
1.13
kꢀ
100
kꢀ
2.87
kꢀ
0 V at 0°C
5 V at 200°C
25 mV/°C
100 ꢀ
INA819
OUT
RG
+IN
Pt100 RTD
100 ꢀ
-15 V
105 kꢀ 1.18 kꢀ
Copyright © 2018, Texas Instruments Incorporated
图9-8. A 3-Wire Interface for RTDs With Analog Linearization
5
4.5
4
0.018
0.016
0.014
0.012
0.01
3.5
3
2.5
2
0.008
0.006
0.004
0.002
0
1.5
1
0.5
0
0
50
100
150
200
0
50
100
150
200
Temperature (°C)
C001
Temperature (°C)
图9-10. Temperature Error Over the Full
图9-9. Transfer Function of a 3-Wire RTD Interface
Temperature Range
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10 Power Supply Recommendations
The nominal performance of the INA819 is specified with a supply voltage of ±15 V and midsupply reference
voltage. The device also operates using power supplies from ±2.25 V (4.5 V) to ±18 V (36 V) and non-midsupply
reference voltages with excellent performance. Parameters that can vary significantly with operating voltage and
reference voltage are shown in the 节7.6 section.
11 Layout
11.1 Layout Guidelines
Attention to good layout practices is always recommended. For best operational performance of the device, use
good PCB layout practices, including:
• Take care to make sure that both input paths are well-matched for source impedance and capacitance to
avoid converting common-mode signals into differential signals. Even slight mismatch in parasitic
capacitance at the gain setting pins can degrade CMRR over frequency. For example, in applications that
implement gain switching using switches or PhotoMOS® relays to change the value of RG, select the
component so that the switch capacitance is as small as possible and most importantly so that capacitance
mismatch between the RG pins is minimized.
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of the device.
Bypass capacitors reduce the coupled noise by providing low-impedance power sources local to the analog
circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better than in
parallel with the noisy trace.
• Place the external components as close to the device as possible. As shown in 图11-1, keep RG close to the
pins to minimize parasitic capacitance.
• Keep the traces as short as possible.
• Connect exposed thermal pad to negative supply –V.
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11.2 Layout Example
+V
C2
R2
+IN
-IN
RG
INA819
R3
OUT
RG
R1
C1
-V
+V
Use ground pours for
shielding the input
signal pairs
Place bypass
capacitors as close to
IC as possible
GND
C2
R1
œIN
1
2
3
4
œIN
RG
RG
+IN
+VS
OUT
REF
-VS
8
7
6
5
OUT
R3
Low-impedance
connection for
reference terminal
+IN
R2
GND
C1
REF
-V
Copyright © 2017, Texas Instruments Incorporated
图11-1. Example Schematic and Associated PCB Layout
Copyright © 2022 Texas Instruments Incorporated
34
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Product Folder Links: INA819
INA819
www.ti.com.cn
ZHCSJ44D –DECEMBER 2018 –REVISED APRIL 2022
12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
12.1.1.1 PSpice® for TI
PSpice® for TI is a design and simulation environment that helps evaluate performance of analog circuits. Create
subsystem designs and prototype solutions before committing to layout and fabrication, reducing development
cost and time to market.
12.1.1.2 TINA-TI™ Simulation Software (Free Download)
TINA-TI™ simulation software is a simple, powerful, and easy-to-use circuit simulation program based on a
SPICE engine. TINA-TI simulation software is a free, fully-functional version of the TINA™ software, preloaded
with a library of macromodels, in addition to a range of both passive and active models. TINA-TI simulation
software provides all the conventional dc, transient, and frequency domain analysis of SPICE, as well as
additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI simulation software offers extensive
post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer the
ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-
start tool.
备注
These files require that either the TINA software or TINA-TI software be installed. Download the free
TINA-TI simulation software from the TINA-TI™ software folder.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
Texas Instruments, Comprehensive Error Calculation for Instrumentation Amplifiers application note
12.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.5 Trademarks
TINA-TI™ and TI E2E™ are trademarks of Texas Instruments.
TINA™ is a trademark of DesignSoft, Inc.
Bluetooth® is a registered trademark of Bluetooth SIG, Inc.
PhotoMOS® is a registered trademark of Panasonic Electric Works Europe AG.
PSpice® is a registered trademark of Cadence Design Systems, Inc.
所有商标均为其各自所有者的财产。
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
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INA819
www.ti.com.cn
ZHCSJ44D –DECEMBER 2018 –REVISED APRIL 2022
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
36
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Product Folder Links: INA819
PACKAGE OPTION ADDENDUM
www.ti.com
27-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
INA819ID
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
VSSOP
VSSOP
SOIC
D
8
8
8
8
8
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
INA819
Samples
Samples
Samples
Samples
Samples
Samples
INA819IDGKR
INA819IDGKT
INA819IDR
DGK
DGK
D
2500 RoHS & Green
250 RoHS & Green
NIPDAUAG | SN
NIPDAUAG | SN
NIPDAU
1X3Q
1X3Q
2500 RoHS & Green
3000 RoHS & Green
INA819
INA819
INA819
INA819IDRGR
INA819IDRGT
SON
DRG
DRG
NIPDAU
SON
250
RoHS & Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
27-Jun-2023
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Jul-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
INA819IDGKR
INA819IDGKR
INA819IDGKT
INA819IDGKT
INA819IDR
VSSOP
VSSOP
VSSOP
VSSOP
SOIC
DGK
DGK
DGK
DGK
D
8
8
8
8
8
8
8
2500
2500
250
330.0
330.0
330.0
330.0
330.0
330.0
180.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
5.3
5.3
5.3
5.3
6.4
3.3
3.3
3.4
3.4
3.4
3.4
5.2
3.3
3.3
1.4
1.4
1.4
1.4
2.1
1.1
1.1
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q2
Q2
250
2500
3000
250
INA819IDRGR
INA819IDRGT
SON
DRG
DRG
SON
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Jul-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
INA819IDGKR
INA819IDGKR
INA819IDGKT
INA819IDGKT
INA819IDR
VSSOP
VSSOP
VSSOP
VSSOP
SOIC
DGK
DGK
DGK
DGK
D
8
8
8
8
8
8
8
2500
2500
250
366.0
366.0
366.0
366.0
356.0
367.0
210.0
364.0
364.0
364.0
364.0
356.0
367.0
185.0
50.0
50.0
50.0
50.0
35.0
35.0
35.0
250
2500
3000
250
INA819IDRGR
INA819IDRGT
SON
DRG
DRG
SON
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Jul-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
SOIC
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
INA819ID
D
8
75
506.6
8
3940
4.32
Pack Materials-Page 3
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DRG0008B
WSON - 0.8 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
3.1
2.9
PIN 1 INDEX AREA
0.8
0.7
C
SEATING PLANE
0.05 C
DIMENSION A
0.05
0.00
OPTION 01
OPTION 02
(0.1)
(0.2)
(DIM A) TYP
OPT 01 SHOWN
EXPOSED
THERMAL PAD
1.45 0.1
4
1
5
2X
1.5
2.4 0.1
8
6X 0.5
0.3
0.2
0.1
0.08
8X
0.6
0.4
PIN 1 ID
(OPTIONAL)
8X
C A B
C
4218886/A 01/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRG0008B
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.45)
SYMM
8X (0.7)
1
8
8X (0.25)
(2.4)
(0.95)
5
6X (0.5)
4
(R0.05) TYP
(0.475)
(
0.2) VIA
(2.7)
TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218886/A 01/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRG0008B
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
METAL
TYP
8X (0.7)
1
8X (0.25)
SYMM
8
(0.635)
6X (0.5)
(1.07)
5
4
(R0.05) TYP
(1.47)
(2.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
82% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218886/A 01/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
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