INA821ID [TI]
高带宽 (4.7MHz)、低噪声 (7nV/√Hz)、精密 (35μV)、低功耗仪表放大器 | D | 8 | -40 to 125;
| 型号： | INA821ID |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 高带宽 (4.7MHz)、低噪声 (7nV/√Hz)、精密 (35μV)、低功耗仪表放大器 | D | 8 | -40 to 125 放大器 仪表 仪表放大器 |
| 文件： | 总49页 (文件大小：1849K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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INA821
ZHCSIM8C –AUGUST 2018–REVISED JULY 2019
INA821 35µV 失调电压、7-nV/√Hz 噪声、低功耗精密仪表放大器
1 特性
3 说明
1
•
低失调电压：10µV（典型值）、35µV（最大值）
INA821 是一款高精度仪表放大器，可提供低功耗并且
可在较宽的单电源或双电源电压范围内工作。可通过单
个外部电阻器在 1 到 10,000 范围内设置任意增益。由
于采用超 β 输入晶体管（这些晶体管可提供较低的输
入失调电压、失调电压漂移、输入偏置电流以及输入电
压和电流噪声），该器件可提供出色的精度。附加电路
可以为输入提供高达 ±40V 的过压保护。
•
增益漂移：5ppm/°C (G = 1)、
35ppm/°C (G > 1)（最大值）
•
•
•
•
•
•
•
•
噪声：7nV/√Hz
带宽：4.7MHz (G = 1)、290kHz (G = 100)
采用 1nF 容性负载时保持稳定
输入保护电压高达 ±40V
共模抑制：112dB，G = 10（最小值）
电源抑制：110dB，G = 1（最小值）
电源电流：650µA（最大值）
电源电压范围：
INA821 经过优化，可提供较高的共模抑制比。当 G =
1 时，整个输入共模范围内共模抑制比超过 92dB。根
据设计，此器件采用低电压运行，由 4.5V 单电源和高
达 ±18V 的双电源供电。
–
–
单电源：4.5V 至 36V
INA821 采用 8 引脚 SOIC 和 8 引脚 VSSOP 封装，
并且额定工作温度范围为 –40°C 至 +125°C。
双电源：±2.25V 至 ±18V
•
•
额定温度范围：–40°C 至 +125°C
封装：8 引脚 SOIC 和 VSSOP
器件信息(1)
器件型号
INA821
封装
SOIC (8)
VSSOP (8)
封装尺寸（标称值）
4.90mm × 3.91mm
3.00mm × 3.00mm
2 应用
•
•
•
•
•
•
•
电池测试设备
流量变送器
ECG 放大器
模拟输入模块
断路器
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
工业过程控制
实验室仪表
INA821 简化内部原理图
输入阶段失调电压漂移的典型分布
+VS
30
Over-
Voltage
Protection
10 kꢀ
+
10 kꢀ
25
20
15
10
5
-IN
œ
RG
œ
24.7 kꢀ
24.7 kꢀ
RG
OUT
REF
+
RG
+IN
œ
Over-
Voltage
Protection
+
10 kꢀ
10 kꢀ
-VS
0
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
49.4 kW
RG
G = 1+
VO = G V+IN - V-IN + V
(
)
REF
Input Stage Offset Voltage Drift (mV/èC)
D002
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS893
INA821
ZHCSIM8C –AUGUST 2018–REVISED JULY 2019
www.ti.com.cn
目录
8.4 Device Functional Modes........................................ 26
Application and Implementation ........................ 26
9.1 Application Information............................................ 26
9.2 Typical Application .................................................. 29
9.3 Other Application Examples.................................... 31
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings ............................................................ 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information.................................................. 5
7.5 Electrical Characteristics........................................... 6
7.6 Typical Characteristics: Table of Graphs.................. 8
7.7 Typical Characteristics............................................ 10
Detailed Description ............................................ 19
8.1 Overview ................................................................. 19
8.2 Functional Block Diagram ....................................... 19
8.3 Feature Description................................................. 20
9
10 Power Supply Recommendations ..................... 32
11 Layout................................................................... 32
11.1 Layout Guidelines ................................................. 32
11.2 Layout Example .................................................... 33
12 器件和文档支持 ..................................................... 34
12.1 器件支持 ............................................................... 34
12.2 文档支持................................................................ 34
12.3 接收文档更新通知 ................................................. 34
12.4 社区资源................................................................ 34
12.5 商标....................................................................... 34
12.6 静电放电警告......................................................... 34
12.7 Glossary................................................................ 34
13 机械、封装和可订购信息....................................... 34
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision B (May 2019) to Revision C
Page
•
•
•
已更改 将 DGK (VSSOP) 封装从预告信息（预览）更改为生产数据（正在供货） ................................................................ 1
已更改 Figure 9, Typical Distribution of Input Offset Current, to show correct image.......................................................... 11
已更改 Figure 27, Typical Distribution of Gain Error, G = 1, to show improved data........................................................... 14
Changes from Revision A (December 2018) to Revision B
Page
•
•
已添加 向数据表中添加了 8 引脚 DGK (VSSOP) 预告信息封装和相关内容 .......................................................................... 1
已更改 应用列表项.................................................................................................................................................................. 1
Changes from Original (August 2018) to Revision A
Page
•
首次发布生产数据数据表 ........................................................................................................................................................ 1
2
Copyright © 2018–2019, Texas Instruments Incorporated
INA821
www.ti.com.cn
ZHCSIM8C –AUGUST 2018–REVISED JULY 2019
5 Device Comparison Table
DEVICE
DESCRIPTION
GAIN EQUATION
RG PINS AT PIN
35-µV Offset, 0.4 µV/°C VOS Drift, 7-nV/√Hz Noise, High-
Bandwidth, Precision Instrumentation Amplifier
INA821
INA819
INA818
INA828
INA333
PGA280
G = 1 + 49.4 kΩ / RG
2, 3
35-µV Offset, 0.4 µV/°C VOS Drift, 8-nV/√Hz Noise, Low-Power,
Precision Instrumentation Amplifier
G = 1 + 50 kΩ / RG
G = 1 + 50 kΩ / RG
G = 1 + 50 kΩ / RG
G = 1 + 100 kΩ / RG
Digital programmable
2, 3
1, 8
1, 8
1, 8
N/A
35-µV Offset, 0.4 µV/°C VOS Drift, 8-nV/√Hz Noise, Low-Power,
Precision Instrumentation Amplifier
50-µV Offset, 0.5 µV/°C VOS Drift, 7-nV/√Hz Noise, Low-Power,
Precision Instrumentation Amplifier
25-µV VOS, 0.1 µV/°C VOS Drift, 1.8-V to 5-V, RRO, 50-µA IQ,
Chopper-Stabilized INA
20-mV to ±10-V Programmable Gain IA With 3-V or 5-V
Differential Output; Analog Supply up to ±18 V
G = 0.2 V Differential Amplifier for ±10-V to 3-V and 5-V
Conversion
INA159
G = 0.2 V/V
N/A
N/A
PGA112
Precision Programmable Gain Op Amp With SPI
Digital programmable
Copyright © 2018–2019, Texas Instruments Incorporated
3
INA821
ZHCSIM8C –AUGUST 2018–REVISED JULY 2019
www.ti.com.cn
6 Pin Configuration and Functions
D and DGK Packages
8-Pin SOIC and 8-Pin VSSOP
Top View
œIN
RG
RG
+IN
1
2
3
4
8
7
6
5
+VS
OUT
REF
œVS
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
–IN
NO.
1
I
Negative (inverting) input
Positive (noninverting) input
Output
+IN
4
O
—
I
OUT
RG
7
2, 3
6
Gain setting pin. Place a gain resistor between pin 2 and pin 3.
Reference input. This pin must be driven by a low impedance source.
Negative supply
REF
–VS
+VS
—
—
5
8
Positive supply
4
Copyright © 2018–2019, Texas Instruments Incorporated
INA821
www.ti.com.cn
ZHCSIM8C –AUGUST 2018–REVISED JULY 2019
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–20
MAX
UNIT
Supply voltage
20
40
V
Voltage
–40
Signal input pins
REF pin
V
V
–20
20
Signal output pins
(-Vs) - 0.5
(+Vs) + 0.5
Output short-circuit(2)
Continuous
Operating Temperature, TA
Junction Temperature, TJ
Storage Temperature, Tstg
–50
150
175
150
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Short-circuit to VS / 2.
7.2 ESD Ratings
VALUE
±1500
±750
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
MAX
36
UNIT
Single-supply
Supply voltage VS
V
Dual-supply
±2.25
–40
±18
125
Specified temperature
Specified temperature
°C
7.4 Thermal Information
INA821
DGK (VSSOP)
THERMAL METRIC(1)
D (SOIC)
UNIT
8 PINS
119.6
66.3
8 PINS
215.4
66.3
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
61.9
97.8
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
20.5
10.5
ψJB
61.4
96.1
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2018–2019, Texas Instruments Incorporated
5
INA821
ZHCSIM8C –AUGUST 2018–REVISED JULY 2019
www.ti.com.cn
7.5 Electrical Characteristics
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT
INA821ID
10
35
40
µV
µV
TA = 25°C
INA821IDGK
INA821ID
Input stage offset
voltage(1)(2)
VOSI
75
µV
TA = –40°C to 125°C(3)
INA821IDGK
80
µV
vs temperature, TA = –40°C to 125°C
TA = 25°C
TA = –40°C to 125°C(3)
vs temperature, TA = –40°C to 125°C
G = 1, RTI
0.4
350
850
5
µV/°C
µV
50
Output stage offset
voltage(1)(2)
VOSO
µV
µV/°C
110
114
130
136
120
130
G = 10, RTI
Power-supply rejection
ratio
PSRR
dB
G = 100, RTI
135
G = 1000, RTI
140
zid
zic
Differential impedance
100 || 1
GΩ || pF
GΩ || pF
Common-mode
impedance
100 || 7
45
RFI filter, –3-dB
frequency
MHz
(V–) + 2
(V+) – 2
±40
VCM
Operating input range(4)
Input overvoltage range
V
V
VS = ±2.25 V to ±18 V, TA = –40°C to 125°C
TA = –40°C to 125°C(3)
See 图 51 to 图 54
At DC to 60 Hz, RTI, VCM = (V–) + 2 V to (V+) – 2 V,
G = 1
92
112
132
140
105
125
145
150
At DC to 60 Hz, RTI, VCM = (V–) + 2 V to (V+) – 2 V,
G = 10
Common-mode rejection
ratio
CMRR
dB
At DC to 60 Hz, RTI, VCM = (V–) + 2 V to (V+) – 2 V,
G = 100
At DC to 60 Hz, RTI, VCM = (V–) + 2 V to (V+) – 2 V,
G = 1000
BIAS CURRENT
VCM = VS / 2
0.15
0.15
0.5
2
IB
Input bias current
nA
nA
TA = –40°C to 125°C
VCM = VS / 2
0.5
2
IOS
Input offset current
TA = –40°C to 125°C
NOISE VOLTAGE
f = 1 kHz, G = 100, RS = 0 Ω
fB = 0.1 Hz to 10 Hz, G = 100, RS = 0 Ω
f = 1 kHz, RS = 0 Ω
7
0.14
65
nV/√Hz
µVPP
Input stage voltage
eNI
eNO
In
noise(5)
nV/√Hz
µVPP
Output stage voltage
noise(5)
fB = 0.1 Hz to 10 Hz, RS = 0 Ω
f = 1 kHz
2.5
130
4.7
fA/√Hz
pAPP
Noise current
fB = 0.1 Hz to 10 Hz, G = 100
GAIN
G
Gain equation
Range of gain
1 + (49.4 kΩ / RG)
V/V
V/V
1
10000
(1) Total offset, referred-to-input (RTI): VOS = (VOSI) + (VOSO / G).
(2) Offset drifts are uncorrelated. Input-referred offset drift is calculated using: ΔVOS(RTI) = √[ΔVOSI2 + (ΔVOSO / G)2]
(3) Specified by characterization.
(4) Input voltage range of the INA821 input stage. The input range depends on the common-mode voltage, differential voltage, gain, and
reference voltage. See Typical Characteristic curves 图 51 through 图 54 for more information.
(5) Total RTI voltage noise is equal to: eN(RTI) = √[eNI2 + (eNO / G)2]
6
Copyright © 2018–2019, Texas Instruments Incorporated
INA821
www.ti.com.cn
ZHCSIM8C –AUGUST 2018–REVISED JULY 2019
Electrical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
±0.005%
±0.025%
±0.025%
±0.05%
MAX
±0.025%
±0.15%
±0.15%
UNIT
G = 1, VO = ±10 V
G = 10, VO = ±10 V
G = 100, VO = ±10 V
G = 1000, VO = ±10 V
GE
Gain error
G = 1, TA = –40°C to 125°C
±5
±35
10
Gain vs temperature(6)
Gain nonlinearity
ppm/°C
ppm
G > 1, TA = –40°C to 125°C
G = 1 to 10, VO = –10 V to 10 V, RL = 10 kΩ
G = 100, VO = –10 V to 10 V, RL = 10 kΩ
G = 1000, VO = –10 V to 10 V, RL = 10 kΩ
G = 1 to 100, VO = –10 V to 10 V, RL = 2 kΩ
1
15
10
30
OUTPUT
(V–) +
0.15
Voltage swing
(V+) – 0.15
V
Load capacitance
stability
1000
pF
Closed-loop output
impedance
ZO
ISC
f = 10 kHz
1.3
Ω
Short-circuit current
Continuous to VS / 2
±20
mA
FREQUENCY RESPONSE
G = 1
4.7
970
290
30
MHz
kHz
G = 10
BW
SR
tS
Bandwidth, –3 dB
Slew rate
G = 100
G = 1000
G = 1, VO = ±10 V
2.0
6
V/µs
0.01%, G = 1 to 100, VSTEP = 10 V
0.01%, G = 1000, VSTEP = 10 V
0.001%, G = 1 to 100, VSTEP = 10 V
0.001%, G = 1000, VSTEP = 10 V
40
Settling time
µs
10
50
REFERENCE INPUT
RIN Input impedance
10
kΩ
V
Voltage range
(V–)
(V+)
Gain to output
1
V/V
Reference gain error
0.01%
POWER SUPPLY
Single-supply
4.5
36
±18
650
870
VS
IQ
Power-supply voltage
V
Dual-supply
±2.25
VIN = 0 V
600
Quiescent current
µA
vs temperature, TA = –40°C to 125°C
(6) The values specified for G > 1 do not include the effects of the external gain-setting resistor, "RG".
版权 © 2018–2019, Texas Instruments Incorporated
7
INA821
ZHCSIM8C –AUGUST 2018–REVISED JULY 2019
www.ti.com.cn
7.6 Typical Characteristics: Table of Graphs
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
表 1. Table of Graphs
DESCRIPTION
Typical Distribution of Input Stage Offset Voltage
Typical Distribution of Input Stage Offset Voltage Drift
Typical Distribution of Output Stage Offset Voltage
Typical Distribution of Output Stage Offset Voltage Drift
Input Stage Offset Voltage vs Temperature
Output Stage Offset Voltage vs Temperature
Typical Distribution of Input Bias Current, TA = 25°C
Typical Distribution of Input Bias Current, TA = 90°C
Typical Distribution of Input Offset Current
Input Bias Current vs Temperature
FIGURE
图 1
图 2
图 3
图 4
图 5
图 6
图 7
图 8
图 9
图 10
图 11
图 12
图 13
图 14
图 15
图 16
图 17
图 18
图 19
图 20
图 21
图 22
图 23
图 24
图 25
图 26
图 27
图 28
图 29
图 30
图 31
图 32
图 33
图 34
图 35
图 36
图 37
图 38
图 39
图 40
图 41
图 42
图 43
图 44
图 45
Input Offset Current vs Temperature
Typical CMRR Distribution, G = 1
Typical CMRR Distribution, G = 10
CMRR vs Temperature, G = 1
CMRR vs Temperature, G = 10
Input Current vs Input Overvoltage
CMRR vs Frequency (RTI)
CMRR vs Frequency (RTI, 1-kΩ source imbalance)
Positive PSRR vs Frequency (RTI)
Negative PSRR vs Frequency (RTI)
Gain vs Frequency
Voltage Noise Spectral Density vs Frequency (RTI)
Current Noise Spectral Density vs Frequency (RTI)
0.1-Hz to 10-Hz RTI Voltage Noise, G = 1
0.1-Hz to 10-Hz RTI Voltage Noise, G = 1000
0.1-Hz to 10-Hz RTI Current Noise
Typical Distribution of Gain Error, G = 1
Typical Distribution of Gain Error, G = 10
Input Bias Current vs Common-Mode Voltage
Gain Error vs Temperature, G = 1
Gain Error vs Temperature, G = 10
Supply Current vs Temperature
Gain Nonlinearity, G = 1
Gain Nonlinearity, G = 10
Offset Voltage vs Negative Common-Mode Voltage
Offset Voltage vs Positive Common-Mode Voltage
Positive Output Voltage Swing vs Output Current
Negative Output Voltage Swing vs Output Current
Short-Circuit Current vs Temperature
Large-Signal Frequency Response
THD+N vs Frequency
Overshoot vs Capacitive Loads
Small-Signal Response, G = 1
Small-Signal Response, G = 10
Small-Signal Response, G = 100
8
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INA821
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ZHCSIM8C –AUGUST 2018–REVISED JULY 2019
Typical Characteristics: Table of Graphs (接下页)
表 1. Table of Graphs (接下页)
DESCRIPTION
Small-Signal Response, G = 1000
FIGURE
图 46
图 47
图 48
图 49
图 50
图 51
图 52
图 53
图 54
Large-Signal Step Response
Closed-Loop Output Impedance
Differential-Mode EMI Rejection Ratio
Common-Mode EMI Rejection Ratio
Input Common-Mode Voltage vs Output Voltage, G = 1, VS = 5 V
Input Common-Mode Voltage vs Output Voltage, G = 100, VS = 5 V
Input Common-Mode Voltage vs Output Voltage, VS = ±5 V
Input Common-Mode Voltage vs Output Voltage, VS = ±15 V
版权 © 2018–2019, Texas Instruments Incorporated
9
INA821
ZHCSIM8C –AUGUST 2018–REVISED JULY 2019
www.ti.com.cn
7.7 Typical Characteristics
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
15
10
5
30
25
20
15
10
5
0
0
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
-30 -25 -20 -15 -10 -5
0
5
10 15 20 25 30
Input Stage Offset Voltage (mV)
Input Stage Offset Voltage Drift (mV/èC)
D001
D002
N = 2667
Mean = 3.1 µV
Std. Dev. = 8.1 µV
N = 81
Mean = -0.03 µV/°C
Std. Dev. = 0.09 µV/°C
图 1. Typical Distribution of
图 2. Typical Distribution of
Input Stage Offset Voltage
Input Stage Offset Voltage Drift
15
10
5
16
14
12
10
8
6
4
2
0
0
-200
-100
0
100
200
-5
-4
-3
-2
-1
0
1
2
3
4
5
Input Stage Offset Voltage (mV)
Output Offset Voltage Drift (mV/èC)
D003
D004
N = 2667
Mean = 7.7 µV
Std. Dev. = 50.7 µV
N = 81
Mean = –1.09 µV/°C
Std. Dev. = 0.94 µV/°C
图 3. Typical Distribution of
图 4. Typical Distribution of
Output Stage Offset Voltage
Output Stage Offset Voltage Drift
100
75
500
400
300
200
100
0
50
25
0
-100
-200
-300
-400
-500
-25
-50
-75
Mean
+3s
-3s
Mean
+3s
-3s
-100
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Temperature (èC)
Temperature (èC)
D005
D006
81 units
81 units
图 5. Input Stage Offset Voltage vs Temperature
图 6. Output Stage Offset Voltage vs Temperature
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Typical Characteristics (接下页)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
20
15
10
5
20
15
10
5
0
0
-300
-200
-100
0
100
200
300
-200 -150 -100
-50
0
50
100
150
200
Input Bias Current (pA)
Input Bias Current (pA)
D007
D008
N = 292
Mean = 45 pA
Std. Dev. = 62 pA
N = 292
Mean = 34 pA
Std. Dev. = 52 pA
TA = 25°C
TA = 90°C
图 7. Typical Distribution of Input Bias Current,
图 8. Typical Distribution of Input Bias Current,
TA = 25°C
TA = 90°C
25
20
15
10
5
1
0.8
0.6
0.4
0.2
0
Avg
+3s
-3s
-0.2
-0.4
-0.6
-0.8
-1
0
-300
-200
-100
0
100
200
300
-50 -30 -10 10
30
50
70
90 110 130 150
Input Offset Current (pA)
Temperature (èC)
D050
D009
N = 294
G = 1
N = 94
Mean = –38.82 pA
Std. Dev. = 47.24 pA
图 9. Typical Distribution of Input Offset Current
图 10. Input Bias Current vs Temperature
25
20
15
10
5
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
Avg
+3s
-3s
0
-20 -16 -12
-8
-4
0
4
8
12
16
20
-50 -30 -10 10
30
50
70
90 110 130 150
Temperature (èC)
Common-Mode Rejection Ratio (mV/V)
D010
D011
N = 294
G = 1
N = 294
G = 1
Mean = 4.87 µV/V
Std. Dev. = 4.14 µV/V
图 11. Input Offset Current vs Temperature
图 12. Typical CMRR Distribution, G = 1
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Typical Characteristics (接下页)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
150
125
100
75
30
25
20
15
10
5
Unit 1
Unit 2
Unit 3
Unit 4
Unit 5
0
50
-50
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
-25
0
25
50
75
100
125
150
Common-Mode Rejection Ratio (mV/V)
Temperature (èC)
D012
D013
N = 5
G = 1
N = 294
G = 10
Mean = 0.51 µV/V
Std. Dev. = 0.42 µV/V
图 13. Typical CMRR Distribution, G = 10
图 14. CMRR vs Temperature, G = 1
175
150
125
100
75
10
20
16
12
8
8
6
4
2
4
0
0
-2
-4
-6
-8
-10
-4
Unit 1
-8
Unit 2
Unit 3
Unit 4
Unit 5
-12
-16
-20
Input Current
Output Voltage
-50
-25
0
25
50
75
100
125
150
-50 -40 -30 -20 -10
0
10
20
30
40
50
Temperature (èC)
Input Voltage (V)
D014
D015
N = 5
VS = ±18 V
G = 10
图 15. CMRR vs Temperature, G = 10
图 16. Input Current vs Input Overvoltage
160
140
140
120
100
80
120
100
80
60
40
20
0
60
40
G = 1
G = 1
G = 10
G = 100
G = 1000
G = 10
G = 100
G = 1000
20
0
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
Frequency (Hz)
Frequency (Hz)
D016
D017
图 17. CMRR vs Frequency (RTI)
图 18. CMRR vs Frequency
(RTI, 1-kΩ source imbalance)
12
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Typical Characteristics (接下页)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
160
140
120
100
80
160
140
120
100
80
60
60
40
40
20
20
G = 1
G = 1
G = 10
G = 100
G = 1000
0
0
G = 10
G = 100
G = 1000
-20
-40
-20
-40
1
10
100
1k
10k
100k
1
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
D018
D019
图 19. Positive PSRR vs Frequency (RTI)
图 20. Negative PSRR vs Frequency (RTI)
80
60
40
20
0
1000
100
10
G = 1
G = 10
G = 100
G = 1000
-20
-40
-60
G = 1
G = 10
G = 100
G = 1000
10
100
1k
10k
100k
1M
10M
100m
1
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
D020
D021
图 21. Gain vs Frequency
图 22. Voltage Noise Spectral Density vs Frequency (RTI)
1k
100
10
Time (1 s/div)
100m
1
10
100
1k
10k
Frequency (Hz)
D023
D022
G = 1
图 24. 0.1-Hz to 10-Hz RTI Voltage Noise, G = 1
图 23. Current Noise Spectral Density vs Frequency (RTI)
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Typical Characteristics (接下页)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
Time (1 s/div)
Time (1 s/div)
D024
D025
G = 1
G = 1000
图 25. 0.1-Hz to 10-Hz RTI Voltage Noise, G = 1000
图 26. 0.1-Hz to 10-Hz RTI Current Noise
30
25
20
15
10
5
20
18
16
14
12
10
8
6
4
2
0
0
-900
-250 -200 -150 -100 -50
0
50 100 150 200 250
-600
-300
0
300
600
900
Gain Error (ppm)
Input Stage Offset Voltage (mV)
D026
D027
N = 5412
G = 1
Mean = 30 ppm
Std. Dev. = 55 ppm
N = 293
G = 10
Mean = 152 ppm
Std. Dev. = 291 ppm
图 27. Typical Distribution of Gain Error, G = 1
图 28. Typical Distribution of Gain Error, G = 10
100
80
60
40
20
0
0.5
0.3
-45èC
25èC
125èC
0.1
-0.1
-0.3
-0.5
-20
-40
-15 -12
-9
-6
-3
0
3
6
9
12
15
-50 -30 -10 10
30
50
70
90 110 130 150
Common-Mode Voltage (V)
Temperature (èC)
D028
D029
VS = ±15 V
Average of 294 units
图 30. Gain Error vs Temperature, G = 1
G = 1
图 29. Input Bias Current vs Common-Mode Voltage
14
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Typical Characteristics (接下页)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
1500
1250
1000
750
0.9
0.84
0.78
0.72
0.66
0.6
500
250
0
-250
-500
-750
-1000
-1250
-1500
0.54
0.48
0.42
0.36
0.3
VS = ê 15 V
VS = ê 2.25 V
-50
-25
0
25
50
75
100
125
150
-50 -30 -10 10
30
50
70
90 110 130 150
Temperature (èC)
Temperature (èC)
D030
D031
Average of 294 units
图 31. Gain Error vs Temperature, G = 10
G = 10
图 32. Supply Current vs Temperature
10
8
1
0.8
0.6
0.4
0.2
0
6
4
2
0
-2
-4
-6
-8
-10
-12
-14
-16
-0.2
-0.4
-0.6
-0.8
-1
-10
-8
-6
-4
-2
0
2
4
6
8
10
-10
-8
-6
-4
-2
0
2
4
6
8
10
Output Voltage (V)
Output Voltage (V)
D032
D033
G = 1
G = 10
图 33. Gain Nonlinearity, G = 1
图 34. Gain Nonlinearity, G = 10
175
150
125
100
75
150
125
100
75
-40èC
25èC
-40èC
25èC
85èC
125èC
85èC
125èC
50
50
25
25
0
0
-25
-50
-75
-25
-50
-15
-14.6 -14.2 -13.8 -13.4
-13
-12.6 -12.2
12
12.4
12.8
13.2
13.6
14
14.4
14.8
Input Common-Mode Voltage (V)
Input Common-Mode Voltage (V)
D034
D035
图 35. Offset Voltage vs Negative Common-Mode Voltage
图 36. Offset Voltage vs Positive Common-Mode Voltage
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Typical Characteristics (接下页)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
15
14.9
14.8
14.7
14.6
14.5
14.4
14.3
14.2
14.1
14
-14
-14.1
-14.2
-14.3
-14.4
-14.5
-14.6
-14.7
-14.8
-14.9
-15
œ40èC
25èC
85èC
125èC
œ40èC
25èC
85èC
125èC
0
2
4
6
8
10
12
14
16
0
2
4
6
8
10
12
14
16
Output Current (mA)
Output Current (mA)
D036
D037
图 37. Positive Output Voltage Swing vs Output Current
图 38. Negative Output Voltage Swing vs Output Current
40
30
20
Vs = ê15 V
Vs = ê5 V
18
20
16
14
12
10
8
10
0
-10
-20
-30
-40
6
4
ISC, Source
ISC, Sink
-50
-60
2
0
-50 -30 -10 10
30
50
70
90 110 130 150
100
1k
10k
100k
1M
10M
Temperature (èC)
Frequency (Hz)
D038
D039
图 39. Short-Circuit Current vs Temperature
图 40. Large-Signal Frequency Response
1
0.1
-40
50
G = 1
G = 10
G = 100
Positive Overshoot
Negative Overshoot
45
40
35
30
25
20
15
10
5
-60
0.01
0.001
-80
-100
0
10
100
1k
10k
100k
1
10
100
1000
Frequency (Hz)
Capacitive Load (pF)
D040
D041
500-kHz measurement bandwidth
1-VRMS output voltage 100-kΩ load
图 41. THD+N vs Frequency
图 42. Overshoot vs Capacitive Loads
16
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Typical Characteristics (接下页)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
75
50
25
0
75
50
25
0
-25
-50
-75
-25
-50
-75
-5
-2.5
0
2.5
5
7.5
10
12.5
15
-5
-2.5
0
2.5
5
7.5
10
12.5
15
Time (µs)
Time (µs)
D042
D043
G = 1
RL = 10 kΩ
CL = 100 pF
G = 10
RL = 10 kΩ
CL = 100 pF
图 43. Small-Signal Response
图 44. Small-Signal Response
75
50
25
0
75
50
25
0
-25
-50
-25
-50
-75
-5
-75
-25
-2.5
0
2.5
5
7.5
10
12.5
15
0
25
50
75
Time (µs)
Time (µs)
D044
D045
G = 100
RL = 10 kΩ
CL = 100 pF
G = 1000
RL = 10 kΩ
CL = 100 pF
图 45. Small-Signal Response
图 46. Small-Signal Response
Output
Input
100
10
1
0.1
Time (10 µs/div)
1
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
D046
D047
图 47. Large-Signal Step Response
图 48. Closed-Loop Output Impedance
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Typical Characteristics (接下页)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
120
100
80
60
40
20
0
140
120
100
80
60
40
20
0
10M
100M
Frequency (Hz)
1G
10G
10M
100M
Frequency (Hz)
1G
10G
D048
D049
图 49. Differential-Mode EMI Rejection Ratio
图 50. Common-Mode EMI Rejection Ratio
5
4
3
2
1
0
5
4
3
2
1
0
VREF = 0 V
VREF = 0 V
VREF = 2.5 V
VREF = 2.5 V
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Output Voltage (V)
G = 1
Output Voltage (V)
C006
C006
VS = 5 V
VS = 5 V
G = 100
图 51. Input Common-Mode Voltage vs Output Voltage
图 52. Input Common-Mode Voltage vs Output Voltage
5
4
15
10
5
3
2
1
0
0
-5
-1
-2
-3
-10
-15
G = 1
G = 1
-4
G = 100
-20
G = 100
-5
0
10
20
0
2
4
±
20
10
±±
±4
±2
Output Voltage (V)
Output Voltage (V)
C006
C00±
VS = ±5 V
VREF = 0 V
VS = ±15 V
VREF = 0 V
图 53. Input Common-Mode Voltage vs Output Voltage
图 54. Input Common-Mode Voltage vs Output Voltage
18
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8 Detailed Description
8.1 Overview
The INA821 is a monolithic precision instrumentation amplifier that incorporates a current-feedback input stage
and a four-resistor difference amplifier output stage. The functional block diagram in the next section shows how
the differential input voltage is buffered by Q1 and Q2 and is forced across RG, which causes a signal current to
flow through RG, R1, and R2. The output difference amplifier, A3, removes the common-mode component of the
input signal and refers the output signal to the REF pin. The VBE and voltage drop across R1 and R2 produces
output voltages on A1 and A2 that are approximately 0.8 V lower than the input voltages.
Each input is protected by two field-effect transistors (FETs) that provide a low series resistance under normal
signal conditions, and preserve excellent noise performance. When excessive voltage is applied, these
transistors limit input current to approximately 8 mA.
8.2 Functional Block Diagram
+VS
VB
RB
RB
IB Cancellation
IB Cancellation
10 kꢀ
-VS +VS
10 kꢀ
œ
A1
A2
A3
+
OUT
REF
10 kꢀ
10 kꢀ
+VS
+VS
-VS +VS
Q2
Q1
Super-ꢁ
Super-ꢁ
-IN
+IN
NPN
NPN
Over-Voltage
Protection
+VS
+VS
Over-Voltage
Protection
R2
24.7 kꢀ
R1
24.7 kꢀ
RG
(External)
-VS
-VS
RG
RG
Copyright © 2017, Texas Instruments Incorporated
-VS
-VS
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8.3 Feature Description
8.3.1 Setting the Gain
图 55 shows that the gain of the INA821 is set by a single external resistor (RG) connected between the RG pins
(pins 1 and 8).
V+
+VS
Overvoltage
Protection
10 kꢀ
+
10 kꢀ
-IN
œ
RG
œ
49.4 kW
24.7 kꢀ
24.7 kꢀ
OUT
REF
G = 1+
RG
RG
+
VO = G V+IN - V-IN + V
(
)
REF
RG
+IN
œ
Overvoltage
Protection
+
10 kꢀ
10 kꢀ
-VS
Copyright © 2017, Texas Instruments Incorporated
V-
图 55. Simplified Diagram of the INA821 With Gain and Output Equations
The value of RG is selected according to:
49.4 kW
G = 1+
RG
(1)
表 2 lists several commonly used gains and resistor values. The 49.4-kΩ term in 公式 1 is a result of the sum of
the two internal 24.7-kΩ feedback resistors. These on-chip resistors are laser-trimmed to accurate absolute
values. The accuracy and temperature coefficients of these resistors are included in the gain accuracy and drift
specifications of the INA821. As shown in 图 55 and explained in more details in the Layout section, make sure
to connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, that are placed as
close to the device as possible.
表 2. Commonly-Used Gains and Resistor Values
DESIRED GAIN
RG (Ω)
NC
NEAREST 1% RG (Ω)
1
2
NC
49.9 k
12.4 k
5.49 k
2.61 k
1 k
49.4 k
12.35 k
5.489 k
2.600 k
1.008 k
499
5
10
20
50
100
200
500
1000
499
248
249
99
100
49.4
49.9
20
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8.3.1.1 Gain Drift
The stability and temperature drift of the external gain setting resistor (RG) also affects gain. The contribution of
RG to gain accuracy and drift is determined from 公式 1.
The best gain drift of 5 ppm/℃ (maximum) is achieved when the INA821 uses G = 1 without RG connected. In
this case, gain drift is limited by the slight mismatch of the temperature coefficient of the integrated 10-kΩ
resistors in the differential amplifier (A3). At gains greater than 1, gain drift increases as a result of the individual
drift of the 24.7-kΩ resistors in the feedback of A1 and A2 relative to the drift of the external gain resistor (RG.)
The low temperature coefficient of the internal feedback resistors significantly improves the overall temperature
stability of applications using gains greater than 1 V/V over alternate options.
Low resistor values required for high gain make wiring resistance an important consideration. Sockets add to the
wiring resistance and contribute additional gain error (such as a possible unstable gain error) at gains of
approximately 100 or greater. To maintain stability, avoid parasitic capacitance of more than a few picofarads at
RG connections. Careful matching of any parasitics on the RG pins maintains optimal CMRR over frequency; see
图 17.
8.3.2 EMI Rejection
Texas Instruments developed a method to accurately measure the immunity of an amplifier over a broad
frequency spectrum extending from 10 MHz to 6 GHz. This method uses an EMI rejection ratio (EMIRR) to
quantify the ability of the INA821 to reject EMI. The offset resulting from an input EMI signal is calculated using
公式 2:
EMIRR (dB)
≈
’
2
≈
∆
’
÷
-
VRF_PEAK
100 mVP
∆
«
÷
◊
20
DVOS
=
∂10
∆
«
÷
◊
where
•
VRF_PEAK is the peak amplitude of the input EMI signal.
(2)
图 56 and 图 57 show the INA821 EMIRR graph for differential and common-mode EMI rejection across this
frequency range. 表 3 lists the EMIRR values for the INA821 at frequencies commonly encountered in real-world
applications. Applications listed in 表 3 are centered on or operated near the particular frequency shown.
Depending on the end-system requirements, additional EMI filters may be required near the signal inputs of the
system. Incorporating known good practices such as using short traces, low-pass filters, and damping resistors
combined with parallel and shielded signal routing may be required.
140
120
100
80
120
100
80
60
40
20
0
60
40
20
0
10M
100M
Frequency (Hz)
1G
10G
10M
100M
Frequency (Hz)
1G
10G
D049
D048
图 56. Common-Mode EMIRR Testing
图 57. Differential Mode EMIRR Testing
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表 3. INA821 EMIRR for Frequencies of Interest
COMMON-MODE
EM is a result of
the sum of the
two IRR
DIFFERENTIAL
EMIRR
FREQUENCY
APPLICATION OR ALLOCATION
Mobile radio, mobile satellite, space operation, weather, radar, ultrahigh-frequency (UHF)
applications
400 MHz
900 MHz
1.8 GHz
60 dB
58 dB
66 dB
88 dB
60 dB
89 dB
Global system for mobile communications (GSM) applications, radio communication, navigation,
GPS (up to 1.6 GHz), GSM, aeronautical mobile, UHF applications
GSM applications, mobile personal communications, broadband, satellite,
L-band (1 GHz to 2 GHz)
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific
and medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
2.4 GHz
3.6 GHz
5 GHz
73 dB
99 dB
83 dB
98 dB
111 dB
91 dB
Radiolocation, aero communication and navigation, satellite, mobile, S-band
802.11a, 802.11n, aero communication and navigation, mobile communication, space and
satellite operation, C-band (4 GHz to 8 GHz)
8.3.3 Input Common-Mode Range
The linear input voltage range of the INA821 input circuitry extends within 2 V of power supplies and maintains
excellent common-mode rejection throughout this range. The common-mode range for the most common
operating conditions are shown in 图 58 to图 61. The common-mode range for other operating conditions is best
calculated using the Common-Mode Input Range Calculator for Instrumentation Amplifiers.
5
4
3
2
1
0
5
4
3
2
1
0
VREF = 0 V
VREF = 0 V
VREF = 2.5 V
VREF = 2.5 V
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Output Voltage (V)
G = 1
Output Voltage (V)
C006
C006
VS = 5 V
VS = 5 V
G = 100
图 58. Input Common-Mode Voltage vs Output Voltage
图 59. Input Common-Mode Voltage vs Output Voltage
5
4
15
10
5
3
2
1
0
0
-5
-1
-2
-3
-10
-15
G = 1
G = 1
-4
G = 100
-20
G = 100
-5
0
10
20
0
2
4
±
20
10
±±
±4
±2
Output Voltage (V)
Output Voltage (V)
C006
C00±
VS = ±5 V
VREF = 0 V
VS = ±15 V
VREF = 0 V
图 60. Input Common-Mode Voltage vs Output Voltage
图 61. Input Common-Mode Voltage vs Output Voltage
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22
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8.3.4 Input Protection
The inputs of the INA821 device are individually protected for voltages up to ±40 V. For example, a condition of
–40 V on one input and +40 V on the other input does not cause damage. Internal circuitry on each input
provides low series impedance under normal signal conditions. If the input is overloaded, the protection circuitry
limits the input current to a value of approximately 8 mA.
+V
ZD1
+VS
IN
Overvoltage
Protection
Input Voltage
Source
+
Input Transistor
œ
-VS
ZD2
-V
图 62. Input Current Path During an Overvoltage Condition
During an input overvoltage condition, current flows through the input protection diodes into the power supplies;
see 图 62. If the power supplies are unable to sink current, then Zener diode clamps (ZD1 and ZD2 in 图 62)
must be placed on the power supplies to provide a current pathway to ground. 图 63 shows the input current for
input voltages from –40 V to 40 V when the INA821 is powered by ±15-V supplies.
10
8
20
16
12
8
6
4
2
4
0
0
-2
-4
-6
-8
-10
-4
-8
-12
-16
-20
Input Current
Output Voltage
-50 -40 -30 -20 -10
0
10
20
30
40
50
Input Voltage (V)
D015
图 63. Input Current vs Input Overvoltage
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INA821
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8.3.5 Operating Voltage
The INA821 operates over a power-supply range of 4.5 V to 36 V (±2.25 V to ±18 V).
CAUTION
Supply voltages higher than 40 V (±20 V) can permanently damage the device.
Parameters that vary over supply voltage or temperature are shown in the Typical
Characteristics section of this data sheet.
8.3.6 Error Sources
Most modern signal-conditioning systems calibrate errors at room temperature. However, calibration of errors
that result from a change in temperature is normally difficult and costly. Therefore, minimize these errors by
choosing high-precision components, such as the INA821, that have improved specifications in critical areas that
impact the precision of the overall system. 图 64 shows an example application.
+15 V
C2
RS+
1 kꢀ
RG
VDIFF = VOUT / G
5.49 kꢀ
INA
RG
VOUT = 1 V
RSœ
0.99 kꢀ
VCM = 10 V
C1
œ15 V
图 64. Example Application with G = 10 V/V and 1 V Output Voltage
Resistor-adjustable devices (such as the INA821) show the lowest gain error in G = 1 because of the inherently
well-matched drift of the internal resistors of the differential amplifier. At gains greater than 1 (for instance, G =
10 V/V or G = 100 V/V), the gain error becomes a significant error source because of the contribution of the
resistor drift of the 24.7-kΩ feedback resistors in conjunction with the external gain resistor. Except for very high
gain applications, the gain drift is by far the largest error contributor compared to other drift errors, such as offset
drift.
The INA821 offers excellent gain error over temperature for both G > 1 and G = 1 (no external gain resistor). 表 5
summarizes the major error sources in common INA applications and compares the three cases of G = 1 (no
external resistor) and G = 10 (5.49-kΩ external resistor) and G = 100 (499-Ω external resistor). All calculations
are assuming an output voltage of VOUT = 1 V. Thus, the input signal VDIFF (given by VDIFF= VOUT/G) exhibits
smaller and smaller amplitudes with increasing gain G. In this example, VDIFF = 1 mV at G = 1000. All
calculations refer the error to the input for easy comparison and system evaluation. As 表 5 shows, errors
generated by the input stage (such as input offset voltage) are more dominant at higher gain, while the effects of
output stage are suppressed because they are divided by the gain when referring them back to the input. the
gain error and gain drift error are much more significant for gains greater than 1 because of the contribution of
the resistor drift of the 24.7-kΩ feedback resistors in conjunction with the external gain resistor. In most
applications, static errors (absolute accuracy errors) can readily be removed during calibration in production,
while the drift errors are the key factors limiting overall system performance.
24
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表 4. System Specifications for Error Calculation
QUANTITY
VALUE
1
UNIT
VOUT
V
VCM
10
V
VS
1
V
Ω
RS+
RS–
1000
999
0.01
10
Ω
RG tolerance
RG drift
%
ppm/°C
°C
Temperature range upper limit
105
表 5. Error Calculation
INA821 VALUES
G = 1
G = 100
ERROR
(ppm)
G = 1000
ERROR
(ppm)
ERROR SOURCE
ERROR CALCULATION
SPECIFICATION
UNIT
ERROR
(ppm)
ABSOLUTE ACCURACY AT 25°C
Input offset voltage
VOSI / VDIFF
35
300
0.5
µV
µV
nA
35
350
1
350
350
5
3500
350
50
Output offset voltage
VOSO / (G × VDIFF)
Input offset current
IOS × maximum (RS+, RS–) / VDIFF
92 (G = 1),
112 (G = 10),
132 (G = 100)
VCM / (10CMRR/20 × VDIFF
)
CMRR (min)
PSRR (min)
dB
dB
251
3
251
20
251
32
110 (G = 1),
114 (G = 10),
130 (G = 100)
(VCC – VS)/ (10PSRR/20 × VDIFF
)
0.02 (G = 1),
0.15 (G = 10, 100)
GE(%) × 104
GE(%) × 104
sum of all errors
Gain error from INA (max)
%
%
—
200
100
940
1500
100
1500
100
Gain error from external resistor RG (max)
0.01
—
Total absolute accuracy error (ppm) at 25°C,
worst case
2576
5738
Total absolute accuracy error (ppm) at 25°C,
average
rms sum of all errors
GTC × (TA – 25)
—
—
487
1603
3834
DRIFT TO 105°C
5 (G = 1),
35 (G = 10, 100)
Gain drift from INA (max)
ppm/°C
400
2800
2800
Gain drift from external resistor RG (max)
Input offset voltage drift (max)
Output offset voltage drift
GTC × (TA – 25)
10
0.4
5
ppm/°C
µV/°C
µV/°C
800
32
800
320
400
800
3200
400
(VOSI_TC / VDIFF) × (TA – 25)
[VOSO_TC / ( G × VDIFF)] × (TA – 25)
400
IOS_TC × maximum (RS+, RS–) ×
(TA – 25) / VDIFF
Offset current drift
20
pA/°C
2
16
160
Total drift error to 105°C (ppm), worst case
Total drift error to 105°C (ppm), typical
RESOLUTION
sum of all errors
—
—
—
—
1634
980
4336
2957
7360
4348
rms sum of all errors
10 (G = 1, 10),
15 (G = 100)
Gain nonlinearity
ppm of FS
µVPP
10
1335
0.4
10
886
2
15
3566
11
2
eNO
6
eNI = 7,
eNO = 65
2
(eNI
+
´
´
BW
Voltage noise (at 1 kHz)
G
VDIFF
IN × maximum (RS+, RS–) × √BW /
Current noise (at 1kHz)
0.13
pA/√Hz
VDIFF
Total resolution error (ppm), worst case
Total resolution error (ppm), typical
TOTAL ERROR
sum of all errors
—
—
—
—
1345
1335
896
886
3581
3566
rms sum of all errors
Total error (ppm), worst case
Total error (ppm), typical
sum of all errors
—
—
—
—
3919
1726
7808
3478
16724
6806
rms sum of all errors
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8.4 Device Functional Modes
The INA821 has a single functional mode and is operational when the power supply voltage is greater than 4.5 V
(±2.25 V). The maximum power-supply voltage for the INA821 is 36 V (±18 V).
9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Reference Pin
The output voltage of the INA821 is developed with respect to the voltage on the reference pin (REF.) Often, in
dual-supply operation, REF (pin 6) connects to the low-impedance system ground. In single-supply operation,
offsetting the output signal to a precise midsupply level is useful (for example, 2.5 V in a 5-V supply
environment). To accomplish this level shift, a voltage source must be connected to the REF pin to level-shift the
output so that the INA821 drives a single-supply analog-to-digital converter (ADC).
The voltage source applied to the reference pin must have a low output impedance. As shown in 图 65, any
resistance at the reference pin ( RREF in 图 65) is in series with one of the internal 10-kΩ resistors.
V+
+VS
Over-
10 kꢀ
Voltage
+
10 kꢀ
-IN
Protection
œ
RG
œ
24.7 kꢀ
24.7 kꢀ
RG
OUT
REF
+
RG
+IN
œ
Over-
Voltage
+
RREF
10 kꢀ
10 kꢀ
Protection
-VS
V-
图 65. Parasitic Resistance Shown at the Reference Pin
26
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Application Information (接下页)
The parasitic resistance at the reference pin (RREF) creates an imbalance in the four resistors of the internal
difference amplifier that results in a degraded common-mode rejection ratio (CMRR). 图 66 shows the
degradation in CMRR of the INA821 as a result of the increased resistance at the reference pin. For the best
performance, keep the source impedance to the REF pin (RREF) less than 5 Ω.
120
100
80
60
0 Ω
40
5 Ω
10 Ω
20
15 Ω
20 Ω
0
10
100
1k
Frequency (Hz)
10k
图 66. The Effect of Increasing Resistance at the Reference Pin
Voltage reference devices are an excellent option for providing a low-impedance voltage source for the reference
pin. However, if a resistor voltage divider generates a reference voltage, the divider must be buffered by an op
amp, as 图 67 shows, to avoid CMRR degradation.
5 V
+IN
RG
RG
INA821
RG
OUT
œIN
5 V
5 V
100 kꢀ
+
OPA191
1 ꢁF
œ
100 kꢀ
Copyright © 2017, Texas Instruments Incorporated
图 67. Using an Op Amp to Buffer Reference Voltages
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Application Information (接下页)
9.1.2 Input Bias Current Return Path
The input impedance of the INA821 is extremely high (approximately 100 GΩ.) However, a path must be
provided for the input bias current of both inputs. This input bias current is typically 150 pA. High input
impedance means that this input bias current changes little with varying input voltage.
For proper operation, Input circuitry must provide a path for this input bias current. 图 68 shows various
provisions for an input bias current path. Without a bias current path, the inputs float to a potential that exceeds
the common-mode range of the INA821 and the input amplifiers saturate. If the differential source resistance is
low, the bias current return path connects to one input (as shown in the thermocouple example in 图 68). With a
higher source impedance, using two equal resistors provides a balanced input with possible advantages of a
lower input offset voltage as a result of bias current and better high-frequency common-mode rejection.
Microphone,
Hydrophone,
and So Forth
TI Device
47 kW
47 kW
Thermocouple
TI Device
10 kW
TI Device
Center tap provides
bias current return.
Copyright © 2017, Texas Instruments Incorporated
图 68. Providing an Input Common-Mode Current Path
28
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9.2 Typical Application
图 69 shows a three-pin programmable-logic controller (PLC) design for the INA821. This PLC reference design
accepts inputs of ±10 V or ±20 mA. The output is a single-ended voltage of 2.5 V ±2.3 V (or 200 mV to 4.8 V).
Typically, PLCs have these input and output ranges.
±10 V
15 V
REF5025
R
= 100 kΩ
= 4.17 kΩ
1
VOUT
GND
VIN
NR
1 ꢀF
1 ꢀF
1 ꢀF
15 V
+VS
R
2
±20 mA
-IN
RG
REF
R
3
=
V
2.5 V ± 2.3 V
INA821
OUT
R
= 10.4 kΩ
OUT
G
20 Ω
RG
+IN
-VS
-15 V
Copyright © 2017, Texas Instruments Incorporated
图 69. PLC Input (±10 V, 4 mA to 20 mA)
9.2.1 Design Requirements
For this application, the design requirements are as follows:
•
•
•
•
•
4-mA to 20-mA input with less than 20-Ω burden
±20-mA input with less than 20-Ω burden
±10-V input with impedance of approximately 100 kΩ
Maximum 4-mA to 20-mA or ±20 mA burden voltage equal to ±0.4 V
Output range within 0 V to 5 V
9.2.2 Detailed Design Procedure
There are two modes of operation for the circuit shown in 图 69: current input and voltage input. This design
requires R1 >> R2 >> R3. Given this relationship, 公式 3 calculates the current input mode transfer function.
VOUT-I = VD ´ G + VREF = -(IIN ´ R3) ´ G + VREF
where
•
•
•
•
G represents the gain of the instrumentation amplifier.
VD represents the differential voltage at the INA821 inputs.
VREF is the voltage at the INA821 REF pin.
IIN is the input current.
(3)
公式 4 shows the transfer function for the voltage input mode.
R2
VOUT-V = VD ´ G + VREF = - VIN
´
´ G + VREF
R1 + R2
where
•
VIN is the input voltage
(4)
29
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Typical Application (接下页)
R1 sets the input impedance of the voltage input mode. The minimum typical input impedance is 100 kΩ. The R1
value is 100 kΩ because increasing the R1 value also increases noise. The value of R3 must be extremely small
compared to R1 and R2. The value of R3 is 20 Ω because that resistance value is smaller than R1 and yields an
input voltage of ±400 mV when operating in current mode (±20 mA).
Use 公式 5 to calculate R2 if VD = ±400 mV, VIN = ±10 V, and R1 = 100 kΩ.
R2
R1 ´ VD
VD = VIN ´
® R2 =
= 4.167 kW
R1 + R2
VIN - VD
(5)
The value obtained from 公式 5 is not a standard 0.1% value, so 4.17 kΩ is selected. R1 and R2 use 0.1%
tolerance resistors to minimize error.
Use 公式 6 to calculate the gain of the instrumentation amplifier.
V
OUT - VREF
V
4.8 V - 2.5 V
G =
=
= 5.75
V
VD
400 mV
(6)
(7)
公式 7 calculates the gain-setting resistor value using the INA821 gain equation (公式 1).
49.4 kW 49.4 kW
RG
=
=
= 10.4 kW
G -1
5.75 -1
Use a standard 0.1% resistor value of 10.5 kΩ for this design.
9.2.3 Application Curves
图 70 and 图 71 show typical characteristic curves for the circuit in 图 69.
C001
5
5
4
4
3
3
2
2
1
1
0
0
-10
-5
0
5
10
-20
-10
0
10
20
Input Voltage (V)
Input Current (mA)
C001
图 70. PLC Output Voltage vs Input Voltage
图 71. PLC Output Voltage vs Input Current
30
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ZHCSIM8C –AUGUST 2018–REVISED JULY 2019
9.3 Other Application Examples
9.3.1 Resistance Temperature Detector Interface
图 72 illustrates a 3-wire interface circuit for resistance temperature detectors (RTDs). The circuit incorporates
analog linearization and has an output voltage range from 0 V to 5 V. The linearization technique employed is
described in Analog linearization of resistance temperature detectors analog application journal. Series and
parallel combinations of standard 1% resistor values are used to achieve less than 0.02°C of error over a 200°C
temperature span.
15 V
REF5050
VOUT
GND
VIN
NR
4.99
kꢀ
4.99
kꢀ
-IN
RG
VOUT
100
kꢀ
0 V at 0°C
5 V at 200°C
25 mV/°C
100 ꢀ
INA821
801 ꢀ
OUT
RG
+IN
Pt100 RTD
100 ꢀ
-15 V
105 kꢀ 1.18 kꢀ
Copyright © 2017, Texas Instruments Incorporated
图 72. A 3-Wire Interface for RTDs With Analog Linearization
5
4.5
4
0.018
0.016
0.014
0.012
0.01
3.5
3
2.5
2
0.008
0.006
0.004
0.002
0
1.5
1
0.5
0
0
50
100
150
200
0
50
100
150
200
Temperature (°C)
Temperature (°C)
C001
图 73. Transfer Function of 3-Wire RTD Interface
图 74. Temperature Error Over Full Temperature Range
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10 Power Supply Recommendations
The nominal performance of the INA821 is specified with a supply voltage of ±15 V and midsupply reference
voltage. The device also operates using power supplies from ±2.25 V (4.5 V) to ±18 V (36 V) and non-midsupply
reference voltages with excellent performance. Parameters that can vary significantly with operating voltage and
reference voltage are shown in the Typical Characteristics section.
11 Layout
11.1 Layout Guidelines
Attention to good layout practices is always recommended. For best operational performance of the device, use
good PCB layout practices, including:
•
Take care to make sure that both input paths are well-matched for source impedance and capacitance to
avoid converting common-mode signals into differential signals. Even slight mismatch in parasitic capacitance
at the gain setting pins can degrade CMRR over frequency. For example, in applications that implement gain
switching using switches or PhotoMOS® relays to change the value of RG, select the component so that the
switch capacitance is as small as possible and most importantly so that capacitance mismatch between the
RG pins is minimized.
•
Noise propagates into analog circuitry through the power pins of the circuit as a whole and of the device.
Bypass capacitors reduce the coupled noise by providing low-impedance power sources local to the analog
circuitry.
–
Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
•
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better than in
parallel with the noisy trace.
•
•
Place the external components as close to the device as possible. As shown in 图 75, keep RG close to the
pins to minimize parasitic capacitance.
Keep the traces as short as possible.
32
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ZHCSIM8C –AUGUST 2018–REVISED JULY 2019
11.2 Layout Example
+V
C2
R2
+IN
-IN
RG
INA821
RG
R3
OUT
R1
C1
-V
+V
Use ground pours for
shielding the input
signal pairs
Place bypass
capacitors as close to
IC as possible
GND
C2
R1
œIN
1
2
3
4
œIN
RG
RG
+IN
+VS
OUT
REF
-VS
8
7
6
5
OUT
R3
Low-impedance
connection for
+IN
R2
reference terminal
GND
C1
REF
-V
Copyright © 2017, Texas Instruments Incorporated
图 75. Example Schematic and Associated PCB Layout
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12 器件和文档支持
12.1 器件支持
12.1.1 开发支持
•
•
基于 SPICE 的模拟仿真程序 - TINA-TI 软件文件夹
用于仪表放大器的共模输入范围计算器
12.2 文档支持
12.2.1 相关文档
请参阅如下相关文档：
•
•
•
德州仪器 (TI)，《仪表放大器的综合误差计算》应用手册
德州仪器 (TI)，《REF50xx 低噪声、极低漂移、精密电压基准》数据表
德州仪器 (TI)，OPAx191 36V、低功耗、精密、CMOS、轨至轨输入/输出、低失调电压、低输入偏置电流运算
放大器 数据表
12.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 商标
E2E is a trademark of Texas Instruments.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
PhotoMOS is a registered trademark of Panasonic Electric Works Europe AG.
All other trademarks are the property of their respective owners.
12.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
34
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
INA821ID
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
VSSOP
VSSOP
SOIC
D
8
8
8
8
8
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
INA821
Samples
Samples
Samples
Samples
Samples
Samples
INA821IDGKR
INA821IDGKT
INA821IDR
DGK
DGK
D
2500 RoHS & Green
250 RoHS & Green
NIPDAUAG | SN
NIPDAUAG | SN
NIPDAU
1X4Q
1X4Q
2500 RoHS & Green
3000 RoHS & Green
INA821
INA821
INA821
INA821IDRGR
INA821IDRGT
SON
DRG
DRG
NIPDAU
SON
250
RoHS & Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Apr-2023
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
INA821IDGKR
INA821IDGKT
INA821IDR
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
8
8
2500
250
330.0
330.0
330.0
330.0
180.0
12.4
12.4
12.4
12.4
12.4
5.3
5.3
6.4
3.3
3.3
3.4
3.4
5.2
3.3
3.3
1.4
1.4
2.1
1.1
1.1
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q2
Q2
2500
3000
250
INA821IDRGR
INA821IDRGT
SON
DRG
DRG
SON
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
INA821IDGKR
INA821IDGKT
INA821IDR
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
8
8
2500
250
366.0
366.0
356.0
367.0
210.0
364.0
364.0
356.0
367.0
185.0
50.0
50.0
35.0
35.0
35.0
2500
3000
250
INA821IDRGR
INA821IDRGT
SON
DRG
DRG
SON
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
SOIC
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
INA821ID
D
8
75
506.6
8
3940
4.32
Pack Materials-Page 3
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DRG0008B
WSON - 0.8 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
3.1
2.9
PIN 1 INDEX AREA
0.8
0.7
C
SEATING PLANE
0.05 C
DIMENSION A
0.05
0.00
OPTION 01
OPTION 02
(0.1)
(0.2)
(DIM A) TYP
OPT 01 SHOWN
EXPOSED
THERMAL PAD
1.45 0.1
4
1
5
2X
1.5
2.4 0.1
8
6X 0.5
0.3
0.2
0.1
0.08
8X
0.6
0.4
PIN 1 ID
(OPTIONAL)
8X
C A B
C
4218886/A 01/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRG0008B
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.45)
SYMM
8X (0.7)
1
8
8X (0.25)
(2.4)
(0.95)
5
6X (0.5)
4
(R0.05) TYP
(0.475)
(
0.2) VIA
(2.7)
TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218886/A 01/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRG0008B
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
METAL
TYP
8X (0.7)
1
8X (0.25)
SYMM
8
(0.635)
6X (0.5)
(1.07)
5
4
(R0.05) TYP
(1.47)
(2.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
82% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218886/A 01/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
相关型号：
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