INA823_V01 [TI]
INA823 Precision, Low-Power, Wide-Supply (2.7-V to 36-V) Instrumentation Amplifier;
| 型号： | INA823_V01 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | INA823 Precision, Low-Power, Wide-Supply (2.7-V to 36-V) Instrumentation Amplifier |
| 文件： | 总40页 (文件大小：3914K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INA823
SBOSA75B – JULY 2021 – REVISED NOVEMBER 2021
INA823 Precision, Low-Power, Wide-Supply (2.7-V to 36-V) Instrumentation Amplifier
1 Features
3 Description
•
•
Input overvoltage protection up to ±60 V
Input voltage extends 150 mV below negative
supply
Low power supply current: 180 µA (typ)
Precision performance:
– Low offset voltage: 20 µV (typ), 100 µV (max)
– Low input bias current: 8nA (max)
– Common-mode rejection:
The INA823 is an integrated instrumentation amplifier
that offers low power consumption and operates
over a wide, single-supply or dual-supply range.
A single external resistor sets any gain from 1
to 10,000. The device provides low input offset
voltage, low offset voltage drift, low input bias
current, and low current noise while remaining
cost-effective. Additional circuitry protects the inputs
against overvoltage up to ±60 V.
•
•
•
•
•
84 dB, G = 1 (min)
104 dB, G = 10 (min)
120 dB, G ≥ 100 (min)
The INA823 is optimized to provide a high common-
mode rejection ratio. At G = 1, the common-mode
rejection ratio exceeds 84 dB across the full input
common-mode range. The INA823 has a wide
common-mode voltage range as low as 150-mV
below negative supply. The device is designed for
low-voltage operation from a 2.7-V single supply, and
dual supplies up to ±18 V. The low power and single
supply operation enable hand-held, battery-operated
systems.
– Power supply rejection: 100 dB, G = 1 (min)
Input voltage noise: 21 nV/√Hz
Bandwidth: 1.9 MHz (G = 1), 60 kHz (G = 100)
Stable with 1-nF capacitive loads
Supply range:
•
•
•
•
– Single-supply: 2.7 V to 36 V
– Dual-supply: ±1.35 V to ±18 V
Specified temperature range: –40°C to +125°C
Packages: 8-pin SOIC and 8-pin VSSOP
•
•
Device Information
PART NUMBER
INA823
PACKAGE(1)
BODY SIZE (NOM)
4.90 mm × 3.91 mm
3.00 mm x 3.00 mm
2 Applications
SOIC (8)
VSSOP (8)
•
•
•
•
•
•
•
•
•
Flow transmitter
Wearable fitness and activity monitor
Infusion pump
Blood glucose monitor
Electrocardiogram (ECG)
Surgical equipment
(1) For all available packages, see the package option
addendum at the end of the data sheet.
Weigh scale
Analog input module
Process analytics (pH, gas, concentration, force
and humidity)
•
Battery test
7
+VS
2
1
IN
RG
Overvoltage
Protection
50 k
+
–
50 k
–
+
50 k
50 k
6
5
OUT
REF
8
3
RG
+IN
–
Overvoltage
Protection
+
50 k
50 k
VS
4
INA823 Simplified Internal Schematic
Typical Distribution of
Input Stage Offset Voltage Drift
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
INA823
www.ti.com
SBOSA75B – JULY 2021 – REVISED NOVEMBER 2021
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings .............................................................. 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................4
7.5 Electrical Characteristics.............................................5
7.6 Typical Characteristics................................................7
8 Detailed Description......................................................19
8.1 Overview...................................................................19
8.2 Functional Block Diagram.........................................19
8.3 Feature Description...................................................20
8.4 Device Functional Modes..........................................22
9 Application and Implementation..................................23
9.1 Application Information............................................. 23
9.2 Typical Applications.................................................. 24
10 Power Supply Recommendations..............................29
11 Layout...........................................................................29
11.1 Layout Guidelines................................................... 29
11.2 Layout Example...................................................... 30
12 Device and Documentation Support..........................31
12.1 Device Support....................................................... 31
12.2 Documentation Support.......................................... 31
12.3 Receiving Notification of Documentation Updates..31
12.4 Support Resources................................................. 31
12.5 Trademarks.............................................................31
12.6 Electrostatic Discharge Caution..............................31
12.7 Glossary..................................................................31
13 Mechanical, Packaging, and Orderable
Information.................................................................... 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (April 2019) to Revision B (November 2021)
Page
•
Changed device from advanced information (preview) to production data (active) ...........................................1
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SBOSA75B – JULY 2021 – REVISED NOVEMBER 2021
5 Device Comparison Table
DEVICE
DESCRIPTION
GAIN EQUATION
RG AT PINS
1-nV/√Hz Noise, 35-µV Offset, 0.4 µV/°C VOS Drift, 28-MHz Bandwidth,
Precision Instrumentation Amplifier
INA849
INA821
INA819
INA826
INA818
INA828
INA333
PGA280
G = 1 + 6 kΩ / RG
2, 3
35-µV Offset, 0.4 µV/°C VOS Drift, 7-nV/√Hz Noise, High-Bandwidth,
Precision Instrumentation Amplifier
G = 1 + 49.4 kΩ / RG
G = 1 + 50 kΩ / RG
G = 1 + 49.4 kΩ / RG
G = 1 + 50 kΩ / RG
G = 1 + 50 kΩ / RG
G = 1 + 100 kΩ / RG
Digital programmable
2, 3
2, 3
2, 3
1, 8
1, 8
1, 8
N/A
35-µV Offset, 0.4 µV/°C VOS Drift, 8-nV/√Hz Noise, Low-Power,
Precision Instrumentation Amplifier
200-μA Supply Current, 3-V to 36-V Supply Instrumentation Amplifier
With Rail-to-Rail Output
35-µV Offset, 0.4 µV/°C VOS Drift, 8-nV/√Hz Noise, Low-Power,
Precision Instrumentation Amplifier
50-µV Offset, 0.5 µV/°C VOS Drift, 7-nV/√Hz Noise, Low-Power,
Precision Instrumentation Amplifier
25-µV VOS, 0.1 µV/°C VOS Drift, 1.8-V to 5-V, RRO, 50-µA IQ, Chopper-
Stabilized INA
1/8 V/V to 128 V/V Programmable Gain Instrumentation Amplifier With
3-V or 5-V Differential Output; Analog Supply up to ±18 V
INA159
G = 0.2 V Differential Amplifier for ±10-V to 3-V and 5-V Conversion
Precision Programmable Gain Op Amp With SPI
G = 0.2 V/V
N/A
N/A
PGA112
Digital programmable
6 Pin Configuration and Functions
RG
–IN
1
2
3
4
8
7
6
5
RG
+VS
OUT
REF
+IN
–VS
Not to scale
Figure 6-1. D (8-Pin SOIC) and DGK (8-Pin VSSOP) Packages, Top View
Table 6-1. Pin Functions
PIN
TYPE
DESCRIPTION
NAME
–IN
NO.
2
Input
Input
Output
Input
—
Negative (inverting) input
Positive (noninverting) input
Output
+IN
3
OUT
REF
RG
6
5
Reference input. This pin must be driven by a low impedance source.
Gain setting pin. Place a gain resistor between pin 1 and pin 8.
Negative supply
1, 8
4
–VS
+VS
Power
Power
7
Positive supply
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SBOSA75B – JULY 2021 – REVISED NOVEMBER 2021
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Dual supply, VS = (+VS) – (–VS)
± 20
40
VS
–VS, +VS pins voltage
V
Single supply, VS = (+VS)
IN pins voltage
(–VS) – 60
(–VS) – 0.5
–10
(+VS) + 60
(+VS) + 0.5
10
V
V
RG, REF, OUT pins voltage
RG pins current
mA
mA
OUT pin current
–50
50
ISC
TA
Output short-circuit current(2)
Operating temperature
Junction temperature
Storage temperature
Continuous
–50
–65
150
175
150
°C
°C
°C
TJ
Tstg
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) Short-circuit to VS / 2.
7.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
V
Single supply, VS = (+VS)
2.7
±1.35
–40
36
±18
125
VS
TA
Supply voltage
Dual supply, VS = (+VS) – (–VS)
Specified temperature
°C
7.4 Thermal Information
INA823
THERMAL METRIC(1)
D (SOIC)
8 PINS
126.7
67.0
DGK (VSSOP)
UNIT
8 PINS
167.5
60.3
88.7
7.9
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
70.1
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
18.6
ψJB
69.4
87.1
n/a
RθJC(bot)
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SBOSA75B – JULY 2021 – REVISED NOVEMBER 2021
7.5 Electrical Characteristics
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VCM = VREF = 0 V, and G = 1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT
20
100
190
1.2
450
850
5
µV
µV/°C
µV
VOSI
Input stage offset voltage(1) (3)
Output stage offset voltage(1) (3)
TA = –40°C to +125°C(2)
0.2
140
VOSO
TA = –40°C to +125°C(2)
VS = ±1.35 V to ±18 V
1
130
µV/°C
G = 1, RTI
100
115
120
120
G = 10, RTI
G = 100, RTI
G = 1000, RTI
148
PSRR Power-supply rejection ratio
dB
148
148
ZIN
Input impedance
12 || 8.5
20
GΩ || pF
MHz
RFI filter, –3-dB frequency
(–VS) – 0.15
(+VS) – 1
±60
VCM
Operating input voltage(4)
Input overvoltage
VS = ±1.35 V to ±18 V
V
V
TA = –40°C to +125°C
See Figure 7-53
TA = –40°C to +125°C(2)
At dc to 60 Hz, RTI, VCM = (V–) –0.15 V to (V+) – 1 V,
G = 1
84
104
120
110
136
149
At dc to 60 Hz, RTI, VCM = (V–) –0.15 V to (V+) – 1 V,
G = 10
CMRR Common-mode rejection ratio
dB
At dc to 60 Hz, RTI, VCM = (V–) –0.15 V to (V+) – 1 V,
G ≥ 100
BIAS CURRENT
1.2
2.4
15
0.4
0.8
4
8
4
nA
pA/°C
nA
IB
Input bias current
Input offset current
TA = –40°C to +125°C
TA = –40°C to +125°C
IOS
pA/°C
NOISE VOLTAGE
Input stage voltage noise
f = 1 kHz, G = 1000, RS = 0 Ω
fB = 0.1 Hz to 10 Hz, G = 1000, RS = 0 Ω
f = 1 kHz, RS = 0 Ω
21
0.4
nV/√Hz
µVPP
density(6)
eNI
Input stage voltage noise(6)
Output stage voltage noise
density(6)
120
nV/√Hz
eNO
Output stage voltage noise(6)
Current noise density
Current noise
fB = 0.1 Hz to 10 Hz, RS = 0 Ω
f = 1 kHz
5
160
5
µVPP
fA/√Hz
pAPP
in
fB = 0.1 Hz to 10 Hz, G = 100
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UNIT
SBOSA75B – JULY 2021 – REVISED NOVEMBER 2021
7.5 Electrical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VCM = VREF = 0 V, and G = 1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
GAIN
Gain equation
1 + (100 kΩ / RG)
V/V
V/V
G
Gain
1
10000
±0.04
±0.2
±0.2
±0.2
±5
G = 1
±0.01
±0.025
±0.025
±0.05
±0.2
±12
G = 10
G = 100
G = 1000
G = 1
GE
Gain error(5)
VO = ±10 V
%
Gain drift(5)
TA = –40°C to +125°C
ppm/°C
ppm
G > 1
±35
G = 1 to 10
2
10
Gain nonlinearity
G > 10
5
G = 1 to 100, RL = 2 kΩ
15
OUTPUT
Output voltage swing
Load capacitance
(–VS) + 0.15
(+VS) – 0.15
V
pF
Ω
Stable operation
1000
See Figure 7-37
±20
ZOUT
ISC
Closed-loop output impedance
Short-circuit current
Continuous to VS / 2
mA
FREQUENCY RESPONSE
G = 1
1.9
350
60
MHz
kHz
G = 10
BW
SR
Bandwidth, –3 dB
Slew rate
G = 100
G = 1000
G = 1, VO = ±10 V
6
0.9
12
V/µs
G = 1 to 10, VSTEP = 10 V
G = 100, VSTEP = 10 V
G = 1000, VSTEP = 10 V
G = 1 to 10, VSTEP = 10 V
G = 100, VSTEP = 10 V
G = 1000, VSTEP = 10 V
To 0.01%
28
260
14
tS
Settling time
µs
To 0.001%
33
290
REFERENCE INPUT
RIN Input impedance
100
kΩ
V
Reference input voltage
Gain to output
(–VS)
(+VS)
0.05
1
V/V
%
Reference gain error
inside the output voltage swing
VIN = 0 V
0.01
POWER SUPPLY
180
250
300
IQ Quiescent current
µA
TA = –40°C to +125°C
(1) Total offset, referred-to-input (RTI): VOS = (VOSI) + (VOSO / G).
(2) Specified by characterization.
(3) Offset drifts are uncorrelated. Input-referred offset drift is calculated using: ΔVOS(RTI) = √[ΔVOSI 2 + (ΔVOSO / G)2].
(4) Input voltage range of the instrumentation amplifier input stage. The input range depends on the common-mode voltage, differential
voltage, gain, and reference voltage. See Typical Characteristic curves for more information.
(5) The values specified for G > 1 do not include the effects of the external gain-setting resistor, RG.
(6) Total RTI voltage noise is equal to: eN(RTI) = √[eNI 2 + (eNO / G)2].
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7.6 Typical Characteristics
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, CL = 0 pF, VCM = VREF = 0 V, and G = 1 (unless otherwise noted)
Table 7-1. Table of Graphs
FIGURE TITLE
FIGURE NUMBER
Typical Distribution Graphs
Typical Distribution of Input Stage Offset Voltage
Typical Distribution of Input Stage Offset Voltage Drift
Typical Distribution of Output Stage Offset Voltage
Typical Distribution of Output Stage Offset Voltage Drift
Typical Distribution of Inverting Input Bias Current
Typical Distribution of Noninverting Input Bias Current
Typical Distribution of Input Offset Current
Typical CMRR Distribution, G = 1
Figure 7-1
Figure 7-2
Figure 7-3
Figure 7-4
Figure 7-5
Figure 7-6
Figure 7-7
Figure 7-8
Figure 7-9
Figure 7-10
Typical CMRR Distribution, G = 10
Typical Gain Error Distribution
vs Temperature Graphs
Input Stage Offset Voltage vs Temperature
Output Stage Offset Voltage vs Temperature
Input Bias Current vs Temperature
Figure 7-11
Figure 7-12
Figure 7-13
Figure 7-14
Figure 7-15
Figure 7-16
Figure 7-17
Figure 7-18
Figure 7-19
Input Offset Current vs Temperature
CMRR vs Temperature, G = 1
CMRR vs Temperature, G = 10
Gain Error vs Temperature, G = 1
Gain Error vs Temperature, G = 100
Supply Current vs Temperature
AC Performance Graphs
Closed-Loop Gain vs Frequency
Figure 7-20
Figure 7-21
Figure 7-22
Figure 7-23
Figure 7-24
Figure 7-25
Figure 7-26
Figure 7-27
Figure 7-28
Figure 7-29
Figure 7-30
Figure 7-31
Figure 7-32
Figure 7-33
Figure 7-34
Figure 7-35
Figure 7-36
Figure 7-37
CMRR vs Frequency (RTI)
CMRR vs Frequency (RTI, 1-kΩ source imbalance)
Positive PSRR vs Frequency (RTI)
Negative PSRR vs Frequency (RTI)
Voltage Noise Spectral Density vs Frequency (RTI)
Current Noise Spectral Density vs Frequency (RTI)
0.1-Hz to 10-Hz RTI Voltage Noise
0.1-Hz to 10-Hz RTI Voltage Noise, G = 1000
Small-Signal Response, G = 1
Small-Signal Response, G = 10
Small-Signal Response, G = 100
Small-Signal Response, G = 1000
Overshoot vs Capacitive Loads
Large-Signal Step Response
Settling Time vs Step Size
Large-Signal Frequency Response
Closed-Loop Output Impedance vs Frequency
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7.6 Typical Characteristics
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, CL = 0 pF, VCM = VREF = 0 V, and G = 1 (unless otherwise noted)
Table 7-1. Table of Graphs (continued)
FIGURE TITLE
FIGURE NUMBER
Input and Output Voltage Graphs
Input Current vs Input Overvoltage
Gain Nonlinearity, G = 1
Figure 7-38
Figure 7-39
Figure 7-40
Figure 7-41
Figure 7-42
Figure 7-43
Figure 7-44
Figure 7-45
Figure 7-46
Figure 7-47
Figure 7-48
Figure 7-49
Figure 7-50
Figure 7-51
Figure 7-52
Figure 7-53
Figure 7-54
Figure 7-55
Figure 7-56
Figure 7-57
Figure 7-58
Gain Nonlinearity, G = 10
Gain Nonlinearity, G = 100
Gain Nonlinearity, G = 1000
Positive Input Bias Current vs Common‑Mode Voltage (VS–
Positive Input Bias Current vs Common‑Mode Voltage (VS+
Negative Input Bias Current vs Common‑Mode Voltage (VS–
)
)
)
Negative Input Bias Current vs Common‑Mode Voltage (VS+
Offset Voltage vs Common-Mode Voltage, VS = 30 V
Offset Voltage vs Common-Mode Voltage, VS = 2.7 V
Positive Output Voltage Swing vs Output Current, VS = 30 V
)
Negative Output Voltage Swing vs Output Current, VS = 30 V
Positive Output Voltage Swing vs Output Current, VS = 2.7 V
Negative Output Voltage Swing vs Output Current, VS = 2.7 V
Input Common-Mode Voltage vs Output Voltage, VS = 2.7 V, G = 1
Input Common-Mode Voltage vs Output Voltage, VS = 2.7 V, G = 1
Input Common-Mode Voltage vs Output Voltage, VS = 5 V, G = 1
Input Common-Mode Voltage vs Output Voltage, VS = 5 V, G = 100
Input Common-Mode Voltage vs Output Voltage, VS = 24 V and VS = 30 V, G = 1
Input Common-Mode Voltage vs Output Voltage, VS = 24 V and VS = 30 V, G = 10
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7.6 Typical Characteristics
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, CL = 0 pF, VCM = VREF = 0 V, and G = 1 (unless otherwise noted)
N = 1225
Mean = 3.63 μV
Std Dev = 18.0 μV
N = 30
Mean = –0.024 μV/ºC Std Dev = 0.177 μV//ºC
Figure 7-1. Typical Distribution of Input Stage Offset Voltage
Figure 7-2. Typical Distribution of Input Stage Offset Voltage
Drift
N = 1225
Mean = 48.0 μV
Std Dev = 92.4 μV
N = 30
Mean = 0.17 μV/ºC Std Dev = 0.795 μV/ºC
Figure 7-3. Typical Distribution of Output Stage Offset Voltage
Figure 7-4. Typical Distribution of Output Stage Offset Voltage
Drift
30
30
20
10
0
20
10
0
-2
-1
0
1
2
3
4
5
-2
-1
0
1
2
3
4
5
Input Bias Current (nA)
Input Bias Current (nA)
N = 1200
Mean = 1.21 nA Std Dev = 0.384 nA
N = 1200
Mean = 1.11 nA Std Dev = 0.368 nA
Figure 7-5. Typical Distribution of Inverting Input Bias Current
Figure 7-6. Typical Distribution of Noninverting Input Bias
Current
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7.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, CL = 0 pF, VCM = VREF = 0 V, and G = 1 (unless otherwise noted)
30
20
10
0
-2
-1
0
1
2
Input Offset Current (nA)
N = 1225
Mean = –0.22 μV/V
Std Dev = 6.95 μV/V
N = 1170
Mean = –0.092 nA
Std Dev = 0.35 nA
Figure 7-8. Typical CMRR Distribution
Figure 7-7. Typical Distribution of Input Offset Current
15
10
5
0
-0.2 -0.15 -0.1 -0.05
0
0.05
0.1
0.15
0.2
Gain Error (%)
Mean = –0.0334 %
G = 10
N = 550
Std. Dev = 0.0433 %
N = 1225
Mean = –0.0599 μV/V Std. Dev = 0.710 μV/V
G = 10
Figure 7-10. Typical Gain Error Distribution
Figure 7-9. Typical CMRR Distribution
100
80
1000
800
60
600
400
40
200
20
0
0
-200
-400
-600
-800
-1000
-20
-40
-60
-80
-100
Mean
+3
-3
Mean
+3
-3
-50
-25
0
25
50
75
100
125
150
-60 -40 -20
0
20
40
60
80 100 120 140
Temperature (ꢀC)
Temperature (ꢀC)
Figure 7-12. Output Stage Offset Voltage vs Temperature
Figure 7-11. Input Stage Offset Voltage vs Temperature
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7.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, CL = 0 pF, VCM = VREF = 0 V, and G = 1 (unless otherwise noted)
4.5
4
2
1.5
1
3.5
3
2.5
2
0.5
0
1.5
1
-0.5
-1
0.5
0
-0.5
-1
-1.5
-2
Mean
+3ꢁ
-3ꢁ
Mean
+3ꢁ
-3ꢁ
-1.5
-2
-2.5
-60 -40 -20
0
20
40
60
80 100 120 140
-60 -40 -20
0
20
40
60
80 100 120 140
Temperature (ꢀC)
Temperature (ꢀC)
Figure 7-13. Input Bias Current vs Temperature
Figure 7-14. Input Offset Current vs Temperature
160
140
130
120
110
100
Unit 1
Unit 2
Unit 3
Unit 4
Unit 5
Unit 1
Unit 2
Unit 3
Unit 4
Unit 5
150
140
130
120
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (ꢀC)
Temperature (ꢀC)
G = 1
G = 10
Figure 7-15. CMRR vs Temperature
Figure 7-16. CMRR vs Temperature
0.03
0.02
0.01
0
0.4
0.3
0.2
0.1
0
-0.01
-0.02
-0.03
-0.04
-0.05
-0.1
-0.2
-0.3
-0.4
Mean
+3ꢁ
-3ꢁ
Mean
+3ꢁ
-3ꢁ
-60 -40 -20
0
20
40
60
80 100 120 140
-60 -40 -20
0
20
40
60
80 100 120 140
Temperature (ꢀC)
Temperature (ꢀC)
G = 1
Average of 120 units
Normalized at +25°C
G = 100
Average of 120 units
Normalized at +25°C
Figure 7-17. Gain Error vs Temperature
Figure 7-18. Gain Error vs Temperature
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7.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, CL = 0 pF, VCM = VREF = 0 V, and G = 1 (unless otherwise noted)
240
230
220
210
200
190
180
170
160
150
140
80
70
60
50
40
30
20
10
0
G = 1
G = 10
G = 100
G = 1000
-10
-20
-30
VS = 2.7 V
VS = 15 V
10
100
1k
10k
100k
1M
-50 -30 -10 10
30
50
70
90 110 130 150
Frequency (Hz)
Temperature (C)
Figure 7-20. Closed-Loop Gain vs Frequency
Figure 7-19. Supply Current vs Temperature
160
140
120
100
80
160
140
120
100
80
G = 1
G = 10
G = 100
G = 1
G = 10
G = 100
G = 1000
60
60
40
40
20
20
0
0
1
10
100
1k
10k
100k
1
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
Figure 7-21. CMRR vs Frequency (RTI)
Figure 7-22. CMRR vs Frequency (RTI, 1-kΩ source imbalance)
160
140
120
100
80
160
140
120
100
80
60
60
40
40
20
0
G = 1
G = 1
G = 10
G = 100
G = 1000
G = 10
G = 100
G = 1000
20
0
100m
1
10
100
1k
10k
100k
1
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
Figure 7-23. Positive PSRR vs Frequency (RTI)
Figure 7-24. Negative PSRR vs Frequency (RTI)
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7.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, CL = 0 pF, VCM = VREF = 0 V, and G = 1 (unless otherwise noted)
1000
100
10
1000
1
G = 1
G = 10
G = 100
G = 1000
0.1
100m
100
100m
1
10
100
1k
10k
100k
1
10
100
1k
10k
Frequency (Hz)
Frequency (Hz)
Figure 7-25. Voltage Noise Spectral Density vs Frequency (RTI)
Figure 7-26. Current Noise Spectral Density vs Frequency (RTI)
Figure 7-27. 0.1-Hz to 10-Hz RTI Voltage Noise
Figure 7-28. 0.1-Hz to 10-Hz RTI Voltage Noise
100
80
100
80
60
60
40
40
20
20
0
0
-20
-40
-60
-80
-100
-20
-40
-60
-80
-100
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10
12
14
16
18
20
Time (ꢀs)
Time (ꢀs)
G = 1
RL = 10 kΩ
CL = 100 pF
G = 10
RL = 10 kΩ
CL = 100 pF
Figure 7-29. Small-Signal Response
Figure 7-30. Small-Signal Response
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7.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, CL = 0 pF, VCM = VREF = 0 V, and G = 1 (unless otherwise noted)
100
80
100
80
60
60
40
40
20
20
0
0
-20
-40
-60
-80
-100
-20
-40
-60
-80
-100
0
10
20
30
40
50
60
70
80
90 100
0
100 200 300 400 500 600 700 800 900 1000
Time (ꢀs)
Time (ꢀs)
G = 100
RL = 10 kΩ
CL = 100 pF
G = 1000
RL = 10 kΩ
CL = 100 pF
Figure 7-31. Small-Signal Response
Figure 7-32. Small-Signal Response
12
9
G = 1
G = 10
G = 100
G = 1000
6
3
0
-3
-6
-9
-12
0
100 200 300 400 500 600 700 800 900 1000
Time (ꢀs)
Figure 7-33. Overshoot vs Capacitive Loads
Figure 7-34. Large-Signal Step Response
39
36
33
30
27
24
21
18
15
12
9
20
18
16
14
12
10
8
0.01%
0.001%
VS = ꢀ15 V
VS = ꢀ2.7 V
6
4
2
0
100
2
4
6
8
10
12
14
16
18
20
1k
10k
100k
1M
Step Size (V)
Frequency (Hz)
Figure 7-35. Settling Time vs Step Size
Figure 7-36. Large-Signal Frequency Response
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7.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, CL = 0 pF, VCM = VREF = 0 V, and G = 1 (unless otherwise noted)
1000
100
10
1
0.1
1
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
VS = ±15 V
Figure 7-38. Input Current vs Input Overvoltage
Figure 7-37. Closed-Loop Output Impedance vs Frequency
2
1.5
1
0.5
0
-0.5
-1
-1.5
G = 1
10 12
-2
-12 -10 -8 -6 -4 -2
Output Voltage (V)
0
2
4
6
8
Figure 7-40. Gain Nonlinearity
Figure 7-39. Gain Nonlinearity
4
3
14
12
10
8
2
6
4
2
1
0
0
-2
-4
-6
-8
-10
-12
-14
-1
-2
-3
-4
G = 1000
8 10 12
G = 100
10 12
-12 -10 -8 -6 -4 -2
0
2
4
6
-12 -10 -8 -6 -4 -2
0
2
4
6
8
Output Voltage (V)
Output Voltage (V)
Figure 7-42. Gain Nonlinearity
Figure 7-41. Gain Nonlinearity
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7.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, CL = 0 pF, VCM = VREF = 0 V, and G = 1 (unless otherwise noted)
0
-10
-20
-30
-40
-50
-60
-70
-80
2
1.5
1
IBP Avg
IBP +3
I
BP −3
VCM Range
0.5
IBP Avg
IBP +3
I
BP −3
VCM Range
0
-16
-15
-14
-13
-12
-11 -10
10
11
12
13
14
15
Common-Mode Voltage (V)
Common-Mode Voltage (V)
Figure 7-43. Positive Input Bias Current vs Common‑Mode
Voltage (VS–
Figure 7-44. Positive Input Bias Current vs Common‑Mode
)
Voltage (VS+)
10
0
2
1.5
1
IBN Avg
IBN +3
I
BN −3
-10
-20
-30
-40
-50
-60
-70
-80
VCM Range
0.5
0
IBN Avg
IBN +3
I
BN −3
VCM Range
-16
-15
-14
-13
-12
-11 -10
10
11
12
13
14
15
Common-Mode Voltage (V)
Common-Mode Voltage (V)
Figure 7-45. Negative Input Bias Current vs Common‑Mode
Voltage (VS–
Figure 7-46. Negative Input Bias Current vs Common‑Mode
Voltage (VS+
)
)
50
40
30
20
10
0
-45ꢁC
-20ꢁC
25ꢁC
85ꢁC
125ꢁC
VCM Range
-10
-20
-16
-12
-8
-4
0
4
8
12
16
Common-Mode Voltage (V)
VS = ±15 V
VS = ±1.35 V
Figure 7-47. Offset Voltage vs Common-Mode Voltage
Figure 7-48. Offset Voltage vs Common-Mode Voltage
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7.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, CL = 0 pF, VCM = VREF = 0 V, and G = 1 (unless otherwise noted)
15
14.9
14.8
14.7
14.6
14.5
14.4
14.3
14.2
14.1
14
-14
-14.1
-14.2
-14.3
-14.4
-14.5
-14.6
-14.7
-14.8
-14.9
-15
-40ꢀC
25ꢀC
85ꢀC
125ꢀC
-40ꢀC
25ꢀC
85ꢀC
125ꢀC
0
0.005
0.01
0.015
0.02
0
0.005
0.01
0.015
0.02
Output Current (A)
Output Current (A)
VS = ±15 V
VS = ±15 V
Figure 7-50. Negative Output Voltage Swing vs Output Current
Figure 7-49. Positive Output Voltage Swing vs Output Current
2.7
2.6
2.5
2.4
2.3
2.2
2.1
-1.7
-40ꢀC
-1.8
25ꢀC
85ꢀC
125ꢀC
-1.9
-2
-2.1
-2.2
-2.3
-2.4
-2.5
-2.6
-2.7
2
-40ꢀC
1.9
25ꢀC
85ꢀC
125ꢀC
1.8
1.7
0
0.005
0.01
0.015
0.02
0.025
0
0.005
0.01
0.015
0.02
0.025
Output Current (A)
Output Current (A)
VS = ±1.35 V
VS = ±1.35 V
Figure 7-51. Positive Output Voltage Swing vs Output Current
Figure 7-52. Negative Output Voltage Swing vs Output Current
1.8
1.6
1.4
1.2
1
2.25
VREF = 0 V
VREF = 1.35 V
2.1
1.95
1.8
1.65
1.5
1.35
1.2
1.05
0.9
0.75
0.6
0.45
0.3
0.15
0
0.8
0.6
0.4
VREF = 0 V
VREF = 1.35 V
0.2
0
0
0.25 0.5 0.75
1
1.25 1.5 1.75
2
2.25 2.5 2.75
0
0.25 0.5 0.75
1
1.25 1.5 1.75
2
2.25 2.5 2.75
Output Voltage (V)
Output Voltage (V)
VS = 2.7 V
G = 100
VS = 2.7 V
G = 1
Figure 7-54. Input Common-Mode Voltage vs Output Voltage
Figure 7-53. Input Common-Mode Voltage vs Output Voltage
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7.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, CL = 0 pF, VCM = VREF = 0 V, and G = 1 (unless otherwise noted)
5
4.5
4
5
4.5
4
VREF = 0 V
VREF = 2.5 V
VREF = 0 V
VREF = 2.5 V
3.5
3
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Output Voltage (V)
Output Voltage (V)
VS = 5 V
G = 1
VS = 5 V
G = 100
Figure 7-55. Input Common-Mode Voltage vs Output Voltage
Figure 7-56. Input Common-Mode Voltage vs Output Voltage
G = 1
G > 10
Figure 7-57. Input Common-Mode Voltage vs Output Voltage
Figure 7-58. Input Common-Mode Voltage vs Output Voltage
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8 Detailed Description
8.1 Overview
The INA823 is a monolithic precision instrumentation amplifier that incorporates a current-feedback input stage
and a four-resistor difference-amplifier output stage. One of the features of an instrumentation amplifier (IA)
is that the gain is set by placing an external resistor across the RG pins, as described in Section 8.3.1. The
three-op-amp IA topology in the INA823 limits the maximum input voltage applied to the input terminal. The
maximum input voltage depends on the common-mode voltage, differential voltage, gain, and the reference
voltage; for more information, see Section 8.3.2. The INA823 also features protection at each input by two
junction field-effect transistors (JFETs) that provide a low series resistance under normal signal conditions,
and preserve excellent noise performance. When excessive voltage is applied, these transistors limit the input
current, as described in Section 8.3.3.
The INA823 is developed for medical-sector applications such as infusion pumps (see Section 9.2.1), and
industrial applications such as programmable logic controllers (see Section 9.2.2)
The schematic in Figure 8-1 shows how the INA823 operates. A differential input voltage is buffered by the input
transistors, Q1 and Q2, and is forced across RG. This causes a signal current through RG, R1, and R2. The output
difference amplifier, A3, removes the common-mode component of the input signal and refers the output signal
to the REF pin. The threshold voltage of Q1 and Q2 (defined as VBE) along with the voltage drop across R1 and
R2 produce output voltages on A1 and A2, respectively, that are approximately 0.8 V less than the input voltages.
V+
V+
Optional RG
(External)
50 kꢀ
A1 Out = VCM + VBE + 0.125 V + VD/2 G
R1
R2
V+
50 kꢀ
50 kꢀ
A2 Out = VCM + VBE + 0.125 V ꢁ VD/2 G
Vꢁ
Vꢁ
50 kꢀ
50 kꢀ
Output Swing Range A1, A2, (V+) ꢁ 0.1 V to (Vꢁ) + 0.1 V
OUT
A3
VO = G (VIN+ ꢁ VINꢁ) + VREF
Linear Input Range A3 = (V+) ꢁ 0.9 V to (Vꢁ) + 0.1 V
V+
Vꢁ
REF
50 kꢀ
V+
V+
Vꢁ
+IN
Q1
Q2
C2
C1
VD/2
Vꢁ
Vꢁ
A1
A2
Overvoltage
Protection
Overvoltage
Protection
IB Cancellation
IB Cancellation
RB
VB
RB
VCM
VD/2
Vꢁ
ꢀ
IN
Figure 8-1. Detailed Schematic
8.2 Functional Block Diagram
External Gain Set
Resistor (Optional)
REF
Input Bias
Current
Cancellation
Current-
Feedback
Input Stage
Overvoltage
Protection
─IN
Difference
Amplifier
OUT
Input Bias
Current
Cancellation
Current-
Feedback
Input Stage
Overvoltage
Protection
+IN
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8.3 Feature Description
8.3.1 Gain-Setting Function
Figure 8-2 shows that the gain of the INA823 is set by a single external resistor (RG) connected between the RG
pins (pins 1 and 8).
+VS
VIN / 2
+VS
IN
Overvoltage
Protection
50 k
+
–
50 k
+
RG
–
+
50 k
50 k
OUT
REF
RG
+
–
RL
VCM
RG
+IN
–
VIN / 2
Overvoltage
Protection
+
50 k
50 k
+
VS
VS
Figure 8-2. Simplified Schematic of the INA823 With Gain and Output Equations
The gain of the INA823 can be calculated with Equation 1:
100 kΩ
G = 1+
(1)
(2)
R
G
The value of the external gain resistor RG is then derived from the gain equation:
100 kΩ
R =
G
G − 1
Table 8-1 lists several commonly used gains and resistor values. The 100-kΩ term in Equation 1 is a result of the
sum of the two internal 50-kΩ feedback resistors. These on-chip resistors are laser-trimmed to accurate absolute
values. The accuracy and temperature coefficients of these resistors are included in the gain accuracy and drift
specifications of the Section 7.5. As shown in Figure 8-2 and explained in more details in Section 11, make sure
to connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground that are placed as
close to the device as possible.
Table 8-1. Commonly Used Gains and Resistor Values
DESIRED GAIN
NEAREST 1% RG (Ω)
CALCULATED GAIN ERROR (%)
1
2
Not connected
100 k
24.9 k
11 k
Not connected
0
5
0.321
0.909
0.602
1.098
0.439
1.091
0.961
0.700
0.200
0.100
10
20
5.23 k
3.09 k
2.05 k
1.58 k
1.02 k
499
33
50
65
100
200
500
1000
200
100
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8.3.1.1 Gain Drift
The stability and temperature drift of the external gain setting resistor (RG) also affects gain. The contribution of
RG to gain accuracy and drift is determined from Equation 2.
The best gain drift of 5 ppm/℃ (maximum) is achieved when the INA823 uses G = 1 V/V without RG connected.
In this case, gain drift is limited by the slight mismatch of the temperature coefficient of the integrated 50-kΩ
resistors in the differential amplifier (A3).
At gains greater than 1 V/V, gain drift increases as a result of the individual drift of the 50-kΩ resistors in the
feedback of A1 and A2 relative to the drift of the external gain resistor (RG.) The low temperature coefficient of
the internal feedback resistors significantly improves the overall temperature stability of applications using gains
greater than 1 V/V over alternate options.
8.3.2 Input Common-Mode Voltage Range
The INA823 linear input voltage range extends from 1 V less than the positive supply to 0.15 V less than the
negative supply, and maintains excellent common-mode rejection throughout this range. The common-mode
range for the most common operating conditions are shown in Figure 8-3. While there are other methods to
calculate the common-mode voltage range, the suggested tool is the Analog Engineers Calculator.
5
4.5
4
5
4.5
4
VREF = 0 V
VREF = 2.5 V
VREF = 0 V
VREF = 2.5 V
3.5
3
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Output Voltage (V)
Output Voltage (V)
VS = 5 V, G = 1
VS = 5 V, G = 100
Figure 8-3. Input Common-Mode Voltage
vs Output Voltage
Figure 8-4. Input Common-Mode Voltage
vs Output Voltage
G = 1, VREF = 0 V
G > 10, VREF = 0 V
Figure 8-5. Input Common-Mode Voltage
vs Output Voltage
Figure 8-6. Input Common-Mode Voltage
vs Output Voltage
A single-supply instrumentation amplifier has special design considerations. To achieve a common-mode
range that extends to single-supply ground, the INA823 employs a current-feedback topology with PNP input
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transistors. The matched PNP transistors, Q1 and Q2, shift the input voltages of both inputs up by a diode drop,
and (through the feedback network) shift the output of A1 and A2 by approximately 0.6 V. The output of A1 and
A2 is well within the linear range when the inputs are within the single-supply ground. When inputs are within the
supply ground, differential measurements can be made at the ground level. As a result of this input level-shifting,
the voltages at pin 1 and pin 8 are not equal to the respective input pin voltages. For most applications, this
inequality is not important because only the gain-setting resistor connects to these pins.
8.3.3 Input Protection
The inputs of the INA823 device are individually protected for voltages up to ±60 V and for short transients up
to ±80 V. For example, a condition of –60 V on one input and +60 V on the other input does not cause damage.
Internal circuitry on each input provides low series impedance under normal signal conditions. If the input is
overloaded, the protection circuitry limits the input current to a value of approximately 4 mA.
+V
ZD1
+VS
IN
Overvoltage
Protection
Input Voltage
Source
+
–
Input Transistor
-VS
ZD2
-V
Figure 8-7. Input Current Path During an Overvoltage Condition
During an input overvoltage condition, current flows through the input protection diodes into the power supplies,
as shown in Figure 8-7. If the power supplies are unable to sink current, then Zener diode clamps (ZD1 and ZD2
in Figure 8-7) must be placed on the power supplies to provide a current pathway to ground. Figure 8-8 shows
the input current for input voltages from –80 V to +80 V when the INA823 is powered by ±15-V supplies.
Figure 8-8. Input Current vs Input Overvoltage
8.4 Device Functional Modes
The INA823 has a single functional mode and is operational when the power supply voltage is greater than 2.7 V
(±1.35 V). The maximum power-supply voltage for the INA823 is 36 V (±18 V).
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
9.1.1 Input Bias Current Return Path
The input impedance of the INA823 is extremely high, but a path must be provided for the input bias current of
both inputs. This input bias current is typically 1.2 nA. High input impedance means that this input bias current
changes little with varying input voltage.
For proper operation, input circuitry must provide a path for this input bias current. Figure 9-1 shows various
provisions for an input bias current path. Without a bias current path, the inputs float to a potential that exceeds
the common-mode range of the INA823, and the input amplifiers saturate. If the differential source resistance
is low, the bias current return path connects to one input (as shown in the thermocouple example in Figure
9-1). With a higher source impedance, use two equal resistors to provide a balanced input, with the possible
advantages of a lower input offset voltage as a result of bias current, and better high-frequency common-mode
rejection. Furthermore, matched input impedances generally minimize the impact to performance in cases where
the input common-mode voltage is very low and input bias current can increase as the IB cancellation circuity
runs out of headroom. The input offset current typically remains low; therefore, well-matched input impedances
reduce the differential error voltage that would otherwise arise.
For more details about why a valid input bias current return path is necessary, see the Importance of Input Bias
Current Return Paths in Instrumentation Amplifier Applications application note.
Microphone,
Hydrophone,
and So Forth
TI Device
47 kW
47 kW
Thermocouple
TI Device
10 kW
TI Device
Center tap provides
bias current return.
Copyright © 2017, Texas Instruments Incorporated
Figure 9-1. Providing an Input Common-Mode Current Path
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9.2 Typical Applications
9.2.1 Resistive-Bridge Pressure Sensor
The INA823 is an integrated instrumentation amplifier that measures small differential voltages while
simultaneously rejecting larger common-mode voltages. The device offers a low power consumption of 250
µA (max) and high precision, thus minimizing errors with voltage offset, offset drift and gain error.
The device is designed for portable applications where sensors measure physical parameters, such as changes
in fluid, pressure, temperature, or humidity. An example of a pressure sensor used in the medical sector is in
portable infusion pumps or dialysis machines.
The pressure sensor is made of a piezo-resistive element that can be derived as a classical 4-resistor
Wheatstone bridge. Occlusion (infusion of fluids, medication, or nutrients) happens only in one direction, and
therefore, can only cause the resistive element (R) to expand. This expansion causes a change in voltage on
one leg of the Wheatstone bridge, which induces a differential voltage VDIFF
.
Figure 9-2 showcases an exemplary circuit for an occlusion pressure sensor application, as required in infusion
pumps. When blockage (occlusion) occurs against a set-point value, the tubing depresses, thus causing the
piezo-resistive element to expand (Node AD: R + ΔR). The signal chain connected to the bridge downstream
processes the pressure change and can trigger an alarm.
VSS = 5 V
VEXT = 2.5 V
1
F
1
F
REF5025
A
0.1
F
D
Pressure
Occlusion
Sensor
B
–
+
VOUT
VDIFF
ADC
µC
RG
INA823
C
VREF
R1
GND
Figure 9-2. Resistive-Bridge Pressure Sensor
Low-tolerance bridge resistors must be used to minimize the offset and gain errors.
Given that there is only a positive differential voltage applied, this circuit is laid out in single-ended supply
mode. The excitation voltage, VEXT, to the bridge must be precise and stable; otherwise, measurement error is
introduced.
The REF5025 is a low-noise, low-drift (3 ppm/C), and high-precision (0.05%) voltage reference that is an
excellent option to generate the excitation voltage VEXT
.
The following subsections give the design requirements and detailed design procedure for an application with a
occlusion pressure sensor.
For more information and design tips to consider when using a resistive-bride pressure sensor, see the Design
tips for a resistive-bridge pressure sensor in industrial process-control systems analog applications journal.
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9.2.1.1 Design Requirements
For this application, the design requirements are as shown in Table 9-1.
Table 9-1. Design Requirements
DESCRIPTION
VALUE
Single supply voltage
VS= 5 V
Excitation voltage
VEXT = 2.5 V
Occlusion pressure range
Occlusion pressure sensitivity
Occlusion pressure impedance (R)
Total pressure sampling rate
Full-scale range of ADC
P = 1...10 psi, increments of p = 0.5 psi
S = 2 ± 0.5 (25%) mV/V/psi
R = 4.99 kΩ ± 50 Ω (0.1%)
Sr = 20 Hz
VADC(fs) = VOUT = 4.5 V
9.2.1.2 Detailed Design Procedure
This section provides basic calculations to lay out the instrumentation amplifier with respect to the given design
requirements.
One of the key considerations in resistive-bridge sensors is the common-mode voltage, VCM. If the bridge is
balanced (no pressure, thus no voltage change), VCM(MAX) is half of the bridge excitation (VEXT). As the pressure
increases to the maximum value, the common-mode voltage decreases to VCM(MIN)
.
To achieve the output voltage of VOUT = 4.5 V with the INA823, the limitation for the common-mode voltage is at
VCM(INA823max) = 1.8 V, as shown in Figure 7-56 and Figure 9-3 (where an initial gain value of 100 V/V is used
as an approximation). An additional series resistor in the Wheatstone bridge string (R1) is required to shift the
common-mode voltage to this value. However, be aware that shifting the common-mode voltage also changes
the effective excitation voltage VEXT across the bridge.
Figure 9-3. Screen Shot From Analog Engineer's Calculator
Calculate the new effective excitation voltage VEXT(NOM) associated with a desired VCM(MIN) value by solving the
following:
V
− V
CM MIN
EXT
1 + S
2.5 − 1.8
V
= 2*
= 2*
= 1.366 V
(3)
EXT NOM
mV
*P
1 + 2.5
*10 psi
MAX MAX
V*psi
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VEXT(NOM) can in turn be used to calculate the desired value of R1:
V
EXT
2.5 V
R = R
− 1 = 4.99 kΩ
− 1 = 4.144 kΩ
1.366 V
(4)
1
V
EXT NOM
Use a standard 0.1% resistor value of 4.12 kΩ.
Calculate the maximum value of VDIFF by solving the following equation for the maximum pressure of 10 psi:
mV
V
= S
*P
*V = 2.5
EXT NOM
*10 psi *1.366 V = 34.15 mV
V*psi
(5)
DIFF
MAX MAX
Use the resulting value to verify that the minimum bridge common-mode voltage, VCM(MIN), is within the limits of
the INA823 by solving the following:
V
DIFF
2
34.15 mV
= 1.817 V
2
V
= V
+
CM MIN
= 1.8 V +
(6)
CM MAX
Next, use Equation 7 to calculate the required gain for the given maximum sensor output voltage span, VDIFF
,
with respect to the required VOUT, which is the full-scale range of the ADC.
V
OUT
4.5 V
G =
=
= 131.77 V/V
34.15 mV
(7)
(8)
V
DIFF(MAX)
Equation 8 calculates the gain-setting resistor value using the INA823 gain equation shown in Equation 2:
100 kΩ
G − 1
100 kΩ
R =
=
= 764.69 Ω
G
V
131.77
− 1
V
Use a standard 0.1% resistor value of 768 Ω, so as not to exceed the full-scale range of the ADC.
9.2.1.3 Application Curves
The following typical characteristic curve is for the circuit in Figure 9-2.
0.05
0.045
0.04
0.035
0.03
0.025
0.02
0.015
0.01
0.005
0
5
VDIFF
VOUT
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
4950
5050
5150
5250
5350
5450
5550
Bridge Resistance R+R ()
Figure 9-4. Input Differential Voltage, Output Voltage vs Bridge Resistance
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9.2.2 Supporting High Common-Mode Voltage in PLC Input Modules
Figure 9-5 showcases a high common-mode voltage circuit that is commonly required for programmable logic
controller (PLC) analog input modules. This circuit uses a resistive scaling network in front of the IA.
Ri
750 k
15 V
+
Rf
249 k
Cf
47 nF
5 V
0.1 μF
VDIFF / 2
+
–
VOUT
RG
33.2 k
ADC
INA823
+
–
+
VCM
VREF
VDIFF / 2
Rf'
249 k
Cf'
47 nF
Ri'
750 k
─ 15 V
0.1 μF
Figure 9-5. High Common-Mode Voltage PLC Input Module
For a detailed description of the passive scaling approach and more, see the Supporting High-Voltage Common
Mode Using Instrumentation Amplifier application brief.
9.2.2.1 Design Requirements
Table 9-2 lists the requirements for this design example.
Table 9-2. Design Parameters
PARAMETER
VALUE
Supply voltage
±15 V
Common-mode voltage
Input differential signal
Gain VOUT/VDIFF
+36 V / –43 V
1 V
1 V/V
Minimum dc CMRR
65 dB
9.2.2.2 Detailed Design Procedure
The gain of the IA is calculated so that the circuit operates at unity gain, where VOUT = VDIFF
.
The single-ended input impedance, Rin(SE), of the circuit is the sum of the scaling resistors (Rf + Ri). To
minimize the error that is caused by the tolerance of the scaling resistors, keep Rin > 1 MΩ.
Ideally, choose the resistors so that Rf / Ri = Rf' / Ri'. In the real world, designers have to trade off between
the mismatch of ratios that degrades the common-mode rejection ratio (CMRR) and the acceptable cost for the
design.
The following text describe how to estimate the CMRR performance of the external resistor scaling approach. In
the calculation of CMRR, the following factors are considered:
•
Take into account the number of resistors, which is estimated by √n, where n is the number of resistors
applied. In this case, this estimation results in a factor of 2.
•
•
ΔR / R is the resistor matching ratio. The resistor tolerance for all four resistors is 0.1%.
Take into account that a normal production distribution of the resistor value with a standard deviation of ±3 σ
(99.7%). In this case, the assumption results in a factor σ = 1/3 = 0.33 into the equation.
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Equation 9 calculates the common-mode rejection ratio with given factors:
G1 + 1
CMRR
=
(9)
dB
dB
ΔR
R
α ∙
∙
n
0.25 +1
0.33∙0.1%∙√4
CMRR
=
= 65.5 dB
(10)
The scaling ratio G1 is calculated by:
R
f
R + R
G1 =
(11)
f
i
where
•
•
Rf is variable
Ri is fixed at 750 kΩ.
Figure 9-6 shows a comparison between the CMRR performance at worst-case (α neglected) and considering
normal distribution for different gain settings of G1.
For more details about the calculation of CMRR, see the Difference amplifier (subtractor) circuit analog
engineer's circuit.
9.2.2.3 Application Curves
Figure 9-6. Common-mode Rejection Ratio of External Resistor Network for Different Scaling Ratios
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10 Power Supply Recommendations
The nominal performance of the INA823 is specified with a supply voltage of ±15 V and midsupply reference
voltage. The device also operates using power supplies from ±1.35 V (2.7 V) to ±18 V (36 V) and non-midsupply
reference voltages with excellent performance. Parameters that can vary significantly with operating voltage and
reference voltage are shown in Section 7.6.
CAUTION
Supply voltages higher than 40 V (±20 V) can permanently damage the device.
11 Layout
11.1 Layout Guidelines
Attention to good layout practices is always recommended. For best operational performance of the device, use
the following PCB layout practices:
•
Make sure that both input paths are well-matched for source impedance and capacitance to avoid converting
common-mode signals into differential signals.
•
Use bypass capacitors to reduce the coupled noise by providing low-impedance power sources local to the
analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
•
Route the input traces as far away from the supply or output traces as possible to reduce parasitic coupling. If
these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better than crossing
in parallel with the noisy trace.
•
•
Place the external components as close to the device as possible.
Use short, symmetric, and wide traces to connect the external gain resistor to minimize capacitance
mismatch between the RG pins.
•
Keep the traces as short as possible.
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11.2 Layout Example
+V
C2
R2
+IN
–IN
RG
INA823
RG
R3
OUT
R1
C1
Ground plane
removed at gain
–V
resistor to minimize
parasitic capacitance
Use ground pours for
shielding the input
signal pairs
R3
+V
GND
GND
R1
C2
1
2
3
4
RG
RG
8
7
6
5
–IN
+IN
–IN
+IN
–VS
+VS
OUT
REF
Input traces routed
adjacent to each other
OUT
R2
Low-impedance
connection for
reference pin
GND
C1
Place bypass
capacitors as close to
IC as possible
–V
Figure 11-1. Example Schematic and Associated PCB Layout
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
•
•
SPICE-based analog simulation program — TINA-TI software folder
Analog Engineer's Calculator
12.1.1.1 PSpice® for TI
PSpice® for TI is a design and simulation environment that helps evaluate performance of analog circuits. Create
subsystem designs and prototype solutions before committing to layout and fabrication, reducing development
cost and time to market.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
•
•
Texas Instruments, Comprehensive Error Calculation for Instrumentation Amplifiers application note
Texas Instruments, Importance of Input Bias Current Return Paths in Instrumentation Amplifier Applications
application note
•
•
Texas Instruments, REF50xx Low-Noise, Very Low Drift, Precision Voltage Reference data sheet
Texas Instruments, OPAx191 36-V, Low Power, Precision, CMOS, Rail-to-Rail Input/Output, Low Offset
Voltage, Low Input Bias Current Op Amp data sheet
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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11-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
INA823DGKR
INA823DGKT
INA823DR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
8
8
8
2500 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Call TI
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
2IVJ
2IVJ
NIPDAU
NIPDAU
NIPDAU
Call TI
INA823
INA823
INA823DT
SOIC
D
250
2500
3000
RoHS & Green
TBD
XINA823DGKR
XINA823DR
VSSOP
SOIC
DGK
D
TBD
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Dec-2021
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Dec-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
INA823DGKR
INA823DGKT
INA823DR
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
8
2500
250
330.0
180.0
330.0
180.0
12.4
12.4
12.4
12.4
5.3
5.3
6.4
6.4
3.4
3.4
5.2
5.2
1.4
1.4
2.1
2.1
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
3000
250
INA823DT
SOIC
D
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Dec-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
INA823DGKR
INA823DGKT
INA823DR
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
8
2500
250
853.0
210.0
853.0
210.0
449.0
185.0
449.0
185.0
35.0
35.0
35.0
35.0
3000
250
INA823DT
SOIC
D
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
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