INA826_13 [TI]
Supply Instrumentation Amplifier;
| 型号： | INA826_13 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Supply Instrumentation Amplifier |
| 文件： | 总39页 (文件大小：1300K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INA826
www.ti.com
SBOS562A –AUGUST 2011–REVISED SEPTEMBER 2011
Precision, 200-µA Supply Current, 2.7-V to 36-V Supply
Instrumentation Amplifier with Rail-to-Rail Output
Check for Samples: INA826
1
FEATURES
DESCRIPTION
The INA826 is a low-cost instrumentation amplifier
234
•
Input Common-Mode Range: Includes V–
that offers extremely low power consumption and
operates over a very wide single or dual supply
range. A single external resistor sets any gain from 1
to 1000. It offers excellent stability over temperature,
even at G > 1, as a result of the low gain drift of only
35 ppm/°C (max).
•
Common-Mode Rejection:
–
–
104 dB, min (G = 10)
100 dB, min at 5 kHz (G = 10)
•
•
•
•
•
•
•
•
•
Power-Supply Rejection: 100 dB, min (G = 1)
Low Offset Voltage: 150 µV, max
Gain Drift: 1 ppm/°C (G = 1), 35 ppm/°C (G > 1)
Noise: 18 nV/√Hz, G ≥ 100
The INA826 is optimized to provide excellent
common-mode rejection ratio of over 100 dB (G = 10)
over frequencies up to 5 kHz. In G = 1, the
common-mode rejection ratio exceeds 84 dB across
the full input common-mode range from the negative
supply all the way up to 1 V of the positive supply.
Using a rail-to-rail output, the INA826 is well-suited
for low voltage operation from a 2.7 V single supply
as well as dual supplies up to ±18 V.
Bandwidth: 1 MHz (G = 1), 60 kHz (G = 100)
Inputs Protected up to ±40 V
Rail-to-Rail Output
Supply Current: 200 µA
Supply Range:
Additional circuitry protects the inputs against
overvoltage of up to ±40 V beyond the power
supplies by limiting the input currents to less than
8 mA.
–
–
Single Supply: +2.7 V to +36 V
Dual Supply: ±1.35 V to ±18 V
•
•
Specified Temperature Range:
–40°C to +125°C
The INA826 is available in SO-8, MSOP-8, and tiny
3-mm × 3-mm DFN-8 surface-mount packages. All
versions are specified for the –40°C to +125°C
temperature range.
Packages: MSOP-8, SO-8 and DFN-8
APPLICATIONS
•
•
•
•
•
•
•
Industrial Process Controls
Circuit Breakers
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G = 0.2 V differential amplifier for ±10-V to 3-V and
5-V conversion
Precision programmable gain op amp with SPI™
interface
+VS
-IN
RG
RG
1
2
3
4
8
7
6
5
VOUT
REF
-VS
+IN
MSOP-8, SO-8
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
4
SPI is a trademark of Motorola.
PhotoMOS is a registered trademark of Panasonic Electric Works Europe AG.
All other trademarks are the property of their respective owners.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
INA826
SBOS562A –AUGUST 2011–REVISED SEPTEMBER 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION(1)
PRODUCT
PACKAGE-LEAD
PACKAGE DESIGNATOR
PACKAGE MARKING
INA826
MSOP-8
SO-8(2)
DFN-8(2)
DGK
D
IPDI
I826
IPEI
INA826
DRG
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
(2) Product preview device.
ABSOLUTE MAXIMUM RATINGS(1)
INA826
±20
UNIT
Supply voltage
V
V
V
Input voltage range
±40
REF input
±20
Output short-circuit(2)
Operating temperature range, TA
Storage temperature range, TA
Junction temperature, TJ
Continuous
–50 to +150
–65 to +150
+175
°C
°C
°C
V
Human body model (HBM)
2500
ESD rating
Charged device model (CDM)
Machine model (MM)
1500
V
150
V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) Short-circuit to VS/2.
2
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INA826
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SBOS562A –AUGUST 2011–REVISED SEPTEMBER 2011
ELECTRICAL CHARACTERISTICS
At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1, unless otherwise noted.
INA826
TYP
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
INPUT
RTI
40
0.4
150
2
µV
µV/°C
µV
VOSI
Input stage offset voltage(1)
vs temperature, TA = –40°C to +125°C
RTI
200
2
700
10
Output stage offset
voltage(1)
VOSO
vs temperature, TA = –40°C to +125°C
G = 1, RTI
µV/°C
dB
100
115
120
120
124
130
140
140
20 || 1
10 || 5
20
G = 10, RTI
dB
PSRR
Power supply rejection
G = 100, RTI
dB
G = 1000, RTI
dB
ZIN
ZIN
Differential impedance
GΩ || pF
GΩ || pF
MHz
V
Common-mode impedance
RFI filter, –3-dB frequency
V–
(V+) – 1
VCM
Operating input range(2)
Input overvoltage range
VS = ±1.35 V to ±18 V, TA = –40°C to +125°C
TA = –40°C to +125°C
See Figure 41 to Figure 44
V
±40
V
G = 1, VCM = (V–) to (V+) – 1 V
G = 10, VCM = (V–) to (V+) – 1 V
84
104
120
120
95
115
130
130
dB
dB
DC to
60 Hz, RTI
G = 100, VCM = (V–) to (V+) – 1 V
G = 1000, VCM = (V–) to (V+) – 1 V
dB
dB
G = 1, VCM = (V–) to (V+) – 1 V,
TA = –40°C to +125°C
CMRR
Common-mode rejection
80
dB
G = 1, VCM = (V–) to (V+) – 1 V
G = 10, VCM = (V–) to (V+) – 1 V
G = 100, VCM = (V–) to (V+) – 1 V
G = 1000, VCM = (V–) to (V+) – 1 V
84
100
105
105
dB
dB
dB
dB
At 5 kHz,
RTI
BIAS CURRENT
VCM = VS/2
35
65
95
5
nA
nA
nA
nA
IB
Input bias current
TA = –40°C to +125°C
VCM = VS/2
0.7
IOS
Input offset current
TA = –40°C to +125°C
10
NOISE VOLTAGE
f = 1 kHz, G = 100, RS = 0 Ω
fB = 0.1 Hz to 10 Hz, G = 100, RS = 0 Ω
f = 1 kHz, G = 1, RS = 0 Ω
fB = 0.1 Hz to 10 Hz, G = 1, RS = 0 Ω
f = 1 kHz
18
0.52
110
3.3
20
nV/√Hz
µVPP
eNI
eNO
iN
Input stage voltage noise(3)
115
nV/√Hz
µVPP
Output stage voltage noise(3)
Noise current
100
5
fA/√Hz
pAPP
fB = 0.1 Hz to 10 Hz
(1) Total offset, referred-to-input (RTI): VOS = (VOSI) + (VOSO/G).
(2) Input voltage range of the INA826 input stage. The input range depends on the common-mode voltage, differential voltage, gain, and
reference voltage. See Typical Characteristic curves Figure 9 through Figure 16 and Figure 41 through Figure 44 for more information.
(3)
2
eNO
2
(eNI
)
+
G
Total RTI voltage noise =
.
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INA826
SBOS562A –AUGUST 2011–REVISED SEPTEMBER 2011
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ELECTRICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1, unless otherwise noted.
INA826
TYP
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
GAIN
G
49.4 kW
Gain equation
Range of gain
1 +
V/V
RG
G
1
1000
±0.015
±0.15
±0.15
±0.15
±1
V/V
%
G = 1, VO = ±10 V
G = 10, VO = ±10 V
±0.003
±0.03
±0.04
±0.04
±0.1
±10
1
%
GE
Gain error
G = 100, VO = ±10 V
%
G = 1000, VO = ±10 V
%
G = 1, TA = –40°C to +125°C
G > 1, TA = –40°C to +125°C
G = 1 to 100, VO = –10 V to +10 V
G = 1000, VO = –10 V to +10 V
ppm/°C
ppm/°C
ppm
ppm
Gain vs temperature(4)
Gain nonlinearity
±35
5
5
20
OUTPUT
Voltage swing
RL = 10 kΩ
(V–) + 0.1
(V+) – 0.15
V
Load capacitance stability
Open loop output impedance
Short-circuit current
1000
See Figure 56
±16
pF
Continuous to VS/2
mA
FREQUENCY RESPONSE
G = 1
1
500
60
6
MHz
kHz
kHz
kHz
V/µs
V/µs
µs
G = 10
BW
SR
tS
Bandwidth, –3 dB
Slew rate
G = 100
G = 1000
G = 1, VO = ±14.5 V
G = 100, VO = ±14.5 V
G = 1, VSTEP = 10 V
G = 10, VSTEP = 10 V
G = 100, VSTEP = 10 V
G = 1000, VSTEP = 10 V
G = 1, VSTEP = 10 V
G = 10, VSTEP = 10 V
G = 100, VSTEP = 10 V
G = 1000, VSTEP = 10 V
1
1
12
12
24
224
14
14
31
278
µs
Settling time to 0.01%
µs
µs
µs
µs
tS
Settling time to 0.001%
µs
µs
(4) The values specified for G > 1 do not include the effects of the external gain-setting resistor, RG.
4
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INA826
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SBOS562A –AUGUST 2011–REVISED SEPTEMBER 2011
ELECTRICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1, unless otherwise noted.
INA826
TYP
PARAMETER
REFERENCE INPUT
TEST CONDITIONS
MIN
MAX
UNIT
RIN
Input impedance
Voltage range
100
kΩ
V
(V–)
(V+)
Gain to output
1
V/V
%
Reference gain error
0.01
POWER SUPPLY
Single
Dual
+2.7
+36
±18
250
300
V
V
VS
IQ
Power-supply voltage
±1.35
VIN = 0 V
200
250
µA
µA
Quiescent current
vs temperature, TA = –40°C to +125°C
TEMPERATURE RANGE
Specified
–40
–50
+125
+150
°C
°C
Operating
THERMAL INFORMATION
INA826
D (SOIC)
8 PINS
141.4
75.4
INA826
INA826
THERMAL METRIC(1)
DGK (MSOP)
8 PINS
215.4
66.3
DRG (DFN)
8 PINS
50.9
UNITS
θJA
Junction-to-ambient thermal resistance
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
60.0
59.6
97.8
25.4
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
27.4
10.5
1.2
ψJB
59.1
96.1
25.5
θJCbot
N/A
N/A
7.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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SBOS562A –AUGUST 2011–REVISED SEPTEMBER 2011
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PIN CONFIGURATIONS
DGK PACKAGE
MSOP-8, SO-8
(TOP VIEW)
DRG PACKAGE
3-mm × 3-mm DFN-8
(TOP VIEW)
+VS
-IN
RG
RG
1
2
3
4
8
7
6
5
+VS
-IN
RG
RG
1
8
7
6
5
VOUT
Exposed
Thermal
Die Pad
on
VOUT
2
3
4
REF
REF
-VS
+IN
Underside
-VS
+IN
(1) SO-8 and DFN-8 packages are product preview.
PIN DESCRIPTIONS
NAME
–IN
NO.
1
DESCRIPTION
Negative input
RG
2
Gain setting pin. Place a gain resistor between pin 2 and pin 3.
RG
3
Gain setting pin. Place a gain resistor between pin 2 and pin 3.
+IN
4
Positive input
–VS
REF
VOUT
+VS
5
Negative supply
6
Reference input. This pin must be driven by low impedance.
7
Output
8
Positive supply
6
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INA826
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SBOS562A –AUGUST 2011–REVISED SEPTEMBER 2011
TYPICAL CHARACTERISTICS
At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1, unless otherwise noted.
TYPICAL DISTRIBUTION OF
INPUT OFFSET VOLTAGE
TYPICAL DISTRIBUTION OF
INPUT OFFSET VOLTAGE DRIFT
1600
1400
1200
1000
800
600
400
200
0
25
20
15
10
5
0
VOSI (µV)
VOSI Drift (µV/°C)
G026
G025
G027
G029
G030
G028
Figure 1.
Figure 2.
TYPICAL DISTRIBUTION OF
OUTPUT OFFSET VOLTAGE
TYPICAL DISTRIBUTION OF
OUTPUT OFFSET VOLTAGE DRIFT
1600
1400
1200
1000
800
600
400
200
0
25
20
15
10
5
0
VOSO Drift (µV/°C)
VOSO (µV)
Figure 3.
Figure 4.
TYPICAL DISTRIBUTION OF
INPUT BIAS CURRENT
TYPICAL DISTRIBUTION OF
INPUT OFFSET CURRENT
2000
1500
1000
500
0
3000
2500
2000
1500
1000
500
0
IB (nA)
IOS (nA)
Figure 5.
Figure 6.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1, unless otherwise noted.
TYPICAL GAIN ERROR DRIFT DISTRIBUTION
(G = 1)
TYPICAL GAIN ERROR DRIFT DISTRIBUTION
(G > 1)
32000
28000
24000
20000
16000
12000
8000
4000
0
16000
14000
12000
10000
8000
6000
4000
2000
0
Wafer Probe Data
Wafer Probe Data
Gain Error Drift (ppm/°C)
Gain Error Drift (ppm/°C)
G052
G051
Figure 7.
Figure 8.
INPUT COMMON-MODE VOLTAGE vs OUTPUT VOLTAGE
INPUT COMMON-MODE VOLTAGE vs OUTPUT VOLTAGE
(Single Supply, VS = +2.7 V, G = 1)
(Single Supply, VS = +2.7 V, G = 100)
3
3
VS = 2.7 V, G = 1
VREF = 0 V
VS = 2.7 V, G = 100
VREF = 0 V
2.5
2
2.5
2
VREF = 1.35 V
VREF = 1.35 V
1.5
1
1.5
1
0.5
0
0.5
0
−0.5
−1
−0.5
−1
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
2.5
3
Output Voltage (V)
Output Voltage (V)
G035
G036
Figure 9.
Figure 10.
INPUT COMMON-MODE VOLTAGE vs OUTPUT VOLTAGE
INPUT COMMON-MODE VOLTAGE vs OUTPUT VOLTAGE
(Single Supply, VS = +5 V, G = 1)
(Single Supply, VS = +5 V, G = 100)
5
5
VS = 5 V, G = 1
VREF = 0 V
VREF = 2.5 V
VS = 5 V, G = 100
VREF = 0 V
VREF = 2.5 V
4.5
4
4.5
4
3.5
3
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
−0.5
−1
−0.5
−1
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Output Voltage (V)
Output Voltage (V)
G034
G037
Figure 11.
Figure 12.
8
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SBOS562A –AUGUST 2011–REVISED SEPTEMBER 2011
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1, unless otherwise noted.
INPUT COMMON-MODE VOLTAGE vs OUTPUT VOLTAGE
INPUT COMMON-MODE VOLTAGE vs OUTPUT VOLTAGE
(Dual Supply, VS = ±5 V)
(Dual Supply, VS = ±3.3 V)
3
5
4
VS = ±3.3 V
VREF= 0 V
VS = ±5 V
VREF= 0 V
G = 1
G = 100
G = 1
G = 100
2
1
3
2
1
0
0
−1
−2
−3
−4
−5
−6
−1
−2
−3
−4
−4
−3
−2
−1
0
1
2
3
4
−6 −5 −4 −3 −2 −1
0
1
2
3
4
5
6
Output Voltage (V)
Output Voltage (V)
G039
G038
Figure 13.
Figure 14.
INPUT COMMON-MODE VOLTAGE vs OUTPUT VOLTAGE
INPUT COMMON-MODE VOLTAGE vs OUTPUT VOLTAGE
(Dual Supply, VS = ±15 V, ±12 V, G = 1)
(Dual Supply, VS = ±15 V, ±12 V, G = 100)
16
16
G = 1, VREF= 0 V
VS= ±15 V
VS= ±12 V
14
12
10
8
G = 100, VREF= 0 V
VS= ±15 V
VS= ±12 V
14
12
10
8
6
6
4
4
2
2
0
0
−2
−4
−6
−8
−10
−12
−14
−16
−2
−4
−6
−8
−10
−12
−14
−16
−16−14−12−10 −8 −6 −4 −2
0
2
4
6
8
10 12 14 16
−16−14−12−10 −8 −6 −4 −2
0
2
4
6
8
10 12 14 16
Output Voltage (V)
Output Voltage (V)
G040
G040
Figure 15.
Figure 16.
INPUT OVERVOLTAGE vs INPUT CURRENT
WITH 10-kΩ RESISTANCE
INPUT OVERVOLTAGE vs INPUT CURRENT
(G = 1, VS = ±15 V)
(G = 1, VS = ±15 V)
12m
9m
16
8m
6m
16
RS = 10k Ω
12
8
12
8
6m
4m
3m
4
2m
4
0
0
0
0
−3m
−6m
−9m
−12m
−4
−8
−12
−16
−2m
−4m
−6m
−8m
−4
−8
−12
−16
IIN
VOUT
IIN
VOUT
RS = 0 Ω
−40−35−30−25−20−15−10 −5
0
5
10 15 20 25 30 35 40
−40−35−30−25−20−15−10 −5
0
5
10 15 20 25 30 35 40
Input Voltage (V)
Input Voltage (V)
G065
G064
Figure 17.
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1, unless otherwise noted.
CMRR vs FREQUENCY
CMRR vs FREQUENCY
(RTI, 1-kΩ Source Imbalance)
(RTI)
160
140
120
100
80
140
120
100
80
60
60
40
G = 1
G = 1
G = 10
G = 100
G = 1000
40
G = 10
G = 100
G = 1000
20
20
0
0
10
100
1k
10k
100k
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
G001
G002
Figure 19.
Figure 20.
POSITIVE PSRR vs FREQUENCY (RTI)
NEGATIVE PSRR vs FREQUENCY (RTI)
160
140
120
100
80
160
140
120
100
80
60
60
G = 1
G = 1
40
40
G = 10
G = 100
G = 1000
G = 10
G = 100
G = 1000
20
20
0
0
10
100
1k
10k
100k
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
G003
G004
Figure 21.
Figure 22.
VOLTAGE NOISE SPECTRAL DENSITY
vs FREQUENCY (RTI)
GAIN vs FREQUENCY
70
60
1k
100
10
G = 1
G = 10
G = 100
G = 1
G = 10
G = 100
G = 1000
50
G = 1000
40
30
20
10
0
−10
−20
−30
10
100
1k
10k
100k
1M
10M
1
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
G005
G019
Figure 23.
Figure 24.
10
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SBOS562A –AUGUST 2011–REVISED SEPTEMBER 2011
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1, unless otherwise noted.
CURRENT NOISE SPECTRAL DENSITY vs FREQUENCY
(RTI)
0.1-Hz TO 10-Hz RTI VOLTAGE NOISE (G = 1)
1k
100
10
3
2
1
0
−1
−2
−3
1
10
100
1k
10k
0
1
2
3
4
5
6
7
8
9
10
Time (s/div)
Frequency (Hz)
G020
G007
Figure 25.
Figure 26.
0.1-Hz TO 10-Hz RTI VOLTAGE NOISE (G = 1000)
0.1-Hz TO 10-Hz RTI CURRENT NOISE
400
15
10
5
300
200
100
0
0
−100
−200
−300
−400
−5
−10
−15
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
Time (s/div)
Time (s/div)
G006
G008
Figure 27.
Figure 28.
INPUT BIAS CURRENT vs COMMON-MODE VOLTAGE
(VS = +2.7 V)
INPUT BIAS CURRENT vs COMMON-MODE VOLTAGE
(VS = ±15 V)
0
0
−40°C
+25°C
+125°C
−40°C
+25°C
+125°C
−10
−20
−30
−40
−50
−60
−70
−80
−10
−20
−30
−40
−50
−60
−70
−80
−1
−0.5
0
0.5
1
1.5
2
2.5
3
−16
−12
−8
−4
0
4
8
12
16
Common Mode Voltage (V)
Common Mode Voltage (V)
G056
G055
Figure 29.
Figure 30.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1, unless otherwise noted.
INPUT BIAS CURRENT vs TEMPERATURE
INPUT OFFSET CURRENT vs TEMPERATURE
100
90
80
70
60
50
40
30
20
10
0
10
8
Representative Data
Max Data
Min Data
Unit 1
Unit 2
Unit 3
6
4
2
0
−2
−4
−6
−8
−10
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
100
125
150
Temperature (°C)
Temperature (°C)
G033
G053
Figure 31.
Figure 32.
GAIN ERROR vs TEMPERATURE
(G = 1)
GAIN ERROR vs TEMPERATURE
(G > 1)
40
30
2000
1500
1000
500
20
10
0
−10
−20
−30
−40
−50
−60
0
−500
−1000
−1500
−2000
Representative Data
Normalized at +25°C
Representative Data
Normalized at +25°C
−50
−25 25
0
50
75
100
125
150
−50
−25 25
0
50
75
100
125
150
Temperature (°C)
Temperature (°C)
G031
G054
Figure 33.
Figure 34.
CMRR vs TEMPERATURE (G = 1)
SUPPLY CURRENT vs TEMPERATURE
10
8
300
250
200
150
100
50
VS = 2.7 V
VS = ±15 V
6
4
2
0
−2
−4
−6
−8
−10
Representative Data
Normalized at +25°C
0
−50
−50
−25 25
0
50
75
100
125
150
−25
0
25
50
75
100
125
150
Temperature (°C)
Temperature (°C)
G032
G043
Figure 35.
Figure 36.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1, unless otherwise noted.
GAIN NONLINEARITY (G = 1)
GAIN NONLINEARITY (G = 10)
4
3
2
1
0
4
3
2
1
0
−10 −8
−6
−4
−2
0
2
4
6
8
10
−10 −8
−6
−4
−2
0
2
4
6
8
10
Output Voltage (V)
Output Voltage (V)
G021
G022
Figure 37.
Figure 38.
GAIN NONLINEARITY (G = 100)
GAIN NONLINEARITY (G = 1000)
−10
−11
−12
−13
−14
−15
−16
−17
−18
−19
−20
0
−2
−4
−6
−8
−10
−12
−14
−16
−18
−20
−10 −8
−6
−4
−2
0
2
4
6
8
10
−10 −8
−6
−4
−2
0
2
4
6
8
10
Output Voltage (V)
Output Voltage (V)
G023
G024
Figure 39.
Figure 40.
OFFSET VOLTAGE vs
OFFSET VOLTAGE vs
NEGATIVE COMMON-MODE VOLTAGE
POSITIVE COMMON-MODE VOLTAGE
(VS = ±15 V)
(VS = ±15 V)
400
350
300
250
200
150
100
50
100
50
VS = ±15 V
VS = ±15 V
−50°C
−40°C
+25°C
+85°C
+125°C
+150°C
0
−50
−100
−150
−200
−250
−300
−350
−400
−50°C
−40°C
+25°C
+85°C
+125°C
+150°C
0
−50
−100
−15.5
−15.3
−15.1
−14.9
−14.7
−14.5
13.8
13.9
14
14.1
14.2
14.3
14.4
Common Mode Voltage (V)
Common Mode Voltage (V)
G057
G058
Figure 41.
Figure 42.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1, unless otherwise noted.
OFFSET VOLTAGE vs
OFFSET VOLTAGE vs
NEGATIVE COMMON-MODE VOLTAGE
(VS = +2.7 V)
POSITIVE COMMON-MODE VOLTAGE
(VS = +2.7 V)
300
250
200
150
100
50
200
150
100
50
VS = 2.7 V
VS = 2.7 V
−50°C
−40°C
+25°C
+85°C
+125°C
+150°C
−50°C
−40°C
+25°C
+85°C
+125°C
+150°C
0
−50
−100
−150
−200
0
−50
−100
−0.5 −0.4 −0.3 −0.2 −0.1
0
0.1 0.2 0.3 0.4 0.5
1
0
0
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
Common Mode Voltage (V)
Common Mode Voltage (V)
G059
G060
Figure 43.
Figure 44.
POSITIVE OUTPUT VOLTAGE SWING
vs OUTPUT CURRENT (VS = ±15 V)
NEGATIVE OUTPUT VOLTAGE SWING
vs OUTPUT CURRENT (VS = ±15 V)
15
14.8
14.6
14.4
14.2
14
−14
−14.2
−14.4
−14.6
−14.8
−15
−50°C
−40°C
+25°C
+85°C
+125°C
+150°C
−50°C
−40°C
+25°C
+85°C
+125°C
+150°C
0
2
4
6
8
10
12
14
16
2
4
6
8
10
12
14
16
Output Current (mA)
Output Current (mA)
G045
G046
Figure 45.
Figure 46.
POSITIVE OUTPUT VOLTAGE SWING
vs OUTPUT CURRENT (VS = 2.7 V)
NEGATIVE OUTPUT VOLTAGE SWING
vs OUTPUT CURRENT (VS = 2.7 V)
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
25°C
25°C
1.9
1.8
1.7
VS = 2.7 V
14 16
VS = 2.7 V
14 16
0
2
4
6
8
10
12
2
4
6
8
10
12
Output Current (mA)
Output Current (mA)
G048
G049
Figure 47.
Figure 48.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1, unless otherwise noted.
SETTLING TIME vs STEP SIZE
(VS = ±15-V)
LARGE-SIGNAL FREQUENCY RESPONSE
30
27
24
21
18
15
12
9
25
21
17
13
9
VS = ±15 V
VS = +5 V
0.01%
0.001%
6
3
0
5
1k
10k
100k
1M
2
0
0
4
6
8
10
12
14
16
18
20
Step Size (V)
Frequency (Hz)
G014
G061
Figure 49.
Figure 50.
SMALL-SIGNAL RESPONSE OVER
CAPACITIVE LOADS (G = 1)
SMALL-SIGNAL RESPONSE
(G = 1, RL = 1 kΩ, CL = 100 pF)
100
80
100
80
60
60
40
40
0 pF
100 pF
220 pF
500 pF
1 nF
20
20
0
0
−20
−40
−60
−80
−100
−20
−40
−60
−80
−100
0
8
16
24
32
40
48
5
10
15
20
25
30
35
40
time (us)
Time (ps)
G013
G009
Figure 51.
Figure 52.
SMALL-SIGNAL RESPONSE
(G = 10, RL = 10 kΩ, CL = 100 pF)
SMALL-SIGNAL RESPONSE
(G = 100, RL = 10 kΩ, CL = 100 pF)
100
80
100
80
60
60
40
40
20
20
0
0
−20
−40
−60
−80
−100
−20
−40
−60
−80
−100
0
5
10
15
20
time (us)
25
30
35
40
20
40
60
80 100 120 140 160 180 200
time (us)
G010
G011
Figure 53.
Figure 54.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1, unless otherwise noted.
SMALL-SIGNAL RESPONSE
(G = 1000, RL = 10 kΩ, CL = 100 pF)
OPEN-LOOP OUTPUT IMPEDANCE
100
80
100k
10k
1k
60
40
20
0
−20
−40
−60
−80
−100
100
0
100 200 300 400 500 600 700 800 900 1000
1
10
100
1k
10k
100k
1M
10M
time (us)
Frequency (Hz)
G012
G062
Figure 55.
Figure 56.
CHANGE IN INPUT OFFSET VOLTAGE vs WARM-UP TIME
15
10
5
0
−5
−10
−15
0
2
4
6
8
10
12
14
16
Warm−up Time (s)
G063
Figure 57.
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SBOS562A –AUGUST 2011–REVISED SEPTEMBER 2011
APPLICATION INFORMATION
Figure 58 shows the basic connections required for operation of the INA826. Good layout practice mandates the
use of bypass capacitors placed as close to the device pins as possible.
The output of the INA826 is referred to the output reference (REF) terminal, which is normally grounded. This
connection must be low-impedance to assure good common-mode rejection. Although 5 Ω or less of stray
resistance can be tolerated while maintaining specified CMRR, small stray resistances of tens of ohms in series
with the REF pin can cause noticeable degradation in CMRR.
V+
0.1 mF
8
(1)
RS
1
RFI Filter
-IN
50 kW
50 kW
A1
VO = G ´ (VIN+ - VIN-
)
2
49.4 kW
24.7 kW
G = 1 +
RG
7
6
RG
A3
24.7 kW
+
3
4
VO
Load
-
50 kW
50 kW
(1)
RS
A2
REF
RFI Filter
+IN
Device
5
0.1 mF
V-
Also drawn in simplified form:
-IN
RG
VO
Device
REF
+IN
(1) This resistor is optional if the input voltage stays above [(V–) – 2 V] or the signal source current drive capability is limited to less than 3.5
mA. See the Input Protection section for more details.
Figure 58. Basic Connections
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SETTING THE GAIN
Gain of the INA826 is set by a single external resistor, RG, connected between pins 2 and 3. The value of RG is
selected according to Equation 1:
49.4 kW
G = 1 +
RG
(1)
Table 1 lists several commonly-used gains and resistor values. The 49.4-kΩ term in Equation 1 comes from the
sum of the two internal 24.7-kΩ feedback resistors. These on-chip resistors are laser-trimmed to accurate
absolute values. The accuracy and temperature coefficients of these resistors are included in the gain accuracy
and drift specifications of the INA826.
Table 1. Commonly-Used Gains and Resistor Values
DESIRED GAIN (V/V)
RG (Ω)
—
NEAREST 1% RG (Ω)
1
2
—
49.4k
12.35k
5.489k
2.600k
1.008k
499
49.9k
12.4k
5.49k
2.61k
1k
5
10
20
50
100
200
500
1000
499
248
249
99
100
49.5
49.9
Gain Drift
The stability and temperature drift of the external gain setting resistor, RG, also affects gain. The contribution of
RG to gain accuracy and drift can be directly inferred from the gain of Equation 1.
The best gain drift of 1 ppm/℃ can be achieved when the INA826 uses G = 1 without RG connected. In this case,
the gain drift is limited only by the slight mismatch of the temperature coefficient of the integrated 50-kΩ resistors
in the differential amplifier (A3). At G greater than 1, the gain drift increases as a result of the individual drift of the
24.7-kΩ resistors in the feedback of A1 and A2, relative to the drift of the external gain resistor RG. Process
improvements of the temperature coefficient of the feedback resistors now make it possible to specify a
maximum gain drift of the feedback resistors of 35 ppm/℃, thus significantly improving the overall temperature
stability of applications using gains greater than 1.
Low resistor values required for high gain can make wiring resistance important. Sockets add to the wiring
resistance and contribute additional gain error (such as a possible unstable gain error) at gains of approximately
100 or greater. To ensure stability, avoid parasitic capacitance of more than a few picofarads at RG connections.
Careful matching of any parasitics on both RG pins maintains optimal CMRR over frequency; see Typical
Characteristics curves (Figure 19 and Figure 20).
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SBOS562A –AUGUST 2011–REVISED SEPTEMBER 2011
OFFSET TRIMMING
Most applications require no external offset adjustment; however, if necessary, adjustments can be made by
applying a voltage to the REF terminal. Figure 59 shows an optional circuit for trimming the output offset voltage.
The voltage applied to the REF terminal is summed at the output. The op amp buffer provides low impedance at
the REF terminal to preserve good common-mode rejection.
mIN-
m+
RG
mO
INA826
REF
100 mA
1/2 REF200
mIN+
100 W
OPA333
10 ꢀm
Adjustꢀent Range
10 kW
100 W
100 mA
1/2 REF200
m-
Figure 59. Optional Trimming of Output Offset Voltage
INPUT COMMON-MODE RANGE
The linear input voltage range of the INA826 input circuitry extends from the negative supply voltage to 1 V
below the positive supply, while maintaining 84-dB (minimum) common-mode rejection throughout this range.
The common-mode range for most common operating conditions is described in the typical characteristic curves
(Input Common-Mode Voltage vs Output Voltage, Figure 9 through Figure 16) and Offset Voltage vs
Common-Mode Voltage (Figure 41 through Figure 44). The INA826 can operate over a wide range of power
supplies and VREF configurations, making it impractical to provide a comprehensive guide to common-mode
range limits for all possible conditions.
The most commonly overlooked overload condition occurs when a circuit exceeds the output swing of A1 and A2,
which are internal circuit nodes that cannot be measured. Calculating the expected voltages at the output of A1
and A2 (see Figure 60) provides a check for the most common overload conditions. The designs of A1 and A2 are
identical and the outputs can swing to within approximately 100 mV of the power-supply rails. For example, when
the A2 output is saturated, A1 may continue to be in linear operation, responding to changes in the noninverting
input voltage. This difference may give the appearance of linear operation but the output voltage is invalid.
A single-supply instrumentation amplifier has special design considerations. To achieve a common-mode range
that extends to single-supply ground, the INA826 employs a current-feedback topology with PNP input
transistors; see Figure 60. The matched PNP transistors Q1 and Q2 shift the input voltages of both inputs up by a
diode drop, and through the feedback network, shift the output of A1 and A2 by approximately +0.8 V. With both
inputs and VREF at single-supply ground (negative power supply), the output of A1 and A2 is well within the linear
range, allowing users to make differential measurements at the GND level. As a result of this input level-shifting,
the voltages at pin 2 and pin 3 are not equal to the respective input terminal voltages (pin 1 and pin 4). For most
applications, this inequality is not important because only the gain-setting resistor connects to these pins.
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INSIDE THE INA826
See Figure 58 for a simplified representation of the INA826. A more detailed diagram (shown in Figure 60)
provides additional insight into the INA826 operation.
Each input is protected by two field-effect transistors (FETs) that provide a low series resistance under normal
signal conditions, and preserve excellent noise performance. When excessive voltage is applied, these
transistors limit input current to approximately 8 mA.
The differential input voltage is buffered by Q1 and Q2 and is impressed across RG, causing a signal current to
flow through RG, R1, and R2. The output difference amp, A3, removes the common-mode component of the input
signal and refers the output signal to the REF terminal.
The equations shown in Figure 60 describe the output voltages of A1 and A2. The VBE and voltage drop across
R1 and R2 produce output voltages on A1 and A2 that are approximately 0.8 V higher than the input voltages.
V+
V+
RG
(External)
50 kW
R1
R2
A1 Out = VCM + VBE + 0.125 V - VD/2 ´ G
V+
24.7 kW
24.7 kW
V-
V-
A2 Out = VCM + VBE + 0.125 V + VD/2 ´ G
50 kW
50 kW
Output Swing Range A1, A2, (V+) - 0.1 V to (V-) + 0.1 V
VOUT
A3
V+
VO = G ´ (VIN+ - VIN-) + VREF
V-
50 kW
Linear Input Range A3 = (V+) - 0.9 V to (V-) + 0.1 V
REF
V-
V+
V+
-IN
Q1
Q2
C1
C2
VD/2
V-
V-
A1
A2
Overvoltage
Protection
Overvoltage
Protection
RB
VB
RB
VCM
VD/2
V-
+IN
Figure 60. INA826 Simplified Circuit Diagram
INPUT PROTECTION
The inputs of the INA826 are individually protected for voltages up to ±40 V. For example, a condition of –40 V
on one input and +40 V on the other input does not cause damage. However, if the input voltage exceeds (V–) –
2 V and the signal source current drive capability exceeds 3.5 mA, the output voltage switches to the opposite
polarity; see typical characteristic curve Input Overvoltage vs Input Current (Figure 17). This polarity reversal can
easily be avoided by adding resistance of 10 kΩ in series with both inputs.
Internal circuitry on each input provides low series impedance under normal signal conditions. If the input is
overloaded, the protection circuitry limits the input current to a safe value of approximately 8 mA. The typical
characteristic curves Input Current vs Input Overvoltage (Figure 17 and Figure 18) illustrate this input current limit
behavior. The inputs are protected even if the power supplies are disconnected or turned off.
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INPUT BIAS CURRENT RETURN PATH
The input impedance of the INA826 is extremely high—approximately 20 GΩ. However, a path must be provided
for the input bias current of both inputs. This input bias current is typically 35 nA. High input impedance means
that this input bias current changes very little with varying input voltage.
Input circuitry must provide a path for this input bias current for proper operation. Figure 61 shows various
provisions for an input bias current path. Without a bias current path, the inputs float to a potential that exceeds
the common-mode range of the INA826, and the input amplifiers saturate. If the differential source resistance is
low, the bias current return path can be connected to one input (as shown in the thermocouple example in
Figure 61). With higher source impedance, using two equal resistors provides a balanced input with possible
advantages of lower input offset voltage as a result of bias current and better high-frequency common-mode
rejection.
Microphone,
Hydrophone,
etc.
Device
47 kW
47 kW
Thermocouple
Device
10 kW
Device
Center tap provides
bias current return.
Figure 61. Providing an Input Common-Mode Current Path
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REFERENCE TERMINAL
The output voltage of the INA826 is developed with respect to the voltage on the reference terminal. Often, in
dual-supply operation, the reference pin (pin 6) is connected to the low-impedance system ground. In
single-supply operation, it can be useful to offset the output signal to a precise mid-supply level (for example,
2.5 V in a 5-V supply environment). To accomplish this, a voltage source can be tied to the REF pin to level-shift
the output so that the INA826 can drive a single-supply ADC, for example.
For the best performance, source impedance to the REF terminal should be kept below 5 Ω. As can be seen in
Figure 58, the reference resistor is at one end of a 50-kΩ resistor. Additional impedance at the REF pin adds to
this 50-kΩ resistor. The imbalance in the resistor ratios results in degraded common-mode rejection ratio
(CMRR).
Figure 62 shows two different methods of driving the reference pin with low impedance. The OPA330 is a
low-power, chopper-stabilized amplifier, and therefore offers excellent stability over temperature. It is available in
the space-saving SC70 and even smaller chip-scale package. The REF3225 is a precision reference in the small
SOT23-6 package.
+5 V
VIN-
+5 V
RG
VOUT
INA826
VIN-
REF
VIN+
RG
VOUT
INA826
+5 V
REF
+5 V
VIN+
+2.5 V
OPA330
REF3225
+5 V
a) Level shifting using the OPA330 as a low-impedance buffer
b) Level shifting using the low-impedance output of the REF3225
Figure 62. Options for Low-Impedance Level Shifting
DYNAMIC PERFORMANCE
The typical characteristic curve Gain vs Frequency (Figure 23) illustrates that, despite its low quiescent current of
only 200 µA, the INA826 achieves much wider bandwidth than other INAs in its class. This achievement is a
result of using TI’s proprietary high-speed precision bipolar process technology. The current-feedback topology
provides the INA826 with wide bandwidth even at high gains. Settling time also remains excellent at high gain
because of a high slew rate of 1 V/µs.
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OPERATING VOLTAGE
The INA826 operates over a power-supply range of +2.7 V to +36 V (±1.35 V to ±18 V). Supply voltages higher
than 40 V (±20 V) can permanently damage the device. Parameters that vary over supply voltage or temperature
are shown in the Typical Characteristics section of this data sheet.
Low-Voltage Operation
The INA826 can operate on power supplies as low as ±1.35 V. Most parameters vary only slightly throughout this
supply voltage range; see the Typical Characteristics section. Operation at very low supply voltage requires
careful attention to assure that the input voltages remain within the linear range. Voltage swing requirements of
internal nodes limit the input common-mode range with low power-supply voltage. The typical characteristic
curves Typical Common-Mode Range vs Output Voltage (Figure 9 to Figure 16) and Offset Voltage vs
Common-Mode Voltage (Figure 41 to Figure 44) describe the range of linear operation for various supply
voltages, reference connections, and gains.
ERROR SOURCES
Most modern signal conditioning systems calibrate errors at room temperature. However, calibration of errors
that result from a change in temperature is normally difficult and costly. Therefore, it is important to minimize
these errors by choosing high-precision components such as the INA826 that have improved specifications in
critical areas that impact the precision of the overall system. Figure 63 shows an example application.
+15 V
RS+ = 10 kW
VDIFF = 1 V
VOUT
5.49 kW
Device
REF
RS- = 9.9 kW
Signal Bandwidth: 5 kHz
VCM = 10 V
-15 V
Figure 63. Example Application with G = 10 V/V and 1-V Differential Voltage
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Resistor-adjustable INAs such as the INA826 show the lowest gain error in G = 1 because of the inherently
well-matched drift of the internal resistors of the differential amplifier. At gains greater than 1 (for instance, G =
10 V/V or G = 100 V/V) the gain error becomes a significant error source because of the contribution of the
resistor drift of the 24.7-kΩ feedback resistors in conjunction with the external gain resistor. Except for very high
gain applications, the gain drift is by far the largest error contributor compared to other drift errors, such as offset
drift. The INA826 offers the lowest gain error over temperature in the marketplace for both G > 1 and G = 1 (no
external gain resistor). Table 2 summarizes the major error sources in common INA applications and compares
the two cases of G = 1 (no external resistor) and G = 10 (5.49-kΩ external resistor). As can be seen in Table 2,
while the static errors (absolute accuracy errors) in G = 1 are almost twice as great as compared to G = 10, there
are much fewer drift errors because of the much lower gain error drift. In most applications, these static errors
can readily be removed during calibration in production. All calculations refer the error to the input for easy
comparison and system evaluation.
Table 2. Error Calculation
INA826
G = 10 ERROR
(ppm)
G = 1 ERROR
(ppm)
SPEC
ERROR SOURCE
ABSOLUTE ACCURACY AT +25°C
Input offset voltage (μV)
ERROR CALCULATION
VOSI/VDIFF
VOSO/(G × VDIFF
OS × maximum (RS+, RS–)/VDIFF
150
700
5
150
70
150
700
50
Output offset voltage (μV)
)
Input offset current (nA)
I
50
104 (G = 10),
84 (G = 1)
VCM/(10CMRR/20 × VDIFF
)
CMRR (dB)
63
631
Total absolute accuracy error (ppm)
333
1531
DRIFT TO +105°C
35 (G = 10),
1 (G = 1)
Gain drift (ppm/°C)
GTC × (TA – 25)
2800
80
Input offset voltage drift (μV/°C)
Output offset voltage drift (μV/°C)
(VOSI_TC/VDIFF) × (TA – 25)
2
160
80
160
800
[VOSO_TC/( G × VDIFF)] × (TA – 25)
10
I
OS_TC × maximum (RS+, RS–) ×
Offset current drift (pA/°C)
60
48
48
(TA – 25)/VDIFF
Total drift error (ppm)
RESOLUTION
3088
1088
Gain nonlinearity (ppm of FS)
5
5
5
2
eNO
G
6
eNI = 18,
eNO = 110
2
(eNI
+
´
´
BW
Voltage noise (1 kHz)
10
10
VDIFF
Total resolution error (ppm)
TOTAL ERROR
15
15
Total error
Total error = sum of all error sources
3436
2634
LAYOUT GUIDELINES
Attention to good layout practices is always recommended. Keep traces short and, when possible, use a printed
circuit board (PCB) ground plane with surface-mount components placed as close to the device pins as possible.
Place 0.1-μF bypass capacitors close to the supply pins. These guidelines should be applied throughout the
analog circuit to improve performance and provide benefits such as reducing the electromagnetic-interference
(EMI) susceptibility.
CMRR vs Frequency
The INA826 pinout has been optimized for achieving maximum CMRR performance over a wide range of
frequencies. However, care must be taken to ensure that both input paths are well-matched for source
impedance and capacitance to avoid converting common-mode signals into differential signals. In addition,
parasitic capacitance at the gain-setting pins can also affect CMRR over frequency. For example, in applications
that implement gain switching using switches or PhotoMOS® relays to change the value of RG, the component
should be chosen so that the switch capacitance is as small as possible.
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INA826
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APPLICATION IDEAS
Circuit Breaker
Figure 64 showns the INA826 used in a circuit breaker application.
+3 V
AVDD
DVDD
SCLK
DIO
CS
MSP430
Microcontroller
Serial
Interface
(SPI)
Passive
Integrator
RG
100 kW
INA826
Mux
ADC
IP
Ch 1
REF
G = 1
Rogowski
Coil
100 kW
PGA112
PGA113
+3 V
GND
REF
1.2 V
REF3312
Figure 64. Circuit Breaker Example
Programmable Logic Controller (PLC) Input
The INA826 used in an example programmable logic controller (PLC) input application is shown in Figure 65.
±10 V
100 kW
+15 V
4.87 kW
4 mA to 20 mA
±20 mA
VOUT = 2.5 V ± 2.3 V
12.4 kW
Device
20 W
REF
+2.5 V
-15 V
REF3225
+5 V
Figure 65. ±10-V, 4-mA to 20-mA PLC Input
Additional application ideas are shown in Figure 66 to Figure 70.
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INA826
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TINA-TI (FREE DOWNLOAD SOFTWARE)
Using TINA-TI SPICE-Based Analog Simulation Program with the INA826
TINA is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully functional version of the TINA software, preloaded with a library of macromodels in addition to a range
of both passive and active models. It provides all the conventional dc, transient, and frequency domain analysis
of SPICE as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways.
Virtual instruments offer users the ability to select input waveforms and probe circuit nodes, voltages, and
waveforms, creating a dynamic quick-start tool.
Figure 66 and Figure 68 show example TINA-TI circuits for the INA826 that can be used to develop, modify, and
assess the circuit design for specific applications. Links to download these simulation files are given below.
NOTE: These files require that either the TINA software (from DesignSoft) or TINA-TI software be installed.
Download the free TINA-TI software from the TINA-TI folder.
The circuit in Figure 66 is used to convert inputs of ±10 V, ±5 V, or ±20 mA to an output voltage range from 0.5 V
to 4.5 V. The input selection depends on the settings of SW1 and SW2. Further explanation as well as the
TINA-TI simulation circuit is provided in the compressed file that can be downloaded at the following link: PLC
Circuit.
+Vs
V1 15
CurrentInput
V2 15
Source_Switch
Vin
Iin
-Vs
Amp Out
Sen
se
+ Terminal
Iin
-
+Vs
INA Out
+
Vin
+
SW1
Rg
+
-
U1 INA159
Ref
2
ADC_Diff
+
Ref
Ref
1
+
RG 49.9k
SW2
VoltageInput
U2 INA826
Rg
-
R4 250
Vref 2.5
Vs 5
-Vs
- Terminal
Figure 66. Two Terminal Programmable Logic Controller (PLC) Input
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INA826
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SBOS562A –AUGUST 2011–REVISED SEPTEMBER 2011
Figure 67 is an example of a LEAD I ECG circuit. The input signals come from leads attached to the right arm
(RA) and left arm (LA). These signals are simulated with the circuitry in the corresponding boxes. Protection
resistors (RPROT1 and RPROT2) and filtering are also provided. The OPA333 is used as an integrator to remove the
gained-up dc offsets and servo the INA826 outputs to VREF. Finally, the right leg drive is biased to a potential
(+VS/2) and it inverts and amplifies the average common-mode signal back into the patient's right leg. This
architecture reduces the 50-/60-Hz noise pickup. Click the following link to download the TINA-TI file: ECG
Circuit.
+Vs
U1 OPA333
Vref
+
-
+
LA Electrode
R4 52k
ECGp
C2 47n
+Vs
+
Rprot1 100k
C10 1u
U4 INA826
+
R12 500k
ECG_LA
ECG_RA
Rg
C5 33p
C7 33p
RG1 6.1k
RG2 6.1k
Ref
Vout
C6 1n
Rg
-
C4 47n
R7 52k
Rprot2 100k
+Vs
ECGn
R1 1M
RA Electrode
Vref
V1 5
RL Electrode
R6 10k
C11 1n
R9 1M
-
+
R3 10k
R5 10M
+
U3 OPA2314
-
+
Rprot3 100k
+Vs
+
Vref
U2 OPA2314
+Vs
Figure 67. ECG Circuit
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Figure 68 shows an example of how the INA826 can be used for low-side current sensing. The load current
(ILOAD) creates a voltage drop across the shunt resistor (RSHUNT). This voltage is amplified by the INA826, with
gain set to 100. The output swing of the INA826 is set by the common-mode voltage (which is 0 V in low-side
current sensing) and power supplies. Therefore, a dual-supply circuit is implemented. The load current was set
from 1 A to 10 A, which corresponds to an output voltage range from 350 mV to 3.5 V. The output range can be
adjusted by changing the shunt resistor and/or the gain of the INA826. Click the following link to download the
TINA-TI file: Current Sensing Circuit.
+Vs
+Vs
Iload 10
V1 5
V2 5
Vbus 10
+
U2 INA826
+
Rg
Ref
Rshunt 3.5m
RG 499
Vout
Rg
-
Rout 10k
-Vs
-Vs
Figure 68. Low-Side Current Sensing
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SBOS562A –AUGUST 2011–REVISED SEPTEMBER 2011
Figure 69 shows an example of how the INA826 can be used for RTD signal conditioning. This circuit creates an
excitation current (ISET) by forcing +2.5 V from the REF5025 across RSET. The zero-drift, low-noise OPA188
creates the virtual ground that maintains a constant differential voltage across RSET with changing common-mode
voltage. This voltage is necessary because the voltage on the positive input of the INA826 fluctuates over
temperature as a result of the changing RTD resistance. Click the following link to download the TINA-TI file:
RTD Circuit.
+Vs
Vref5025
U2 REF5025
NC
Vout
Vin
Temp
Trim
GND
R2 1.5M
+
-
Vset
Rset 2.5k
VirtualGND
-Vs
+Vs
-
+
+
V1 15
V2 15
U1 OPA188
+
+Vs
A
Iset
+Vs
+
+
U4 INA826
Rg
-Vs
Ref
RTD 100
Rg 5k
+
-
Rg
-
Vout
-Vs
Rparasitic 5
Figure 69. RTD Signal Conditioning
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The circuit in Figure 70 creates a precision current ISET by forcing the INA826 VDIFF across RSET. The input
voltage VIN is amplified to the output of the INA826 and then divided down by the gain of the INA826 to create
VDIFF. ISET can be controlled either by changing the value of the gain-set resistor RG, the set resistor RSET, or by
changing VOUT through the gain of the composite loop. Care must be taken to ensure that the changing load
resistance RL does not create a voltage on the negative input of the INA826 that violates the compliance of the
common-mode input range. Likewise, the voltage on the output of the OPA170 must remain compliant
throughout the changing load resistance for this circuit to work properly. Click the following link to download the
TINA-TI file: Current Source.
R1 10k
R2 10k
C1 100p
-Vs
+Vs
U2 OPA170
-
+
+
+
U4 INA826
+
Rg
Vout
+
-
Ref
Vdiff
RG 1k
Rset 10k
+Vs
Rg
-
Vin
+Vs
-Vs
+
A
V1 15
V2 15
Iset
RL 1k
-Vs
Figure 70. Precision Current Source
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INA826
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SBOS562A –AUGUST 2011–REVISED SEPTEMBER 2011
EVALUATION MODULE (EVM)
The INA826EVM is intended to provide basic functional evaluation of the INA826. A diagram of the INA826EVM
is provided in Figure 71.
Figure 71. INA826 Evaluation Module
The INA826 provides the following features:
•
•
•
•
•
Intuitive evaluation with silkscreen schematic
Easy access to nodes with surface-mount test points
Advanced evaluation with two prototype areas
Reference voltage source flexibility
Convenient input and output filtering
The INA826EVM User Guide (SBOU115) available for download at www.ti.com provides instructions on how to
set up the device for dual- and single-supply operation. The user guide also includes schematics, layout, and a
bill of material (BOM).
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PACKAGE OPTION ADDENDUM
www.ti.com
14-Nov-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
INA826AID
INA826AIDGK
INA826AIDGKR
INA826AIDR
PREVIEW
ACTIVE
SOIC
MSOP
MSOP
SOIC
SON
D
8
8
8
8
8
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
DGK
DGK
D
80
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
ACTIVE
2500
2500
1000
250
Green (RoHS
& no Sb/Br)
PREVIEW
PREVIEW
PREVIEW
Green (RoHS
& no Sb/Br)
INA826AIDRGR
INA826AIDRGT
DRG
DRG
Green (RoHS
& no Sb/Br)
SON
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Nov-2011
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Sep-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
INA826AIDGKR
MSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Sep-2011
*All dimensions are nominal
Device
Package Type Package Drawing Pins
MSOP DGK
SPQ
Length (mm) Width (mm) Height (mm)
358.0 335.0 35.0
INA826AIDGKR
8
2500
Pack Materials-Page 2
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