INA828 [TI]
50µV 失调电压、7nV/√Hz 噪声、低功耗、精密仪表放大器;
| 型号： | INA828 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 50µV 失调电压、7nV/√Hz 噪声、低功耗、精密仪表放大器 放大器 仪表 仪表放大器 |
| 文件： | 总40页 (文件大小：1953K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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INA828
ZHCSGR1A –AUGUST 2017–REVISED JANUARY 2018
INA828 50µV 偏移、7nV/√Hz 噪声低功耗精密仪表放大器
1 特性
3 说明
1
•
精密仪表放大器演变：
INA828 是一款高精度仪表放大器，此放大器提供低功
耗并且可在极宽的单电源或双电源范围内工作。可通过
单个外部电阻器在 1 到 1000 范围内设置增益。由于采
用新的超 β 输入晶体管（这些晶体管可提供极低的输
入失调电压、失调电压漂移、输入偏置电流以及输入电
压和电流噪声），该器件可提供出色的精度。附加电路
可以为输入提供高达 ±40V 的过压保护。
–
–
第二代：INA828
第一代：INA128
•
•
•
•
•
•
•
低失调电压：最大值为 50µV
增益漂移：5ppm/°C (G = 1)，50ppm/°C (G > 1)
噪声：7nV/√Hz
带宽：2MHz (G = 1)、260kHz (G = 100)
与 1nF 电容负载一起工作时保持稳定
输入保护电压高达 ±40V
INA828 经过优化，可提供出色的共模抑制比。当 G =
1 时，整个输入共模范围内共模抑制比超过 90dB。该
器件非常适用于通过 5V 单电源和高达 ±18V 的双电源
供电的低电压运行。最后，INA828 采用 8 引脚 SOIC
封装，额定温度范围为 –40°C 至 +125°C。
共模抑制：
–
最小值为 110dB (G = 10)
•
•
•
电源抑制：最小值为 100dB (G = 1)
电源电流：最大值为 650 µA
电源范围：
Device Information(1)
PART NUMBER
INA828
PACKAGE
BODY SIZE (NOM)
–
–
单电源：4.5V 至 36V
SOIC (8)
4.90mm x 3.91mm
双电源：±2.25V 至 ±18V
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
•
•
额定温度范围：
–40°C 至 +125°C
封装：8 引脚 SOIC
2 应用
•
•
•
•
•
•
•
工业过程控制
断路器
电池检测仪
心电图 (ECG) 放大器
电力自动化
医疗仪表
便携式仪表
INA828 简化内部原理图
输入失调电压漂移的典型分布
+VS
4500
4000
3500
3000
2500
2000
1500
1000
500
Overvoltage
Protection
40 kꢀ
+
40 kꢀ
-IN
RG
œ
œ
25 kꢀ
25 kꢀ
OUT
REF
+
œ
RG
+IN
Overvoltage
Protection
+
40 kꢀ
40 kꢀ
0
-VS
Copyright © 2017, Texas Instruments Incorporated
Input Offset Voltage Drift (ꢀV/°C)
C001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBOS792
INA828
ZHCSGR1A –AUGUST 2017–REVISED JANUARY 2018
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 7
Detailed Description ............................................ 16
7.1 Overview ................................................................. 16
7.2 Functional Block Diagram ....................................... 16
7.3 Feature Description................................................. 17
7.4 Device Functional Modes........................................ 21
8
9
Application and Implementation ........................ 22
8.1 Reference Terminal................................................. 22
8.2 Input Bias Current Return Path............................... 24
8.3 PCB Assembly Effects on Precision ....................... 25
8.4 Typical Application .................................................. 26
8.5 Other Application Examples.................................... 28
Power Supply Recommendations...................... 29
10 Layout................................................................... 29
10.1 Layout Guidelines ................................................. 29
10.2 Layout Example .................................................... 30
11 器件和文档支持 ..................................................... 31
11.1 Documentation Support ........................................ 31
11.2 Receiving Notification of Documentation Updates 31
11.3 Community Resources.......................................... 31
11.4 商标....................................................................... 31
11.5 静电放电警告......................................................... 31
11.6 Glossary................................................................ 31
12 机械、封装和可订购信息....................................... 31
7
4 修订历史记录
Changes from Original (August 2017) to Revision A
Page
•
Changed MAX value for G = 1 in "GE" row from "±0.020%" to "±0.025%"............................................................................ 5
2
Copyright © 2017–2018, Texas Instruments Incorporated
INA828
www.ti.com.cn
ZHCSGR1A –AUGUST 2017–REVISED JANUARY 2018
5 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
1
RG
œIN
+IN
-VS
RG
8
7
6
5
2
3
4
+VS
OUT
REF
Pin Functions
PIN
I/O
DESCRIPTION
NAME
RG
NO.
1
—
Gain setting pin. Place a gain resistor between pin 1 and pin 8.
8
–IN
2
I
I
Negative (inverting) input
+IN
3
Positive (noninverting) input
–VS
REF
OUT
+VS
4
—
I
Negative supply
5
Reference input. This pin must be driven by a low impedance source.
6
O
—
Output
7
Positive supply
Copyright © 2017–2018, Texas Instruments Incorporated
3
INA828
ZHCSGR1A –AUGUST 2017–REVISED JANUARY 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–18
–40
–18
MAX
18
UNIT
Supply voltage
V
Voltage
40
Signal input pins
V
REF pin
18
Output short-circuit(2)
Operating, TA
Continuous
–50
–65
150
175
150
Temperature
Junction, TJ
Storage, Tstg
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Short-circuit to VS / 2.
6.2 ESD Ratings
VALUE
±1500
±750
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD) Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
MAX
36
UNIT
Single supply
Dual supply
Supply voltage
V
±2.25
–40
±18
125
150
Specified temperature
Operating temperature
°C
°C
–50
6.4 Thermal Information
INA828
THERMAL METRIC(1)
D (SOIC)
8 PINS
119.6
66.3
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
61.9
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
20.5
ψJB
61.4
RθJC(bot)
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2017–2018, Texas Instruments Incorporated
INA828
www.ti.com.cn
ZHCSGR1A –AUGUST 2017–REVISED JANUARY 2018
6.5 Electrical Characteristics
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT
G = 100, RTI
20
50
90
µV
µV
Input stage offset
voltage(1)(2)
VOSI
TA = –40°C to +125°C(3)
vs temperature, TA = –40°C to +125°C
G = 1, RTI
TA = –40°C to +125°C(3)
vs temperature, TA = –40°C to +125°C
G = 1, RTI
0.5
250
500
5
µV/°C
µV
50
Output stage offset
voltage(1)(2)
VOSO
µV
µV/°C
110
114
130
136
120
130
G = 10, RTI
Power-supply rejection
ratio
PSRR
dB
G = 100, RTI
135
G = 1000, RTI
140
zid
zic
Differential impedance
100 || 1
100 || 10
53
GΩ || pF
GΩ || pF
MHz
Common-mode impedance
RFI filter, –3-dB frequency
(V–) + 2
(V+) – 2
±40
VCM
Operating input range(4)
Input overvoltage range
V
V
VS = ±2.25 V to ±18 V, TA = –40°C to +125°C
TA = –40°C to +125°C
See Figure 48 to Figure 51
At dc to 60 Hz, RTI, VCM = (V–) + 2 V to (V+) – 2 V,
G = 1
90
110
130
140
100
120
140
145
At dc to 60 Hz, RTI, VCM = (V–) + 2 V to (V+) – 2 V,
G = 10
Common-mode rejection
ratio
CMRR
dB
At dc to 60 Hz, RTI, VCM = (V–) + 2 V to (V+) – 2 V,
G = 100
At dc to 60 Hz, RTI, VCM = (V–) + 2 V to (V+) – 2 V,
G = 1000
BIAS CURRENT
VCM = VS / 2
0.15
0.15
0.6
2
IB
Input bias current
nA
nA
TA = –40°C to +125°C
VCM = VS / 2
0.6
2
IOS
Input offset current
TA = –40°C to +125°C
NOISE VOLTAGE
f = 1 kHz, G = 100, RS = 0 Ω
fB = 0.1 Hz to 10 Hz, G = 100, RS = 0 Ω
f = 1 kHz, RS = 0 Ω
7
0.14
90
nV/√Hz
µVPP
Input stage voltage
eNI
eNO
In
noise(5)
nV/√Hz
µVPP
Output stage voltage
noise(5)
fB = 0.1 Hz to 10 Hz, RS = 0 Ω
f = 1 kHz
7.7
170
4.7
fA/√Hz
pAPP
Noise current
fB = 0.1 Hz to 10 Hz, G = 100
GAIN
G
Gain equation
Range of gain
1 + (50 kΩ / RG)
V/V
V/V
1
1000
±0.025%
±0.15%
±0.15%
G = 1, VO = ±10 V
±0.005%
±0.025%
±0.025%
±0.05%
G = 10, VO = ±10 V
GE
Gain error
G = 100, VO = ±10 V
G = 1000, VO = ±10 V
G = 1, TA = –40°C to +125°C
G > 1, TA = –40°C to +125°C
±5
Gain vs temperature(6)
ppm/°C
±50
(1) Total offset, referred-to-input (RTI): VOS = (VOSI) + (VOSO / G).
(2) Offset drifts are uncorrelated. Input-referred offset drift is calculated using: ΔVOS(RTI) = √[ΔVOSI2 + (ΔVOSO / G)2]
(3) Specified by characterization.
(4) Input voltage range of the INA828 input stage. The input range depends on the common-mode voltage, differential voltage, gain, and
reference voltage. See Typical Characteristic curves 图 48 through 图 51 for more information.
(5) Total RTI voltage noise is equal to: eN(RTI) = √[eNI2 + (eNO / G)2]
(6) The values specified for G > 1 do not include the effects of the external gain-setting resistor, RG.
Copyright © 2017–2018, Texas Instruments Incorporated
5
INA828
ZHCSGR1A –AUGUST 2017–REVISED JANUARY 2018
www.ti.com.cn
Electrical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
G = 1 to 10, VO = –10 V to +10 V, RL = 10 kΩ
G = 100, VO = –10 V to +10 V, RL = 10 kΩ
G = 1000, VO = –10 V to +10 V, RL = 10 kΩ
G = 1 to 100, VO = –10 V to +10 V, RL = 2 kΩ
1
10
15
20
Gain nonlinearity
ppm
30
OUTPUT
Voltage swing
(V–) + 0.15
(V+) – 0.15
V
Load capacitance stability
1000
1.3
pF
Closed-loop output
impedance
ZO
ISC
f = 10 kHz
Ω
Short-circuit current
Continuous to VS / 2
±18
mA
FREQUENCY RESPONSE
G = 1
2.0
640
260
33
MHz
kHz
G = 10
BW
SR
tS
Bandwidth, –3 dB
Slew rate
G = 100
G = 1000
G = 1, VO = ±10 V
1.2
12
V/µs
0.01%, G = 1 to 100, VSTEP = 10 V
0.01%, G = 1000, VSTEP = 10 V
0.001%, G = 1 to 100, VSTEP = 10 V
0.001%, G = 1000, VSTEP = 10 V
40
Settling time
µs
16
50
REFERENCE INPUT
RIN Input impedance
40
kΩ
V
Voltage range
(V–)
(V+)
Gain to output
1
V/V
Reference gain error
0.01%
POWER SUPPLY
Single supply
4.5
36
±18
650
850
VS
IQ
Power-supply voltage
V
Dual supply
±2.25
VIN = 0 V
600
Quiescent current
µA
vs temperature, TA = –40°C to +125°C
6
版权 © 2017–2018, Texas Instruments Incorporated
INA828
www.ti.com.cn
ZHCSGR1A –AUGUST 2017–REVISED JANUARY 2018
6.6 Typical Characteristics
At TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
450
400
350
300
250
200
150
100
50
4500
4000
3500
3000
2500
2000
1500
1000
500
0
0
Input Offset Voltage (ꢀV)
Input Offset Voltage Drift (ꢀV/°C)
C001
C001
N = 1886
Mean = 4.73 µV
N = 19081
Mean = 0.16 nV/°C
Std. Dev. = 13.98 µV
Std. Dev. = 0.09 µV/°C
图 1. Typical Distribution of Input Offset Voltage
图 2. Typical Distribution of Input Offset Voltage Drift
600
500
400
300
200
100
0
6000
5000
4000
3000
2000
1000
0
Output Offset Voltage Drift (ꢀV/°C)
Output Offset Voltage (ꢀV)
C001
C001
N = 1886
Mean = –8.71 µV
N = 19081
Mean = –0.73 µV/°C
Std. Dev. = 48.57 µV
Std. Dev. = 0.74 µV/°C
图 3. Typical Distribution of Output Offset Voltage
图 4. Typical Distribution of Output Offset Voltage Drift
100
80
500
Mean
+31
-31
Mean
400
+31
-31
60
300
200
40
20
100
0
0
œ20
œ40
œ60
œ80
œ100
œ100
œ200
œ300
œ400
œ500
0
50
100
150
0
50
100
150
œ50
œ50
Temperature (°C)
Temperature (°C)
C001
C001
G = 100
88 units, 3 wafer lots
G = 1
88 units, 3 wafer lots
图 5. Input-Referred Offset Voltage vs Temperature
图 6. Input-Referred Offset Voltage vs Temperature
版权 © 2017–2018, Texas Instruments Incorporated
7
INA828
ZHCSGR1A –AUGUST 2017–REVISED JANUARY 2018
www.ti.com.cn
Typical Characteristics (接下页)
At TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
450
400
350
300
250
200
150
100
50
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
0
0
Input Bias Current (pA)
Input Bias Current (pA)
C001
C001
N = 1886
Mean = 36.25 pA
N = 19081
Mean = –5.32 pA
Std. Dev. = 65.31 pA
Std. Dev. = 57.46 pA
图 7. Typical Distribution of Input Bias Current (25°C)
图 8. Typical Distribution of Input Bias Current (90°C)
0.6
450
400
350
300
250
200
150
100
50
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
Mean
+31
-31
0
0
50
100
150
œ50
Input Offset Current (pA)
Temperature (°C)
C117
C001
N = 1886
Std. Dev. = 63.86 pA
Mean = –52.64 pA
图 10. Input Bias Current vs Temperature
图 9. Typical Distribution of Input Offset Current
0.8
0.6
0.4
0.2
0
300
Mean
+31
-31
250
200
150
100
50
-0.2
-0.4
-0.6
-0.8
0
-50
0
50
100
150
Common-Mode Rejection Ratio (ꢀV/V)
Temperature (°C)
C116
C001
N = 1886
Mean = 1.18 µV/V
Std. Dev. = 10.04 µV/V
图 11. Input Offset Current vs Temperature
图 12. Typical CMRR Distribution (G = 1)
8
版权 © 2017–2018, Texas Instruments Incorporated
INA828
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ZHCSGR1A –AUGUST 2017–REVISED JANUARY 2018
Typical Characteristics (接下页)
At TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
125
120
115
110
105
100
95
300
250
200
150
100
50
Unit 1
Unit 2
Unit 3
Unit 4
Unit 5
90
0
85
-50
0
50
100
150
Common-Mode Rejection Ratio (ꢀV/V)
Temperature (°C)
5 Typical Units
C121
C001
N = 1886
Mean = 0.01 µV/V
Std. Dev. = 0.1 µV/V
图 14. CMRR vs Temperature (G = 1)
图 13. Typical CMRR Distribution (G = 100)
155
150
145
140
135
130
125
120
115
10
8
20
15
10
5
6
4
2
0
0
œ2
œ4
œ6
œ8
œ10
-5
Unit 1
Unit 2
Unit 3
Unit 4
Unit 5
-10
-15
-20
Input Current
Output Voltage
-50
0
50
100
150
0
10
20
30
40
œ40 œ30 œ20 œ10
Temperature (°C)
Input Voltage (V)
C122
C015
图 15. CMRR vs Temperature (G = 100)
图 16. Input Current vs Input Overvoltage
140
120
100
80
140
120
100
80
60
60
G = 1
G = 1
40
40
G = 10
G = 100
G = 1000
G = 10
G = 100
G = 1000
20
20
0
0
10
100
1k
10k
100k
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
C006
C005
图 18. CMRR vs Frequency
(RTI, 1-kΩ Source Imbalance)
图 17. CMRR vs Frequency (RTI)
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INA828
ZHCSGR1A –AUGUST 2017–REVISED JANUARY 2018
www.ti.com.cn
Typical Characteristics (接下页)
At TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
140
120
100
80
140
120
100
80
60
60
G = 1
G = 1
40
40
G = 10
G = 100
G = 1000
G = 10
G = 100
G = 1000
20
20
0
0
1
10
100
1k
10k
100k
1
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
C003
C004
图 19. Positive PSRR vs Frequency (RTI)
图 20. Negative PSRR vs Frequency (RTI)
80
1000
G = 1
G = 1
G = 10
G = 100
G = 1000
G = 10
G = 100
G = 1000
60
40
20
0
100
10
1
-20
-40
100
1k
10k
100k
1M
10M
1
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
C001
C002
图 21. Gain vs Frequency
图 22. Voltage Noise Spectral Density
vs Frequency (RTI)
3
2
1
0
1000
100
10
-1
-2
-3
-4
1
10
100
1k
10k
0
1
2
3
4
5
6
7
8
9
10
Frequency (Hz)
Time (1 s/div)
C007
C008
图 23. Current Noise Spectral Density
图 24. 0.1-Hz to 10-Hz RTI Voltage Noise (G = 1)
vs Frequency (RTI)
10
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ZHCSGR1A –AUGUST 2017–REVISED JANUARY 2018
Typical Characteristics (接下页)
At TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
80
2
1.5
1
60
40
20
0.5
0
0
-20
-40
-60
-80
-0.5
-1
-1.5
-2
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
Time (1 s/div)
Time (1 s/div)
C008
C008
图 25. 0.1-Hz to 10-Hz RTI Voltage Noise (G = 1000)
图 26. 0.1-Hz to 10-Hz RTI Current Noise
2
1.5
1
1
0.5
0
-0.5
-1
0.5
0
-40°C
25°C
-1.5
-2
-0.5
-1
125°C
-50
0
50
100
150
-16
-12
-8
-4
0
4
8
12
16
Common Mode Voltage(V)
Temperature (°C)
C119
C116
VS = ±15 V
图 28. Gain Error vs Temperature (G = 1)
图 27. Input Bias Current vs Common-Mode Voltage
30
20
0.9
0.8
0.7
0.6
0.5
0.4
0.3
10
0
-10
-20
-30
-40
-50
VS = ± 15 V
VS = ± 2.25 V
100 150
-50
0
50
100
150
0
50
œ50
Temperature (°C)
Temperature (°C)
C120
C123
图 29. Gain Error vs Temperature (G = 100)
图 30. Supply Current vs Temperature
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Typical Characteristics (接下页)
At TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
10
20
15
10
5
8
6
4
2
0
0
-2
-4
-6
-8
-10
-5
-10
-15
-20
0
2
4
6
8
10
0
2
4
6
8
10
œ10 œ8
œ6
œ4
œ2
œ10 œ8
œ6
œ4
œ2
Output Voltage (V)
Output Voltage (V)
C124
C125
图 31. Gain Nonlinearity (G = 1)
图 32. Gain Nonlinearity (G = 100)
300
250
200
150
100
50
-40°C
25°C
-40°C
25°C
85°C
-160
-180
-200
-220
-240
-260
-280
-300
85°C
125°C
125°C
-14
-13.8 -13.6 -13.4 -13.2
-13
-12.8 -12.6
12.5
12.7
12.9
13.1
13.3
13.5
13.7
Input Common-Mode Voltage (V)
Input Common-Mode Voltage (V)
C126
C127
图 33. Offset Voltage vs Negative Common-Mode Voltage
图 34. Offset Voltage vs Positive Common-Mode Voltage
15
14.9
14.8
14.7
14.6
14.5
14.4
-14
-40°C
-14.1
25°C
85°C
-14.2
125°C
-14.3
-14.4
-14.5
-14.6
-14.7
-14.8
-14.9
-15
14.3
-40°C
14.2
25°C
85°C
14.1
125°C
14
0
2
4
6
8
10
12
14
16
0
2
4
6
8
10
12
14
16
Output Current (mA)
Output Current (mA)
C128
C129
图 35. Positive Output Voltage Swing vs Output Current
图 36. Negative Output Voltage Swing vs Output Current
12
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Typical Characteristics (接下页)
At TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
20
1
-40
-60
-80
-100
VS = ±15 V
18
VS = ±5 V
16
14
0.1
12
10
8
0.01
6
4
2
G = 1
G = 10
G = 100
0
0.001
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
C001
C002
500-kHz Measurement bandwidth
1-VRMS Output voltage
100-kΩ Load
图 37. Large-Signal Frequency Response
图 38. THD+N vs Frequency
100
80
70
60
50
40
30
20
10
0
Positive Overshoot
Negative Overshoot
60
40
20
0
-20
-40
-60
-80
-100
-10
-5
0
5
10
15
20
25
30
1
10
100
1000
Time (ꢀs)
Capacitive Load (pF)
C012
C011
G = 1, RL = 10 kΩ, CL = 100 pF
图 40. Small-Signal Response
图 39. Overshoot vs Capacitive Loads
100
80
100
80
60
60
40
40
20
20
0
0
-20
-40
-60
-80
-100
-20
-40
-60
-80
-100
-10
-5
0
5
10
15
20
25
30
-50 -30 -10 10
30
50
70
90 110 130 150
Time (ꢀs)
Time (ꢀs)
C013
C014
G = 10, RL = 10 kΩ, CL = 100 pF
图 41. Small-Signal Response
G = 100, RL = 10 kΩ, CL = 100 pF
图 42. Small-Signal Response
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Typical Characteristics (接下页)
At TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
100
Output
Input
80
60
40
20
0
-20
-40
-60
-80
-100
-200 -100
0
100 200 300 400 500 600 700 800
Time (10 µs/div)
Time (ꢀs)
C015
C0xx
G = 1000, RL = 10 kΩ, CL = 100 pF
图 43. Small-Signal Response
图 44. Large Signal Step Response
1000
100
10
110
90
70
50
30
10
1
0.1
0.01
1
10
100
1k
10k
100k
1M
10M
10M
100M
Frequency (Hz)
1G
10G
Frequency (Hz)
C001
C001
图 45. Closed-Loop Output Impedance
图 46. Differential-Mode EMI Rejection Ratio
5
4
3
2
1
0
VREF = 0 V
110
90
70
50
30
10
VREF = 2.5 V
10M
100M
Frequency (Hz)
1G
10G
0
1
2
3
4
5
6
Output Voltage (V)
C001
C006
VS = 5 V, G = 1
图 48. Input Common-Mode Voltage vs Output Voltage
图 47. Common-Mode EMI Rejection Ratio
14
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Typical Characteristics (接下页)
At TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
5
4
3
2
1
0
5
VREF = 0 V
4
VREF = 2.5 V
3
2
1
0
-1
-2
-3
-4
-5
G = 1
G = 100
0
1
2
3
4
5
6
0
2
4
6
œ6
œ4
œ2
Output Voltage (V)
Output Voltage (V)
C006
C006
VS = 5 V, G = 100
VS = ±5 V, VREF = 0 V
图 50. Input Common-Mode Voltage vs Output Voltage
图 49. Input Common-Mode Voltage vs Output Voltage
15
10
5
0
-5
-10
-15
G = 1
G = 100
-20
0
10
20
œ20
œ10
Output Voltage (V)
C006
VS = ±15 V, VREF = 0 V
图 51. Input Common-Mode Voltage vs Output Voltage
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7 Detailed Description
7.1 Overview
The INA828 is a monolithic precision instrumentation amplifier incorporating a current-feedback input stage and a
4-resistor difference amplifier output stage. The differential input voltage is buffered by Q1 and Q2 and is forced
across RG, which causes a signal current to flow through RG, R1, and R2. The output difference amplifier, A3,
removes the common-mode component of the input signal and refers the output signal to the REF terminal. The
VBE and voltage drop across R1 and R2 produce output voltages on A1 and A2 that are approximately 0.8 V lower
than the input voltages.
Each input is protected by two field-effect transistors (FETs) that provide a low series resistance under normal
signal conditions, and preserve excellent noise performance. When excessive voltage is applied, these
transistors limit input current to approximately 8 mA.
7.2 Functional Block Diagram
+VS
VB
RB
RB
IB Cancellation
IB Cancellation
40 kꢀ
-VS +VS
40 kꢀ
œ
A1
A2
A3
+
OUT
REF
40 kꢀ
40 kꢀ
+VS
+VS
-VS +VS
Q2
Q1
Super-ꢁ
Super-ꢁ
-IN
+IN
NPN
NPN
Overvoltage
Protection
+VS
+VS
Overvoltage
Protection
R2
25 kꢀ
R1
25 kꢀ
RG
(External)
-VS
-VS
RG
RG
-VS
-VS
Copyright © 2017, Texas Instruments Incorporated
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7.3 Feature Description
7.3.1 Setting the Gain
图 52 shows that the gain of the INA828 is set by a single external resistor, RG, connected between the RG pins
(pins 1 and 8).
V+
+VS
Overvoltage
Protection
40 kꢀ
+
40 kꢀ
-IN
œ
RG
œ
50 kW
RG
25 kꢀ
25 kꢀ
OUT
REF
G = 1+
RG
+
VO = G V+IN - V-IN + V
(
)
REF
RG
+IN
œ
Overvoltage
Protection
+
40 kꢀ
40 kꢀ
-VS
Copyright © 2017, Texas Instruments Incorporated
V-
图 52. Simplified Diagram of the INA828 With Gain and Output Equations
The value of RG is selected according to:
50 kW
RG
G = 1+
(1)
表 1 lists several commonly-used gains and resistor values. The 50-kΩ term in 公式 1 comes from the sum of the
two internal 25-kΩ feedback resistors. These on-chip resistors are laser-trimmed to accurate absolute values.
The accuracy and temperature coefficients of these resistors are included in the gain accuracy and drift
specifications of the INA828.
表 1. Commonly-Used Gains and Resistor Values
DESIRED GAIN
RG (Ω)
NC
NEAREST 1% RG (Ω)
1
2
NC
49.9 k
12.4 k
5.49 k
2.61 k
1.02 k
511
50 k
5
12.5 k
5.556 k
2.632 k
1.02 k
505.1
251.3
100.2
50.05
10
20
50
100
200
500
1000
249
100
49.9
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7.3.1.1 Gain Drift
The stability and temperature drift of the external gain setting resistor, RG, also affects gain. The contribution of
RG to gain accuracy and drift can be determined from 公式 1.
The best gain drift of 5 ppm/℃ (maximum) can be achieved when the INA828 uses G = 1 without RG connected.
In this case, gain drift is limited only by the slight mismatch of the temperature coefficient of the integrated 40-kΩ
resistors in the differential amplifier (A3). At gains greater than 1, gain drift increases as a result of the individual
drift of the 25-kΩ resistors in the feedback of A1 and A2, relative to the drift of the external gain resistor RG. The
low temperature coefficient of the internal feedback resistors significantly improves the overall temperature
stability of applications using gains greater than 1 V/V over alternate solutions.
Low resistor values required for high gain can make wiring resistance important. Sockets add to the wiring
resistance and contribute additional gain error (such as a possible unstable gain error) at gains of approximately
100 or greater. To assure stability, avoid parasitic capacitance of more than a few picofarads at RG connections.
Careful matching of any parasitics on both RG pins maintains optimal CMRR over frequency; see Typical
Characteristics, 图 17.
7.3.2 EMI Rejection
Texas Instruments developed a method to accurately measure the immunity of an amplifier over a broad
frequency spectrum, extending from 10 MHz to 6 GHz. This method uses an EMI rejection ratio (EMIRR) to
quantify the ability of the INA828 to reject EMI. The offset resulting from an input EMI signal can be calculated
using 公式 2:
EMIRR (dB)
≈
’
2
≈
∆
’
÷
-
VRF_PEAK
100 mVP
∆
«
÷
◊
20
DVOS
=
∂10
∆
«
÷
◊
where
•
VRF_PEAK is the peak amplitude of the input EMI signal.
(2)
图 53 and 图 54 show the INA828 EMIRR graph for both differential and common-mode EMI rejection across this
frequency range. 表 2 shows the EMIRR values for the INA828 at frequencies commonly encountered in real-
world applications. Applications listed in 表 2 can be centered on or operated near the particular frequency
shown. Depending on the end-system requirements, additional EMI filters may be required near the signal inputs
of the system, as well as incorporating known good practices such as using short traces, low-pass filters, and
damping resistors combined with parallel and shielded signal routing.
110
90
70
50
30
10
110
90
70
50
30
10
10M
100M
Frequency (Hz)
1G
10G
10M
100M
Frequency (Hz)
1G
10G
C001
C001
图 53. Common-Mode EMIRR Testing
图 54. Differential Mode EMIRR Testing
18
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表 2. INA828 EMIRR for Frequencies of Interest
DIFFERENTIAL COMMON-MODE
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR
EMIRR
Mobile radio, mobile satellite, space operation, weather, radar, ultrahigh-
frequency (UHF) applications
400 MHz
48 dB
87 dB
Global system for mobile communications (GSM) applications, radio
communication, navigation, GPS (up to 1.6 GHz), GSM, aeronautical mobile,
UHF applications
900 MHz
1.8 GHz
2.4 GHz
52 dB
94 dB
66 dB
98 dB
51 dB
57 dB
GSM applications, mobile personal communications, broadband, satellite,
L-band (1 GHz to 2 GHz)
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications,
industrial, scientific and medical (ISM) radio band, amateur radio and satellite,
S-band (2 GHz to 4 GHz)
3.6 GHz
5 GHz
Radiolocation, aero communication and navigation, satellite, mobile, S-band
79 dB
90 dB
87 dB
92 dB
802.11a, 802.11n, aero communication and navigation, mobile communication,
space and satellite operation, C-band (4 GHz to 8 GHz)
7.3.3 Input Common-Mode Range
The linear input voltage range of the INA828 input circuitry extends within 2 Volts of both power supplies and
maintains excellent common-mode rejection throughout this range. The common-mode range for the most
common operating conditions are shown in 图 55, 图 50, and 图 51. The common-mode range for other
operating conditions is best calculated using the INA common-mode range calculating tool. The INA828 device
can operate over a wide range of power supplies and VREF configurations, thus providing a comprehensive
guide to common-mode range limits for all possible conditions is impractical.
5
4
3
2
1
0
5
4
3
2
1
0
VREF = 0 V
VREF = 0 V
VREF = 2.5 V
VREF = 2.5 V
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Output Voltage (V)
Output Voltage (V)
C006
C006
VS = 5 V, G = 1
VS = 5 V, G = 100
图 55. Input Common-Mode Voltage vs Output Voltage
图 56. Input Common-Mode Voltage vs Output Voltage
5
4
15
10
5
3
2
1
0
0
-5
-1
-2
-3
-10
-15
G = 1
G = 1
-4
G = 100
-5
G = 100
-20
0
2
4
6
0
10
20
œ6
œ4
œ2
œ20
œ10
Output Voltage (V)
Output Voltage (V)
C006
C006
VS = ±5 V, VREF = 0 V
VS = ±15 V, VREF = 0 V
图 58. Input Common-Mode Voltage vs Output Voltage
图 57. Input Common-Mode Voltage vs Output Voltage
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7.3.4 Input Protection
The inputs of the INA828 device are individually protected for voltages up to ±40 V. For example, a condition of
–40 V on one input and 40 V on the other input does not cause damage. Internal circuitry on each input provides
low series impedance under normal signal conditions. If the input is overloaded, the protection circuitry limits the
input current to a value of approximately 8 mA.
+V
ZD1
+VS
IN
Overvoltage
Protection
Input Voltage
Source
+
Input Transistor
œ
-VS
ZD2
-V
图 59. Input Current Path During an Overvoltage Condition
During an input overvoltage condition, current flows through the input protection diodes into the power supplies,
see 图 59. If the power supplies are unable to sink current, then Zener diode clamps (ZD1 and ZD2 in 图 59)
must be placed on the power supplies to provide a current pathway to ground. 图 60 illustrates the input current
for input voltages from –40 V to +40 V when the INA828 is powered by ±15-V supplies.
10
8
20
15
10
5
6
4
2
0
0
œ2
œ4
œ6
œ8
œ10
-5
-10
-15
-20
Input Current
Output Voltage
0
10
20
30
40
œ40 œ30 œ20 œ10
Input Voltage (V)
C015
图 60. Input Current vs Input Overvoltage
20
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7.3.5 Operating Voltage
The INA828 operates over a power-supply range of 4.5 V to 36 V (±2.25 V to ±18 V).
CAUTION
Supply voltages higher than 40 V (±20 V) can permanently damage the device.
Parameters that vary over supply voltage or temperature are shown in the Typical
Characteristics section of this data sheet.
7.4 Device Functional Modes
The INA828 has a single functional mode and is operational when the power-supply voltage is greater than 4.5 V
(±2.25 V). The maximum power-supply voltage for the INA828 is 36 V (±18 V).
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Reference Terminal
The output voltage of the INA828 is developed with respect to the voltage on the reference terminal, REF. Often,
in dual-supply operation, the reference pin (pin 6) is connected to the low-impedance system ground. In single-
supply operation, offsetting the output signal to a precise mid-supply level is useful (for example, 2.5 V in a 5-V
supply environment). To accomplish this level shift, a voltage source must be connected to the REF pin to level-
shift the output so that the INA828 can drive a single-supply ADC.
The voltage source applied to the reference terminal must have a low output impedance. As illustrated in 图 61,
any resistance at the reference terminal (shown as RREF in 图 61) is in series with one of the internal 40-kΩ
resistors.
V+
+VS
Overvoltage
Protection
40 kꢀ
+
40 kꢀ
-IN
œ
RG
œ
25 kꢀ
25 kꢀ
RG
OUT
REF
+
RG
+IN
œ
Overvoltage
Protection
+
RREF
40 kꢀ
40 kꢀ
-VS
V-
图 61. Parasitic Resistance Shown at the Reference Terminal
The parasitic resistance at the reference terminal, RREF, creates an imbalance in the 4 resistors of the internal
difference amplifier, resulting in degraded common-mode rejection ratio (CMRR). 图 62 shows the degradation in
CMRR of the INA828 for increasing resistance at the reference terminal. For the best performance, keep the
source impedance to the REF terminal, RREF, below 5 Ω.
22
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Reference Terminal (接下页)
120
100
80
60
40
20
0
0 ꢀ
5 ꢀ
10 ꢀ
15 ꢀ
20 ꢀ
10
100
1k
10k
Frequency (Hz)
C001
图 62. The Effect of Increasing Resistance at the Reference Terminal
Voltage reference ICs are an excellent option for providing a low-impedance voltage source for the reference
terminal. However, if a resistor voltage divider is used to generate a reference voltage, it must be buffered by an
op amp as shown in 图 63 to avoid CMRR degradation.
5 V
+IN
RG
RG
INA828
RG
OUT
œIN
5 V
5 V
100 kꢀ
+
OPA191
1 ꢁF
œ
100 kꢀ
Copyright © 2017, Texas Instruments Incorporated
图 63. Using an Op Amp to Buffer Reference Voltages
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8.2 Input Bias Current Return Path
The input impedance of the INA828 is extremely high—approximately 100 GΩ. However, a path must be
provided for the input bias current of both inputs. This input bias current is typically 150 pA. High input
impedance means that this input bias current changes very little with varying input voltage.
Input circuitry must provide a path for this input bias current for proper operation. 图 64 shows various provisions
for an input bias current path. Without a bias current path, the inputs float to a potential that exceeds the
common-mode range of the INA828, and the input amplifiers saturate. If the differential source resistance is low,
the bias current return path can be connected to one input (as shown in the thermocouple example in 图 64).
With a higher source impedance, using two equal resistors provides a balanced input with possible advantages
of a lower input offset voltage as a result of bias current and better high-frequency common-mode rejection.
Microphone,
Hydrophone,
and So Forth
TI Device
47 kW
47 kW
Thermocouple
TI Device
10 kW
TI Device
Center tap provides
bias current return.
Copyright © 2017, Texas Instruments Incorporated
图 64. Providing an Input Common-Mode Current Path
24
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8.3 PCB Assembly Effects on Precision
The printed-circuit board (PCB) assembly process, including reflow soldering, imparts thermal stresses on the
INA828 which can degrade the precision of the device and must be considered in the development of very-high-
precision systems. Baking the PCBs after the assembly process can restore the precision of the device to pre-
assembly values. 图 65, 图 66, and 图 67 illustrate the effect of reflow soldering on the typical distribution of input
offset voltage of the INA828. 图 65 shows the distribution of input offset voltage for a set of INA828 devices prior
to the PCB assembly process. Exposing the INA828 to a JEDEC-standard thermal profile for reflow soldering
produces the histogram shown in 图 66 on another set of INA828 devices. The standard deviation of input offset
voltage has almost doubled due to the thermal stress imparted to the INA828 from the reflow process. However,
baking INA828 units for 30 minutes at 125°C after the reflow soldering process produced the distribution given in
图 67. The post-reflow bake restored the standard deviation of the input offset voltage to pre-assembly levels.
300
250
200
150
100
50
80
70
60
50
40
30
20
10
0
0
Input Offset Voltage (ꢀV)
Input Offset Voltage (ꢀV)
C001
C001
图 65. Typical Distribution of INA828 Input Offset Voltage
图 66. Typical Distribution of INA828 Input Offset Voltage
Prior to Reflow Soldering
After Reflow Soldering
250
200
150
100
50
0
Input Offset Voltage (ꢀV)
C001
图 67. Typical Distribution of Post-Reflow INA828 Units Baked at 125°C for 30 Minutes
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8.4 Typical Application
图 68 shows a three-terminal programmable-logic controller (PLC) design for the INA828. This PLC reference
design accepts inputs of ±10 V or ±20 mA. The output is a single-ended voltage of 2.5 V ±2.3 V (or 200 mV to
4.8 V). Many PLCs typically have these input and output ranges.
±10 V
15 V
REF5025
R
= 100 kΩ
= 4.17 kΩ
1
VOUT
GND
VIN
NR
1 ꢀF
1 ꢀF
1 ꢀF
15 V
+VS
R
2
±20 mA
-IN
RG
REF
R
3
=
V
2.5 V ± 2.3 V
INA828
OUT
R
= 10.5 kΩ
OUT
G
20 Ω
RG
+IN
-VS
-15 V
Copyright © 2017, Texas Instruments Incorporated
图 68. PLC Input (±10 V, 4 mA to 20 mA)
8.4.1 Design Requirements
For this application, the design requirements are:
•
•
•
•
•
4-mA to 20-mA input with less than 20-Ω burden
±20-mA input with less than 20-Ω burden
±10-V input with impedance of approximately 100 kΩ
Maximum 4-mA to 20-mA or ±20-mA burden voltage equal to ±0.4 V
Output range within 0 V to 5 V
8.4.2 Detailed Design Procedure
There are two modes of operation for the circuit shown in 图 68: current input and voltage input. This design
requires R1 >> R2 >> R3. Given this relationship, 公式 3 calculates the current input mode transfer function.
VOUT-I = VD ´ G + VREF = -(IIN ´ R3) ´ G + VREF
where
•
•
•
•
G represents the gain of the instrumentation amplifier
VD represents the differential voltage at the INA828 inputs
VREF is the voltage at the INA828 REF pin
IIN is the input current
(3)
(4)
公式 4 shows the transfer function for the voltage input mode.
R2
VOUT-V = VD ´ G + VREF = - VIN
´
´ G + VREF
R1 + R2
where
•
VIN is the input voltage
R1 sets the input impedance of the voltage input mode. The minimum typical input impedance is 100 kΩ. 100 kΩ
is selected for R1 because increasing the R1 value also increases noise. The value of R3 must be extremely
small compared to R1 and R2. 20 Ω for R3 is selected because that resistance value is much smaller than R1 and
yields an input voltage of ±400 mV when operated in current mode (±20 mA).
26
版权 © 2017–2018, Texas Instruments Incorporated
INA828
www.ti.com.cn
ZHCSGR1A –AUGUST 2017–REVISED JANUARY 2018
Typical Application (接下页)
Use 公式 5 to calculate R2 given VD = ±400 mV, VIN = ±10 V, and R1 = 100 kΩ.
R2
R1 ´ VD
VD = VIN ´
® R2 =
= 4.167 kW
R1 + R2
VIN - VD
(5)
The value obtained from 公式 5 is not a standard 0.1% value, so 4.17 kΩ is selected. R1 and R2 also use 0.1%
tolerance resistors to minimize error.
Use 公式 6 to calculate the ideal gain of the instrumentation amplifier.
V
OUT - VREF
V
4.8 V - 2.5 V
G =
=
= 5.75
V
VD
400 mV
(6)
(7)
公式 7 calculates the gain-setting resistor value using the INA828 gain equation, 公式 1.
50 kW 50 kW
RG
=
=
= 10.5 kW
G -1 5.75 -1
10.5 kΩ is a standard 0.1% resistor value that can be used in this design.
8.4.3 Application Curves
图 69 and 图 70 show typical characteristic curves for the circuit in 图 68.
5
4
3
2
1
0
5
4
3
2
1
0
-10
-5
0
5
10
-20
-10
0
10
20
Input Voltage (V)
Input Current (mA)
C001
C001
图 69. PLC Output Voltage vs Input Voltage
图 70. PLC Output Voltage vs Input Current
版权 © 2017–2018, Texas Instruments Incorporated
27
INA828
ZHCSGR1A –AUGUST 2017–REVISED JANUARY 2018
www.ti.com.cn
8.5 Other Application Examples
8.5.1 Resistance Temperature Detector Interface
图 71 illustrates a 3-wire interface circuit for resistance temperature detectors (RTDs). The circuit incorporates
analog linearization and has an output voltage range from 0 to 5 V. The linearization technique employed is
described in Analog linearization of resistance temperature detectors. Series and parallel combinations of
standard 1% resistor values are used to achieve less than 0.02°C of error over a 200°C temperature span.
15 V
REF5050
VOUT
GND
VIN
NR
4.99
kꢀ
4.99
kꢀ
-IN
RG
VOUT
1.13
kꢀ
100
kꢀ
2.87
kꢀ
0 V at 0°C
5 V at 200°C
25 mV/°C
100 ꢀ
INA828
OUT
RG
+IN
Pt100 RTD
100 ꢀ
-15 V
105 kꢀ 1.18 kꢀ
Copyright © 2017, Texas Instruments Incorporated
图 71. A 3-Wire Interface for RTDs With Analog Linearization
5
4.5
4
0.018
0.016
0.014
0.012
0.01
3.5
3
2.5
2
0.008
0.006
0.004
0.002
0
1.5
1
0.5
0
0
50
100
150
200
0
50
100
150
200
Temperature (°C)
Temperature (°C)
C001
C001
图 72. Transfer Function of 3-Wire RTD Interface
图 73. Temperature Error Over Full Temperature Range
28
版权 © 2017–2018, Texas Instruments Incorporated
INA828
www.ti.com.cn
ZHCSGR1A –AUGUST 2017–REVISED JANUARY 2018
9 Power Supply Recommendations
The nominal performance of the INA828 is specified with a supply voltage of ±15 V and mid-supply reference
voltage. The device can also be operated using power supplies from ±1.5 V (3 V) to ±18 V (36 V) and non mid-
supply reference voltages with excellent performance. Parameters that can vary significantly with operating
voltage and reference voltage are illustrated in the Typical Characteristics section.
10 Layout
10.1 Layout Guidelines
Attention to good layout practices is always recommended. For best operational performance of the device, use
good PCB layout practices, including:
•
Care must be taken to assure that both input paths are well-matched for source impedance and capacitance
to avoid converting common-mode signals into differential signals. In addition, parasitic capacitance at the
gain-setting pins can also affect CMRR over frequency. For example, in applications that implement gain
switching using switches or PhotoMOS® relays to change the value of RG, select the component so that the
switch capacitance is as small as possible.
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of the device
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources
local to the analog circuitry.
–
Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
•
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better than in
parallel with the noisy trace.
•
•
Place the external components as close to the device as possible. As illustrated in 图 74, keeping RG close to
the pins minimizes parasitic capacitance.
Keep the traces as short as possible.
版权 © 2017–2018, Texas Instruments Incorporated
29
INA828
ZHCSGR1A –AUGUST 2017–REVISED JANUARY 2018
www.ti.com.cn
10.2 Layout Example
+V
C2
R2
+IN
-IN
RG
INA828
RG
R3
OUT
R1
C1
Ground plane
removed at gain
-V
resistor to minimize
parasitic capacitance
Use ground pours for
shielding the input
signal pairs
R3
+V
GND
R1
C2
1
2
3
4
RG
RG
8
7
6
5
œIN
+IN
œIN
+IN
-VS
+VS
OUT
REF
Input traces routed
adjacent to each other
OUT
R2
Low-impedance
connection for
reference terminal
GND
C1
Place bypass
capacitors as close to
IC as possible
-V
Copyright © 2017, Texas Instruments Incorporated
图 74. Example Schematic and Associated PCB Layout
30
版权 © 2017–2018, Texas Instruments Incorporated
INA828
www.ti.com.cn
ZHCSGR1A –AUGUST 2017–REVISED JANUARY 2018
11 器件和文档支持
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
•
•
•
•
《REF50xx 低噪声、极低漂移、高精度电压基准》
OPA191 低功耗精密 36V e-trim CMOS 放大器
TINA-TI 软件文件夹
INA 共模范围计算器
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. 有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 Community Resources
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
E2E is a trademark of Texas Instruments.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
PhotoMOS is a registered trademark of Panasonic Electric Works Europe AG.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知和修
订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。
版权 © 2017–2018, Texas Instruments Incorporated
31
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
INA828ID
ACTIVE
ACTIVE
SOIC
SOIC
D
D
8
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
INA828
INA828
INA828IDR
2500 RoHS & Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
INA828IDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC
SPQ
Length (mm) Width (mm) Height (mm)
356.0 356.0 35.0
INA828IDR
D
8
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
SOIC
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
INA828ID
D
8
75
506.6
8
3940
4.32
Pack Materials-Page 3
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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