INA849_V02 [TI]
INA849 Ultra-Low-Noise (1 nV/âHz), High-Bandwidth, Instrumentation Amplifier;
| 型号： | INA849_V02 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | INA849 Ultra-Low-Noise (1 nV/âHz), High-Bandwidth, Instrumentation Amplifier |
| 文件： | 总36页 (文件大小：3282K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INA849
SBOS945B – NOVEMBER 2020 – REVISED APRIL 2021
INA849 Ultra-Low-Noise (1 nV/√Hz), High-Bandwidth, Instrumentation Amplifier
1 Features
3 Description
•
Ultra-low noise: 1-nV/√Hz input voltage noise
(typical)
The INA849 is an ultra-low noise instrumentation
amplifier optimized for maximum accuracy in high-
resolution systems and operation over a wide single-
supply or dual-supply range. The device offers
significantly lower input bias current than competitors
as a result of super-beta input transistors. A state-of-
the-art manufacturing process provides exceptionally
low voltage noise, input offset voltage, and offset
voltage drift.
•
Precision super-beta input performance:
– Low offset voltage: 35 µV (maximum)
– Low offset voltage drift: 0.4 μV/°C (maximum)
– Low input bias current: 20 nA (maximum)
– Low gain drift: 5 ppm/°C for G = 1 (maximum)
Bandwidth: 28 MHz (G = 1), 8 MHz (G = 100)
Slew rate: 35 V/µs
Common-mode rejection: 120 dB (minimum) for
maximum gain
Supply range:
– Single supply: 8 V to 36 V
– Dual supply: ±4 V to ±18 V
Specified temperature range:
–40°C to +125°C
Packages: 8-pin SOIC and VSSOP
•
•
•
Precisely matched integrated resistors provide a high,
92-dB (G = 1) common-mode rejection across the full
input common-mode range. A single external resistor
sets any gain from 1 to 10,000. The current-feedback
topology of the INA849 provides wide bandwidth at
higher gains for very-small, fast-moving signals. For
example, the device provides 8 MHz of bandwidth
at G = 100, and 28 MHz at a G = 1, with a fast
0.4-µs settling time (0.01%) for directly driving high-
resolution, analog-to-digital converters (ADCs).
•
•
•
2 Applications
•
•
•
•
•
•
•
•
Analog input module
Microphone preamplifier
Flow transmitter
Battery test
LCD test
Electrocardiogram (ECG)
Surgical equipment
Process analytics (pH, gas, concentration, force
and humidity)
Device Information
PART NUMBER
INA849
PACKAGE(1)
BODY SIZE (NOM)
4.90 mm × 3.91 mm
3.00 mm × 3.00 mm
SOIC (8)
VSSOP (8)
(1) See the package option addendum at the end of the data
sheet for all available packages.
+VS
100 nF
+VS
5 kꢀ
+
5 kꢀ
ÞIN
œ
RG
œ
3 kꢀ
3 kꢀ
OUT
REF
RG
+
VO = G V+IN - V-IN + V
(
)
REF
RG
+IN
œ
+
5 kꢀ
5 kꢀ
ÞVS
100 nF
ÞVS
INA849 Simplified Internal Schematic
Input-Referred Voltage Noise Spectral Density vs
Frequency
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
INA849
www.ti.com
SBOS945B – NOVEMBER 2020 – REVISED APRIL 2021
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings ....................................... 4
7.2 ESD Ratings .............................................................. 4
7.3 Recommended Operating Conditions ........................4
7.4 Thermal Information ...................................................5
7.5 Electrical Characteristics ............................................5
7.6 Typical Characteristics................................................8
8 Detailed Description......................................................16
8.1 Overview...................................................................16
8.2 Functional Block Diagram.........................................16
8.3 Feature Description...................................................17
8.4 Device Functional Modes..........................................18
9 Application and Implementation..................................19
9.1 Application Information............................................. 19
9.2 Typical Application.................................................... 23
10 Power Supply Recommendations..............................25
11 Layout...........................................................................25
11.1 Layout Guidelines................................................... 25
11.2 Layout Example...................................................... 26
12 Device and Documentation Support..........................27
12.1 Documentation Support.......................................... 27
12.2 Receiving Notification of Documentation Updates..27
12.3 Support Resources................................................. 27
12.4 Trademarks.............................................................27
12.5 Electrostatic Discharge Caution..............................27
12.6 Glossary..................................................................27
13 Mechanical, Packaging, and Orderable
Information.................................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (December 2020) to Revision B (April 2021)
Page
•
•
•
•
•
•
•
•
Changed DGK (VSSOP-8) package from advanced information (preview) to production data (active) ............1
Changed typical value of current noise from 1.6 pA/√Hz to 1.1 pA/√(Hz).......................................................... 5
Added note 9...................................................................................................................................................... 5
Changed Figure 7-25, Current Noise Spectral Density vs Frequency (RTI) ......................................................8
Changed Figure 7-42, Total Harmonic Distortion vs Frequency ........................................................................8
Changed Figure 7-43, Total Harmonic Distortion vs Frequency at Different Loads ...........................................8
Changed Figure 7-44, Second Harmonic Distortion vs Frequency ................................................................... 8
Changed Figure 7-45, Third Harmonic Distortion vs Frequency ....................................................................... 8
Changes from Revision * (November 2020) to Revision A (December 2020)
Page
Changed INA849 device from advanced information (preview) to production data (active)...............................1
Added preview DGK package and associated content.......................................................................................1
•
•
Copyright © 2021 Texas Instruments Incorporated
2
Submit Document Feedback
Product Folder Links: INA849
INA849
www.ti.com
SBOS945B – NOVEMBER 2020 – REVISED APRIL 2021
5 Device Comparison Table
DEVICE
DESCRIPTION
GAIN EQUATION
RG PINS AT PIN
INA159
INA819
G = 0.2 V differential amplifier for ±10-V to 3-V and 5-V conversion
G = 0.2 V/V
N/A
35-µV offset, 0.4-µV/°C VOS drift, 8-nV/√Hz noise, low-power, precision
instrumentation amplifier
G = 1 + 50 kΩ / RG
G = 1 + 50 kΩ / RG
G = 1 + 49.4 kΩ / RG
G = 1 + 50 kΩ / RG
G = 1 + 100 kΩ / RG
G = 2000 V/V
2, 3
1, 8
2, 3
1, 8
1, 8
N/A
35-µV offset, 0.4-µV/°C VOS drift, 8-nV/√Hz noise, low-power, precision
instrumentation amplifier
INA818
INA821
INA828
INA333
INA848
35-µV offset, 0.4-µV/°C VOS drift, 7-nV/√Hz noise, high-bandwidth,
precision instrumentation amplifier
50-µV offset, 0.5-µV/°C VOS drift, 7-nV/√Hz noise, low-power, precision
instrumentation amplifier
25-µV VOS, 0.1-µV/°C VOS drift, 1.8-V to 5-V, RRO, 50-µA IQ, chopper-
stabilized INA
Ultra-low-noise (1.5-nV/√Hz), high-bandwidth instrumentation amplifier with
fixed gain of 2000
Zero-drift, high-voltage programmable gain instrumentation amplifier with
signal integrity test capability (overload detection, input switch matrix, wire
break test, SPI with checksum, GPIO ports)
PGA280
PGA112
Digitally programmable
Digitally programmable
N/A
N/A
Precision programmable gain op amp with SPI
6 Pin Configuration and Functions
œIN
RG
RG
+IN
1
2
3
4
8
7
6
5
+VS
OUT
REF
œVS
Not to scale
Figure 6-1. D Package (8-Pin SOIC) and DGK Package (8-Pin VSSOP), Top View
Table 6-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
–IN
NO.
1
I
Negative (inverting) input
Positive (noninverting) input
Output
+IN
4
I
OUT
RG
7
O
—
I
2, 3
6
Gain setting pin. Place a gain resistor between pin 2 and pin 3.
Reference input. This pin must be driven by a low impedance source.
Negative supply
REF
–VS
+VS
5
—
—
8
Positive supply
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: INA849
INA849
www.ti.com
SBOS945B – NOVEMBER 2020 – REVISED APRIL 2021
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
40
UNIT
Single supply, VS = (+VS)
VS
VI
Supply voltage
V
Dual supply, VS = (+VS) – (–VS)
Voltage
±20
(–VS ) – 0.5
–10
(+VS) + 0.5
+10
V
Signal input pins
Current
mA
Gain ≤ 4
–VS
+VS
Signal differential input voltage
4 < Gain < 50
Gain > 50
(–VS) / Gain
–1 V
(+VS) / Gain
+1 V
V
VREF
VO
IS
Reference input voltage
Signal output voltage
Output short-circuit(2)
Operating temperature(3)
Junction temperature(3)
Storage temperature
(–VS ) – 0.5
(–VS) – 0.5
(+VS) + 0.5
(+VS) + 0.5
V
V
Continuous
TA
–40
–40
–65
125
175
150
°C
°C
°C
TJ
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Short-circuit to VS / 2.
(3) As a result of the quiescent current, the supply voltage and load-dependent self-heating of the device must be considered.
7.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
8
MAX
UNIT
V
Single supply, VS = (+VS)
36
VS
TA
Supply voltage
Dual supply, VS = (+VS) – (–VS)
±4
±18
125
Specified temperature
–40
°C
Copyright © 2021 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: INA849
INA849
www.ti.com
SBOS945B – NOVEMBER 2020 – REVISED APRIL 2021
7.4 Thermal Information
INA849
D (SOIC)
8 PINS
119.6
66.3
INA849
DGK (VSSOP)
8 PINS
168.7
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
61.4
61.9
90.0
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
20.5
8.4
ψJB
61.4
88.4
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, connected to ground, VREF = 0 V, VCM = 0 V, and G = 1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT
10
35
75
VOSI
Input stage offset voltage(1) (3)
Input stage offset voltage drift
Output stage offset voltage(1) (3)
Output stage offset voltage drift
µV
µV/°C
µV
TA = –40°C to +125°C(2)
TA = –40°C to +125°C
0.1
50
0.4
500
2000
15
VOSO
TA = –40°C to +125°C(2)
TA = –40°C to +125°C(2)
G = 1, RTI
µV/°C
106
114
121
123
120
120
G = 10, RTI
PSRR
Zin
Power-supply rejection ratio
dB
G = 100, RTI
126
G = 1000, RTI
128
Input impedance
1 || 7
220
GΩ || pF
MHz
RFI filter, –3-dB frequency
(–VS) + 2.5
(+VS) – 2.5
VCM
Operating input range(4)
V
VS = ±4 V to ±18 V
See Figure 8-2 and Figure 8-3
At dc to 60 Hz, RTI,
VCM = (V–) + 2.5 V to (V+) – 2.5 V,
G = 1
92
112
120
120
110
125
127
127
At dc to 60 Hz, RTI,
VCM = (V–) + 2.5 V to (V+) – 2.5 V,
G = 10
CMRR
Common-mode rejection ratio
dB
At dc to 60 Hz, RTI,
VCM = (V–) + 2.5 V to (V+) – 2.5 V,
G = 100
At dc to 60 Hz, RTI,
VCM = (V–) + 2.5 V to (V+) – 2.5 V,
G = 1000
BIAS CURRENT
Input bias current
VCM = VS / 2
20
80
6
nA
pA/°C
nA
IB
Input bias current drift
Input offset current
TA = –40°C to +125°C
VCM = VS / 2
10
5
IOS
Input offset current drift
TA = –40°C to +125°C
pA/°C
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: INA849
INA849
www.ti.com
SBOS945B – NOVEMBER 2020 – REVISED APRIL 2021
7.5 Electrical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, connected to ground, VREF = 0 V, VCM = 0 V, and G = 1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
NOISE VOLTAGE
f = 1 kHz, G = 1000,
RS = 0 Ω
1
nV/√Hz
eNI
Input stage voltage noise(8)
fB = 0.1 Hz to 10 Hz, G = 1000,
RS = 0 Ω
0.06
45
5
µVPP
nV/√Hz
µVPP
f = 1 kHz, RS = 0 Ω
eNO
Output stage voltage noise(8)
Current noise
fB = 0.1 Hz to 10 Hz,
RS = 0 Ω
f = 1 kHz(9)
1.1
pA/√Hz
pAPP
iN
fB = 0.1 Hz to 10 Hz
100
GAIN
G
Gain equation
Gain
1 + (6 kΩ / RG)
V/V
V/V
1
10000
±0.025
±0.1
G = 1, VO = ±10 V
±0.005
±0.025
±0.025
±0.05
G = 10, VO = ±10 V
GE
Gain error (7)
%
G = 100, VO = ±10 V
±0.1
G = 1000, VO = ±10 V
G = 1, TA = –40°C to +125°C
G > 1, TA = –40°C to +125°C
G = 1, VO = –10 V to +10 V
G = 10(6), VO = –10 V to +10 V
f = 1 kHz, VO = 10 VPP
f = 1 kHz, VO = 10 VPP
f = 1 kHz, VO = 10 VPP
f = 10 kHz, VO = 10 VPP
f = 10 kHz, VO = 10 VPP
f = 10 kHz, VO = 10 VPP
±5
Gain error drift(5)
Gain nonlinearity
ppm/°C
ppm
±35
3
10
THD
Total harmonic distortion
127
127
157
119
130
120
dBc
dBc
dBc
dBc
dBc
dBc
HD2
Second-order harmonic distortion
Third-order harmonic distortion
Total harmonic distortion
HD3
THD
HD2
Second-order harmonic distortion
Third-order harmonic distortion
HD3
OUTPUT
Voltage swing
RL = 10 kΩ
(V–) + 0.15
(V+) – 0.15
V
pF
Ω
Load capacitance stability
Closed-loop output impedance
Short-circuit current
200
1.5
ZO
f = 1 MHz
ISC
Continuous to VS / 2
±34
mA
FREQUENCY RESPONSE
G = 1
28
13
G = 10
BW
SR
Bandwidth, –3 dB
Slew rate
MHz
V/µs
G = 100
8
G = 1000
G = 1, VSTEP = 10 V
1.25
35
0.01%, G = 1 to 100,
VSTEP = 10 V
0.4
0.4
0.6
1.5
0.01%, G = 1000,
VSTEP = 10 V
tS
Settling time
µs
0.001%, G = 1 to 100,
VSTEP = 10 V
0.001%, G = 1000,
VSTEP = 10 V
Copyright © 2021 Texas Instruments Incorporated
6
Submit Document Feedback
Product Folder Links: INA849
INA849
www.ti.com
SBOS945B – NOVEMBER 2020 – REVISED APRIL 2021
7.5 Electrical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, connected to ground, VREF = 0 V, VCM = 0 V, and G = 1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
REFERENCE INPUT
RIN
Input impedance
Input current
10
80
kΩ
µA
V
Reference input voltage
Gain to output
(V–)
(V+)
0.05
1
V/V
VO = ±10 V, inside the voltage swing
range
Reference gain error
0.01
%
POWER SUPPLY
IQ
Quiescent current (7)
VIN = 0 V
6.2
6.6
8.9
mA
TA = –40°C to +125°C
(1) Total offset, referred-to-input (RTI): VOS = (VOSI) + (VOSO / G).
(2) Specified by characterization. Not tested in production.
(3) Offset drifts are uncorrelated. Input-referred offset drift is calculated using: ΔVOS(RTI) = √[ΔVOSI 2 + (ΔVOSO / G)2].
(4) Input voltage range of the input stage. The input range depends on the common-mode voltage, differential voltage, gain, and reference
voltage; see Figure 7-12.
(5) The values specified for G > 1 do not include the effects of the external gain resistor, RG.
(6) Thermal effects can degrade input stage nonlinearity and thus can scale with gain; See Figure 9-5.
(7) This parameter is tested in a high speed automatic test environment and does not measure the thermal effects with a longer a time
constant. The thermal effect depends on supply voltage, layout, heat sinking and air flow conditions.
(8) Total RTI voltage noise is equal to: eN(RTI) = √[eNI 2 + (eNO / G)2].
(9) Input current noise density specified for unbalanced input impedance. Bias current cancellation improves noise performance for
balanced systems; See Figure 7-25.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: INA849
INA849
www.ti.com
SBOS945B – NOVEMBER 2020 – REVISED APRIL 2021
7.6 Typical Characteristics
at TA = 25°C, VS = ±15 V, VCM at mid-supply, VRL = 10 kΩ, connected to ground, VREF = 0 V, and G = 1 (unless otherwise
noted)
N = 1695, mean = 0.26 µV, std dev = 5.85 µV
N = 30, mean = 0.10 µV/°C, std dev = 0.08 µV/°C
Figure 7-1. Typical Distribution of Input Offset Voltage
Figure 7-2. Typical Distribution of Input Offset Voltage Drift
N = 1695, mean = -43.83 µV, std dev = 111.74 µV
N = 120, mean = -4.14 µV/°C, std dev = 2.00 µV/°C
Figure 7-3. Typical Distribution of Output Offset Voltage
Figure 7-4. Typical Distribution of Output Offset Voltage Drift
N = 120, mean = 7.58 nA, std dev = 1.84 nA
N = 120, mean = 7.24 nA, std dev = 1.80 nA
Figure 7-5. Typical Distribution of Input Bias Current
Figure 7-6. Typical Distribution of Input Bias Current at 85°C
Copyright © 2021 Texas Instruments Incorporated
8
Submit Document Feedback
Product Folder Links: INA849
INA849
www.ti.com
SBOS945B – NOVEMBER 2020 – REVISED APRIL 2021
7.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, VCM at mid-supply, VRL = 10 kΩ, connected to ground, VREF = 0 V, and G = 1 (unless otherwise
noted)
N = 120, mean = -0.11 nA, std dev = 1.01 nA
N = 120, mean = 3.08 µV/V, std dev = 5.57 µV/V
Figure 7-7. Typical Distribution of Input Offset Current
Figure 7-8. Typical CMRR Distribution G = 1
N = 120, mean = -0.375 µV/V, std dev = 0.043 µV/V
N = 120
Figure 7-9. Typical CMRR Distribution G = 100
Figure 7-10. Input Stage Offset Voltage vs Temperature
N = 120
VREF = 0 V
Figure 7-11. Output Stage Offset Voltage vs Temperature
Figure 7-12. Boundary Plot - Input Common-Mode Voltage vs
Output Voltage
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: INA849
INA849
www.ti.com
SBOS945B – NOVEMBER 2020 – REVISED APRIL 2021
7.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, VCM at mid-supply, VRL = 10 kΩ, connected to ground, VREF = 0 V, and G = 1 (unless otherwise
noted)
Figure 7-13. Output-referred Offset Voltage vs Negative Input
Common-Mode Voltage
Figure 7-14. Output-referred Offset Voltage vs Positive Input
Common-Mode Voltage
Figure 7-15. Positive Input Bias Current vs Input Common-
Mode Voltage
Figure 7-16. Negative Input Bias Current vs Input Common-
Mode Voltage
Figure 7-17. Input Offset Current vs Input Common-Mode
Voltage
Figure 7-18. Input Bias Current vs Temperature
Copyright © 2021 Texas Instruments Incorporated
10
Submit Document Feedback
Product Folder Links: INA849
INA849
www.ti.com
SBOS945B – NOVEMBER 2020 – REVISED APRIL 2021
7.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, VCM at mid-supply, VRL = 10 kΩ, connected to ground, VREF = 0 V, and G = 1 (unless otherwise
noted)
Figure 7-19. Input Offset Current vs Temperature
Figure 7-20. CMRR vs Frequency (RTI)
Figure 7-21. CMRR vs Frequency (1-kΩ source imbalance)
Figure 7-22. Positive PSRR vs Frequency (RTI)
Figure 7-23. Negative PSRR vs Frequency (RTI)
Figure 7-24. Voltage Noise Spectral Density vs Frequency (RTI)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: INA849
INA849
www.ti.com
SBOS945B – NOVEMBER 2020 – REVISED APRIL 2021
7.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, VCM at mid-supply, VRL = 10 kΩ, connected to ground, VREF = 0 V, and G = 1 (unless otherwise
noted)
G = 1
Figure 7-26. 0.1-Hz to 10-Hz RTI Voltage Noise
Figure 7-25. Current Noise Spectral Density vs Frequency (RTI)
G = 1000
Figure 7-27. 0.1-Hz to 10-Hz RTI Voltage Noise
Figure 7-28. 0.1-Hz to 10-Hz RTI Current Noise
G = 1
G = 10
Figure 7-29. Gain Nonlinearity vs Output Voltage
Figure 7-30. Gain Nonlinearity vs Output Voltage
Copyright © 2021 Texas Instruments Incorporated
12
Submit Document Feedback
Product Folder Links: INA849
INA849
www.ti.com
SBOS945B – NOVEMBER 2020 – REVISED APRIL 2021
7.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, VCM at mid-supply, VRL = 10 kΩ, connected to ground, VREF = 0 V, and G = 1 (unless otherwise
noted)
Figure 7-31. Closed-Loop Gain vs Frequency
Figure 7-32. Closed-Loop Output Impedance vs Frequency
Figure 7-33. Large-Signal Frequency Response
Figure 7-34. Overshoot vs Capacitive Loads
G = 1, CL = 100 pF
G = 10, CL = 100 pF
Figure 7-35. Small-Signal Step Response at G = 1
Figure 7-36. Small-Signal Step Response at G = 10
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: INA849
INA849
www.ti.com
SBOS945B – NOVEMBER 2020 – REVISED APRIL 2021
7.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, VCM at mid-supply, VRL = 10 kΩ, connected to ground, VREF = 0 V, and G = 1 (unless otherwise
noted)
G = 100, CL = 100 pF
G = 1000, CL = 100 pF
Figure 7-37. Small-Signal Step Response at G = 100
Figure 7-38. Small-Signal Step Response at G = 1000
G = 1
VSTEP = 10 V
G = 100
VSTEP = 10 V
Figure 7-39. Settling Time for G = 1
Figure 7-40. Settling Time for G = 100
G = 1000
VSTEP = 10 V
Figure 7-41. Settling Time for G = 1000
Figure 7-42. Total Harmonic Distortion vs Frequency
Copyright © 2021 Texas Instruments Incorporated
14
Submit Document Feedback
Product Folder Links: INA849
INA849
www.ti.com
SBOS945B – NOVEMBER 2020 – REVISED APRIL 2021
7.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, VCM at mid-supply, VRL = 10 kΩ, connected to ground, VREF = 0 V, and G = 1 (unless otherwise
noted)
0.001
-100
-120
-140
HD2 (%), G = 1
HD2 (%), G = 10
0.0001
0.00001
20
200
2k
20k
Frequency (Hz)
Figure 7-44. Second Harmonic Distortion vs Frequency
Figure 7-43. Total Harmonic Distortion vs Frequency at
Different Loads
0.001
-100
-120
-140
-160
HD3 (%), G = 1
HD3 (%), G = 10
0.0001
0.00001
0.000001
20
200
2k
20k
Frequency (Hz)
Figure 7-45. Third Harmonic Distortion vs Frequency
Figure 7-46. Supply Current vs Temperature
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: INA849
INA849
www.ti.com
SBOS945B – NOVEMBER 2020 – REVISED APRIL 2021
8 Detailed Description
8.1 Overview
The INA849 is a monolithic, precision, instrumentation amplifier that incorporates a current-feedback input stage
and a four-resistor difference amplifier output stage. The functional block diagram in the next section shows how
the differential input voltage is buffered by Q1 and Q2, and is forced across RG, which causes a signal current to
flow through RG, R1, and R2. The output difference amplifier, A3, removes the common-mode component of the
input signal and refers the output signal to the REF pin. The VBE and voltage drop across R1 and R2 produce
output voltages on A1 and A2 that are approximately 0.8 V lower than the input voltages.
8.2 Functional Block Diagram
+VS
VB
RB
RB
IB Cancellation
IB Cancellation
R5
5 kꢀ
ÞVS +VS
R3
5 kꢀ
œ
A1
A2
C1
A3
+
OUT
REF
C2
R4
5 kꢀ
R6
5 kꢀ
+VS
+VS
+VS
ÞVS
Q2
Q1
Super-ꢁ
NPN
Super-ꢁ
NPN
+IN
ÞIN
+VS
+VS
R2
3 kꢀ
R1
3 kꢀ
ÞVS
ÞVS
RG
RG
RG
ÞVS
ÞVS
Copyright © 2021 Texas Instruments Incorporated
16
Submit Document Feedback
Product Folder Links: INA849
INA849
www.ti.com
SBOS945B – NOVEMBER 2020 – REVISED APRIL 2021
8.3 Feature Description
8.3.1 Adjustable Gain Setting
Figure 8-1 shows that the gain of the INA849 is set by a single external resistor (RG) connected between the RG
pins (pins 2 and 3).
+VS
100 nF
+VS
5 kꢀ
+
5 kꢀ
ÞIN
œ
RG
œ
3 kꢀ
3 kꢀ
OUT
REF
RG
+
VO = G V+IN - V-IN + V
(
)
REF
RG
+IN
œ
+
5 kꢀ
5 kꢀ
ÞVS
100 nF
ÞVS
Figure 8-1. Simplified Diagram of the INA849 with Output Equation
The value of RG is selected according to the following equation:
6 kΩ
G = 1+
RG
(1)
Table 8-1 lists several commonly used gains and resistor values. The 6-kΩ term in Equation 1 is a result of the
sum of the two internal 3-kΩ feedback resistors. These on-chip resistors are laser-trimmed to accurate, absolute
values. The accuracy and temperature coefficients of these resistors are included in the gain accuracy and drift
specifications of the INA849.
Table 8-1. Commonly Used Gains and Resistor Values
CALCULATED GAIN
(V/V)
CALCULATED GAIN
ERROR (%)
DESIRED GAIN (V/V)
STANDARD 1% RG (Ω)
1
2
Not connected
6.04 k
1.50 k
665
N/A
N/A
0.33
0
1.9933
5
5
10
10.022
19.987
50.586
100.337
200.335
496.867
994.377
–0.23
0.06
–1.17
–0.34
–0.17
0.63
0.56
20
316
50
121
100
200
500
1000
60.4
30.1
12.1
6.04
The 5-kΩ feedback resistors in the output stage are ratiometrically matched to achieve unity-gain stability. These
resistors may shift up to 15% depending on production.
As shown in Figure 8-1 and explained in more detail in Figure 11-1, make sure to connect low-ESR, 0.1-µF,
ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: INA849
INA849
www.ti.com
SBOS945B – NOVEMBER 2020 – REVISED APRIL 2021
8.3.2 Gain Drift
The stability and temperature drift of external gain setting resistor RG also affects gain. The contribution of RG to
gain accuracy and drift is determined from Equation 1.
The best gain drift of 5 ppm/℃ (maximum) is achieved when the INA849 uses G = 1 without RG connected. In
this case, gain drift is limited by the mismatch of the temperature coefficient of the integrated 5-kΩ resistors in
differential amplifier A3. At gains greater than 1, gain drift increases as a result of the individual drift of the 3-kΩ
resistors in the feedback of A1 and A2, relative to the drift of external gain resistor RG.
The low temperature coefficient of the internal feedback resistors improves the overall temperature stability of
applications using gains greater than 1 V/V over alternate solutions.
The low resistor values required for high gain make wiring resistance an important consideration. Sockets add
to the wiring resistance and contribute additional gain error (such as a possible unstable gain error) at gains of
approximately 100 or greater.
To maintain stability, avoid parasitic capacitance of more than a few picofarads at the RG connections. Careful
matching of any parasitics on the RG pins maintains optimal CMRR over frequency.
8.3.3 Wide Input Common-Mode Range
The linear input voltage range of the INA849 input circuitry extends within 2.5 V (maximum) of both power
supplies, and maintains excellent common-mode rejection throughout this range. The common-mode range
for the most common operating conditions are shown in Figure 8-2 and Figure 8-3. The common-mode
range for other operating conditions is best calculated using the Common-Mode Input Range Calculator for
Instrumentation Amplifiers.
VS = ±5 V, ±12 V, ±18 V
G = 1
VS = ±5 V, ±12 V, ±18 V
G = 100
Figure 8-2. Input Common-Mode Voltage vs Output Figure 8-3. Input Common-Mode Voltage vs Output
Voltage
Voltage
8.4 Device Functional Modes
The INA849 has a single functional mode and is operational when the power-supply voltage is greater than 8 V
(±4 V). The maximum power-supply voltage for the INA849 is 36 V (±18 V).
Copyright © 2021 Texas Instruments Incorporated
18
Submit Document Feedback
Product Folder Links: INA849
INA849
www.ti.com
SBOS945B – NOVEMBER 2020 – REVISED APRIL 2021
9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
9.1.1 Reference Pin
The output voltage of the INA849 is developed with respect to the voltage on reference pin REF.
Use the REF pin to offset the output signal to a precise midsupply level. Typically, this offset is 2.5 V in a
5-V supply environment. To accomplish this level shift, a voltage source must be connected to the REF pin to
level-shift the output so that the INA849 drives a single-supply analog-to-digital converter (ADC).
For dual-supply operation, the reference pin is typically connected to the low-impedance system ground.
The voltage source applied to the reference pin must have a low output impedance. As shown in Figure 9-1,
any resistance at the reference pin (shown as RREF) is in series with an internal 5-kΩ resistor that creates an
imbalance in the four resistors of the internal difference amplifier.
+VS
C2
+VS
5 kꢀ
+
5 kꢀ
ÞIN
œ
ÞRG
œ
3 kꢀ
3 kꢀ
OUT
RG
+
C3
R2
+RG
+IN
œ
REF
+
5 kꢀ
5 kꢀ
R1
ÞVS
C1
ÞVS
Figure 9-1. Parasitic Resistance Shown at the Reference Pin
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
19
Product Folder Links: INA849
INA849
www.ti.com
SBOS945B – NOVEMBER 2020 – REVISED APRIL 2021
This imbalance results in a degraded common-mode rejection ratio (CMRR). Figure 9-2 shows how the
common-mode rejection ratio degrades depending on the source resistance on the reference pin. For best
performance, keep the dc CMRR greater than 100 dB by keeping the source impedance to the REF pin
(represented as R1) to less than 0.1 Ω.
Figure 9-2. Effect of Parasitic Resistance at the Reference Pin
Voltage-reference devices are an excellent option for providing a low-impedance voltage source for the
reference pin. However, if a resistor voltage divider generates a reference voltage, the divider must be buffered
by an op amp (as Figure 9-3 shows) to avoid CMRR degradation.
5 V
INA849
+IN
+
OUT
œ
ÞIN
5 V
REF
Þ5 V
5 V
100 kꢀ
100 kꢀ
œ
+
OPA320
1 …F
Figure 9-3. Using an Op Amp to Buffer Reference Voltages
Copyright © 2021 Texas Instruments Incorporated
20
Submit Document Feedback
Product Folder Links: INA849
INA849
www.ti.com
SBOS945B – NOVEMBER 2020 – REVISED APRIL 2021
9.1.2 Input Bias Current Return Path
The input impedance of the INA849 is extremely high (approximately 100 GΩ). However, a path must be
provided for the input bias current of both inputs. This input bias current is typically 6 nA. High input impedance
means that this input bias current changes little with varying input voltage.
Input circuitry must provide a path for this input bias current for proper operation. Figure 9-4 shows various
provisions for an input bias current path. Without a bias current path, the inputs float to a potential that exceeds
the common-mode range of the INA849, and the input amplifiers saturate. If the differential source resistance is
low, the bias current return path connects to one input (as shown in the thermocouple example). With a higher
source impedance, using two equal resistors provides a balanced input with possible advantages of a lower
input offset voltage as a result of bias current, and better high-frequency common-mode rejection.
C1
+VS
R1
AC Coupling
INA849
REF
+
C2
œ
R2
Þ VS
+VS
INA849
REF
+
Microphone,
Hydrophone,
and more
L1
œ
Þ VS
R3
R4
+VS
+
INA849
REF
Thermocouple
œ
R5
10 kΩ
Þ VS
+VS
+
INA849
REF
T1
Transformer
œ
Þ VS
NOTE: Center tap in the transformer provides bias current return.
Figure 9-4. Providing an Input Common-Mode Current Path
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: INA849
INA849
www.ti.com
SBOS945B – NOVEMBER 2020 – REVISED APRIL 2021
9.1.3 Thermal Effects due to Power Dissipation
The INA849 dissipates approximately 200 mW of power under quiescent conditions at a ±15-V supply voltage.
The internal resistor network and output load drive causes an additional power dissipation that depends on
the input signal. The small silicon area of the INA849 causes the internal circuitry to experience temperature
gradients that might adversely affect the electrical performance.
Precision parameters, such as offset voltage, linearity, common-mode rejection ratio, and total harmonic
distortion, can be impacted as a result of these thermal effects in the silicon. The thermal gradient particularly
affects the performance of low-frequency input signals with higher gains (> 10) and large output voltage
variation. As shown in the measurement Figure 9-5, the thermal effect can be minimized by lowering the supply
voltage, if the application permits.
Figure 9-5. Linearity vs Supply Voltage for G = 1000
Copyright © 2021 Texas Instruments Incorporated
22
Submit Document Feedback
Product Folder Links: INA849
INA849
www.ti.com
SBOS945B – NOVEMBER 2020 – REVISED APRIL 2021
9.2 Typical Application
9.2.1 Sensor Conditioning Circuit
Figure 9-6 shows a typical application for the INA849.
+VS
C4
0.1 …F
+IN
R1
1 kꢀ
C2
470 pF
+
RG
INA849
RG
C3
47 pF
RG
C1
470 pF
REF
R6
10 kꢀ
œ
ÞIN
5 V
C3
0.1 …F
R2
1 kꢀ
+VS
R4
100 kꢀ
œ
ÞVS
+
C7
100 pF
OPA192
R5
100 kꢀ
C6
0.1 …F
ÞVS
Figure 9-6. Sensor Conditioning Circuit
9.2.1.1 Design Requirements
For the typical application, the design requirements are:
•
•
Power-supply voltage of VS = ± 15 V
AC-coupled input signal
– Capacitor tolerance of 5%
•
•
•
Reference voltage buffered to VREF = 2.5 V
Output range within 0 V to 5 V
First-order filter stage with ‒3-dB frequency of 27 kHz
9.2.1.2 Detailed Design Procedure
If the instrumentation amplifier is used to drive ac-coupled input signals, an input bias current path must be
provided as described in Section 9.1.2, represented with resistors R1 and R2 in Figure 9-6. For the selection of
the resistor value, a trade-off must be made between input current noise that increases at lower values and input
voltage noise that increases at higher values.
Section 9.1.1 states that the reference pin must be connected to a low-impedance reference, as shown in the
application circuit example of the Sensor Conditioning Circuit. The reference pin must be connected to a 2.5-V
reference voltage established through a high-resistive divider. The OPA192 helps to buffer the reference voltage.
The effective output impedance of the OPA192 is derived as follows. The dc open-loop impedance of the
OPA192 amplifier is approximately 3 kΩ. In a buffer configuration (AV = 1), the output impedance of an amplifier
degrades by the open-loop voltage gain. The OPA192 specifies a typical AOL of 126 dB, thereby resulting in an
output impedance of ROUT = 1.5 mΩ.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
23
Product Folder Links: INA849
INA849
www.ti.com
SBOS945B – NOVEMBER 2020 – REVISED APRIL 2021
9.2.2 Phantom Power in Microphone Preamplifier Circuit
R3
48-V
47 k
GND
VS
R2
6.2 k
R1
6.2 k
C6
0.1 μF
C3
47 µF
+VS
IN+
R4
3 k
+
RG
R6
2 k
+VS
GND
INA849
R7
VOUT
RG
C4
47 µF
3 k
R5
–
REF
IN
VS
0.1 μF
C5
VS
Figure 9-7. Phantom Power in Microphone Preamplifier Circuit
Figure 9-7 shows a typical application circuit for a microphone input amplifier used to generate phantom power.
Phantom power is a technique that provides power and the audio signal using the same signal path.
R1 and R2 connected to the 48-V supply define the current path in the case when the microphone must
be powered. Therefore, C3 and C4 are used as blocking capacitors to protect the INA849. When the input
connections are shorted In a fault scenario, a large surge current discharges the dc blocking capacitor through
the Shottky diodes. For 48-V phantom power, the surge current exceeds 4 A for a short duration of time. Make
sure to use Shottky diodes that are specified for at least a 10-A surge current. Additional series resistance with
the dc blocking capacitor limits the surge current, but must be traded off because these add noise to the circuit.
One of the key criteria for high-performance microphones is to enable an optimum source impedance throughout
the audible frequency range. The exceptional ultra-low noise performance of the INA849 permits direct input
without the need for a transformer.
R4 and R5 in parallel with R1 and R2 provide the bias current path for the INA849. The input bias current
(maximum of 20 nA) provides a dc differential input voltage that reflects as an voltage error on the output. Use
the lowest possible value resistors to make sure that the thermal noise of these resistors does not dominate.
The mismatch of the input ac-coupling capacitors (C3 and C4) can reduce the common-mode rejection ratio
significantly at low frequencies. An additional resistor (R6) connected to both of the bias resistors (R4 and R5)
can mitigate this effect.
Use the TINA TI™ simulation software for a detailed analysis.
Copyright © 2021 Texas Instruments Incorporated
24
Submit Document Feedback
Product Folder Links: INA849
INA849
www.ti.com
SBOS945B – NOVEMBER 2020 – REVISED APRIL 2021
10 Power Supply Recommendations
The nominal performance of the INA849 is specified with a supply voltage of ±15 V and midsupply reference
voltage. The device also operates using power supplies from ±4 V (8 V) to ±18 V (36 V) and non-midsupply
reference voltages with excellent performance. Section 7.6 shows the parameters that can vary significantly with
operating voltage and reference voltage.
11 Layout
11.1 Layout Guidelines
Use good PCB layout practices for best operational performance of the device, including:
•
To avoid converting common-mode signals into differential signals and thermal electromotive forces (EMFs),
make sure that both input paths are symmetrical and well-matched for source impedance and capacitance.
Place the external gain resistor close to the RG pins to keep the loop inductance as low as possible and
to avoid a potential parasitic coupling path, but also so that capacitance mismatch between the RG pins is
minimized.
•
•
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of the device.
Bypass capacitors reduce the coupled noise by providing low-impedance power sources local to the analog
circuitry.
– Connect low-ESR, 0.1-µF, ceramic bypass capacitors between each supply pin and ground, placed as
close as possible to the device.
– A single bypass capacitor from V+ to ground is applicable for single-supply applications.
To reduce parasitic coupling, run the input traces as far away as possible from the supply or output traces.
If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better than in
parallel with the noisy trace.
•
•
•
Keep traces as short as possible.
Minimize the number of thermal junctions. Ideally, the signal path is routed within a single layer without vias.
Keep sufficient distance from major thermal energy sources (circuits with high power dissipation). If not
possible, place the device such that it matches the thermal energy source on the differential signal path.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
25
Product Folder Links: INA849
INA849
www.ti.com
SBOS945B – NOVEMBER 2020 – REVISED APRIL 2021
11.2 Layout Example
+V
C2
R2
+IN
RG
INA849
R3
OUT
RG
ÞIN
R1
C1
ÞV
+V
Use ground pours for
shielding the input
signal pairs
Place bypass
capacitors as close to
IC as possible
GND
C2
R1
œIN
1
2
3
4
œIN
RG
RG
+IN
+VS
OUT
REF
ÞVS
8
7
6
5
OUT
R3
Low-impedance
connection for
reference terminal
+IN
R2
GND
C1
REF
ÞV
Figure 11-1. Example Schematic and Associated PCB Layout
Copyright © 2021 Texas Instruments Incorporated
26
Submit Document Feedback
Product Folder Links: INA849
INA849
www.ti.com
SBOS945B – NOVEMBER 2020 – REVISED APRIL 2021
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
•
Texas Instruments, Comprehensive Error Calculation for Instrumentation Amplifiers application note
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TINA TI™ and TI E2E™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
27
Product Folder Links: INA849
PACKAGE OPTION ADDENDUM
www.ti.com
12-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
INA849DGKR
INA849DGKT
INA849DR
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
2ENJ
2ENJ
NIPDAU
NIPDAU
INA849
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
12-Aug-2021
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Jul-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
INA849DGKR
INA849DGKT
INA849DR
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
2500
250
330.0
180.0
330.0
12.4
12.4
12.4
5.3
5.3
6.4
3.4
3.4
5.2
1.4
1.4
2.1
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
2500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Jul-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
INA849DGKR
INA849DGKT
INA849DR
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
2500
250
853.0
210.0
853.0
449.0
185.0
449.0
35.0
35.0
35.0
2500
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,
costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either
on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s
applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
相关型号：
INA851RGTR
Low-noise (3.2 nV/√Hz) high-speed (22 MHz) fully-differential instrumentation amp with OVP (±40 V) | RGT | 16 | -40 to 125
TI
INA851RGTT
Low-noise (3.2 nV/√Hz) high-speed (22 MHz) fully-differential instrumentation amp with OVP (±40 V) | RGT | 16 | -40 to 125
TI
©2020 ICPDF网 联系我们和版权申明