INA851 [TI]
具有低噪声 (3.2nV/√Hz)、高速 (22MHz) 和 OVP (±40V) 的全差分仪表放大器;
| 型号： | INA851 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有低噪声 (3.2nV/√Hz)、高速 (22MHz) 和 OVP (±40V) 的全差分仪表放大器 放大器 仪表 仪表放大器 |
| 文件： | 总53页 (文件大小：3828K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INA851
ZHCSQ83A –MARCH 2022 –REVISED OCTOBER 2022
INA851 具有衰减增益和输出钳位的低噪声、全差分输出精密仪表放大器
1 特性
3 说明
• 可使用外部电阻器
在G = 0.2 至10,000 的范围内对增益进行编程
• 具有集成钳位的全差分输出
• 低失调电压：10 µV（典型值），35 µV（最大值）
• 低温漂：0.1 µV/°C（典型值），0.3 µV/°C（最大
值）
INA851 是业内首款具有全差分输出的高精度仪表放大
器。该器件经过优化，可驱动具有全差分输入的现代高
性能模数转换器 (ADC) 的输入。INA851 可在非常宽的
单电源或双电源电压范围内运行。可通过短接或悬空两
个引脚，将输出级增益设置为 0.2 或 1。可通过单个外
部电阻器在1 到10,000 范围内设置任意输入级增益。
• 低输入偏置电流：5 nA（典型值）
• 输入级噪声：3.2 nV/√Hz、0.8 pA/√Hz
• 高带宽：在G = 0.2 时为22 MHz，
在G = 1 时为15 MHz
• 共模抑制：在G = 10 时为106 dB（最小值），在
100 ≤G ≤1000 时为120 dB（最小值）
• 电源抑制：在G = 1 时为110 dB（最小值）
• 电源电流：6mA（典型值）
INA851 采用了超级 ß 输入晶体管，因此与同一级别的
其他放大器相比，可提供极低的输入偏置电流和低输入
参考电流噪声。先进的制造工艺实现了极低的电压噪
声、输入失调电压和失调电压漂移。附加电路可保护器
件输入免受超过电源电压多达±40V 的过压影响。器件
输出具有内置钳位电路，可保护 ADC 或下游器件免受
过驱损坏。
该器件可在单电源（最小 8V，最大 36V）或双电源
（最小±4V，最大±18V）供电的情况下运行。
• 在超过电源电压多达±40V 时提供输入过压保护
• 电源电压范围：
– 单电源：8V 至36V
– 双电源：±4V 至±18V
• 额定温度范围：–40°C 至+125°C
• 微型封装：16 引脚VQFN
封装信息
封装(1)
封装尺寸（标称值）
器件型号
INA851
RGT（VQFN，
16）
3.00mm × 3.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
2 应用
• 模拟输入模块
• 流量变送器
• LCD 测试
• 心电图(ECG)
• 外科手术设备
• 示波器(DSO)
• 称重计
• 半导体测试
VS+
14
5 V
VS+
INA851
16
15
VCLAMP+
FDA_IN
LDO
6 k
RG
1
2
IN
Overvoltage
Protection
GIN
= 1 +
+
–
VIN
G02+(1) 12
R7
RG
GOUT = 0.2 or 1
1.25 k
R5
G = GIN * GOUT
R2
3 k
R3
VDD
ADC
VSS
5 k
5 k
INP
INN
OUT+ 11
OUT 10
–
+
+
–
RG
R1
5 k
R4
R6
3 k
5 k
R8
3
4
RG+
IN+
–
+
(1)
G02
9
6
5
Overvoltage
Protection
1.25 k
VIN+
FDA_IN+
VCLAMP
LDO
VS
VOCM
7
13
VOCM
(1)
Short OUT to G02 and OUT+ to G02+ for
output stage G = 0.2 option.
VS
INA851 ADC 驱动器应用
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS999
INA851
www.ti.com.cn
ZHCSQ83A –MARCH 2022 –REVISED OCTOBER 2022
Table of Contents
8.4 Device Functional Modes..........................................29
9 Application and Implementation..................................30
9.1 Application Information............................................. 30
9.2 Typical Applications.................................................. 33
9.3 Power Supply Recommendations.............................41
9.4 Layout....................................................................... 41
10 Device and Documentation Support..........................43
10.1 Device Support....................................................... 43
10.2 Documentation Support.......................................... 43
10.3 接收文档更新通知................................................... 43
10.4 支持资源..................................................................43
10.5 Trademarks.............................................................43
10.6 Electrostatic Discharge Caution..............................44
10.7 术语表..................................................................... 44
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Related Products.............................................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings .............................................................. 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................6
7.5 Electrical Characteristics.............................................6
7.6 Typical Characteristics..............................................10
8 Detailed Description......................................................22
8.1 Overview...................................................................22
8.2 Functional Block Diagram.........................................23
8.3 Feature Description...................................................23
Information.................................................................... 44
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (March 2022) to Revision A (October 2022)
Page
• 将INA851 从预告信息（预发布）更改为量产数据（正在供货）....................................................................... 1
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5 Related Products
DEVICE
DESCRIPTION
GAIN EQUATION
RG PINS AT PIN
INA159
G = 0.2 V differential amplifier for ±10-V to 3-V and 5-V conversion
G = 0.2 V/V
N/A
35-µV offset, 0.4-µV/°C VOS drift, 8-nV/√Hz noise, low-power,
precision instrumentation amplifier
INA818
1, 8
2, 3
2, 3
1, 8
1, 8
G = 1 + 50 kΩ/ RG
G = 1 + 50 kΩ/ RG
G = 1 + 49.4 kΩ/ RG
G = 1 + 50 kΩ/ RG
G = 1 + 100 kΩ/ RG
G = 2000 V/V
35-µV offset, 0.4-µV/°C VOS drift, 8-nV/√Hz noise, low-power,
precision instrumentation amplifier
INA819
INA821
INA828
INA333
35-µV offset, 0.4-µV/°C VOS drift, 7-nV/√Hz noise, high-bandwidth,
precision instrumentation amplifier
50-µV offset, 0.5-µV/°C VOS drift, 7-nV/√Hz noise, low-power,
precision instrumentation amplifier
25-µV VOS, 0.1-µV/°C VOS drift, 1.8-V to 5-V, RRO, 50-µA IQ, chopper-
stabilized INA
Ultra-low-noise (1.5-nV/√Hz), high-bandwidth instrumentation
amplifier with fixed gain of 2000
INA848
INA849
PGA280
N/A
2, 3
N/A
Ultra-low-noise (1-nV/√Hz), high-bandwidth instrumentation amplifier
G = 1 + 6 kΩ/ RG
20-mV to ±10-V programmable gain IA with 3-V or 5-V differential
output; analog supply up to ±18 V
Digital programmable
Precision, zero-drift, programmable gain IA with differential output;
binary gain steps from 1/8 V/V to 128 V/V
PGA281
PGA112
Digital programmable
Digital programmable
N/A
N/A
Precision programmable gain op amp with SPI
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ZHCSQ83A –MARCH 2022 –REVISED OCTOBER 2022
6 Pin Configuration and Functions
IN–
RG
RG
IN+
1
2
3
4
12
11
10
9
G02+
OUT+
OUT–
G02–
Thermal Pad
Not to scale
图6-1. RGT (16-Pin VQFN) Package, Top View
表6-1. Pin Functions
PIN
TYPE
DESCRIPTION
NAME
FDA_IN–
FDA_IN+
G02–
G02+
IN–
NO.
15
6
Input
Input
Input
Input
Input
Input
Connection to output driver summing node.
Connection to output driver summing node.
9
Connection to gain network. Short to OUT–for output stage gain GOUT of 0.2 V/V.
12
1
Connection to gain network. Short to OUT+ for output stage gain GOUT of 0.2 V/V.
Negative (inverting) input.
Positive (noninverting) input.
No connect
IN+
4
NC
8
—
10
11
2,3
Output
Output
Negative Output
OUT–
OUT+
RG
Positive Output
Gain setting pin. Place a gain resistor between pin 2 and pin 3.
—
Level set for output clamp value. Connect either to an external supply that is at least 1.5 V
above VS–or connect to VS–if clamping function is not required.
5
Input
VCLAMP–
Level set for output clamp value. Connect either to an external supply that is at least 1.5 V
below VS+ or connect to VS+ if clamping function is not required.
VCLAMP+
16
Input
VOCM
VS–
VS+
13
7
Input
Power
Power
Level set for output common mode value.
Negative supply
14
Positive supply
The thermal pad must be soldered to the printed-circuit board (PCB). Connect thermal pad
to a plane or large copper pour electrically connected to the most negative supply or VS–.
Thermal Pad
Thermal pad
—
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
0
MAX
40
UNIT
VS
V
Supply voltage on VS+, VS–pins; VS = (VS+) –(VS–
Input voltage on IN+, IN–pins
)
VIN
(VS+) + 40
VS + 40
VS + 40
(VS+) + 0.5
(VS–) –40
(–VS) –40
(–VS) –40
(VS–) –0.5
GIN = 1 V/V, continuous
GIN > 1 V/V(3)
V
VDIFF
Differential input voltage, VDIFF = (VIN+) –(VIN–
)
V
V
Output voltage on OUT+, OUT–pins
FDA_IN+, FDA_IN–, G02+, G02–, VCLAMP+, VCLAMP–, VOCM pins
voltage
(VS+) + 0.5
(VS–) –0.5
Output short-circuit(2)
Operating temperature
Junction temperature
Storage temperature
Continuous
TA
125
175
150
°C
°C
°C
–40
TJ
Tstg
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) Short-circuit to VS / 2.
(3) Keep operation below 1% duty cycle of device lifecycle.
7.2 ESD Ratings
VALUE
±2500
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
V
Single supply, VS = (VS+), GND = (VS–
)
8
36
VS
Supply voltage
±4
–VS
±18
Dual supply, VS = (VS+) –(VS–
)
VIN
VDIFF
TA
VS
VS
V
Input voltage on IN+, IN–pins
GIN = 1 V/V
–VS
Differential input voltage,
V
GIN > 1 V/V(1)
1 + (VS) / GIN
125
VDIFF = (VIN+) –(VIN–
)
–1 –(VS) / GIN
–40
Specified temperature
°C
(1) See also INA851 Calculator Tool.
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UNIT
ZHCSQ83A –MARCH 2022 –REVISED OCTOBER 2022
7.4 Thermal Information
INA851
RGT (VQFN)
16 PINS
47.3
THERMAL METRIC(1)
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
53.2
22.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.4
ψJT
22.1
ψJB
RθJC(bot)
7.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
at TA = 25°C, VS = ±15 V, VICM = VOCM = midsupply, VCLAMP+ = VS+, VCLAMP– = VS–, G = GIN = GOUT = 1 V/V, and RL = 10
kΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT
±10
±35
±65
Input stage offset
voltage(1)
VOSI
µV
TA = –40°C to +125°C(4)
Input stage offset voltage
drift(2)
TA = –40°C to +125°C(4)
±0.1
±0.3 µV/°C
G = 0.2
G = 1
±150
±150
±5
±1150
Output stage offset
voltage(1)
VOSO
µV
±650
±15
G = 0.2
G = 1
Output stage offset
voltage drift(2)
TA = –40°C to +125°C(4)
µV/°C
±5
±15
G = 0.2
G = 1
100
110
120
126
130
120
126
Power-supply rejection
ratio
PSRR
GIN = 10
GIN = 100
GIN = 1000
140
dB
±4 V ≤VS ≤±18 V, RTI
140
140
zid
zic
Differential impedance
1 || 100
pF || GΩ
pF || GΩ
Common-mode
impedance
7 || 100
VIN
Input voltage(4) (5)
See also INA851 Calculator Tool
(VS–) + 2.5
V
V
(VS+) –2.5
Protected input voltage(8)
(VS+) + 40
(VS–) –40
Input current in
(VS–) –40 V ≤VIN ≤(VS+) + 40 V(3)
G = 0.2
16
mA
overvoltage mode(9)
76
86
90
96
G = 1
At dc to 60 Hz, RTI,
Common-mode rejection
ratio
CMRR
GIN = 10
GIN = 100
GIN = 1000
106
120
120
116
132
134
dB
VCM = (VS–) + 2.5 V to (VS+) –2.5
V
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7.5 Electrical Characteristics (continued)
at TA = 25°C, VS = ±15 V, VICM = VOCM = midsupply, VCLAMP+ = VS+, VCLAMP– = VS–, G = GIN = GOUT = 1 V/V, and RL = 10
kΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BIAS CURRENT
5
15
18
IB
Input bias current
nA
pA/°C
nA
TA = –40°C to +125°C(4)
Input bias current drift
Input offset current
Input offset current drift
25
TA = –40°C to +125°C
0.5
5.5
6
IOS
TA = –40°C to +125°C(4)
TA = –40°C to +125°C
5
pA/°C
NOISE VOLTAGE
Input stage voltage noise
density
eNI
f = 1 kHz, G = 1000
3.2
nV/√Hz
Input stage voltage noise fB = 0.1 Hz to 10 Hz, G = 1000
0.1
83
52
µVPP
G = 0.2
G = 1
Output stage voltage
f = 1 kHz
eNO
nV/√Hz
noise density(7)
G = 1;
GIN = 5, GOUT = 0.2
12
G = 0.2
G = 1
5.0
2.8
0.8
37
µVPP
µVPP
Output stage voltage
fB = 0.1 Hz to 10 Hz
noise(7)
Current noise density
Current noise
f = 1 kHz, GIN = 1000
pA/√Hz
pAPP
In
fB = 0.1 Hz to 10 Hz, G = 100
GAIN
Gain equation
Gain
G = GIN × GOUT
GOUT = 0.2
V/V
V/V
(1 + (6 kΩ / RG)) × (0.2 or 1)
0.2
1
2000
10000
±0.1
G
GOUT = 1
G = 0.2, VO = ±2 V
G = 1, VO = ±10 V
GIN ≥10, VO = ±10 V
±0.02
±0.2
GE
Gain error
%
G = 0.2
G = 1
±5
Gain drift(6)
±5 ppm/°C
±35
TA = –40°C to +125°C(4)
GIN > 1
±5
±5
G = 0.2, VO = –2 V to +2 V
G = 1, VO = –10 V to +10 V
Gain nonlinearity
ppm
OUTPUT
No output clamping
(VCLAMP+ = VS+
,
(VS–) + 1.4
(VS+) –1.4
VCLAMP– = VS–
)
IOUT = 10 mA,
TA = –40°C to +125°C
VO
Output voltage swing
Load capacitance
V
Output clamping enabled
(VCLAMP+ = VS+ –1.5 V,
VCLAMP– = VS–+1.5 V)
(VCLAMP+) +
0.1
(VCLAMP–) –
0.1
CL
ZO
ISC
Stable operation for differential load
f = 1 MHz
100
0.9
pF
Closed-loop output
impedance
Ω
Short-circuit current
±37
mA
TA = –40°C to 125°C, continuous to VS / 2
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7.5 Electrical Characteristics (continued)
at TA = 25°C, VS = ±15 V, VICM = VOCM = midsupply, VCLAMP+ = VS+, VCLAMP– = VS–, G = GIN = GOUT = 1 V/V, and RL = 10
kΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE
G = 0.2
22
22
G = 1, GIN = 5, GOUT = 0.2
G = 1
15
BW
SR
MHz
Bandwidth, –3 dB
GIN = 10
11
GIN = 100
5
GIN = 1000
0.8
Slew rate
G = 1, VO = ±10 V
37
V/µs
µs
G = 0.2, VSTEP = 2 V
G = 1, VSTEP = 10 V
GIN = 10, 100, VSTEP = 10 V
GIN = 1000, VSTEP = 10 V
G = 0.2, VSTEP = 2 V
G = 1, VSTEP = 10 V
GIN = 10,100, VSTEP = 10 V
GIN = 1000, VSTEP = 10 V
G = 0.2, VO = 2 VPP
G = 1, VO = 10 VPP
0.24
0.24
0.5
0.01%
1.7
tS
Settling time
0.55
0.55
2.1
0.001%
µs
2.5
–109
–110
–131
–128
–119
–121
Total harmonic distortion
plus noise
THD+N
HD2
Differential input, f = 10 kHz
Differential input, f = 10 kHz
Differential input, f = 10 kHz
dB
dB
dB
G = 0.2, VO = 2 VPP
G = 1, VO = 10 VPP
Second-order harmonic
distortion
G = 0.2, VO = 2 VPP
G = 1, VO = 10 VPP
Third-order harmonic
distortion
HD3
OUTPUT COMMON-MODE VOLTAGE (VOCM) CONTROL
No output clamping
(VS–) + 2.5
(VS+) –2.5
VOCM Input voltage
V
TA = –40°C to +125°C
(VCLAMP–) +
1
Output clamp enabled
(VCLAMP+) –1
Small-signal bandwidth
from VOCM pin
VOCM = 100 mVPP
VOCM = 0.5-V step
30
47
MHz
MHz
Large-signal bandwidth
from VOCM pin
Slew rate from VOCM pin
DC output balance
VOCM = 0.5-V step
37
70
V/µs
dB
VOCM fixed midsupply (VO = ±1 V)
Input impedance VVOCM
pin
250 || 1
kΩ|| pF
VOCM offset from mid-
supply
VOCM pin floating
±2
±2
±6
mV
±6
VOCM common-mode
offset voltage
VOCM = VICM, VO = 0 V
mV
±10
TA = –40°C to +125°C
VOCM common-mode
offset voltage drift
±20
±60 µV/°C
VOCM = VICM, VO = 0 V, TA = –40°C to +125°C
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7.5 Electrical Characteristics (continued)
at TA = 25°C, VS = ±15 V, VICM = VOCM = midsupply, VCLAMP+ = VS+, VCLAMP– = VS–, G = GIN = GOUT = 1 V/V, and RL = 10
kΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VS+
MAX
UNIT
OUTPUT CLAMPING
No output clamping
VCLAMP+ Positive clamp voltage(10)
V
V
TA = –40°C to +125°C
Output clamp enabled
No output clamping
Output clamp enabled
VS+ –1.5
VS–
Negative clamp
VCLAMP–
TA = –40°C to +125°C
voltage(10)
VS–+ 1.5
3
Δ
VCLAMP
Clamp voltage(10)
V
ΔVCLAMP = (VCLAMP+) –(VCLAMP–
)
Power-supply rejection
ratio from VCLAMP to VO
120
dB
(3)
Fail-safe current VCLAMP+ VS+ = VS– = 0 V, VCLAMP+ = 10 V
2
–60
60
mA
µA
µA
ICLAMP+ Positive clamp current
ICLAMP– Negative clamp current
POWER SUPPLY
V
CLAMP+ ≤VS+ –1.5 V
–80
80
VCLAMP– ≥VS– + 1.5 V
6
7
9
IQ
Quiescent current
VIN = 0 V
mA
TA = –40°C to +125°C
(1) Offset voltages are uncorrelated. Total offset voltage, referred-to-input (RTI): VOS = √[VOSI 2 + (VOSO(Gout1 or Gout0.2) / GIN)2]. See more
details on Offset Voltage section.
(2) Offset drifts are uncorrelated. Offset drift, referred-to-input (RTI): ΔVOS(RTI) = √[ΔVOSI 2 + (ΔVOSO / GIN)2].
(3) Specified by design.
(4) Specified by characterization.
(5) Input voltage range of the instrumentation amplifier input stage. The valid input range depends on the common-mode voltage,
differential voltage, gain, and VOCM. See also the Input Common-Mode Range section.
(6) The values specified for G > 1 do not include the effects of the external gain-setting resistor, RG.
(7) eNO refers to output stage noise referred to the input of the FDA. See also the Noise Equivalent Model section.
(8) See also the Input Protection section.
(9) See also the Typical Characteristics section.
(10) See also the Output Clamping section.
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ZHCSQ83A –MARCH 2022 –REVISED OCTOBER 2022
7.6 Typical Characteristics
at TA = 25°C, VS = ±15 V, VICM = VOCM = midsupply, VCLAMP+ = VS+, VCLAMP– = VS–, G = GIN = GOUT = 1 V/V, and RL = 10
kΩ(unless otherwise noted)
表7-1. Table of Graphs
DESCRIPTION
Typical Distribution of Input Stage Offset Voltage
Typical Distribution of Input Stage Offset Voltage Drift
Typical Distribution of Output Stage Offset Voltage, G = 1
Typical Distribution of Output Stage Offset Voltage, G = 0.2
Typical Distribution of Output Stage Offset Voltage Drift
Typical Distribution of Input Offset Current
Typical Distribution of Input Bias Current, TA = 25°C
Typical Distribution of Input Bias Current, TA = 90°C
Typical CMRR Distribution, G = 1
FIGURE
图7-1
图7-2
图7-3
图7-4
图7-5
图7-6
图7-7
图7-8
图7-9
Typical CMRR Distribution, G = 10
图7-10
图7-11
图7-12
图7-13
图7-14
图7-15
图7-16
图7-17
图7-18
图7-19
图7-20
图7-21
图7-22
图7-23
图7-24
图7-25
图7-26
图7-27
图7-28
图7-29
图7-30
图7-31
图7-32
图7-33
图7-34
图7-35
图7-36
图7-37
图7-38
图7-39
Typical Distribution of Gain Error, G = 0.2
Typical Distribution of Gain Error, G = 1
Typical Distribution of Gain Error, G = 10
Input Stage Offset Voltage vs Temperature
Input Bias Current vs Temperature
Input Offset Current vs Temperature
Input-Referred Output Offset Voltage vs Temperature
CMRR vs Temperature, G = 1
CMRR vs Temperature, G = 10
CMRR vs Frequency (RTI)
CMRR vs Frequency (RTI, 1-kΩsource imbalance)
Positive/Negative PSRR vs Frequency (RTI)
PSRR vs Frequency of VCLAMP+ (RTI)
Gain vs Frequency
Voltage Noise Spectral Density vs Frequency (RTI)
Current Noise Spectral Density vs Frequency (RTI)
0.1-Hz to 10-Hz RTI Voltage Noise, G = 0.2
0.1-Hz to 10-Hz RTI Voltage Noise, G = 1
0.1-Hz to 10-Hz RTI Voltage Noise, G = 1000
Positive Input Bias Current vs Common-Mode Voltage
Negative Input Bias Current vs Common-Mode Voltage
Gain Error vs Temperature
Quiescent Current vs Temperature
Gain Nonlinearity, G = 1
Gain Nonlinearity, G = 10
Offset Voltage vs Negative Common-Mode Voltage
Offset Voltage vs Positive Common-Mode Voltage
Positive Output Voltage Swing vs Output Current
Negative Output Voltage Swing vs Output Current
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ZHCSQ83A –MARCH 2022 –REVISED OCTOBER 2022
7.6 Typical Characteristics
at TA = 25°C, VS = ±15 V, VICM = VOCM = midsupply, VCLAMP+ = VS+, VCLAMP– = VS–, G = GIN = GOUT = 1 V/V, and RL = 10
kΩ(unless otherwise noted)
表7-1. Table of Graphs (continued)
DESCRIPTION
FIGURE
图7-40
图7-41
图7-42
图7-43
图7-44
图7-45
图7-46
图7-47
图7-48
图7-49
图7-50
图7-51
图7-52
图7-53
图7-54
图7-55
图7-56
Claw Curve of VCLAMP+
Short Circuit Current vs Temperature
Large-Signal Frequency Response
THD+N vs Frequency
Overshoot vs Capacitive Loads
Small-Signal Response with different Output Capacitors G = 1 V/V
Small-Signal Response, G = 0.2
Small-Signal Response, G = 1
Small-Signal Response, G = 10
Small-Signal Response, G = 1000
Small-Signal Response of VOCM Amplifier
Large Signal Step Response
Closed-Loop Output Impedance
Settling Time for G = 0.2
Settling Time for G = 1
Offset Warm-up for G = 1
Offset Warm-up for G = 100
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ZHCSQ83A –MARCH 2022 –REVISED OCTOBER 2022
7.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, VICM = VOCM = midsupply, VCLAMP+ = VS+, VCLAMP– = VS–, G = GIN = GOUT = 1 V/V, and RL = 10
kΩ(unless otherwise noted)
15
10
5
20
15
10
5
0
0
-35
-25
-15
-5
5
15
25
35
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
Input Offset Voltage (ꢀV)
Input Offset Voltage Drift (ꢀV)
N = 82 Mean = 0.062 µV/°C Std. Dev. = 0.0738 µV/°C
N = 150
Std. Dev. = 6.73 µV
Mean = –2.32 µV
图7-2. Typical Distribution of Input Stage Offset Voltage Drift
图7-1. Typical Distribution of
Input Stage Offset Voltage
15
20
15
10
5
10
5
0
0
-650
-450
-250
0
250
450
650
-1150-950 -750 -550 -350 -150 0 150 350 550 750 950 1150
Output Offset Voltage (ꢀV)
Output Offset Voltage (ꢀV)
N = 150
Std. Dev. = 82.71 µV
N = 150
Mean = –27.84 µV
Mean = –97.17 μV Std. Dev. = 179.33 μV
G = 1 V/V
G = 0.2 V/V
图7-3. Typical Distribution of Output Offset Voltage
图7-4. Typical Distribution of Output Offset Voltage
30
30
20
10
0
20
10
0
-15
-10
-5
0
5
10
15
-5
-4
-3
-2
-1
0
1
2
3
4
5
Output Offset Voltage Drift (ꢀV/ꢁC)
Input Offset Current (nA)
N = 82
Std. Dev. = 1.59 µV/°C
N = 53
Std. Dev. = 0.50 nA
Mean = –4.98 µV/°C
Mean = –0.14 nA
图7-5. Typical Distribution of Output Stage Offset Voltage Drift
图7-6. Typical Distribution of
Input Offset Current
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ZHCSQ83A –MARCH 2022 –REVISED OCTOBER 2022
7.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, VICM = VOCM = midsupply, VCLAMP+ = VS+, VCLAMP– = VS–, G = GIN = GOUT = 1 V/V, and RL = 10
kΩ(unless otherwise noted)
30
20
10
0
-18
-14
-10
-6
-2
0
2
6
10
14
18
Input Bias Current (nA)
N = 107
Std. Dev. = 0.75 nA
Mean = –2.34
Mean = –2.2 nA
N = 107
Std. Dev. = 0.78 nA
nA
TA = 90°C
TA = 25°C
图7-8. Typical Distribution of Input Bias Current
图7-7. Typical Distribution of Input Bias Current
20
15
10
5
0
-50 -40 -30 -20 -10
0
10
20
30
40
50
Common-Mode Rejection Ratio (ꢀV/V)
N = 150
G = 1 V/V
图7-9. Typical CMRR Distribution at G = 1 V/V
Std. Dev. = 8.67 µV/V
Mean = –4.78 µV/V
N = 300
Std. Dev. = 1.03 µV/V
Mean = –0.62 µV/V
G = 10 V/V
图7-10. Typical CMRR Distribution at G = 10 V/V
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ZHCSQ83A –MARCH 2022 –REVISED OCTOBER 2022
7.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, VICM = VOCM = midsupply, VCLAMP+ = VS+, VCLAMP– = VS–, G = GIN = GOUT = 1 V/V, and RL = 10
kΩ(unless otherwise noted)
60
40
20
0
-0.02
-0.01
0
0.01
0.02
Gain Error (%)
N = 293
G = 1 V/V
Std. Dev. = 0.0011%
Mean = –0.0037%
N = 293
Std. Dev. = 0.005%
Mean = –0.017%
图7-11. Typical Gain Error Distribution at G = 0.2 V/V
图7-12. Typical Gain Error Distribution at G = 1 V/V
75
Mean
+3
-3
50
25
0
-25
-50
-75
-40
-20
0
20
40
60
80
100 120 140
Temperature (ꢀC)
N = 52
N = 297
Std. Dev. = 0.0136%
Mean = –0.0048 %
G = 10 V/V
图7-14. Input Stage Offset Voltage vs Temperature
图7-13. Typical Gain Error Distribution at G = 10 V/V
6
5
Avg
+3ꢁ
-3ꢁ
5
4
4
3
3
2
2
1
1
0
0
-1
-2
-3
-4
-5
-6
-1
-2
-3
-4
-5
Avg
+3ꢁ
-3ꢁ
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (ꢀC)
Temperature (ꢀC)
N = 54
N = 54
图7-15. Input Bias Current vs Temperature
图7-16. Input Offset Current vs Temperature
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ZHCSQ83A –MARCH 2022 –REVISED OCTOBER 2022
7.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, VICM = VOCM = midsupply, VCLAMP+ = VS+, VCLAMP– = VS–, G = GIN = GOUT = 1 V/V, and RL = 10
kΩ(unless otherwise noted)
300
200
100
0
-90
-100
-110
-120
-130
-100
-200
-300
-400
-500
-600
-700
-800
Unit 1
Unit 2
Unit 3
Unit 4
Unit 5
Mean
+3
-3
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (ꢀC)
Temperature (ꢀC)
N = 50
图7-17. Input-Referred Output Offset Voltage vs Temperature
图7-18. CMRR vs Temperature
-110
140
130
120
110
100
90
-120
80
70
60
-130
G = 0.2
G = 1
Unit 1
Unit 2
50
G = 10
G = 100
G = 1000
Unit 3
Unit 4
Unit 5
40
30
20
-140
-40
10
100
1k
10k
100k
1M
10M
-20
0
20
40
60
80
100 120 140
Frequency (Hz)
Temperature (ꢀC)
G = 10
图7-20. CMRR vs Frequency (RTI)
图7-19. CMRR vs Temperature
120
100
80
60
40
Positive Supply PSRR(VS+
)
Negative Supply PSRR(VS-
)
20
1
10
100
1k
Frequency (Hz)
10k
100k
1M
1-kΩsource imbalance
图7-21. CMRR vs Frequency (RTI) Imbalance
图7-22. PSRR vs Frequency (RTI)
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ZHCSQ83A –MARCH 2022 –REVISED OCTOBER 2022
7.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, VICM = VOCM = midsupply, VCLAMP+ = VS+, VCLAMP– = VS–, G = GIN = GOUT = 1 V/V, and RL = 10
kΩ(unless otherwise noted)
160
150
140
130
120
110
100
90
140
120
100
80
G = 1
G = 1*0.2
G = 10
G = 100
G = 1000
G = 5*0.2
60
40
80
70
20
60
50
0
40
-20
30
20
100m
-40
1k
1
10
100
1k
10k
100k
1M
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
图7-23. PSRR vs Frequency (RTI) of VCLAMP+
图7-24. Gain vs Frequency
20000
Current Noise N
Current Noise P
10000
7000
5000
3000
2000
1000
700
500
300
200
100m
1
10
100
1k
10k
100k
Frequency (Hz)
eN(RTI) = √[eNI 2 + (eNO(G0.2 or G1) / GIN)2]
G = 1000 V/V
图7-26. Current Noise Spectral Density vs Frequency (RTI)
图7-25. Voltage Noise Spectral Density vs Frequency (RTI)
3
2.5
2
2
1
1.5
1
0.5
0
0
-0.5
-1
-1
-2
-3
-1.5
-2
-2.5
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
Time (1s/div)
Time (1s/div)
G = 1 V/V
图7-28. 0.1-Hz to 10-Hz RTI Voltage Noise
G = 0.2 V/V
图7-27. 0.1-Hz to 10-Hz RTI Voltage Noise
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ZHCSQ83A –MARCH 2022 –REVISED OCTOBER 2022
7.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, VICM = VOCM = midsupply, VCLAMP+ = VS+, VCLAMP– = VS–, G = GIN = GOUT = 1 V/V, and RL = 10
kΩ(unless otherwise noted)
40
30
0
-0.5
-1
-40ꢀC
25ꢀC
85ꢀC
125ꢀC
CM Range
20
10
-1.5
-2
0
-10
-20
-30
-40
-2.5
-3
-3.5
-4
-15 -12
-9
-6
-3
0
3
6
9
12
15
0
1
2
3
4
5
6
7
8
9
10
Input Common Mode Voltage (V)
Time (1s/div)
G = 1000 V/V
图7-29. 0.1-Hz to 10-Hz RTI Voltage Noise
图7-30. Positive Input Bias Current vs Common‑Mode Voltage
0
-40ꢀC
25ꢀC
85ꢀC
125ꢀC
-0.5
-1
CM Range
-1.5
-2
-2.5
-3
-15 -12
-9
-6
-3
0
3
6
9
12
15
Input Common Mode Voltage (V)
图7-31. Negative Input Bias Current vs Common‑Mode Voltage
图7-32. Gain Error vs Temperature
10
0.5
0.4
0.3
0.2
0.1
0
9
8
7
6
-0.1
-0.2
-0.3
5
VS = ꢁ 15 V
VS = ꢁ 4 V
4
-60 -40 -20
0
20 40 60 80 100 120 140 160
-12 -10 -8 -6 -4 -2
0
2
4
6
8
10 12
Temperature (ꢀC)
Output Voltage (V)
G = 1
图7-34. Gain Nonlinearity, G = 1
图7-33. Quiescent Current vs Temperature
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ZHCSQ83A –MARCH 2022 –REVISED OCTOBER 2022
7.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, VICM = VOCM = midsupply, VCLAMP+ = VS+, VCLAMP– = VS–, G = GIN = GOUT = 1 V/V, and RL = 10
kΩ(unless otherwise noted)
12
10
8
200
150
100
50
-40ꢁC
-20ꢁC
25ꢁC
60ꢁC
6
85ꢁC
125ꢁC
CM Range
4
0
2
-50
0
-100
-150
-200
-250
-300
-350
-400
-2
-4
-6
-8
-10
-12
-12 -10 -8 -6 -4 -2
0
2
4
6
8
10 12
-14
-13.5
-13
-12.5
-12
-11.5
-11
Output Voltage (V)
Input Common-Mode Voltage (V)
G = 10
图7-35. Gain Nonlinearity, G = 10
图7-36. Offset Voltage vs Negative Common-Mode Voltage
200
150
100
50
15
-40ꢁC
-40ꢀC
25ꢀC
-20ꢁC
25ꢁC
60ꢁC
85ꢁC
125ꢁC
14.5
85ꢀC
125ꢀC
VO(max)
0
14
-50
-100
-150
-200
-250
-300
-350
-400
13.5
13
12.5
12
11
11.5
12
12.5
13
13.5
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25
Output Current (mA)
Input Common-Mode Voltage (V)
图7-37. Offset Voltage vs Positive Common-Mode Voltage
图7-38. Positive Output Voltage Swing vs Output Current
-12
6
-40ꢀC
25ꢀC
5
-12.5
85ꢀC
125ꢀC
VO(min)
4
-13
-40ꢀC
25 ꢀC
3
2
85ꢀC
-13.5
-14
125ꢀC
VClamp+/-
1
-14.5
-15
0
-1
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25
Output Current (mA)
0
5
10
15
20
25
Output Current (mA)
图7-39. Negative Output Voltage Swing vs Output Current
图7-40. Claw Curve of VCLAMP+/-
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ZHCSQ83A –MARCH 2022 –REVISED OCTOBER 2022
7.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, VICM = VOCM = midsupply, VCLAMP+ = VS+, VCLAMP– = VS–, G = GIN = GOUT = 1 V/V, and RL = 10
kΩ(unless otherwise noted)
60
40
20
0
20
18
16
14
12
10
8
VS = ꢀ15 V
VS = ꢀ5 V
ISC, Source
ISC, Sink
-20
-40
-60
6
4
2
0
100
-40
-20
0
20
40
60
80
100 120 140
1k
10k
100k
1M
10M
Temperature (ꢀC)
Frequency (Hz)
图7-41. Short Circuit Current vs Temperature
图7-42. Large-Signal Frequency Response
1
-40
-60
-80
-100
40
30
20
10
0
G = 1
G = 10
G = 100
No stable operation
0.1
0.01
Riso = 0 ꢀ
Riso = 25 ꢀ
Riso = 50 ꢀ
0.001
10
100
1k
Frequency (Hz)
10k
100k
D040
50
75
100
125
150
175
200
Capacitive Load (pF)
500-kHz measurement bandwidth
1-VRMS output voltage
图7-43. THD+N vs Frequency
100-kΩload
图7-44. Overshoot vs Capacitive Loads
200
150
100
50
100
80
CL = 40 pF
CL = 76 pF
CL = 100 pF
CL = 130 pF
CL = 150 pF
60
40
20
0
-20
-40
-60
-80
-100
0
-50
-100
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
-1
0
1
2
3
4
5
6
Time (ꢀs)
Time (ꢀs)
G = 1
G = 0.2 V/V
CL = 100 pF
RL = 10 kΩ
RL = 10 kΩ
图7-45. Small-Signal Response with different Output
图7-46. Small-Signal Response for G = 0.2 V/V
Capacitors G = 1 V/V
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ZHCSQ83A –MARCH 2022 –REVISED OCTOBER 2022
7.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, VICM = VOCM = midsupply, VCLAMP+ = VS+, VCLAMP– = VS–, G = GIN = GOUT = 1 V/V, and RL = 10
kΩ(unless otherwise noted)
90
60
30
0
-30
-60
-90
-1
0
1
2
3
4
5
6
Time (ꢀs)
G = 1 V/V
CL = 100 pF
G = 10 V/V
CL = 100 pF
RL = 10 kΩ
RL = 10 kΩ
图7-47. Small-Signal Response for G = 1 V/V
图7-48. Small-Signal Response for G = 10 V/V
60
40
20
0
100
75
VOCM Input
Output
50
25
0
-20
-40
-60
-25
-50
-75
2
3
4
5
6
7
8
9
10
-2
-1
0
1
2
3
4
5
6
7
Time (us)
Time (ꢀs)
G = 1000 V/V
CL = 100 pF
RL = 10 kΩ
图7-50. Small-Signal Response of VOCM Amplifier
图7-49. Small-Signal Response for G = 1000 V/V
7.5
100
5
10
1
2.5
0
0.1
-2.5
-5
0.01
0.001
0.0001
-7.5
-4
-3
-2
-1
0
1
2
3
4
5
6
1
10
100
1k
10k
100k
1M
10M
Time (ꢀs)
Frequency (Hz)
图7-51. Large Signal Step Response
图7-52. Closed-Loop Output Impedance
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ZHCSQ83A –MARCH 2022 –REVISED OCTOBER 2022
7.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, VICM = VOCM = midsupply, VCLAMP+ = VS+, VCLAMP– = VS–, G = GIN = GOUT = 1 V/V, and RL = 10
kΩ(unless otherwise noted)
0.001%
0.01%
0.01%
0.001%
Time (100 µs/div)
Time (1 µs/div)
G = 1 V/V
G = 0.2 V/V
图7-54. Settling Time for G = 1 V/V
图7-53. Settling Time for G = 0.2 V/V
20
16
12
8
4
0
-4
-8
-12
-16
-20
0
10 20 30 40 50 60 70 80 90 100 110 120
Time (s)
G = 100 V/V
G = 1 V/V
图7-56. Offset Warm-up for G = 100 V/V
图7-55. Offset Warm-up for G = 1 V/V
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8 Detailed Description
8.1 Overview
The INA851 is a monolithic, precision instrumentation amplifier that incorporates a current-feedback input stage
and a four-resistor, fully differential amplifier output stage. The schematic in 图 8-1 shows how the differential
input voltage is buffered by Q1 and Q2, and is forced across RG, which causes a signal current to flow through
RG, R1, and R2. The fully differential amplifier, A3, removes the common-mode component of the input signal and
refers the output signal to the VOCM pin. The VBE and voltage drop across R1 and R2 produce output voltages
on A1 and A2 that are approximately 0.8 V less than the input voltages.
VS +VS
FDA_IN–
VS +VS
+VS
R7
1.25 k
G02+
VB
RB
RB
IB Cancellation
IB Cancellation
VS +VS
R5
5 k
R3
5 k
–
A1
A2
OUT+
OUT–
+
–
C1
A3
C2
+
R4
5 k
R6
5 k
VS +VS
VS +VS
VS +VS
+VS
+VS
G02–
R8
1.25 k
Super-
NPN
Super-
NPN
+IN
IN
+VS
+VS
FDA_IN+
Q1
Q2
R2
3 k
R1
3 k
VS
VS
OUT+
VCLAMP+
A4
Optional RG
(External)
C3
0.5pF
R11
70 k
R9
500 k
VS
VS
VOCM
C4
0.5pF
R12
70 k
R10
500 k
OUT–
VCLAMP
VS +VS
图8-1. Detailed Schematic
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8.2 Functional Block Diagram
External Gain Set
Resistor (Optional)
VOCM VCLAMP+ FDA_IN─ (Optional)
G02+ (Optional, Externally
Short to OUT+ or Float)
LDO
Input Bias
Current
Cancellation
Current-
Feedback
Input Stage
Overvoltage
Protection
─IN
OUT+
Fully Differential
Amplifier
OUT─
Input Bias
Current
Cancellation
Current-
Feedback
Input Stage
Overvoltage
Protection
+IN
G02─ (Optional, Externally
Short to OUT─ or Float)
LDO
VCLAMP─ FDA_IN+ (Optional)
8.3 Feature Description
8.3.1 Adjustable Gain Setting
图 8-2 shows that the INA851 input-stage gain is set by a single external resistor (RG) connected between the
RG pins. The gain of the output stage can be set to a unity gain of 1 V/V by floating the G02+ and G02–pins, or
to an attenuating gain of 0.2 V/V by shorting those pins to the respective OUT+ and OUT–pins.
Short OUT to G02 and
INA851
IN
OUT+ to G02+ for output
stage G = 0.2 option
FDA_IN
G02+
+
–
VIN
R3
RG
VO = G • (VIN+ VIN ) + VOCM
1.25 k
R4
RF
3 k
R1
5 k
5 k
INP
INN
OUT+
OUT
+
VO
–
+
+
–
RG
ADC
RF
5 k
R2
R5
3 k
5 k
R6
RG+
IN+
–
+
G02
6 k
RG
GIN
= 1 +
1.25 k
VIN+
GOUT = 0.2 or 1
FDA_IN+
G = GIN * GOUT
VOCM
VOCM
图8-2. Simplified Diagram of the INA851 With Gain Equations
If the output stage is in the unity gain configuration, the value of RG is selected according to the following
equation:
6kΩ
G = 1 +
(1)
R
G
When OUT+ is shorted to G02+ (pin 11 to pin 12) and OUT– is shorted to G02– (pin 9 to pin 10) so that the
output stage is in the attenuating configuration, the gain equation becomes:
6kΩ
G = 0.2 × 1 +
(2)
R
G
表 8-1 lists several commonly used gains and resistor values, as well as the additional gain error that is
contributed by the gain resistors. The 6-kΩ term in the gain equation is a result of the sum of the two internal 3-
kΩ feedback resistors. These on-chip resistors are laser-trimmed to accurate absolute values. The accuracy
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and temperature coefficients of these resistors are included in the gain accuracy and drift specifications of the
INA851. The 5-kΩ and 1.25-kΩ resistors used in the output stage are ratiometrically matched to achieve stable
1-V/V and 0.2-V/V gain terms; although, the resistor values can shift up to 15%, depending on production.
表8-1. Commonly Used Gains and Resistor Values
RG
(Ω)
NEAREST 1% RG
DESIRED GAIN
(V/V)
CALCULATED GAIN
(V/V)
CONTRIBUTED GAIN ERROR
(%)
(Ω)
NC, short OUT+ to G02+
and OUT–to G02–
0.2
0.5
NC
0.200
0.499
N/A
4 k, short OUT+ to G02+
and OUT–to G02–
4.02 k
0.30
1
2
NC
6 k
NC
5.97 k
1.5 k
665
1.000
2.005
N/A
–0.25
0.00
5
1.5 k
5.000
10
666.67
315.79
122.45
60.61
30.15
12.02
6.01
10.023
19.987
49.387
100.338
200.336
496.868
994.377
9934.775
–0.23
0.06
20
316
50
124
1.23
100
200
500
1000
10000
60.4
30.1
12.1
6.04
604 m
–0.34
–0.17
0.63
0.56
600 m
0.65
As shown in 图 8-2 and explained in more detail in 节 9.4, make sure to connect low-ESR, 0.1-µF ceramic
bypass capacitors between each supply pin and ground, and to place these capacitors as close as possible to
the device pins.
8.3.1.1 Gain Drift
The stability and temperature drift of external gain setting resistor RG also affects gain. The contribution of RG to
gain accuracy and drift is determined from 方程式 1. The best gain drift of 5 ppm/℃ (maximum) is achieved
when the INA851 uses G = 1 in the input stage, without RG connected. In this case, gain drift is limited by the
mismatch of the temperature coefficient of the integrated resistors in fully differential amplifier A3. When the
output stage is in attenuating gain mode (OUT− shorted to G02− and OUT+ shorted to G02+), both the 1.25-kΩ
and the 5-kΩ resistors contribute mismatch, as do the traces between the G02x and OUTx pins. Only the 5-kΩ
resistors contribute mismatch when the output stage is in unity gain mode (with G02− and G02+ floating).
At input stage gains greater than 1, gain drift increases as a result of the individual drift of the 3-kΩ resistors in
the feedback of A1 and A2, relative to the drift of external gain resistor RG. The low temperature coefficient of the
internal feedback resistors improves the overall temperature stability of applications using input-stage gains
greater than 1 V/V over alternate solutions. The low resistor values required for high gain make wiring resistance
an important consideration. Sockets add to the wiring resistance and contribute additional gain error (such as a
possible unstable gain error) at gains of approximately 20 or greater. To maintain stability, avoid parasitic
capacitance of more than a few picofarads at the RG connections. Careful matching of any parasitics on the RG
pins maintains optimal CMRR over frequency.
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8.3.2 Offset Voltage
Low offset voltage is one of the key parameters for an instrumentation amplifier (INA). In a current-feedback INA,
this error source is classified in three stages: input, output, and intermediate. The input-stage dc offset (VOSI) is
mainly caused by the mismatch of the input transistors Q1 and Q2, (see 图 8-1). The output-stage dc offset
(VOSO) is caused partially by the mismatch of the output amplifier A3. In the INA851, A3 is a fully-differential
amplifier and gained up by the noise gain of the circuit (1 + R5 / R3). An additional intermediate stage offset
contribution error adds to VOSO that is caused by the mismatch of the current mirrors in the front end (through R1
and R2).
Unlike typical instrumentation amplifiers that incorporate a difference amplifier (A3) with a fixed output gain, the
INA851 has two different output gain stages that subsequently contribute differently to VOSO; see Gaussian
distributions for G = GOUT = 1 V/V in 图7-3 and for G = GOUT = 0.2 V/V in 图7-4.
The following equation calculates the total offset voltage error referred to the input:
2
V
OSO G
= 1 or G
= 0.2
OUT
2
OUT
V
=
V
+
OSI
(3)
OS
G
IN
8.3.3 Input Common-Mode Range
The linear input voltage range of the INA851 input circuitry extends within 2.5 V (maximum) of both power
supplies, and maintains excellent common-mode rejection throughout this range. The valid input common-mode
range is a function of the input common-mode voltage, input differential voltage, gain, and output common-mode
voltage.
The common-mode range is best calculated using the INA851 Input-Output Range Design Calculator .
The common-mode range for the most common operating conditions are shown in 图8-3 to 图8-9.
2
1.6
1.2
0.8
0.4
0
15
12
9
G = 0.2 V/V
G = 0.5 V/V
G = 0.2 V/V
G = 0.5 V/V
6
3
0
-3
-6
-9
-12
-15
-0.4
-0.8
-1.2
-1.6
-2
-6 -5 -4 -3 -2 -1
0
1
2
3
4
5
6
-1 -0.8 -0.6 -0.4 -0.2
0
0.2 0.4 0.6 0.8
1
Output Differential Voltage (V)
Output Differential Voltage (V)
VS± = 15 V
VS± = ±4 V
图8-4. Input Common-Mode Voltage vs Output
图8-3. Input Common-Mode Voltage vs Output
Voltage, Low Gains
Voltage, Low Gains
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2
15
12
9
G = 1 V/V
G = 5 x 0.2 V/V
G = 1 V/V
G = 5x0.2 V/V
1
0
6
3
0
-3
-6
-9
-12
-15
-1
-2
-25 -20 -15 -10
-5
0
5
10
15
20
25
-4
-3
-2
-1
0
1
2
3
4
Output Differential Voltage (V)
Output Differential Voltage (V)
VS± = ±15 V
VS± = ±4 V
图8-6. Input Common-Mode Voltage vs Output
图8-5. Input Common-Mode Voltage vs Output
Voltage, Unity-Gains
Voltage, Unity-Gain
2
15
G = 10x1 V/V
G = 100x1 V/V
G = 10 x 1 V/V
G = 100 x 1 V/V
12
1.5
1
9
6
0.5
0
3
0
-3
-6
-9
-12
-15
-0.5
-1
-1.5
-2
-5
-4
-3
-2
-1
0
1
2
3
4
5
-28 -24 -20 -16 -12 -8 -4
0
4
8
12 16 20 24 28
Output Differential Voltage (V)
Output Differential Voltage (V)
VS± = ±4 V
High Gains
图8-7. Input Common-Mode Voltage vs Output
图8-8. Input Common-Mode Voltage vs Output
Voltage, High Gains
Voltage, High Gains
21
G = 0.2 V/V
G = 0.5 V/V
18
G = 10 V/V
15
12
9
6
3
0
-3
-6
-9
-12
-3
-2
-1
0
1
2
3
Output Differential Voltage (V)
VS± = ±12 V
Vclamp+ = 5 V, Vclamp- = GND
图8-9. Input Common-Mode Voltage vs Output Voltage With Output Clamping
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8.3.4 Input Protection
The inputs of the INA851 device are individually protected for voltages up to ±40 V beyond the power supply
rails. For example, a condition of VS– = –55 V on one input and VS+ = 55 V on the other input does not cause
damage. Internal circuitry on each input provides low series impedance under normal signal conditions. 图 8-10
shows that if the input is overloaded, the protection circuitry limits the input current to a value of approximately
16 mA.
图8-10. Input Current During an Overvoltage Condition
图 8-11 shows that during an input overvoltage condition, current flows through the input protection diodes into
the power supplies. If the power supplies are unable to sink current, then place Zener diode clamps (ZD1 and
ZD2 in 图8-11) on the power supplies to provide a current pathway to ground.
VS+
ZD1
VS+
INx
RIN
Overvoltage
Protection
Input Voltage
Source
+
–
Input Transistor
VS–
ZD2
VS–
图8-11. Input Current Path During an Overvoltage Condition
If an input stage gain greater than GIN = 1 V/V is implemented, where a gain resistor is present across the RG
pins, the inputs are still well protected against overvoltage conditions; however, make sure that the input
differential voltage limitations of the INA851 are not exceeded. For example, a condition of (VS+) + 40 V on both
inputs does not cause damage. However, a condition of (VS–) – 40 V on one input and (VS+) + 40 V on the
other input can cause damage. Precautions can include the use of external resistors in series with each of the
inputs.
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8.3.5 Output Clamping
The INA851 features a unique output clamping function that protects the downstream device against damage
that results from inadvertent over-driving. Usually the downstream device is an ADC that typically operates at a
lower supply voltage than the INA851.
To implement this function, use the VCLAMP+ and VCLAMP– pins to limit the supply voltage range of the
differential output drive amplifier. For typical operation, use a low-impedance connection from the pins to the
power supplies of the ADC. For proper operation of the clamp circuitry, set the VS+ or VS– supply voltages at
least 1.5 V beyond the respective VCLAMP+ and VCLAMP– clamping voltages. In addition, for the output driver to
function correctly, the VCLAMP+ and VCLAMP– voltages must be at least 3 V apart. If the output clamping
functionality is not desired, short the VCLAMP+ and VCLAMP–pins to the amplifier VS+ and VS–supply pins.
The output driver operates up to the VCLAMP+ or VCLAMP– limits without experiencing distortion. When the
clamping function is in use the output voltage is clamped at approximately 600 mV beyond the clamp voltage.),
so that the device output spans the full input range of the ADC. However, if the predriver output swings beyond
the VCLAMP+ or VCLAMP– voltage, the output driver begins to run out of headroom as a result of the clamped
supply voltage, shown in 图8-12.
The output is unable to swing greater than approximately 500 mV beyond the VCLAMP+ or VCLAMP– voltage (at
zero load), helping prevent or reduce damage to the ADC from overvoltage conditions.
The linear operation becomes distorted when the driver load becomes higher than 20 mA, see 图8-13.
VS+
VCLAMP+
–
Output Driver
OUT+
OUT
–
–
FDA_IN
+
+
+
FDA Input
–
Predriver
–
+
–
FDA_IN+
+
+
VS
VCLAMP
图8-12. Simplified Schematic of Output Driver Clamping Structure
备注
Be aware that instead of providing an immediate hard-stop voltage limit, the output driver is not
clamped until VCLAMP+ or VCLAMP– voltage has been exceeded, and the driver starts to run out of
headroom. This configuration prevents distortion of the amplifier output when operating near the
VCLAMP+ and VCLAMP– rails. However, the output voltage exceeds VCLAMP+ and VCLAMP– by several
hundreds of millivolts before the clamps turn on strongly. When used in conjunction with several tens
of ohms of resistance between the amplifier output and ADC input pins (commonly implemented as
part of a low-pass filter for proper ADC acquisition), output clamping helps severely diminish any
potential damage to the ADC that can otherwise result.
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6
5
4
-40ꢀC
25 ꢀC
85ꢀC
3
125ꢀC
VClamp+/-
2
1
0
-1
0
5
10
15
20
25
Output Current (mA)
图8-13. Output Voltage With Output Clamping Enabled
The VCLAMP+ pin features a fail-safe against power-up sequencing issues between the INA851 and a
downstream device. For example, a condition of V(CLAMP+) + 10 V on this pin does not cause damage.
Therefore, the ADC supply can safely turn on while the INA851 supply is still off or just beginning to turn on. In
this case, the current draw through the VCLAMP+ pin is limited to a safe value of typically 3 mA.
8.3.6 Low Noise
An output noise calculation helps design a low-noise circuit to drive high-precision ADC applications and
optimize the signal-to-noise ratio (SNR).
图 8-14 shows a simplified noise model for the INA851. The eNO noise refers to the input resistor network of the
FDA. This term incorporates the thermal noise of the internal feedback resistors, and the interaction of the
internal current noise density of the output stage with the internal feedback resistors.
In
GOUT
eN(RTO)
eN(RTI)
GIN
+
+
eNO(GOUT = 1 or GOUT = 0.2)
+
eNI
图8-14. Simplified Noise Model for the INA851
The internal feedback resistor network is considered in the eNO specification; therefore, the calculation of the
total input-referred noise, eN(RTI), is simplified to the following equation:
2
e
NO G
= 1 or G
= 0.2
OUT
OUT
2
e
=
e
+
NI
(4)
N RTI
G
IN
The total output-referred noise, eN(RTO), multiplies directly by the output stage gain, GOUT, by GOUT = 0.2 V/V or
GOUT = 1 V/V respectively, as shown in the following equation:
2
2
e
=
e
× G × 0.2 V/V or 1 V/V + e
× 0.2 V/V or 1 V/V
= 0.2
OUT
(5)
N RTO
NI
IN
NO G
= 1 or G
OUT
8.4 Device Functional Modes
The INA851 has a single functional mode and operates when the power-supply voltage is greater than 8 V
(±4 V). The maximum power-supply voltage for the INA851 is 36 V (±18 V).
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
9.1.1 Output Common-Mode Pin
The output voltage of the INA851 is developed with respect to the voltage on the output common-mode pin,
VOCM. The starting point for most designs is to assign an output common-mode voltage for the INA851. For ac-
coupled signal paths, this voltage is often the default midsupply voltage, so as to retain the most available output
swing around the voltage centered at VOCM. For dc-coupled signal paths, set this voltage between a minimum of
VS+ – 2.5 V and maximum of VS– + 2.5 V. For precision ADC applications, this voltage is typically the input
common mode voltage of the ADC.
The voltage at the VOCM pin is internally buffered to bias the fully differential output amplifier, eliminating the
need for an additional external VOCM buffer. While the buffer input is high-ohmic, the VOCM pin also connects
through internal 500-kΩ resistors to VCLAMP+ and VCLAMP–, which sets the output common-mode voltage to
midsupply in the event that the pin is floating.
While the VOCM buffer has high small-signal bandwidth, be aware that large-signal steps with fast edges at the
VOCM pin cause delays in the output. For best tracking between the buffer input and output signals, use rise
times of 200 ns or greater for large steps.
9.1.2 Output-Stage Gain Selection and Noise-Gain Shaping
In the default unity-gain configuration, the INA851 fully differential amplifier output stage uses 5-kΩ feedback
resistors between the OUT+ and OUT– outputs and the inverting and noninverting inputs, respectively.
However, the INA851 also features internal 1.25-kΩ feedback resistors between those inputs and the G02+ and
G02– pins. By shorting the G02+ pin to the OUT+ pin, and the G02– pin to the OUT– pin, the amplifier is
placed in an attenuating gain of 0.2 V/V.
Additionally, access directly to the inverting and noninverting inputs of the fully differential amplifier is provided
through the FDA_IN– and FDA_IN+ pins, respectively. This option allows circuit designers to add external
feedback capacitors in parallel with the internal feedback resistors to implement noise filtering or noise-gain
shaping techniques. These pins can also be used to implement customized attenuating gains for the output
stage. Do not treat these pins as outputs, nor use the pins to source or sink current.
备注
These pins are internally disconnected on preliminary samples of the INA851; these pins will be
connected to the aforementioned internal nodes in the final device release.
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9.1.3 Input Bias Current Return Path
The input impedance of the INA851 is very high at approximately 1 GΩ. However, a path must be provided for
the input bias current of both inputs. This input bias current is typically 5 nA. High input impedance means that
this input bias current changes very little with varying input voltage.
For proper operation, input circuitry must provide a path for input bias current. 图 9-1 shows various provisions
for an input bias current path. Without a bias current path, the inputs float to a potential that exceeds the
common-mode range of the INA851, and the input amplifiers saturate. If the differential source resistance is low,
the thermocouple example in 图 9-1 shows that the bias current return path can connect to one input. With a
higher source impedance, using two equal resistors provides a balanced input with the possible advantages of a
lower input offset voltage as a result of bias current and better high-frequency common-mode rejection.
For more details about why a valid input bias current return path is necessary, see the Importance of Input Bias
Current Return Paths in Instrumentation Amplifier Applications application report.
Microphone,
Hydrophone,
and So Forth
TI Device
47 kW
47 kW
Thermocouple
TI Device
10 kW
TI Device
Center tap provides
bias current return.
Copyright © 2017, Texas Instruments Incorporated
图9-1. Providing an Input Common-Mode Current Path
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9.1.4 Thermal Effects due to Power Dissipation
The INA851 dissipates approximately 180 mW of power under quiescent conditions at a ±15-V supply voltage.
The internal resistor network and output load drive causes an additional power dissipation that depends on the
input signal. The small silicon area of the INA851 causes the internal circuitry to experience temperature
gradients that can adversely affect the electrical performance.
Precision parameters, such as offset voltage, linearity, common-mode rejection ratio, and total harmonic
distortion, can be impacted as a result of these thermal effects in the silicon. The thermal gradient particularly
affects the performance of low-frequency input signals with higher gains (> 10) and large output voltage
variation. 图9-2 shows that the thermal effect can be minimized by lowering the supply voltage, if the application
permits.
To properly dissipate heat from the INA851, connect the thermal pad with sufficient thermal vias to a large
copper plane that is connected to the negative supply, VS–. A thorough PCB layout is of key importance (see
also 节9.4).
500
450
400
350
300
250
200
150
100
50
0
-50
-100
VS = ꢀ 6
-150
-200
-250
-300
VS = ꢀ 12
VS = ꢀ 15
VS = ꢀ 18
-8
-6
-4
-2
0
2
4
6
8
Output Voltage (V)
图9-2. Linearity vs Supply Voltage for G = 1000
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9.2 Typical Applications
9.2.1 Three-Pin Programmable Logic Controller (PLC)
图9-3 shows a three-pin programmable-logic controller (PLC) design for the INA851. This PLC reference design
accepts inputs of ±10 V or ±20 mA. The output is a differential voltage of ±4.95 V with a VOCM of 2.5 V (or 25 mV
to 4.975 V on OUT+ and OUT−) to be measured by the ADS8920B SAR ADC.
5.3 V
REF5050
VOUT
GND
VIN
±10 V
1
F
5 k
5 k
0.1
10
F
R1
100 k
100 nF
15 V
VS+
1 k
10 μF
R2
4.17 k
VOCM
VCLAMP+
IN
100 pF
±20 mA
REFIN RVDD
AINP
47.4
FDA_IN
RG
OUT+
OUT
+
RG
530
= ± 4.95 V
100 pF
510 pF
ADS8920B
AINM
REFM
INA851
VO
R3
20
RG
FDA_IN+
47.4
51 pF
GND
IN+ VCLAMP
51 pF
VS
15 V
图9-3. PLC Input with INA851 (±10 V, 4 mA to 20 mA)
9.2.1.1 Design Requirements
For this application, the design requirements are as follows:
• 4-mA to 20-mA input with less than 20-Ωburden
• ±20-mA input with less than 20-Ωburden
• ±10-V input with impedance of approximately 100 kΩ
• Maximum 4-mA to 20-mA or ±20-mA burden voltage equal to ±0.4 V
• Output range within 0 V to 5 V
9.2.1.2 Detailed Design Procedure
There are two modes of operation for the circuit shown in 图 9-3: current input and voltage input. This design
requires R1 >> R2 >> R3. Given this relationship, the following equation calculates the current input mode
transfer function.
V
= V
× G = − I × R
3
(6)
OUT
DIFF
IN
where
• VOUT represents the differential voltage at the INA851 outputs in current input mode.
• VDIFF represents the differential voltage at the INA851 inputs.
• G represents the total gain of the INA851
• IIN is the input current to the PLC.
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The following equation shows the transfer function for the voltage input mode:
R
2
+ R
V
= V
× G = – V ×
IN
(7)
OUT
DIFF
R
2
1
where
• VOUT represents the differential voltage at the INA851 outputs in voltage input mode.
• VIN is the input voltage to the PLC.
The voltages on the output pins of the INA851 follow the relationships in 方程式8 and 方程式9.
G
2
V
V
= V
×
+ V
OCM
(8)
(9)
OUT +
DIFF
G
= −V
×
+ V
OCM
2
OUT −
DIFF
R1 sets the input impedance of the voltage input mode. The minimum typical input impedance is 100 kΩ. The R1
value is 100 kΩbecause increasing the R1 value also increases noise. The value of R3 must be extremely small
compared to R1 and R2. A 20‑Ω value is selected for R3 because that resistance value is much smaller than R1
and yields an input voltage of ±400 mV when operated in current mode (±20 mA).
Use 方程式10 to calculate R2 given VDIFF = ±400 mV, VIN = ±10 V, and R1 = 100 kΩ.
R
R × V
1 DIFF
2
V
= V
×
R =
= 4.167 kΩ
(10)
DIFF
IN
2
R
+ R
V
− V
1
2
IN DIFF
The value obtained from 方程式 10 is not a standard 0.1% value; therefore, 4.17 kΩ is selected. R1 and R2 also
use 0.1% tolerance resistors to minimize error.
Use 方程式11 to calculate the gain of the instrumentation amplifier.
V
OUT
DIFF
4.95 V
400 mV
G =
=
= 12.375 V/V
(11)
V
方程式12 calculates the gain-setting resistor value using the INA851 gain equation for GOUT = 1 V/V (方程式1).
6 kΩ
G−1
6 kΩ
12.375 − 1
R
=
=
= 527.473 Ω
(12)
G
Use a standard 0.1% resistor value of 530 Ωfor this design.
The ADS8920B is selected because of the differential input, 1-MSPS sampling rate, and integrated reference
buffer. Implement the antialiasing R-C-R filter using two 47.4-Ω resistors, a COG or NPO-type 510-pF
differential capacitor, and two ceramic 51-pF common-mode capacitors. The REF5050 is selected to create a 5-
V reference voltage for the ADC. Use well-matched precision resistors to create a voltage divider that generates
a stable 2.5-V VOCM reference. Connect the VCLAMP+ and VCLAMP− pins of the INA851 to the supplies of the
ADC to protect against overdrive damage in the event of a fault. Consider implementing a TVS diode from the
ADC supply to GND for additional protection, and include 100-nF decoupling capacitors between the amplifier
and ADC supplies and GND.
9.2.1.3 应用曲线
图9-4 和图9-5 展示了图9-3 中电路的典型特性曲线。
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C001
5
5
4
3
2
1
0
4
3
2
1
0
-10
-5
0
5
10
-20
-10
0
10
20
Input Voltage (V)
Input Current (mA)
C001
图9-4. PLC 输出电压与输入电压之间的关系
图9-5. PLC 输出电压与输入电流间的关系
9.2.2 20-Bit, 1-MSPS ADS8900B Driver Circuit With FDA Noise Filter
The application circuit in 图 9-6 shows the schematic of a complete input and reference driver circuit for the
ADS8900B, a 20-bit, precision, 1-MSPS, successive approximation register (SAR), analog-to-digital converter
(ADC). This circuit is used to measure the driving capability of the INA851 with the ADS8900B ADC.
To test the complete dynamic range of the circuit, the common-mode voltage VOCM of the input of the ADC is
established at a value of VREF / 2.
To exclude noise caused by supply voltage, the test circuit uses the TPS7A4700, a low-noise 4-µVRMS, RF
LDO voltage regulator, to generate the 5.2-V supply rail.
For VOCM, the circuit uses the REF5050, a low-noise, low-drift, 5-V reference, a 20k-20k voltage divider to
establish VREF/2 and an additional RC filter (10 Ω, 150 pF) into the VOCM pin. See also the ADS8900EVM-
PDK user's guide.
15 V
14
5.2 V
VS+
LDO
INA851
16
15
5.0 V
VCLAMP+
FDA_IN
1
2
IN
VIN-
+
–
OVP
R3
G02+ 12
CFB
1 nF
RG
1.25 k
R4
CFIL
RF
3 k
R1
RFIL
VDD VREF
ADS8900B
VSS
1 nF
5 k
5 k
INP
INN
OUT+ 11
OUT 10
–
+
+
–
47.4
RG
RF
5 k
R2
R5
3 k
RFIL
47.4
CFIL
1 nF
5 k
R6
3
4
RG+
IN+
–
+
CFB
G02
FDA_IN+
VCLAMP
9
6
5
1 nF
VIN+
1.25 k
OVP
LDO
VS
VOCM
13
7
15 V
10
VREF/2
150 pF
图9-6. Driving ADS8900B With FDA Noise Filter
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9.2.2.1 Design Requirements
The requirements for the application driving the ADS8900B ADC are listed in the following table.
表9-1. Design Parameters
PARAMETER
Differential to differential conversion
Supply voltages
VALUE
VINDIFF to VOUTDIFF
VS± = ± 15 V, VDD = 5.2 V, VREF = 5 V
FSR = ± 5 V
Full-scale range of ADC for FSR
Driver configuration
See 表9-2
Circuit bandwidth
f(–3dB) = 31.7 kHz
Output RC elements
See ADS8900B input requirements
To eliminate ground loops, unwanted parasitic effects, and distortion, use appropriate PCB layout and grounding
techniques (see also 节9.4).
9.2.2.2 Application Curves
表 9-2 show the typical signal-to-noise (SNR) and total harmonic distortion (THD) of the INA851 driving the
ADS8900B SAR ADC at full-scale range and at different gain configurations. The RC filter combination (RFIL
,
C
FIL) shown in 图 9-6 helps attenuate the nonlinear charge kickback of the ADC and optimize for best THD
performance. The combination of the RC filter and the feedback capacitor CFB allow for the best trade-off
between harmonic distortion and maintaining stability of the FDA. Low voltage-coefficient C0G capacitors are
used everywhere in the signal path (CFB, CFIL) for the low-distortion properties.
For other bandwidth requirements, adjust the feedback capacitor accordingly, and verify the circuit performance
using a SPICE simulation using the INA851 TINA-TI™ SPICE Model. The amplifier output voltage must settle
within the ADC bit accuracy during the ADC acquisition time window. Verify the desired circuit is stable; that is,
the FDA has more than a 45º phase margin.
表9-2. INA851 + ADS8900B FFT Data Summary
INPUT AMPLITUDE
GIN (V/V)
GOUT (V/V)
SNR (dB)
THD (dB)
ENOB (Bits)
RG RESISTOR (Ω)
(Vpk)
23.7378
4.7476
0.2374
0.0475
None
None
316
1
1
0.2
1
100.7
100.6
99.1
16.42
16.41
16.10
14.64
–117.3
–122.7
–112.0
–99.0
20
100
1
60.4
1
91.1
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G = 0.2 V/V, fIN = 1 kHz, SNR = 100.73 dB, THD = –117.28
G = 1 V/V, fIN = 1 kHz, SNR = 100.6 dB, THD = –122.74 dB
dB
图9-8. Noise Performance FFT Plots for G = 1 V/V
图9-7. Noise Performance FFT Plots for
G = 0.2 V/V
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9.2.3 24-Bit, 200 kSPS, Delta-Sigma ADS127L11 ADC Driver Circuit With FDA Noise Filter
The application circuit in 图 9-9 shows an schematic for a 24-bit-precision, 200-kSPS, delta-sigma, ADC. The
circuit is used to measure the driving capacity of the INA851 with the ADS127L11 ADC.
The ADS127L11 ADC offers two digital filters to optimize for ac applications (wideband filter) or dc applications
(Sinc4 filter). Application Curves shows measurement results in both filter settings. For detailed design
procedure to operate the ADS127L11 ADC, see the ADS127L11EVM-PDK evaluation module.
15 V
14
5.2 V
VS+
LDO
INA851
16
15
2.5 V
VCLAMP+
FDA_IN
1
2
IN
VIN-
+
–
OVP
R3
G02+ 12
CFB
100 pF
RG
1.25 k
R4
CCM
51 pF
RFIL
47.4
RF
3 k
R1
AVDD VREF
5 k
5 k
INP
INN
OUT+ 11
OUT 10
–
+
+
–
CDIFF
510 pF
ADS127L11
2x Input Range
RG
RF
5 k
R2
R5
3 k
RFIL
47.4
AVSS
CCM
51 pF
5 k
R6
3
4
RG+
IN+
–
+
CFB
100 pF
G02
FDA_IN+
VCLAMP
9
6
5
VIN+
1.25 k
OVP
LDO
VS
VOCM
13
7
15 V
10
ADS127L11 V
VCM Pin
150 pF
图9-9. Driving the Delta-Sigma ADC ADS127L11
9.2.3.1 Design Requirements
The design requirements for the application driving the ADS127L11 ADC are listed in the following table.
表9-3. Design Parameters
PARAMETER
Differential-to-differential conversion
Supply voltages
VALUE
VINDIFF to VOUTDIFF
VS± = ±15 V, AVDD = 5.2 V, VREF = 2.5 V
FSR = ± 5 V
Full-scale range of ADC for FSR
Data rate of ADC
fDATA = 187.5 kSPS
(1) High-speed mode, Sinc4 filter, OSR = 64
(2) High-speed mode, wideband filter, OSR = 64
See 表9-4 and 表9-5
ADC filter configuration
INA gain and filter configuration
Signal frequency
fIN = 1 kHz
RC kickback filter(1)
RFIL = 47.4 Ω+ CDIFF = 510 pF + RFIL = 47.4 Ω, CFIL = 51 pF
(1) A trade-off must be considered between THD, frequency response and drift. The differential current drift into the ADC can interact with
this filter resistors and result in higher drift errors. However, low resistance degrades the phase margin of the INA851. For low drift
applications, keep RFIL < 50 Ω.
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For optimized linearity and THD performance, use good printed circuit board (PCB) layout practice. For proper
heat dissipation of the INA851, connect the thermal pad to a plane or a large copper pour at the bottom
connected to VS–(see also 节9.4.2).
9.2.3.2 Application Curves
表 9-4 and 表 9-5 show the typical signal-to-noise (SNR) and total harmonic distortion (THD) of the INA851
driving the ADS127L11 delta-sigma ADC at full-scale range and at different gain configurations.
The RC filter combination is dimensioned such to help attenuate the nonlinear charge kickback and optimize for
best THD performance. The ADC requires a low impedance input for lowest distortion performance; however,
driving heavier loads degrades the phase margin of the INA851. Use a feedback capacitor (CFB) in the range of
47 pF to 100 pF to optimize for stability versus THD performance. Low voltage-coefficient C0G capacitors are
used everywhere in the signal path (CFB, CDIFF, CCM) for their low distortion properties.
For other bandwidth requirements, adjust the feedback capacitor accordingly and verify the circuit performance
using a SPICE simulation using INA851 TINA-TI™ SPICE Model. Confirm that the desired circuit is stable; that
is, the FDA has more than a 45º phase margin.
表9-4. INA851 + ADS127L11 (Sinc4 Filter) FFT Data Summary
INPUT
AMPLITUDE
(Vpk)
RG RESISTOR
GIN (V/V)
GOUT (V/V)
SNR (dB)
THD (dB)
ENOB (Bits)
(Ω)
23.7378
4.7476
None
None
1500
316
1
1
0.2
1
106.8
105.9
107.2
102.5
92.5
17.36
17.28
17.25
16.59
14.81
–116.0
–122.0
–113.8
–112.0
–99.0
2.3738(1)
0.2374
5
0.2
1
20
100
0.0475
60.4
1
G = 0.2 V/V, fIN = 1 kHz, SNR = 106.75 dB, THD = –115.95
G = 0.2 V/V, fIN = 1 kHz, SNR = 105.88 dB, THD = –122.00
dB
dB
图9-10. Noise Performance FFT Plots with Sinc4
图9-11. Noise Performance FFT Plots with Sinc4
Filter for G = 0.2 V/V
Filter for G = 1 V/V
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ENOB (Bits)
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表9-5. INA851 + ADS127L11 (Wideband Filter) FFT Data Summary
INPUT
AMPLITUDE
(Vpk)
RG RESISTOR
GIN (V/V)
GOUT (V/V)
SNR (dB)
THD (dB)
(Ω)
23.76015
4.7476
2.3738
0.2360
0.0472
None
None
1500
316
1
1
0.2
1
105.3
103.1
104.2
99.0
17.14
16.81
16.85
16.08
14.40
–116.2
–120.0
–113.0
–112.0
–99.0
5
0.2
1
20
100
60.4
1
89.3
G = 0.2 V/V, fIN = 1 kHz, SNR = 105.29 dB, THD = –116.21
G = 1 V/V, fIN = 1 kHz, SNR = 103.07 dB, THD = –120.01 dB
dB
图9-13. Noise Performance FFT Plots with
图9-12. Noise Performance FFT Plots with
Wideband Filter for G = 1 V/V
Wideband Filter for G = 0.2 V/V
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9.3 Power Supply Recommendations
The nominal performance of the INA851 is specified with a supply voltage of ±15 V, and VICM and VOCM at
midsupply. The device also operates using power supplies from ±4 V (8 V) to ±18 V (36 V) and non-midsupply
input and output common-mode voltages with excellent performance.
9.4 Layout
9.4.1 Layout Guidelines
Attention to good layout practices is always recommended. For best operational performance of the device, use
good printed circuit board (PCB) layout practices:
• To avoid converting common-mode signals into differential signals and thermal electromotive forces (EMFs),
make sure that both input paths are symmetrical and well-matched for source impedance and capacitance.
• As shown in 图9-14, keep the external gain resistor close to the RG pins to keep the loop inductance as low
as possible and to avoid a potential parasitic coupling path. Even slight mismatch in parasitic capacitance at
the gain setting pins can degrade CMRR over frequency. In applications that implement gain switching using
switches or PhotoMOS® relays to change the value of RG, select the component so that the switch
capacitance is as small as possible, and most importantly, so that capacitance mismatch between the RG
pins is minimized.
• Noise can propagate into analog circuitry through the power pins of the device and of the circuit as a whole.
Bypass capacitors reduce the coupled noise by providing low-impedance power sources local to the analog
circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close as possible to the device. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
• To reduce parasitic coupling, run the input traces as far away as possible from the supply or output traces. If
these traces cannot be kept separate, crossing the sensitive trace perpendicular to the noisy trace is much
better than in parallel.
• Leakage on the FDA_IN+ and FDA_IN–pins can cause in a dc offset error in the output voltages.
Additionally, excessive parasitic capacitance at these pins can result in decreased phase margin and affect
the stability of the output stage. If these pins are not used to implement deliberate capacitive feedback, follow
best practices to minimize leakage and parasitic capacitance. Consider implementing keep-out areas in any
ground planes that lie immediately below the pins.
• Minimize the number of thermal junctions. Ideally, the signal path is routed within a single layer without vias.
• Keep sufficient distance from major thermal energy sources (circuits with high power dissipation). If not
possible, place the device so that the effects of the thermal energy source on the high and low sides of the
differential signal path are evenly matched.
• Solder the thermal pad to the PCB. For the INA851 to properly dissipate heat, connect the thermal pad to a
plane or large copper pour that is electrically connected to VS–, even for low-power applications.
• Keep the traces as short as possible.
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9.4.2 Layout Example
Connect feedback
capacitors between
OUTx and FDA_INx
(optional)
VS+
C1
R1
C3
C5
R3
VIN–
INP
INN
RG
OUT+
OUT–
INA851
RG
C7
ADC
RG
R4
VIN+
C6
C4
VOCM
R2
C2
VS–
Place bypass
capacitors as close to
IC as possible
Use ground pours for
shielding the input
signal pairs
VS+
GND
Short OUTx to
G02x for output
stage G = 0.2
C1
VOCM
VCLAMP+
GND
GND
R1
VIN–
12
11
10
9
1
2
3
4
IN–
RG
RG
C5
G02+
OUT+
OUT–
G02–
R3
C3
INP
INN
PAD
C7
RG
Cutouts on ground planes
underneath input pins
(1, 4, 6, 15) can reduce
stray capacitance, for
better phase margin
C4
C6
R4
IN+
VIN+
GND
R2
Consider utilizing
thermal vias for
heatsinking
GND
VCLAMP–
C2
VS–
GND
图9-14. Example Schematic and Associated PCB Layout
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10 Device and Documentation Support
10.1 Device Support
10.1.1 Development Support
10.1.1.1 PSpice® for TI
PSpice® for TI 是可帮助评估模拟电路性能的设计和仿真环境。在进行布局和制造之前创建子系统设计和原型解决
方案，可降低开发成本并缩短上市时间。
10.1.1.2 TINA-TI™ Simulation Software (Free Download)
TINA-TI™ simulation software is a simple, powerful, and easy-to-use circuit simulation program based on a
SPICE engine. TINA-TI simulation software is a free, fully-functional version of the TINA™ software, preloaded
with a library of macromodels, in addition to a range of both passive and active models. TINA-TI simulation
software provides all the conventional dc, transient, and frequency domain analysis of SPICE, as well as
additional design capabilities.
Available as a free download from the Design tools and simulation web page, TINA-TI simulation software offers
extensive post-processing capability that allows users to format results in a variety of ways. Virtual instruments
offer the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic
quick-start tool.
备注
These files require that either the TINA software or TINA-TI software be installed. Download the free
TINA-TI simulation software from the TINA-TI™ software folder.
10.2 Documentation Support
10.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Comprehensive Error Calculation for Instrumentation Amplifiers application note
• Texas Instruments, Importance of Input Bias Current Return Paths in Instrumentation Amplifier Applications
application note
10.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.5 Trademarks
TINA-TI™ and TI E2E™ are trademarks of Texas Instruments.
TINA™ is a trademark of DesignSoft, Inc.
PhotoMOS® is a registered trademark of Panasonic Electric Works Europe AG.
PSpice® is a registered trademark of Cadence Design Systems, Inc.
所有商标均为其各自所有者的财产。
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10.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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11-Nov-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
INA851RGTR
INA851RGTT
XINA851RGTR
ACTIVE
ACTIVE
ACTIVE
VQFN
VQFN
VQFN
RGT
RGT
RGT
16
16
16
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Call TI
-40 to 125
-40 to 125
-40 to 85
INA851
INA851
Samples
Samples
Samples
250
RoHS & Green
TBD
NIPDAU
Call TI
3000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Nov-2022
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Nov-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
INA851RGTR
INA851RGTT
VQFN
VQFN
RGT
RGT
16
16
3000
250
330.0
180.0
12.4
12.4
3.3
3.3
3.3
3.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Nov-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
INA851RGTR
INA851RGTT
VQFN
VQFN
RGT
RGT
16
16
3000
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
RGT0016C
VQFN - 1 mm max height
S
C
A
L
E
3
.
6
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
SIDE WALL
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
1.0
0.8
C
SEATING PLANE
0.08
0.05
0.00
1.68 0.07
(DIM A) TYP
5
8
EXPOSED
THERMAL PAD
12X 0.5
4
9
4X
SYMM
1.5
1
12
0.30
16X
0.18
13
16
0.1
C A B
PIN 1 ID
(OPTIONAL)
SYMM
0.05
0.5
0.3
16X
4222419/D 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGT0016C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.68)
SYMM
13
16
16X (0.6)
1
12
16X (0.24)
SYMM
(2.8)
(0.58)
TYP
12X (0.5)
9
4
(
0.2) TYP
VIA
5
(0.58) TYP
8
(R0.05)
ALL PAD CORNERS
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222419/D 04/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGT0016C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.55)
16
13
16X (0.6)
1
12
16X (0.24)
17
SYMM
(2.8)
12X (0.5)
9
4
METAL
ALL AROUND
5
8
SYMM
(2.8)
(R0.05) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4222419/D 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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Copyright © 2022，德州仪器 (TI) 公司
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